SDFileSystemDMA - first 2016/02 SDFileSystemDMA inherited from Offi…

Users » mimi3 » Code » SDFileSystemDMA

first 2016/02 SDFileSystemDMA inherited from Official SDFileSystem.

Dependents: SDFileSystemDMA-test DmdFullRGB_0_1

SDFileSystemDMA is enhanced SDFileSystem library for STM32 micros by using DMA functionality.
Max read transfer rate reaches over 2MByte/sec at 24MHz SPI clock if enough read buffer size is set.
Even though minimum read buffer size (512Byte) is set, read transfer rate will reach over 1MByte/sec at 24MHz SPI Clock.
( but depends on the ability of each SD card)

Test program is here.
https://developer.mbed.org/users/mimi3/code/SDFileSystemDMA-test/

/media/uploads/mimi3/sdfilesystemdma-speed-test3-read-buffer-512byte.png

Supported SPI port is shown below table.

(v): Verified. It works well.
(w): Probably it will work well. (not tested)
(c): Only compiled. (not tested)
(f): Over flash.
(r): Only read mode. (when _FS_READONLY==1)
(u) Under construction
(z): Dose not work.

Caution

If your board has SRAM less than or equal to 8KB, the buffer size must be set to 512 Bytes.

Supported Boards:
Cortex-M0

Board	SRAM	SPI1	SPI2	SPI3
NUCLEO-F030R8	8KB	(v)
DISCO-F051R8	8KB	(w)
~~NUCLEO-F031K6~~	4KB	(f)
NUCLEO-F042K6	6KB	(r)
NUCLEO-F070RB	16KB	(w)
NUCLEO-F072RB	16KB	(w)
NUCLEO-F091RC	32KB	(c)

Cortex-L0

Board	SRAM	SPI1	SPI2	SPI3
DISCO-L053C8	8KB	(c)
NUCLEO-L053R8	8KB	(c)
NUCLEO-L073RZ	20KB	(c)

Cortex-M3

Board	SRAM	SPI1	SPI2	SPI3
DISCO-F100RB	8KB	(v)	(v)	-
BLUEPILL-F103CB	20KB	(w)	(w)	-
NUCLEO-F103RB	20KB	(v)	(v)	-
NUCLEO-L152RE	80KB	(v)	(w)	-
MOTE-L152RC	32KB	(w)	(w)	-

Cortex-M4
F3

Board	SRAM	SPI1	SPI2	SPI3
DISCO-F303VC	40KB	-	(v)	(v)
NUCLEO-F303RE	64KB	(w)	(w)	(w)
NUCLEO-F302R8	16KB	-	-	(c)
NUCLEO-F303K8	12KB	(c)	-	-
DISCO-F334C8	12KB	(c)	-	-
NUCLEO-F334R8	12KB	(c)	-	-

Board	SPI1	SPI2	SPI3
ELMO-F411RE	(w)	-	(w)
MTS-MDOT-F411RE	(u)	-	(u)
MTS-DRAGONFLY-F411RE	(w)	-	(w)
NUCLEO-F411RE	(v)	-	(v)
NUCLEO-F401RE	(w)	-	(w)
MTS-MDOT-F405RG	(u)	-	(u)
NUCLEO-F410RB	(c)	-	(c)
NUCLEO-F446RE	(c)	-	(c)
NUCLEO-F429ZI	(c)	-	(c)
B96B-F446VE	(c)	-	(c)
NUCLEO-F446ZE	(c)	-	(c)
DISCO-F429ZI	(u)	-	(u)
DISCO-F469NI	(c)	-	(c)

Information

This library is set to use "short file name" in SDFileSystemDMA/FATFileSystem/ChaN/ffconf.h . ( _USE_LFN=0)
You can change this option to _USE_LFN=1 .

spi_dma/spi_dma_stm32f3.c@24:92bf692d61e2, 2016-02-17 (annotated)

Committer:: mimi3
Date:: Wed Feb 17 23:23:16 2016 +0900
Revision:: 24:92bf692d61e2
Child:: 33:73237494298b

Enable: F3: SPI1, SPI2,SPI3

Who changed what in which revision?

User	Revision	Line number	New contents of line
mimi3	24:92bf692d61e2	1	#if defined(TARGET_NUCLEO_F302R8) \
mimi3	24:92bf692d61e2	2	\|\| defined(TARGET_NUCLEO_F303RE) \
mimi3	24:92bf692d61e2	3	\|\| defined( TARGET_DISCO_F303VC)
mimi3	24:92bf692d61e2	4
mimi3	24:92bf692d61e2	5	/*
mimi3	24:92bf692d61e2	6
mimi3	24:92bf692d61e2	7	This file is licensed under Apache 2.0 license.
mimi3	24:92bf692d61e2	8	(C) 2016 dinau
mimi3	24:92bf692d61e2	9
mimi3	24:92bf692d61e2	10	*/
mimi3	24:92bf692d61e2	11	#include "spi_dma.h"
mimi3	24:92bf692d61e2	12
mimi3	24:92bf692d61e2	13	/* For SPI1 */
mimi3	24:92bf692d61e2	14	#define SPI1_DMAx_CLK_ENABLE() __DMA1_CLK_ENABLE()
mimi3	24:92bf692d61e2	15	#define SPI1_DMAx_TX_CHANNEL DMA1_Channel3
mimi3	24:92bf692d61e2	16	#define SPI1_DMAx_RX_CHANNEL DMA1_Channel2
mimi3	24:92bf692d61e2	17	#define SPI1_DMAx_TX_IRQn DMA1_Channel3_IRQn
mimi3	24:92bf692d61e2	18	#define SPI1_DMAx_RX_IRQn DMA1_Channel2_IRQn
mimi3	24:92bf692d61e2	19	#define SPI1_DMAx_TX_IRQHandler DMA1_Channel3_IRQHandler
mimi3	24:92bf692d61e2	20	#define SPI1_DMAx_RX_IRQHandler DMA1_Channel2_IRQHandler
mimi3	24:92bf692d61e2	21	/* For SPI2 */
mimi3	24:92bf692d61e2	22	#define SPI2_DMAx_CLK_ENABLE() __DMA1_CLK_ENABLE()
mimi3	24:92bf692d61e2	23	#define SPI2_DMAx_TX_CHANNEL DMA1_Channel5
mimi3	24:92bf692d61e2	24	#define SPI2_DMAx_RX_CHANNEL DMA1_Channel4
mimi3	24:92bf692d61e2	25	#define SPI2_DMAx_TX_IRQn DMA1_Channel5_IRQn
mimi3	24:92bf692d61e2	26	#define SPI2_DMAx_RX_IRQn DMA1_Channel4_IRQn
mimi3	24:92bf692d61e2	27	#define SPI2_DMAx_TX_IRQHandler DMA1_Channel5_IRQHandler
mimi3	24:92bf692d61e2	28	#define SPI2_DMAx_RX_IRQHandler DMA1_Channel4_IRQHandler
mimi3	24:92bf692d61e2	29	/* For SPI3 */
mimi3	24:92bf692d61e2	30	#define SPI3_DMAx_CLK_ENABLE() __DMA2_CLK_ENABLE()
mimi3	24:92bf692d61e2	31	#define SPI3_DMAx_TX_CHANNEL DMA2_Channel2
mimi3	24:92bf692d61e2	32	#define SPI3_DMAx_RX_CHANNEL DMA2_Channel1
mimi3	24:92bf692d61e2	33	#define SPI3_DMAx_TX_IRQn DMA2_Channel2_IRQn
mimi3	24:92bf692d61e2	34	#define SPI3_DMAx_RX_IRQn DMA2_Channel1_IRQn
mimi3	24:92bf692d61e2	35	#define SPI3_DMAx_TX_IRQHandler DMA2_Channel2_IRQHandler
mimi3	24:92bf692d61e2	36	#define SPI3_DMAx_RX_IRQHandler DMA2_Channel1_IRQHandler
mimi3	24:92bf692d61e2	37
mimi3	24:92bf692d61e2	38	#define readReg( reg, mask) ( (reg) & (mask) )
mimi3	24:92bf692d61e2	39
mimi3	24:92bf692d61e2	40
mimi3	24:92bf692d61e2	41	void spi_dma_get_info( SPI_TypeDef *spi )
mimi3	24:92bf692d61e2	42	{
mimi3	24:92bf692d61e2	43	SpiHandle.Instance = spi;
mimi3	24:92bf692d61e2	44	SpiHandle.Init.Mode = readReg(spi->CR1, SPI_MODE_MASTER);
mimi3	24:92bf692d61e2	45	SpiHandle.Init.BaudRatePrescaler = readReg(spi->CR1, SPI_CR1_BR);
mimi3	24:92bf692d61e2	46	SpiHandle.Init.Direction = readReg(spi->CR1, SPI_CR1_BIDIMODE);
mimi3	24:92bf692d61e2	47	SpiHandle.Init.CLKPhase = readReg(spi->CR1, SPI_CR1_CPHA);
mimi3	24:92bf692d61e2	48	SpiHandle.Init.CLKPolarity = readReg(spi->CR1, SPI_CR1_CPOL);
mimi3	24:92bf692d61e2	49	SpiHandle.Init.CRCCalculation = readReg(spi->CR1, SPI_CR1_CRCEN);
mimi3	24:92bf692d61e2	50	SpiHandle.Init.CRCPolynomial = spi->CRCPR & 0xFFFF;
mimi3	24:92bf692d61e2	51	SpiHandle.Init.DataSize = readReg(spi->CR1, SPI_CR2_DS);
mimi3	24:92bf692d61e2	52	SpiHandle.Init.FirstBit = SPI_FIRSTBIT_MSB;
mimi3	24:92bf692d61e2	53	SpiHandle.Init.NSS = readReg(spi->CR1, SPI_CR1_SSM);
mimi3	24:92bf692d61e2	54	SpiHandle.Init.TIMode = SPI_TIMODE_DISABLED;
mimi3	24:92bf692d61e2	55	SpiHandle.State = HAL_SPI_STATE_READY;
mimi3	24:92bf692d61e2	56	}
mimi3	24:92bf692d61e2	57
mimi3	24:92bf692d61e2	58	void spi_dma_handle_setup( SPI_TypeDef *spi, uint8_t mode )
mimi3	24:92bf692d61e2	59	{
mimi3	24:92bf692d61e2	60	static uint8_t dma_handle_inited = 0;
mimi3	24:92bf692d61e2	61	/* Peripheral DMA init*/
mimi3	24:92bf692d61e2	62	/* TX: */
mimi3	24:92bf692d61e2	63	if( !dma_handle_inited ){
mimi3	24:92bf692d61e2	64	if( spi == SPI1 ){
mimi3	24:92bf692d61e2	65	hdma_spi_tx.Instance = SPI1_DMAx_TX_CHANNEL;
mimi3	24:92bf692d61e2	66	} else if( spi == SPI2 ){
mimi3	24:92bf692d61e2	67	hdma_spi_tx.Instance = SPI2_DMAx_TX_CHANNEL;
mimi3	24:92bf692d61e2	68	} else if( spi == SPI3 ){
mimi3	24:92bf692d61e2	69	hdma_spi_tx.Instance = SPI3_DMAx_TX_CHANNEL;
mimi3	24:92bf692d61e2	70	}
mimi3	24:92bf692d61e2	71	hdma_spi_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
mimi3	24:92bf692d61e2	72	hdma_spi_tx.Init.PeriphInc = DMA_PINC_DISABLE;
mimi3	24:92bf692d61e2	73	hdma_spi_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
mimi3	24:92bf692d61e2	74	hdma_spi_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
mimi3	24:92bf692d61e2	75	hdma_spi_tx.Init.Mode = DMA_NORMAL;
mimi3	24:92bf692d61e2	76	hdma_spi_tx.Init.Priority = DMA_PRIORITY_LOW;
mimi3	24:92bf692d61e2	77	}
mimi3	24:92bf692d61e2	78	hdma_spi_tx.Init.MemInc = ( mode == DMA_SPI_READ) ? DMA_MINC_DISABLE : DMA_MINC_ENABLE;
mimi3	24:92bf692d61e2	79	HAL_DMA_Init(&hdma_spi_tx);
mimi3	24:92bf692d61e2	80	__HAL_LINKDMA( &SpiHandle,hdmatx,hdma_spi_tx);
mimi3	24:92bf692d61e2	81	/* RX: */
mimi3	24:92bf692d61e2	82	if( !dma_handle_inited ){
mimi3	24:92bf692d61e2	83	if( spi == SPI1 ){
mimi3	24:92bf692d61e2	84	hdma_spi_rx.Instance = SPI1_DMAx_RX_CHANNEL;
mimi3	24:92bf692d61e2	85	} else if( spi == SPI2 ){
mimi3	24:92bf692d61e2	86	hdma_spi_rx.Instance = SPI2_DMAx_RX_CHANNEL;
mimi3	24:92bf692d61e2	87	} else if( spi == SPI3 ){
mimi3	24:92bf692d61e2	88	hdma_spi_rx.Instance = SPI3_DMAx_RX_CHANNEL;
mimi3	24:92bf692d61e2	89	}
mimi3	24:92bf692d61e2	90	hdma_spi_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
mimi3	24:92bf692d61e2	91	hdma_spi_rx.Init.PeriphInc = DMA_PINC_DISABLE;
mimi3	24:92bf692d61e2	92	hdma_spi_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
mimi3	24:92bf692d61e2	93	hdma_spi_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
mimi3	24:92bf692d61e2	94	hdma_spi_rx.Init.Mode = DMA_NORMAL;
mimi3	24:92bf692d61e2	95	hdma_spi_rx.Init.Priority = DMA_PRIORITY_HIGH;
mimi3	24:92bf692d61e2	96	}
mimi3	24:92bf692d61e2	97	hdma_spi_rx.Init.MemInc = (mode == DMA_SPI_READ) ? DMA_MINC_ENABLE : DMA_MINC_DISABLE;
mimi3	24:92bf692d61e2	98	HAL_DMA_Init(&hdma_spi_rx);
mimi3	24:92bf692d61e2	99	__HAL_LINKDMA( &SpiHandle,hdmarx,hdma_spi_rx);
mimi3	24:92bf692d61e2	100	}
mimi3	24:92bf692d61e2	101
mimi3	24:92bf692d61e2	102	void spi_dma_irq_setup( SPI_TypeDef *spi)
mimi3	24:92bf692d61e2	103	{
mimi3	24:92bf692d61e2	104	/* DMA controller clock enable */
mimi3	24:92bf692d61e2	105	if( spi == SPI1 ){
mimi3	24:92bf692d61e2	106	SPI1_DMAx_CLK_ENABLE();
mimi3	24:92bf692d61e2	107	HAL_NVIC_SetPriority(SPI1_DMAx_TX_IRQn, 3, 0);
mimi3	24:92bf692d61e2	108	HAL_NVIC_EnableIRQ( SPI1_DMAx_TX_IRQn);
mimi3	24:92bf692d61e2	109	HAL_NVIC_SetPriority(SPI1_DMAx_RX_IRQn, 2, 0);
mimi3	24:92bf692d61e2	110	HAL_NVIC_EnableIRQ( SPI1_DMAx_RX_IRQn);
mimi3	24:92bf692d61e2	111	} else if( spi == SPI2 ){
mimi3	24:92bf692d61e2	112	SPI2_DMAx_CLK_ENABLE();
mimi3	24:92bf692d61e2	113	HAL_NVIC_SetPriority(SPI2_DMAx_TX_IRQn, 3, 0);
mimi3	24:92bf692d61e2	114	HAL_NVIC_EnableIRQ( SPI2_DMAx_TX_IRQn);
mimi3	24:92bf692d61e2	115	HAL_NVIC_SetPriority(SPI2_DMAx_RX_IRQn, 2, 0);
mimi3	24:92bf692d61e2	116	HAL_NVIC_EnableIRQ( SPI2_DMAx_RX_IRQn);
mimi3	24:92bf692d61e2	117	} else if( spi == SPI3 ){
mimi3	24:92bf692d61e2	118	SPI3_DMAx_CLK_ENABLE();
mimi3	24:92bf692d61e2	119	HAL_NVIC_SetPriority(SPI3_DMAx_TX_IRQn, 3, 0);
mimi3	24:92bf692d61e2	120	HAL_NVIC_EnableIRQ( SPI3_DMAx_TX_IRQn);
mimi3	24:92bf692d61e2	121	HAL_NVIC_SetPriority(SPI3_DMAx_RX_IRQn, 2, 0);
mimi3	24:92bf692d61e2	122	HAL_NVIC_EnableIRQ( SPI3_DMAx_RX_IRQn);
mimi3	24:92bf692d61e2	123	}
mimi3	24:92bf692d61e2	124	/* DMA interrupt init */
mimi3	24:92bf692d61e2	125	}
mimi3	24:92bf692d61e2	126
mimi3	24:92bf692d61e2	127	/* SPI1 */
mimi3	24:92bf692d61e2	128	void SPI1_DMAx_TX_IRQHandler(void)
mimi3	24:92bf692d61e2	129	{
mimi3	24:92bf692d61e2	130	HAL_DMA_IRQHandler(&hdma_spi_tx);
mimi3	24:92bf692d61e2	131	}
mimi3	24:92bf692d61e2	132	void SPI1_DMAx_RX_IRQHandler(void)
mimi3	24:92bf692d61e2	133	{
mimi3	24:92bf692d61e2	134	HAL_DMA_IRQHandler(&hdma_spi_rx);
mimi3	24:92bf692d61e2	135	}
mimi3	24:92bf692d61e2	136
mimi3	24:92bf692d61e2	137	#if defined(SPI2_BASE)
mimi3	24:92bf692d61e2	138	/* SPI2 */
mimi3	24:92bf692d61e2	139	void SPI2_DMAx_TX_IRQHandler(void)
mimi3	24:92bf692d61e2	140	{
mimi3	24:92bf692d61e2	141	HAL_DMA_IRQHandler(&hdma_spi_tx);
mimi3	24:92bf692d61e2	142	}
mimi3	24:92bf692d61e2	143	void SPI2_DMAx_RX_IRQHandler(void)
mimi3	24:92bf692d61e2	144	{
mimi3	24:92bf692d61e2	145	HAL_DMA_IRQHandler(&hdma_spi_rx);
mimi3	24:92bf692d61e2	146	}
mimi3	24:92bf692d61e2	147	#endif
mimi3	24:92bf692d61e2	148
mimi3	24:92bf692d61e2	149	/* SPI3 */
mimi3	24:92bf692d61e2	150	#if defined(SPI3_BASE)
mimi3	24:92bf692d61e2	151	void SPI3_DMAx_TX_IRQHandler(void)
mimi3	24:92bf692d61e2	152	{
mimi3	24:92bf692d61e2	153	HAL_DMA_IRQHandler(&hdma_spi_tx);
mimi3	24:92bf692d61e2	154	}
mimi3	24:92bf692d61e2	155	void SPI3_DMAx_RX_IRQHandler(void)
mimi3	24:92bf692d61e2	156	{
mimi3	24:92bf692d61e2	157	HAL_DMA_IRQHandler(&hdma_spi_rx);
mimi3	24:92bf692d61e2	158	}
mimi3	24:92bf692d61e2	159	#endif
mimi3	24:92bf692d61e2	160
mimi3	24:92bf692d61e2	161	#endif /* TARGET_STM32F3 */
mimi3	24:92bf692d61e2	162

Repository toolbox

Export to desktop IDE

Repository details

Type:	Library
Created:	14 Feb 2016
Imports:	90
Forks:	1
Commits:	39
Dependents:	2
Dependencies:	0
Followers:	10
Issues:	1

The code in this repository is Apache licensed.