mi mi / SDFileSystemDMA Featured

first 2016/02 SDFileSystemDMA inherited from Official SDFileSystem.

Dependents:   SDFileSystemDMA-test DmdFullRGB_0_1

Fork of SDFileSystemDMA by mi mi

SDFileSystemDMA is enhanced SDFileSystem library for STM32 micros by using DMA functionality.
Max read transfer rate reaches over 2MByte/sec at 24MHz SPI clock if enough read buffer size is set.
Even though minimum read buffer size (512Byte) is set, read transfer rate will reach over 1MByte/sec at 24MHz SPI Clock.
( but depends on the ability of each SD card)

Test program is here.
https://developer.mbed.org/users/mimi3/code/SDFileSystemDMA-test/

/media/uploads/mimi3/sdfilesystemdma-speed-test3-read-buffer-512byte.png

/media/uploads/mimi3/sdfilesystemdma-speed-test-buffer-vs-spi-clock-nucleo-f411re-96mhz.png

Supported SPI port is shown below table.

(v): Verified. It works well.
(w): Probably it will work well. (not tested)
(c): Only compiled. (not tested)
(f): Over flash.
(r): Only read mode. (when _FS_READONLY==1)
(u) Under construction
(z): Dose not work.

Caution

If your board has SRAM less than or equal to 8KB, the buffer size must be set to 512 Bytes.

Supported Boards:
Cortex-M0

BoardSRAMSPI1SPI2SPI3
NUCLEO-F030R88KB(v)
DISCO-F051R88KB(w)
NUCLEO-F031K64KB(f)
NUCLEO-F042K66KB(r)
NUCLEO-F070RB16KB(w)
NUCLEO-F072RB16KB(w)
NUCLEO-F091RC32KB(c)

Cortex-L0

BoardSRAMSPI1SPI2SPI3
DISCO-L053C88KB(c)
NUCLEO-L053R88KB(c)
NUCLEO-L073RZ20KB(c)

Cortex-M3

BoardSRAMSPI1SPI2SPI3
DISCO-F100RB8KB(v)(v)-
BLUEPILL-F103CB20KB(w)(w)-
NUCLEO-F103RB20KB(v)(v)-
NUCLEO-L152RE80KB(v)(w)-
MOTE-L152RC32KB(w)(w)-

Cortex-M4
F3

BoardSRAMSPI1SPI2SPI3
DISCO-F303VC40KB-(v)(v)
NUCLEO-F303RE64KB(w)(w)(w)
NUCLEO-F302R816KB--(c)
NUCLEO-F303K812KB(c)--
DISCO-F334C812KB(c)--
NUCLEO-F334R812KB(c)--

F4

BoardSPI1SPI2SPI3
ELMO-F411RE(w)-(w)
MTS-MDOT-F411RE(u)-(u)
MTS-DRAGONFLY-F411RE(w)-(w)
NUCLEO-F411RE(v)-(v)
NUCLEO-F401RE(w)-(w)
MTS-MDOT-F405RG(u)-(u)
NUCLEO-F410RB(c)-(c)
NUCLEO-F446RE(c)-(c)
NUCLEO-F429ZI(c)-(c)
B96B-F446VE(c)-(c)
NUCLEO-F446ZE(c)-(c)
DISCO-F429ZI(u)-(u)
DISCO-F469NI(c)-(c)

Information

This library is set to use "short file name" in SDFileSystemDMA/FATFileSystem/ChaN/ffconf.h . ( _USE_LFN=0)
You can change this option to _USE_LFN=1 .

spi_dma/spi_dma_stm32f3.c@5:809e2eece945, 2016-02-14 (annotated)

Committer:
mimi3
Date:
Sun Feb 14 15:57:06 2016 +0900
Revision:
5:809e2eece945
Child:
8:dc1dac5c7abd
DISCO-F303VC: OK. Verified

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mimi3 5:809e2eece945 1 #if defined(TARGET_STM32F3)
mimi3 5:809e2eece945 2 /*
mimi3 5:809e2eece945 3
mimi3 5:809e2eece945 4 This file is licensed under Apache 2.0 license.
mimi3 5:809e2eece945 5 (C) 2016 dinau
mimi3 5:809e2eece945 6
mimi3 5:809e2eece945 7 */
mimi3 5:809e2eece945 8 #include "spi_dma.h"
mimi3 5:809e2eece945 9
mimi3 5:809e2eece945 10 #define DMAx_CLK_ENABLE() __DMA2_CLK_ENABLE()
mimi3 5:809e2eece945 11 #define SPIx_TX_DMA_CHANNEL DMA2_Channel2
mimi3 5:809e2eece945 12 #define SPIx_RX_DMA_CHANNEL DMA2_Channel1
mimi3 5:809e2eece945 13 #define SPIx_DMA_TX_IRQn DMA2_Channel2_IRQn
mimi3 5:809e2eece945 14 #define SPIx_DMA_RX_IRQn DMA2_Channel1_IRQn
mimi3 5:809e2eece945 15 #define DMAx_TX_IRQHandler DMA2_Channel2_IRQHandler
mimi3 5:809e2eece945 16 #define DMAx_RX_IRQHandler DMA2_Channel1_IRQHandler
mimi3 5:809e2eece945 17
mimi3 5:809e2eece945 18 #define readReg( reg, mask) ( (reg) & (mask) )
mimi3 5:809e2eece945 19
mimi3 5:809e2eece945 20
mimi3 5:809e2eece945 21 void spi_dma_get_info( SPI_TypeDef *spi )
mimi3 5:809e2eece945 22 {
mimi3 5:809e2eece945 23 SPI_HandleTypeDef *hspi;
mimi3 5:809e2eece945 24 if( spi == SPI3 ){
mimi3 5:809e2eece945 25 hspi = &Spi3Handle;
mimi3 5:809e2eece945 26 }
mimi3 5:809e2eece945 27 #if 0
mimi3 5:809e2eece945 28 else {
mimi3 5:809e2eece945 29 hspi = &Spi2Handle;
mimi3 5:809e2eece945 30 }
mimi3 5:809e2eece945 31 #endif
mimi3 5:809e2eece945 32 hspi->Instance = spi;
mimi3 5:809e2eece945 33 hspi->Init.Mode = readReg(spi->CR1, SPI_MODE_MASTER);
mimi3 5:809e2eece945 34 hspi->Init.BaudRatePrescaler = readReg(spi->CR1, SPI_CR1_BR);
mimi3 5:809e2eece945 35 hspi->Init.Direction = readReg(spi->CR1, SPI_CR1_BIDIMODE);
mimi3 5:809e2eece945 36 hspi->Init.CLKPhase = readReg(spi->CR1, SPI_CR1_CPHA);
mimi3 5:809e2eece945 37 hspi->Init.CLKPolarity = readReg(spi->CR1, SPI_CR1_CPOL);
mimi3 5:809e2eece945 38 hspi->Init.CRCCalculation = readReg(spi->CR1, SPI_CR1_CRCEN);
mimi3 5:809e2eece945 39 hspi->Init.CRCPolynomial = spi->CRCPR & 0xFFFF;
mimi3 5:809e2eece945 40 hspi->Init.DataSize = readReg(spi->CR1, SPI_CR2_DS);
mimi3 5:809e2eece945 41 hspi->Init.FirstBit = SPI_FIRSTBIT_MSB;
mimi3 5:809e2eece945 42 hspi->Init.NSS = readReg(spi->CR1, SPI_CR1_SSM);
mimi3 5:809e2eece945 43 hspi->Init.TIMode = SPI_TIMODE_DISABLED;
mimi3 5:809e2eece945 44 hspi->State = HAL_SPI_STATE_READY;
mimi3 5:809e2eece945 45 }
mimi3 5:809e2eece945 46
mimi3 5:809e2eece945 47 void spi_dma_handle_setup( SPI_TypeDef *spi, uint8_t mode ){
mimi3 5:809e2eece945 48 /* Peripheral DMA init*/
mimi3 5:809e2eece945 49 if( spi == SPI3 ){
mimi3 5:809e2eece945 50 /* TX: */
mimi3 5:809e2eece945 51 hdma_spi3_tx.Instance = SPIx_TX_DMA_CHANNEL;
mimi3 5:809e2eece945 52 hdma_spi3_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
mimi3 5:809e2eece945 53 hdma_spi3_tx.Init.PeriphInc = DMA_PINC_DISABLE;
mimi3 5:809e2eece945 54 if (mode == DMA_SPI_READ){
mimi3 5:809e2eece945 55 hdma_spi3_tx.Init.MemInc = DMA_MINC_DISABLE;
mimi3 5:809e2eece945 56 }
mimi3 5:809e2eece945 57 else{
mimi3 5:809e2eece945 58 hdma_spi3_tx.Init.MemInc = DMA_MINC_ENABLE;
mimi3 5:809e2eece945 59 }
mimi3 5:809e2eece945 60 hdma_spi3_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
mimi3 5:809e2eece945 61 hdma_spi3_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
mimi3 5:809e2eece945 62 hdma_spi3_tx.Init.Mode = DMA_NORMAL;
mimi3 5:809e2eece945 63 hdma_spi3_tx.Init.Priority = DMA_PRIORITY_LOW;
mimi3 5:809e2eece945 64 HAL_DMA_Init(&hdma_spi3_tx);
mimi3 5:809e2eece945 65 __HAL_LINKDMA( &Spi3Handle,hdmatx,hdma_spi3_tx);
mimi3 5:809e2eece945 66
mimi3 5:809e2eece945 67 /* RX: */
mimi3 5:809e2eece945 68 hdma_spi3_rx.Instance = SPIx_RX_DMA_CHANNEL;
mimi3 5:809e2eece945 69 hdma_spi3_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
mimi3 5:809e2eece945 70 hdma_spi3_rx.Init.PeriphInc = DMA_PINC_DISABLE;
mimi3 5:809e2eece945 71 if (mode == DMA_SPI_READ){
mimi3 5:809e2eece945 72 hdma_spi3_rx.Init.MemInc = DMA_MINC_ENABLE;
mimi3 5:809e2eece945 73 }
mimi3 5:809e2eece945 74 else{
mimi3 5:809e2eece945 75 hdma_spi3_rx.Init.MemInc = DMA_MINC_DISABLE;
mimi3 5:809e2eece945 76 }
mimi3 5:809e2eece945 77 hdma_spi3_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
mimi3 5:809e2eece945 78 hdma_spi3_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
mimi3 5:809e2eece945 79 hdma_spi3_rx.Init.Mode = DMA_NORMAL;
mimi3 5:809e2eece945 80 hdma_spi3_rx.Init.Priority = DMA_PRIORITY_HIGH;
mimi3 5:809e2eece945 81 HAL_DMA_Init(&hdma_spi3_rx);
mimi3 5:809e2eece945 82
mimi3 5:809e2eece945 83 __HAL_LINKDMA( &Spi3Handle,hdmarx,hdma_spi3_rx);
mimi3 5:809e2eece945 84 }
mimi3 5:809e2eece945 85 #if 0
mimi3 5:809e2eece945 86 else if( spi == SPI2 ) {
mimi3 5:809e2eece945 87
mimi3 5:809e2eece945 88 }
mimi3 5:809e2eece945 89 #endif
mimi3 5:809e2eece945 90 }
mimi3 5:809e2eece945 91
mimi3 5:809e2eece945 92 void spi_dma_irq_setup( SPI_TypeDef *spi)
mimi3 5:809e2eece945 93 {
mimi3 5:809e2eece945 94 if( spi == SPI3 ) {
mimi3 5:809e2eece945 95 /* DMA controller clock enable */
mimi3 5:809e2eece945 96 DMAx_CLK_ENABLE();
mimi3 5:809e2eece945 97
mimi3 5:809e2eece945 98 /* DMA interrupt init */
mimi3 5:809e2eece945 99 HAL_NVIC_SetPriority(SPIx_DMA_TX_IRQn, 3, 0);
mimi3 5:809e2eece945 100 HAL_NVIC_EnableIRQ( SPIx_DMA_TX_IRQn);
mimi3 5:809e2eece945 101 HAL_NVIC_SetPriority(SPIx_DMA_RX_IRQn, 2, 0);
mimi3 5:809e2eece945 102 HAL_NVIC_EnableIRQ( SPIx_DMA_RX_IRQn);
mimi3 5:809e2eece945 103 }
mimi3 5:809e2eece945 104 #if 0
mimi3 5:809e2eece945 105 else if ( spi == SPI2 ){
mimi3 5:809e2eece945 106
mimi3 5:809e2eece945 107 }
mimi3 5:809e2eece945 108 #endif
mimi3 5:809e2eece945 109 }
mimi3 5:809e2eece945 110
mimi3 5:809e2eece945 111 void DMAx_RX_IRQHandler(void)
mimi3 5:809e2eece945 112 {
mimi3 5:809e2eece945 113 HAL_DMA_IRQHandler(&hdma_spi3_rx);
mimi3 5:809e2eece945 114 }
mimi3 5:809e2eece945 115
mimi3 5:809e2eece945 116 void DMAx_TX_IRQHandler(void)
mimi3 5:809e2eece945 117 {
mimi3 5:809e2eece945 118 HAL_DMA_IRQHandler(&hdma_spi3_tx);
mimi3 5:809e2eece945 119 }
mimi3 5:809e2eece945 120
mimi3 5:809e2eece945 121 #endif /* TARGET_STM32F1 */
mimi3 5:809e2eece945 122