workaround

#include "mbed.h"



/*************** functions needed to use external xtal with mbed library for Nucleo F031K6 **********/

uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
{
    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
    RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};

    //Select HSI as system clock source to allow modification of the PLL configuration
    RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
    RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
    if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
        return 0; // FAIL
    }


    // Select HSE oscillator as PLL source
    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
    if (bypass == 0) {
        RCC_OscInitStruct.HSEState   = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
    } else {
        RCC_OscInitStruct.HSEState   = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN only
    }
    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_ON;
    RCC_OscInitStruct.PLL.PLLSource  = RCC_PLLSOURCE_HSE;
    RCC_OscInitStruct.PLL.PREDIV     = RCC_PREDIV_DIV2;
    RCC_OscInitStruct.PLL.PLLMUL     = RCC_PLL_MUL12;
    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
        return 0; // FAIL
    }

    // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 48 MHz
    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 48 MHz
    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
        return 0; // FAIL
    }


    return 1; // OK
}

uint8_t SetSysClock_PLL_HSI(void)
{
    RCC_OscInitTypeDef RCC_OscInitStruct;
    RCC_ClkInitTypeDef RCC_ClkInitStruct;

    // Select PLLCLK = 48 MHz ((HSI 8 MHz / 2) * 12)
    RCC_OscInitStruct.OscillatorType          = RCC_OSCILLATORTYPE_HSI;
    RCC_OscInitStruct.HSEState                = RCC_HSE_OFF;
    RCC_OscInitStruct.LSEState                = RCC_LSE_OFF;
    RCC_OscInitStruct.HSIState                = RCC_HSI_ON;
    RCC_OscInitStruct.HSICalibrationValue     = RCC_HSICALIBRATION_DEFAULT;
    RCC_OscInitStruct.HSI14State              = RCC_HSI_OFF;
    RCC_OscInitStruct.HSI14CalibrationValue   = RCC_HSI14CALIBRATION_DEFAULT;
    RCC_OscInitStruct.LSIState                = RCC_LSI_OFF;
    RCC_OscInitStruct.PLL.PLLState            = RCC_PLL_ON;
    RCC_OscInitStruct.PLL.PLLSource           = RCC_PLLSOURCE_HSI; // HSI div 2
    RCC_OscInitStruct.PLL.PREDIV              = RCC_PREDIV_DIV1;
    RCC_OscInitStruct.PLL.PLLMUL              = RCC_PLL_MUL12;
    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
        return 0; // FAIL
    }

    // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 48 MHz
    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 48 MHz
    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
        return 0; // FAIL
    }


    return 1; // OK
}


void SwitchToExtXtal()
{
    /* HSE must be off before second call HAL_RCC_OscConfig (HAL v1.4.4)  */
    __HAL_RCC_HSE_CONFIG(RCC_HSE_OFF);
    /* try to start with HSE and external xtal */
    if (SetSysClock_PLL_HSE(0) == 0) {
        /* start with HSI clock */
        SetSysClock_PLL_HSI();
    }

}

/****************************************************************************************/

PwmOut testout(PA_4);

int main()
{
    SwitchToExtXtal(); // switch system clock to external xtal 8MHz

   // frequency test
    testout.period(0.001f); // 1kHz frequency on pin PA_4
    testout.write(0.5f);

    while (1) {}
    
}