Nothing Special / mbed-STM32F103C8

Modification of Mbed-dev library for LQFP48 package microcontrollers: STM32F103C8 (STM32F103C8T6) and STM32F103CB (STM32F103CBT6) (Bluepill boards, Maple mini etc. )

Fork of mbed-STM32F103C8_org by Nothing Special

Library for STM32F103C8 (Bluepill boards etc.).
Use this instead of mbed library.
This library allows the size of the code in the FLASH up to 128kB. Therefore, code also runs on microcontrollers STM32F103CB (eg. Maple mini).
But in the case of STM32F103C8, check the size of the resulting code would not exceed 64kB.

To compile a program with this library, use NUCLEO-F103RB as the target name. !

Changes:

  • Corrected initialization of the HSE + crystal clock (mbed permanent bug), allowing the use of on-board xtal (8MHz).(1)
  • Additionally, it also set USB clock (48Mhz).(2)
  • Definitions of pins and peripherals adjusted to LQFP48 case.
  • Board led LED1 is now PC_13 (3)
  • USER_BUTTON is now PC_14 (4)

    Now the library is complete rebuilt based on mbed-dev v160 (and not yet fully tested).

notes
(1) - In case 8MHz xtal on board, CPU frequency is 72MHz. Without xtal is 64MHz.
(2) - Using the USB interface is only possible if STM32 is clocking by on-board 8MHz xtal or external clock signal 8MHz on the OSC_IN pin.
(3) - On Bluepill board led operation is reversed, i.e. 0 - led on, 1 - led off.
(4) - Bluepill board has no real user button

Information

After export to SW4STM (AC6):

  • add line #include "mbed_config.h" in files Serial.h and RawSerial.h
  • in project properties change Optimisation Level to Optimise for size (-Os)

cmsis/core_sc000.h@148:8b0b02bf146f, 2017-04-27 (annotated)

Committer:
mega64
Date:
Thu Apr 27 23:56:38 2017 +0000
Revision:
148:8b0b02bf146f
Parent:
146:03e976389d16 
Remove unnecessary folders

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mega64 146:03e976389d16 1 /**************************************************************************//**
mega64 146:03e976389d16 2 * @file core_sc000.h
mega64 146:03e976389d16 3 * @brief CMSIS SC000 Core Peripheral Access Layer Header File
mega64 146:03e976389d16 4 * @version V4.10
mega64 146:03e976389d16 5 * @date 18. March 2015
mega64 146:03e976389d16 6 *
mega64 146:03e976389d16 7 * @note
mega64 146:03e976389d16 8 *
mega64 146:03e976389d16 9 ******************************************************************************/
mega64 146:03e976389d16 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
mega64 146:03e976389d16 11
mega64 146:03e976389d16 12 All rights reserved.
mega64 146:03e976389d16 13 Redistribution and use in source and binary forms, with or without
mega64 146:03e976389d16 14 modification, are permitted provided that the following conditions are met:
mega64 146:03e976389d16 15 - Redistributions of source code must retain the above copyright
mega64 146:03e976389d16 16 notice, this list of conditions and the following disclaimer.
mega64 146:03e976389d16 17 - Redistributions in binary form must reproduce the above copyright
mega64 146:03e976389d16 18 notice, this list of conditions and the following disclaimer in the
mega64 146:03e976389d16 19 documentation and/or other materials provided with the distribution.
mega64 146:03e976389d16 20 - Neither the name of ARM nor the names of its contributors may be used
mega64 146:03e976389d16 21 to endorse or promote products derived from this software without
mega64 146:03e976389d16 22 specific prior written permission.
mega64 146:03e976389d16 23 *
mega64 146:03e976389d16 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mega64 146:03e976389d16 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mega64 146:03e976389d16 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
mega64 146:03e976389d16 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
mega64 146:03e976389d16 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
mega64 146:03e976389d16 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
mega64 146:03e976389d16 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mega64 146:03e976389d16 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mega64 146:03e976389d16 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
mega64 146:03e976389d16 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mega64 146:03e976389d16 34 POSSIBILITY OF SUCH DAMAGE.
mega64 146:03e976389d16 35 ---------------------------------------------------------------------------*/
mega64 146:03e976389d16 36
mega64 146:03e976389d16 37
mega64 146:03e976389d16 38 #if defined ( __ICCARM__ )
mega64 146:03e976389d16 39 #pragma system_include /* treat file as system include file for MISRA check */
mega64 146:03e976389d16 40 #endif
mega64 146:03e976389d16 41
mega64 146:03e976389d16 42 #ifndef __CORE_SC000_H_GENERIC
mega64 146:03e976389d16 43 #define __CORE_SC000_H_GENERIC
mega64 146:03e976389d16 44
mega64 146:03e976389d16 45 #ifdef __cplusplus
mega64 146:03e976389d16 46 extern "C" {
mega64 146:03e976389d16 47 #endif
mega64 146:03e976389d16 48
mega64 146:03e976389d16 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
mega64 146:03e976389d16 50 CMSIS violates the following MISRA-C:2004 rules:
mega64 146:03e976389d16 51
mega64 146:03e976389d16 52 \li Required Rule 8.5, object/function definition in header file.<br>
mega64 146:03e976389d16 53 Function definitions in header files are used to allow 'inlining'.
mega64 146:03e976389d16 54
mega64 146:03e976389d16 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
mega64 146:03e976389d16 56 Unions are used for effective representation of core registers.
mega64 146:03e976389d16 57
mega64 146:03e976389d16 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
mega64 146:03e976389d16 59 Function-like macros are used to allow more efficient code.
mega64 146:03e976389d16 60 */
mega64 146:03e976389d16 61
mega64 146:03e976389d16 62
mega64 146:03e976389d16 63 /*******************************************************************************
mega64 146:03e976389d16 64 * CMSIS definitions
mega64 146:03e976389d16 65 ******************************************************************************/
mega64 146:03e976389d16 66 /** \ingroup SC000
mega64 146:03e976389d16 67 @{
mega64 146:03e976389d16 68 */
mega64 146:03e976389d16 69
mega64 146:03e976389d16 70 /* CMSIS SC000 definitions */
mega64 146:03e976389d16 71 #define __SC000_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
mega64 146:03e976389d16 72 #define __SC000_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
mega64 146:03e976389d16 73 #define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16) | \
mega64 146:03e976389d16 74 __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
mega64 146:03e976389d16 75
mega64 146:03e976389d16 76 #define __CORTEX_SC (000) /*!< Cortex secure core */
mega64 146:03e976389d16 77
mega64 146:03e976389d16 78
mega64 146:03e976389d16 79 #if defined ( __CC_ARM )
mega64 146:03e976389d16 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
mega64 146:03e976389d16 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
mega64 146:03e976389d16 82 #define __STATIC_INLINE static __inline
mega64 146:03e976389d16 83
mega64 146:03e976389d16 84 #elif defined ( __GNUC__ )
mega64 146:03e976389d16 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
mega64 146:03e976389d16 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
mega64 146:03e976389d16 87 #define __STATIC_INLINE static inline
mega64 146:03e976389d16 88
mega64 146:03e976389d16 89 #elif defined ( __ICCARM__ )
mega64 146:03e976389d16 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
mega64 146:03e976389d16 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
mega64 146:03e976389d16 92 #define __STATIC_INLINE static inline
mega64 146:03e976389d16 93
mega64 146:03e976389d16 94 #elif defined ( __TMS470__ )
mega64 146:03e976389d16 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
mega64 146:03e976389d16 96 #define __STATIC_INLINE static inline
mega64 146:03e976389d16 97
mega64 146:03e976389d16 98 #elif defined ( __TASKING__ )
mega64 146:03e976389d16 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
mega64 146:03e976389d16 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
mega64 146:03e976389d16 101 #define __STATIC_INLINE static inline
mega64 146:03e976389d16 102
mega64 146:03e976389d16 103 #elif defined ( __CSMC__ )
mega64 146:03e976389d16 104 #define __packed
mega64 146:03e976389d16 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
mega64 146:03e976389d16 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
mega64 146:03e976389d16 107 #define __STATIC_INLINE static inline
mega64 146:03e976389d16 108
mega64 146:03e976389d16 109 #endif
mega64 146:03e976389d16 110
mega64 146:03e976389d16 111 /** __FPU_USED indicates whether an FPU is used or not.
mega64 146:03e976389d16 112 This core does not support an FPU at all
mega64 146:03e976389d16 113 */
mega64 146:03e976389d16 114 #define __FPU_USED 0
mega64 146:03e976389d16 115
mega64 146:03e976389d16 116 #if defined ( __CC_ARM )
mega64 146:03e976389d16 117 #if defined __TARGET_FPU_VFP
mega64 146:03e976389d16 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mega64 146:03e976389d16 119 #endif
mega64 146:03e976389d16 120
mega64 146:03e976389d16 121 #elif defined ( __GNUC__ )
mega64 146:03e976389d16 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
mega64 146:03e976389d16 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mega64 146:03e976389d16 124 #endif
mega64 146:03e976389d16 125
mega64 146:03e976389d16 126 #elif defined ( __ICCARM__ )
mega64 146:03e976389d16 127 #if defined __ARMVFP__
mega64 146:03e976389d16 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mega64 146:03e976389d16 129 #endif
mega64 146:03e976389d16 130
mega64 146:03e976389d16 131 #elif defined ( __TMS470__ )
mega64 146:03e976389d16 132 #if defined __TI__VFP_SUPPORT____
mega64 146:03e976389d16 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mega64 146:03e976389d16 134 #endif
mega64 146:03e976389d16 135
mega64 146:03e976389d16 136 #elif defined ( __TASKING__ )
mega64 146:03e976389d16 137 #if defined __FPU_VFP__
mega64 146:03e976389d16 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mega64 146:03e976389d16 139 #endif
mega64 146:03e976389d16 140
mega64 146:03e976389d16 141 #elif defined ( __CSMC__ ) /* Cosmic */
mega64 146:03e976389d16 142 #if ( __CSMC__ & 0x400) // FPU present for parser
mega64 146:03e976389d16 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mega64 146:03e976389d16 144 #endif
mega64 146:03e976389d16 145 #endif
mega64 146:03e976389d16 146
mega64 146:03e976389d16 147 #include <stdint.h> /* standard types definitions */
mega64 146:03e976389d16 148 #include <core_cmInstr.h> /* Core Instruction Access */
mega64 146:03e976389d16 149 #include <core_cmFunc.h> /* Core Function Access */
mega64 146:03e976389d16 150
mega64 146:03e976389d16 151 #ifdef __cplusplus
mega64 146:03e976389d16 152 }
mega64 146:03e976389d16 153 #endif
mega64 146:03e976389d16 154
mega64 146:03e976389d16 155 #endif /* __CORE_SC000_H_GENERIC */
mega64 146:03e976389d16 156
mega64 146:03e976389d16 157 #ifndef __CMSIS_GENERIC
mega64 146:03e976389d16 158
mega64 146:03e976389d16 159 #ifndef __CORE_SC000_H_DEPENDANT
mega64 146:03e976389d16 160 #define __CORE_SC000_H_DEPENDANT
mega64 146:03e976389d16 161
mega64 146:03e976389d16 162 #ifdef __cplusplus
mega64 146:03e976389d16 163 extern "C" {
mega64 146:03e976389d16 164 #endif
mega64 146:03e976389d16 165
mega64 146:03e976389d16 166 /* check device defines and use defaults */
mega64 146:03e976389d16 167 #if defined __CHECK_DEVICE_DEFINES
mega64 146:03e976389d16 168 #ifndef __SC000_REV
mega64 146:03e976389d16 169 #define __SC000_REV 0x0000
mega64 146:03e976389d16 170 #warning "__SC000_REV not defined in device header file; using default!"
mega64 146:03e976389d16 171 #endif
mega64 146:03e976389d16 172
mega64 146:03e976389d16 173 #ifndef __MPU_PRESENT
mega64 146:03e976389d16 174 #define __MPU_PRESENT 0
mega64 146:03e976389d16 175 #warning "__MPU_PRESENT not defined in device header file; using default!"
mega64 146:03e976389d16 176 #endif
mega64 146:03e976389d16 177
mega64 146:03e976389d16 178 #ifndef __NVIC_PRIO_BITS
mega64 146:03e976389d16 179 #define __NVIC_PRIO_BITS 2
mega64 146:03e976389d16 180 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
mega64 146:03e976389d16 181 #endif
mega64 146:03e976389d16 182
mega64 146:03e976389d16 183 #ifndef __Vendor_SysTickConfig
mega64 146:03e976389d16 184 #define __Vendor_SysTickConfig 0
mega64 146:03e976389d16 185 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
mega64 146:03e976389d16 186 #endif
mega64 146:03e976389d16 187 #endif
mega64 146:03e976389d16 188
mega64 146:03e976389d16 189 /* IO definitions (access restrictions to peripheral registers) */
mega64 146:03e976389d16 190 /**
mega64 146:03e976389d16 191 \defgroup CMSIS_glob_defs CMSIS Global Defines
mega64 146:03e976389d16 192
mega64 146:03e976389d16 193 <strong>IO Type Qualifiers</strong> are used
mega64 146:03e976389d16 194 \li to specify the access to peripheral variables.
mega64 146:03e976389d16 195 \li for automatic generation of peripheral register debug information.
mega64 146:03e976389d16 196 */
mega64 146:03e976389d16 197 #ifdef __cplusplus
mega64 146:03e976389d16 198 #define __I volatile /*!< Defines 'read only' permissions */
mega64 146:03e976389d16 199 #else
mega64 146:03e976389d16 200 #define __I volatile const /*!< Defines 'read only' permissions */
mega64 146:03e976389d16 201 #endif
mega64 146:03e976389d16 202 #define __O volatile /*!< Defines 'write only' permissions */
mega64 146:03e976389d16 203 #define __IO volatile /*!< Defines 'read / write' permissions */
mega64 146:03e976389d16 204
mega64 146:03e976389d16 205 /*@} end of group SC000 */
mega64 146:03e976389d16 206
mega64 146:03e976389d16 207
mega64 146:03e976389d16 208
mega64 146:03e976389d16 209 /*******************************************************************************
mega64 146:03e976389d16 210 * Register Abstraction
mega64 146:03e976389d16 211 Core Register contain:
mega64 146:03e976389d16 212 - Core Register
mega64 146:03e976389d16 213 - Core NVIC Register
mega64 146:03e976389d16 214 - Core SCB Register
mega64 146:03e976389d16 215 - Core SysTick Register
mega64 146:03e976389d16 216 - Core MPU Register
mega64 146:03e976389d16 217 ******************************************************************************/
mega64 146:03e976389d16 218 /** \defgroup CMSIS_core_register Defines and Type Definitions
mega64 146:03e976389d16 219 \brief Type definitions and defines for Cortex-M processor based devices.
mega64 146:03e976389d16 220 */
mega64 146:03e976389d16 221
mega64 146:03e976389d16 222 /** \ingroup CMSIS_core_register
mega64 146:03e976389d16 223 \defgroup CMSIS_CORE Status and Control Registers
mega64 146:03e976389d16 224 \brief Core Register type definitions.
mega64 146:03e976389d16 225 @{
mega64 146:03e976389d16 226 */
mega64 146:03e976389d16 227
mega64 146:03e976389d16 228 /** \brief Union type to access the Application Program Status Register (APSR).
mega64 146:03e976389d16 229 */
mega64 146:03e976389d16 230 typedef union
mega64 146:03e976389d16 231 {
mega64 146:03e976389d16 232 struct
mega64 146:03e976389d16 233 {
mega64 146:03e976389d16 234 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
mega64 146:03e976389d16 235 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
mega64 146:03e976389d16 236 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
mega64 146:03e976389d16 237 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
mega64 146:03e976389d16 238 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
mega64 146:03e976389d16 239 } b; /*!< Structure used for bit access */
mega64 146:03e976389d16 240 uint32_t w; /*!< Type used for word access */
mega64 146:03e976389d16 241 } APSR_Type;
mega64 146:03e976389d16 242
mega64 146:03e976389d16 243 /* APSR Register Definitions */
mega64 146:03e976389d16 244 #define APSR_N_Pos 31 /*!< APSR: N Position */
mega64 146:03e976389d16 245 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
mega64 146:03e976389d16 246
mega64 146:03e976389d16 247 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
mega64 146:03e976389d16 248 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
mega64 146:03e976389d16 249
mega64 146:03e976389d16 250 #define APSR_C_Pos 29 /*!< APSR: C Position */
mega64 146:03e976389d16 251 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
mega64 146:03e976389d16 252
mega64 146:03e976389d16 253 #define APSR_V_Pos 28 /*!< APSR: V Position */
mega64 146:03e976389d16 254 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
mega64 146:03e976389d16 255
mega64 146:03e976389d16 256
mega64 146:03e976389d16 257 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
mega64 146:03e976389d16 258 */
mega64 146:03e976389d16 259 typedef union
mega64 146:03e976389d16 260 {
mega64 146:03e976389d16 261 struct
mega64 146:03e976389d16 262 {
mega64 146:03e976389d16 263 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
mega64 146:03e976389d16 264 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
mega64 146:03e976389d16 265 } b; /*!< Structure used for bit access */
mega64 146:03e976389d16 266 uint32_t w; /*!< Type used for word access */
mega64 146:03e976389d16 267 } IPSR_Type;
mega64 146:03e976389d16 268
mega64 146:03e976389d16 269 /* IPSR Register Definitions */
mega64 146:03e976389d16 270 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
mega64 146:03e976389d16 271 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
mega64 146:03e976389d16 272
mega64 146:03e976389d16 273
mega64 146:03e976389d16 274 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
mega64 146:03e976389d16 275 */
mega64 146:03e976389d16 276 typedef union
mega64 146:03e976389d16 277 {
mega64 146:03e976389d16 278 struct
mega64 146:03e976389d16 279 {
mega64 146:03e976389d16 280 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
mega64 146:03e976389d16 281 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
mega64 146:03e976389d16 282 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
mega64 146:03e976389d16 283 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
mega64 146:03e976389d16 284 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
mega64 146:03e976389d16 285 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
mega64 146:03e976389d16 286 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
mega64 146:03e976389d16 287 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
mega64 146:03e976389d16 288 } b; /*!< Structure used for bit access */
mega64 146:03e976389d16 289 uint32_t w; /*!< Type used for word access */
mega64 146:03e976389d16 290 } xPSR_Type;
mega64 146:03e976389d16 291
mega64 146:03e976389d16 292 /* xPSR Register Definitions */
mega64 146:03e976389d16 293 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
mega64 146:03e976389d16 294 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
mega64 146:03e976389d16 295
mega64 146:03e976389d16 296 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
mega64 146:03e976389d16 297 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
mega64 146:03e976389d16 298
mega64 146:03e976389d16 299 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
mega64 146:03e976389d16 300 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
mega64 146:03e976389d16 301
mega64 146:03e976389d16 302 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
mega64 146:03e976389d16 303 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
mega64 146:03e976389d16 304
mega64 146:03e976389d16 305 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
mega64 146:03e976389d16 306 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
mega64 146:03e976389d16 307
mega64 146:03e976389d16 308 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
mega64 146:03e976389d16 309 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
mega64 146:03e976389d16 310
mega64 146:03e976389d16 311
mega64 146:03e976389d16 312 /** \brief Union type to access the Control Registers (CONTROL).
mega64 146:03e976389d16 313 */
mega64 146:03e976389d16 314 typedef union
mega64 146:03e976389d16 315 {
mega64 146:03e976389d16 316 struct
mega64 146:03e976389d16 317 {
mega64 146:03e976389d16 318 uint32_t _reserved0:1; /*!< bit: 0 Reserved */
mega64 146:03e976389d16 319 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
mega64 146:03e976389d16 320 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
mega64 146:03e976389d16 321 } b; /*!< Structure used for bit access */
mega64 146:03e976389d16 322 uint32_t w; /*!< Type used for word access */
mega64 146:03e976389d16 323 } CONTROL_Type;
mega64 146:03e976389d16 324
mega64 146:03e976389d16 325 /* CONTROL Register Definitions */
mega64 146:03e976389d16 326 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
mega64 146:03e976389d16 327 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
mega64 146:03e976389d16 328
mega64 146:03e976389d16 329 /*@} end of group CMSIS_CORE */
mega64 146:03e976389d16 330
mega64 146:03e976389d16 331
mega64 146:03e976389d16 332 /** \ingroup CMSIS_core_register
mega64 146:03e976389d16 333 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
mega64 146:03e976389d16 334 \brief Type definitions for the NVIC Registers
mega64 146:03e976389d16 335 @{
mega64 146:03e976389d16 336 */
mega64 146:03e976389d16 337
mega64 146:03e976389d16 338 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
mega64 146:03e976389d16 339 */
mega64 146:03e976389d16 340 typedef struct
mega64 146:03e976389d16 341 {
mega64 146:03e976389d16 342 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
mega64 146:03e976389d16 343 uint32_t RESERVED0[31];
mega64 146:03e976389d16 344 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
mega64 146:03e976389d16 345 uint32_t RSERVED1[31];
mega64 146:03e976389d16 346 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
mega64 146:03e976389d16 347 uint32_t RESERVED2[31];
mega64 146:03e976389d16 348 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
mega64 146:03e976389d16 349 uint32_t RESERVED3[31];
mega64 146:03e976389d16 350 uint32_t RESERVED4[64];
mega64 146:03e976389d16 351 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
mega64 146:03e976389d16 352 } NVIC_Type;
mega64 146:03e976389d16 353
mega64 146:03e976389d16 354 /*@} end of group CMSIS_NVIC */
mega64 146:03e976389d16 355
mega64 146:03e976389d16 356
mega64 146:03e976389d16 357 /** \ingroup CMSIS_core_register
mega64 146:03e976389d16 358 \defgroup CMSIS_SCB System Control Block (SCB)
mega64 146:03e976389d16 359 \brief Type definitions for the System Control Block Registers
mega64 146:03e976389d16 360 @{
mega64 146:03e976389d16 361 */
mega64 146:03e976389d16 362
mega64 146:03e976389d16 363 /** \brief Structure type to access the System Control Block (SCB).
mega64 146:03e976389d16 364 */
mega64 146:03e976389d16 365 typedef struct
mega64 146:03e976389d16 366 {
mega64 146:03e976389d16 367 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
mega64 146:03e976389d16 368 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
mega64 146:03e976389d16 369 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
mega64 146:03e976389d16 370 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
mega64 146:03e976389d16 371 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
mega64 146:03e976389d16 372 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
mega64 146:03e976389d16 373 uint32_t RESERVED0[1];
mega64 146:03e976389d16 374 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
mega64 146:03e976389d16 375 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
mega64 146:03e976389d16 376 uint32_t RESERVED1[154];
mega64 146:03e976389d16 377 __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
mega64 146:03e976389d16 378 } SCB_Type;
mega64 146:03e976389d16 379
mega64 146:03e976389d16 380 /* SCB CPUID Register Definitions */
mega64 146:03e976389d16 381 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
mega64 146:03e976389d16 382 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
mega64 146:03e976389d16 383
mega64 146:03e976389d16 384 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
mega64 146:03e976389d16 385 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
mega64 146:03e976389d16 386
mega64 146:03e976389d16 387 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
mega64 146:03e976389d16 388 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
mega64 146:03e976389d16 389
mega64 146:03e976389d16 390 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
mega64 146:03e976389d16 391 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
mega64 146:03e976389d16 392
mega64 146:03e976389d16 393 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
mega64 146:03e976389d16 394 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
mega64 146:03e976389d16 395
mega64 146:03e976389d16 396 /* SCB Interrupt Control State Register Definitions */
mega64 146:03e976389d16 397 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
mega64 146:03e976389d16 398 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
mega64 146:03e976389d16 399
mega64 146:03e976389d16 400 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
mega64 146:03e976389d16 401 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
mega64 146:03e976389d16 402
mega64 146:03e976389d16 403 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
mega64 146:03e976389d16 404 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
mega64 146:03e976389d16 405
mega64 146:03e976389d16 406 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
mega64 146:03e976389d16 407 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
mega64 146:03e976389d16 408
mega64 146:03e976389d16 409 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
mega64 146:03e976389d16 410 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
mega64 146:03e976389d16 411
mega64 146:03e976389d16 412 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
mega64 146:03e976389d16 413 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
mega64 146:03e976389d16 414
mega64 146:03e976389d16 415 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
mega64 146:03e976389d16 416 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
mega64 146:03e976389d16 417
mega64 146:03e976389d16 418 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
mega64 146:03e976389d16 419 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
mega64 146:03e976389d16 420
mega64 146:03e976389d16 421 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
mega64 146:03e976389d16 422 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
mega64 146:03e976389d16 423
mega64 146:03e976389d16 424 /* SCB Interrupt Control State Register Definitions */
mega64 146:03e976389d16 425 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
mega64 146:03e976389d16 426 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
mega64 146:03e976389d16 427
mega64 146:03e976389d16 428 /* SCB Application Interrupt and Reset Control Register Definitions */
mega64 146:03e976389d16 429 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
mega64 146:03e976389d16 430 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
mega64 146:03e976389d16 431
mega64 146:03e976389d16 432 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
mega64 146:03e976389d16 433 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
mega64 146:03e976389d16 434
mega64 146:03e976389d16 435 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
mega64 146:03e976389d16 436 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
mega64 146:03e976389d16 437
mega64 146:03e976389d16 438 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
mega64 146:03e976389d16 439 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
mega64 146:03e976389d16 440
mega64 146:03e976389d16 441 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
mega64 146:03e976389d16 442 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
mega64 146:03e976389d16 443
mega64 146:03e976389d16 444 /* SCB System Control Register Definitions */
mega64 146:03e976389d16 445 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
mega64 146:03e976389d16 446 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
mega64 146:03e976389d16 447
mega64 146:03e976389d16 448 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
mega64 146:03e976389d16 449 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
mega64 146:03e976389d16 450
mega64 146:03e976389d16 451 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
mega64 146:03e976389d16 452 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
mega64 146:03e976389d16 453
mega64 146:03e976389d16 454 /* SCB Configuration Control Register Definitions */
mega64 146:03e976389d16 455 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
mega64 146:03e976389d16 456 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
mega64 146:03e976389d16 457
mega64 146:03e976389d16 458 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
mega64 146:03e976389d16 459 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
mega64 146:03e976389d16 460
mega64 146:03e976389d16 461 /* SCB System Handler Control and State Register Definitions */
mega64 146:03e976389d16 462 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
mega64 146:03e976389d16 463 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
mega64 146:03e976389d16 464
mega64 146:03e976389d16 465 /*@} end of group CMSIS_SCB */
mega64 146:03e976389d16 466
mega64 146:03e976389d16 467
mega64 146:03e976389d16 468 /** \ingroup CMSIS_core_register
mega64 146:03e976389d16 469 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
mega64 146:03e976389d16 470 \brief Type definitions for the System Control and ID Register not in the SCB
mega64 146:03e976389d16 471 @{
mega64 146:03e976389d16 472 */
mega64 146:03e976389d16 473
mega64 146:03e976389d16 474 /** \brief Structure type to access the System Control and ID Register not in the SCB.
mega64 146:03e976389d16 475 */
mega64 146:03e976389d16 476 typedef struct
mega64 146:03e976389d16 477 {
mega64 146:03e976389d16 478 uint32_t RESERVED0[2];
mega64 146:03e976389d16 479 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
mega64 146:03e976389d16 480 } SCnSCB_Type;
mega64 146:03e976389d16 481
mega64 146:03e976389d16 482 /* Auxiliary Control Register Definitions */
mega64 146:03e976389d16 483 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
mega64 146:03e976389d16 484 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
mega64 146:03e976389d16 485
mega64 146:03e976389d16 486 /*@} end of group CMSIS_SCnotSCB */
mega64 146:03e976389d16 487
mega64 146:03e976389d16 488
mega64 146:03e976389d16 489 /** \ingroup CMSIS_core_register
mega64 146:03e976389d16 490 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
mega64 146:03e976389d16 491 \brief Type definitions for the System Timer Registers.
mega64 146:03e976389d16 492 @{
mega64 146:03e976389d16 493 */
mega64 146:03e976389d16 494
mega64 146:03e976389d16 495 /** \brief Structure type to access the System Timer (SysTick).
mega64 146:03e976389d16 496 */
mega64 146:03e976389d16 497 typedef struct
mega64 146:03e976389d16 498 {
mega64 146:03e976389d16 499 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
mega64 146:03e976389d16 500 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
mega64 146:03e976389d16 501 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
mega64 146:03e976389d16 502 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
mega64 146:03e976389d16 503 } SysTick_Type;
mega64 146:03e976389d16 504
mega64 146:03e976389d16 505 /* SysTick Control / Status Register Definitions */
mega64 146:03e976389d16 506 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
mega64 146:03e976389d16 507 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
mega64 146:03e976389d16 508
mega64 146:03e976389d16 509 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
mega64 146:03e976389d16 510 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
mega64 146:03e976389d16 511
mega64 146:03e976389d16 512 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
mega64 146:03e976389d16 513 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
mega64 146:03e976389d16 514
mega64 146:03e976389d16 515 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
mega64 146:03e976389d16 516 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
mega64 146:03e976389d16 517
mega64 146:03e976389d16 518 /* SysTick Reload Register Definitions */
mega64 146:03e976389d16 519 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
mega64 146:03e976389d16 520 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
mega64 146:03e976389d16 521
mega64 146:03e976389d16 522 /* SysTick Current Register Definitions */
mega64 146:03e976389d16 523 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
mega64 146:03e976389d16 524 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
mega64 146:03e976389d16 525
mega64 146:03e976389d16 526 /* SysTick Calibration Register Definitions */
mega64 146:03e976389d16 527 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
mega64 146:03e976389d16 528 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
mega64 146:03e976389d16 529
mega64 146:03e976389d16 530 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
mega64 146:03e976389d16 531 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
mega64 146:03e976389d16 532
mega64 146:03e976389d16 533 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
mega64 146:03e976389d16 534 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
mega64 146:03e976389d16 535
mega64 146:03e976389d16 536 /*@} end of group CMSIS_SysTick */
mega64 146:03e976389d16 537
mega64 146:03e976389d16 538 #if (__MPU_PRESENT == 1)
mega64 146:03e976389d16 539 /** \ingroup CMSIS_core_register
mega64 146:03e976389d16 540 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
mega64 146:03e976389d16 541 \brief Type definitions for the Memory Protection Unit (MPU)
mega64 146:03e976389d16 542 @{
mega64 146:03e976389d16 543 */
mega64 146:03e976389d16 544
mega64 146:03e976389d16 545 /** \brief Structure type to access the Memory Protection Unit (MPU).
mega64 146:03e976389d16 546 */
mega64 146:03e976389d16 547 typedef struct
mega64 146:03e976389d16 548 {
mega64 146:03e976389d16 549 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
mega64 146:03e976389d16 550 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
mega64 146:03e976389d16 551 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
mega64 146:03e976389d16 552 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
mega64 146:03e976389d16 553 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
mega64 146:03e976389d16 554 } MPU_Type;
mega64 146:03e976389d16 555
mega64 146:03e976389d16 556 /* MPU Type Register */
mega64 146:03e976389d16 557 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
mega64 146:03e976389d16 558 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
mega64 146:03e976389d16 559
mega64 146:03e976389d16 560 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
mega64 146:03e976389d16 561 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
mega64 146:03e976389d16 562
mega64 146:03e976389d16 563 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
mega64 146:03e976389d16 564 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
mega64 146:03e976389d16 565
mega64 146:03e976389d16 566 /* MPU Control Register */
mega64 146:03e976389d16 567 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
mega64 146:03e976389d16 568 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
mega64 146:03e976389d16 569
mega64 146:03e976389d16 570 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
mega64 146:03e976389d16 571 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
mega64 146:03e976389d16 572
mega64 146:03e976389d16 573 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
mega64 146:03e976389d16 574 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
mega64 146:03e976389d16 575
mega64 146:03e976389d16 576 /* MPU Region Number Register */
mega64 146:03e976389d16 577 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
mega64 146:03e976389d16 578 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
mega64 146:03e976389d16 579
mega64 146:03e976389d16 580 /* MPU Region Base Address Register */
mega64 146:03e976389d16 581 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
mega64 146:03e976389d16 582 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
mega64 146:03e976389d16 583
mega64 146:03e976389d16 584 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
mega64 146:03e976389d16 585 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
mega64 146:03e976389d16 586
mega64 146:03e976389d16 587 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
mega64 146:03e976389d16 588 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
mega64 146:03e976389d16 589
mega64 146:03e976389d16 590 /* MPU Region Attribute and Size Register */
mega64 146:03e976389d16 591 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
mega64 146:03e976389d16 592 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
mega64 146:03e976389d16 593
mega64 146:03e976389d16 594 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
mega64 146:03e976389d16 595 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
mega64 146:03e976389d16 596
mega64 146:03e976389d16 597 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
mega64 146:03e976389d16 598 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
mega64 146:03e976389d16 599
mega64 146:03e976389d16 600 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
mega64 146:03e976389d16 601 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
mega64 146:03e976389d16 602
mega64 146:03e976389d16 603 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
mega64 146:03e976389d16 604 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
mega64 146:03e976389d16 605
mega64 146:03e976389d16 606 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
mega64 146:03e976389d16 607 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
mega64 146:03e976389d16 608
mega64 146:03e976389d16 609 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
mega64 146:03e976389d16 610 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
mega64 146:03e976389d16 611
mega64 146:03e976389d16 612 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
mega64 146:03e976389d16 613 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
mega64 146:03e976389d16 614
mega64 146:03e976389d16 615 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
mega64 146:03e976389d16 616 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
mega64 146:03e976389d16 617
mega64 146:03e976389d16 618 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
mega64 146:03e976389d16 619 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
mega64 146:03e976389d16 620
mega64 146:03e976389d16 621 /*@} end of group CMSIS_MPU */
mega64 146:03e976389d16 622 #endif
mega64 146:03e976389d16 623
mega64 146:03e976389d16 624
mega64 146:03e976389d16 625 /** \ingroup CMSIS_core_register
mega64 146:03e976389d16 626 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
mega64 146:03e976389d16 627 \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR)
mega64 146:03e976389d16 628 are only accessible over DAP and not via processor. Therefore
mega64 146:03e976389d16 629 they are not covered by the Cortex-M0 header file.
mega64 146:03e976389d16 630 @{
mega64 146:03e976389d16 631 */
mega64 146:03e976389d16 632 /*@} end of group CMSIS_CoreDebug */
mega64 146:03e976389d16 633
mega64 146:03e976389d16 634
mega64 146:03e976389d16 635 /** \ingroup CMSIS_core_register
mega64 146:03e976389d16 636 \defgroup CMSIS_core_base Core Definitions
mega64 146:03e976389d16 637 \brief Definitions for base addresses, unions, and structures.
mega64 146:03e976389d16 638 @{
mega64 146:03e976389d16 639 */
mega64 146:03e976389d16 640
mega64 146:03e976389d16 641 /* Memory mapping of SC000 Hardware */
mega64 146:03e976389d16 642 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
mega64 146:03e976389d16 643 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
mega64 146:03e976389d16 644 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
mega64 146:03e976389d16 645 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
mega64 146:03e976389d16 646
mega64 146:03e976389d16 647 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
mega64 146:03e976389d16 648 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
mega64 146:03e976389d16 649 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
mega64 146:03e976389d16 650 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
mega64 146:03e976389d16 651
mega64 146:03e976389d16 652 #if (__MPU_PRESENT == 1)
mega64 146:03e976389d16 653 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
mega64 146:03e976389d16 654 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
mega64 146:03e976389d16 655 #endif
mega64 146:03e976389d16 656
mega64 146:03e976389d16 657 /*@} */
mega64 146:03e976389d16 658
mega64 146:03e976389d16 659
mega64 146:03e976389d16 660
mega64 146:03e976389d16 661 /*******************************************************************************
mega64 146:03e976389d16 662 * Hardware Abstraction Layer
mega64 146:03e976389d16 663 Core Function Interface contains:
mega64 146:03e976389d16 664 - Core NVIC Functions
mega64 146:03e976389d16 665 - Core SysTick Functions
mega64 146:03e976389d16 666 - Core Register Access Functions
mega64 146:03e976389d16 667 ******************************************************************************/
mega64 146:03e976389d16 668 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
mega64 146:03e976389d16 669 */
mega64 146:03e976389d16 670
mega64 146:03e976389d16 671
mega64 146:03e976389d16 672
mega64 146:03e976389d16 673 /* ########################## NVIC functions #################################### */
mega64 146:03e976389d16 674 /** \ingroup CMSIS_Core_FunctionInterface
mega64 146:03e976389d16 675 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
mega64 146:03e976389d16 676 \brief Functions that manage interrupts and exceptions via the NVIC.
mega64 146:03e976389d16 677 @{
mega64 146:03e976389d16 678 */
mega64 146:03e976389d16 679
mega64 146:03e976389d16 680 /* Interrupt Priorities are WORD accessible only under ARMv6M */
mega64 146:03e976389d16 681 /* The following MACROS handle generation of the register offset and byte masks */
mega64 146:03e976389d16 682 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
mega64 146:03e976389d16 683 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
mega64 146:03e976389d16 684 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
mega64 146:03e976389d16 685
mega64 146:03e976389d16 686
mega64 146:03e976389d16 687 /** \brief Enable External Interrupt
mega64 146:03e976389d16 688
mega64 146:03e976389d16 689 The function enables a device-specific interrupt in the NVIC interrupt controller.
mega64 146:03e976389d16 690
mega64 146:03e976389d16 691 \param [in] IRQn External interrupt number. Value cannot be negative.
mega64 146:03e976389d16 692 */
mega64 146:03e976389d16 693 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
mega64 146:03e976389d16 694 {
mega64 146:03e976389d16 695 NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
mega64 146:03e976389d16 696 }
mega64 146:03e976389d16 697
mega64 146:03e976389d16 698
mega64 146:03e976389d16 699 /** \brief Disable External Interrupt
mega64 146:03e976389d16 700
mega64 146:03e976389d16 701 The function disables a device-specific interrupt in the NVIC interrupt controller.
mega64 146:03e976389d16 702
mega64 146:03e976389d16 703 \param [in] IRQn External interrupt number. Value cannot be negative.
mega64 146:03e976389d16 704 */
mega64 146:03e976389d16 705 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
mega64 146:03e976389d16 706 {
mega64 146:03e976389d16 707 NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
mega64 146:03e976389d16 708 __DSB();
mega64 146:03e976389d16 709 __ISB();
mega64 146:03e976389d16 710 }
mega64 146:03e976389d16 711
mega64 146:03e976389d16 712
mega64 146:03e976389d16 713 /** \brief Get Pending Interrupt
mega64 146:03e976389d16 714
mega64 146:03e976389d16 715 The function reads the pending register in the NVIC and returns the pending bit
mega64 146:03e976389d16 716 for the specified interrupt.
mega64 146:03e976389d16 717
mega64 146:03e976389d16 718 \param [in] IRQn Interrupt number.
mega64 146:03e976389d16 719
mega64 146:03e976389d16 720 \return 0 Interrupt status is not pending.
mega64 146:03e976389d16 721 \return 1 Interrupt status is pending.
mega64 146:03e976389d16 722 */
mega64 146:03e976389d16 723 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
mega64 146:03e976389d16 724 {
mega64 146:03e976389d16 725 return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
mega64 146:03e976389d16 726 }
mega64 146:03e976389d16 727
mega64 146:03e976389d16 728
mega64 146:03e976389d16 729 /** \brief Set Pending Interrupt
mega64 146:03e976389d16 730
mega64 146:03e976389d16 731 The function sets the pending bit of an external interrupt.
mega64 146:03e976389d16 732
mega64 146:03e976389d16 733 \param [in] IRQn Interrupt number. Value cannot be negative.
mega64 146:03e976389d16 734 */
mega64 146:03e976389d16 735 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
mega64 146:03e976389d16 736 {
mega64 146:03e976389d16 737 NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
mega64 146:03e976389d16 738 }
mega64 146:03e976389d16 739
mega64 146:03e976389d16 740
mega64 146:03e976389d16 741 /** \brief Clear Pending Interrupt
mega64 146:03e976389d16 742
mega64 146:03e976389d16 743 The function clears the pending bit of an external interrupt.
mega64 146:03e976389d16 744
mega64 146:03e976389d16 745 \param [in] IRQn External interrupt number. Value cannot be negative.
mega64 146:03e976389d16 746 */
mega64 146:03e976389d16 747 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
mega64 146:03e976389d16 748 {
mega64 146:03e976389d16 749 NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
mega64 146:03e976389d16 750 }
mega64 146:03e976389d16 751
mega64 146:03e976389d16 752
mega64 146:03e976389d16 753 /** \brief Set Interrupt Priority
mega64 146:03e976389d16 754
mega64 146:03e976389d16 755 The function sets the priority of an interrupt.
mega64 146:03e976389d16 756
mega64 146:03e976389d16 757 \note The priority cannot be set for every core interrupt.
mega64 146:03e976389d16 758
mega64 146:03e976389d16 759 \param [in] IRQn Interrupt number.
mega64 146:03e976389d16 760 \param [in] priority Priority to set.
mega64 146:03e976389d16 761 */
mega64 146:03e976389d16 762 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
mega64 146:03e976389d16 763 {
mega64 146:03e976389d16 764 if((int32_t)(IRQn) < 0) {
mega64 146:03e976389d16 765 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
mega64 146:03e976389d16 766 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
mega64 146:03e976389d16 767 }
mega64 146:03e976389d16 768 else {
mega64 146:03e976389d16 769 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
mega64 146:03e976389d16 770 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
mega64 146:03e976389d16 771 }
mega64 146:03e976389d16 772 }
mega64 146:03e976389d16 773
mega64 146:03e976389d16 774
mega64 146:03e976389d16 775 /** \brief Get Interrupt Priority
mega64 146:03e976389d16 776
mega64 146:03e976389d16 777 The function reads the priority of an interrupt. The interrupt
mega64 146:03e976389d16 778 number can be positive to specify an external (device specific)
mega64 146:03e976389d16 779 interrupt, or negative to specify an internal (core) interrupt.
mega64 146:03e976389d16 780
mega64 146:03e976389d16 781
mega64 146:03e976389d16 782 \param [in] IRQn Interrupt number.
mega64 146:03e976389d16 783 \return Interrupt Priority. Value is aligned automatically to the implemented
mega64 146:03e976389d16 784 priority bits of the microcontroller.
mega64 146:03e976389d16 785 */
mega64 146:03e976389d16 786 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
mega64 146:03e976389d16 787 {
mega64 146:03e976389d16 788
mega64 146:03e976389d16 789 if((int32_t)(IRQn) < 0) {
mega64 146:03e976389d16 790 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
mega64 146:03e976389d16 791 }
mega64 146:03e976389d16 792 else {
mega64 146:03e976389d16 793 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
mega64 146:03e976389d16 794 }
mega64 146:03e976389d16 795 }
mega64 146:03e976389d16 796
mega64 146:03e976389d16 797
mega64 146:03e976389d16 798 /** \brief System Reset
mega64 146:03e976389d16 799
mega64 146:03e976389d16 800 The function initiates a system reset request to reset the MCU.
mega64 146:03e976389d16 801 */
mega64 146:03e976389d16 802 __STATIC_INLINE void NVIC_SystemReset(void)
mega64 146:03e976389d16 803 {
mega64 146:03e976389d16 804 __DSB(); /* Ensure all outstanding memory accesses included
mega64 146:03e976389d16 805 buffered write are completed before reset */
mega64 146:03e976389d16 806 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
mega64 146:03e976389d16 807 SCB_AIRCR_SYSRESETREQ_Msk);
mega64 146:03e976389d16 808 __DSB(); /* Ensure completion of memory access */
mega64 146:03e976389d16 809 while(1) { __NOP(); } /* wait until reset */
mega64 146:03e976389d16 810 }
mega64 146:03e976389d16 811
mega64 146:03e976389d16 812 /*@} end of CMSIS_Core_NVICFunctions */
mega64 146:03e976389d16 813
mega64 146:03e976389d16 814
mega64 146:03e976389d16 815
mega64 146:03e976389d16 816 /* ################################## SysTick function ############################################ */
mega64 146:03e976389d16 817 /** \ingroup CMSIS_Core_FunctionInterface
mega64 146:03e976389d16 818 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
mega64 146:03e976389d16 819 \brief Functions that configure the System.
mega64 146:03e976389d16 820 @{
mega64 146:03e976389d16 821 */
mega64 146:03e976389d16 822
mega64 146:03e976389d16 823 #if (__Vendor_SysTickConfig == 0)
mega64 146:03e976389d16 824
mega64 146:03e976389d16 825 /** \brief System Tick Configuration
mega64 146:03e976389d16 826
mega64 146:03e976389d16 827 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
mega64 146:03e976389d16 828 Counter is in free running mode to generate periodic interrupts.
mega64 146:03e976389d16 829
mega64 146:03e976389d16 830 \param [in] ticks Number of ticks between two interrupts.
mega64 146:03e976389d16 831
mega64 146:03e976389d16 832 \return 0 Function succeeded.
mega64 146:03e976389d16 833 \return 1 Function failed.
mega64 146:03e976389d16 834
mega64 146:03e976389d16 835 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
mega64 146:03e976389d16 836 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
mega64 146:03e976389d16 837 must contain a vendor-specific implementation of this function.
mega64 146:03e976389d16 838
mega64 146:03e976389d16 839 */
mega64 146:03e976389d16 840 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
mega64 146:03e976389d16 841 {
mega64 146:03e976389d16 842 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);} /* Reload value impossible */
mega64 146:03e976389d16 843
mega64 146:03e976389d16 844 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
mega64 146:03e976389d16 845 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
mega64 146:03e976389d16 846 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
mega64 146:03e976389d16 847 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
mega64 146:03e976389d16 848 SysTick_CTRL_TICKINT_Msk |
mega64 146:03e976389d16 849 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
mega64 146:03e976389d16 850 return (0UL); /* Function successful */
mega64 146:03e976389d16 851 }
mega64 146:03e976389d16 852
mega64 146:03e976389d16 853 #endif
mega64 146:03e976389d16 854
mega64 146:03e976389d16 855 /*@} end of CMSIS_Core_SysTickFunctions */
mega64 146:03e976389d16 856
mega64 146:03e976389d16 857
mega64 146:03e976389d16 858
mega64 146:03e976389d16 859
mega64 146:03e976389d16 860 #ifdef __cplusplus
mega64 146:03e976389d16 861 }
mega64 146:03e976389d16 862 #endif
mega64 146:03e976389d16 863
mega64 146:03e976389d16 864 #endif /* __CORE_SC000_H_DEPENDANT */
mega64 146:03e976389d16 865
mega64 146:03e976389d16 866 #endif /* __CMSIS_GENERIC */