Nothing Special / mbed-STM32F103C8

Modification of Mbed-dev library for LQFP48 package microcontrollers: STM32F103C8 (STM32F103C8T6) and STM32F103CB (STM32F103CBT6) (Bluepill boards, Maple mini etc. )

Fork of mbed-STM32F103C8_org by Nothing Special

Library for STM32F103C8 (Bluepill boards etc.).
Use this instead of mbed library.
This library allows the size of the code in the FLASH up to 128kB. Therefore, code also runs on microcontrollers STM32F103CB (eg. Maple mini).
But in the case of STM32F103C8, check the size of the resulting code would not exceed 64kB.

To compile a program with this library, use NUCLEO-F103RB as the target name. !

Changes:

  • Corrected initialization of the HSE + crystal clock (mbed permanent bug), allowing the use of on-board xtal (8MHz).(1)
  • Additionally, it also set USB clock (48Mhz).(2)
  • Definitions of pins and peripherals adjusted to LQFP48 case.
  • Board led LED1 is now PC_13 (3)
  • USER_BUTTON is now PC_14 (4)

    Now the library is complete rebuilt based on mbed-dev v160 (and not yet fully tested).

notes
(1) - In case 8MHz xtal on board, CPU frequency is 72MHz. Without xtal is 64MHz.
(2) - Using the USB interface is only possible if STM32 is clocking by on-board 8MHz xtal or external clock signal 8MHz on the OSC_IN pin.
(3) - On Bluepill board led operation is reversed, i.e. 0 - led on, 1 - led off.
(4) - Bluepill board has no real user button

Information

After export to SW4STM (AC6):

  • add line #include "mbed_config.h" in files Serial.h and RawSerial.h
  • in project properties change Optimisation Level to Optimise for size (-Os)

cmsis/core_cmSimd.h@148:8b0b02bf146f, 2017-04-27 (annotated)

Committer:
mega64
Date:
Thu Apr 27 23:56:38 2017 +0000
Revision:
148:8b0b02bf146f
Parent:
146:03e976389d16 
Remove unnecessary folders

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mega64 146:03e976389d16 1 /**************************************************************************//**
mega64 146:03e976389d16 2 * @file core_cmSimd.h
mega64 146:03e976389d16 3 * @brief CMSIS Cortex-M SIMD Header File
mega64 146:03e976389d16 4 * @version V4.10
mega64 146:03e976389d16 5 * @date 18. March 2015
mega64 146:03e976389d16 6 *
mega64 146:03e976389d16 7 * @note
mega64 146:03e976389d16 8 *
mega64 146:03e976389d16 9 ******************************************************************************/
mega64 146:03e976389d16 10 /* Copyright (c) 2009 - 2014 ARM LIMITED
mega64 146:03e976389d16 11
mega64 146:03e976389d16 12 All rights reserved.
mega64 146:03e976389d16 13 Redistribution and use in source and binary forms, with or without
mega64 146:03e976389d16 14 modification, are permitted provided that the following conditions are met:
mega64 146:03e976389d16 15 - Redistributions of source code must retain the above copyright
mega64 146:03e976389d16 16 notice, this list of conditions and the following disclaimer.
mega64 146:03e976389d16 17 - Redistributions in binary form must reproduce the above copyright
mega64 146:03e976389d16 18 notice, this list of conditions and the following disclaimer in the
mega64 146:03e976389d16 19 documentation and/or other materials provided with the distribution.
mega64 146:03e976389d16 20 - Neither the name of ARM nor the names of its contributors may be used
mega64 146:03e976389d16 21 to endorse or promote products derived from this software without
mega64 146:03e976389d16 22 specific prior written permission.
mega64 146:03e976389d16 23 *
mega64 146:03e976389d16 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mega64 146:03e976389d16 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mega64 146:03e976389d16 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
mega64 146:03e976389d16 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
mega64 146:03e976389d16 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
mega64 146:03e976389d16 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
mega64 146:03e976389d16 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mega64 146:03e976389d16 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mega64 146:03e976389d16 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
mega64 146:03e976389d16 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mega64 146:03e976389d16 34 POSSIBILITY OF SUCH DAMAGE.
mega64 146:03e976389d16 35 ---------------------------------------------------------------------------*/
mega64 146:03e976389d16 36
mega64 146:03e976389d16 37
mega64 146:03e976389d16 38 #if defined ( __ICCARM__ )
mega64 146:03e976389d16 39 #pragma system_include /* treat file as system include file for MISRA check */
mega64 146:03e976389d16 40 #endif
mega64 146:03e976389d16 41
mega64 146:03e976389d16 42 #ifndef __CORE_CMSIMD_H
mega64 146:03e976389d16 43 #define __CORE_CMSIMD_H
mega64 146:03e976389d16 44
mega64 146:03e976389d16 45 #ifdef __cplusplus
mega64 146:03e976389d16 46 extern "C" {
mega64 146:03e976389d16 47 #endif
mega64 146:03e976389d16 48
mega64 146:03e976389d16 49
mega64 146:03e976389d16 50 /*******************************************************************************
mega64 146:03e976389d16 51 * Hardware Abstraction Layer
mega64 146:03e976389d16 52 ******************************************************************************/
mega64 146:03e976389d16 53
mega64 146:03e976389d16 54
mega64 146:03e976389d16 55 /* ################### Compiler specific Intrinsics ########################### */
mega64 146:03e976389d16 56 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
mega64 146:03e976389d16 57 Access to dedicated SIMD instructions
mega64 146:03e976389d16 58 @{
mega64 146:03e976389d16 59 */
mega64 146:03e976389d16 60
mega64 146:03e976389d16 61 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
mega64 146:03e976389d16 62 /* ARM armcc specific functions */
mega64 146:03e976389d16 63 #define __SADD8 __sadd8
mega64 146:03e976389d16 64 #define __QADD8 __qadd8
mega64 146:03e976389d16 65 #define __SHADD8 __shadd8
mega64 146:03e976389d16 66 #define __UADD8 __uadd8
mega64 146:03e976389d16 67 #define __UQADD8 __uqadd8
mega64 146:03e976389d16 68 #define __UHADD8 __uhadd8
mega64 146:03e976389d16 69 #define __SSUB8 __ssub8
mega64 146:03e976389d16 70 #define __QSUB8 __qsub8
mega64 146:03e976389d16 71 #define __SHSUB8 __shsub8
mega64 146:03e976389d16 72 #define __USUB8 __usub8
mega64 146:03e976389d16 73 #define __UQSUB8 __uqsub8
mega64 146:03e976389d16 74 #define __UHSUB8 __uhsub8
mega64 146:03e976389d16 75 #define __SADD16 __sadd16
mega64 146:03e976389d16 76 #define __QADD16 __qadd16
mega64 146:03e976389d16 77 #define __SHADD16 __shadd16
mega64 146:03e976389d16 78 #define __UADD16 __uadd16
mega64 146:03e976389d16 79 #define __UQADD16 __uqadd16
mega64 146:03e976389d16 80 #define __UHADD16 __uhadd16
mega64 146:03e976389d16 81 #define __SSUB16 __ssub16
mega64 146:03e976389d16 82 #define __QSUB16 __qsub16
mega64 146:03e976389d16 83 #define __SHSUB16 __shsub16
mega64 146:03e976389d16 84 #define __USUB16 __usub16
mega64 146:03e976389d16 85 #define __UQSUB16 __uqsub16
mega64 146:03e976389d16 86 #define __UHSUB16 __uhsub16
mega64 146:03e976389d16 87 #define __SASX __sasx
mega64 146:03e976389d16 88 #define __QASX __qasx
mega64 146:03e976389d16 89 #define __SHASX __shasx
mega64 146:03e976389d16 90 #define __UASX __uasx
mega64 146:03e976389d16 91 #define __UQASX __uqasx
mega64 146:03e976389d16 92 #define __UHASX __uhasx
mega64 146:03e976389d16 93 #define __SSAX __ssax
mega64 146:03e976389d16 94 #define __QSAX __qsax
mega64 146:03e976389d16 95 #define __SHSAX __shsax
mega64 146:03e976389d16 96 #define __USAX __usax
mega64 146:03e976389d16 97 #define __UQSAX __uqsax
mega64 146:03e976389d16 98 #define __UHSAX __uhsax
mega64 146:03e976389d16 99 #define __USAD8 __usad8
mega64 146:03e976389d16 100 #define __USADA8 __usada8
mega64 146:03e976389d16 101 #define __SSAT16 __ssat16
mega64 146:03e976389d16 102 #define __USAT16 __usat16
mega64 146:03e976389d16 103 #define __UXTB16 __uxtb16
mega64 146:03e976389d16 104 #define __UXTAB16 __uxtab16
mega64 146:03e976389d16 105 #define __SXTB16 __sxtb16
mega64 146:03e976389d16 106 #define __SXTAB16 __sxtab16
mega64 146:03e976389d16 107 #define __SMUAD __smuad
mega64 146:03e976389d16 108 #define __SMUADX __smuadx
mega64 146:03e976389d16 109 #define __SMLAD __smlad
mega64 146:03e976389d16 110 #define __SMLADX __smladx
mega64 146:03e976389d16 111 #define __SMLALD __smlald
mega64 146:03e976389d16 112 #define __SMLALDX __smlaldx
mega64 146:03e976389d16 113 #define __SMUSD __smusd
mega64 146:03e976389d16 114 #define __SMUSDX __smusdx
mega64 146:03e976389d16 115 #define __SMLSD __smlsd
mega64 146:03e976389d16 116 #define __SMLSDX __smlsdx
mega64 146:03e976389d16 117 #define __SMLSLD __smlsld
mega64 146:03e976389d16 118 #define __SMLSLDX __smlsldx
mega64 146:03e976389d16 119 #define __SEL __sel
mega64 146:03e976389d16 120 #define __QADD __qadd
mega64 146:03e976389d16 121 #define __QSUB __qsub
mega64 146:03e976389d16 122
mega64 146:03e976389d16 123 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
mega64 146:03e976389d16 124 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
mega64 146:03e976389d16 125
mega64 146:03e976389d16 126 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
mega64 146:03e976389d16 127 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
mega64 146:03e976389d16 128
mega64 146:03e976389d16 129 #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
mega64 146:03e976389d16 130 ((int64_t)(ARG3) << 32) ) >> 32))
mega64 146:03e976389d16 131
mega64 146:03e976389d16 132
mega64 146:03e976389d16 133 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
mega64 146:03e976389d16 134 /* GNU gcc specific functions */
mega64 146:03e976389d16 135 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
mega64 146:03e976389d16 136 {
mega64 146:03e976389d16 137 uint32_t result;
mega64 146:03e976389d16 138
mega64 146:03e976389d16 139 __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mega64 146:03e976389d16 140 return(result);
mega64 146:03e976389d16 141 }
mega64 146:03e976389d16 142
mega64 146:03e976389d16 143 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
mega64 146:03e976389d16 144 {
mega64 146:03e976389d16 145 uint32_t result;
mega64 146:03e976389d16 146
mega64 146:03e976389d16 147 __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mega64 146:03e976389d16 148 return(result);
mega64 146:03e976389d16 149 }
mega64 146:03e976389d16 150
mega64 146:03e976389d16 151 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
mega64 146:03e976389d16 152 {
mega64 146:03e976389d16 153 uint32_t result;
mega64 146:03e976389d16 154
mega64 146:03e976389d16 155 __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mega64 146:03e976389d16 156 return(result);
mega64 146:03e976389d16 157 }
mega64 146:03e976389d16 158
mega64 146:03e976389d16 159 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
mega64 146:03e976389d16 160 {
mega64 146:03e976389d16 161 uint32_t result;
mega64 146:03e976389d16 162
mega64 146:03e976389d16 163 __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mega64 146:03e976389d16 164 return(result);
mega64 146:03e976389d16 165 }
mega64 146:03e976389d16 166
mega64 146:03e976389d16 167 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
mega64 146:03e976389d16 168 {
mega64 146:03e976389d16 169 uint32_t result;
mega64 146:03e976389d16 170
mega64 146:03e976389d16 171 __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mega64 146:03e976389d16 172 return(result);
mega64 146:03e976389d16 173 }
mega64 146:03e976389d16 174
mega64 146:03e976389d16 175 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
mega64 146:03e976389d16 176 {
mega64 146:03e976389d16 177 uint32_t result;
mega64 146:03e976389d16 178
mega64 146:03e976389d16 179 __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mega64 146:03e976389d16 180 return(result);
mega64 146:03e976389d16 181 }
mega64 146:03e976389d16 182
mega64 146:03e976389d16 183
mega64 146:03e976389d16 184 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
mega64 146:03e976389d16 185 {
mega64 146:03e976389d16 186 uint32_t result;
mega64 146:03e976389d16 187
mega64 146:03e976389d16 188 __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mega64 146:03e976389d16 189 return(result);
mega64 146:03e976389d16 190 }
mega64 146:03e976389d16 191
mega64 146:03e976389d16 192 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
mega64 146:03e976389d16 193 {
mega64 146:03e976389d16 194 uint32_t result;
mega64 146:03e976389d16 195
mega64 146:03e976389d16 196 __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mega64 146:03e976389d16 197 return(result);
mega64 146:03e976389d16 198 }
mega64 146:03e976389d16 199
mega64 146:03e976389d16 200 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
mega64 146:03e976389d16 201 {
mega64 146:03e976389d16 202 uint32_t result;
mega64 146:03e976389d16 203
mega64 146:03e976389d16 204 __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mega64 146:03e976389d16 205 return(result);
mega64 146:03e976389d16 206 }
mega64 146:03e976389d16 207
mega64 146:03e976389d16 208 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
mega64 146:03e976389d16 209 {
mega64 146:03e976389d16 210 uint32_t result;
mega64 146:03e976389d16 211
mega64 146:03e976389d16 212 __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mega64 146:03e976389d16 213 return(result);
mega64 146:03e976389d16 214 }
mega64 146:03e976389d16 215
mega64 146:03e976389d16 216 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
mega64 146:03e976389d16 217 {
mega64 146:03e976389d16 218 uint32_t result;
mega64 146:03e976389d16 219
mega64 146:03e976389d16 220 __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mega64 146:03e976389d16 221 return(result);
mega64 146:03e976389d16 222 }
mega64 146:03e976389d16 223
mega64 146:03e976389d16 224 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
mega64 146:03e976389d16 225 {
mega64 146:03e976389d16 226 uint32_t result;
mega64 146:03e976389d16 227
mega64 146:03e976389d16 228 __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mega64 146:03e976389d16 229 return(result);
mega64 146:03e976389d16 230 }
mega64 146:03e976389d16 231
mega64 146:03e976389d16 232
mega64 146:03e976389d16 233 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
mega64 146:03e976389d16 234 {
mega64 146:03e976389d16 235 uint32_t result;
mega64 146:03e976389d16 236
mega64 146:03e976389d16 237 __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mega64 146:03e976389d16 238 return(result);
mega64 146:03e976389d16 239 }
mega64 146:03e976389d16 240
mega64 146:03e976389d16 241 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
mega64 146:03e976389d16 242 {
mega64 146:03e976389d16 243 uint32_t result;
mega64 146:03e976389d16 244
mega64 146:03e976389d16 245 __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mega64 146:03e976389d16 246 return(result);
mega64 146:03e976389d16 247 }
mega64 146:03e976389d16 248
mega64 146:03e976389d16 249 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
mega64 146:03e976389d16 250 {
mega64 146:03e976389d16 251 uint32_t result;
mega64 146:03e976389d16 252
mega64 146:03e976389d16 253 __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mega64 146:03e976389d16 254 return(result);
mega64 146:03e976389d16 255 }
mega64 146:03e976389d16 256
mega64 146:03e976389d16 257 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
mega64 146:03e976389d16 258 {
mega64 146:03e976389d16 259 uint32_t result;
mega64 146:03e976389d16 260
mega64 146:03e976389d16 261 __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mega64 146:03e976389d16 262 return(result);
mega64 146:03e976389d16 263 }
mega64 146:03e976389d16 264
mega64 146:03e976389d16 265 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
mega64 146:03e976389d16 266 {
mega64 146:03e976389d16 267 uint32_t result;
mega64 146:03e976389d16 268
mega64 146:03e976389d16 269 __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mega64 146:03e976389d16 270 return(result);
mega64 146:03e976389d16 271 }
mega64 146:03e976389d16 272
mega64 146:03e976389d16 273 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
mega64 146:03e976389d16 274 {
mega64 146:03e976389d16 275 uint32_t result;
mega64 146:03e976389d16 276
mega64 146:03e976389d16 277 __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mega64 146:03e976389d16 278 return(result);
mega64 146:03e976389d16 279 }
mega64 146:03e976389d16 280
mega64 146:03e976389d16 281 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
mega64 146:03e976389d16 282 {
mega64 146:03e976389d16 283 uint32_t result;
mega64 146:03e976389d16 284
mega64 146:03e976389d16 285 __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mega64 146:03e976389d16 286 return(result);
mega64 146:03e976389d16 287 }
mega64 146:03e976389d16 288
mega64 146:03e976389d16 289 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
mega64 146:03e976389d16 290 {
mega64 146:03e976389d16 291 uint32_t result;
mega64 146:03e976389d16 292
mega64 146:03e976389d16 293 __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mega64 146:03e976389d16 294 return(result);
mega64 146:03e976389d16 295 }
mega64 146:03e976389d16 296
mega64 146:03e976389d16 297 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
mega64 146:03e976389d16 298 {
mega64 146:03e976389d16 299 uint32_t result;
mega64 146:03e976389d16 300
mega64 146:03e976389d16 301 __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mega64 146:03e976389d16 302 return(result);
mega64 146:03e976389d16 303 }
mega64 146:03e976389d16 304
mega64 146:03e976389d16 305 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
mega64 146:03e976389d16 306 {
mega64 146:03e976389d16 307 uint32_t result;
mega64 146:03e976389d16 308
mega64 146:03e976389d16 309 __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mega64 146:03e976389d16 310 return(result);
mega64 146:03e976389d16 311 }
mega64 146:03e976389d16 312
mega64 146:03e976389d16 313 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
mega64 146:03e976389d16 314 {
mega64 146:03e976389d16 315 uint32_t result;
mega64 146:03e976389d16 316
mega64 146:03e976389d16 317 __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mega64 146:03e976389d16 318 return(result);
mega64 146:03e976389d16 319 }
mega64 146:03e976389d16 320
mega64 146:03e976389d16 321 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
mega64 146:03e976389d16 322 {
mega64 146:03e976389d16 323 uint32_t result;
mega64 146:03e976389d16 324
mega64 146:03e976389d16 325 __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mega64 146:03e976389d16 326 return(result);
mega64 146:03e976389d16 327 }
mega64 146:03e976389d16 328
mega64 146:03e976389d16 329 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
mega64 146:03e976389d16 330 {
mega64 146:03e976389d16 331 uint32_t result;
mega64 146:03e976389d16 332
mega64 146:03e976389d16 333 __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mega64 146:03e976389d16 334 return(result);
mega64 146:03e976389d16 335 }
mega64 146:03e976389d16 336
mega64 146:03e976389d16 337 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
mega64 146:03e976389d16 338 {
mega64 146:03e976389d16 339 uint32_t result;
mega64 146:03e976389d16 340
mega64 146:03e976389d16 341 __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mega64 146:03e976389d16 342 return(result);
mega64 146:03e976389d16 343 }
mega64 146:03e976389d16 344
mega64 146:03e976389d16 345 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
mega64 146:03e976389d16 346 {
mega64 146:03e976389d16 347 uint32_t result;
mega64 146:03e976389d16 348
mega64 146:03e976389d16 349 __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mega64 146:03e976389d16 350 return(result);
mega64 146:03e976389d16 351 }
mega64 146:03e976389d16 352
mega64 146:03e976389d16 353 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
mega64 146:03e976389d16 354 {
mega64 146:03e976389d16 355 uint32_t result;
mega64 146:03e976389d16 356
mega64 146:03e976389d16 357 __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mega64 146:03e976389d16 358 return(result);
mega64 146:03e976389d16 359 }
mega64 146:03e976389d16 360
mega64 146:03e976389d16 361 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
mega64 146:03e976389d16 362 {
mega64 146:03e976389d16 363 uint32_t result;
mega64 146:03e976389d16 364
mega64 146:03e976389d16 365 __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mega64 146:03e976389d16 366 return(result);
mega64 146:03e976389d16 367 }
mega64 146:03e976389d16 368
mega64 146:03e976389d16 369 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
mega64 146:03e976389d16 370 {
mega64 146:03e976389d16 371 uint32_t result;
mega64 146:03e976389d16 372
mega64 146:03e976389d16 373 __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mega64 146:03e976389d16 374 return(result);
mega64 146:03e976389d16 375 }
mega64 146:03e976389d16 376
mega64 146:03e976389d16 377 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
mega64 146:03e976389d16 378 {
mega64 146:03e976389d16 379 uint32_t result;
mega64 146:03e976389d16 380
mega64 146:03e976389d16 381 __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mega64 146:03e976389d16 382 return(result);
mega64 146:03e976389d16 383 }
mega64 146:03e976389d16 384
mega64 146:03e976389d16 385 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
mega64 146:03e976389d16 386 {
mega64 146:03e976389d16 387 uint32_t result;
mega64 146:03e976389d16 388
mega64 146:03e976389d16 389 __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mega64 146:03e976389d16 390 return(result);
mega64 146:03e976389d16 391 }
mega64 146:03e976389d16 392
mega64 146:03e976389d16 393 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
mega64 146:03e976389d16 394 {
mega64 146:03e976389d16 395 uint32_t result;
mega64 146:03e976389d16 396
mega64 146:03e976389d16 397 __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mega64 146:03e976389d16 398 return(result);
mega64 146:03e976389d16 399 }
mega64 146:03e976389d16 400
mega64 146:03e976389d16 401 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
mega64 146:03e976389d16 402 {
mega64 146:03e976389d16 403 uint32_t result;
mega64 146:03e976389d16 404
mega64 146:03e976389d16 405 __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mega64 146:03e976389d16 406 return(result);
mega64 146:03e976389d16 407 }
mega64 146:03e976389d16 408
mega64 146:03e976389d16 409 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
mega64 146:03e976389d16 410 {
mega64 146:03e976389d16 411 uint32_t result;
mega64 146:03e976389d16 412
mega64 146:03e976389d16 413 __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mega64 146:03e976389d16 414 return(result);
mega64 146:03e976389d16 415 }
mega64 146:03e976389d16 416
mega64 146:03e976389d16 417 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
mega64 146:03e976389d16 418 {
mega64 146:03e976389d16 419 uint32_t result;
mega64 146:03e976389d16 420
mega64 146:03e976389d16 421 __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mega64 146:03e976389d16 422 return(result);
mega64 146:03e976389d16 423 }
mega64 146:03e976389d16 424
mega64 146:03e976389d16 425 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
mega64 146:03e976389d16 426 {
mega64 146:03e976389d16 427 uint32_t result;
mega64 146:03e976389d16 428
mega64 146:03e976389d16 429 __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mega64 146:03e976389d16 430 return(result);
mega64 146:03e976389d16 431 }
mega64 146:03e976389d16 432
mega64 146:03e976389d16 433 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
mega64 146:03e976389d16 434 {
mega64 146:03e976389d16 435 uint32_t result;
mega64 146:03e976389d16 436
mega64 146:03e976389d16 437 __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
mega64 146:03e976389d16 438 return(result);
mega64 146:03e976389d16 439 }
mega64 146:03e976389d16 440
mega64 146:03e976389d16 441 #define __SSAT16(ARG1,ARG2) \
mega64 146:03e976389d16 442 ({ \
mega64 146:03e976389d16 443 uint32_t __RES, __ARG1 = (ARG1); \
mega64 146:03e976389d16 444 __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
mega64 146:03e976389d16 445 __RES; \
mega64 146:03e976389d16 446 })
mega64 146:03e976389d16 447
mega64 146:03e976389d16 448 #define __USAT16(ARG1,ARG2) \
mega64 146:03e976389d16 449 ({ \
mega64 146:03e976389d16 450 uint32_t __RES, __ARG1 = (ARG1); \
mega64 146:03e976389d16 451 __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
mega64 146:03e976389d16 452 __RES; \
mega64 146:03e976389d16 453 })
mega64 146:03e976389d16 454
mega64 146:03e976389d16 455 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
mega64 146:03e976389d16 456 {
mega64 146:03e976389d16 457 uint32_t result;
mega64 146:03e976389d16 458
mega64 146:03e976389d16 459 __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
mega64 146:03e976389d16 460 return(result);
mega64 146:03e976389d16 461 }
mega64 146:03e976389d16 462
mega64 146:03e976389d16 463 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
mega64 146:03e976389d16 464 {
mega64 146:03e976389d16 465 uint32_t result;
mega64 146:03e976389d16 466
mega64 146:03e976389d16 467 __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mega64 146:03e976389d16 468 return(result);
mega64 146:03e976389d16 469 }
mega64 146:03e976389d16 470
mega64 146:03e976389d16 471 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
mega64 146:03e976389d16 472 {
mega64 146:03e976389d16 473 uint32_t result;
mega64 146:03e976389d16 474
mega64 146:03e976389d16 475 __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
mega64 146:03e976389d16 476 return(result);
mega64 146:03e976389d16 477 }
mega64 146:03e976389d16 478
mega64 146:03e976389d16 479 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
mega64 146:03e976389d16 480 {
mega64 146:03e976389d16 481 uint32_t result;
mega64 146:03e976389d16 482
mega64 146:03e976389d16 483 __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mega64 146:03e976389d16 484 return(result);
mega64 146:03e976389d16 485 }
mega64 146:03e976389d16 486
mega64 146:03e976389d16 487 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
mega64 146:03e976389d16 488 {
mega64 146:03e976389d16 489 uint32_t result;
mega64 146:03e976389d16 490
mega64 146:03e976389d16 491 __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mega64 146:03e976389d16 492 return(result);
mega64 146:03e976389d16 493 }
mega64 146:03e976389d16 494
mega64 146:03e976389d16 495 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
mega64 146:03e976389d16 496 {
mega64 146:03e976389d16 497 uint32_t result;
mega64 146:03e976389d16 498
mega64 146:03e976389d16 499 __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mega64 146:03e976389d16 500 return(result);
mega64 146:03e976389d16 501 }
mega64 146:03e976389d16 502
mega64 146:03e976389d16 503 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
mega64 146:03e976389d16 504 {
mega64 146:03e976389d16 505 uint32_t result;
mega64 146:03e976389d16 506
mega64 146:03e976389d16 507 __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
mega64 146:03e976389d16 508 return(result);
mega64 146:03e976389d16 509 }
mega64 146:03e976389d16 510
mega64 146:03e976389d16 511 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
mega64 146:03e976389d16 512 {
mega64 146:03e976389d16 513 uint32_t result;
mega64 146:03e976389d16 514
mega64 146:03e976389d16 515 __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
mega64 146:03e976389d16 516 return(result);
mega64 146:03e976389d16 517 }
mega64 146:03e976389d16 518
mega64 146:03e976389d16 519 __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
mega64 146:03e976389d16 520 {
mega64 146:03e976389d16 521 union llreg_u{
mega64 146:03e976389d16 522 uint32_t w32[2];
mega64 146:03e976389d16 523 uint64_t w64;
mega64 146:03e976389d16 524 } llr;
mega64 146:03e976389d16 525 llr.w64 = acc;
mega64 146:03e976389d16 526
mega64 146:03e976389d16 527 #ifndef __ARMEB__ // Little endian
mega64 146:03e976389d16 528 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
mega64 146:03e976389d16 529 #else // Big endian
mega64 146:03e976389d16 530 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
mega64 146:03e976389d16 531 #endif
mega64 146:03e976389d16 532
mega64 146:03e976389d16 533 return(llr.w64);
mega64 146:03e976389d16 534 }
mega64 146:03e976389d16 535
mega64 146:03e976389d16 536 __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
mega64 146:03e976389d16 537 {
mega64 146:03e976389d16 538 union llreg_u{
mega64 146:03e976389d16 539 uint32_t w32[2];
mega64 146:03e976389d16 540 uint64_t w64;
mega64 146:03e976389d16 541 } llr;
mega64 146:03e976389d16 542 llr.w64 = acc;
mega64 146:03e976389d16 543
mega64 146:03e976389d16 544 #ifndef __ARMEB__ // Little endian
mega64 146:03e976389d16 545 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
mega64 146:03e976389d16 546 #else // Big endian
mega64 146:03e976389d16 547 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
mega64 146:03e976389d16 548 #endif
mega64 146:03e976389d16 549
mega64 146:03e976389d16 550 return(llr.w64);
mega64 146:03e976389d16 551 }
mega64 146:03e976389d16 552
mega64 146:03e976389d16 553 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
mega64 146:03e976389d16 554 {
mega64 146:03e976389d16 555 uint32_t result;
mega64 146:03e976389d16 556
mega64 146:03e976389d16 557 __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mega64 146:03e976389d16 558 return(result);
mega64 146:03e976389d16 559 }
mega64 146:03e976389d16 560
mega64 146:03e976389d16 561 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
mega64 146:03e976389d16 562 {
mega64 146:03e976389d16 563 uint32_t result;
mega64 146:03e976389d16 564
mega64 146:03e976389d16 565 __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mega64 146:03e976389d16 566 return(result);
mega64 146:03e976389d16 567 }
mega64 146:03e976389d16 568
mega64 146:03e976389d16 569 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
mega64 146:03e976389d16 570 {
mega64 146:03e976389d16 571 uint32_t result;
mega64 146:03e976389d16 572
mega64 146:03e976389d16 573 __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
mega64 146:03e976389d16 574 return(result);
mega64 146:03e976389d16 575 }
mega64 146:03e976389d16 576
mega64 146:03e976389d16 577 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
mega64 146:03e976389d16 578 {
mega64 146:03e976389d16 579 uint32_t result;
mega64 146:03e976389d16 580
mega64 146:03e976389d16 581 __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
mega64 146:03e976389d16 582 return(result);
mega64 146:03e976389d16 583 }
mega64 146:03e976389d16 584
mega64 146:03e976389d16 585 __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
mega64 146:03e976389d16 586 {
mega64 146:03e976389d16 587 union llreg_u{
mega64 146:03e976389d16 588 uint32_t w32[2];
mega64 146:03e976389d16 589 uint64_t w64;
mega64 146:03e976389d16 590 } llr;
mega64 146:03e976389d16 591 llr.w64 = acc;
mega64 146:03e976389d16 592
mega64 146:03e976389d16 593 #ifndef __ARMEB__ // Little endian
mega64 146:03e976389d16 594 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
mega64 146:03e976389d16 595 #else // Big endian
mega64 146:03e976389d16 596 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
mega64 146:03e976389d16 597 #endif
mega64 146:03e976389d16 598
mega64 146:03e976389d16 599 return(llr.w64);
mega64 146:03e976389d16 600 }
mega64 146:03e976389d16 601
mega64 146:03e976389d16 602 __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
mega64 146:03e976389d16 603 {
mega64 146:03e976389d16 604 union llreg_u{
mega64 146:03e976389d16 605 uint32_t w32[2];
mega64 146:03e976389d16 606 uint64_t w64;
mega64 146:03e976389d16 607 } llr;
mega64 146:03e976389d16 608 llr.w64 = acc;
mega64 146:03e976389d16 609
mega64 146:03e976389d16 610 #ifndef __ARMEB__ // Little endian
mega64 146:03e976389d16 611 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
mega64 146:03e976389d16 612 #else // Big endian
mega64 146:03e976389d16 613 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
mega64 146:03e976389d16 614 #endif
mega64 146:03e976389d16 615
mega64 146:03e976389d16 616 return(llr.w64);
mega64 146:03e976389d16 617 }
mega64 146:03e976389d16 618
mega64 146:03e976389d16 619 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
mega64 146:03e976389d16 620 {
mega64 146:03e976389d16 621 uint32_t result;
mega64 146:03e976389d16 622
mega64 146:03e976389d16 623 __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mega64 146:03e976389d16 624 return(result);
mega64 146:03e976389d16 625 }
mega64 146:03e976389d16 626
mega64 146:03e976389d16 627 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
mega64 146:03e976389d16 628 {
mega64 146:03e976389d16 629 uint32_t result;
mega64 146:03e976389d16 630
mega64 146:03e976389d16 631 __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mega64 146:03e976389d16 632 return(result);
mega64 146:03e976389d16 633 }
mega64 146:03e976389d16 634
mega64 146:03e976389d16 635 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
mega64 146:03e976389d16 636 {
mega64 146:03e976389d16 637 uint32_t result;
mega64 146:03e976389d16 638
mega64 146:03e976389d16 639 __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mega64 146:03e976389d16 640 return(result);
mega64 146:03e976389d16 641 }
mega64 146:03e976389d16 642
mega64 146:03e976389d16 643 #define __PKHBT(ARG1,ARG2,ARG3) \
mega64 146:03e976389d16 644 ({ \
mega64 146:03e976389d16 645 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
mega64 146:03e976389d16 646 __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
mega64 146:03e976389d16 647 __RES; \
mega64 146:03e976389d16 648 })
mega64 146:03e976389d16 649
mega64 146:03e976389d16 650 #define __PKHTB(ARG1,ARG2,ARG3) \
mega64 146:03e976389d16 651 ({ \
mega64 146:03e976389d16 652 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
mega64 146:03e976389d16 653 if (ARG3 == 0) \
mega64 146:03e976389d16 654 __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
mega64 146:03e976389d16 655 else \
mega64 146:03e976389d16 656 __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
mega64 146:03e976389d16 657 __RES; \
mega64 146:03e976389d16 658 })
mega64 146:03e976389d16 659
mega64 146:03e976389d16 660 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
mega64 146:03e976389d16 661 {
mega64 146:03e976389d16 662 int32_t result;
mega64 146:03e976389d16 663
mega64 146:03e976389d16 664 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
mega64 146:03e976389d16 665 return(result);
mega64 146:03e976389d16 666 }
mega64 146:03e976389d16 667
mega64 146:03e976389d16 668
mega64 146:03e976389d16 669 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
mega64 146:03e976389d16 670 /* IAR iccarm specific functions */
mega64 146:03e976389d16 671 #include <cmsis_iar.h>
mega64 146:03e976389d16 672
mega64 146:03e976389d16 673
mega64 146:03e976389d16 674 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
mega64 146:03e976389d16 675 /* TI CCS specific functions */
mega64 146:03e976389d16 676 #include <cmsis_ccs.h>
mega64 146:03e976389d16 677
mega64 146:03e976389d16 678
mega64 146:03e976389d16 679 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
mega64 146:03e976389d16 680 /* TASKING carm specific functions */
mega64 146:03e976389d16 681 /* not yet supported */
mega64 146:03e976389d16 682
mega64 146:03e976389d16 683
mega64 146:03e976389d16 684 #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
mega64 146:03e976389d16 685 /* Cosmic specific functions */
mega64 146:03e976389d16 686 #include <cmsis_csm.h>
mega64 146:03e976389d16 687
mega64 146:03e976389d16 688 #endif
mega64 146:03e976389d16 689
mega64 146:03e976389d16 690 /*@} end of group CMSIS_SIMD_intrinsics */
mega64 146:03e976389d16 691
mega64 146:03e976389d16 692
mega64 146:03e976389d16 693 #ifdef __cplusplus
mega64 146:03e976389d16 694 }
mega64 146:03e976389d16 695 #endif
mega64 146:03e976389d16 696
mega64 146:03e976389d16 697 #endif /* __CORE_CMSIMD_H */