Nothing Special / mbed-STM32F103C8

Modification of Mbed-dev library for LQFP48 package microcontrollers: STM32F103C8 (STM32F103C8T6) and STM32F103CB (STM32F103CBT6) (Bluepill boards, Maple mini etc. )

Fork of mbed-STM32F103C8_org by Nothing Special

Library for STM32F103C8 (Bluepill boards etc.).
Use this instead of mbed library.
This library allows the size of the code in the FLASH up to 128kB. Therefore, code also runs on microcontrollers STM32F103CB (eg. Maple mini).
But in the case of STM32F103C8, check the size of the resulting code would not exceed 64kB.

To compile a program with this library, use NUCLEO-F103RB as the target name. !

Changes:

  • Corrected initialization of the HSE + crystal clock (mbed permanent bug), allowing the use of on-board xtal (8MHz).(1)
  • Additionally, it also set USB clock (48Mhz).(2)
  • Definitions of pins and peripherals adjusted to LQFP48 case.
  • Board led LED1 is now PC_13 (3)
  • USER_BUTTON is now PC_14 (4)

    Now the library is complete rebuilt based on mbed-dev v160 (and not yet fully tested).

notes
(1) - In case 8MHz xtal on board, CPU frequency is 72MHz. Without xtal is 64MHz.
(2) - Using the USB interface is only possible if STM32 is clocking by on-board 8MHz xtal or external clock signal 8MHz on the OSC_IN pin.
(3) - On Bluepill board led operation is reversed, i.e. 0 - led on, 1 - led off.
(4) - Bluepill board has no real user button

Information

After export to SW4STM (AC6):

  • add line #include "mbed_config.h" in files Serial.h and RawSerial.h
  • in project properties change Optimisation Level to Optimise for size (-Os)

cmsis/core_cmInstr.h@148:8b0b02bf146f, 2017-04-27 (annotated)

Committer:
mega64
Date:
Thu Apr 27 23:56:38 2017 +0000
Revision:
148:8b0b02bf146f
Parent:
146:03e976389d16 
Remove unnecessary folders

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mega64 146:03e976389d16 1 /**************************************************************************//**
mega64 146:03e976389d16 2 * @file core_cmInstr.h
mega64 146:03e976389d16 3 * @brief CMSIS Cortex-M Core Instruction Access Header File
mega64 146:03e976389d16 4 * @version V4.10
mega64 146:03e976389d16 5 * @date 18. March 2015
mega64 146:03e976389d16 6 *
mega64 146:03e976389d16 7 * @note
mega64 146:03e976389d16 8 *
mega64 146:03e976389d16 9 ******************************************************************************/
mega64 146:03e976389d16 10 /* Copyright (c) 2009 - 2014 ARM LIMITED
mega64 146:03e976389d16 11
mega64 146:03e976389d16 12 All rights reserved.
mega64 146:03e976389d16 13 Redistribution and use in source and binary forms, with or without
mega64 146:03e976389d16 14 modification, are permitted provided that the following conditions are met:
mega64 146:03e976389d16 15 - Redistributions of source code must retain the above copyright
mega64 146:03e976389d16 16 notice, this list of conditions and the following disclaimer.
mega64 146:03e976389d16 17 - Redistributions in binary form must reproduce the above copyright
mega64 146:03e976389d16 18 notice, this list of conditions and the following disclaimer in the
mega64 146:03e976389d16 19 documentation and/or other materials provided with the distribution.
mega64 146:03e976389d16 20 - Neither the name of ARM nor the names of its contributors may be used
mega64 146:03e976389d16 21 to endorse or promote products derived from this software without
mega64 146:03e976389d16 22 specific prior written permission.
mega64 146:03e976389d16 23 *
mega64 146:03e976389d16 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mega64 146:03e976389d16 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mega64 146:03e976389d16 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
mega64 146:03e976389d16 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
mega64 146:03e976389d16 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
mega64 146:03e976389d16 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
mega64 146:03e976389d16 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mega64 146:03e976389d16 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mega64 146:03e976389d16 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
mega64 146:03e976389d16 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mega64 146:03e976389d16 34 POSSIBILITY OF SUCH DAMAGE.
mega64 146:03e976389d16 35 ---------------------------------------------------------------------------*/
mega64 146:03e976389d16 36
mega64 146:03e976389d16 37
mega64 146:03e976389d16 38 #ifndef __CORE_CMINSTR_H
mega64 146:03e976389d16 39 #define __CORE_CMINSTR_H
mega64 146:03e976389d16 40
mega64 146:03e976389d16 41
mega64 146:03e976389d16 42 /* ########################## Core Instruction Access ######################### */
mega64 146:03e976389d16 43 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
mega64 146:03e976389d16 44 Access to dedicated instructions
mega64 146:03e976389d16 45 @{
mega64 146:03e976389d16 46 */
mega64 146:03e976389d16 47
mega64 146:03e976389d16 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
mega64 146:03e976389d16 49 /* ARM armcc specific functions */
mega64 146:03e976389d16 50
mega64 146:03e976389d16 51 #if (__ARMCC_VERSION < 400677)
mega64 146:03e976389d16 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
mega64 146:03e976389d16 53 #endif
mega64 146:03e976389d16 54
mega64 146:03e976389d16 55
mega64 146:03e976389d16 56 /** \brief No Operation
mega64 146:03e976389d16 57
mega64 146:03e976389d16 58 No Operation does nothing. This instruction can be used for code alignment purposes.
mega64 146:03e976389d16 59 */
mega64 146:03e976389d16 60 #define __NOP __nop
mega64 146:03e976389d16 61
mega64 146:03e976389d16 62
mega64 146:03e976389d16 63 /** \brief Wait For Interrupt
mega64 146:03e976389d16 64
mega64 146:03e976389d16 65 Wait For Interrupt is a hint instruction that suspends execution
mega64 146:03e976389d16 66 until one of a number of events occurs.
mega64 146:03e976389d16 67 */
mega64 146:03e976389d16 68 #define __WFI __wfi
mega64 146:03e976389d16 69
mega64 146:03e976389d16 70
mega64 146:03e976389d16 71 /** \brief Wait For Event
mega64 146:03e976389d16 72
mega64 146:03e976389d16 73 Wait For Event is a hint instruction that permits the processor to enter
mega64 146:03e976389d16 74 a low-power state until one of a number of events occurs.
mega64 146:03e976389d16 75 */
mega64 146:03e976389d16 76 #define __WFE __wfe
mega64 146:03e976389d16 77
mega64 146:03e976389d16 78
mega64 146:03e976389d16 79 /** \brief Send Event
mega64 146:03e976389d16 80
mega64 146:03e976389d16 81 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
mega64 146:03e976389d16 82 */
mega64 146:03e976389d16 83 #define __SEV __sev
mega64 146:03e976389d16 84
mega64 146:03e976389d16 85
mega64 146:03e976389d16 86 /** \brief Instruction Synchronization Barrier
mega64 146:03e976389d16 87
mega64 146:03e976389d16 88 Instruction Synchronization Barrier flushes the pipeline in the processor,
mega64 146:03e976389d16 89 so that all instructions following the ISB are fetched from cache or
mega64 146:03e976389d16 90 memory, after the instruction has been completed.
mega64 146:03e976389d16 91 */
mega64 146:03e976389d16 92 #define __ISB() do {\
mega64 146:03e976389d16 93 __schedule_barrier();\
mega64 146:03e976389d16 94 __isb(0xF);\
mega64 146:03e976389d16 95 __schedule_barrier();\
mega64 146:03e976389d16 96 } while (0)
mega64 146:03e976389d16 97
mega64 146:03e976389d16 98 /** \brief Data Synchronization Barrier
mega64 146:03e976389d16 99
mega64 146:03e976389d16 100 This function acts as a special kind of Data Memory Barrier.
mega64 146:03e976389d16 101 It completes when all explicit memory accesses before this instruction complete.
mega64 146:03e976389d16 102 */
mega64 146:03e976389d16 103 #define __DSB() do {\
mega64 146:03e976389d16 104 __schedule_barrier();\
mega64 146:03e976389d16 105 __dsb(0xF);\
mega64 146:03e976389d16 106 __schedule_barrier();\
mega64 146:03e976389d16 107 } while (0)
mega64 146:03e976389d16 108
mega64 146:03e976389d16 109 /** \brief Data Memory Barrier
mega64 146:03e976389d16 110
mega64 146:03e976389d16 111 This function ensures the apparent order of the explicit memory operations before
mega64 146:03e976389d16 112 and after the instruction, without ensuring their completion.
mega64 146:03e976389d16 113 */
mega64 146:03e976389d16 114 #define __DMB() do {\
mega64 146:03e976389d16 115 __schedule_barrier();\
mega64 146:03e976389d16 116 __dmb(0xF);\
mega64 146:03e976389d16 117 __schedule_barrier();\
mega64 146:03e976389d16 118 } while (0)
mega64 146:03e976389d16 119
mega64 146:03e976389d16 120 /** \brief Reverse byte order (32 bit)
mega64 146:03e976389d16 121
mega64 146:03e976389d16 122 This function reverses the byte order in integer value.
mega64 146:03e976389d16 123
mega64 146:03e976389d16 124 \param [in] value Value to reverse
mega64 146:03e976389d16 125 \return Reversed value
mega64 146:03e976389d16 126 */
mega64 146:03e976389d16 127 #define __REV __rev
mega64 146:03e976389d16 128
mega64 146:03e976389d16 129
mega64 146:03e976389d16 130 /** \brief Reverse byte order (16 bit)
mega64 146:03e976389d16 131
mega64 146:03e976389d16 132 This function reverses the byte order in two unsigned short values.
mega64 146:03e976389d16 133
mega64 146:03e976389d16 134 \param [in] value Value to reverse
mega64 146:03e976389d16 135 \return Reversed value
mega64 146:03e976389d16 136 */
mega64 146:03e976389d16 137 #ifndef __NO_EMBEDDED_ASM
mega64 146:03e976389d16 138 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
mega64 146:03e976389d16 139 {
mega64 146:03e976389d16 140 rev16 r0, r0
mega64 146:03e976389d16 141 bx lr
mega64 146:03e976389d16 142 }
mega64 146:03e976389d16 143 #endif
mega64 146:03e976389d16 144
mega64 146:03e976389d16 145 /** \brief Reverse byte order in signed short value
mega64 146:03e976389d16 146
mega64 146:03e976389d16 147 This function reverses the byte order in a signed short value with sign extension to integer.
mega64 146:03e976389d16 148
mega64 146:03e976389d16 149 \param [in] value Value to reverse
mega64 146:03e976389d16 150 \return Reversed value
mega64 146:03e976389d16 151 */
mega64 146:03e976389d16 152 #ifndef __NO_EMBEDDED_ASM
mega64 146:03e976389d16 153 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
mega64 146:03e976389d16 154 {
mega64 146:03e976389d16 155 revsh r0, r0
mega64 146:03e976389d16 156 bx lr
mega64 146:03e976389d16 157 }
mega64 146:03e976389d16 158 #endif
mega64 146:03e976389d16 159
mega64 146:03e976389d16 160
mega64 146:03e976389d16 161 /** \brief Rotate Right in unsigned value (32 bit)
mega64 146:03e976389d16 162
mega64 146:03e976389d16 163 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
mega64 146:03e976389d16 164
mega64 146:03e976389d16 165 \param [in] value Value to rotate
mega64 146:03e976389d16 166 \param [in] value Number of Bits to rotate
mega64 146:03e976389d16 167 \return Rotated value
mega64 146:03e976389d16 168 */
mega64 146:03e976389d16 169 #define __ROR __ror
mega64 146:03e976389d16 170
mega64 146:03e976389d16 171
mega64 146:03e976389d16 172 /** \brief Breakpoint
mega64 146:03e976389d16 173
mega64 146:03e976389d16 174 This function causes the processor to enter Debug state.
mega64 146:03e976389d16 175 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
mega64 146:03e976389d16 176
mega64 146:03e976389d16 177 \param [in] value is ignored by the processor.
mega64 146:03e976389d16 178 If required, a debugger can use it to store additional information about the breakpoint.
mega64 146:03e976389d16 179 */
mega64 146:03e976389d16 180 #define __BKPT(value) __breakpoint(value)
mega64 146:03e976389d16 181
mega64 146:03e976389d16 182
mega64 146:03e976389d16 183 /** \brief Reverse bit order of value
mega64 146:03e976389d16 184
mega64 146:03e976389d16 185 This function reverses the bit order of the given value.
mega64 146:03e976389d16 186
mega64 146:03e976389d16 187 \param [in] value Value to reverse
mega64 146:03e976389d16 188 \return Reversed value
mega64 146:03e976389d16 189 */
mega64 146:03e976389d16 190 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
mega64 146:03e976389d16 191 #define __RBIT __rbit
mega64 146:03e976389d16 192 #else
mega64 146:03e976389d16 193 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
mega64 146:03e976389d16 194 {
mega64 146:03e976389d16 195 uint32_t result;
mega64 146:03e976389d16 196 int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
mega64 146:03e976389d16 197
mega64 146:03e976389d16 198 result = value; // r will be reversed bits of v; first get LSB of v
mega64 146:03e976389d16 199 for (value >>= 1; value; value >>= 1)
mega64 146:03e976389d16 200 {
mega64 146:03e976389d16 201 result <<= 1;
mega64 146:03e976389d16 202 result |= value & 1;
mega64 146:03e976389d16 203 s--;
mega64 146:03e976389d16 204 }
mega64 146:03e976389d16 205 result <<= s; // shift when v's highest bits are zero
mega64 146:03e976389d16 206 return(result);
mega64 146:03e976389d16 207 }
mega64 146:03e976389d16 208 #endif
mega64 146:03e976389d16 209
mega64 146:03e976389d16 210
mega64 146:03e976389d16 211 /** \brief Count leading zeros
mega64 146:03e976389d16 212
mega64 146:03e976389d16 213 This function counts the number of leading zeros of a data value.
mega64 146:03e976389d16 214
mega64 146:03e976389d16 215 \param [in] value Value to count the leading zeros
mega64 146:03e976389d16 216 \return number of leading zeros in value
mega64 146:03e976389d16 217 */
mega64 146:03e976389d16 218 #define __CLZ __clz
mega64 146:03e976389d16 219
mega64 146:03e976389d16 220
mega64 146:03e976389d16 221 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
mega64 146:03e976389d16 222
mega64 146:03e976389d16 223 /** \brief LDR Exclusive (8 bit)
mega64 146:03e976389d16 224
mega64 146:03e976389d16 225 This function executes a exclusive LDR instruction for 8 bit value.
mega64 146:03e976389d16 226
mega64 146:03e976389d16 227 \param [in] ptr Pointer to data
mega64 146:03e976389d16 228 \return value of type uint8_t at (*ptr)
mega64 146:03e976389d16 229 */
mega64 146:03e976389d16 230 #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
mega64 146:03e976389d16 231
mega64 146:03e976389d16 232
mega64 146:03e976389d16 233 /** \brief LDR Exclusive (16 bit)
mega64 146:03e976389d16 234
mega64 146:03e976389d16 235 This function executes a exclusive LDR instruction for 16 bit values.
mega64 146:03e976389d16 236
mega64 146:03e976389d16 237 \param [in] ptr Pointer to data
mega64 146:03e976389d16 238 \return value of type uint16_t at (*ptr)
mega64 146:03e976389d16 239 */
mega64 146:03e976389d16 240 #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
mega64 146:03e976389d16 241
mega64 146:03e976389d16 242
mega64 146:03e976389d16 243 /** \brief LDR Exclusive (32 bit)
mega64 146:03e976389d16 244
mega64 146:03e976389d16 245 This function executes a exclusive LDR instruction for 32 bit values.
mega64 146:03e976389d16 246
mega64 146:03e976389d16 247 \param [in] ptr Pointer to data
mega64 146:03e976389d16 248 \return value of type uint32_t at (*ptr)
mega64 146:03e976389d16 249 */
mega64 146:03e976389d16 250 #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
mega64 146:03e976389d16 251
mega64 146:03e976389d16 252
mega64 146:03e976389d16 253 /** \brief STR Exclusive (8 bit)
mega64 146:03e976389d16 254
mega64 146:03e976389d16 255 This function executes a exclusive STR instruction for 8 bit values.
mega64 146:03e976389d16 256
mega64 146:03e976389d16 257 \param [in] value Value to store
mega64 146:03e976389d16 258 \param [in] ptr Pointer to location
mega64 146:03e976389d16 259 \return 0 Function succeeded
mega64 146:03e976389d16 260 \return 1 Function failed
mega64 146:03e976389d16 261 */
mega64 146:03e976389d16 262 #define __STREXB(value, ptr) __strex(value, ptr)
mega64 146:03e976389d16 263
mega64 146:03e976389d16 264
mega64 146:03e976389d16 265 /** \brief STR Exclusive (16 bit)
mega64 146:03e976389d16 266
mega64 146:03e976389d16 267 This function executes a exclusive STR instruction for 16 bit values.
mega64 146:03e976389d16 268
mega64 146:03e976389d16 269 \param [in] value Value to store
mega64 146:03e976389d16 270 \param [in] ptr Pointer to location
mega64 146:03e976389d16 271 \return 0 Function succeeded
mega64 146:03e976389d16 272 \return 1 Function failed
mega64 146:03e976389d16 273 */
mega64 146:03e976389d16 274 #define __STREXH(value, ptr) __strex(value, ptr)
mega64 146:03e976389d16 275
mega64 146:03e976389d16 276
mega64 146:03e976389d16 277 /** \brief STR Exclusive (32 bit)
mega64 146:03e976389d16 278
mega64 146:03e976389d16 279 This function executes a exclusive STR instruction for 32 bit values.
mega64 146:03e976389d16 280
mega64 146:03e976389d16 281 \param [in] value Value to store
mega64 146:03e976389d16 282 \param [in] ptr Pointer to location
mega64 146:03e976389d16 283 \return 0 Function succeeded
mega64 146:03e976389d16 284 \return 1 Function failed
mega64 146:03e976389d16 285 */
mega64 146:03e976389d16 286 #define __STREXW(value, ptr) __strex(value, ptr)
mega64 146:03e976389d16 287
mega64 146:03e976389d16 288
mega64 146:03e976389d16 289 /** \brief Remove the exclusive lock
mega64 146:03e976389d16 290
mega64 146:03e976389d16 291 This function removes the exclusive lock which is created by LDREX.
mega64 146:03e976389d16 292
mega64 146:03e976389d16 293 */
mega64 146:03e976389d16 294 #define __CLREX __clrex
mega64 146:03e976389d16 295
mega64 146:03e976389d16 296
mega64 146:03e976389d16 297 /** \brief Signed Saturate
mega64 146:03e976389d16 298
mega64 146:03e976389d16 299 This function saturates a signed value.
mega64 146:03e976389d16 300
mega64 146:03e976389d16 301 \param [in] value Value to be saturated
mega64 146:03e976389d16 302 \param [in] sat Bit position to saturate to (1..32)
mega64 146:03e976389d16 303 \return Saturated value
mega64 146:03e976389d16 304 */
mega64 146:03e976389d16 305 #define __SSAT __ssat
mega64 146:03e976389d16 306
mega64 146:03e976389d16 307
mega64 146:03e976389d16 308 /** \brief Unsigned Saturate
mega64 146:03e976389d16 309
mega64 146:03e976389d16 310 This function saturates an unsigned value.
mega64 146:03e976389d16 311
mega64 146:03e976389d16 312 \param [in] value Value to be saturated
mega64 146:03e976389d16 313 \param [in] sat Bit position to saturate to (0..31)
mega64 146:03e976389d16 314 \return Saturated value
mega64 146:03e976389d16 315 */
mega64 146:03e976389d16 316 #define __USAT __usat
mega64 146:03e976389d16 317
mega64 146:03e976389d16 318
mega64 146:03e976389d16 319 /** \brief Rotate Right with Extend (32 bit)
mega64 146:03e976389d16 320
mega64 146:03e976389d16 321 This function moves each bit of a bitstring right by one bit.
mega64 146:03e976389d16 322 The carry input is shifted in at the left end of the bitstring.
mega64 146:03e976389d16 323
mega64 146:03e976389d16 324 \param [in] value Value to rotate
mega64 146:03e976389d16 325 \return Rotated value
mega64 146:03e976389d16 326 */
mega64 146:03e976389d16 327 #ifndef __NO_EMBEDDED_ASM
mega64 146:03e976389d16 328 __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
mega64 146:03e976389d16 329 {
mega64 146:03e976389d16 330 rrx r0, r0
mega64 146:03e976389d16 331 bx lr
mega64 146:03e976389d16 332 }
mega64 146:03e976389d16 333 #endif
mega64 146:03e976389d16 334
mega64 146:03e976389d16 335
mega64 146:03e976389d16 336 /** \brief LDRT Unprivileged (8 bit)
mega64 146:03e976389d16 337
mega64 146:03e976389d16 338 This function executes a Unprivileged LDRT instruction for 8 bit value.
mega64 146:03e976389d16 339
mega64 146:03e976389d16 340 \param [in] ptr Pointer to data
mega64 146:03e976389d16 341 \return value of type uint8_t at (*ptr)
mega64 146:03e976389d16 342 */
mega64 146:03e976389d16 343 #define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
mega64 146:03e976389d16 344
mega64 146:03e976389d16 345
mega64 146:03e976389d16 346 /** \brief LDRT Unprivileged (16 bit)
mega64 146:03e976389d16 347
mega64 146:03e976389d16 348 This function executes a Unprivileged LDRT instruction for 16 bit values.
mega64 146:03e976389d16 349
mega64 146:03e976389d16 350 \param [in] ptr Pointer to data
mega64 146:03e976389d16 351 \return value of type uint16_t at (*ptr)
mega64 146:03e976389d16 352 */
mega64 146:03e976389d16 353 #define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
mega64 146:03e976389d16 354
mega64 146:03e976389d16 355
mega64 146:03e976389d16 356 /** \brief LDRT Unprivileged (32 bit)
mega64 146:03e976389d16 357
mega64 146:03e976389d16 358 This function executes a Unprivileged LDRT instruction for 32 bit values.
mega64 146:03e976389d16 359
mega64 146:03e976389d16 360 \param [in] ptr Pointer to data
mega64 146:03e976389d16 361 \return value of type uint32_t at (*ptr)
mega64 146:03e976389d16 362 */
mega64 146:03e976389d16 363 #define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
mega64 146:03e976389d16 364
mega64 146:03e976389d16 365
mega64 146:03e976389d16 366 /** \brief STRT Unprivileged (8 bit)
mega64 146:03e976389d16 367
mega64 146:03e976389d16 368 This function executes a Unprivileged STRT instruction for 8 bit values.
mega64 146:03e976389d16 369
mega64 146:03e976389d16 370 \param [in] value Value to store
mega64 146:03e976389d16 371 \param [in] ptr Pointer to location
mega64 146:03e976389d16 372 */
mega64 146:03e976389d16 373 #define __STRBT(value, ptr) __strt(value, ptr)
mega64 146:03e976389d16 374
mega64 146:03e976389d16 375
mega64 146:03e976389d16 376 /** \brief STRT Unprivileged (16 bit)
mega64 146:03e976389d16 377
mega64 146:03e976389d16 378 This function executes a Unprivileged STRT instruction for 16 bit values.
mega64 146:03e976389d16 379
mega64 146:03e976389d16 380 \param [in] value Value to store
mega64 146:03e976389d16 381 \param [in] ptr Pointer to location
mega64 146:03e976389d16 382 */
mega64 146:03e976389d16 383 #define __STRHT(value, ptr) __strt(value, ptr)
mega64 146:03e976389d16 384
mega64 146:03e976389d16 385
mega64 146:03e976389d16 386 /** \brief STRT Unprivileged (32 bit)
mega64 146:03e976389d16 387
mega64 146:03e976389d16 388 This function executes a Unprivileged STRT instruction for 32 bit values.
mega64 146:03e976389d16 389
mega64 146:03e976389d16 390 \param [in] value Value to store
mega64 146:03e976389d16 391 \param [in] ptr Pointer to location
mega64 146:03e976389d16 392 */
mega64 146:03e976389d16 393 #define __STRT(value, ptr) __strt(value, ptr)
mega64 146:03e976389d16 394
mega64 146:03e976389d16 395 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
mega64 146:03e976389d16 396
mega64 146:03e976389d16 397
mega64 146:03e976389d16 398 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
mega64 146:03e976389d16 399 /* GNU gcc specific functions */
mega64 146:03e976389d16 400
mega64 146:03e976389d16 401 /* Define macros for porting to both thumb1 and thumb2.
mega64 146:03e976389d16 402 * For thumb1, use low register (r0-r7), specified by constrant "l"
mega64 146:03e976389d16 403 * Otherwise, use general registers, specified by constrant "r" */
mega64 146:03e976389d16 404 #if defined (__thumb__) && !defined (__thumb2__)
mega64 146:03e976389d16 405 #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
mega64 146:03e976389d16 406 #define __CMSIS_GCC_USE_REG(r) "l" (r)
mega64 146:03e976389d16 407 #else
mega64 146:03e976389d16 408 #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
mega64 146:03e976389d16 409 #define __CMSIS_GCC_USE_REG(r) "r" (r)
mega64 146:03e976389d16 410 #endif
mega64 146:03e976389d16 411
mega64 146:03e976389d16 412 /** \brief No Operation
mega64 146:03e976389d16 413
mega64 146:03e976389d16 414 No Operation does nothing. This instruction can be used for code alignment purposes.
mega64 146:03e976389d16 415 */
mega64 146:03e976389d16 416 __attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
mega64 146:03e976389d16 417 {
mega64 146:03e976389d16 418 __ASM volatile ("nop");
mega64 146:03e976389d16 419 }
mega64 146:03e976389d16 420
mega64 146:03e976389d16 421
mega64 146:03e976389d16 422 /** \brief Wait For Interrupt
mega64 146:03e976389d16 423
mega64 146:03e976389d16 424 Wait For Interrupt is a hint instruction that suspends execution
mega64 146:03e976389d16 425 until one of a number of events occurs.
mega64 146:03e976389d16 426 */
mega64 146:03e976389d16 427 __attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
mega64 146:03e976389d16 428 {
mega64 146:03e976389d16 429 __ASM volatile ("wfi");
mega64 146:03e976389d16 430 }
mega64 146:03e976389d16 431
mega64 146:03e976389d16 432
mega64 146:03e976389d16 433 /** \brief Wait For Event
mega64 146:03e976389d16 434
mega64 146:03e976389d16 435 Wait For Event is a hint instruction that permits the processor to enter
mega64 146:03e976389d16 436 a low-power state until one of a number of events occurs.
mega64 146:03e976389d16 437 */
mega64 146:03e976389d16 438 __attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
mega64 146:03e976389d16 439 {
mega64 146:03e976389d16 440 __ASM volatile ("wfe");
mega64 146:03e976389d16 441 }
mega64 146:03e976389d16 442
mega64 146:03e976389d16 443
mega64 146:03e976389d16 444 /** \brief Send Event
mega64 146:03e976389d16 445
mega64 146:03e976389d16 446 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
mega64 146:03e976389d16 447 */
mega64 146:03e976389d16 448 __attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
mega64 146:03e976389d16 449 {
mega64 146:03e976389d16 450 __ASM volatile ("sev");
mega64 146:03e976389d16 451 }
mega64 146:03e976389d16 452
mega64 146:03e976389d16 453
mega64 146:03e976389d16 454 /** \brief Instruction Synchronization Barrier
mega64 146:03e976389d16 455
mega64 146:03e976389d16 456 Instruction Synchronization Barrier flushes the pipeline in the processor,
mega64 146:03e976389d16 457 so that all instructions following the ISB are fetched from cache or
mega64 146:03e976389d16 458 memory, after the instruction has been completed.
mega64 146:03e976389d16 459 */
mega64 146:03e976389d16 460 __attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
mega64 146:03e976389d16 461 {
mega64 146:03e976389d16 462 __ASM volatile ("isb 0xF":::"memory");
mega64 146:03e976389d16 463 }
mega64 146:03e976389d16 464
mega64 146:03e976389d16 465
mega64 146:03e976389d16 466 /** \brief Data Synchronization Barrier
mega64 146:03e976389d16 467
mega64 146:03e976389d16 468 This function acts as a special kind of Data Memory Barrier.
mega64 146:03e976389d16 469 It completes when all explicit memory accesses before this instruction complete.
mega64 146:03e976389d16 470 */
mega64 146:03e976389d16 471 __attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
mega64 146:03e976389d16 472 {
mega64 146:03e976389d16 473 __ASM volatile ("dsb 0xF":::"memory");
mega64 146:03e976389d16 474 }
mega64 146:03e976389d16 475
mega64 146:03e976389d16 476
mega64 146:03e976389d16 477 /** \brief Data Memory Barrier
mega64 146:03e976389d16 478
mega64 146:03e976389d16 479 This function ensures the apparent order of the explicit memory operations before
mega64 146:03e976389d16 480 and after the instruction, without ensuring their completion.
mega64 146:03e976389d16 481 */
mega64 146:03e976389d16 482 __attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
mega64 146:03e976389d16 483 {
mega64 146:03e976389d16 484 __ASM volatile ("dmb 0xF":::"memory");
mega64 146:03e976389d16 485 }
mega64 146:03e976389d16 486
mega64 146:03e976389d16 487
mega64 146:03e976389d16 488 /** \brief Reverse byte order (32 bit)
mega64 146:03e976389d16 489
mega64 146:03e976389d16 490 This function reverses the byte order in integer value.
mega64 146:03e976389d16 491
mega64 146:03e976389d16 492 \param [in] value Value to reverse
mega64 146:03e976389d16 493 \return Reversed value
mega64 146:03e976389d16 494 */
mega64 146:03e976389d16 495 __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
mega64 146:03e976389d16 496 {
mega64 146:03e976389d16 497 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
mega64 146:03e976389d16 498 return __builtin_bswap32(value);
mega64 146:03e976389d16 499 #else
mega64 146:03e976389d16 500 uint32_t result;
mega64 146:03e976389d16 501
mega64 146:03e976389d16 502 __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
mega64 146:03e976389d16 503 return(result);
mega64 146:03e976389d16 504 #endif
mega64 146:03e976389d16 505 }
mega64 146:03e976389d16 506
mega64 146:03e976389d16 507
mega64 146:03e976389d16 508 /** \brief Reverse byte order (16 bit)
mega64 146:03e976389d16 509
mega64 146:03e976389d16 510 This function reverses the byte order in two unsigned short values.
mega64 146:03e976389d16 511
mega64 146:03e976389d16 512 \param [in] value Value to reverse
mega64 146:03e976389d16 513 \return Reversed value
mega64 146:03e976389d16 514 */
mega64 146:03e976389d16 515 __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
mega64 146:03e976389d16 516 {
mega64 146:03e976389d16 517 uint32_t result;
mega64 146:03e976389d16 518
mega64 146:03e976389d16 519 __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
mega64 146:03e976389d16 520 return(result);
mega64 146:03e976389d16 521 }
mega64 146:03e976389d16 522
mega64 146:03e976389d16 523
mega64 146:03e976389d16 524 /** \brief Reverse byte order in signed short value
mega64 146:03e976389d16 525
mega64 146:03e976389d16 526 This function reverses the byte order in a signed short value with sign extension to integer.
mega64 146:03e976389d16 527
mega64 146:03e976389d16 528 \param [in] value Value to reverse
mega64 146:03e976389d16 529 \return Reversed value
mega64 146:03e976389d16 530 */
mega64 146:03e976389d16 531 __attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
mega64 146:03e976389d16 532 {
mega64 146:03e976389d16 533 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
mega64 146:03e976389d16 534 return (short)__builtin_bswap16(value);
mega64 146:03e976389d16 535 #else
mega64 146:03e976389d16 536 uint32_t result;
mega64 146:03e976389d16 537
mega64 146:03e976389d16 538 __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
mega64 146:03e976389d16 539 return(result);
mega64 146:03e976389d16 540 #endif
mega64 146:03e976389d16 541 }
mega64 146:03e976389d16 542
mega64 146:03e976389d16 543
mega64 146:03e976389d16 544 /** \brief Rotate Right in unsigned value (32 bit)
mega64 146:03e976389d16 545
mega64 146:03e976389d16 546 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
mega64 146:03e976389d16 547
mega64 146:03e976389d16 548 \param [in] value Value to rotate
mega64 146:03e976389d16 549 \param [in] value Number of Bits to rotate
mega64 146:03e976389d16 550 \return Rotated value
mega64 146:03e976389d16 551 */
mega64 146:03e976389d16 552 __attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
mega64 146:03e976389d16 553 {
mega64 146:03e976389d16 554 return (op1 >> op2) | (op1 << (32 - op2));
mega64 146:03e976389d16 555 }
mega64 146:03e976389d16 556
mega64 146:03e976389d16 557
mega64 146:03e976389d16 558 /** \brief Breakpoint
mega64 146:03e976389d16 559
mega64 146:03e976389d16 560 This function causes the processor to enter Debug state.
mega64 146:03e976389d16 561 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
mega64 146:03e976389d16 562
mega64 146:03e976389d16 563 \param [in] value is ignored by the processor.
mega64 146:03e976389d16 564 If required, a debugger can use it to store additional information about the breakpoint.
mega64 146:03e976389d16 565 */
mega64 146:03e976389d16 566 #define __BKPT(value) __ASM volatile ("bkpt "#value)
mega64 146:03e976389d16 567
mega64 146:03e976389d16 568
mega64 146:03e976389d16 569 /** \brief Reverse bit order of value
mega64 146:03e976389d16 570
mega64 146:03e976389d16 571 This function reverses the bit order of the given value.
mega64 146:03e976389d16 572
mega64 146:03e976389d16 573 \param [in] value Value to reverse
mega64 146:03e976389d16 574 \return Reversed value
mega64 146:03e976389d16 575 */
mega64 146:03e976389d16 576 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
mega64 146:03e976389d16 577 {
mega64 146:03e976389d16 578 uint32_t result;
mega64 146:03e976389d16 579
mega64 146:03e976389d16 580 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
mega64 146:03e976389d16 581 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
mega64 146:03e976389d16 582 #else
mega64 146:03e976389d16 583 int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
mega64 146:03e976389d16 584
mega64 146:03e976389d16 585 result = value; // r will be reversed bits of v; first get LSB of v
mega64 146:03e976389d16 586 for (value >>= 1; value; value >>= 1)
mega64 146:03e976389d16 587 {
mega64 146:03e976389d16 588 result <<= 1;
mega64 146:03e976389d16 589 result |= value & 1;
mega64 146:03e976389d16 590 s--;
mega64 146:03e976389d16 591 }
mega64 146:03e976389d16 592 result <<= s; // shift when v's highest bits are zero
mega64 146:03e976389d16 593 #endif
mega64 146:03e976389d16 594 return(result);
mega64 146:03e976389d16 595 }
mega64 146:03e976389d16 596
mega64 146:03e976389d16 597
mega64 146:03e976389d16 598 /** \brief Count leading zeros
mega64 146:03e976389d16 599
mega64 146:03e976389d16 600 This function counts the number of leading zeros of a data value.
mega64 146:03e976389d16 601
mega64 146:03e976389d16 602 \param [in] value Value to count the leading zeros
mega64 146:03e976389d16 603 \return number of leading zeros in value
mega64 146:03e976389d16 604 */
mega64 146:03e976389d16 605 #define __CLZ __builtin_clz
mega64 146:03e976389d16 606
mega64 146:03e976389d16 607
mega64 146:03e976389d16 608 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
mega64 146:03e976389d16 609
mega64 146:03e976389d16 610 /** \brief LDR Exclusive (8 bit)
mega64 146:03e976389d16 611
mega64 146:03e976389d16 612 This function executes a exclusive LDR instruction for 8 bit value.
mega64 146:03e976389d16 613
mega64 146:03e976389d16 614 \param [in] ptr Pointer to data
mega64 146:03e976389d16 615 \return value of type uint8_t at (*ptr)
mega64 146:03e976389d16 616 */
mega64 146:03e976389d16 617 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
mega64 146:03e976389d16 618 {
mega64 146:03e976389d16 619 uint32_t result;
mega64 146:03e976389d16 620
mega64 146:03e976389d16 621 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
mega64 146:03e976389d16 622 __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
mega64 146:03e976389d16 623 #else
mega64 146:03e976389d16 624 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
mega64 146:03e976389d16 625 accepted by assembler. So has to use following less efficient pattern.
mega64 146:03e976389d16 626 */
mega64 146:03e976389d16 627 __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
mega64 146:03e976389d16 628 #endif
mega64 146:03e976389d16 629 return ((uint8_t) result); /* Add explicit type cast here */
mega64 146:03e976389d16 630 }
mega64 146:03e976389d16 631
mega64 146:03e976389d16 632
mega64 146:03e976389d16 633 /** \brief LDR Exclusive (16 bit)
mega64 146:03e976389d16 634
mega64 146:03e976389d16 635 This function executes a exclusive LDR instruction for 16 bit values.
mega64 146:03e976389d16 636
mega64 146:03e976389d16 637 \param [in] ptr Pointer to data
mega64 146:03e976389d16 638 \return value of type uint16_t at (*ptr)
mega64 146:03e976389d16 639 */
mega64 146:03e976389d16 640 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
mega64 146:03e976389d16 641 {
mega64 146:03e976389d16 642 uint32_t result;
mega64 146:03e976389d16 643
mega64 146:03e976389d16 644 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
mega64 146:03e976389d16 645 __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
mega64 146:03e976389d16 646 #else
mega64 146:03e976389d16 647 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
mega64 146:03e976389d16 648 accepted by assembler. So has to use following less efficient pattern.
mega64 146:03e976389d16 649 */
mega64 146:03e976389d16 650 __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
mega64 146:03e976389d16 651 #endif
mega64 146:03e976389d16 652 return ((uint16_t) result); /* Add explicit type cast here */
mega64 146:03e976389d16 653 }
mega64 146:03e976389d16 654
mega64 146:03e976389d16 655
mega64 146:03e976389d16 656 /** \brief LDR Exclusive (32 bit)
mega64 146:03e976389d16 657
mega64 146:03e976389d16 658 This function executes a exclusive LDR instruction for 32 bit values.
mega64 146:03e976389d16 659
mega64 146:03e976389d16 660 \param [in] ptr Pointer to data
mega64 146:03e976389d16 661 \return value of type uint32_t at (*ptr)
mega64 146:03e976389d16 662 */
mega64 146:03e976389d16 663 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
mega64 146:03e976389d16 664 {
mega64 146:03e976389d16 665 uint32_t result;
mega64 146:03e976389d16 666
mega64 146:03e976389d16 667 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
mega64 146:03e976389d16 668 return(result);
mega64 146:03e976389d16 669 }
mega64 146:03e976389d16 670
mega64 146:03e976389d16 671
mega64 146:03e976389d16 672 /** \brief STR Exclusive (8 bit)
mega64 146:03e976389d16 673
mega64 146:03e976389d16 674 This function executes a exclusive STR instruction for 8 bit values.
mega64 146:03e976389d16 675
mega64 146:03e976389d16 676 \param [in] value Value to store
mega64 146:03e976389d16 677 \param [in] ptr Pointer to location
mega64 146:03e976389d16 678 \return 0 Function succeeded
mega64 146:03e976389d16 679 \return 1 Function failed
mega64 146:03e976389d16 680 */
mega64 146:03e976389d16 681 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
mega64 146:03e976389d16 682 {
mega64 146:03e976389d16 683 uint32_t result;
mega64 146:03e976389d16 684
mega64 146:03e976389d16 685 __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
mega64 146:03e976389d16 686 return(result);
mega64 146:03e976389d16 687 }
mega64 146:03e976389d16 688
mega64 146:03e976389d16 689
mega64 146:03e976389d16 690 /** \brief STR Exclusive (16 bit)
mega64 146:03e976389d16 691
mega64 146:03e976389d16 692 This function executes a exclusive STR instruction for 16 bit values.
mega64 146:03e976389d16 693
mega64 146:03e976389d16 694 \param [in] value Value to store
mega64 146:03e976389d16 695 \param [in] ptr Pointer to location
mega64 146:03e976389d16 696 \return 0 Function succeeded
mega64 146:03e976389d16 697 \return 1 Function failed
mega64 146:03e976389d16 698 */
mega64 146:03e976389d16 699 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
mega64 146:03e976389d16 700 {
mega64 146:03e976389d16 701 uint32_t result;
mega64 146:03e976389d16 702
mega64 146:03e976389d16 703 __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
mega64 146:03e976389d16 704 return(result);
mega64 146:03e976389d16 705 }
mega64 146:03e976389d16 706
mega64 146:03e976389d16 707
mega64 146:03e976389d16 708 /** \brief STR Exclusive (32 bit)
mega64 146:03e976389d16 709
mega64 146:03e976389d16 710 This function executes a exclusive STR instruction for 32 bit values.
mega64 146:03e976389d16 711
mega64 146:03e976389d16 712 \param [in] value Value to store
mega64 146:03e976389d16 713 \param [in] ptr Pointer to location
mega64 146:03e976389d16 714 \return 0 Function succeeded
mega64 146:03e976389d16 715 \return 1 Function failed
mega64 146:03e976389d16 716 */
mega64 146:03e976389d16 717 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
mega64 146:03e976389d16 718 {
mega64 146:03e976389d16 719 uint32_t result;
mega64 146:03e976389d16 720
mega64 146:03e976389d16 721 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
mega64 146:03e976389d16 722 return(result);
mega64 146:03e976389d16 723 }
mega64 146:03e976389d16 724
mega64 146:03e976389d16 725
mega64 146:03e976389d16 726 /** \brief Remove the exclusive lock
mega64 146:03e976389d16 727
mega64 146:03e976389d16 728 This function removes the exclusive lock which is created by LDREX.
mega64 146:03e976389d16 729
mega64 146:03e976389d16 730 */
mega64 146:03e976389d16 731 __attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
mega64 146:03e976389d16 732 {
mega64 146:03e976389d16 733 __ASM volatile ("clrex" ::: "memory");
mega64 146:03e976389d16 734 }
mega64 146:03e976389d16 735
mega64 146:03e976389d16 736
mega64 146:03e976389d16 737 /** \brief Signed Saturate
mega64 146:03e976389d16 738
mega64 146:03e976389d16 739 This function saturates a signed value.
mega64 146:03e976389d16 740
mega64 146:03e976389d16 741 \param [in] value Value to be saturated
mega64 146:03e976389d16 742 \param [in] sat Bit position to saturate to (1..32)
mega64 146:03e976389d16 743 \return Saturated value
mega64 146:03e976389d16 744 */
mega64 146:03e976389d16 745 #define __SSAT(ARG1,ARG2) \
mega64 146:03e976389d16 746 ({ \
mega64 146:03e976389d16 747 uint32_t __RES, __ARG1 = (ARG1); \
mega64 146:03e976389d16 748 __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
mega64 146:03e976389d16 749 __RES; \
mega64 146:03e976389d16 750 })
mega64 146:03e976389d16 751
mega64 146:03e976389d16 752
mega64 146:03e976389d16 753 /** \brief Unsigned Saturate
mega64 146:03e976389d16 754
mega64 146:03e976389d16 755 This function saturates an unsigned value.
mega64 146:03e976389d16 756
mega64 146:03e976389d16 757 \param [in] value Value to be saturated
mega64 146:03e976389d16 758 \param [in] sat Bit position to saturate to (0..31)
mega64 146:03e976389d16 759 \return Saturated value
mega64 146:03e976389d16 760 */
mega64 146:03e976389d16 761 #define __USAT(ARG1,ARG2) \
mega64 146:03e976389d16 762 ({ \
mega64 146:03e976389d16 763 uint32_t __RES, __ARG1 = (ARG1); \
mega64 146:03e976389d16 764 __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
mega64 146:03e976389d16 765 __RES; \
mega64 146:03e976389d16 766 })
mega64 146:03e976389d16 767
mega64 146:03e976389d16 768
mega64 146:03e976389d16 769 /** \brief Rotate Right with Extend (32 bit)
mega64 146:03e976389d16 770
mega64 146:03e976389d16 771 This function moves each bit of a bitstring right by one bit.
mega64 146:03e976389d16 772 The carry input is shifted in at the left end of the bitstring.
mega64 146:03e976389d16 773
mega64 146:03e976389d16 774 \param [in] value Value to rotate
mega64 146:03e976389d16 775 \return Rotated value
mega64 146:03e976389d16 776 */
mega64 146:03e976389d16 777 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
mega64 146:03e976389d16 778 {
mega64 146:03e976389d16 779 uint32_t result;
mega64 146:03e976389d16 780
mega64 146:03e976389d16 781 __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
mega64 146:03e976389d16 782 return(result);
mega64 146:03e976389d16 783 }
mega64 146:03e976389d16 784
mega64 146:03e976389d16 785
mega64 146:03e976389d16 786 /** \brief LDRT Unprivileged (8 bit)
mega64 146:03e976389d16 787
mega64 146:03e976389d16 788 This function executes a Unprivileged LDRT instruction for 8 bit value.
mega64 146:03e976389d16 789
mega64 146:03e976389d16 790 \param [in] ptr Pointer to data
mega64 146:03e976389d16 791 \return value of type uint8_t at (*ptr)
mega64 146:03e976389d16 792 */
mega64 146:03e976389d16 793 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
mega64 146:03e976389d16 794 {
mega64 146:03e976389d16 795 uint32_t result;
mega64 146:03e976389d16 796
mega64 146:03e976389d16 797 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
mega64 146:03e976389d16 798 __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
mega64 146:03e976389d16 799 #else
mega64 146:03e976389d16 800 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
mega64 146:03e976389d16 801 accepted by assembler. So has to use following less efficient pattern.
mega64 146:03e976389d16 802 */
mega64 146:03e976389d16 803 __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
mega64 146:03e976389d16 804 #endif
mega64 146:03e976389d16 805 return ((uint8_t) result); /* Add explicit type cast here */
mega64 146:03e976389d16 806 }
mega64 146:03e976389d16 807
mega64 146:03e976389d16 808
mega64 146:03e976389d16 809 /** \brief LDRT Unprivileged (16 bit)
mega64 146:03e976389d16 810
mega64 146:03e976389d16 811 This function executes a Unprivileged LDRT instruction for 16 bit values.
mega64 146:03e976389d16 812
mega64 146:03e976389d16 813 \param [in] ptr Pointer to data
mega64 146:03e976389d16 814 \return value of type uint16_t at (*ptr)
mega64 146:03e976389d16 815 */
mega64 146:03e976389d16 816 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
mega64 146:03e976389d16 817 {
mega64 146:03e976389d16 818 uint32_t result;
mega64 146:03e976389d16 819
mega64 146:03e976389d16 820 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
mega64 146:03e976389d16 821 __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
mega64 146:03e976389d16 822 #else
mega64 146:03e976389d16 823 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
mega64 146:03e976389d16 824 accepted by assembler. So has to use following less efficient pattern.
mega64 146:03e976389d16 825 */
mega64 146:03e976389d16 826 __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
mega64 146:03e976389d16 827 #endif
mega64 146:03e976389d16 828 return ((uint16_t) result); /* Add explicit type cast here */
mega64 146:03e976389d16 829 }
mega64 146:03e976389d16 830
mega64 146:03e976389d16 831
mega64 146:03e976389d16 832 /** \brief LDRT Unprivileged (32 bit)
mega64 146:03e976389d16 833
mega64 146:03e976389d16 834 This function executes a Unprivileged LDRT instruction for 32 bit values.
mega64 146:03e976389d16 835
mega64 146:03e976389d16 836 \param [in] ptr Pointer to data
mega64 146:03e976389d16 837 \return value of type uint32_t at (*ptr)
mega64 146:03e976389d16 838 */
mega64 146:03e976389d16 839 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
mega64 146:03e976389d16 840 {
mega64 146:03e976389d16 841 uint32_t result;
mega64 146:03e976389d16 842
mega64 146:03e976389d16 843 __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
mega64 146:03e976389d16 844 return(result);
mega64 146:03e976389d16 845 }
mega64 146:03e976389d16 846
mega64 146:03e976389d16 847
mega64 146:03e976389d16 848 /** \brief STRT Unprivileged (8 bit)
mega64 146:03e976389d16 849
mega64 146:03e976389d16 850 This function executes a Unprivileged STRT instruction for 8 bit values.
mega64 146:03e976389d16 851
mega64 146:03e976389d16 852 \param [in] value Value to store
mega64 146:03e976389d16 853 \param [in] ptr Pointer to location
mega64 146:03e976389d16 854 */
mega64 146:03e976389d16 855 __attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
mega64 146:03e976389d16 856 {
mega64 146:03e976389d16 857 __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
mega64 146:03e976389d16 858 }
mega64 146:03e976389d16 859
mega64 146:03e976389d16 860
mega64 146:03e976389d16 861 /** \brief STRT Unprivileged (16 bit)
mega64 146:03e976389d16 862
mega64 146:03e976389d16 863 This function executes a Unprivileged STRT instruction for 16 bit values.
mega64 146:03e976389d16 864
mega64 146:03e976389d16 865 \param [in] value Value to store
mega64 146:03e976389d16 866 \param [in] ptr Pointer to location
mega64 146:03e976389d16 867 */
mega64 146:03e976389d16 868 __attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
mega64 146:03e976389d16 869 {
mega64 146:03e976389d16 870 __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
mega64 146:03e976389d16 871 }
mega64 146:03e976389d16 872
mega64 146:03e976389d16 873
mega64 146:03e976389d16 874 /** \brief STRT Unprivileged (32 bit)
mega64 146:03e976389d16 875
mega64 146:03e976389d16 876 This function executes a Unprivileged STRT instruction for 32 bit values.
mega64 146:03e976389d16 877
mega64 146:03e976389d16 878 \param [in] value Value to store
mega64 146:03e976389d16 879 \param [in] ptr Pointer to location
mega64 146:03e976389d16 880 */
mega64 146:03e976389d16 881 __attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
mega64 146:03e976389d16 882 {
mega64 146:03e976389d16 883 __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
mega64 146:03e976389d16 884 }
mega64 146:03e976389d16 885
mega64 146:03e976389d16 886 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
mega64 146:03e976389d16 887
mega64 146:03e976389d16 888
mega64 146:03e976389d16 889 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
mega64 146:03e976389d16 890 /* IAR iccarm specific functions */
mega64 146:03e976389d16 891 #include <cmsis_iar.h>
mega64 146:03e976389d16 892
mega64 146:03e976389d16 893
mega64 146:03e976389d16 894 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
mega64 146:03e976389d16 895 /* TI CCS specific functions */
mega64 146:03e976389d16 896 #include <cmsis_ccs.h>
mega64 146:03e976389d16 897
mega64 146:03e976389d16 898
mega64 146:03e976389d16 899 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
mega64 146:03e976389d16 900 /* TASKING carm specific functions */
mega64 146:03e976389d16 901 /*
mega64 146:03e976389d16 902 * The CMSIS functions have been implemented as intrinsics in the compiler.
mega64 146:03e976389d16 903 * Please use "carm -?i" to get an up to date list of all intrinsics,
mega64 146:03e976389d16 904 * Including the CMSIS ones.
mega64 146:03e976389d16 905 */
mega64 146:03e976389d16 906
mega64 146:03e976389d16 907
mega64 146:03e976389d16 908 #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
mega64 146:03e976389d16 909 /* Cosmic specific functions */
mega64 146:03e976389d16 910 #include <cmsis_csm.h>
mega64 146:03e976389d16 911
mega64 146:03e976389d16 912 #endif
mega64 146:03e976389d16 913
mega64 146:03e976389d16 914 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
mega64 146:03e976389d16 915
mega64 146:03e976389d16 916 #endif /* __CORE_CMINSTR_H */