Modification of Mbed-dev library for LQFP48 package microcontrollers: STM32F103C8 (STM32F103C8T6) and STM32F103CB (STM32F103CBT6) (Bluepill boards, Maple mini etc. )

Fork of mbed-STM32F103C8_org by Nothing Special

Library for STM32F103C8 (Bluepill boards etc.).
Use this instead of mbed library.
This library allows the size of the code in the FLASH up to 128kB. Therefore, code also runs on microcontrollers STM32F103CB (eg. Maple mini).
But in the case of STM32F103C8, check the size of the resulting code would not exceed 64kB.

To compile a program with this library, use NUCLEO-F103RB as the target name. !

Changes:

  • Corrected initialization of the HSE + crystal clock (mbed permanent bug), allowing the use of on-board xtal (8MHz).(1)
  • Additionally, it also set USB clock (48Mhz).(2)
  • Definitions of pins and peripherals adjusted to LQFP48 case.
  • Board led LED1 is now PC_13 (3)
  • USER_BUTTON is now PC_14 (4)

    Now the library is complete rebuilt based on mbed-dev v160 (and not yet fully tested).

notes
(1) - In case 8MHz xtal on board, CPU frequency is 72MHz. Without xtal is 64MHz.
(2) - Using the USB interface is only possible if STM32 is clocking by on-board 8MHz xtal or external clock signal 8MHz on the OSC_IN pin.
(3) - On Bluepill board led operation is reversed, i.e. 0 - led on, 1 - led off.
(4) - Bluepill board has no real user button

Information

After export to SW4STM (AC6):

  • add line #include "mbed_config.h" in files Serial.h and RawSerial.h
  • in project properties change Optimisation Level to Optimise for size (-Os)
Committer:
mega64
Date:
Thu Apr 27 23:56:38 2017 +0000
Revision:
148:8b0b02bf146f
Parent:
146:03e976389d16
Remove unnecessary folders

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mega64 146:03e976389d16 1 /**************************************************************************//**
mega64 146:03e976389d16 2 * @file core_cm4.h
mega64 146:03e976389d16 3 * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
mega64 146:03e976389d16 4 * @version V4.10
mega64 146:03e976389d16 5 * @date 18. March 2015
mega64 146:03e976389d16 6 *
mega64 146:03e976389d16 7 * @note
mega64 146:03e976389d16 8 *
mega64 146:03e976389d16 9 ******************************************************************************/
mega64 146:03e976389d16 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
mega64 146:03e976389d16 11
mega64 146:03e976389d16 12 All rights reserved.
mega64 146:03e976389d16 13 Redistribution and use in source and binary forms, with or without
mega64 146:03e976389d16 14 modification, are permitted provided that the following conditions are met:
mega64 146:03e976389d16 15 - Redistributions of source code must retain the above copyright
mega64 146:03e976389d16 16 notice, this list of conditions and the following disclaimer.
mega64 146:03e976389d16 17 - Redistributions in binary form must reproduce the above copyright
mega64 146:03e976389d16 18 notice, this list of conditions and the following disclaimer in the
mega64 146:03e976389d16 19 documentation and/or other materials provided with the distribution.
mega64 146:03e976389d16 20 - Neither the name of ARM nor the names of its contributors may be used
mega64 146:03e976389d16 21 to endorse or promote products derived from this software without
mega64 146:03e976389d16 22 specific prior written permission.
mega64 146:03e976389d16 23 *
mega64 146:03e976389d16 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mega64 146:03e976389d16 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mega64 146:03e976389d16 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
mega64 146:03e976389d16 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
mega64 146:03e976389d16 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
mega64 146:03e976389d16 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
mega64 146:03e976389d16 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mega64 146:03e976389d16 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mega64 146:03e976389d16 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
mega64 146:03e976389d16 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mega64 146:03e976389d16 34 POSSIBILITY OF SUCH DAMAGE.
mega64 146:03e976389d16 35 ---------------------------------------------------------------------------*/
mega64 146:03e976389d16 36
mega64 146:03e976389d16 37
mega64 146:03e976389d16 38 #if defined ( __ICCARM__ )
mega64 146:03e976389d16 39 #pragma system_include /* treat file as system include file for MISRA check */
mega64 146:03e976389d16 40 #endif
mega64 146:03e976389d16 41
mega64 146:03e976389d16 42 #ifndef __CORE_CM4_H_GENERIC
mega64 146:03e976389d16 43 #define __CORE_CM4_H_GENERIC
mega64 146:03e976389d16 44
mega64 146:03e976389d16 45 #ifdef __cplusplus
mega64 146:03e976389d16 46 extern "C" {
mega64 146:03e976389d16 47 #endif
mega64 146:03e976389d16 48
mega64 146:03e976389d16 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
mega64 146:03e976389d16 50 CMSIS violates the following MISRA-C:2004 rules:
mega64 146:03e976389d16 51
mega64 146:03e976389d16 52 \li Required Rule 8.5, object/function definition in header file.<br>
mega64 146:03e976389d16 53 Function definitions in header files are used to allow 'inlining'.
mega64 146:03e976389d16 54
mega64 146:03e976389d16 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
mega64 146:03e976389d16 56 Unions are used for effective representation of core registers.
mega64 146:03e976389d16 57
mega64 146:03e976389d16 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
mega64 146:03e976389d16 59 Function-like macros are used to allow more efficient code.
mega64 146:03e976389d16 60 */
mega64 146:03e976389d16 61
mega64 146:03e976389d16 62
mega64 146:03e976389d16 63 /*******************************************************************************
mega64 146:03e976389d16 64 * CMSIS definitions
mega64 146:03e976389d16 65 ******************************************************************************/
mega64 146:03e976389d16 66 /** \ingroup Cortex_M4
mega64 146:03e976389d16 67 @{
mega64 146:03e976389d16 68 */
mega64 146:03e976389d16 69
mega64 146:03e976389d16 70 /* CMSIS CM4 definitions */
mega64 146:03e976389d16 71 #define __CM4_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
mega64 146:03e976389d16 72 #define __CM4_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
mega64 146:03e976389d16 73 #define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \
mega64 146:03e976389d16 74 __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
mega64 146:03e976389d16 75
mega64 146:03e976389d16 76 #define __CORTEX_M (0x04) /*!< Cortex-M Core */
mega64 146:03e976389d16 77
mega64 146:03e976389d16 78
mega64 146:03e976389d16 79 #if defined ( __CC_ARM )
mega64 146:03e976389d16 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
mega64 146:03e976389d16 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
mega64 146:03e976389d16 82 #define __STATIC_INLINE static __inline
mega64 146:03e976389d16 83
mega64 146:03e976389d16 84 #elif defined ( __GNUC__ )
mega64 146:03e976389d16 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
mega64 146:03e976389d16 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
mega64 146:03e976389d16 87 #define __STATIC_INLINE static inline
mega64 146:03e976389d16 88
mega64 146:03e976389d16 89 #elif defined ( __ICCARM__ )
mega64 146:03e976389d16 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
mega64 146:03e976389d16 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
mega64 146:03e976389d16 92 #define __STATIC_INLINE static inline
mega64 146:03e976389d16 93
mega64 146:03e976389d16 94 #elif defined ( __TMS470__ )
mega64 146:03e976389d16 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
mega64 146:03e976389d16 96 #define __STATIC_INLINE static inline
mega64 146:03e976389d16 97
mega64 146:03e976389d16 98 #elif defined ( __TASKING__ )
mega64 146:03e976389d16 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
mega64 146:03e976389d16 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
mega64 146:03e976389d16 101 #define __STATIC_INLINE static inline
mega64 146:03e976389d16 102
mega64 146:03e976389d16 103 #elif defined ( __CSMC__ )
mega64 146:03e976389d16 104 #define __packed
mega64 146:03e976389d16 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
mega64 146:03e976389d16 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
mega64 146:03e976389d16 107 #define __STATIC_INLINE static inline
mega64 146:03e976389d16 108
mega64 146:03e976389d16 109 #endif
mega64 146:03e976389d16 110
mega64 146:03e976389d16 111 /** __FPU_USED indicates whether an FPU is used or not.
mega64 146:03e976389d16 112 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
mega64 146:03e976389d16 113 */
mega64 146:03e976389d16 114 #if defined ( __CC_ARM )
mega64 146:03e976389d16 115 #if defined __TARGET_FPU_VFP
mega64 146:03e976389d16 116 #if (__FPU_PRESENT == 1)
mega64 146:03e976389d16 117 #define __FPU_USED 1
mega64 146:03e976389d16 118 #else
mega64 146:03e976389d16 119 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mega64 146:03e976389d16 120 #define __FPU_USED 0
mega64 146:03e976389d16 121 #endif
mega64 146:03e976389d16 122 #else
mega64 146:03e976389d16 123 #define __FPU_USED 0
mega64 146:03e976389d16 124 #endif
mega64 146:03e976389d16 125
mega64 146:03e976389d16 126 #elif defined ( __GNUC__ )
mega64 146:03e976389d16 127 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
mega64 146:03e976389d16 128 #if (__FPU_PRESENT == 1)
mega64 146:03e976389d16 129 #define __FPU_USED 1
mega64 146:03e976389d16 130 #else
mega64 146:03e976389d16 131 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mega64 146:03e976389d16 132 #define __FPU_USED 0
mega64 146:03e976389d16 133 #endif
mega64 146:03e976389d16 134 #else
mega64 146:03e976389d16 135 #define __FPU_USED 0
mega64 146:03e976389d16 136 #endif
mega64 146:03e976389d16 137
mega64 146:03e976389d16 138 #elif defined ( __ICCARM__ )
mega64 146:03e976389d16 139 #if defined __ARMVFP__
mega64 146:03e976389d16 140 #if (__FPU_PRESENT == 1)
mega64 146:03e976389d16 141 #define __FPU_USED 1
mega64 146:03e976389d16 142 #else
mega64 146:03e976389d16 143 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mega64 146:03e976389d16 144 #define __FPU_USED 0
mega64 146:03e976389d16 145 #endif
mega64 146:03e976389d16 146 #else
mega64 146:03e976389d16 147 #define __FPU_USED 0
mega64 146:03e976389d16 148 #endif
mega64 146:03e976389d16 149
mega64 146:03e976389d16 150 #elif defined ( __TMS470__ )
mega64 146:03e976389d16 151 #if defined __TI_VFP_SUPPORT__
mega64 146:03e976389d16 152 #if (__FPU_PRESENT == 1)
mega64 146:03e976389d16 153 #define __FPU_USED 1
mega64 146:03e976389d16 154 #else
mega64 146:03e976389d16 155 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mega64 146:03e976389d16 156 #define __FPU_USED 0
mega64 146:03e976389d16 157 #endif
mega64 146:03e976389d16 158 #else
mega64 146:03e976389d16 159 #define __FPU_USED 0
mega64 146:03e976389d16 160 #endif
mega64 146:03e976389d16 161
mega64 146:03e976389d16 162 #elif defined ( __TASKING__ )
mega64 146:03e976389d16 163 #if defined __FPU_VFP__
mega64 146:03e976389d16 164 #if (__FPU_PRESENT == 1)
mega64 146:03e976389d16 165 #define __FPU_USED 1
mega64 146:03e976389d16 166 #else
mega64 146:03e976389d16 167 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mega64 146:03e976389d16 168 #define __FPU_USED 0
mega64 146:03e976389d16 169 #endif
mega64 146:03e976389d16 170 #else
mega64 146:03e976389d16 171 #define __FPU_USED 0
mega64 146:03e976389d16 172 #endif
mega64 146:03e976389d16 173
mega64 146:03e976389d16 174 #elif defined ( __CSMC__ ) /* Cosmic */
mega64 146:03e976389d16 175 #if ( __CSMC__ & 0x400) // FPU present for parser
mega64 146:03e976389d16 176 #if (__FPU_PRESENT == 1)
mega64 146:03e976389d16 177 #define __FPU_USED 1
mega64 146:03e976389d16 178 #else
mega64 146:03e976389d16 179 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mega64 146:03e976389d16 180 #define __FPU_USED 0
mega64 146:03e976389d16 181 #endif
mega64 146:03e976389d16 182 #else
mega64 146:03e976389d16 183 #define __FPU_USED 0
mega64 146:03e976389d16 184 #endif
mega64 146:03e976389d16 185 #endif
mega64 146:03e976389d16 186
mega64 146:03e976389d16 187 #include <stdint.h> /* standard types definitions */
mega64 146:03e976389d16 188 #include <core_cmInstr.h> /* Core Instruction Access */
mega64 146:03e976389d16 189 #include <core_cmFunc.h> /* Core Function Access */
mega64 146:03e976389d16 190 #include <core_cmSimd.h> /* Compiler specific SIMD Intrinsics */
mega64 146:03e976389d16 191
mega64 146:03e976389d16 192 #ifdef __cplusplus
mega64 146:03e976389d16 193 }
mega64 146:03e976389d16 194 #endif
mega64 146:03e976389d16 195
mega64 146:03e976389d16 196 #endif /* __CORE_CM4_H_GENERIC */
mega64 146:03e976389d16 197
mega64 146:03e976389d16 198 #ifndef __CMSIS_GENERIC
mega64 146:03e976389d16 199
mega64 146:03e976389d16 200 #ifndef __CORE_CM4_H_DEPENDANT
mega64 146:03e976389d16 201 #define __CORE_CM4_H_DEPENDANT
mega64 146:03e976389d16 202
mega64 146:03e976389d16 203 #ifdef __cplusplus
mega64 146:03e976389d16 204 extern "C" {
mega64 146:03e976389d16 205 #endif
mega64 146:03e976389d16 206
mega64 146:03e976389d16 207 /* check device defines and use defaults */
mega64 146:03e976389d16 208 #if defined __CHECK_DEVICE_DEFINES
mega64 146:03e976389d16 209 #ifndef __CM4_REV
mega64 146:03e976389d16 210 #define __CM4_REV 0x0000
mega64 146:03e976389d16 211 #warning "__CM4_REV not defined in device header file; using default!"
mega64 146:03e976389d16 212 #endif
mega64 146:03e976389d16 213
mega64 146:03e976389d16 214 #ifndef __FPU_PRESENT
mega64 146:03e976389d16 215 #define __FPU_PRESENT 0
mega64 146:03e976389d16 216 #warning "__FPU_PRESENT not defined in device header file; using default!"
mega64 146:03e976389d16 217 #endif
mega64 146:03e976389d16 218
mega64 146:03e976389d16 219 #ifndef __MPU_PRESENT
mega64 146:03e976389d16 220 #define __MPU_PRESENT 0
mega64 146:03e976389d16 221 #warning "__MPU_PRESENT not defined in device header file; using default!"
mega64 146:03e976389d16 222 #endif
mega64 146:03e976389d16 223
mega64 146:03e976389d16 224 #ifndef __NVIC_PRIO_BITS
mega64 146:03e976389d16 225 #define __NVIC_PRIO_BITS 4
mega64 146:03e976389d16 226 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
mega64 146:03e976389d16 227 #endif
mega64 146:03e976389d16 228
mega64 146:03e976389d16 229 #ifndef __Vendor_SysTickConfig
mega64 146:03e976389d16 230 #define __Vendor_SysTickConfig 0
mega64 146:03e976389d16 231 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
mega64 146:03e976389d16 232 #endif
mega64 146:03e976389d16 233 #endif
mega64 146:03e976389d16 234
mega64 146:03e976389d16 235 /* IO definitions (access restrictions to peripheral registers) */
mega64 146:03e976389d16 236 /**
mega64 146:03e976389d16 237 \defgroup CMSIS_glob_defs CMSIS Global Defines
mega64 146:03e976389d16 238
mega64 146:03e976389d16 239 <strong>IO Type Qualifiers</strong> are used
mega64 146:03e976389d16 240 \li to specify the access to peripheral variables.
mega64 146:03e976389d16 241 \li for automatic generation of peripheral register debug information.
mega64 146:03e976389d16 242 */
mega64 146:03e976389d16 243 #ifdef __cplusplus
mega64 146:03e976389d16 244 #define __I volatile /*!< Defines 'read only' permissions */
mega64 146:03e976389d16 245 #else
mega64 146:03e976389d16 246 #define __I volatile const /*!< Defines 'read only' permissions */
mega64 146:03e976389d16 247 #endif
mega64 146:03e976389d16 248 #define __O volatile /*!< Defines 'write only' permissions */
mega64 146:03e976389d16 249 #define __IO volatile /*!< Defines 'read / write' permissions */
mega64 146:03e976389d16 250
mega64 146:03e976389d16 251 #ifdef __cplusplus
mega64 146:03e976389d16 252 #define __IM volatile /*!< Defines 'read only' permissions */
mega64 146:03e976389d16 253 #else
mega64 146:03e976389d16 254 #define __IM volatile const /*!< Defines 'read only' permissions */
mega64 146:03e976389d16 255 #endif
mega64 146:03e976389d16 256 #define __OM volatile /*!< Defines 'write only' permissions */
mega64 146:03e976389d16 257 #define __IOM volatile /*!< Defines 'read / write' permissions */
mega64 146:03e976389d16 258
mega64 146:03e976389d16 259 /*@} end of group Cortex_M4 */
mega64 146:03e976389d16 260
mega64 146:03e976389d16 261
mega64 146:03e976389d16 262
mega64 146:03e976389d16 263 /*******************************************************************************
mega64 146:03e976389d16 264 * Register Abstraction
mega64 146:03e976389d16 265 Core Register contain:
mega64 146:03e976389d16 266 - Core Register
mega64 146:03e976389d16 267 - Core NVIC Register
mega64 146:03e976389d16 268 - Core SCB Register
mega64 146:03e976389d16 269 - Core SysTick Register
mega64 146:03e976389d16 270 - Core Debug Register
mega64 146:03e976389d16 271 - Core MPU Register
mega64 146:03e976389d16 272 - Core FPU Register
mega64 146:03e976389d16 273 ******************************************************************************/
mega64 146:03e976389d16 274 /** \defgroup CMSIS_core_register Defines and Type Definitions
mega64 146:03e976389d16 275 \brief Type definitions and defines for Cortex-M processor based devices.
mega64 146:03e976389d16 276 */
mega64 146:03e976389d16 277
mega64 146:03e976389d16 278 /** \ingroup CMSIS_core_register
mega64 146:03e976389d16 279 \defgroup CMSIS_CORE Status and Control Registers
mega64 146:03e976389d16 280 \brief Core Register type definitions.
mega64 146:03e976389d16 281 @{
mega64 146:03e976389d16 282 */
mega64 146:03e976389d16 283
mega64 146:03e976389d16 284 /** \brief Union type to access the Application Program Status Register (APSR).
mega64 146:03e976389d16 285 */
mega64 146:03e976389d16 286 typedef union
mega64 146:03e976389d16 287 {
mega64 146:03e976389d16 288 struct
mega64 146:03e976389d16 289 {
mega64 146:03e976389d16 290 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
mega64 146:03e976389d16 291 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
mega64 146:03e976389d16 292 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
mega64 146:03e976389d16 293 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
mega64 146:03e976389d16 294 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
mega64 146:03e976389d16 295 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
mega64 146:03e976389d16 296 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
mega64 146:03e976389d16 297 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
mega64 146:03e976389d16 298 } b; /*!< Structure used for bit access */
mega64 146:03e976389d16 299 uint32_t w; /*!< Type used for word access */
mega64 146:03e976389d16 300 } APSR_Type;
mega64 146:03e976389d16 301
mega64 146:03e976389d16 302 /* APSR Register Definitions */
mega64 146:03e976389d16 303 #define APSR_N_Pos 31 /*!< APSR: N Position */
mega64 146:03e976389d16 304 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
mega64 146:03e976389d16 305
mega64 146:03e976389d16 306 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
mega64 146:03e976389d16 307 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
mega64 146:03e976389d16 308
mega64 146:03e976389d16 309 #define APSR_C_Pos 29 /*!< APSR: C Position */
mega64 146:03e976389d16 310 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
mega64 146:03e976389d16 311
mega64 146:03e976389d16 312 #define APSR_V_Pos 28 /*!< APSR: V Position */
mega64 146:03e976389d16 313 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
mega64 146:03e976389d16 314
mega64 146:03e976389d16 315 #define APSR_Q_Pos 27 /*!< APSR: Q Position */
mega64 146:03e976389d16 316 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
mega64 146:03e976389d16 317
mega64 146:03e976389d16 318 #define APSR_GE_Pos 16 /*!< APSR: GE Position */
mega64 146:03e976389d16 319 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
mega64 146:03e976389d16 320
mega64 146:03e976389d16 321
mega64 146:03e976389d16 322 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
mega64 146:03e976389d16 323 */
mega64 146:03e976389d16 324 typedef union
mega64 146:03e976389d16 325 {
mega64 146:03e976389d16 326 struct
mega64 146:03e976389d16 327 {
mega64 146:03e976389d16 328 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
mega64 146:03e976389d16 329 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
mega64 146:03e976389d16 330 } b; /*!< Structure used for bit access */
mega64 146:03e976389d16 331 uint32_t w; /*!< Type used for word access */
mega64 146:03e976389d16 332 } IPSR_Type;
mega64 146:03e976389d16 333
mega64 146:03e976389d16 334 /* IPSR Register Definitions */
mega64 146:03e976389d16 335 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
mega64 146:03e976389d16 336 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
mega64 146:03e976389d16 337
mega64 146:03e976389d16 338
mega64 146:03e976389d16 339 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
mega64 146:03e976389d16 340 */
mega64 146:03e976389d16 341 typedef union
mega64 146:03e976389d16 342 {
mega64 146:03e976389d16 343 struct
mega64 146:03e976389d16 344 {
mega64 146:03e976389d16 345 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
mega64 146:03e976389d16 346 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
mega64 146:03e976389d16 347 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
mega64 146:03e976389d16 348 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
mega64 146:03e976389d16 349 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
mega64 146:03e976389d16 350 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
mega64 146:03e976389d16 351 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
mega64 146:03e976389d16 352 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
mega64 146:03e976389d16 353 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
mega64 146:03e976389d16 354 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
mega64 146:03e976389d16 355 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
mega64 146:03e976389d16 356 } b; /*!< Structure used for bit access */
mega64 146:03e976389d16 357 uint32_t w; /*!< Type used for word access */
mega64 146:03e976389d16 358 } xPSR_Type;
mega64 146:03e976389d16 359
mega64 146:03e976389d16 360 /* xPSR Register Definitions */
mega64 146:03e976389d16 361 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
mega64 146:03e976389d16 362 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
mega64 146:03e976389d16 363
mega64 146:03e976389d16 364 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
mega64 146:03e976389d16 365 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
mega64 146:03e976389d16 366
mega64 146:03e976389d16 367 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
mega64 146:03e976389d16 368 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
mega64 146:03e976389d16 369
mega64 146:03e976389d16 370 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
mega64 146:03e976389d16 371 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
mega64 146:03e976389d16 372
mega64 146:03e976389d16 373 #define xPSR_Q_Pos 27 /*!< xPSR: Q Position */
mega64 146:03e976389d16 374 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
mega64 146:03e976389d16 375
mega64 146:03e976389d16 376 #define xPSR_IT_Pos 25 /*!< xPSR: IT Position */
mega64 146:03e976389d16 377 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
mega64 146:03e976389d16 378
mega64 146:03e976389d16 379 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
mega64 146:03e976389d16 380 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
mega64 146:03e976389d16 381
mega64 146:03e976389d16 382 #define xPSR_GE_Pos 16 /*!< xPSR: GE Position */
mega64 146:03e976389d16 383 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
mega64 146:03e976389d16 384
mega64 146:03e976389d16 385 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
mega64 146:03e976389d16 386 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
mega64 146:03e976389d16 387
mega64 146:03e976389d16 388
mega64 146:03e976389d16 389 /** \brief Union type to access the Control Registers (CONTROL).
mega64 146:03e976389d16 390 */
mega64 146:03e976389d16 391 typedef union
mega64 146:03e976389d16 392 {
mega64 146:03e976389d16 393 struct
mega64 146:03e976389d16 394 {
mega64 146:03e976389d16 395 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
mega64 146:03e976389d16 396 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
mega64 146:03e976389d16 397 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
mega64 146:03e976389d16 398 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
mega64 146:03e976389d16 399 } b; /*!< Structure used for bit access */
mega64 146:03e976389d16 400 uint32_t w; /*!< Type used for word access */
mega64 146:03e976389d16 401 } CONTROL_Type;
mega64 146:03e976389d16 402
mega64 146:03e976389d16 403 /* CONTROL Register Definitions */
mega64 146:03e976389d16 404 #define CONTROL_FPCA_Pos 2 /*!< CONTROL: FPCA Position */
mega64 146:03e976389d16 405 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
mega64 146:03e976389d16 406
mega64 146:03e976389d16 407 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
mega64 146:03e976389d16 408 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
mega64 146:03e976389d16 409
mega64 146:03e976389d16 410 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
mega64 146:03e976389d16 411 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
mega64 146:03e976389d16 412
mega64 146:03e976389d16 413 /*@} end of group CMSIS_CORE */
mega64 146:03e976389d16 414
mega64 146:03e976389d16 415
mega64 146:03e976389d16 416 /** \ingroup CMSIS_core_register
mega64 146:03e976389d16 417 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
mega64 146:03e976389d16 418 \brief Type definitions for the NVIC Registers
mega64 146:03e976389d16 419 @{
mega64 146:03e976389d16 420 */
mega64 146:03e976389d16 421
mega64 146:03e976389d16 422 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
mega64 146:03e976389d16 423 */
mega64 146:03e976389d16 424 typedef struct
mega64 146:03e976389d16 425 {
mega64 146:03e976389d16 426 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
mega64 146:03e976389d16 427 uint32_t RESERVED0[24];
mega64 146:03e976389d16 428 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
mega64 146:03e976389d16 429 uint32_t RSERVED1[24];
mega64 146:03e976389d16 430 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
mega64 146:03e976389d16 431 uint32_t RESERVED2[24];
mega64 146:03e976389d16 432 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
mega64 146:03e976389d16 433 uint32_t RESERVED3[24];
mega64 146:03e976389d16 434 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
mega64 146:03e976389d16 435 uint32_t RESERVED4[56];
mega64 146:03e976389d16 436 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
mega64 146:03e976389d16 437 uint32_t RESERVED5[644];
mega64 146:03e976389d16 438 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
mega64 146:03e976389d16 439 } NVIC_Type;
mega64 146:03e976389d16 440
mega64 146:03e976389d16 441 /* Software Triggered Interrupt Register Definitions */
mega64 146:03e976389d16 442 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
mega64 146:03e976389d16 443 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
mega64 146:03e976389d16 444
mega64 146:03e976389d16 445 /*@} end of group CMSIS_NVIC */
mega64 146:03e976389d16 446
mega64 146:03e976389d16 447
mega64 146:03e976389d16 448 /** \ingroup CMSIS_core_register
mega64 146:03e976389d16 449 \defgroup CMSIS_SCB System Control Block (SCB)
mega64 146:03e976389d16 450 \brief Type definitions for the System Control Block Registers
mega64 146:03e976389d16 451 @{
mega64 146:03e976389d16 452 */
mega64 146:03e976389d16 453
mega64 146:03e976389d16 454 /** \brief Structure type to access the System Control Block (SCB).
mega64 146:03e976389d16 455 */
mega64 146:03e976389d16 456 typedef struct
mega64 146:03e976389d16 457 {
mega64 146:03e976389d16 458 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
mega64 146:03e976389d16 459 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
mega64 146:03e976389d16 460 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
mega64 146:03e976389d16 461 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
mega64 146:03e976389d16 462 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
mega64 146:03e976389d16 463 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
mega64 146:03e976389d16 464 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
mega64 146:03e976389d16 465 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
mega64 146:03e976389d16 466 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
mega64 146:03e976389d16 467 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
mega64 146:03e976389d16 468 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
mega64 146:03e976389d16 469 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
mega64 146:03e976389d16 470 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
mega64 146:03e976389d16 471 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
mega64 146:03e976389d16 472 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
mega64 146:03e976389d16 473 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
mega64 146:03e976389d16 474 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
mega64 146:03e976389d16 475 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
mega64 146:03e976389d16 476 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
mega64 146:03e976389d16 477 uint32_t RESERVED0[5];
mega64 146:03e976389d16 478 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
mega64 146:03e976389d16 479 } SCB_Type;
mega64 146:03e976389d16 480
mega64 146:03e976389d16 481 /* SCB CPUID Register Definitions */
mega64 146:03e976389d16 482 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
mega64 146:03e976389d16 483 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
mega64 146:03e976389d16 484
mega64 146:03e976389d16 485 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
mega64 146:03e976389d16 486 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
mega64 146:03e976389d16 487
mega64 146:03e976389d16 488 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
mega64 146:03e976389d16 489 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
mega64 146:03e976389d16 490
mega64 146:03e976389d16 491 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
mega64 146:03e976389d16 492 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
mega64 146:03e976389d16 493
mega64 146:03e976389d16 494 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
mega64 146:03e976389d16 495 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
mega64 146:03e976389d16 496
mega64 146:03e976389d16 497 /* SCB Interrupt Control State Register Definitions */
mega64 146:03e976389d16 498 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
mega64 146:03e976389d16 499 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
mega64 146:03e976389d16 500
mega64 146:03e976389d16 501 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
mega64 146:03e976389d16 502 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
mega64 146:03e976389d16 503
mega64 146:03e976389d16 504 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
mega64 146:03e976389d16 505 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
mega64 146:03e976389d16 506
mega64 146:03e976389d16 507 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
mega64 146:03e976389d16 508 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
mega64 146:03e976389d16 509
mega64 146:03e976389d16 510 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
mega64 146:03e976389d16 511 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
mega64 146:03e976389d16 512
mega64 146:03e976389d16 513 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
mega64 146:03e976389d16 514 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
mega64 146:03e976389d16 515
mega64 146:03e976389d16 516 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
mega64 146:03e976389d16 517 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
mega64 146:03e976389d16 518
mega64 146:03e976389d16 519 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
mega64 146:03e976389d16 520 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
mega64 146:03e976389d16 521
mega64 146:03e976389d16 522 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
mega64 146:03e976389d16 523 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
mega64 146:03e976389d16 524
mega64 146:03e976389d16 525 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
mega64 146:03e976389d16 526 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
mega64 146:03e976389d16 527
mega64 146:03e976389d16 528 /* SCB Vector Table Offset Register Definitions */
mega64 146:03e976389d16 529 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
mega64 146:03e976389d16 530 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
mega64 146:03e976389d16 531
mega64 146:03e976389d16 532 /* SCB Application Interrupt and Reset Control Register Definitions */
mega64 146:03e976389d16 533 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
mega64 146:03e976389d16 534 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
mega64 146:03e976389d16 535
mega64 146:03e976389d16 536 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
mega64 146:03e976389d16 537 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
mega64 146:03e976389d16 538
mega64 146:03e976389d16 539 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
mega64 146:03e976389d16 540 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
mega64 146:03e976389d16 541
mega64 146:03e976389d16 542 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
mega64 146:03e976389d16 543 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
mega64 146:03e976389d16 544
mega64 146:03e976389d16 545 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
mega64 146:03e976389d16 546 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
mega64 146:03e976389d16 547
mega64 146:03e976389d16 548 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
mega64 146:03e976389d16 549 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
mega64 146:03e976389d16 550
mega64 146:03e976389d16 551 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
mega64 146:03e976389d16 552 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
mega64 146:03e976389d16 553
mega64 146:03e976389d16 554 /* SCB System Control Register Definitions */
mega64 146:03e976389d16 555 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
mega64 146:03e976389d16 556 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
mega64 146:03e976389d16 557
mega64 146:03e976389d16 558 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
mega64 146:03e976389d16 559 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
mega64 146:03e976389d16 560
mega64 146:03e976389d16 561 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
mega64 146:03e976389d16 562 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
mega64 146:03e976389d16 563
mega64 146:03e976389d16 564 /* SCB Configuration Control Register Definitions */
mega64 146:03e976389d16 565 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
mega64 146:03e976389d16 566 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
mega64 146:03e976389d16 567
mega64 146:03e976389d16 568 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
mega64 146:03e976389d16 569 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
mega64 146:03e976389d16 570
mega64 146:03e976389d16 571 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
mega64 146:03e976389d16 572 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
mega64 146:03e976389d16 573
mega64 146:03e976389d16 574 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
mega64 146:03e976389d16 575 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
mega64 146:03e976389d16 576
mega64 146:03e976389d16 577 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
mega64 146:03e976389d16 578 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
mega64 146:03e976389d16 579
mega64 146:03e976389d16 580 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
mega64 146:03e976389d16 581 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
mega64 146:03e976389d16 582
mega64 146:03e976389d16 583 /* SCB System Handler Control and State Register Definitions */
mega64 146:03e976389d16 584 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
mega64 146:03e976389d16 585 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
mega64 146:03e976389d16 586
mega64 146:03e976389d16 587 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
mega64 146:03e976389d16 588 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
mega64 146:03e976389d16 589
mega64 146:03e976389d16 590 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
mega64 146:03e976389d16 591 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
mega64 146:03e976389d16 592
mega64 146:03e976389d16 593 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
mega64 146:03e976389d16 594 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
mega64 146:03e976389d16 595
mega64 146:03e976389d16 596 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
mega64 146:03e976389d16 597 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
mega64 146:03e976389d16 598
mega64 146:03e976389d16 599 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
mega64 146:03e976389d16 600 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
mega64 146:03e976389d16 601
mega64 146:03e976389d16 602 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
mega64 146:03e976389d16 603 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
mega64 146:03e976389d16 604
mega64 146:03e976389d16 605 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
mega64 146:03e976389d16 606 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
mega64 146:03e976389d16 607
mega64 146:03e976389d16 608 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
mega64 146:03e976389d16 609 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
mega64 146:03e976389d16 610
mega64 146:03e976389d16 611 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
mega64 146:03e976389d16 612 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
mega64 146:03e976389d16 613
mega64 146:03e976389d16 614 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
mega64 146:03e976389d16 615 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
mega64 146:03e976389d16 616
mega64 146:03e976389d16 617 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
mega64 146:03e976389d16 618 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
mega64 146:03e976389d16 619
mega64 146:03e976389d16 620 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
mega64 146:03e976389d16 621 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
mega64 146:03e976389d16 622
mega64 146:03e976389d16 623 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
mega64 146:03e976389d16 624 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
mega64 146:03e976389d16 625
mega64 146:03e976389d16 626 /* SCB Configurable Fault Status Registers Definitions */
mega64 146:03e976389d16 627 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
mega64 146:03e976389d16 628 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
mega64 146:03e976389d16 629
mega64 146:03e976389d16 630 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
mega64 146:03e976389d16 631 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
mega64 146:03e976389d16 632
mega64 146:03e976389d16 633 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
mega64 146:03e976389d16 634 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
mega64 146:03e976389d16 635
mega64 146:03e976389d16 636 /* SCB Hard Fault Status Registers Definitions */
mega64 146:03e976389d16 637 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
mega64 146:03e976389d16 638 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
mega64 146:03e976389d16 639
mega64 146:03e976389d16 640 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
mega64 146:03e976389d16 641 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
mega64 146:03e976389d16 642
mega64 146:03e976389d16 643 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
mega64 146:03e976389d16 644 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
mega64 146:03e976389d16 645
mega64 146:03e976389d16 646 /* SCB Debug Fault Status Register Definitions */
mega64 146:03e976389d16 647 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
mega64 146:03e976389d16 648 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
mega64 146:03e976389d16 649
mega64 146:03e976389d16 650 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
mega64 146:03e976389d16 651 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
mega64 146:03e976389d16 652
mega64 146:03e976389d16 653 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
mega64 146:03e976389d16 654 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
mega64 146:03e976389d16 655
mega64 146:03e976389d16 656 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
mega64 146:03e976389d16 657 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
mega64 146:03e976389d16 658
mega64 146:03e976389d16 659 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
mega64 146:03e976389d16 660 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
mega64 146:03e976389d16 661
mega64 146:03e976389d16 662 /*@} end of group CMSIS_SCB */
mega64 146:03e976389d16 663
mega64 146:03e976389d16 664
mega64 146:03e976389d16 665 /** \ingroup CMSIS_core_register
mega64 146:03e976389d16 666 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
mega64 146:03e976389d16 667 \brief Type definitions for the System Control and ID Register not in the SCB
mega64 146:03e976389d16 668 @{
mega64 146:03e976389d16 669 */
mega64 146:03e976389d16 670
mega64 146:03e976389d16 671 /** \brief Structure type to access the System Control and ID Register not in the SCB.
mega64 146:03e976389d16 672 */
mega64 146:03e976389d16 673 typedef struct
mega64 146:03e976389d16 674 {
mega64 146:03e976389d16 675 uint32_t RESERVED0[1];
mega64 146:03e976389d16 676 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
mega64 146:03e976389d16 677 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
mega64 146:03e976389d16 678 } SCnSCB_Type;
mega64 146:03e976389d16 679
mega64 146:03e976389d16 680 /* Interrupt Controller Type Register Definitions */
mega64 146:03e976389d16 681 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
mega64 146:03e976389d16 682 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
mega64 146:03e976389d16 683
mega64 146:03e976389d16 684 /* Auxiliary Control Register Definitions */
mega64 146:03e976389d16 685 #define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */
mega64 146:03e976389d16 686 #define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
mega64 146:03e976389d16 687
mega64 146:03e976389d16 688 #define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */
mega64 146:03e976389d16 689 #define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
mega64 146:03e976389d16 690
mega64 146:03e976389d16 691 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
mega64 146:03e976389d16 692 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
mega64 146:03e976389d16 693
mega64 146:03e976389d16 694 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
mega64 146:03e976389d16 695 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
mega64 146:03e976389d16 696
mega64 146:03e976389d16 697 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
mega64 146:03e976389d16 698 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
mega64 146:03e976389d16 699
mega64 146:03e976389d16 700 /*@} end of group CMSIS_SCnotSCB */
mega64 146:03e976389d16 701
mega64 146:03e976389d16 702
mega64 146:03e976389d16 703 /** \ingroup CMSIS_core_register
mega64 146:03e976389d16 704 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
mega64 146:03e976389d16 705 \brief Type definitions for the System Timer Registers.
mega64 146:03e976389d16 706 @{
mega64 146:03e976389d16 707 */
mega64 146:03e976389d16 708
mega64 146:03e976389d16 709 /** \brief Structure type to access the System Timer (SysTick).
mega64 146:03e976389d16 710 */
mega64 146:03e976389d16 711 typedef struct
mega64 146:03e976389d16 712 {
mega64 146:03e976389d16 713 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
mega64 146:03e976389d16 714 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
mega64 146:03e976389d16 715 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
mega64 146:03e976389d16 716 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
mega64 146:03e976389d16 717 } SysTick_Type;
mega64 146:03e976389d16 718
mega64 146:03e976389d16 719 /* SysTick Control / Status Register Definitions */
mega64 146:03e976389d16 720 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
mega64 146:03e976389d16 721 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
mega64 146:03e976389d16 722
mega64 146:03e976389d16 723 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
mega64 146:03e976389d16 724 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
mega64 146:03e976389d16 725
mega64 146:03e976389d16 726 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
mega64 146:03e976389d16 727 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
mega64 146:03e976389d16 728
mega64 146:03e976389d16 729 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
mega64 146:03e976389d16 730 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
mega64 146:03e976389d16 731
mega64 146:03e976389d16 732 /* SysTick Reload Register Definitions */
mega64 146:03e976389d16 733 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
mega64 146:03e976389d16 734 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
mega64 146:03e976389d16 735
mega64 146:03e976389d16 736 /* SysTick Current Register Definitions */
mega64 146:03e976389d16 737 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
mega64 146:03e976389d16 738 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
mega64 146:03e976389d16 739
mega64 146:03e976389d16 740 /* SysTick Calibration Register Definitions */
mega64 146:03e976389d16 741 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
mega64 146:03e976389d16 742 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
mega64 146:03e976389d16 743
mega64 146:03e976389d16 744 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
mega64 146:03e976389d16 745 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
mega64 146:03e976389d16 746
mega64 146:03e976389d16 747 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
mega64 146:03e976389d16 748 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
mega64 146:03e976389d16 749
mega64 146:03e976389d16 750 /*@} end of group CMSIS_SysTick */
mega64 146:03e976389d16 751
mega64 146:03e976389d16 752
mega64 146:03e976389d16 753 /** \ingroup CMSIS_core_register
mega64 146:03e976389d16 754 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
mega64 146:03e976389d16 755 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
mega64 146:03e976389d16 756 @{
mega64 146:03e976389d16 757 */
mega64 146:03e976389d16 758
mega64 146:03e976389d16 759 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
mega64 146:03e976389d16 760 */
mega64 146:03e976389d16 761 typedef struct
mega64 146:03e976389d16 762 {
mega64 146:03e976389d16 763 __O union
mega64 146:03e976389d16 764 {
mega64 146:03e976389d16 765 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
mega64 146:03e976389d16 766 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
mega64 146:03e976389d16 767 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
mega64 146:03e976389d16 768 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
mega64 146:03e976389d16 769 uint32_t RESERVED0[864];
mega64 146:03e976389d16 770 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
mega64 146:03e976389d16 771 uint32_t RESERVED1[15];
mega64 146:03e976389d16 772 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
mega64 146:03e976389d16 773 uint32_t RESERVED2[15];
mega64 146:03e976389d16 774 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
mega64 146:03e976389d16 775 uint32_t RESERVED3[29];
mega64 146:03e976389d16 776 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
mega64 146:03e976389d16 777 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
mega64 146:03e976389d16 778 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
mega64 146:03e976389d16 779 uint32_t RESERVED4[43];
mega64 146:03e976389d16 780 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
mega64 146:03e976389d16 781 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
mega64 146:03e976389d16 782 uint32_t RESERVED5[6];
mega64 146:03e976389d16 783 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
mega64 146:03e976389d16 784 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
mega64 146:03e976389d16 785 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
mega64 146:03e976389d16 786 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
mega64 146:03e976389d16 787 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
mega64 146:03e976389d16 788 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
mega64 146:03e976389d16 789 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
mega64 146:03e976389d16 790 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
mega64 146:03e976389d16 791 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
mega64 146:03e976389d16 792 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
mega64 146:03e976389d16 793 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
mega64 146:03e976389d16 794 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
mega64 146:03e976389d16 795 } ITM_Type;
mega64 146:03e976389d16 796
mega64 146:03e976389d16 797 /* ITM Trace Privilege Register Definitions */
mega64 146:03e976389d16 798 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
mega64 146:03e976389d16 799 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
mega64 146:03e976389d16 800
mega64 146:03e976389d16 801 /* ITM Trace Control Register Definitions */
mega64 146:03e976389d16 802 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
mega64 146:03e976389d16 803 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
mega64 146:03e976389d16 804
mega64 146:03e976389d16 805 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
mega64 146:03e976389d16 806 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
mega64 146:03e976389d16 807
mega64 146:03e976389d16 808 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
mega64 146:03e976389d16 809 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
mega64 146:03e976389d16 810
mega64 146:03e976389d16 811 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
mega64 146:03e976389d16 812 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
mega64 146:03e976389d16 813
mega64 146:03e976389d16 814 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
mega64 146:03e976389d16 815 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
mega64 146:03e976389d16 816
mega64 146:03e976389d16 817 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
mega64 146:03e976389d16 818 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
mega64 146:03e976389d16 819
mega64 146:03e976389d16 820 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
mega64 146:03e976389d16 821 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
mega64 146:03e976389d16 822
mega64 146:03e976389d16 823 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
mega64 146:03e976389d16 824 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
mega64 146:03e976389d16 825
mega64 146:03e976389d16 826 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
mega64 146:03e976389d16 827 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
mega64 146:03e976389d16 828
mega64 146:03e976389d16 829 /* ITM Integration Write Register Definitions */
mega64 146:03e976389d16 830 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
mega64 146:03e976389d16 831 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
mega64 146:03e976389d16 832
mega64 146:03e976389d16 833 /* ITM Integration Read Register Definitions */
mega64 146:03e976389d16 834 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
mega64 146:03e976389d16 835 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
mega64 146:03e976389d16 836
mega64 146:03e976389d16 837 /* ITM Integration Mode Control Register Definitions */
mega64 146:03e976389d16 838 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
mega64 146:03e976389d16 839 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
mega64 146:03e976389d16 840
mega64 146:03e976389d16 841 /* ITM Lock Status Register Definitions */
mega64 146:03e976389d16 842 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
mega64 146:03e976389d16 843 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
mega64 146:03e976389d16 844
mega64 146:03e976389d16 845 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
mega64 146:03e976389d16 846 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
mega64 146:03e976389d16 847
mega64 146:03e976389d16 848 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
mega64 146:03e976389d16 849 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
mega64 146:03e976389d16 850
mega64 146:03e976389d16 851 /*@}*/ /* end of group CMSIS_ITM */
mega64 146:03e976389d16 852
mega64 146:03e976389d16 853
mega64 146:03e976389d16 854 /** \ingroup CMSIS_core_register
mega64 146:03e976389d16 855 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
mega64 146:03e976389d16 856 \brief Type definitions for the Data Watchpoint and Trace (DWT)
mega64 146:03e976389d16 857 @{
mega64 146:03e976389d16 858 */
mega64 146:03e976389d16 859
mega64 146:03e976389d16 860 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
mega64 146:03e976389d16 861 */
mega64 146:03e976389d16 862 typedef struct
mega64 146:03e976389d16 863 {
mega64 146:03e976389d16 864 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
mega64 146:03e976389d16 865 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
mega64 146:03e976389d16 866 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
mega64 146:03e976389d16 867 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
mega64 146:03e976389d16 868 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
mega64 146:03e976389d16 869 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
mega64 146:03e976389d16 870 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
mega64 146:03e976389d16 871 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
mega64 146:03e976389d16 872 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
mega64 146:03e976389d16 873 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
mega64 146:03e976389d16 874 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
mega64 146:03e976389d16 875 uint32_t RESERVED0[1];
mega64 146:03e976389d16 876 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
mega64 146:03e976389d16 877 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
mega64 146:03e976389d16 878 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
mega64 146:03e976389d16 879 uint32_t RESERVED1[1];
mega64 146:03e976389d16 880 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
mega64 146:03e976389d16 881 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
mega64 146:03e976389d16 882 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
mega64 146:03e976389d16 883 uint32_t RESERVED2[1];
mega64 146:03e976389d16 884 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
mega64 146:03e976389d16 885 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
mega64 146:03e976389d16 886 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
mega64 146:03e976389d16 887 } DWT_Type;
mega64 146:03e976389d16 888
mega64 146:03e976389d16 889 /* DWT Control Register Definitions */
mega64 146:03e976389d16 890 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
mega64 146:03e976389d16 891 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
mega64 146:03e976389d16 892
mega64 146:03e976389d16 893 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
mega64 146:03e976389d16 894 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
mega64 146:03e976389d16 895
mega64 146:03e976389d16 896 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
mega64 146:03e976389d16 897 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
mega64 146:03e976389d16 898
mega64 146:03e976389d16 899 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
mega64 146:03e976389d16 900 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
mega64 146:03e976389d16 901
mega64 146:03e976389d16 902 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
mega64 146:03e976389d16 903 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
mega64 146:03e976389d16 904
mega64 146:03e976389d16 905 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
mega64 146:03e976389d16 906 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
mega64 146:03e976389d16 907
mega64 146:03e976389d16 908 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
mega64 146:03e976389d16 909 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
mega64 146:03e976389d16 910
mega64 146:03e976389d16 911 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
mega64 146:03e976389d16 912 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
mega64 146:03e976389d16 913
mega64 146:03e976389d16 914 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
mega64 146:03e976389d16 915 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
mega64 146:03e976389d16 916
mega64 146:03e976389d16 917 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
mega64 146:03e976389d16 918 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
mega64 146:03e976389d16 919
mega64 146:03e976389d16 920 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
mega64 146:03e976389d16 921 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
mega64 146:03e976389d16 922
mega64 146:03e976389d16 923 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
mega64 146:03e976389d16 924 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
mega64 146:03e976389d16 925
mega64 146:03e976389d16 926 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
mega64 146:03e976389d16 927 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
mega64 146:03e976389d16 928
mega64 146:03e976389d16 929 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
mega64 146:03e976389d16 930 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
mega64 146:03e976389d16 931
mega64 146:03e976389d16 932 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
mega64 146:03e976389d16 933 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
mega64 146:03e976389d16 934
mega64 146:03e976389d16 935 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
mega64 146:03e976389d16 936 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
mega64 146:03e976389d16 937
mega64 146:03e976389d16 938 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
mega64 146:03e976389d16 939 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
mega64 146:03e976389d16 940
mega64 146:03e976389d16 941 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
mega64 146:03e976389d16 942 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
mega64 146:03e976389d16 943
mega64 146:03e976389d16 944 /* DWT CPI Count Register Definitions */
mega64 146:03e976389d16 945 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
mega64 146:03e976389d16 946 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
mega64 146:03e976389d16 947
mega64 146:03e976389d16 948 /* DWT Exception Overhead Count Register Definitions */
mega64 146:03e976389d16 949 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
mega64 146:03e976389d16 950 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
mega64 146:03e976389d16 951
mega64 146:03e976389d16 952 /* DWT Sleep Count Register Definitions */
mega64 146:03e976389d16 953 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
mega64 146:03e976389d16 954 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
mega64 146:03e976389d16 955
mega64 146:03e976389d16 956 /* DWT LSU Count Register Definitions */
mega64 146:03e976389d16 957 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
mega64 146:03e976389d16 958 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
mega64 146:03e976389d16 959
mega64 146:03e976389d16 960 /* DWT Folded-instruction Count Register Definitions */
mega64 146:03e976389d16 961 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
mega64 146:03e976389d16 962 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
mega64 146:03e976389d16 963
mega64 146:03e976389d16 964 /* DWT Comparator Mask Register Definitions */
mega64 146:03e976389d16 965 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
mega64 146:03e976389d16 966 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
mega64 146:03e976389d16 967
mega64 146:03e976389d16 968 /* DWT Comparator Function Register Definitions */
mega64 146:03e976389d16 969 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
mega64 146:03e976389d16 970 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
mega64 146:03e976389d16 971
mega64 146:03e976389d16 972 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
mega64 146:03e976389d16 973 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
mega64 146:03e976389d16 974
mega64 146:03e976389d16 975 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
mega64 146:03e976389d16 976 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
mega64 146:03e976389d16 977
mega64 146:03e976389d16 978 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
mega64 146:03e976389d16 979 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
mega64 146:03e976389d16 980
mega64 146:03e976389d16 981 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
mega64 146:03e976389d16 982 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
mega64 146:03e976389d16 983
mega64 146:03e976389d16 984 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
mega64 146:03e976389d16 985 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
mega64 146:03e976389d16 986
mega64 146:03e976389d16 987 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
mega64 146:03e976389d16 988 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
mega64 146:03e976389d16 989
mega64 146:03e976389d16 990 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
mega64 146:03e976389d16 991 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
mega64 146:03e976389d16 992
mega64 146:03e976389d16 993 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
mega64 146:03e976389d16 994 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
mega64 146:03e976389d16 995
mega64 146:03e976389d16 996 /*@}*/ /* end of group CMSIS_DWT */
mega64 146:03e976389d16 997
mega64 146:03e976389d16 998
mega64 146:03e976389d16 999 /** \ingroup CMSIS_core_register
mega64 146:03e976389d16 1000 \defgroup CMSIS_TPI Trace Port Interface (TPI)
mega64 146:03e976389d16 1001 \brief Type definitions for the Trace Port Interface (TPI)
mega64 146:03e976389d16 1002 @{
mega64 146:03e976389d16 1003 */
mega64 146:03e976389d16 1004
mega64 146:03e976389d16 1005 /** \brief Structure type to access the Trace Port Interface Register (TPI).
mega64 146:03e976389d16 1006 */
mega64 146:03e976389d16 1007 typedef struct
mega64 146:03e976389d16 1008 {
mega64 146:03e976389d16 1009 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
mega64 146:03e976389d16 1010 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
mega64 146:03e976389d16 1011 uint32_t RESERVED0[2];
mega64 146:03e976389d16 1012 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
mega64 146:03e976389d16 1013 uint32_t RESERVED1[55];
mega64 146:03e976389d16 1014 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
mega64 146:03e976389d16 1015 uint32_t RESERVED2[131];
mega64 146:03e976389d16 1016 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
mega64 146:03e976389d16 1017 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
mega64 146:03e976389d16 1018 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
mega64 146:03e976389d16 1019 uint32_t RESERVED3[759];
mega64 146:03e976389d16 1020 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
mega64 146:03e976389d16 1021 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
mega64 146:03e976389d16 1022 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
mega64 146:03e976389d16 1023 uint32_t RESERVED4[1];
mega64 146:03e976389d16 1024 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
mega64 146:03e976389d16 1025 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
mega64 146:03e976389d16 1026 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
mega64 146:03e976389d16 1027 uint32_t RESERVED5[39];
mega64 146:03e976389d16 1028 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
mega64 146:03e976389d16 1029 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
mega64 146:03e976389d16 1030 uint32_t RESERVED7[8];
mega64 146:03e976389d16 1031 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
mega64 146:03e976389d16 1032 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
mega64 146:03e976389d16 1033 } TPI_Type;
mega64 146:03e976389d16 1034
mega64 146:03e976389d16 1035 /* TPI Asynchronous Clock Prescaler Register Definitions */
mega64 146:03e976389d16 1036 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
mega64 146:03e976389d16 1037 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
mega64 146:03e976389d16 1038
mega64 146:03e976389d16 1039 /* TPI Selected Pin Protocol Register Definitions */
mega64 146:03e976389d16 1040 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
mega64 146:03e976389d16 1041 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
mega64 146:03e976389d16 1042
mega64 146:03e976389d16 1043 /* TPI Formatter and Flush Status Register Definitions */
mega64 146:03e976389d16 1044 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
mega64 146:03e976389d16 1045 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
mega64 146:03e976389d16 1046
mega64 146:03e976389d16 1047 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
mega64 146:03e976389d16 1048 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
mega64 146:03e976389d16 1049
mega64 146:03e976389d16 1050 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
mega64 146:03e976389d16 1051 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
mega64 146:03e976389d16 1052
mega64 146:03e976389d16 1053 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
mega64 146:03e976389d16 1054 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
mega64 146:03e976389d16 1055
mega64 146:03e976389d16 1056 /* TPI Formatter and Flush Control Register Definitions */
mega64 146:03e976389d16 1057 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
mega64 146:03e976389d16 1058 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
mega64 146:03e976389d16 1059
mega64 146:03e976389d16 1060 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
mega64 146:03e976389d16 1061 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
mega64 146:03e976389d16 1062
mega64 146:03e976389d16 1063 /* TPI TRIGGER Register Definitions */
mega64 146:03e976389d16 1064 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
mega64 146:03e976389d16 1065 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
mega64 146:03e976389d16 1066
mega64 146:03e976389d16 1067 /* TPI Integration ETM Data Register Definitions (FIFO0) */
mega64 146:03e976389d16 1068 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
mega64 146:03e976389d16 1069 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
mega64 146:03e976389d16 1070
mega64 146:03e976389d16 1071 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
mega64 146:03e976389d16 1072 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
mega64 146:03e976389d16 1073
mega64 146:03e976389d16 1074 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
mega64 146:03e976389d16 1075 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
mega64 146:03e976389d16 1076
mega64 146:03e976389d16 1077 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
mega64 146:03e976389d16 1078 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
mega64 146:03e976389d16 1079
mega64 146:03e976389d16 1080 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
mega64 146:03e976389d16 1081 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
mega64 146:03e976389d16 1082
mega64 146:03e976389d16 1083 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
mega64 146:03e976389d16 1084 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
mega64 146:03e976389d16 1085
mega64 146:03e976389d16 1086 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
mega64 146:03e976389d16 1087 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
mega64 146:03e976389d16 1088
mega64 146:03e976389d16 1089 /* TPI ITATBCTR2 Register Definitions */
mega64 146:03e976389d16 1090 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
mega64 146:03e976389d16 1091 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
mega64 146:03e976389d16 1092
mega64 146:03e976389d16 1093 /* TPI Integration ITM Data Register Definitions (FIFO1) */
mega64 146:03e976389d16 1094 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
mega64 146:03e976389d16 1095 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
mega64 146:03e976389d16 1096
mega64 146:03e976389d16 1097 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
mega64 146:03e976389d16 1098 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
mega64 146:03e976389d16 1099
mega64 146:03e976389d16 1100 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
mega64 146:03e976389d16 1101 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
mega64 146:03e976389d16 1102
mega64 146:03e976389d16 1103 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
mega64 146:03e976389d16 1104 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
mega64 146:03e976389d16 1105
mega64 146:03e976389d16 1106 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
mega64 146:03e976389d16 1107 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
mega64 146:03e976389d16 1108
mega64 146:03e976389d16 1109 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
mega64 146:03e976389d16 1110 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
mega64 146:03e976389d16 1111
mega64 146:03e976389d16 1112 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
mega64 146:03e976389d16 1113 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
mega64 146:03e976389d16 1114
mega64 146:03e976389d16 1115 /* TPI ITATBCTR0 Register Definitions */
mega64 146:03e976389d16 1116 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
mega64 146:03e976389d16 1117 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
mega64 146:03e976389d16 1118
mega64 146:03e976389d16 1119 /* TPI Integration Mode Control Register Definitions */
mega64 146:03e976389d16 1120 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
mega64 146:03e976389d16 1121 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
mega64 146:03e976389d16 1122
mega64 146:03e976389d16 1123 /* TPI DEVID Register Definitions */
mega64 146:03e976389d16 1124 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
mega64 146:03e976389d16 1125 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
mega64 146:03e976389d16 1126
mega64 146:03e976389d16 1127 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
mega64 146:03e976389d16 1128 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
mega64 146:03e976389d16 1129
mega64 146:03e976389d16 1130 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
mega64 146:03e976389d16 1131 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
mega64 146:03e976389d16 1132
mega64 146:03e976389d16 1133 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
mega64 146:03e976389d16 1134 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
mega64 146:03e976389d16 1135
mega64 146:03e976389d16 1136 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
mega64 146:03e976389d16 1137 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
mega64 146:03e976389d16 1138
mega64 146:03e976389d16 1139 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
mega64 146:03e976389d16 1140 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
mega64 146:03e976389d16 1141
mega64 146:03e976389d16 1142 /* TPI DEVTYPE Register Definitions */
mega64 146:03e976389d16 1143 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
mega64 146:03e976389d16 1144 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
mega64 146:03e976389d16 1145
mega64 146:03e976389d16 1146 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
mega64 146:03e976389d16 1147 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
mega64 146:03e976389d16 1148
mega64 146:03e976389d16 1149 /*@}*/ /* end of group CMSIS_TPI */
mega64 146:03e976389d16 1150
mega64 146:03e976389d16 1151
mega64 146:03e976389d16 1152 #if (__MPU_PRESENT == 1)
mega64 146:03e976389d16 1153 /** \ingroup CMSIS_core_register
mega64 146:03e976389d16 1154 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
mega64 146:03e976389d16 1155 \brief Type definitions for the Memory Protection Unit (MPU)
mega64 146:03e976389d16 1156 @{
mega64 146:03e976389d16 1157 */
mega64 146:03e976389d16 1158
mega64 146:03e976389d16 1159 /** \brief Structure type to access the Memory Protection Unit (MPU).
mega64 146:03e976389d16 1160 */
mega64 146:03e976389d16 1161 typedef struct
mega64 146:03e976389d16 1162 {
mega64 146:03e976389d16 1163 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
mega64 146:03e976389d16 1164 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
mega64 146:03e976389d16 1165 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
mega64 146:03e976389d16 1166 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
mega64 146:03e976389d16 1167 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
mega64 146:03e976389d16 1168 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
mega64 146:03e976389d16 1169 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
mega64 146:03e976389d16 1170 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
mega64 146:03e976389d16 1171 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
mega64 146:03e976389d16 1172 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
mega64 146:03e976389d16 1173 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
mega64 146:03e976389d16 1174 } MPU_Type;
mega64 146:03e976389d16 1175
mega64 146:03e976389d16 1176 /* MPU Type Register */
mega64 146:03e976389d16 1177 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
mega64 146:03e976389d16 1178 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
mega64 146:03e976389d16 1179
mega64 146:03e976389d16 1180 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
mega64 146:03e976389d16 1181 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
mega64 146:03e976389d16 1182
mega64 146:03e976389d16 1183 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
mega64 146:03e976389d16 1184 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
mega64 146:03e976389d16 1185
mega64 146:03e976389d16 1186 /* MPU Control Register */
mega64 146:03e976389d16 1187 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
mega64 146:03e976389d16 1188 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
mega64 146:03e976389d16 1189
mega64 146:03e976389d16 1190 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
mega64 146:03e976389d16 1191 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
mega64 146:03e976389d16 1192
mega64 146:03e976389d16 1193 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
mega64 146:03e976389d16 1194 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
mega64 146:03e976389d16 1195
mega64 146:03e976389d16 1196 /* MPU Region Number Register */
mega64 146:03e976389d16 1197 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
mega64 146:03e976389d16 1198 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
mega64 146:03e976389d16 1199
mega64 146:03e976389d16 1200 /* MPU Region Base Address Register */
mega64 146:03e976389d16 1201 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
mega64 146:03e976389d16 1202 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
mega64 146:03e976389d16 1203
mega64 146:03e976389d16 1204 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
mega64 146:03e976389d16 1205 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
mega64 146:03e976389d16 1206
mega64 146:03e976389d16 1207 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
mega64 146:03e976389d16 1208 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
mega64 146:03e976389d16 1209
mega64 146:03e976389d16 1210 /* MPU Region Attribute and Size Register */
mega64 146:03e976389d16 1211 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
mega64 146:03e976389d16 1212 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
mega64 146:03e976389d16 1213
mega64 146:03e976389d16 1214 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
mega64 146:03e976389d16 1215 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
mega64 146:03e976389d16 1216
mega64 146:03e976389d16 1217 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
mega64 146:03e976389d16 1218 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
mega64 146:03e976389d16 1219
mega64 146:03e976389d16 1220 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
mega64 146:03e976389d16 1221 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
mega64 146:03e976389d16 1222
mega64 146:03e976389d16 1223 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
mega64 146:03e976389d16 1224 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
mega64 146:03e976389d16 1225
mega64 146:03e976389d16 1226 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
mega64 146:03e976389d16 1227 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
mega64 146:03e976389d16 1228
mega64 146:03e976389d16 1229 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
mega64 146:03e976389d16 1230 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
mega64 146:03e976389d16 1231
mega64 146:03e976389d16 1232 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
mega64 146:03e976389d16 1233 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
mega64 146:03e976389d16 1234
mega64 146:03e976389d16 1235 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
mega64 146:03e976389d16 1236 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
mega64 146:03e976389d16 1237
mega64 146:03e976389d16 1238 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
mega64 146:03e976389d16 1239 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
mega64 146:03e976389d16 1240
mega64 146:03e976389d16 1241 /*@} end of group CMSIS_MPU */
mega64 146:03e976389d16 1242 #endif
mega64 146:03e976389d16 1243
mega64 146:03e976389d16 1244
mega64 146:03e976389d16 1245 #if (__FPU_PRESENT == 1)
mega64 146:03e976389d16 1246 /** \ingroup CMSIS_core_register
mega64 146:03e976389d16 1247 \defgroup CMSIS_FPU Floating Point Unit (FPU)
mega64 146:03e976389d16 1248 \brief Type definitions for the Floating Point Unit (FPU)
mega64 146:03e976389d16 1249 @{
mega64 146:03e976389d16 1250 */
mega64 146:03e976389d16 1251
mega64 146:03e976389d16 1252 /** \brief Structure type to access the Floating Point Unit (FPU).
mega64 146:03e976389d16 1253 */
mega64 146:03e976389d16 1254 typedef struct
mega64 146:03e976389d16 1255 {
mega64 146:03e976389d16 1256 uint32_t RESERVED0[1];
mega64 146:03e976389d16 1257 __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
mega64 146:03e976389d16 1258 __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
mega64 146:03e976389d16 1259 __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
mega64 146:03e976389d16 1260 __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
mega64 146:03e976389d16 1261 __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
mega64 146:03e976389d16 1262 } FPU_Type;
mega64 146:03e976389d16 1263
mega64 146:03e976389d16 1264 /* Floating-Point Context Control Register */
mega64 146:03e976389d16 1265 #define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */
mega64 146:03e976389d16 1266 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
mega64 146:03e976389d16 1267
mega64 146:03e976389d16 1268 #define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */
mega64 146:03e976389d16 1269 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
mega64 146:03e976389d16 1270
mega64 146:03e976389d16 1271 #define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */
mega64 146:03e976389d16 1272 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
mega64 146:03e976389d16 1273
mega64 146:03e976389d16 1274 #define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */
mega64 146:03e976389d16 1275 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
mega64 146:03e976389d16 1276
mega64 146:03e976389d16 1277 #define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */
mega64 146:03e976389d16 1278 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
mega64 146:03e976389d16 1279
mega64 146:03e976389d16 1280 #define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */
mega64 146:03e976389d16 1281 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
mega64 146:03e976389d16 1282
mega64 146:03e976389d16 1283 #define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */
mega64 146:03e976389d16 1284 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
mega64 146:03e976389d16 1285
mega64 146:03e976389d16 1286 #define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */
mega64 146:03e976389d16 1287 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
mega64 146:03e976389d16 1288
mega64 146:03e976389d16 1289 #define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */
mega64 146:03e976389d16 1290 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
mega64 146:03e976389d16 1291
mega64 146:03e976389d16 1292 /* Floating-Point Context Address Register */
mega64 146:03e976389d16 1293 #define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */
mega64 146:03e976389d16 1294 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
mega64 146:03e976389d16 1295
mega64 146:03e976389d16 1296 /* Floating-Point Default Status Control Register */
mega64 146:03e976389d16 1297 #define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */
mega64 146:03e976389d16 1298 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
mega64 146:03e976389d16 1299
mega64 146:03e976389d16 1300 #define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */
mega64 146:03e976389d16 1301 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
mega64 146:03e976389d16 1302
mega64 146:03e976389d16 1303 #define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */
mega64 146:03e976389d16 1304 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
mega64 146:03e976389d16 1305
mega64 146:03e976389d16 1306 #define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */
mega64 146:03e976389d16 1307 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
mega64 146:03e976389d16 1308
mega64 146:03e976389d16 1309 /* Media and FP Feature Register 0 */
mega64 146:03e976389d16 1310 #define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */
mega64 146:03e976389d16 1311 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
mega64 146:03e976389d16 1312
mega64 146:03e976389d16 1313 #define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */
mega64 146:03e976389d16 1314 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
mega64 146:03e976389d16 1315
mega64 146:03e976389d16 1316 #define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */
mega64 146:03e976389d16 1317 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
mega64 146:03e976389d16 1318
mega64 146:03e976389d16 1319 #define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */
mega64 146:03e976389d16 1320 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
mega64 146:03e976389d16 1321
mega64 146:03e976389d16 1322 #define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */
mega64 146:03e976389d16 1323 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
mega64 146:03e976389d16 1324
mega64 146:03e976389d16 1325 #define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */
mega64 146:03e976389d16 1326 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
mega64 146:03e976389d16 1327
mega64 146:03e976389d16 1328 #define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */
mega64 146:03e976389d16 1329 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
mega64 146:03e976389d16 1330
mega64 146:03e976389d16 1331 #define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */
mega64 146:03e976389d16 1332 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
mega64 146:03e976389d16 1333
mega64 146:03e976389d16 1334 /* Media and FP Feature Register 1 */
mega64 146:03e976389d16 1335 #define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */
mega64 146:03e976389d16 1336 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
mega64 146:03e976389d16 1337
mega64 146:03e976389d16 1338 #define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */
mega64 146:03e976389d16 1339 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
mega64 146:03e976389d16 1340
mega64 146:03e976389d16 1341 #define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */
mega64 146:03e976389d16 1342 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
mega64 146:03e976389d16 1343
mega64 146:03e976389d16 1344 #define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */
mega64 146:03e976389d16 1345 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
mega64 146:03e976389d16 1346
mega64 146:03e976389d16 1347 /*@} end of group CMSIS_FPU */
mega64 146:03e976389d16 1348 #endif
mega64 146:03e976389d16 1349
mega64 146:03e976389d16 1350
mega64 146:03e976389d16 1351 /** \ingroup CMSIS_core_register
mega64 146:03e976389d16 1352 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
mega64 146:03e976389d16 1353 \brief Type definitions for the Core Debug Registers
mega64 146:03e976389d16 1354 @{
mega64 146:03e976389d16 1355 */
mega64 146:03e976389d16 1356
mega64 146:03e976389d16 1357 /** \brief Structure type to access the Core Debug Register (CoreDebug).
mega64 146:03e976389d16 1358 */
mega64 146:03e976389d16 1359 typedef struct
mega64 146:03e976389d16 1360 {
mega64 146:03e976389d16 1361 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
mega64 146:03e976389d16 1362 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
mega64 146:03e976389d16 1363 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
mega64 146:03e976389d16 1364 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
mega64 146:03e976389d16 1365 } CoreDebug_Type;
mega64 146:03e976389d16 1366
mega64 146:03e976389d16 1367 /* Debug Halting Control and Status Register */
mega64 146:03e976389d16 1368 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
mega64 146:03e976389d16 1369 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
mega64 146:03e976389d16 1370
mega64 146:03e976389d16 1371 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
mega64 146:03e976389d16 1372 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
mega64 146:03e976389d16 1373
mega64 146:03e976389d16 1374 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
mega64 146:03e976389d16 1375 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
mega64 146:03e976389d16 1376
mega64 146:03e976389d16 1377 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
mega64 146:03e976389d16 1378 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
mega64 146:03e976389d16 1379
mega64 146:03e976389d16 1380 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
mega64 146:03e976389d16 1381 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
mega64 146:03e976389d16 1382
mega64 146:03e976389d16 1383 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
mega64 146:03e976389d16 1384 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
mega64 146:03e976389d16 1385
mega64 146:03e976389d16 1386 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
mega64 146:03e976389d16 1387 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
mega64 146:03e976389d16 1388
mega64 146:03e976389d16 1389 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
mega64 146:03e976389d16 1390 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
mega64 146:03e976389d16 1391
mega64 146:03e976389d16 1392 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
mega64 146:03e976389d16 1393 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
mega64 146:03e976389d16 1394
mega64 146:03e976389d16 1395 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
mega64 146:03e976389d16 1396 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
mega64 146:03e976389d16 1397
mega64 146:03e976389d16 1398 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
mega64 146:03e976389d16 1399 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
mega64 146:03e976389d16 1400
mega64 146:03e976389d16 1401 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
mega64 146:03e976389d16 1402 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
mega64 146:03e976389d16 1403
mega64 146:03e976389d16 1404 /* Debug Core Register Selector Register */
mega64 146:03e976389d16 1405 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
mega64 146:03e976389d16 1406 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
mega64 146:03e976389d16 1407
mega64 146:03e976389d16 1408 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
mega64 146:03e976389d16 1409 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
mega64 146:03e976389d16 1410
mega64 146:03e976389d16 1411 /* Debug Exception and Monitor Control Register */
mega64 146:03e976389d16 1412 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
mega64 146:03e976389d16 1413 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
mega64 146:03e976389d16 1414
mega64 146:03e976389d16 1415 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
mega64 146:03e976389d16 1416 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
mega64 146:03e976389d16 1417
mega64 146:03e976389d16 1418 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
mega64 146:03e976389d16 1419 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
mega64 146:03e976389d16 1420
mega64 146:03e976389d16 1421 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
mega64 146:03e976389d16 1422 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
mega64 146:03e976389d16 1423
mega64 146:03e976389d16 1424 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
mega64 146:03e976389d16 1425 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
mega64 146:03e976389d16 1426
mega64 146:03e976389d16 1427 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
mega64 146:03e976389d16 1428 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
mega64 146:03e976389d16 1429
mega64 146:03e976389d16 1430 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
mega64 146:03e976389d16 1431 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
mega64 146:03e976389d16 1432
mega64 146:03e976389d16 1433 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
mega64 146:03e976389d16 1434 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
mega64 146:03e976389d16 1435
mega64 146:03e976389d16 1436 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
mega64 146:03e976389d16 1437 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
mega64 146:03e976389d16 1438
mega64 146:03e976389d16 1439 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
mega64 146:03e976389d16 1440 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
mega64 146:03e976389d16 1441
mega64 146:03e976389d16 1442 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
mega64 146:03e976389d16 1443 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
mega64 146:03e976389d16 1444
mega64 146:03e976389d16 1445 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
mega64 146:03e976389d16 1446 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
mega64 146:03e976389d16 1447
mega64 146:03e976389d16 1448 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
mega64 146:03e976389d16 1449 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
mega64 146:03e976389d16 1450
mega64 146:03e976389d16 1451 /*@} end of group CMSIS_CoreDebug */
mega64 146:03e976389d16 1452
mega64 146:03e976389d16 1453
mega64 146:03e976389d16 1454 /** \ingroup CMSIS_core_register
mega64 146:03e976389d16 1455 \defgroup CMSIS_core_base Core Definitions
mega64 146:03e976389d16 1456 \brief Definitions for base addresses, unions, and structures.
mega64 146:03e976389d16 1457 @{
mega64 146:03e976389d16 1458 */
mega64 146:03e976389d16 1459
mega64 146:03e976389d16 1460 /* Memory mapping of Cortex-M4 Hardware */
mega64 146:03e976389d16 1461 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
mega64 146:03e976389d16 1462 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
mega64 146:03e976389d16 1463 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
mega64 146:03e976389d16 1464 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
mega64 146:03e976389d16 1465 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
mega64 146:03e976389d16 1466 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
mega64 146:03e976389d16 1467 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
mega64 146:03e976389d16 1468 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
mega64 146:03e976389d16 1469
mega64 146:03e976389d16 1470 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
mega64 146:03e976389d16 1471 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
mega64 146:03e976389d16 1472 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
mega64 146:03e976389d16 1473 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
mega64 146:03e976389d16 1474 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
mega64 146:03e976389d16 1475 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
mega64 146:03e976389d16 1476 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
mega64 146:03e976389d16 1477 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
mega64 146:03e976389d16 1478
mega64 146:03e976389d16 1479 #if (__MPU_PRESENT == 1)
mega64 146:03e976389d16 1480 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
mega64 146:03e976389d16 1481 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
mega64 146:03e976389d16 1482 #endif
mega64 146:03e976389d16 1483
mega64 146:03e976389d16 1484 #if (__FPU_PRESENT == 1)
mega64 146:03e976389d16 1485 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
mega64 146:03e976389d16 1486 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
mega64 146:03e976389d16 1487 #endif
mega64 146:03e976389d16 1488
mega64 146:03e976389d16 1489 /*@} */
mega64 146:03e976389d16 1490
mega64 146:03e976389d16 1491
mega64 146:03e976389d16 1492
mega64 146:03e976389d16 1493 /*******************************************************************************
mega64 146:03e976389d16 1494 * Hardware Abstraction Layer
mega64 146:03e976389d16 1495 Core Function Interface contains:
mega64 146:03e976389d16 1496 - Core NVIC Functions
mega64 146:03e976389d16 1497 - Core SysTick Functions
mega64 146:03e976389d16 1498 - Core Debug Functions
mega64 146:03e976389d16 1499 - Core Register Access Functions
mega64 146:03e976389d16 1500 ******************************************************************************/
mega64 146:03e976389d16 1501 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
mega64 146:03e976389d16 1502 */
mega64 146:03e976389d16 1503
mega64 146:03e976389d16 1504
mega64 146:03e976389d16 1505
mega64 146:03e976389d16 1506 /* ########################## NVIC functions #################################### */
mega64 146:03e976389d16 1507 /** \ingroup CMSIS_Core_FunctionInterface
mega64 146:03e976389d16 1508 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
mega64 146:03e976389d16 1509 \brief Functions that manage interrupts and exceptions via the NVIC.
mega64 146:03e976389d16 1510 @{
mega64 146:03e976389d16 1511 */
mega64 146:03e976389d16 1512
mega64 146:03e976389d16 1513 #ifdef CMSIS_NVIC_VIRTUAL
mega64 146:03e976389d16 1514 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
mega64 146:03e976389d16 1515 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
mega64 146:03e976389d16 1516 #endif
mega64 146:03e976389d16 1517 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
mega64 146:03e976389d16 1518 #else
mega64 146:03e976389d16 1519 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
mega64 146:03e976389d16 1520 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
mega64 146:03e976389d16 1521 #define NVIC_EnableIRQ __NVIC_EnableIRQ
mega64 146:03e976389d16 1522 #define NVIC_DisableIRQ __NVIC_DisableIRQ
mega64 146:03e976389d16 1523 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
mega64 146:03e976389d16 1524 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
mega64 146:03e976389d16 1525 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
mega64 146:03e976389d16 1526 #define NVIC_GetActive __NVIC_GetActive
mega64 146:03e976389d16 1527 #define NVIC_SetPriority __NVIC_SetPriority
mega64 146:03e976389d16 1528 #define NVIC_GetPriority __NVIC_GetPriority
mega64 146:03e976389d16 1529 #define NVIC_SystemReset __NVIC_SystemReset
mega64 146:03e976389d16 1530 #endif /* CMSIS_NVIC_VIRTUAL */
mega64 146:03e976389d16 1531
mega64 146:03e976389d16 1532 #ifdef CMSIS_VECTAB_VIRTUAL
mega64 146:03e976389d16 1533 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
mega64 146:03e976389d16 1534 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
mega64 146:03e976389d16 1535 #endif
mega64 146:03e976389d16 1536 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
mega64 146:03e976389d16 1537 #else
mega64 146:03e976389d16 1538 #define NVIC_SetVector __NVIC_SetVector
mega64 146:03e976389d16 1539 #define NVIC_GetVector __NVIC_GetVector
mega64 146:03e976389d16 1540 #endif /* CMSIS_VECTAB_VIRTUAL */
mega64 146:03e976389d16 1541
mega64 146:03e976389d16 1542
mega64 146:03e976389d16 1543 /** \brief Set Priority Grouping
mega64 146:03e976389d16 1544
mega64 146:03e976389d16 1545 The function sets the priority grouping field using the required unlock sequence.
mega64 146:03e976389d16 1546 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
mega64 146:03e976389d16 1547 Only values from 0..7 are used.
mega64 146:03e976389d16 1548 In case of a conflict between priority grouping and available
mega64 146:03e976389d16 1549 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
mega64 146:03e976389d16 1550
mega64 146:03e976389d16 1551 \param [in] PriorityGroup Priority grouping field.
mega64 146:03e976389d16 1552 */
mega64 146:03e976389d16 1553 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
mega64 146:03e976389d16 1554 {
mega64 146:03e976389d16 1555 uint32_t reg_value;
mega64 146:03e976389d16 1556 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
mega64 146:03e976389d16 1557
mega64 146:03e976389d16 1558 reg_value = SCB->AIRCR; /* read old register configuration */
mega64 146:03e976389d16 1559 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
mega64 146:03e976389d16 1560 reg_value = (reg_value |
mega64 146:03e976389d16 1561 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
mega64 146:03e976389d16 1562 (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
mega64 146:03e976389d16 1563 SCB->AIRCR = reg_value;
mega64 146:03e976389d16 1564 }
mega64 146:03e976389d16 1565
mega64 146:03e976389d16 1566
mega64 146:03e976389d16 1567 /** \brief Get Priority Grouping
mega64 146:03e976389d16 1568
mega64 146:03e976389d16 1569 The function reads the priority grouping field from the NVIC Interrupt Controller.
mega64 146:03e976389d16 1570
mega64 146:03e976389d16 1571 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
mega64 146:03e976389d16 1572 */
mega64 146:03e976389d16 1573 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
mega64 146:03e976389d16 1574 {
mega64 146:03e976389d16 1575 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
mega64 146:03e976389d16 1576 }
mega64 146:03e976389d16 1577
mega64 146:03e976389d16 1578
mega64 146:03e976389d16 1579 /** \brief Enable External Interrupt
mega64 146:03e976389d16 1580
mega64 146:03e976389d16 1581 The function enables a device-specific interrupt in the NVIC interrupt controller.
mega64 146:03e976389d16 1582
mega64 146:03e976389d16 1583 \param [in] IRQn External interrupt number. Value cannot be negative.
mega64 146:03e976389d16 1584 */
mega64 146:03e976389d16 1585 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
mega64 146:03e976389d16 1586 {
mega64 146:03e976389d16 1587 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
mega64 146:03e976389d16 1588 }
mega64 146:03e976389d16 1589
mega64 146:03e976389d16 1590
mega64 146:03e976389d16 1591 /** \brief Disable External Interrupt
mega64 146:03e976389d16 1592
mega64 146:03e976389d16 1593 The function disables a device-specific interrupt in the NVIC interrupt controller.
mega64 146:03e976389d16 1594
mega64 146:03e976389d16 1595 \param [in] IRQn External interrupt number. Value cannot be negative.
mega64 146:03e976389d16 1596 */
mega64 146:03e976389d16 1597 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
mega64 146:03e976389d16 1598 {
mega64 146:03e976389d16 1599 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
mega64 146:03e976389d16 1600 __DSB();
mega64 146:03e976389d16 1601 __ISB();
mega64 146:03e976389d16 1602 }
mega64 146:03e976389d16 1603
mega64 146:03e976389d16 1604
mega64 146:03e976389d16 1605 /** \brief Get Pending Interrupt
mega64 146:03e976389d16 1606
mega64 146:03e976389d16 1607 The function reads the pending register in the NVIC and returns the pending bit
mega64 146:03e976389d16 1608 for the specified interrupt.
mega64 146:03e976389d16 1609
mega64 146:03e976389d16 1610 \param [in] IRQn Interrupt number.
mega64 146:03e976389d16 1611
mega64 146:03e976389d16 1612 \return 0 Interrupt status is not pending.
mega64 146:03e976389d16 1613 \return 1 Interrupt status is pending.
mega64 146:03e976389d16 1614 */
mega64 146:03e976389d16 1615 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
mega64 146:03e976389d16 1616 {
mega64 146:03e976389d16 1617 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
mega64 146:03e976389d16 1618 }
mega64 146:03e976389d16 1619
mega64 146:03e976389d16 1620
mega64 146:03e976389d16 1621 /** \brief Set Pending Interrupt
mega64 146:03e976389d16 1622
mega64 146:03e976389d16 1623 The function sets the pending bit of an external interrupt.
mega64 146:03e976389d16 1624
mega64 146:03e976389d16 1625 \param [in] IRQn Interrupt number. Value cannot be negative.
mega64 146:03e976389d16 1626 */
mega64 146:03e976389d16 1627 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
mega64 146:03e976389d16 1628 {
mega64 146:03e976389d16 1629 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
mega64 146:03e976389d16 1630 }
mega64 146:03e976389d16 1631
mega64 146:03e976389d16 1632
mega64 146:03e976389d16 1633 /** \brief Clear Pending Interrupt
mega64 146:03e976389d16 1634
mega64 146:03e976389d16 1635 The function clears the pending bit of an external interrupt.
mega64 146:03e976389d16 1636
mega64 146:03e976389d16 1637 \param [in] IRQn External interrupt number. Value cannot be negative.
mega64 146:03e976389d16 1638 */
mega64 146:03e976389d16 1639 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
mega64 146:03e976389d16 1640 {
mega64 146:03e976389d16 1641 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
mega64 146:03e976389d16 1642 }
mega64 146:03e976389d16 1643
mega64 146:03e976389d16 1644
mega64 146:03e976389d16 1645 /** \brief Get Active Interrupt
mega64 146:03e976389d16 1646
mega64 146:03e976389d16 1647 The function reads the active register in NVIC and returns the active bit.
mega64 146:03e976389d16 1648
mega64 146:03e976389d16 1649 \param [in] IRQn Interrupt number.
mega64 146:03e976389d16 1650
mega64 146:03e976389d16 1651 \return 0 Interrupt status is not active.
mega64 146:03e976389d16 1652 \return 1 Interrupt status is active.
mega64 146:03e976389d16 1653 */
mega64 146:03e976389d16 1654 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
mega64 146:03e976389d16 1655 {
mega64 146:03e976389d16 1656 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
mega64 146:03e976389d16 1657 }
mega64 146:03e976389d16 1658
mega64 146:03e976389d16 1659
mega64 146:03e976389d16 1660 /** \brief Set Interrupt Priority
mega64 146:03e976389d16 1661
mega64 146:03e976389d16 1662 The function sets the priority of an interrupt.
mega64 146:03e976389d16 1663
mega64 146:03e976389d16 1664 \note The priority cannot be set for every core interrupt.
mega64 146:03e976389d16 1665
mega64 146:03e976389d16 1666 \param [in] IRQn Interrupt number.
mega64 146:03e976389d16 1667 \param [in] priority Priority to set.
mega64 146:03e976389d16 1668 */
mega64 146:03e976389d16 1669 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
mega64 146:03e976389d16 1670 {
mega64 146:03e976389d16 1671 if((int32_t)IRQn < 0) {
mega64 146:03e976389d16 1672 SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
mega64 146:03e976389d16 1673 }
mega64 146:03e976389d16 1674 else {
mega64 146:03e976389d16 1675 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
mega64 146:03e976389d16 1676 }
mega64 146:03e976389d16 1677 }
mega64 146:03e976389d16 1678
mega64 146:03e976389d16 1679
mega64 146:03e976389d16 1680 /** \brief Get Interrupt Priority
mega64 146:03e976389d16 1681
mega64 146:03e976389d16 1682 The function reads the priority of an interrupt. The interrupt
mega64 146:03e976389d16 1683 number can be positive to specify an external (device specific)
mega64 146:03e976389d16 1684 interrupt, or negative to specify an internal (core) interrupt.
mega64 146:03e976389d16 1685
mega64 146:03e976389d16 1686
mega64 146:03e976389d16 1687 \param [in] IRQn Interrupt number.
mega64 146:03e976389d16 1688 \return Interrupt Priority. Value is aligned automatically to the implemented
mega64 146:03e976389d16 1689 priority bits of the microcontroller.
mega64 146:03e976389d16 1690 */
mega64 146:03e976389d16 1691 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
mega64 146:03e976389d16 1692 {
mega64 146:03e976389d16 1693
mega64 146:03e976389d16 1694 if((int32_t)IRQn < 0) {
mega64 146:03e976389d16 1695 return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
mega64 146:03e976389d16 1696 }
mega64 146:03e976389d16 1697 else {
mega64 146:03e976389d16 1698 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
mega64 146:03e976389d16 1699 }
mega64 146:03e976389d16 1700 }
mega64 146:03e976389d16 1701
mega64 146:03e976389d16 1702
mega64 146:03e976389d16 1703 /** \brief Encode Priority
mega64 146:03e976389d16 1704
mega64 146:03e976389d16 1705 The function encodes the priority for an interrupt with the given priority group,
mega64 146:03e976389d16 1706 preemptive priority value, and subpriority value.
mega64 146:03e976389d16 1707 In case of a conflict between priority grouping and available
mega64 146:03e976389d16 1708 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
mega64 146:03e976389d16 1709
mega64 146:03e976389d16 1710 \param [in] PriorityGroup Used priority group.
mega64 146:03e976389d16 1711 \param [in] PreemptPriority Preemptive priority value (starting from 0).
mega64 146:03e976389d16 1712 \param [in] SubPriority Subpriority value (starting from 0).
mega64 146:03e976389d16 1713 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
mega64 146:03e976389d16 1714 */
mega64 146:03e976389d16 1715 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
mega64 146:03e976389d16 1716 {
mega64 146:03e976389d16 1717 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
mega64 146:03e976389d16 1718 uint32_t PreemptPriorityBits;
mega64 146:03e976389d16 1719 uint32_t SubPriorityBits;
mega64 146:03e976389d16 1720
mega64 146:03e976389d16 1721 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
mega64 146:03e976389d16 1722 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
mega64 146:03e976389d16 1723
mega64 146:03e976389d16 1724 return (
mega64 146:03e976389d16 1725 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
mega64 146:03e976389d16 1726 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
mega64 146:03e976389d16 1727 );
mega64 146:03e976389d16 1728 }
mega64 146:03e976389d16 1729
mega64 146:03e976389d16 1730
mega64 146:03e976389d16 1731 /** \brief Decode Priority
mega64 146:03e976389d16 1732
mega64 146:03e976389d16 1733 The function decodes an interrupt priority value with a given priority group to
mega64 146:03e976389d16 1734 preemptive priority value and subpriority value.
mega64 146:03e976389d16 1735 In case of a conflict between priority grouping and available
mega64 146:03e976389d16 1736 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
mega64 146:03e976389d16 1737
mega64 146:03e976389d16 1738 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
mega64 146:03e976389d16 1739 \param [in] PriorityGroup Used priority group.
mega64 146:03e976389d16 1740 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
mega64 146:03e976389d16 1741 \param [out] pSubPriority Subpriority value (starting from 0).
mega64 146:03e976389d16 1742 */
mega64 146:03e976389d16 1743 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
mega64 146:03e976389d16 1744 {
mega64 146:03e976389d16 1745 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
mega64 146:03e976389d16 1746 uint32_t PreemptPriorityBits;
mega64 146:03e976389d16 1747 uint32_t SubPriorityBits;
mega64 146:03e976389d16 1748
mega64 146:03e976389d16 1749 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
mega64 146:03e976389d16 1750 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
mega64 146:03e976389d16 1751
mega64 146:03e976389d16 1752 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
mega64 146:03e976389d16 1753 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
mega64 146:03e976389d16 1754 }
mega64 146:03e976389d16 1755
mega64 146:03e976389d16 1756
mega64 146:03e976389d16 1757 /** \brief System Reset
mega64 146:03e976389d16 1758
mega64 146:03e976389d16 1759 The function initiates a system reset request to reset the MCU.
mega64 146:03e976389d16 1760 */
mega64 146:03e976389d16 1761 __STATIC_INLINE void __NVIC_SystemReset(void)
mega64 146:03e976389d16 1762 {
mega64 146:03e976389d16 1763 __DSB(); /* Ensure all outstanding memory accesses included
mega64 146:03e976389d16 1764 buffered write are completed before reset */
mega64 146:03e976389d16 1765 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
mega64 146:03e976389d16 1766 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
mega64 146:03e976389d16 1767 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
mega64 146:03e976389d16 1768 __DSB(); /* Ensure completion of memory access */
mega64 146:03e976389d16 1769 while(1) { __NOP(); } /* wait until reset */
mega64 146:03e976389d16 1770 }
mega64 146:03e976389d16 1771
mega64 146:03e976389d16 1772 /*@} end of CMSIS_Core_NVICFunctions */
mega64 146:03e976389d16 1773
mega64 146:03e976389d16 1774
mega64 146:03e976389d16 1775
mega64 146:03e976389d16 1776 /* ################################## SysTick function ############################################ */
mega64 146:03e976389d16 1777 /** \ingroup CMSIS_Core_FunctionInterface
mega64 146:03e976389d16 1778 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
mega64 146:03e976389d16 1779 \brief Functions that configure the System.
mega64 146:03e976389d16 1780 @{
mega64 146:03e976389d16 1781 */
mega64 146:03e976389d16 1782
mega64 146:03e976389d16 1783 #if (__Vendor_SysTickConfig == 0)
mega64 146:03e976389d16 1784
mega64 146:03e976389d16 1785 /** \brief System Tick Configuration
mega64 146:03e976389d16 1786
mega64 146:03e976389d16 1787 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
mega64 146:03e976389d16 1788 Counter is in free running mode to generate periodic interrupts.
mega64 146:03e976389d16 1789
mega64 146:03e976389d16 1790 \param [in] ticks Number of ticks between two interrupts.
mega64 146:03e976389d16 1791
mega64 146:03e976389d16 1792 \return 0 Function succeeded.
mega64 146:03e976389d16 1793 \return 1 Function failed.
mega64 146:03e976389d16 1794
mega64 146:03e976389d16 1795 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
mega64 146:03e976389d16 1796 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
mega64 146:03e976389d16 1797 must contain a vendor-specific implementation of this function.
mega64 146:03e976389d16 1798
mega64 146:03e976389d16 1799 */
mega64 146:03e976389d16 1800 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
mega64 146:03e976389d16 1801 {
mega64 146:03e976389d16 1802 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
mega64 146:03e976389d16 1803
mega64 146:03e976389d16 1804 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
mega64 146:03e976389d16 1805 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
mega64 146:03e976389d16 1806 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
mega64 146:03e976389d16 1807 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
mega64 146:03e976389d16 1808 SysTick_CTRL_TICKINT_Msk |
mega64 146:03e976389d16 1809 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
mega64 146:03e976389d16 1810 return (0UL); /* Function successful */
mega64 146:03e976389d16 1811 }
mega64 146:03e976389d16 1812
mega64 146:03e976389d16 1813 #endif
mega64 146:03e976389d16 1814
mega64 146:03e976389d16 1815 /*@} end of CMSIS_Core_SysTickFunctions */
mega64 146:03e976389d16 1816
mega64 146:03e976389d16 1817
mega64 146:03e976389d16 1818
mega64 146:03e976389d16 1819 /* ##################################### Debug In/Output function ########################################### */
mega64 146:03e976389d16 1820 /** \ingroup CMSIS_Core_FunctionInterface
mega64 146:03e976389d16 1821 \defgroup CMSIS_core_DebugFunctions ITM Functions
mega64 146:03e976389d16 1822 \brief Functions that access the ITM debug interface.
mega64 146:03e976389d16 1823 @{
mega64 146:03e976389d16 1824 */
mega64 146:03e976389d16 1825
mega64 146:03e976389d16 1826 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
mega64 146:03e976389d16 1827 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
mega64 146:03e976389d16 1828
mega64 146:03e976389d16 1829
mega64 146:03e976389d16 1830 /** \brief ITM Send Character
mega64 146:03e976389d16 1831
mega64 146:03e976389d16 1832 The function transmits a character via the ITM channel 0, and
mega64 146:03e976389d16 1833 \li Just returns when no debugger is connected that has booked the output.
mega64 146:03e976389d16 1834 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
mega64 146:03e976389d16 1835
mega64 146:03e976389d16 1836 \param [in] ch Character to transmit.
mega64 146:03e976389d16 1837
mega64 146:03e976389d16 1838 \returns Character to transmit.
mega64 146:03e976389d16 1839 */
mega64 146:03e976389d16 1840 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
mega64 146:03e976389d16 1841 {
mega64 146:03e976389d16 1842 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
mega64 146:03e976389d16 1843 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
mega64 146:03e976389d16 1844 {
mega64 146:03e976389d16 1845 while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
mega64 146:03e976389d16 1846 ITM->PORT[0].u8 = (uint8_t)ch;
mega64 146:03e976389d16 1847 }
mega64 146:03e976389d16 1848 return (ch);
mega64 146:03e976389d16 1849 }
mega64 146:03e976389d16 1850
mega64 146:03e976389d16 1851
mega64 146:03e976389d16 1852 /** \brief ITM Receive Character
mega64 146:03e976389d16 1853
mega64 146:03e976389d16 1854 The function inputs a character via the external variable \ref ITM_RxBuffer.
mega64 146:03e976389d16 1855
mega64 146:03e976389d16 1856 \return Received character.
mega64 146:03e976389d16 1857 \return -1 No character pending.
mega64 146:03e976389d16 1858 */
mega64 146:03e976389d16 1859 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
mega64 146:03e976389d16 1860 int32_t ch = -1; /* no character available */
mega64 146:03e976389d16 1861
mega64 146:03e976389d16 1862 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
mega64 146:03e976389d16 1863 ch = ITM_RxBuffer;
mega64 146:03e976389d16 1864 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
mega64 146:03e976389d16 1865 }
mega64 146:03e976389d16 1866
mega64 146:03e976389d16 1867 return (ch);
mega64 146:03e976389d16 1868 }
mega64 146:03e976389d16 1869
mega64 146:03e976389d16 1870
mega64 146:03e976389d16 1871 /** \brief ITM Check Character
mega64 146:03e976389d16 1872
mega64 146:03e976389d16 1873 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
mega64 146:03e976389d16 1874
mega64 146:03e976389d16 1875 \return 0 No character available.
mega64 146:03e976389d16 1876 \return 1 Character available.
mega64 146:03e976389d16 1877 */
mega64 146:03e976389d16 1878 __STATIC_INLINE int32_t ITM_CheckChar (void) {
mega64 146:03e976389d16 1879
mega64 146:03e976389d16 1880 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
mega64 146:03e976389d16 1881 return (0); /* no character available */
mega64 146:03e976389d16 1882 } else {
mega64 146:03e976389d16 1883 return (1); /* character available */
mega64 146:03e976389d16 1884 }
mega64 146:03e976389d16 1885 }
mega64 146:03e976389d16 1886
mega64 146:03e976389d16 1887 /*@} end of CMSIS_core_DebugFunctions */
mega64 146:03e976389d16 1888
mega64 146:03e976389d16 1889
mega64 146:03e976389d16 1890
mega64 146:03e976389d16 1891
mega64 146:03e976389d16 1892 #ifdef __cplusplus
mega64 146:03e976389d16 1893 }
mega64 146:03e976389d16 1894 #endif
mega64 146:03e976389d16 1895
mega64 146:03e976389d16 1896 #endif /* __CORE_CM4_H_DEPENDANT */
mega64 146:03e976389d16 1897
mega64 146:03e976389d16 1898 #endif /* __CMSIS_GENERIC */