mbed-STM32F103C8 - Modification of Mbed-dev library for LQFP48 packa…

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Modification of Mbed-dev library for LQFP48 package microcontrollers: STM32F103C8 (STM32F103C8T6) and STM32F103CB (STM32F103CBT6) (Bluepill boards, Maple mini etc. )

Fork of mbed-STM32F103C8_org by Nothing Special

Library for STM32F103C8 (Bluepill boards etc.).
Use this instead of mbed library.
This library allows the size of the code in the FLASH up to 128kB. Therefore, code also runs on microcontrollers STM32F103CB (eg. Maple mini).
But in the case of STM32F103C8, check the size of the resulting code would not exceed 64kB.

To compile a program with this library, use NUCLEO-F103RB as the target name. !

Changes:

Corrected initialization of the HSE + crystal clock (mbed permanent bug), allowing the use of on-board xtal (8MHz).⁽¹⁾
Additionally, it also set USB clock (48Mhz).⁽²⁾
Definitions of pins and peripherals adjusted to LQFP48 case.
Board led LED1 is now PC_13 ⁽³⁾
USER_BUTTON is now PC_14 ⁽⁴⁾

Now the library is complete rebuilt based on mbed-dev v160 (and not yet fully tested).

notes
⁽¹⁾ - In case 8MHz xtal on board, CPU frequency is 72MHz. Without xtal is 64MHz.
⁽²⁾ - Using the USB interface is only possible if STM32 is clocking by on-board 8MHz xtal or external clock signal 8MHz on the OSC_IN pin.
⁽³⁾ - On Bluepill board led operation is reversed, i.e. 0 - led on, 1 - led off.
⁽⁴⁾ - Bluepill board has no real user button

Information

After export to SW4STM (AC6):

add line #include "mbed_config.h" in files Serial.h and RawSerial.h
in project properties change Optimisation Level to Optimise for size (-Os)

cmsis/core_cm3.h@148:8b0b02bf146f, 2017-04-27 (annotated)

Committer:: mega64
Date:: Thu Apr 27 23:56:38 2017 +0000
Revision:: 148:8b0b02bf146f
Parent:: 146:03e976389d16

Remove unnecessary folders

Who changed what in which revision?

User	Revision	Line number	New contents of line
mega64	146:03e976389d16	1	/************************************************************************//
mega64	146:03e976389d16	2	* @file core_cm3.h
mega64	146:03e976389d16	3	* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
mega64	146:03e976389d16	4	* @version V4.10
mega64	146:03e976389d16	5	* @date 18. March 2015
mega64	146:03e976389d16	6	*
mega64	146:03e976389d16	7	* @note
mega64	146:03e976389d16	8	*
mega64	146:03e976389d16	9	******************************************************************************/
mega64	146:03e976389d16	10	/* Copyright (c) 2009 - 2015 ARM LIMITED
mega64	146:03e976389d16	11
mega64	146:03e976389d16	12	All rights reserved.
mega64	146:03e976389d16	13	Redistribution and use in source and binary forms, with or without
mega64	146:03e976389d16	14	modification, are permitted provided that the following conditions are met:
mega64	146:03e976389d16	15	- Redistributions of source code must retain the above copyright
mega64	146:03e976389d16	16	notice, this list of conditions and the following disclaimer.
mega64	146:03e976389d16	17	- Redistributions in binary form must reproduce the above copyright
mega64	146:03e976389d16	18	notice, this list of conditions and the following disclaimer in the
mega64	146:03e976389d16	19	documentation and/or other materials provided with the distribution.
mega64	146:03e976389d16	20	- Neither the name of ARM nor the names of its contributors may be used
mega64	146:03e976389d16	21	to endorse or promote products derived from this software without
mega64	146:03e976389d16	22	specific prior written permission.
mega64	146:03e976389d16	23	*
mega64	146:03e976389d16	24	THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mega64	146:03e976389d16	25	AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mega64	146:03e976389d16	26	IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
mega64	146:03e976389d16	27	ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
mega64	146:03e976389d16	28	LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
mega64	146:03e976389d16	29	CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
mega64	146:03e976389d16	30	SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mega64	146:03e976389d16	31	INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mega64	146:03e976389d16	32	CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
mega64	146:03e976389d16	33	ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mega64	146:03e976389d16	34	POSSIBILITY OF SUCH DAMAGE.
mega64	146:03e976389d16	35	---------------------------------------------------------------------------*/
mega64	146:03e976389d16	36
mega64	146:03e976389d16	37
mega64	146:03e976389d16	38	#if defined ( __ICCARM__ )
mega64	146:03e976389d16	39	#pragma system_include /* treat file as system include file for MISRA check */
mega64	146:03e976389d16	40	#endif
mega64	146:03e976389d16	41
mega64	146:03e976389d16	42	#ifndef __CORE_CM3_H_GENERIC
mega64	146:03e976389d16	43	#define __CORE_CM3_H_GENERIC
mega64	146:03e976389d16	44
mega64	146:03e976389d16	45	#ifdef __cplusplus
mega64	146:03e976389d16	46	extern "C" {
mega64	146:03e976389d16	47	#endif
mega64	146:03e976389d16	48
mega64	146:03e976389d16	49	/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
mega64	146:03e976389d16	50	CMSIS violates the following MISRA-C:2004 rules:
mega64	146:03e976389d16	51
mega64	146:03e976389d16	52	\li Required Rule 8.5, object/function definition in header file.<br>
mega64	146:03e976389d16	53	Function definitions in header files are used to allow 'inlining'.
mega64	146:03e976389d16	54
mega64	146:03e976389d16	55	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
mega64	146:03e976389d16	56	Unions are used for effective representation of core registers.
mega64	146:03e976389d16	57
mega64	146:03e976389d16	58	\li Advisory Rule 19.7, Function-like macro defined.<br>
mega64	146:03e976389d16	59	Function-like macros are used to allow more efficient code.
mega64	146:03e976389d16	60	*/
mega64	146:03e976389d16	61
mega64	146:03e976389d16	62
mega64	146:03e976389d16	63	/*******************************************************************************
mega64	146:03e976389d16	64	* CMSIS definitions
mega64	146:03e976389d16	65	******************************************************************************/
mega64	146:03e976389d16	66	/** \ingroup Cortex_M3
mega64	146:03e976389d16	67	@{
mega64	146:03e976389d16	68	*/
mega64	146:03e976389d16	69
mega64	146:03e976389d16	70	/* CMSIS CM3 definitions */
mega64	146:03e976389d16	71	#define __CM3_CMSIS_VERSION_MAIN (0x04) /!< [31:16] CMSIS HAL main version /
mega64	146:03e976389d16	72	#define __CM3_CMSIS_VERSION_SUB (0x00) /!< [15:0] CMSIS HAL sub version /
mega64	146:03e976389d16	73	#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) \| \
mega64	146:03e976389d16	74	__CM3_CMSIS_VERSION_SUB ) /!< CMSIS HAL version number /
mega64	146:03e976389d16	75
mega64	146:03e976389d16	76	#define __CORTEX_M (0x03) /!< Cortex-M Core /
mega64	146:03e976389d16	77
mega64	146:03e976389d16	78
mega64	146:03e976389d16	79	#if defined ( __CC_ARM )
mega64	146:03e976389d16	80	#define __ASM __asm /!< asm keyword for ARM Compiler /
mega64	146:03e976389d16	81	#define __INLINE __inline /!< inline keyword for ARM Compiler /
mega64	146:03e976389d16	82	#define __STATIC_INLINE static __inline
mega64	146:03e976389d16	83
mega64	146:03e976389d16	84	#elif defined ( __GNUC__ )
mega64	146:03e976389d16	85	#define __ASM __asm /!< asm keyword for GNU Compiler /
mega64	146:03e976389d16	86	#define __INLINE inline /!< inline keyword for GNU Compiler /
mega64	146:03e976389d16	87	#define __STATIC_INLINE static inline
mega64	146:03e976389d16	88
mega64	146:03e976389d16	89	#elif defined ( __ICCARM__ )
mega64	146:03e976389d16	90	#define __ASM __asm /!< asm keyword for IAR Compiler /
mega64	146:03e976389d16	91	#define __INLINE inline /!< inline keyword for IAR Compiler. Only available in High optimization mode! /
mega64	146:03e976389d16	92	#define __STATIC_INLINE static inline
mega64	146:03e976389d16	93
mega64	146:03e976389d16	94	#elif defined ( __TMS470__ )
mega64	146:03e976389d16	95	#define __ASM __asm /!< asm keyword for TI CCS Compiler /
mega64	146:03e976389d16	96	#define __STATIC_INLINE static inline
mega64	146:03e976389d16	97
mega64	146:03e976389d16	98	#elif defined ( __TASKING__ )
mega64	146:03e976389d16	99	#define __ASM __asm /!< asm keyword for TASKING Compiler /
mega64	146:03e976389d16	100	#define __INLINE inline /!< inline keyword for TASKING Compiler /
mega64	146:03e976389d16	101	#define __STATIC_INLINE static inline
mega64	146:03e976389d16	102
mega64	146:03e976389d16	103	#elif defined ( __CSMC__ )
mega64	146:03e976389d16	104	#define __packed
mega64	146:03e976389d16	105	#define __ASM _asm /!< asm keyword for COSMIC Compiler /
mega64	146:03e976389d16	106	#define __INLINE inline /use -pc99 on compile line !< inline keyword for COSMIC Compiler /
mega64	146:03e976389d16	107	#define __STATIC_INLINE static inline
mega64	146:03e976389d16	108
mega64	146:03e976389d16	109	#endif
mega64	146:03e976389d16	110
mega64	146:03e976389d16	111	/** __FPU_USED indicates whether an FPU is used or not.
mega64	146:03e976389d16	112	This core does not support an FPU at all
mega64	146:03e976389d16	113	*/
mega64	146:03e976389d16	114	#define __FPU_USED 0
mega64	146:03e976389d16	115
mega64	146:03e976389d16	116	#if defined ( __CC_ARM )
mega64	146:03e976389d16	117	#if defined __TARGET_FPU_VFP
mega64	146:03e976389d16	118	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mega64	146:03e976389d16	119	#endif
mega64	146:03e976389d16	120
mega64	146:03e976389d16	121	#elif defined ( __GNUC__ )
mega64	146:03e976389d16	122	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
mega64	146:03e976389d16	123	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mega64	146:03e976389d16	124	#endif
mega64	146:03e976389d16	125
mega64	146:03e976389d16	126	#elif defined ( __ICCARM__ )
mega64	146:03e976389d16	127	#if defined __ARMVFP__
mega64	146:03e976389d16	128	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mega64	146:03e976389d16	129	#endif
mega64	146:03e976389d16	130
mega64	146:03e976389d16	131	#elif defined ( __TMS470__ )
mega64	146:03e976389d16	132	#if defined __TI__VFP_SUPPORT____
mega64	146:03e976389d16	133	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mega64	146:03e976389d16	134	#endif
mega64	146:03e976389d16	135
mega64	146:03e976389d16	136	#elif defined ( __TASKING__ )
mega64	146:03e976389d16	137	#if defined __FPU_VFP__
mega64	146:03e976389d16	138	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mega64	146:03e976389d16	139	#endif
mega64	146:03e976389d16	140
mega64	146:03e976389d16	141	#elif defined ( __CSMC__ ) /* Cosmic */
mega64	146:03e976389d16	142	#if ( __CSMC__ & 0x400) // FPU present for parser
mega64	146:03e976389d16	143	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mega64	146:03e976389d16	144	#endif
mega64	146:03e976389d16	145	#endif
mega64	146:03e976389d16	146
mega64	146:03e976389d16	147	#include <stdint.h> /* standard types definitions */
mega64	146:03e976389d16	148	#include <core_cmInstr.h> /* Core Instruction Access */
mega64	146:03e976389d16	149	#include <core_cmFunc.h> /* Core Function Access */
mega64	146:03e976389d16	150
mega64	146:03e976389d16	151	#ifdef __cplusplus
mega64	146:03e976389d16	152	}
mega64	146:03e976389d16	153	#endif
mega64	146:03e976389d16	154
mega64	146:03e976389d16	155	#endif /* __CORE_CM3_H_GENERIC */
mega64	146:03e976389d16	156
mega64	146:03e976389d16	157	#ifndef __CMSIS_GENERIC
mega64	146:03e976389d16	158
mega64	146:03e976389d16	159	#ifndef __CORE_CM3_H_DEPENDANT
mega64	146:03e976389d16	160	#define __CORE_CM3_H_DEPENDANT
mega64	146:03e976389d16	161
mega64	146:03e976389d16	162	#ifdef __cplusplus
mega64	146:03e976389d16	163	extern "C" {
mega64	146:03e976389d16	164	#endif
mega64	146:03e976389d16	165
mega64	146:03e976389d16	166	/* check device defines and use defaults */
mega64	146:03e976389d16	167	#if defined __CHECK_DEVICE_DEFINES
mega64	146:03e976389d16	168	#ifndef __CM3_REV
mega64	146:03e976389d16	169	#define __CM3_REV 0x0200
mega64	146:03e976389d16	170	#warning "__CM3_REV not defined in device header file; using default!"
mega64	146:03e976389d16	171	#endif
mega64	146:03e976389d16	172
mega64	146:03e976389d16	173	#ifndef __MPU_PRESENT
mega64	146:03e976389d16	174	#define __MPU_PRESENT 0
mega64	146:03e976389d16	175	#warning "__MPU_PRESENT not defined in device header file; using default!"
mega64	146:03e976389d16	176	#endif
mega64	146:03e976389d16	177
mega64	146:03e976389d16	178	#ifndef __NVIC_PRIO_BITS
mega64	146:03e976389d16	179	#define __NVIC_PRIO_BITS 4
mega64	146:03e976389d16	180	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
mega64	146:03e976389d16	181	#endif
mega64	146:03e976389d16	182
mega64	146:03e976389d16	183	#ifndef __Vendor_SysTickConfig
mega64	146:03e976389d16	184	#define __Vendor_SysTickConfig 0
mega64	146:03e976389d16	185	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
mega64	146:03e976389d16	186	#endif
mega64	146:03e976389d16	187	#endif
mega64	146:03e976389d16	188
mega64	146:03e976389d16	189	/* IO definitions (access restrictions to peripheral registers) */
mega64	146:03e976389d16	190	/**
mega64	146:03e976389d16	191	\defgroup CMSIS_glob_defs CMSIS Global Defines
mega64	146:03e976389d16	192
mega64	146:03e976389d16	193	<strong>IO Type Qualifiers</strong> are used
mega64	146:03e976389d16	194	\li to specify the access to peripheral variables.
mega64	146:03e976389d16	195	\li for automatic generation of peripheral register debug information.
mega64	146:03e976389d16	196	*/
mega64	146:03e976389d16	197	#ifdef __cplusplus
mega64	146:03e976389d16	198	#define __I volatile /!< Defines 'read only' permissions /
mega64	146:03e976389d16	199	#else
mega64	146:03e976389d16	200	#define __I volatile const /!< Defines 'read only' permissions /
mega64	146:03e976389d16	201	#endif
mega64	146:03e976389d16	202	#define __O volatile /!< Defines 'write only' permissions /
mega64	146:03e976389d16	203	#define __IO volatile /!< Defines 'read / write' permissions /
mega64	146:03e976389d16	204
mega64	146:03e976389d16	205	#ifdef __cplusplus
mega64	146:03e976389d16	206	#define __IM volatile /!< Defines 'read only' permissions /
mega64	146:03e976389d16	207	#else
mega64	146:03e976389d16	208	#define __IM volatile const /!< Defines 'read only' permissions /
mega64	146:03e976389d16	209	#endif
mega64	146:03e976389d16	210	#define __OM volatile /!< Defines 'write only' permissions /
mega64	146:03e976389d16	211	#define __IOM volatile /!< Defines 'read / write' permissions /
mega64	146:03e976389d16	212
mega64	146:03e976389d16	213	/@} end of group Cortex_M3 /
mega64	146:03e976389d16	214
mega64	146:03e976389d16	215
mega64	146:03e976389d16	216
mega64	146:03e976389d16	217	/*******************************************************************************
mega64	146:03e976389d16	218	* Register Abstraction
mega64	146:03e976389d16	219	Core Register contain:
mega64	146:03e976389d16	220	- Core Register
mega64	146:03e976389d16	221	- Core NVIC Register
mega64	146:03e976389d16	222	- Core SCB Register
mega64	146:03e976389d16	223	- Core SysTick Register
mega64	146:03e976389d16	224	- Core Debug Register
mega64	146:03e976389d16	225	- Core MPU Register
mega64	146:03e976389d16	226	******************************************************************************/
mega64	146:03e976389d16	227	/** \defgroup CMSIS_core_register Defines and Type Definitions
mega64	146:03e976389d16	228	\brief Type definitions and defines for Cortex-M processor based devices.
mega64	146:03e976389d16	229	*/
mega64	146:03e976389d16	230
mega64	146:03e976389d16	231	/** \ingroup CMSIS_core_register
mega64	146:03e976389d16	232	\defgroup CMSIS_CORE Status and Control Registers
mega64	146:03e976389d16	233	\brief Core Register type definitions.
mega64	146:03e976389d16	234	@{
mega64	146:03e976389d16	235	*/
mega64	146:03e976389d16	236
mega64	146:03e976389d16	237	/** \brief Union type to access the Application Program Status Register (APSR).
mega64	146:03e976389d16	238	*/
mega64	146:03e976389d16	239	typedef union
mega64	146:03e976389d16	240	{
mega64	146:03e976389d16	241	struct
mega64	146:03e976389d16	242	{
mega64	146:03e976389d16	243	uint32_t _reserved0:27; /!< bit: 0..26 Reserved /
mega64	146:03e976389d16	244	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
mega64	146:03e976389d16	245	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
mega64	146:03e976389d16	246	uint32_t C:1; /!< bit: 29 Carry condition code flag /
mega64	146:03e976389d16	247	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
mega64	146:03e976389d16	248	uint32_t N:1; /!< bit: 31 Negative condition code flag /
mega64	146:03e976389d16	249	} b; /!< Structure used for bit access /
mega64	146:03e976389d16	250	uint32_t w; /!< Type used for word access /
mega64	146:03e976389d16	251	} APSR_Type;
mega64	146:03e976389d16	252
mega64	146:03e976389d16	253	/* APSR Register Definitions */
mega64	146:03e976389d16	254	#define APSR_N_Pos 31 /!< APSR: N Position /
mega64	146:03e976389d16	255	#define APSR_N_Msk (1UL << APSR_N_Pos) /!< APSR: N Mask /
mega64	146:03e976389d16	256
mega64	146:03e976389d16	257	#define APSR_Z_Pos 30 /!< APSR: Z Position /
mega64	146:03e976389d16	258	#define APSR_Z_Msk (1UL << APSR_Z_Pos) /!< APSR: Z Mask /
mega64	146:03e976389d16	259
mega64	146:03e976389d16	260	#define APSR_C_Pos 29 /!< APSR: C Position /
mega64	146:03e976389d16	261	#define APSR_C_Msk (1UL << APSR_C_Pos) /!< APSR: C Mask /
mega64	146:03e976389d16	262
mega64	146:03e976389d16	263	#define APSR_V_Pos 28 /!< APSR: V Position /
mega64	146:03e976389d16	264	#define APSR_V_Msk (1UL << APSR_V_Pos) /!< APSR: V Mask /
mega64	146:03e976389d16	265
mega64	146:03e976389d16	266	#define APSR_Q_Pos 27 /!< APSR: Q Position /
mega64	146:03e976389d16	267	#define APSR_Q_Msk (1UL << APSR_Q_Pos) /!< APSR: Q Mask /
mega64	146:03e976389d16	268
mega64	146:03e976389d16	269
mega64	146:03e976389d16	270	/** \brief Union type to access the Interrupt Program Status Register (IPSR).
mega64	146:03e976389d16	271	*/
mega64	146:03e976389d16	272	typedef union
mega64	146:03e976389d16	273	{
mega64	146:03e976389d16	274	struct
mega64	146:03e976389d16	275	{
mega64	146:03e976389d16	276	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
mega64	146:03e976389d16	277	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
mega64	146:03e976389d16	278	} b; /!< Structure used for bit access /
mega64	146:03e976389d16	279	uint32_t w; /!< Type used for word access /
mega64	146:03e976389d16	280	} IPSR_Type;
mega64	146:03e976389d16	281
mega64	146:03e976389d16	282	/* IPSR Register Definitions */
mega64	146:03e976389d16	283	#define IPSR_ISR_Pos 0 /!< IPSR: ISR Position /
mega64	146:03e976389d16	284	#define IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/) /!< IPSR: ISR Mask /
mega64	146:03e976389d16	285
mega64	146:03e976389d16	286
mega64	146:03e976389d16	287	/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
mega64	146:03e976389d16	288	*/
mega64	146:03e976389d16	289	typedef union
mega64	146:03e976389d16	290	{
mega64	146:03e976389d16	291	struct
mega64	146:03e976389d16	292	{
mega64	146:03e976389d16	293	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
mega64	146:03e976389d16	294	uint32_t _reserved0:15; /!< bit: 9..23 Reserved /
mega64	146:03e976389d16	295	uint32_t T:1; /!< bit: 24 Thumb bit (read 0) /
mega64	146:03e976389d16	296	uint32_t IT:2; /!< bit: 25..26 saved IT state (read 0) /
mega64	146:03e976389d16	297	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
mega64	146:03e976389d16	298	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
mega64	146:03e976389d16	299	uint32_t C:1; /!< bit: 29 Carry condition code flag /
mega64	146:03e976389d16	300	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
mega64	146:03e976389d16	301	uint32_t N:1; /!< bit: 31 Negative condition code flag /
mega64	146:03e976389d16	302	} b; /!< Structure used for bit access /
mega64	146:03e976389d16	303	uint32_t w; /!< Type used for word access /
mega64	146:03e976389d16	304	} xPSR_Type;
mega64	146:03e976389d16	305
mega64	146:03e976389d16	306	/* xPSR Register Definitions */
mega64	146:03e976389d16	307	#define xPSR_N_Pos 31 /!< xPSR: N Position /
mega64	146:03e976389d16	308	#define xPSR_N_Msk (1UL << xPSR_N_Pos) /!< xPSR: N Mask /
mega64	146:03e976389d16	309
mega64	146:03e976389d16	310	#define xPSR_Z_Pos 30 /!< xPSR: Z Position /
mega64	146:03e976389d16	311	#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /!< xPSR: Z Mask /
mega64	146:03e976389d16	312
mega64	146:03e976389d16	313	#define xPSR_C_Pos 29 /!< xPSR: C Position /
mega64	146:03e976389d16	314	#define xPSR_C_Msk (1UL << xPSR_C_Pos) /!< xPSR: C Mask /
mega64	146:03e976389d16	315
mega64	146:03e976389d16	316	#define xPSR_V_Pos 28 /!< xPSR: V Position /
mega64	146:03e976389d16	317	#define xPSR_V_Msk (1UL << xPSR_V_Pos) /!< xPSR: V Mask /
mega64	146:03e976389d16	318
mega64	146:03e976389d16	319	#define xPSR_Q_Pos 27 /!< xPSR: Q Position /
mega64	146:03e976389d16	320	#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /!< xPSR: Q Mask /
mega64	146:03e976389d16	321
mega64	146:03e976389d16	322	#define xPSR_IT_Pos 25 /!< xPSR: IT Position /
mega64	146:03e976389d16	323	#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /!< xPSR: IT Mask /
mega64	146:03e976389d16	324
mega64	146:03e976389d16	325	#define xPSR_T_Pos 24 /!< xPSR: T Position /
mega64	146:03e976389d16	326	#define xPSR_T_Msk (1UL << xPSR_T_Pos) /!< xPSR: T Mask /
mega64	146:03e976389d16	327
mega64	146:03e976389d16	328	#define xPSR_ISR_Pos 0 /!< xPSR: ISR Position /
mega64	146:03e976389d16	329	#define xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/) /!< xPSR: ISR Mask /
mega64	146:03e976389d16	330
mega64	146:03e976389d16	331
mega64	146:03e976389d16	332	/** \brief Union type to access the Control Registers (CONTROL).
mega64	146:03e976389d16	333	*/
mega64	146:03e976389d16	334	typedef union
mega64	146:03e976389d16	335	{
mega64	146:03e976389d16	336	struct
mega64	146:03e976389d16	337	{
mega64	146:03e976389d16	338	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
mega64	146:03e976389d16	339	uint32_t SPSEL:1; /!< bit: 1 Stack to be used /
mega64	146:03e976389d16	340	uint32_t _reserved1:30; /!< bit: 2..31 Reserved /
mega64	146:03e976389d16	341	} b; /!< Structure used for bit access /
mega64	146:03e976389d16	342	uint32_t w; /!< Type used for word access /
mega64	146:03e976389d16	343	} CONTROL_Type;
mega64	146:03e976389d16	344
mega64	146:03e976389d16	345	/* CONTROL Register Definitions */
mega64	146:03e976389d16	346	#define CONTROL_SPSEL_Pos 1 /!< CONTROL: SPSEL Position /
mega64	146:03e976389d16	347	#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /!< CONTROL: SPSEL Mask /
mega64	146:03e976389d16	348
mega64	146:03e976389d16	349	#define CONTROL_nPRIV_Pos 0 /!< CONTROL: nPRIV Position /
mega64	146:03e976389d16	350	#define CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/) /!< CONTROL: nPRIV Mask /
mega64	146:03e976389d16	351
mega64	146:03e976389d16	352	/@} end of group CMSIS_CORE /
mega64	146:03e976389d16	353
mega64	146:03e976389d16	354
mega64	146:03e976389d16	355	/** \ingroup CMSIS_core_register
mega64	146:03e976389d16	356	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
mega64	146:03e976389d16	357	\brief Type definitions for the NVIC Registers
mega64	146:03e976389d16	358	@{
mega64	146:03e976389d16	359	*/
mega64	146:03e976389d16	360
mega64	146:03e976389d16	361	/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
mega64	146:03e976389d16	362	*/
mega64	146:03e976389d16	363	typedef struct
mega64	146:03e976389d16	364	{
mega64	146:03e976389d16	365	__IO uint32_t ISER[8]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
mega64	146:03e976389d16	366	uint32_t RESERVED0[24];
mega64	146:03e976389d16	367	__IO uint32_t ICER[8]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
mega64	146:03e976389d16	368	uint32_t RSERVED1[24];
mega64	146:03e976389d16	369	__IO uint32_t ISPR[8]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
mega64	146:03e976389d16	370	uint32_t RESERVED2[24];
mega64	146:03e976389d16	371	__IO uint32_t ICPR[8]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
mega64	146:03e976389d16	372	uint32_t RESERVED3[24];
mega64	146:03e976389d16	373	__IO uint32_t IABR[8]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
mega64	146:03e976389d16	374	uint32_t RESERVED4[56];
mega64	146:03e976389d16	375	__IO uint8_t IP[240]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
mega64	146:03e976389d16	376	uint32_t RESERVED5[644];
mega64	146:03e976389d16	377	__O uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
mega64	146:03e976389d16	378	} NVIC_Type;
mega64	146:03e976389d16	379
mega64	146:03e976389d16	380	/* Software Triggered Interrupt Register Definitions */
mega64	146:03e976389d16	381	#define NVIC_STIR_INTID_Pos 0 /!< STIR: INTLINESNUM Position /
mega64	146:03e976389d16	382	#define NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/) /!< STIR: INTLINESNUM Mask /
mega64	146:03e976389d16	383
mega64	146:03e976389d16	384	/@} end of group CMSIS_NVIC /
mega64	146:03e976389d16	385
mega64	146:03e976389d16	386
mega64	146:03e976389d16	387	/** \ingroup CMSIS_core_register
mega64	146:03e976389d16	388	\defgroup CMSIS_SCB System Control Block (SCB)
mega64	146:03e976389d16	389	\brief Type definitions for the System Control Block Registers
mega64	146:03e976389d16	390	@{
mega64	146:03e976389d16	391	*/
mega64	146:03e976389d16	392
mega64	146:03e976389d16	393	/** \brief Structure type to access the System Control Block (SCB).
mega64	146:03e976389d16	394	*/
mega64	146:03e976389d16	395	typedef struct
mega64	146:03e976389d16	396	{
mega64	146:03e976389d16	397	__I uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
mega64	146:03e976389d16	398	__IO uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
mega64	146:03e976389d16	399	__IO uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
mega64	146:03e976389d16	400	__IO uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
mega64	146:03e976389d16	401	__IO uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
mega64	146:03e976389d16	402	__IO uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
mega64	146:03e976389d16	403	__IO uint8_t SHP[12]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
mega64	146:03e976389d16	404	__IO uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
mega64	146:03e976389d16	405	__IO uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
mega64	146:03e976389d16	406	__IO uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
mega64	146:03e976389d16	407	__IO uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
mega64	146:03e976389d16	408	__IO uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
mega64	146:03e976389d16	409	__IO uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
mega64	146:03e976389d16	410	__IO uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
mega64	146:03e976389d16	411	__I uint32_t PFR[2]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
mega64	146:03e976389d16	412	__I uint32_t DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
mega64	146:03e976389d16	413	__I uint32_t ADR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
mega64	146:03e976389d16	414	__I uint32_t MMFR[4]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
mega64	146:03e976389d16	415	__I uint32_t ISAR[5]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
mega64	146:03e976389d16	416	uint32_t RESERVED0[5];
mega64	146:03e976389d16	417	__IO uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
mega64	146:03e976389d16	418	} SCB_Type;
mega64	146:03e976389d16	419
mega64	146:03e976389d16	420	/* SCB CPUID Register Definitions */
mega64	146:03e976389d16	421	#define SCB_CPUID_IMPLEMENTER_Pos 24 /!< SCB CPUID: IMPLEMENTER Position /
mega64	146:03e976389d16	422	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
mega64	146:03e976389d16	423
mega64	146:03e976389d16	424	#define SCB_CPUID_VARIANT_Pos 20 /!< SCB CPUID: VARIANT Position /
mega64	146:03e976389d16	425	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
mega64	146:03e976389d16	426
mega64	146:03e976389d16	427	#define SCB_CPUID_ARCHITECTURE_Pos 16 /!< SCB CPUID: ARCHITECTURE Position /
mega64	146:03e976389d16	428	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
mega64	146:03e976389d16	429
mega64	146:03e976389d16	430	#define SCB_CPUID_PARTNO_Pos 4 /!< SCB CPUID: PARTNO Position /
mega64	146:03e976389d16	431	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
mega64	146:03e976389d16	432
mega64	146:03e976389d16	433	#define SCB_CPUID_REVISION_Pos 0 /!< SCB CPUID: REVISION Position /
mega64	146:03e976389d16	434	#define SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/) /!< SCB CPUID: REVISION Mask /
mega64	146:03e976389d16	435
mega64	146:03e976389d16	436	/* SCB Interrupt Control State Register Definitions */
mega64	146:03e976389d16	437	#define SCB_ICSR_NMIPENDSET_Pos 31 /!< SCB ICSR: NMIPENDSET Position /
mega64	146:03e976389d16	438	#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /!< SCB ICSR: NMIPENDSET Mask /
mega64	146:03e976389d16	439
mega64	146:03e976389d16	440	#define SCB_ICSR_PENDSVSET_Pos 28 /!< SCB ICSR: PENDSVSET Position /
mega64	146:03e976389d16	441	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
mega64	146:03e976389d16	442
mega64	146:03e976389d16	443	#define SCB_ICSR_PENDSVCLR_Pos 27 /!< SCB ICSR: PENDSVCLR Position /
mega64	146:03e976389d16	444	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
mega64	146:03e976389d16	445
mega64	146:03e976389d16	446	#define SCB_ICSR_PENDSTSET_Pos 26 /!< SCB ICSR: PENDSTSET Position /
mega64	146:03e976389d16	447	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
mega64	146:03e976389d16	448
mega64	146:03e976389d16	449	#define SCB_ICSR_PENDSTCLR_Pos 25 /!< SCB ICSR: PENDSTCLR Position /
mega64	146:03e976389d16	450	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
mega64	146:03e976389d16	451
mega64	146:03e976389d16	452	#define SCB_ICSR_ISRPREEMPT_Pos 23 /!< SCB ICSR: ISRPREEMPT Position /
mega64	146:03e976389d16	453	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
mega64	146:03e976389d16	454
mega64	146:03e976389d16	455	#define SCB_ICSR_ISRPENDING_Pos 22 /!< SCB ICSR: ISRPENDING Position /
mega64	146:03e976389d16	456	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
mega64	146:03e976389d16	457
mega64	146:03e976389d16	458	#define SCB_ICSR_VECTPENDING_Pos 12 /!< SCB ICSR: VECTPENDING Position /
mega64	146:03e976389d16	459	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
mega64	146:03e976389d16	460
mega64	146:03e976389d16	461	#define SCB_ICSR_RETTOBASE_Pos 11 /!< SCB ICSR: RETTOBASE Position /
mega64	146:03e976389d16	462	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
mega64	146:03e976389d16	463
mega64	146:03e976389d16	464	#define SCB_ICSR_VECTACTIVE_Pos 0 /!< SCB ICSR: VECTACTIVE Position /
mega64	146:03e976389d16	465	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/) /!< SCB ICSR: VECTACTIVE Mask /
mega64	146:03e976389d16	466
mega64	146:03e976389d16	467	/* SCB Vector Table Offset Register Definitions */
mega64	146:03e976389d16	468	#if (__CM3_REV < 0x0201) /* core r2p1 */
mega64	146:03e976389d16	469	#define SCB_VTOR_TBLBASE_Pos 29 /!< SCB VTOR: TBLBASE Position /
mega64	146:03e976389d16	470	#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /!< SCB VTOR: TBLBASE Mask /
mega64	146:03e976389d16	471
mega64	146:03e976389d16	472	#define SCB_VTOR_TBLOFF_Pos 7 /!< SCB VTOR: TBLOFF Position /
mega64	146:03e976389d16	473	#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
mega64	146:03e976389d16	474	#else
mega64	146:03e976389d16	475	#define SCB_VTOR_TBLOFF_Pos 7 /!< SCB VTOR: TBLOFF Position /
mega64	146:03e976389d16	476	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
mega64	146:03e976389d16	477	#endif
mega64	146:03e976389d16	478
mega64	146:03e976389d16	479	/* SCB Application Interrupt and Reset Control Register Definitions */
mega64	146:03e976389d16	480	#define SCB_AIRCR_VECTKEY_Pos 16 /!< SCB AIRCR: VECTKEY Position /
mega64	146:03e976389d16	481	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
mega64	146:03e976389d16	482
mega64	146:03e976389d16	483	#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /!< SCB AIRCR: VECTKEYSTAT Position /
mega64	146:03e976389d16	484	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
mega64	146:03e976389d16	485
mega64	146:03e976389d16	486	#define SCB_AIRCR_ENDIANESS_Pos 15 /!< SCB AIRCR: ENDIANESS Position /
mega64	146:03e976389d16	487	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
mega64	146:03e976389d16	488
mega64	146:03e976389d16	489	#define SCB_AIRCR_PRIGROUP_Pos 8 /!< SCB AIRCR: PRIGROUP Position /
mega64	146:03e976389d16	490	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
mega64	146:03e976389d16	491
mega64	146:03e976389d16	492	#define SCB_AIRCR_SYSRESETREQ_Pos 2 /!< SCB AIRCR: SYSRESETREQ Position /
mega64	146:03e976389d16	493	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
mega64	146:03e976389d16	494
mega64	146:03e976389d16	495	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /!< SCB AIRCR: VECTCLRACTIVE Position /
mega64	146:03e976389d16	496	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
mega64	146:03e976389d16	497
mega64	146:03e976389d16	498	#define SCB_AIRCR_VECTRESET_Pos 0 /!< SCB AIRCR: VECTRESET Position /
mega64	146:03e976389d16	499	#define SCB_AIRCR_VECTRESET_Msk (1UL /<< SCB_AIRCR_VECTRESET_Pos/) /!< SCB AIRCR: VECTRESET Mask /
mega64	146:03e976389d16	500
mega64	146:03e976389d16	501	/* SCB System Control Register Definitions */
mega64	146:03e976389d16	502	#define SCB_SCR_SEVONPEND_Pos 4 /!< SCB SCR: SEVONPEND Position /
mega64	146:03e976389d16	503	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
mega64	146:03e976389d16	504
mega64	146:03e976389d16	505	#define SCB_SCR_SLEEPDEEP_Pos 2 /!< SCB SCR: SLEEPDEEP Position /
mega64	146:03e976389d16	506	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
mega64	146:03e976389d16	507
mega64	146:03e976389d16	508	#define SCB_SCR_SLEEPONEXIT_Pos 1 /!< SCB SCR: SLEEPONEXIT Position /
mega64	146:03e976389d16	509	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
mega64	146:03e976389d16	510
mega64	146:03e976389d16	511	/* SCB Configuration Control Register Definitions */
mega64	146:03e976389d16	512	#define SCB_CCR_STKALIGN_Pos 9 /!< SCB CCR: STKALIGN Position /
mega64	146:03e976389d16	513	#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /!< SCB CCR: STKALIGN Mask /
mega64	146:03e976389d16	514
mega64	146:03e976389d16	515	#define SCB_CCR_BFHFNMIGN_Pos 8 /!< SCB CCR: BFHFNMIGN Position /
mega64	146:03e976389d16	516	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
mega64	146:03e976389d16	517
mega64	146:03e976389d16	518	#define SCB_CCR_DIV_0_TRP_Pos 4 /!< SCB CCR: DIV_0_TRP Position /
mega64	146:03e976389d16	519	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
mega64	146:03e976389d16	520
mega64	146:03e976389d16	521	#define SCB_CCR_UNALIGN_TRP_Pos 3 /!< SCB CCR: UNALIGN_TRP Position /
mega64	146:03e976389d16	522	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
mega64	146:03e976389d16	523
mega64	146:03e976389d16	524	#define SCB_CCR_USERSETMPEND_Pos 1 /!< SCB CCR: USERSETMPEND Position /
mega64	146:03e976389d16	525	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
mega64	146:03e976389d16	526
mega64	146:03e976389d16	527	#define SCB_CCR_NONBASETHRDENA_Pos 0 /!< SCB CCR: NONBASETHRDENA Position /
mega64	146:03e976389d16	528	#define SCB_CCR_NONBASETHRDENA_Msk (1UL /<< SCB_CCR_NONBASETHRDENA_Pos/) /!< SCB CCR: NONBASETHRDENA Mask /
mega64	146:03e976389d16	529
mega64	146:03e976389d16	530	/* SCB System Handler Control and State Register Definitions */
mega64	146:03e976389d16	531	#define SCB_SHCSR_USGFAULTENA_Pos 18 /!< SCB SHCSR: USGFAULTENA Position /
mega64	146:03e976389d16	532	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
mega64	146:03e976389d16	533
mega64	146:03e976389d16	534	#define SCB_SHCSR_BUSFAULTENA_Pos 17 /!< SCB SHCSR: BUSFAULTENA Position /
mega64	146:03e976389d16	535	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
mega64	146:03e976389d16	536
mega64	146:03e976389d16	537	#define SCB_SHCSR_MEMFAULTENA_Pos 16 /!< SCB SHCSR: MEMFAULTENA Position /
mega64	146:03e976389d16	538	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
mega64	146:03e976389d16	539
mega64	146:03e976389d16	540	#define SCB_SHCSR_SVCALLPENDED_Pos 15 /!< SCB SHCSR: SVCALLPENDED Position /
mega64	146:03e976389d16	541	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
mega64	146:03e976389d16	542
mega64	146:03e976389d16	543	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /!< SCB SHCSR: BUSFAULTPENDED Position /
mega64	146:03e976389d16	544	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
mega64	146:03e976389d16	545
mega64	146:03e976389d16	546	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /!< SCB SHCSR: MEMFAULTPENDED Position /
mega64	146:03e976389d16	547	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
mega64	146:03e976389d16	548
mega64	146:03e976389d16	549	#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /!< SCB SHCSR: USGFAULTPENDED Position /
mega64	146:03e976389d16	550	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
mega64	146:03e976389d16	551
mega64	146:03e976389d16	552	#define SCB_SHCSR_SYSTICKACT_Pos 11 /!< SCB SHCSR: SYSTICKACT Position /
mega64	146:03e976389d16	553	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
mega64	146:03e976389d16	554
mega64	146:03e976389d16	555	#define SCB_SHCSR_PENDSVACT_Pos 10 /!< SCB SHCSR: PENDSVACT Position /
mega64	146:03e976389d16	556	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
mega64	146:03e976389d16	557
mega64	146:03e976389d16	558	#define SCB_SHCSR_MONITORACT_Pos 8 /!< SCB SHCSR: MONITORACT Position /
mega64	146:03e976389d16	559	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
mega64	146:03e976389d16	560
mega64	146:03e976389d16	561	#define SCB_SHCSR_SVCALLACT_Pos 7 /!< SCB SHCSR: SVCALLACT Position /
mega64	146:03e976389d16	562	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
mega64	146:03e976389d16	563
mega64	146:03e976389d16	564	#define SCB_SHCSR_USGFAULTACT_Pos 3 /!< SCB SHCSR: USGFAULTACT Position /
mega64	146:03e976389d16	565	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
mega64	146:03e976389d16	566
mega64	146:03e976389d16	567	#define SCB_SHCSR_BUSFAULTACT_Pos 1 /!< SCB SHCSR: BUSFAULTACT Position /
mega64	146:03e976389d16	568	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
mega64	146:03e976389d16	569
mega64	146:03e976389d16	570	#define SCB_SHCSR_MEMFAULTACT_Pos 0 /!< SCB SHCSR: MEMFAULTACT Position /
mega64	146:03e976389d16	571	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/) /!< SCB SHCSR: MEMFAULTACT Mask /
mega64	146:03e976389d16	572
mega64	146:03e976389d16	573	/* SCB Configurable Fault Status Registers Definitions */
mega64	146:03e976389d16	574	#define SCB_CFSR_USGFAULTSR_Pos 16 /!< SCB CFSR: Usage Fault Status Register Position /
mega64	146:03e976389d16	575	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
mega64	146:03e976389d16	576
mega64	146:03e976389d16	577	#define SCB_CFSR_BUSFAULTSR_Pos 8 /!< SCB CFSR: Bus Fault Status Register Position /
mega64	146:03e976389d16	578	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
mega64	146:03e976389d16	579
mega64	146:03e976389d16	580	#define SCB_CFSR_MEMFAULTSR_Pos 0 /!< SCB CFSR: Memory Manage Fault Status Register Position /
mega64	146:03e976389d16	581	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
mega64	146:03e976389d16	582
mega64	146:03e976389d16	583	/* SCB Hard Fault Status Registers Definitions */
mega64	146:03e976389d16	584	#define SCB_HFSR_DEBUGEVT_Pos 31 /!< SCB HFSR: DEBUGEVT Position /
mega64	146:03e976389d16	585	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
mega64	146:03e976389d16	586
mega64	146:03e976389d16	587	#define SCB_HFSR_FORCED_Pos 30 /!< SCB HFSR: FORCED Position /
mega64	146:03e976389d16	588	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
mega64	146:03e976389d16	589
mega64	146:03e976389d16	590	#define SCB_HFSR_VECTTBL_Pos 1 /!< SCB HFSR: VECTTBL Position /
mega64	146:03e976389d16	591	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
mega64	146:03e976389d16	592
mega64	146:03e976389d16	593	/* SCB Debug Fault Status Register Definitions */
mega64	146:03e976389d16	594	#define SCB_DFSR_EXTERNAL_Pos 4 /!< SCB DFSR: EXTERNAL Position /
mega64	146:03e976389d16	595	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
mega64	146:03e976389d16	596
mega64	146:03e976389d16	597	#define SCB_DFSR_VCATCH_Pos 3 /!< SCB DFSR: VCATCH Position /
mega64	146:03e976389d16	598	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
mega64	146:03e976389d16	599
mega64	146:03e976389d16	600	#define SCB_DFSR_DWTTRAP_Pos 2 /!< SCB DFSR: DWTTRAP Position /
mega64	146:03e976389d16	601	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
mega64	146:03e976389d16	602
mega64	146:03e976389d16	603	#define SCB_DFSR_BKPT_Pos 1 /!< SCB DFSR: BKPT Position /
mega64	146:03e976389d16	604	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
mega64	146:03e976389d16	605
mega64	146:03e976389d16	606	#define SCB_DFSR_HALTED_Pos 0 /!< SCB DFSR: HALTED Position /
mega64	146:03e976389d16	607	#define SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/) /!< SCB DFSR: HALTED Mask /
mega64	146:03e976389d16	608
mega64	146:03e976389d16	609	/@} end of group CMSIS_SCB /
mega64	146:03e976389d16	610
mega64	146:03e976389d16	611
mega64	146:03e976389d16	612	/** \ingroup CMSIS_core_register
mega64	146:03e976389d16	613	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
mega64	146:03e976389d16	614	\brief Type definitions for the System Control and ID Register not in the SCB
mega64	146:03e976389d16	615	@{
mega64	146:03e976389d16	616	*/
mega64	146:03e976389d16	617
mega64	146:03e976389d16	618	/** \brief Structure type to access the System Control and ID Register not in the SCB.
mega64	146:03e976389d16	619	*/
mega64	146:03e976389d16	620	typedef struct
mega64	146:03e976389d16	621	{
mega64	146:03e976389d16	622	uint32_t RESERVED0[1];
mega64	146:03e976389d16	623	__I uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
mega64	146:03e976389d16	624	#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
mega64	146:03e976389d16	625	__IO uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
mega64	146:03e976389d16	626	#else
mega64	146:03e976389d16	627	uint32_t RESERVED1[1];
mega64	146:03e976389d16	628	#endif
mega64	146:03e976389d16	629	} SCnSCB_Type;
mega64	146:03e976389d16	630
mega64	146:03e976389d16	631	/* Interrupt Controller Type Register Definitions */
mega64	146:03e976389d16	632	#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /!< ICTR: INTLINESNUM Position /
mega64	146:03e976389d16	633	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/) /!< ICTR: INTLINESNUM Mask /
mega64	146:03e976389d16	634
mega64	146:03e976389d16	635	/* Auxiliary Control Register Definitions */
mega64	146:03e976389d16	636
mega64	146:03e976389d16	637	#define SCnSCB_ACTLR_DISFOLD_Pos 2 /!< ACTLR: DISFOLD Position /
mega64	146:03e976389d16	638	#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /!< ACTLR: DISFOLD Mask /
mega64	146:03e976389d16	639
mega64	146:03e976389d16	640	#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /!< ACTLR: DISDEFWBUF Position /
mega64	146:03e976389d16	641	#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /!< ACTLR: DISDEFWBUF Mask /
mega64	146:03e976389d16	642
mega64	146:03e976389d16	643	#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /!< ACTLR: DISMCYCINT Position /
mega64	146:03e976389d16	644	#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /<< SCnSCB_ACTLR_DISMCYCINT_Pos/) /!< ACTLR: DISMCYCINT Mask /
mega64	146:03e976389d16	645
mega64	146:03e976389d16	646	/@} end of group CMSIS_SCnotSCB /
mega64	146:03e976389d16	647
mega64	146:03e976389d16	648
mega64	146:03e976389d16	649	/** \ingroup CMSIS_core_register
mega64	146:03e976389d16	650	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
mega64	146:03e976389d16	651	\brief Type definitions for the System Timer Registers.
mega64	146:03e976389d16	652	@{
mega64	146:03e976389d16	653	*/
mega64	146:03e976389d16	654
mega64	146:03e976389d16	655	/** \brief Structure type to access the System Timer (SysTick).
mega64	146:03e976389d16	656	*/
mega64	146:03e976389d16	657	typedef struct
mega64	146:03e976389d16	658	{
mega64	146:03e976389d16	659	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
mega64	146:03e976389d16	660	__IO uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
mega64	146:03e976389d16	661	__IO uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
mega64	146:03e976389d16	662	__I uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
mega64	146:03e976389d16	663	} SysTick_Type;
mega64	146:03e976389d16	664
mega64	146:03e976389d16	665	/* SysTick Control / Status Register Definitions */
mega64	146:03e976389d16	666	#define SysTick_CTRL_COUNTFLAG_Pos 16 /!< SysTick CTRL: COUNTFLAG Position /
mega64	146:03e976389d16	667	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
mega64	146:03e976389d16	668
mega64	146:03e976389d16	669	#define SysTick_CTRL_CLKSOURCE_Pos 2 /!< SysTick CTRL: CLKSOURCE Position /
mega64	146:03e976389d16	670	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
mega64	146:03e976389d16	671
mega64	146:03e976389d16	672	#define SysTick_CTRL_TICKINT_Pos 1 /!< SysTick CTRL: TICKINT Position /
mega64	146:03e976389d16	673	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
mega64	146:03e976389d16	674
mega64	146:03e976389d16	675	#define SysTick_CTRL_ENABLE_Pos 0 /!< SysTick CTRL: ENABLE Position /
mega64	146:03e976389d16	676	#define SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/) /!< SysTick CTRL: ENABLE Mask /
mega64	146:03e976389d16	677
mega64	146:03e976389d16	678	/* SysTick Reload Register Definitions */
mega64	146:03e976389d16	679	#define SysTick_LOAD_RELOAD_Pos 0 /!< SysTick LOAD: RELOAD Position /
mega64	146:03e976389d16	680	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/) /!< SysTick LOAD: RELOAD Mask /
mega64	146:03e976389d16	681
mega64	146:03e976389d16	682	/* SysTick Current Register Definitions */
mega64	146:03e976389d16	683	#define SysTick_VAL_CURRENT_Pos 0 /!< SysTick VAL: CURRENT Position /
mega64	146:03e976389d16	684	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/) /!< SysTick VAL: CURRENT Mask /
mega64	146:03e976389d16	685
mega64	146:03e976389d16	686	/* SysTick Calibration Register Definitions */
mega64	146:03e976389d16	687	#define SysTick_CALIB_NOREF_Pos 31 /!< SysTick CALIB: NOREF Position /
mega64	146:03e976389d16	688	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
mega64	146:03e976389d16	689
mega64	146:03e976389d16	690	#define SysTick_CALIB_SKEW_Pos 30 /!< SysTick CALIB: SKEW Position /
mega64	146:03e976389d16	691	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
mega64	146:03e976389d16	692
mega64	146:03e976389d16	693	#define SysTick_CALIB_TENMS_Pos 0 /!< SysTick CALIB: TENMS Position /
mega64	146:03e976389d16	694	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/) /!< SysTick CALIB: TENMS Mask /
mega64	146:03e976389d16	695
mega64	146:03e976389d16	696	/@} end of group CMSIS_SysTick /
mega64	146:03e976389d16	697
mega64	146:03e976389d16	698
mega64	146:03e976389d16	699	/** \ingroup CMSIS_core_register
mega64	146:03e976389d16	700	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
mega64	146:03e976389d16	701	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
mega64	146:03e976389d16	702	@{
mega64	146:03e976389d16	703	*/
mega64	146:03e976389d16	704
mega64	146:03e976389d16	705	/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
mega64	146:03e976389d16	706	*/
mega64	146:03e976389d16	707	typedef struct
mega64	146:03e976389d16	708	{
mega64	146:03e976389d16	709	__O union
mega64	146:03e976389d16	710	{
mega64	146:03e976389d16	711	__O uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
mega64	146:03e976389d16	712	__O uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
mega64	146:03e976389d16	713	__O uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
mega64	146:03e976389d16	714	} PORT [32]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
mega64	146:03e976389d16	715	uint32_t RESERVED0[864];
mega64	146:03e976389d16	716	__IO uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
mega64	146:03e976389d16	717	uint32_t RESERVED1[15];
mega64	146:03e976389d16	718	__IO uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
mega64	146:03e976389d16	719	uint32_t RESERVED2[15];
mega64	146:03e976389d16	720	__IO uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
mega64	146:03e976389d16	721	uint32_t RESERVED3[29];
mega64	146:03e976389d16	722	__O uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
mega64	146:03e976389d16	723	__I uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
mega64	146:03e976389d16	724	__IO uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
mega64	146:03e976389d16	725	uint32_t RESERVED4[43];
mega64	146:03e976389d16	726	__O uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
mega64	146:03e976389d16	727	__I uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
mega64	146:03e976389d16	728	uint32_t RESERVED5[6];
mega64	146:03e976389d16	729	__I uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
mega64	146:03e976389d16	730	__I uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
mega64	146:03e976389d16	731	__I uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
mega64	146:03e976389d16	732	__I uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
mega64	146:03e976389d16	733	__I uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
mega64	146:03e976389d16	734	__I uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
mega64	146:03e976389d16	735	__I uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
mega64	146:03e976389d16	736	__I uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
mega64	146:03e976389d16	737	__I uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
mega64	146:03e976389d16	738	__I uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
mega64	146:03e976389d16	739	__I uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
mega64	146:03e976389d16	740	__I uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
mega64	146:03e976389d16	741	} ITM_Type;
mega64	146:03e976389d16	742
mega64	146:03e976389d16	743	/* ITM Trace Privilege Register Definitions */
mega64	146:03e976389d16	744	#define ITM_TPR_PRIVMASK_Pos 0 /!< ITM TPR: PRIVMASK Position /
mega64	146:03e976389d16	745	#define ITM_TPR_PRIVMASK_Msk (0xFUL /<< ITM_TPR_PRIVMASK_Pos/) /!< ITM TPR: PRIVMASK Mask /
mega64	146:03e976389d16	746
mega64	146:03e976389d16	747	/* ITM Trace Control Register Definitions */
mega64	146:03e976389d16	748	#define ITM_TCR_BUSY_Pos 23 /!< ITM TCR: BUSY Position /
mega64	146:03e976389d16	749	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
mega64	146:03e976389d16	750
mega64	146:03e976389d16	751	#define ITM_TCR_TraceBusID_Pos 16 /!< ITM TCR: ATBID Position /
mega64	146:03e976389d16	752	#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /!< ITM TCR: ATBID Mask /
mega64	146:03e976389d16	753
mega64	146:03e976389d16	754	#define ITM_TCR_GTSFREQ_Pos 10 /!< ITM TCR: Global timestamp frequency Position /
mega64	146:03e976389d16	755	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
mega64	146:03e976389d16	756
mega64	146:03e976389d16	757	#define ITM_TCR_TSPrescale_Pos 8 /!< ITM TCR: TSPrescale Position /
mega64	146:03e976389d16	758	#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /!< ITM TCR: TSPrescale Mask /
mega64	146:03e976389d16	759
mega64	146:03e976389d16	760	#define ITM_TCR_SWOENA_Pos 4 /!< ITM TCR: SWOENA Position /
mega64	146:03e976389d16	761	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
mega64	146:03e976389d16	762
mega64	146:03e976389d16	763	#define ITM_TCR_DWTENA_Pos 3 /!< ITM TCR: DWTENA Position /
mega64	146:03e976389d16	764	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
mega64	146:03e976389d16	765
mega64	146:03e976389d16	766	#define ITM_TCR_SYNCENA_Pos 2 /!< ITM TCR: SYNCENA Position /
mega64	146:03e976389d16	767	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
mega64	146:03e976389d16	768
mega64	146:03e976389d16	769	#define ITM_TCR_TSENA_Pos 1 /!< ITM TCR: TSENA Position /
mega64	146:03e976389d16	770	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
mega64	146:03e976389d16	771
mega64	146:03e976389d16	772	#define ITM_TCR_ITMENA_Pos 0 /!< ITM TCR: ITM Enable bit Position /
mega64	146:03e976389d16	773	#define ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/) /!< ITM TCR: ITM Enable bit Mask /
mega64	146:03e976389d16	774
mega64	146:03e976389d16	775	/* ITM Integration Write Register Definitions */
mega64	146:03e976389d16	776	#define ITM_IWR_ATVALIDM_Pos 0 /!< ITM IWR: ATVALIDM Position /
mega64	146:03e976389d16	777	#define ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/) /!< ITM IWR: ATVALIDM Mask /
mega64	146:03e976389d16	778
mega64	146:03e976389d16	779	/* ITM Integration Read Register Definitions */
mega64	146:03e976389d16	780	#define ITM_IRR_ATREADYM_Pos 0 /!< ITM IRR: ATREADYM Position /
mega64	146:03e976389d16	781	#define ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/) /!< ITM IRR: ATREADYM Mask /
mega64	146:03e976389d16	782
mega64	146:03e976389d16	783	/* ITM Integration Mode Control Register Definitions */
mega64	146:03e976389d16	784	#define ITM_IMCR_INTEGRATION_Pos 0 /!< ITM IMCR: INTEGRATION Position /
mega64	146:03e976389d16	785	#define ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/) /!< ITM IMCR: INTEGRATION Mask /
mega64	146:03e976389d16	786
mega64	146:03e976389d16	787	/* ITM Lock Status Register Definitions */
mega64	146:03e976389d16	788	#define ITM_LSR_ByteAcc_Pos 2 /!< ITM LSR: ByteAcc Position /
mega64	146:03e976389d16	789	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
mega64	146:03e976389d16	790
mega64	146:03e976389d16	791	#define ITM_LSR_Access_Pos 1 /!< ITM LSR: Access Position /
mega64	146:03e976389d16	792	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
mega64	146:03e976389d16	793
mega64	146:03e976389d16	794	#define ITM_LSR_Present_Pos 0 /!< ITM LSR: Present Position /
mega64	146:03e976389d16	795	#define ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/) /!< ITM LSR: Present Mask /
mega64	146:03e976389d16	796
mega64	146:03e976389d16	797	/@}/ /* end of group CMSIS_ITM */
mega64	146:03e976389d16	798
mega64	146:03e976389d16	799
mega64	146:03e976389d16	800	/** \ingroup CMSIS_core_register
mega64	146:03e976389d16	801	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
mega64	146:03e976389d16	802	\brief Type definitions for the Data Watchpoint and Trace (DWT)
mega64	146:03e976389d16	803	@{
mega64	146:03e976389d16	804	*/
mega64	146:03e976389d16	805
mega64	146:03e976389d16	806	/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
mega64	146:03e976389d16	807	*/
mega64	146:03e976389d16	808	typedef struct
mega64	146:03e976389d16	809	{
mega64	146:03e976389d16	810	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
mega64	146:03e976389d16	811	__IO uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
mega64	146:03e976389d16	812	__IO uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
mega64	146:03e976389d16	813	__IO uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
mega64	146:03e976389d16	814	__IO uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
mega64	146:03e976389d16	815	__IO uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
mega64	146:03e976389d16	816	__IO uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
mega64	146:03e976389d16	817	__I uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
mega64	146:03e976389d16	818	__IO uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
mega64	146:03e976389d16	819	__IO uint32_t MASK0; /!< Offset: 0x024 (R/W) Mask Register 0 /
mega64	146:03e976389d16	820	__IO uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
mega64	146:03e976389d16	821	uint32_t RESERVED0[1];
mega64	146:03e976389d16	822	__IO uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
mega64	146:03e976389d16	823	__IO uint32_t MASK1; /!< Offset: 0x034 (R/W) Mask Register 1 /
mega64	146:03e976389d16	824	__IO uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
mega64	146:03e976389d16	825	uint32_t RESERVED1[1];
mega64	146:03e976389d16	826	__IO uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
mega64	146:03e976389d16	827	__IO uint32_t MASK2; /!< Offset: 0x044 (R/W) Mask Register 2 /
mega64	146:03e976389d16	828	__IO uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
mega64	146:03e976389d16	829	uint32_t RESERVED2[1];
mega64	146:03e976389d16	830	__IO uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
mega64	146:03e976389d16	831	__IO uint32_t MASK3; /!< Offset: 0x054 (R/W) Mask Register 3 /
mega64	146:03e976389d16	832	__IO uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
mega64	146:03e976389d16	833	} DWT_Type;
mega64	146:03e976389d16	834
mega64	146:03e976389d16	835	/* DWT Control Register Definitions */
mega64	146:03e976389d16	836	#define DWT_CTRL_NUMCOMP_Pos 28 /!< DWT CTRL: NUMCOMP Position /
mega64	146:03e976389d16	837	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
mega64	146:03e976389d16	838
mega64	146:03e976389d16	839	#define DWT_CTRL_NOTRCPKT_Pos 27 /!< DWT CTRL: NOTRCPKT Position /
mega64	146:03e976389d16	840	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
mega64	146:03e976389d16	841
mega64	146:03e976389d16	842	#define DWT_CTRL_NOEXTTRIG_Pos 26 /!< DWT CTRL: NOEXTTRIG Position /
mega64	146:03e976389d16	843	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
mega64	146:03e976389d16	844
mega64	146:03e976389d16	845	#define DWT_CTRL_NOCYCCNT_Pos 25 /!< DWT CTRL: NOCYCCNT Position /
mega64	146:03e976389d16	846	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
mega64	146:03e976389d16	847
mega64	146:03e976389d16	848	#define DWT_CTRL_NOPRFCNT_Pos 24 /!< DWT CTRL: NOPRFCNT Position /
mega64	146:03e976389d16	849	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
mega64	146:03e976389d16	850
mega64	146:03e976389d16	851	#define DWT_CTRL_CYCEVTENA_Pos 22 /!< DWT CTRL: CYCEVTENA Position /
mega64	146:03e976389d16	852	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
mega64	146:03e976389d16	853
mega64	146:03e976389d16	854	#define DWT_CTRL_FOLDEVTENA_Pos 21 /!< DWT CTRL: FOLDEVTENA Position /
mega64	146:03e976389d16	855	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
mega64	146:03e976389d16	856
mega64	146:03e976389d16	857	#define DWT_CTRL_LSUEVTENA_Pos 20 /!< DWT CTRL: LSUEVTENA Position /
mega64	146:03e976389d16	858	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
mega64	146:03e976389d16	859
mega64	146:03e976389d16	860	#define DWT_CTRL_SLEEPEVTENA_Pos 19 /!< DWT CTRL: SLEEPEVTENA Position /
mega64	146:03e976389d16	861	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
mega64	146:03e976389d16	862
mega64	146:03e976389d16	863	#define DWT_CTRL_EXCEVTENA_Pos 18 /!< DWT CTRL: EXCEVTENA Position /
mega64	146:03e976389d16	864	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
mega64	146:03e976389d16	865
mega64	146:03e976389d16	866	#define DWT_CTRL_CPIEVTENA_Pos 17 /!< DWT CTRL: CPIEVTENA Position /
mega64	146:03e976389d16	867	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
mega64	146:03e976389d16	868
mega64	146:03e976389d16	869	#define DWT_CTRL_EXCTRCENA_Pos 16 /!< DWT CTRL: EXCTRCENA Position /
mega64	146:03e976389d16	870	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
mega64	146:03e976389d16	871
mega64	146:03e976389d16	872	#define DWT_CTRL_PCSAMPLENA_Pos 12 /!< DWT CTRL: PCSAMPLENA Position /
mega64	146:03e976389d16	873	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
mega64	146:03e976389d16	874
mega64	146:03e976389d16	875	#define DWT_CTRL_SYNCTAP_Pos 10 /!< DWT CTRL: SYNCTAP Position /
mega64	146:03e976389d16	876	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
mega64	146:03e976389d16	877
mega64	146:03e976389d16	878	#define DWT_CTRL_CYCTAP_Pos 9 /!< DWT CTRL: CYCTAP Position /
mega64	146:03e976389d16	879	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
mega64	146:03e976389d16	880
mega64	146:03e976389d16	881	#define DWT_CTRL_POSTINIT_Pos 5 /!< DWT CTRL: POSTINIT Position /
mega64	146:03e976389d16	882	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
mega64	146:03e976389d16	883
mega64	146:03e976389d16	884	#define DWT_CTRL_POSTPRESET_Pos 1 /!< DWT CTRL: POSTPRESET Position /
mega64	146:03e976389d16	885	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
mega64	146:03e976389d16	886
mega64	146:03e976389d16	887	#define DWT_CTRL_CYCCNTENA_Pos 0 /!< DWT CTRL: CYCCNTENA Position /
mega64	146:03e976389d16	888	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /<< DWT_CTRL_CYCCNTENA_Pos/) /!< DWT CTRL: CYCCNTENA Mask /
mega64	146:03e976389d16	889
mega64	146:03e976389d16	890	/* DWT CPI Count Register Definitions */
mega64	146:03e976389d16	891	#define DWT_CPICNT_CPICNT_Pos 0 /!< DWT CPICNT: CPICNT Position /
mega64	146:03e976389d16	892	#define DWT_CPICNT_CPICNT_Msk (0xFFUL /<< DWT_CPICNT_CPICNT_Pos/) /!< DWT CPICNT: CPICNT Mask /
mega64	146:03e976389d16	893
mega64	146:03e976389d16	894	/* DWT Exception Overhead Count Register Definitions */
mega64	146:03e976389d16	895	#define DWT_EXCCNT_EXCCNT_Pos 0 /!< DWT EXCCNT: EXCCNT Position /
mega64	146:03e976389d16	896	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /<< DWT_EXCCNT_EXCCNT_Pos/) /!< DWT EXCCNT: EXCCNT Mask /
mega64	146:03e976389d16	897
mega64	146:03e976389d16	898	/* DWT Sleep Count Register Definitions */
mega64	146:03e976389d16	899	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /!< DWT SLEEPCNT: SLEEPCNT Position /
mega64	146:03e976389d16	900	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /<< DWT_SLEEPCNT_SLEEPCNT_Pos/) /!< DWT SLEEPCNT: SLEEPCNT Mask /
mega64	146:03e976389d16	901
mega64	146:03e976389d16	902	/* DWT LSU Count Register Definitions */
mega64	146:03e976389d16	903	#define DWT_LSUCNT_LSUCNT_Pos 0 /!< DWT LSUCNT: LSUCNT Position /
mega64	146:03e976389d16	904	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /<< DWT_LSUCNT_LSUCNT_Pos/) /!< DWT LSUCNT: LSUCNT Mask /
mega64	146:03e976389d16	905
mega64	146:03e976389d16	906	/* DWT Folded-instruction Count Register Definitions */
mega64	146:03e976389d16	907	#define DWT_FOLDCNT_FOLDCNT_Pos 0 /!< DWT FOLDCNT: FOLDCNT Position /
mega64	146:03e976389d16	908	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /<< DWT_FOLDCNT_FOLDCNT_Pos/) /!< DWT FOLDCNT: FOLDCNT Mask /
mega64	146:03e976389d16	909
mega64	146:03e976389d16	910	/* DWT Comparator Mask Register Definitions */
mega64	146:03e976389d16	911	#define DWT_MASK_MASK_Pos 0 /!< DWT MASK: MASK Position /
mega64	146:03e976389d16	912	#define DWT_MASK_MASK_Msk (0x1FUL /<< DWT_MASK_MASK_Pos/) /!< DWT MASK: MASK Mask /
mega64	146:03e976389d16	913
mega64	146:03e976389d16	914	/* DWT Comparator Function Register Definitions */
mega64	146:03e976389d16	915	#define DWT_FUNCTION_MATCHED_Pos 24 /!< DWT FUNCTION: MATCHED Position /
mega64	146:03e976389d16	916	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
mega64	146:03e976389d16	917
mega64	146:03e976389d16	918	#define DWT_FUNCTION_DATAVADDR1_Pos 16 /!< DWT FUNCTION: DATAVADDR1 Position /
mega64	146:03e976389d16	919	#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /!< DWT FUNCTION: DATAVADDR1 Mask /
mega64	146:03e976389d16	920
mega64	146:03e976389d16	921	#define DWT_FUNCTION_DATAVADDR0_Pos 12 /!< DWT FUNCTION: DATAVADDR0 Position /
mega64	146:03e976389d16	922	#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /!< DWT FUNCTION: DATAVADDR0 Mask /
mega64	146:03e976389d16	923
mega64	146:03e976389d16	924	#define DWT_FUNCTION_DATAVSIZE_Pos 10 /!< DWT FUNCTION: DATAVSIZE Position /
mega64	146:03e976389d16	925	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
mega64	146:03e976389d16	926
mega64	146:03e976389d16	927	#define DWT_FUNCTION_LNK1ENA_Pos 9 /!< DWT FUNCTION: LNK1ENA Position /
mega64	146:03e976389d16	928	#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /!< DWT FUNCTION: LNK1ENA Mask /
mega64	146:03e976389d16	929
mega64	146:03e976389d16	930	#define DWT_FUNCTION_DATAVMATCH_Pos 8 /!< DWT FUNCTION: DATAVMATCH Position /
mega64	146:03e976389d16	931	#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /!< DWT FUNCTION: DATAVMATCH Mask /
mega64	146:03e976389d16	932
mega64	146:03e976389d16	933	#define DWT_FUNCTION_CYCMATCH_Pos 7 /!< DWT FUNCTION: CYCMATCH Position /
mega64	146:03e976389d16	934	#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /!< DWT FUNCTION: CYCMATCH Mask /
mega64	146:03e976389d16	935
mega64	146:03e976389d16	936	#define DWT_FUNCTION_EMITRANGE_Pos 5 /!< DWT FUNCTION: EMITRANGE Position /
mega64	146:03e976389d16	937	#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /!< DWT FUNCTION: EMITRANGE Mask /
mega64	146:03e976389d16	938
mega64	146:03e976389d16	939	#define DWT_FUNCTION_FUNCTION_Pos 0 /!< DWT FUNCTION: FUNCTION Position /
mega64	146:03e976389d16	940	#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /<< DWT_FUNCTION_FUNCTION_Pos/) /!< DWT FUNCTION: FUNCTION Mask /
mega64	146:03e976389d16	941
mega64	146:03e976389d16	942	/@}/ /* end of group CMSIS_DWT */
mega64	146:03e976389d16	943
mega64	146:03e976389d16	944
mega64	146:03e976389d16	945	/** \ingroup CMSIS_core_register
mega64	146:03e976389d16	946	\defgroup CMSIS_TPI Trace Port Interface (TPI)
mega64	146:03e976389d16	947	\brief Type definitions for the Trace Port Interface (TPI)
mega64	146:03e976389d16	948	@{
mega64	146:03e976389d16	949	*/
mega64	146:03e976389d16	950
mega64	146:03e976389d16	951	/** \brief Structure type to access the Trace Port Interface Register (TPI).
mega64	146:03e976389d16	952	*/
mega64	146:03e976389d16	953	typedef struct
mega64	146:03e976389d16	954	{
mega64	146:03e976389d16	955	__IO uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
mega64	146:03e976389d16	956	__IO uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
mega64	146:03e976389d16	957	uint32_t RESERVED0[2];
mega64	146:03e976389d16	958	__IO uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
mega64	146:03e976389d16	959	uint32_t RESERVED1[55];
mega64	146:03e976389d16	960	__IO uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
mega64	146:03e976389d16	961	uint32_t RESERVED2[131];
mega64	146:03e976389d16	962	__I uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
mega64	146:03e976389d16	963	__IO uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
mega64	146:03e976389d16	964	__I uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
mega64	146:03e976389d16	965	uint32_t RESERVED3[759];
mega64	146:03e976389d16	966	__I uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER /
mega64	146:03e976389d16	967	__I uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
mega64	146:03e976389d16	968	__I uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
mega64	146:03e976389d16	969	uint32_t RESERVED4[1];
mega64	146:03e976389d16	970	__I uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
mega64	146:03e976389d16	971	__I uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
mega64	146:03e976389d16	972	__IO uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
mega64	146:03e976389d16	973	uint32_t RESERVED5[39];
mega64	146:03e976389d16	974	__IO uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
mega64	146:03e976389d16	975	__IO uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
mega64	146:03e976389d16	976	uint32_t RESERVED7[8];
mega64	146:03e976389d16	977	__I uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
mega64	146:03e976389d16	978	__I uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
mega64	146:03e976389d16	979	} TPI_Type;
mega64	146:03e976389d16	980
mega64	146:03e976389d16	981	/* TPI Asynchronous Clock Prescaler Register Definitions */
mega64	146:03e976389d16	982	#define TPI_ACPR_PRESCALER_Pos 0 /!< TPI ACPR: PRESCALER Position /
mega64	146:03e976389d16	983	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/) /!< TPI ACPR: PRESCALER Mask /
mega64	146:03e976389d16	984
mega64	146:03e976389d16	985	/* TPI Selected Pin Protocol Register Definitions */
mega64	146:03e976389d16	986	#define TPI_SPPR_TXMODE_Pos 0 /!< TPI SPPR: TXMODE Position /
mega64	146:03e976389d16	987	#define TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/) /!< TPI SPPR: TXMODE Mask /
mega64	146:03e976389d16	988
mega64	146:03e976389d16	989	/* TPI Formatter and Flush Status Register Definitions */
mega64	146:03e976389d16	990	#define TPI_FFSR_FtNonStop_Pos 3 /!< TPI FFSR: FtNonStop Position /
mega64	146:03e976389d16	991	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
mega64	146:03e976389d16	992
mega64	146:03e976389d16	993	#define TPI_FFSR_TCPresent_Pos 2 /!< TPI FFSR: TCPresent Position /
mega64	146:03e976389d16	994	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
mega64	146:03e976389d16	995
mega64	146:03e976389d16	996	#define TPI_FFSR_FtStopped_Pos 1 /!< TPI FFSR: FtStopped Position /
mega64	146:03e976389d16	997	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
mega64	146:03e976389d16	998
mega64	146:03e976389d16	999	#define TPI_FFSR_FlInProg_Pos 0 /!< TPI FFSR: FlInProg Position /
mega64	146:03e976389d16	1000	#define TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/) /!< TPI FFSR: FlInProg Mask /
mega64	146:03e976389d16	1001
mega64	146:03e976389d16	1002	/* TPI Formatter and Flush Control Register Definitions */
mega64	146:03e976389d16	1003	#define TPI_FFCR_TrigIn_Pos 8 /!< TPI FFCR: TrigIn Position /
mega64	146:03e976389d16	1004	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
mega64	146:03e976389d16	1005
mega64	146:03e976389d16	1006	#define TPI_FFCR_EnFCont_Pos 1 /!< TPI FFCR: EnFCont Position /
mega64	146:03e976389d16	1007	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
mega64	146:03e976389d16	1008
mega64	146:03e976389d16	1009	/* TPI TRIGGER Register Definitions */
mega64	146:03e976389d16	1010	#define TPI_TRIGGER_TRIGGER_Pos 0 /!< TPI TRIGGER: TRIGGER Position /
mega64	146:03e976389d16	1011	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/) /!< TPI TRIGGER: TRIGGER Mask /
mega64	146:03e976389d16	1012
mega64	146:03e976389d16	1013	/* TPI Integration ETM Data Register Definitions (FIFO0) */
mega64	146:03e976389d16	1014	#define TPI_FIFO0_ITM_ATVALID_Pos 29 /!< TPI FIFO0: ITM_ATVALID Position /
mega64	146:03e976389d16	1015	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
mega64	146:03e976389d16	1016
mega64	146:03e976389d16	1017	#define TPI_FIFO0_ITM_bytecount_Pos 27 /!< TPI FIFO0: ITM_bytecount Position /
mega64	146:03e976389d16	1018	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
mega64	146:03e976389d16	1019
mega64	146:03e976389d16	1020	#define TPI_FIFO0_ETM_ATVALID_Pos 26 /!< TPI FIFO0: ETM_ATVALID Position /
mega64	146:03e976389d16	1021	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
mega64	146:03e976389d16	1022
mega64	146:03e976389d16	1023	#define TPI_FIFO0_ETM_bytecount_Pos 24 /!< TPI FIFO0: ETM_bytecount Position /
mega64	146:03e976389d16	1024	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
mega64	146:03e976389d16	1025
mega64	146:03e976389d16	1026	#define TPI_FIFO0_ETM2_Pos 16 /!< TPI FIFO0: ETM2 Position /
mega64	146:03e976389d16	1027	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
mega64	146:03e976389d16	1028
mega64	146:03e976389d16	1029	#define TPI_FIFO0_ETM1_Pos 8 /!< TPI FIFO0: ETM1 Position /
mega64	146:03e976389d16	1030	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
mega64	146:03e976389d16	1031
mega64	146:03e976389d16	1032	#define TPI_FIFO0_ETM0_Pos 0 /!< TPI FIFO0: ETM0 Position /
mega64	146:03e976389d16	1033	#define TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/) /!< TPI FIFO0: ETM0 Mask /
mega64	146:03e976389d16	1034
mega64	146:03e976389d16	1035	/* TPI ITATBCTR2 Register Definitions */
mega64	146:03e976389d16	1036	#define TPI_ITATBCTR2_ATREADY_Pos 0 /!< TPI ITATBCTR2: ATREADY Position /
mega64	146:03e976389d16	1037	#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY_Pos/) /!< TPI ITATBCTR2: ATREADY Mask /
mega64	146:03e976389d16	1038
mega64	146:03e976389d16	1039	/* TPI Integration ITM Data Register Definitions (FIFO1) */
mega64	146:03e976389d16	1040	#define TPI_FIFO1_ITM_ATVALID_Pos 29 /!< TPI FIFO1: ITM_ATVALID Position /
mega64	146:03e976389d16	1041	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
mega64	146:03e976389d16	1042
mega64	146:03e976389d16	1043	#define TPI_FIFO1_ITM_bytecount_Pos 27 /!< TPI FIFO1: ITM_bytecount Position /
mega64	146:03e976389d16	1044	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
mega64	146:03e976389d16	1045
mega64	146:03e976389d16	1046	#define TPI_FIFO1_ETM_ATVALID_Pos 26 /!< TPI FIFO1: ETM_ATVALID Position /
mega64	146:03e976389d16	1047	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
mega64	146:03e976389d16	1048
mega64	146:03e976389d16	1049	#define TPI_FIFO1_ETM_bytecount_Pos 24 /!< TPI FIFO1: ETM_bytecount Position /
mega64	146:03e976389d16	1050	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
mega64	146:03e976389d16	1051
mega64	146:03e976389d16	1052	#define TPI_FIFO1_ITM2_Pos 16 /!< TPI FIFO1: ITM2 Position /
mega64	146:03e976389d16	1053	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
mega64	146:03e976389d16	1054
mega64	146:03e976389d16	1055	#define TPI_FIFO1_ITM1_Pos 8 /!< TPI FIFO1: ITM1 Position /
mega64	146:03e976389d16	1056	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
mega64	146:03e976389d16	1057
mega64	146:03e976389d16	1058	#define TPI_FIFO1_ITM0_Pos 0 /!< TPI FIFO1: ITM0 Position /
mega64	146:03e976389d16	1059	#define TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/) /!< TPI FIFO1: ITM0 Mask /
mega64	146:03e976389d16	1060
mega64	146:03e976389d16	1061	/* TPI ITATBCTR0 Register Definitions */
mega64	146:03e976389d16	1062	#define TPI_ITATBCTR0_ATREADY_Pos 0 /!< TPI ITATBCTR0: ATREADY Position /
mega64	146:03e976389d16	1063	#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY_Pos/) /!< TPI ITATBCTR0: ATREADY Mask /
mega64	146:03e976389d16	1064
mega64	146:03e976389d16	1065	/* TPI Integration Mode Control Register Definitions */
mega64	146:03e976389d16	1066	#define TPI_ITCTRL_Mode_Pos 0 /!< TPI ITCTRL: Mode Position /
mega64	146:03e976389d16	1067	#define TPI_ITCTRL_Mode_Msk (0x1UL /<< TPI_ITCTRL_Mode_Pos/) /!< TPI ITCTRL: Mode Mask /
mega64	146:03e976389d16	1068
mega64	146:03e976389d16	1069	/* TPI DEVID Register Definitions */
mega64	146:03e976389d16	1070	#define TPI_DEVID_NRZVALID_Pos 11 /!< TPI DEVID: NRZVALID Position /
mega64	146:03e976389d16	1071	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
mega64	146:03e976389d16	1072
mega64	146:03e976389d16	1073	#define TPI_DEVID_MANCVALID_Pos 10 /!< TPI DEVID: MANCVALID Position /
mega64	146:03e976389d16	1074	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
mega64	146:03e976389d16	1075
mega64	146:03e976389d16	1076	#define TPI_DEVID_PTINVALID_Pos 9 /!< TPI DEVID: PTINVALID Position /
mega64	146:03e976389d16	1077	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
mega64	146:03e976389d16	1078
mega64	146:03e976389d16	1079	#define TPI_DEVID_MinBufSz_Pos 6 /!< TPI DEVID: MinBufSz Position /
mega64	146:03e976389d16	1080	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
mega64	146:03e976389d16	1081
mega64	146:03e976389d16	1082	#define TPI_DEVID_AsynClkIn_Pos 5 /!< TPI DEVID: AsynClkIn Position /
mega64	146:03e976389d16	1083	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
mega64	146:03e976389d16	1084
mega64	146:03e976389d16	1085	#define TPI_DEVID_NrTraceInput_Pos 0 /!< TPI DEVID: NrTraceInput Position /
mega64	146:03e976389d16	1086	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/) /!< TPI DEVID: NrTraceInput Mask /
mega64	146:03e976389d16	1087
mega64	146:03e976389d16	1088	/* TPI DEVTYPE Register Definitions */
mega64	146:03e976389d16	1089	#define TPI_DEVTYPE_MajorType_Pos 4 /!< TPI DEVTYPE: MajorType Position /
mega64	146:03e976389d16	1090	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
mega64	146:03e976389d16	1091
mega64	146:03e976389d16	1092	#define TPI_DEVTYPE_SubType_Pos 0 /!< TPI DEVTYPE: SubType Position /
mega64	146:03e976389d16	1093	#define TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/) /!< TPI DEVTYPE: SubType Mask /
mega64	146:03e976389d16	1094
mega64	146:03e976389d16	1095	/@}/ /* end of group CMSIS_TPI */
mega64	146:03e976389d16	1096
mega64	146:03e976389d16	1097
mega64	146:03e976389d16	1098	#if (__MPU_PRESENT == 1)
mega64	146:03e976389d16	1099	/** \ingroup CMSIS_core_register
mega64	146:03e976389d16	1100	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
mega64	146:03e976389d16	1101	\brief Type definitions for the Memory Protection Unit (MPU)
mega64	146:03e976389d16	1102	@{
mega64	146:03e976389d16	1103	*/
mega64	146:03e976389d16	1104
mega64	146:03e976389d16	1105	/** \brief Structure type to access the Memory Protection Unit (MPU).
mega64	146:03e976389d16	1106	*/
mega64	146:03e976389d16	1107	typedef struct
mega64	146:03e976389d16	1108	{
mega64	146:03e976389d16	1109	__I uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
mega64	146:03e976389d16	1110	__IO uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
mega64	146:03e976389d16	1111	__IO uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region RNRber Register /
mega64	146:03e976389d16	1112	__IO uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
mega64	146:03e976389d16	1113	__IO uint32_t RASR; /!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register /
mega64	146:03e976389d16	1114	__IO uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register /
mega64	146:03e976389d16	1115	__IO uint32_t RASR_A1; /!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register /
mega64	146:03e976389d16	1116	__IO uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register /
mega64	146:03e976389d16	1117	__IO uint32_t RASR_A2; /!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register /
mega64	146:03e976389d16	1118	__IO uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register /
mega64	146:03e976389d16	1119	__IO uint32_t RASR_A3; /!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register /
mega64	146:03e976389d16	1120	} MPU_Type;
mega64	146:03e976389d16	1121
mega64	146:03e976389d16	1122	/* MPU Type Register */
mega64	146:03e976389d16	1123	#define MPU_TYPE_IREGION_Pos 16 /!< MPU TYPE: IREGION Position /
mega64	146:03e976389d16	1124	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
mega64	146:03e976389d16	1125
mega64	146:03e976389d16	1126	#define MPU_TYPE_DREGION_Pos 8 /!< MPU TYPE: DREGION Position /
mega64	146:03e976389d16	1127	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
mega64	146:03e976389d16	1128
mega64	146:03e976389d16	1129	#define MPU_TYPE_SEPARATE_Pos 0 /!< MPU TYPE: SEPARATE Position /
mega64	146:03e976389d16	1130	#define MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/) /!< MPU TYPE: SEPARATE Mask /
mega64	146:03e976389d16	1131
mega64	146:03e976389d16	1132	/* MPU Control Register */
mega64	146:03e976389d16	1133	#define MPU_CTRL_PRIVDEFENA_Pos 2 /!< MPU CTRL: PRIVDEFENA Position /
mega64	146:03e976389d16	1134	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
mega64	146:03e976389d16	1135
mega64	146:03e976389d16	1136	#define MPU_CTRL_HFNMIENA_Pos 1 /!< MPU CTRL: HFNMIENA Position /
mega64	146:03e976389d16	1137	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
mega64	146:03e976389d16	1138
mega64	146:03e976389d16	1139	#define MPU_CTRL_ENABLE_Pos 0 /!< MPU CTRL: ENABLE Position /
mega64	146:03e976389d16	1140	#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/) /!< MPU CTRL: ENABLE Mask /
mega64	146:03e976389d16	1141
mega64	146:03e976389d16	1142	/* MPU Region Number Register */
mega64	146:03e976389d16	1143	#define MPU_RNR_REGION_Pos 0 /!< MPU RNR: REGION Position /
mega64	146:03e976389d16	1144	#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/) /!< MPU RNR: REGION Mask /
mega64	146:03e976389d16	1145
mega64	146:03e976389d16	1146	/* MPU Region Base Address Register */
mega64	146:03e976389d16	1147	#define MPU_RBAR_ADDR_Pos 5 /!< MPU RBAR: ADDR Position /
mega64	146:03e976389d16	1148	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
mega64	146:03e976389d16	1149
mega64	146:03e976389d16	1150	#define MPU_RBAR_VALID_Pos 4 /!< MPU RBAR: VALID Position /
mega64	146:03e976389d16	1151	#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /!< MPU RBAR: VALID Mask /
mega64	146:03e976389d16	1152
mega64	146:03e976389d16	1153	#define MPU_RBAR_REGION_Pos 0 /!< MPU RBAR: REGION Position /
mega64	146:03e976389d16	1154	#define MPU_RBAR_REGION_Msk (0xFUL /<< MPU_RBAR_REGION_Pos/) /!< MPU RBAR: REGION Mask /
mega64	146:03e976389d16	1155
mega64	146:03e976389d16	1156	/* MPU Region Attribute and Size Register */
mega64	146:03e976389d16	1157	#define MPU_RASR_ATTRS_Pos 16 /!< MPU RASR: MPU Region Attribute field Position /
mega64	146:03e976389d16	1158	#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /!< MPU RASR: MPU Region Attribute field Mask /
mega64	146:03e976389d16	1159
mega64	146:03e976389d16	1160	#define MPU_RASR_XN_Pos 28 /!< MPU RASR: ATTRS.XN Position /
mega64	146:03e976389d16	1161	#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /!< MPU RASR: ATTRS.XN Mask /
mega64	146:03e976389d16	1162
mega64	146:03e976389d16	1163	#define MPU_RASR_AP_Pos 24 /!< MPU RASR: ATTRS.AP Position /
mega64	146:03e976389d16	1164	#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /!< MPU RASR: ATTRS.AP Mask /
mega64	146:03e976389d16	1165
mega64	146:03e976389d16	1166	#define MPU_RASR_TEX_Pos 19 /!< MPU RASR: ATTRS.TEX Position /
mega64	146:03e976389d16	1167	#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /!< MPU RASR: ATTRS.TEX Mask /
mega64	146:03e976389d16	1168
mega64	146:03e976389d16	1169	#define MPU_RASR_S_Pos 18 /!< MPU RASR: ATTRS.S Position /
mega64	146:03e976389d16	1170	#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /!< MPU RASR: ATTRS.S Mask /
mega64	146:03e976389d16	1171
mega64	146:03e976389d16	1172	#define MPU_RASR_C_Pos 17 /!< MPU RASR: ATTRS.C Position /
mega64	146:03e976389d16	1173	#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /!< MPU RASR: ATTRS.C Mask /
mega64	146:03e976389d16	1174
mega64	146:03e976389d16	1175	#define MPU_RASR_B_Pos 16 /!< MPU RASR: ATTRS.B Position /
mega64	146:03e976389d16	1176	#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /!< MPU RASR: ATTRS.B Mask /
mega64	146:03e976389d16	1177
mega64	146:03e976389d16	1178	#define MPU_RASR_SRD_Pos 8 /!< MPU RASR: Sub-Region Disable Position /
mega64	146:03e976389d16	1179	#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /!< MPU RASR: Sub-Region Disable Mask /
mega64	146:03e976389d16	1180
mega64	146:03e976389d16	1181	#define MPU_RASR_SIZE_Pos 1 /!< MPU RASR: Region Size Field Position /
mega64	146:03e976389d16	1182	#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /!< MPU RASR: Region Size Field Mask /
mega64	146:03e976389d16	1183
mega64	146:03e976389d16	1184	#define MPU_RASR_ENABLE_Pos 0 /!< MPU RASR: Region enable bit Position /
mega64	146:03e976389d16	1185	#define MPU_RASR_ENABLE_Msk (1UL /<< MPU_RASR_ENABLE_Pos/) /!< MPU RASR: Region enable bit Disable Mask /
mega64	146:03e976389d16	1186
mega64	146:03e976389d16	1187	/@} end of group CMSIS_MPU /
mega64	146:03e976389d16	1188	#endif
mega64	146:03e976389d16	1189
mega64	146:03e976389d16	1190
mega64	146:03e976389d16	1191	/** \ingroup CMSIS_core_register
mega64	146:03e976389d16	1192	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
mega64	146:03e976389d16	1193	\brief Type definitions for the Core Debug Registers
mega64	146:03e976389d16	1194	@{
mega64	146:03e976389d16	1195	*/
mega64	146:03e976389d16	1196
mega64	146:03e976389d16	1197	/** \brief Structure type to access the Core Debug Register (CoreDebug).
mega64	146:03e976389d16	1198	*/
mega64	146:03e976389d16	1199	typedef struct
mega64	146:03e976389d16	1200	{
mega64	146:03e976389d16	1201	__IO uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
mega64	146:03e976389d16	1202	__O uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
mega64	146:03e976389d16	1203	__IO uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
mega64	146:03e976389d16	1204	__IO uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
mega64	146:03e976389d16	1205	} CoreDebug_Type;
mega64	146:03e976389d16	1206
mega64	146:03e976389d16	1207	/* Debug Halting Control and Status Register */
mega64	146:03e976389d16	1208	#define CoreDebug_DHCSR_DBGKEY_Pos 16 /!< CoreDebug DHCSR: DBGKEY Position /
mega64	146:03e976389d16	1209	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
mega64	146:03e976389d16	1210
mega64	146:03e976389d16	1211	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /!< CoreDebug DHCSR: S_RESET_ST Position /
mega64	146:03e976389d16	1212	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
mega64	146:03e976389d16	1213
mega64	146:03e976389d16	1214	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /!< CoreDebug DHCSR: S_RETIRE_ST Position /
mega64	146:03e976389d16	1215	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
mega64	146:03e976389d16	1216
mega64	146:03e976389d16	1217	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /!< CoreDebug DHCSR: S_LOCKUP Position /
mega64	146:03e976389d16	1218	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
mega64	146:03e976389d16	1219
mega64	146:03e976389d16	1220	#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /!< CoreDebug DHCSR: S_SLEEP Position /
mega64	146:03e976389d16	1221	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
mega64	146:03e976389d16	1222
mega64	146:03e976389d16	1223	#define CoreDebug_DHCSR_S_HALT_Pos 17 /!< CoreDebug DHCSR: S_HALT Position /
mega64	146:03e976389d16	1224	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
mega64	146:03e976389d16	1225
mega64	146:03e976389d16	1226	#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /!< CoreDebug DHCSR: S_REGRDY Position /
mega64	146:03e976389d16	1227	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
mega64	146:03e976389d16	1228
mega64	146:03e976389d16	1229	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /!< CoreDebug DHCSR: C_SNAPSTALL Position /
mega64	146:03e976389d16	1230	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
mega64	146:03e976389d16	1231
mega64	146:03e976389d16	1232	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /!< CoreDebug DHCSR: C_MASKINTS Position /
mega64	146:03e976389d16	1233	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
mega64	146:03e976389d16	1234
mega64	146:03e976389d16	1235	#define CoreDebug_DHCSR_C_STEP_Pos 2 /!< CoreDebug DHCSR: C_STEP Position /
mega64	146:03e976389d16	1236	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
mega64	146:03e976389d16	1237
mega64	146:03e976389d16	1238	#define CoreDebug_DHCSR_C_HALT_Pos 1 /!< CoreDebug DHCSR: C_HALT Position /
mega64	146:03e976389d16	1239	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
mega64	146:03e976389d16	1240
mega64	146:03e976389d16	1241	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /!< CoreDebug DHCSR: C_DEBUGEN Position /
mega64	146:03e976389d16	1242	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
mega64	146:03e976389d16	1243
mega64	146:03e976389d16	1244	/* Debug Core Register Selector Register */
mega64	146:03e976389d16	1245	#define CoreDebug_DCRSR_REGWnR_Pos 16 /!< CoreDebug DCRSR: REGWnR Position /
mega64	146:03e976389d16	1246	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
mega64	146:03e976389d16	1247
mega64	146:03e976389d16	1248	#define CoreDebug_DCRSR_REGSEL_Pos 0 /!< CoreDebug DCRSR: REGSEL Position /
mega64	146:03e976389d16	1249	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/) /!< CoreDebug DCRSR: REGSEL Mask /
mega64	146:03e976389d16	1250
mega64	146:03e976389d16	1251	/* Debug Exception and Monitor Control Register */
mega64	146:03e976389d16	1252	#define CoreDebug_DEMCR_TRCENA_Pos 24 /!< CoreDebug DEMCR: TRCENA Position /
mega64	146:03e976389d16	1253	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
mega64	146:03e976389d16	1254
mega64	146:03e976389d16	1255	#define CoreDebug_DEMCR_MON_REQ_Pos 19 /!< CoreDebug DEMCR: MON_REQ Position /
mega64	146:03e976389d16	1256	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
mega64	146:03e976389d16	1257
mega64	146:03e976389d16	1258	#define CoreDebug_DEMCR_MON_STEP_Pos 18 /!< CoreDebug DEMCR: MON_STEP Position /
mega64	146:03e976389d16	1259	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
mega64	146:03e976389d16	1260
mega64	146:03e976389d16	1261	#define CoreDebug_DEMCR_MON_PEND_Pos 17 /!< CoreDebug DEMCR: MON_PEND Position /
mega64	146:03e976389d16	1262	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
mega64	146:03e976389d16	1263
mega64	146:03e976389d16	1264	#define CoreDebug_DEMCR_MON_EN_Pos 16 /!< CoreDebug DEMCR: MON_EN Position /
mega64	146:03e976389d16	1265	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
mega64	146:03e976389d16	1266
mega64	146:03e976389d16	1267	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /!< CoreDebug DEMCR: VC_HARDERR Position /
mega64	146:03e976389d16	1268	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
mega64	146:03e976389d16	1269
mega64	146:03e976389d16	1270	#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /!< CoreDebug DEMCR: VC_INTERR Position /
mega64	146:03e976389d16	1271	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
mega64	146:03e976389d16	1272
mega64	146:03e976389d16	1273	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /!< CoreDebug DEMCR: VC_BUSERR Position /
mega64	146:03e976389d16	1274	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
mega64	146:03e976389d16	1275
mega64	146:03e976389d16	1276	#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /!< CoreDebug DEMCR: VC_STATERR Position /
mega64	146:03e976389d16	1277	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
mega64	146:03e976389d16	1278
mega64	146:03e976389d16	1279	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /!< CoreDebug DEMCR: VC_CHKERR Position /
mega64	146:03e976389d16	1280	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
mega64	146:03e976389d16	1281
mega64	146:03e976389d16	1282	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /!< CoreDebug DEMCR: VC_NOCPERR Position /
mega64	146:03e976389d16	1283	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
mega64	146:03e976389d16	1284
mega64	146:03e976389d16	1285	#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /!< CoreDebug DEMCR: VC_MMERR Position /
mega64	146:03e976389d16	1286	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
mega64	146:03e976389d16	1287
mega64	146:03e976389d16	1288	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /!< CoreDebug DEMCR: VC_CORERESET Position /
mega64	146:03e976389d16	1289	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/) /!< CoreDebug DEMCR: VC_CORERESET Mask /
mega64	146:03e976389d16	1290
mega64	146:03e976389d16	1291	/@} end of group CMSIS_CoreDebug /
mega64	146:03e976389d16	1292
mega64	146:03e976389d16	1293
mega64	146:03e976389d16	1294	/** \ingroup CMSIS_core_register
mega64	146:03e976389d16	1295	\defgroup CMSIS_core_base Core Definitions
mega64	146:03e976389d16	1296	\brief Definitions for base addresses, unions, and structures.
mega64	146:03e976389d16	1297	@{
mega64	146:03e976389d16	1298	*/
mega64	146:03e976389d16	1299
mega64	146:03e976389d16	1300	/* Memory mapping of Cortex-M3 Hardware */
mega64	146:03e976389d16	1301	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
mega64	146:03e976389d16	1302	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
mega64	146:03e976389d16	1303	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
mega64	146:03e976389d16	1304	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
mega64	146:03e976389d16	1305	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
mega64	146:03e976389d16	1306	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
mega64	146:03e976389d16	1307	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
mega64	146:03e976389d16	1308	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
mega64	146:03e976389d16	1309
mega64	146:03e976389d16	1310	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
mega64	146:03e976389d16	1311	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
mega64	146:03e976389d16	1312	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
mega64	146:03e976389d16	1313	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
mega64	146:03e976389d16	1314	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
mega64	146:03e976389d16	1315	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
mega64	146:03e976389d16	1316	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
mega64	146:03e976389d16	1317	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE) /!< Core Debug configuration struct */
mega64	146:03e976389d16	1318
mega64	146:03e976389d16	1319	#if (__MPU_PRESENT == 1)
mega64	146:03e976389d16	1320	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
mega64	146:03e976389d16	1321	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
mega64	146:03e976389d16	1322	#endif
mega64	146:03e976389d16	1323
mega64	146:03e976389d16	1324	/@} /
mega64	146:03e976389d16	1325
mega64	146:03e976389d16	1326
mega64	146:03e976389d16	1327
mega64	146:03e976389d16	1328	/*******************************************************************************
mega64	146:03e976389d16	1329	* Hardware Abstraction Layer
mega64	146:03e976389d16	1330	Core Function Interface contains:
mega64	146:03e976389d16	1331	- Core NVIC Functions
mega64	146:03e976389d16	1332	- Core SysTick Functions
mega64	146:03e976389d16	1333	- Core Debug Functions
mega64	146:03e976389d16	1334	- Core Register Access Functions
mega64	146:03e976389d16	1335	******************************************************************************/
mega64	146:03e976389d16	1336	/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
mega64	146:03e976389d16	1337	*/
mega64	146:03e976389d16	1338
mega64	146:03e976389d16	1339
mega64	146:03e976389d16	1340
mega64	146:03e976389d16	1341	/* ########################## NVIC functions #################################### */
mega64	146:03e976389d16	1342	/** \ingroup CMSIS_Core_FunctionInterface
mega64	146:03e976389d16	1343	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
mega64	146:03e976389d16	1344	\brief Functions that manage interrupts and exceptions via the NVIC.
mega64	146:03e976389d16	1345	@{
mega64	146:03e976389d16	1346	*/
mega64	146:03e976389d16	1347
mega64	146:03e976389d16	1348	#ifdef CMSIS_NVIC_VIRTUAL
mega64	146:03e976389d16	1349	#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
mega64	146:03e976389d16	1350	#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
mega64	146:03e976389d16	1351	#endif
mega64	146:03e976389d16	1352	#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
mega64	146:03e976389d16	1353	#else
mega64	146:03e976389d16	1354	#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
mega64	146:03e976389d16	1355	#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
mega64	146:03e976389d16	1356	#define NVIC_EnableIRQ __NVIC_EnableIRQ
mega64	146:03e976389d16	1357	#define NVIC_DisableIRQ __NVIC_DisableIRQ
mega64	146:03e976389d16	1358	#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
mega64	146:03e976389d16	1359	#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
mega64	146:03e976389d16	1360	#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
mega64	146:03e976389d16	1361	#define NVIC_GetActive __NVIC_GetActive
mega64	146:03e976389d16	1362	#define NVIC_SetPriority __NVIC_SetPriority
mega64	146:03e976389d16	1363	#define NVIC_GetPriority __NVIC_GetPriority
mega64	146:03e976389d16	1364	#define NVIC_SystemReset __NVIC_SystemReset
mega64	146:03e976389d16	1365	#endif /* CMSIS_NVIC_VIRTUAL */
mega64	146:03e976389d16	1366
mega64	146:03e976389d16	1367	#ifdef CMSIS_VECTAB_VIRTUAL
mega64	146:03e976389d16	1368	#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
mega64	146:03e976389d16	1369	#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
mega64	146:03e976389d16	1370	#endif
mega64	146:03e976389d16	1371	#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
mega64	146:03e976389d16	1372	#else
mega64	146:03e976389d16	1373	#define NVIC_SetVector __NVIC_SetVector
mega64	146:03e976389d16	1374	#define NVIC_GetVector __NVIC_GetVector
mega64	146:03e976389d16	1375	#endif /* CMSIS_VECTAB_VIRTUAL */
mega64	146:03e976389d16	1376
mega64	146:03e976389d16	1377	/** \brief Set Priority Grouping
mega64	146:03e976389d16	1378
mega64	146:03e976389d16	1379	The function sets the priority grouping field using the required unlock sequence.
mega64	146:03e976389d16	1380	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
mega64	146:03e976389d16	1381	Only values from 0..7 are used.
mega64	146:03e976389d16	1382	In case of a conflict between priority grouping and available
mega64	146:03e976389d16	1383	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
mega64	146:03e976389d16	1384
mega64	146:03e976389d16	1385	\param [in] PriorityGroup Priority grouping field.
mega64	146:03e976389d16	1386	*/
mega64	146:03e976389d16	1387	__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
mega64	146:03e976389d16	1388	{
mega64	146:03e976389d16	1389	uint32_t reg_value;
mega64	146:03e976389d16	1390	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
mega64	146:03e976389d16	1391
mega64	146:03e976389d16	1392	reg_value = SCB->AIRCR; /* read old register configuration */
mega64	146:03e976389d16	1393	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
mega64	146:03e976389d16	1394	reg_value = (reg_value \|
mega64	146:03e976389d16	1395	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
mega64	146:03e976389d16	1396	(PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
mega64	146:03e976389d16	1397	SCB->AIRCR = reg_value;
mega64	146:03e976389d16	1398	}
mega64	146:03e976389d16	1399
mega64	146:03e976389d16	1400
mega64	146:03e976389d16	1401	/** \brief Get Priority Grouping
mega64	146:03e976389d16	1402
mega64	146:03e976389d16	1403	The function reads the priority grouping field from the NVIC Interrupt Controller.
mega64	146:03e976389d16	1404
mega64	146:03e976389d16	1405	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
mega64	146:03e976389d16	1406	*/
mega64	146:03e976389d16	1407	__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
mega64	146:03e976389d16	1408	{
mega64	146:03e976389d16	1409	return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
mega64	146:03e976389d16	1410	}
mega64	146:03e976389d16	1411
mega64	146:03e976389d16	1412
mega64	146:03e976389d16	1413	/** \brief Enable External Interrupt
mega64	146:03e976389d16	1414
mega64	146:03e976389d16	1415	The function enables a device-specific interrupt in the NVIC interrupt controller.
mega64	146:03e976389d16	1416
mega64	146:03e976389d16	1417	\param [in] IRQn External interrupt number. Value cannot be negative.
mega64	146:03e976389d16	1418	*/
mega64	146:03e976389d16	1419	__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
mega64	146:03e976389d16	1420	{
mega64	146:03e976389d16	1421	NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
mega64	146:03e976389d16	1422	}
mega64	146:03e976389d16	1423
mega64	146:03e976389d16	1424
mega64	146:03e976389d16	1425	/** \brief Disable External Interrupt
mega64	146:03e976389d16	1426
mega64	146:03e976389d16	1427	The function disables a device-specific interrupt in the NVIC interrupt controller.
mega64	146:03e976389d16	1428
mega64	146:03e976389d16	1429	\param [in] IRQn External interrupt number. Value cannot be negative.
mega64	146:03e976389d16	1430	*/
mega64	146:03e976389d16	1431	__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
mega64	146:03e976389d16	1432	{
mega64	146:03e976389d16	1433	NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
mega64	146:03e976389d16	1434	__DSB();
mega64	146:03e976389d16	1435	__ISB();
mega64	146:03e976389d16	1436	}
mega64	146:03e976389d16	1437
mega64	146:03e976389d16	1438
mega64	146:03e976389d16	1439	/** \brief Get Pending Interrupt
mega64	146:03e976389d16	1440
mega64	146:03e976389d16	1441	The function reads the pending register in the NVIC and returns the pending bit
mega64	146:03e976389d16	1442	for the specified interrupt.
mega64	146:03e976389d16	1443
mega64	146:03e976389d16	1444	\param [in] IRQn Interrupt number.
mega64	146:03e976389d16	1445
mega64	146:03e976389d16	1446	\return 0 Interrupt status is not pending.
mega64	146:03e976389d16	1447	\return 1 Interrupt status is pending.
mega64	146:03e976389d16	1448	*/
mega64	146:03e976389d16	1449	__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
mega64	146:03e976389d16	1450	{
mega64	146:03e976389d16	1451	return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
mega64	146:03e976389d16	1452	}
mega64	146:03e976389d16	1453
mega64	146:03e976389d16	1454
mega64	146:03e976389d16	1455	/** \brief Set Pending Interrupt
mega64	146:03e976389d16	1456
mega64	146:03e976389d16	1457	The function sets the pending bit of an external interrupt.
mega64	146:03e976389d16	1458
mega64	146:03e976389d16	1459	\param [in] IRQn Interrupt number. Value cannot be negative.
mega64	146:03e976389d16	1460	*/
mega64	146:03e976389d16	1461	__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
mega64	146:03e976389d16	1462	{
mega64	146:03e976389d16	1463	NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
mega64	146:03e976389d16	1464	}
mega64	146:03e976389d16	1465
mega64	146:03e976389d16	1466
mega64	146:03e976389d16	1467	/** \brief Clear Pending Interrupt
mega64	146:03e976389d16	1468
mega64	146:03e976389d16	1469	The function clears the pending bit of an external interrupt.
mega64	146:03e976389d16	1470
mega64	146:03e976389d16	1471	\param [in] IRQn External interrupt number. Value cannot be negative.
mega64	146:03e976389d16	1472	*/
mega64	146:03e976389d16	1473	__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
mega64	146:03e976389d16	1474	{
mega64	146:03e976389d16	1475	NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
mega64	146:03e976389d16	1476	}
mega64	146:03e976389d16	1477
mega64	146:03e976389d16	1478
mega64	146:03e976389d16	1479	/** \brief Get Active Interrupt
mega64	146:03e976389d16	1480
mega64	146:03e976389d16	1481	The function reads the active register in NVIC and returns the active bit.
mega64	146:03e976389d16	1482
mega64	146:03e976389d16	1483	\param [in] IRQn Interrupt number.
mega64	146:03e976389d16	1484
mega64	146:03e976389d16	1485	\return 0 Interrupt status is not active.
mega64	146:03e976389d16	1486	\return 1 Interrupt status is active.
mega64	146:03e976389d16	1487	*/
mega64	146:03e976389d16	1488	__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
mega64	146:03e976389d16	1489	{
mega64	146:03e976389d16	1490	return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
mega64	146:03e976389d16	1491	}
mega64	146:03e976389d16	1492
mega64	146:03e976389d16	1493
mega64	146:03e976389d16	1494	/** \brief Set Interrupt Priority
mega64	146:03e976389d16	1495
mega64	146:03e976389d16	1496	The function sets the priority of an interrupt.
mega64	146:03e976389d16	1497
mega64	146:03e976389d16	1498	\note The priority cannot be set for every core interrupt.
mega64	146:03e976389d16	1499
mega64	146:03e976389d16	1500	\param [in] IRQn Interrupt number.
mega64	146:03e976389d16	1501	\param [in] priority Priority to set.
mega64	146:03e976389d16	1502	*/
mega64	146:03e976389d16	1503	__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
mega64	146:03e976389d16	1504	{
mega64	146:03e976389d16	1505	if((int32_t)IRQn < 0) {
mega64	146:03e976389d16	1506	SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
mega64	146:03e976389d16	1507	}
mega64	146:03e976389d16	1508	else {
mega64	146:03e976389d16	1509	NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
mega64	146:03e976389d16	1510	}
mega64	146:03e976389d16	1511	}
mega64	146:03e976389d16	1512
mega64	146:03e976389d16	1513
mega64	146:03e976389d16	1514	/** \brief Get Interrupt Priority
mega64	146:03e976389d16	1515
mega64	146:03e976389d16	1516	The function reads the priority of an interrupt. The interrupt
mega64	146:03e976389d16	1517	number can be positive to specify an external (device specific)
mega64	146:03e976389d16	1518	interrupt, or negative to specify an internal (core) interrupt.
mega64	146:03e976389d16	1519
mega64	146:03e976389d16	1520
mega64	146:03e976389d16	1521	\param [in] IRQn Interrupt number.
mega64	146:03e976389d16	1522	\return Interrupt Priority. Value is aligned automatically to the implemented
mega64	146:03e976389d16	1523	priority bits of the microcontroller.
mega64	146:03e976389d16	1524	*/
mega64	146:03e976389d16	1525	__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
mega64	146:03e976389d16	1526	{
mega64	146:03e976389d16	1527
mega64	146:03e976389d16	1528	if((int32_t)IRQn < 0) {
mega64	146:03e976389d16	1529	return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
mega64	146:03e976389d16	1530	}
mega64	146:03e976389d16	1531	else {
mega64	146:03e976389d16	1532	return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
mega64	146:03e976389d16	1533	}
mega64	146:03e976389d16	1534	}
mega64	146:03e976389d16	1535
mega64	146:03e976389d16	1536
mega64	146:03e976389d16	1537	/** \brief Encode Priority
mega64	146:03e976389d16	1538
mega64	146:03e976389d16	1539	The function encodes the priority for an interrupt with the given priority group,
mega64	146:03e976389d16	1540	preemptive priority value, and subpriority value.
mega64	146:03e976389d16	1541	In case of a conflict between priority grouping and available
mega64	146:03e976389d16	1542	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
mega64	146:03e976389d16	1543
mega64	146:03e976389d16	1544	\param [in] PriorityGroup Used priority group.
mega64	146:03e976389d16	1545	\param [in] PreemptPriority Preemptive priority value (starting from 0).
mega64	146:03e976389d16	1546	\param [in] SubPriority Subpriority value (starting from 0).
mega64	146:03e976389d16	1547	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
mega64	146:03e976389d16	1548	*/
mega64	146:03e976389d16	1549	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
mega64	146:03e976389d16	1550	{
mega64	146:03e976389d16	1551	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
mega64	146:03e976389d16	1552	uint32_t PreemptPriorityBits;
mega64	146:03e976389d16	1553	uint32_t SubPriorityBits;
mega64	146:03e976389d16	1554
mega64	146:03e976389d16	1555	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
mega64	146:03e976389d16	1556	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
mega64	146:03e976389d16	1557
mega64	146:03e976389d16	1558	return (
mega64	146:03e976389d16	1559	((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) \|
mega64	146:03e976389d16	1560	((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
mega64	146:03e976389d16	1561	);
mega64	146:03e976389d16	1562	}
mega64	146:03e976389d16	1563
mega64	146:03e976389d16	1564
mega64	146:03e976389d16	1565	/** \brief Decode Priority
mega64	146:03e976389d16	1566
mega64	146:03e976389d16	1567	The function decodes an interrupt priority value with a given priority group to
mega64	146:03e976389d16	1568	preemptive priority value and subpriority value.
mega64	146:03e976389d16	1569	In case of a conflict between priority grouping and available
mega64	146:03e976389d16	1570	priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
mega64	146:03e976389d16	1571
mega64	146:03e976389d16	1572	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
mega64	146:03e976389d16	1573	\param [in] PriorityGroup Used priority group.
mega64	146:03e976389d16	1574	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
mega64	146:03e976389d16	1575	\param [out] pSubPriority Subpriority value (starting from 0).
mega64	146:03e976389d16	1576	*/
mega64	146:03e976389d16	1577	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
mega64	146:03e976389d16	1578	{
mega64	146:03e976389d16	1579	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
mega64	146:03e976389d16	1580	uint32_t PreemptPriorityBits;
mega64	146:03e976389d16	1581	uint32_t SubPriorityBits;
mega64	146:03e976389d16	1582
mega64	146:03e976389d16	1583	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
mega64	146:03e976389d16	1584	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
mega64	146:03e976389d16	1585
mega64	146:03e976389d16	1586	*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
mega64	146:03e976389d16	1587	*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
mega64	146:03e976389d16	1588	}
mega64	146:03e976389d16	1589
mega64	146:03e976389d16	1590
mega64	146:03e976389d16	1591	/** \brief System Reset
mega64	146:03e976389d16	1592
mega64	146:03e976389d16	1593	The function initiates a system reset request to reset the MCU.
mega64	146:03e976389d16	1594	*/
mega64	146:03e976389d16	1595	__STATIC_INLINE void __NVIC_SystemReset(void)
mega64	146:03e976389d16	1596	{
mega64	146:03e976389d16	1597	__DSB(); /* Ensure all outstanding memory accesses included
mega64	146:03e976389d16	1598	buffered write are completed before reset */
mega64	146:03e976389d16	1599	SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
mega64	146:03e976389d16	1600	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
mega64	146:03e976389d16	1601	SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
mega64	146:03e976389d16	1602	__DSB(); /* Ensure completion of memory access */
mega64	146:03e976389d16	1603	while(1) { __NOP(); } /* wait until reset */
mega64	146:03e976389d16	1604	}
mega64	146:03e976389d16	1605
mega64	146:03e976389d16	1606	/@} end of CMSIS_Core_NVICFunctions /
mega64	146:03e976389d16	1607
mega64	146:03e976389d16	1608
mega64	146:03e976389d16	1609
mega64	146:03e976389d16	1610	/* ################################## SysTick function ############################################ */
mega64	146:03e976389d16	1611	/** \ingroup CMSIS_Core_FunctionInterface
mega64	146:03e976389d16	1612	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
mega64	146:03e976389d16	1613	\brief Functions that configure the System.
mega64	146:03e976389d16	1614	@{
mega64	146:03e976389d16	1615	*/
mega64	146:03e976389d16	1616
mega64	146:03e976389d16	1617	#if (__Vendor_SysTickConfig == 0)
mega64	146:03e976389d16	1618
mega64	146:03e976389d16	1619	/** \brief System Tick Configuration
mega64	146:03e976389d16	1620
mega64	146:03e976389d16	1621	The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
mega64	146:03e976389d16	1622	Counter is in free running mode to generate periodic interrupts.
mega64	146:03e976389d16	1623
mega64	146:03e976389d16	1624	\param [in] ticks Number of ticks between two interrupts.
mega64	146:03e976389d16	1625
mega64	146:03e976389d16	1626	\return 0 Function succeeded.
mega64	146:03e976389d16	1627	\return 1 Function failed.
mega64	146:03e976389d16	1628
mega64	146:03e976389d16	1629	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
mega64	146:03e976389d16	1630	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
mega64	146:03e976389d16	1631	must contain a vendor-specific implementation of this function.
mega64	146:03e976389d16	1632
mega64	146:03e976389d16	1633	*/
mega64	146:03e976389d16	1634	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
mega64	146:03e976389d16	1635	{
mega64	146:03e976389d16	1636	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
mega64	146:03e976389d16	1637
mega64	146:03e976389d16	1638	SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
mega64	146:03e976389d16	1639	NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
mega64	146:03e976389d16	1640	SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
mega64	146:03e976389d16	1641	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
mega64	146:03e976389d16	1642	SysTick_CTRL_TICKINT_Msk \|
mega64	146:03e976389d16	1643	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
mega64	146:03e976389d16	1644	return (0UL); /* Function successful */
mega64	146:03e976389d16	1645	}
mega64	146:03e976389d16	1646
mega64	146:03e976389d16	1647	#endif
mega64	146:03e976389d16	1648
mega64	146:03e976389d16	1649	/@} end of CMSIS_Core_SysTickFunctions /
mega64	146:03e976389d16	1650
mega64	146:03e976389d16	1651
mega64	146:03e976389d16	1652
mega64	146:03e976389d16	1653	/* ##################################### Debug In/Output function ########################################### */
mega64	146:03e976389d16	1654	/** \ingroup CMSIS_Core_FunctionInterface
mega64	146:03e976389d16	1655	\defgroup CMSIS_core_DebugFunctions ITM Functions
mega64	146:03e976389d16	1656	\brief Functions that access the ITM debug interface.
mega64	146:03e976389d16	1657	@{
mega64	146:03e976389d16	1658	*/
mega64	146:03e976389d16	1659
mega64	146:03e976389d16	1660	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
mega64	146:03e976389d16	1661	#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
mega64	146:03e976389d16	1662
mega64	146:03e976389d16	1663
mega64	146:03e976389d16	1664	/** \brief ITM Send Character
mega64	146:03e976389d16	1665
mega64	146:03e976389d16	1666	The function transmits a character via the ITM channel 0, and
mega64	146:03e976389d16	1667	\li Just returns when no debugger is connected that has booked the output.
mega64	146:03e976389d16	1668	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
mega64	146:03e976389d16	1669
mega64	146:03e976389d16	1670	\param [in] ch Character to transmit.
mega64	146:03e976389d16	1671
mega64	146:03e976389d16	1672	\returns Character to transmit.
mega64	146:03e976389d16	1673	*/
mega64	146:03e976389d16	1674	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
mega64	146:03e976389d16	1675	{
mega64	146:03e976389d16	1676	if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
mega64	146:03e976389d16	1677	((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
mega64	146:03e976389d16	1678	{
mega64	146:03e976389d16	1679	while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
mega64	146:03e976389d16	1680	ITM->PORT[0].u8 = (uint8_t)ch;
mega64	146:03e976389d16	1681	}
mega64	146:03e976389d16	1682	return (ch);
mega64	146:03e976389d16	1683	}
mega64	146:03e976389d16	1684
mega64	146:03e976389d16	1685
mega64	146:03e976389d16	1686	/** \brief ITM Receive Character
mega64	146:03e976389d16	1687
mega64	146:03e976389d16	1688	The function inputs a character via the external variable \ref ITM_RxBuffer.
mega64	146:03e976389d16	1689
mega64	146:03e976389d16	1690	\return Received character.
mega64	146:03e976389d16	1691	\return -1 No character pending.
mega64	146:03e976389d16	1692	*/
mega64	146:03e976389d16	1693	__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
mega64	146:03e976389d16	1694	int32_t ch = -1; /* no character available */
mega64	146:03e976389d16	1695
mega64	146:03e976389d16	1696	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
mega64	146:03e976389d16	1697	ch = ITM_RxBuffer;
mega64	146:03e976389d16	1698	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
mega64	146:03e976389d16	1699	}
mega64	146:03e976389d16	1700
mega64	146:03e976389d16	1701	return (ch);
mega64	146:03e976389d16	1702	}
mega64	146:03e976389d16	1703
mega64	146:03e976389d16	1704
mega64	146:03e976389d16	1705	/** \brief ITM Check Character
mega64	146:03e976389d16	1706
mega64	146:03e976389d16	1707	The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
mega64	146:03e976389d16	1708
mega64	146:03e976389d16	1709	\return 0 No character available.
mega64	146:03e976389d16	1710	\return 1 Character available.
mega64	146:03e976389d16	1711	*/
mega64	146:03e976389d16	1712	__STATIC_INLINE int32_t ITM_CheckChar (void) {
mega64	146:03e976389d16	1713
mega64	146:03e976389d16	1714	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
mega64	146:03e976389d16	1715	return (0); /* no character available */
mega64	146:03e976389d16	1716	} else {
mega64	146:03e976389d16	1717	return (1); /* character available */
mega64	146:03e976389d16	1718	}
mega64	146:03e976389d16	1719	}
mega64	146:03e976389d16	1720
mega64	146:03e976389d16	1721	/@} end of CMSIS_core_DebugFunctions /
mega64	146:03e976389d16	1722
mega64	146:03e976389d16	1723
mega64	146:03e976389d16	1724
mega64	146:03e976389d16	1725
mega64	146:03e976389d16	1726	#ifdef __cplusplus
mega64	146:03e976389d16	1727	}
mega64	146:03e976389d16	1728	#endif
mega64	146:03e976389d16	1729
mega64	146:03e976389d16	1730	#endif /* __CORE_CM3_H_DEPENDANT */
mega64	146:03e976389d16	1731
mega64	146:03e976389d16	1732	#endif /* __CMSIS_GENERIC */

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Type:	Library
Created:	16 Mar 2017
Imports:	228
Forks:	0
Commits:	149
Dependents:	0
Dependencies:	0
Followers:	18
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The code in this repository is MIT licensed.

The code in this repository is Apache licensed.

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cmsis/core_cm3.h@148:8b0b02bf146f, 2017-04-27 (annotated)

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