Nothing Special / mbed-STM32F103C8

Modification of Mbed-dev library for LQFP48 package microcontrollers: STM32F103C8 (STM32F103C8T6) and STM32F103CB (STM32F103CBT6) (Bluepill boards, Maple mini etc. )

Fork of mbed-STM32F103C8_org by Nothing Special

Library for STM32F103C8 (Bluepill boards etc.).
Use this instead of mbed library.
This library allows the size of the code in the FLASH up to 128kB. Therefore, code also runs on microcontrollers STM32F103CB (eg. Maple mini).
But in the case of STM32F103C8, check the size of the resulting code would not exceed 64kB.

To compile a program with this library, use NUCLEO-F103RB as the target name. !

Changes:

  • Corrected initialization of the HSE + crystal clock (mbed permanent bug), allowing the use of on-board xtal (8MHz).(1)
  • Additionally, it also set USB clock (48Mhz).(2)
  • Definitions of pins and peripherals adjusted to LQFP48 case.
  • Board led LED1 is now PC_13 (3)
  • USER_BUTTON is now PC_14 (4)

    Now the library is complete rebuilt based on mbed-dev v160 (and not yet fully tested).

notes
(1) - In case 8MHz xtal on board, CPU frequency is 72MHz. Without xtal is 64MHz.
(2) - Using the USB interface is only possible if STM32 is clocking by on-board 8MHz xtal or external clock signal 8MHz on the OSC_IN pin.
(3) - On Bluepill board led operation is reversed, i.e. 0 - led on, 1 - led off.
(4) - Bluepill board has no real user button

Information

After export to SW4STM (AC6):

  • add line #include "mbed_config.h" in files Serial.h and RawSerial.h
  • in project properties change Optimisation Level to Optimise for size (-Os)

cmsis/core_caFunc.h@148:8b0b02bf146f, 2017-04-27 (annotated)

Committer:
mega64
Date:
Thu Apr 27 23:56:38 2017 +0000
Revision:
148:8b0b02bf146f
Parent:
146:03e976389d16 
Remove unnecessary folders

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mega64 146:03e976389d16 1 /**************************************************************************//**
mega64 146:03e976389d16 2 * @file core_caFunc.h
mega64 146:03e976389d16 3 * @brief CMSIS Cortex-A Core Function Access Header File
mega64 146:03e976389d16 4 * @version V3.10
mega64 146:03e976389d16 5 * @date 30 Oct 2013
mega64 146:03e976389d16 6 *
mega64 146:03e976389d16 7 * @note
mega64 146:03e976389d16 8 *
mega64 146:03e976389d16 9 ******************************************************************************/
mega64 146:03e976389d16 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
mega64 146:03e976389d16 11
mega64 146:03e976389d16 12 All rights reserved.
mega64 146:03e976389d16 13 Redistribution and use in source and binary forms, with or without
mega64 146:03e976389d16 14 modification, are permitted provided that the following conditions are met:
mega64 146:03e976389d16 15 - Redistributions of source code must retain the above copyright
mega64 146:03e976389d16 16 notice, this list of conditions and the following disclaimer.
mega64 146:03e976389d16 17 - Redistributions in binary form must reproduce the above copyright
mega64 146:03e976389d16 18 notice, this list of conditions and the following disclaimer in the
mega64 146:03e976389d16 19 documentation and/or other materials provided with the distribution.
mega64 146:03e976389d16 20 - Neither the name of ARM nor the names of its contributors may be used
mega64 146:03e976389d16 21 to endorse or promote products derived from this software without
mega64 146:03e976389d16 22 specific prior written permission.
mega64 146:03e976389d16 23 *
mega64 146:03e976389d16 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mega64 146:03e976389d16 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mega64 146:03e976389d16 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
mega64 146:03e976389d16 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
mega64 146:03e976389d16 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
mega64 146:03e976389d16 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
mega64 146:03e976389d16 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mega64 146:03e976389d16 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mega64 146:03e976389d16 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
mega64 146:03e976389d16 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mega64 146:03e976389d16 34 POSSIBILITY OF SUCH DAMAGE.
mega64 146:03e976389d16 35 ---------------------------------------------------------------------------*/
mega64 146:03e976389d16 36
mega64 146:03e976389d16 37
mega64 146:03e976389d16 38 #ifndef __CORE_CAFUNC_H__
mega64 146:03e976389d16 39 #define __CORE_CAFUNC_H__
mega64 146:03e976389d16 40
mega64 146:03e976389d16 41
mega64 146:03e976389d16 42 /* ########################### Core Function Access ########################### */
mega64 146:03e976389d16 43 /** \ingroup CMSIS_Core_FunctionInterface
mega64 146:03e976389d16 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
mega64 146:03e976389d16 45 @{
mega64 146:03e976389d16 46 */
mega64 146:03e976389d16 47
mega64 146:03e976389d16 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
mega64 146:03e976389d16 49 /* ARM armcc specific functions */
mega64 146:03e976389d16 50
mega64 146:03e976389d16 51 #if (__ARMCC_VERSION < 400677)
mega64 146:03e976389d16 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
mega64 146:03e976389d16 53 #endif
mega64 146:03e976389d16 54
mega64 146:03e976389d16 55 #define MODE_USR 0x10
mega64 146:03e976389d16 56 #define MODE_FIQ 0x11
mega64 146:03e976389d16 57 #define MODE_IRQ 0x12
mega64 146:03e976389d16 58 #define MODE_SVC 0x13
mega64 146:03e976389d16 59 #define MODE_MON 0x16
mega64 146:03e976389d16 60 #define MODE_ABT 0x17
mega64 146:03e976389d16 61 #define MODE_HYP 0x1A
mega64 146:03e976389d16 62 #define MODE_UND 0x1B
mega64 146:03e976389d16 63 #define MODE_SYS 0x1F
mega64 146:03e976389d16 64
mega64 146:03e976389d16 65 /** \brief Get APSR Register
mega64 146:03e976389d16 66
mega64 146:03e976389d16 67 This function returns the content of the APSR Register.
mega64 146:03e976389d16 68
mega64 146:03e976389d16 69 \return APSR Register value
mega64 146:03e976389d16 70 */
mega64 146:03e976389d16 71 __STATIC_INLINE uint32_t __get_APSR(void)
mega64 146:03e976389d16 72 {
mega64 146:03e976389d16 73 register uint32_t __regAPSR __ASM("apsr");
mega64 146:03e976389d16 74 return(__regAPSR);
mega64 146:03e976389d16 75 }
mega64 146:03e976389d16 76
mega64 146:03e976389d16 77
mega64 146:03e976389d16 78 /** \brief Get CPSR Register
mega64 146:03e976389d16 79
mega64 146:03e976389d16 80 This function returns the content of the CPSR Register.
mega64 146:03e976389d16 81
mega64 146:03e976389d16 82 \return CPSR Register value
mega64 146:03e976389d16 83 */
mega64 146:03e976389d16 84 __STATIC_INLINE uint32_t __get_CPSR(void)
mega64 146:03e976389d16 85 {
mega64 146:03e976389d16 86 register uint32_t __regCPSR __ASM("cpsr");
mega64 146:03e976389d16 87 return(__regCPSR);
mega64 146:03e976389d16 88 }
mega64 146:03e976389d16 89
mega64 146:03e976389d16 90 /** \brief Set Stack Pointer
mega64 146:03e976389d16 91
mega64 146:03e976389d16 92 This function assigns the given value to the current stack pointer.
mega64 146:03e976389d16 93
mega64 146:03e976389d16 94 \param [in] topOfStack Stack Pointer value to set
mega64 146:03e976389d16 95 */
mega64 146:03e976389d16 96 register uint32_t __regSP __ASM("sp");
mega64 146:03e976389d16 97 __STATIC_INLINE void __set_SP(uint32_t topOfStack)
mega64 146:03e976389d16 98 {
mega64 146:03e976389d16 99 __regSP = topOfStack;
mega64 146:03e976389d16 100 }
mega64 146:03e976389d16 101
mega64 146:03e976389d16 102
mega64 146:03e976389d16 103 /** \brief Get link register
mega64 146:03e976389d16 104
mega64 146:03e976389d16 105 This function returns the value of the link register
mega64 146:03e976389d16 106
mega64 146:03e976389d16 107 \return Value of link register
mega64 146:03e976389d16 108 */
mega64 146:03e976389d16 109 register uint32_t __reglr __ASM("lr");
mega64 146:03e976389d16 110 __STATIC_INLINE uint32_t __get_LR(void)
mega64 146:03e976389d16 111 {
mega64 146:03e976389d16 112 return(__reglr);
mega64 146:03e976389d16 113 }
mega64 146:03e976389d16 114
mega64 146:03e976389d16 115 /** \brief Set link register
mega64 146:03e976389d16 116
mega64 146:03e976389d16 117 This function sets the value of the link register
mega64 146:03e976389d16 118
mega64 146:03e976389d16 119 \param [in] lr LR value to set
mega64 146:03e976389d16 120 */
mega64 146:03e976389d16 121 __STATIC_INLINE void __set_LR(uint32_t lr)
mega64 146:03e976389d16 122 {
mega64 146:03e976389d16 123 __reglr = lr;
mega64 146:03e976389d16 124 }
mega64 146:03e976389d16 125
mega64 146:03e976389d16 126 /** \brief Set Process Stack Pointer
mega64 146:03e976389d16 127
mega64 146:03e976389d16 128 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
mega64 146:03e976389d16 129
mega64 146:03e976389d16 130 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
mega64 146:03e976389d16 131 */
mega64 146:03e976389d16 132 __STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
mega64 146:03e976389d16 133 {
mega64 146:03e976389d16 134 ARM
mega64 146:03e976389d16 135 PRESERVE8
mega64 146:03e976389d16 136
mega64 146:03e976389d16 137 BIC R0, R0, #7 ;ensure stack is 8-byte aligned
mega64 146:03e976389d16 138 MRS R1, CPSR
mega64 146:03e976389d16 139 CPS #MODE_SYS ;no effect in USR mode
mega64 146:03e976389d16 140 MOV SP, R0
mega64 146:03e976389d16 141 MSR CPSR_c, R1 ;no effect in USR mode
mega64 146:03e976389d16 142 ISB
mega64 146:03e976389d16 143 BX LR
mega64 146:03e976389d16 144
mega64 146:03e976389d16 145 }
mega64 146:03e976389d16 146
mega64 146:03e976389d16 147 /** \brief Set User Mode
mega64 146:03e976389d16 148
mega64 146:03e976389d16 149 This function changes the processor state to User Mode
mega64 146:03e976389d16 150 */
mega64 146:03e976389d16 151 __STATIC_ASM void __set_CPS_USR(void)
mega64 146:03e976389d16 152 {
mega64 146:03e976389d16 153 ARM
mega64 146:03e976389d16 154
mega64 146:03e976389d16 155 CPS #MODE_USR
mega64 146:03e976389d16 156 BX LR
mega64 146:03e976389d16 157 }
mega64 146:03e976389d16 158
mega64 146:03e976389d16 159
mega64 146:03e976389d16 160 /** \brief Enable FIQ
mega64 146:03e976389d16 161
mega64 146:03e976389d16 162 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
mega64 146:03e976389d16 163 Can only be executed in Privileged modes.
mega64 146:03e976389d16 164 */
mega64 146:03e976389d16 165 #define __enable_fault_irq __enable_fiq
mega64 146:03e976389d16 166
mega64 146:03e976389d16 167
mega64 146:03e976389d16 168 /** \brief Disable FIQ
mega64 146:03e976389d16 169
mega64 146:03e976389d16 170 This function disables FIQ interrupts by setting the F-bit in the CPSR.
mega64 146:03e976389d16 171 Can only be executed in Privileged modes.
mega64 146:03e976389d16 172 */
mega64 146:03e976389d16 173 #define __disable_fault_irq __disable_fiq
mega64 146:03e976389d16 174
mega64 146:03e976389d16 175
mega64 146:03e976389d16 176 /** \brief Get FPSCR
mega64 146:03e976389d16 177
mega64 146:03e976389d16 178 This function returns the current value of the Floating Point Status/Control register.
mega64 146:03e976389d16 179
mega64 146:03e976389d16 180 \return Floating Point Status/Control register value
mega64 146:03e976389d16 181 */
mega64 146:03e976389d16 182 __STATIC_INLINE uint32_t __get_FPSCR(void)
mega64 146:03e976389d16 183 {
mega64 146:03e976389d16 184 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
mega64 146:03e976389d16 185 register uint32_t __regfpscr __ASM("fpscr");
mega64 146:03e976389d16 186 return(__regfpscr);
mega64 146:03e976389d16 187 #else
mega64 146:03e976389d16 188 return(0);
mega64 146:03e976389d16 189 #endif
mega64 146:03e976389d16 190 }
mega64 146:03e976389d16 191
mega64 146:03e976389d16 192
mega64 146:03e976389d16 193 /** \brief Set FPSCR
mega64 146:03e976389d16 194
mega64 146:03e976389d16 195 This function assigns the given value to the Floating Point Status/Control register.
mega64 146:03e976389d16 196
mega64 146:03e976389d16 197 \param [in] fpscr Floating Point Status/Control value to set
mega64 146:03e976389d16 198 */
mega64 146:03e976389d16 199 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
mega64 146:03e976389d16 200 {
mega64 146:03e976389d16 201 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
mega64 146:03e976389d16 202 register uint32_t __regfpscr __ASM("fpscr");
mega64 146:03e976389d16 203 __regfpscr = (fpscr);
mega64 146:03e976389d16 204 #endif
mega64 146:03e976389d16 205 }
mega64 146:03e976389d16 206
mega64 146:03e976389d16 207 /** \brief Get FPEXC
mega64 146:03e976389d16 208
mega64 146:03e976389d16 209 This function returns the current value of the Floating Point Exception Control register.
mega64 146:03e976389d16 210
mega64 146:03e976389d16 211 \return Floating Point Exception Control register value
mega64 146:03e976389d16 212 */
mega64 146:03e976389d16 213 __STATIC_INLINE uint32_t __get_FPEXC(void)
mega64 146:03e976389d16 214 {
mega64 146:03e976389d16 215 #if (__FPU_PRESENT == 1)
mega64 146:03e976389d16 216 register uint32_t __regfpexc __ASM("fpexc");
mega64 146:03e976389d16 217 return(__regfpexc);
mega64 146:03e976389d16 218 #else
mega64 146:03e976389d16 219 return(0);
mega64 146:03e976389d16 220 #endif
mega64 146:03e976389d16 221 }
mega64 146:03e976389d16 222
mega64 146:03e976389d16 223
mega64 146:03e976389d16 224 /** \brief Set FPEXC
mega64 146:03e976389d16 225
mega64 146:03e976389d16 226 This function assigns the given value to the Floating Point Exception Control register.
mega64 146:03e976389d16 227
mega64 146:03e976389d16 228 \param [in] fpscr Floating Point Exception Control value to set
mega64 146:03e976389d16 229 */
mega64 146:03e976389d16 230 __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
mega64 146:03e976389d16 231 {
mega64 146:03e976389d16 232 #if (__FPU_PRESENT == 1)
mega64 146:03e976389d16 233 register uint32_t __regfpexc __ASM("fpexc");
mega64 146:03e976389d16 234 __regfpexc = (fpexc);
mega64 146:03e976389d16 235 #endif
mega64 146:03e976389d16 236 }
mega64 146:03e976389d16 237
mega64 146:03e976389d16 238 /** \brief Get CPACR
mega64 146:03e976389d16 239
mega64 146:03e976389d16 240 This function returns the current value of the Coprocessor Access Control register.
mega64 146:03e976389d16 241
mega64 146:03e976389d16 242 \return Coprocessor Access Control register value
mega64 146:03e976389d16 243 */
mega64 146:03e976389d16 244 __STATIC_INLINE uint32_t __get_CPACR(void)
mega64 146:03e976389d16 245 {
mega64 146:03e976389d16 246 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
mega64 146:03e976389d16 247 return __regCPACR;
mega64 146:03e976389d16 248 }
mega64 146:03e976389d16 249
mega64 146:03e976389d16 250 /** \brief Set CPACR
mega64 146:03e976389d16 251
mega64 146:03e976389d16 252 This function assigns the given value to the Coprocessor Access Control register.
mega64 146:03e976389d16 253
mega64 146:03e976389d16 254 \param [in] cpacr Coprocessor Acccess Control value to set
mega64 146:03e976389d16 255 */
mega64 146:03e976389d16 256 __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
mega64 146:03e976389d16 257 {
mega64 146:03e976389d16 258 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
mega64 146:03e976389d16 259 __regCPACR = cpacr;
mega64 146:03e976389d16 260 __ISB();
mega64 146:03e976389d16 261 }
mega64 146:03e976389d16 262
mega64 146:03e976389d16 263 /** \brief Get CBAR
mega64 146:03e976389d16 264
mega64 146:03e976389d16 265 This function returns the value of the Configuration Base Address register.
mega64 146:03e976389d16 266
mega64 146:03e976389d16 267 \return Configuration Base Address register value
mega64 146:03e976389d16 268 */
mega64 146:03e976389d16 269 __STATIC_INLINE uint32_t __get_CBAR() {
mega64 146:03e976389d16 270 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
mega64 146:03e976389d16 271 return(__regCBAR);
mega64 146:03e976389d16 272 }
mega64 146:03e976389d16 273
mega64 146:03e976389d16 274 /** \brief Get TTBR0
mega64 146:03e976389d16 275
mega64 146:03e976389d16 276 This function returns the value of the Translation Table Base Register 0.
mega64 146:03e976389d16 277
mega64 146:03e976389d16 278 \return Translation Table Base Register 0 value
mega64 146:03e976389d16 279 */
mega64 146:03e976389d16 280 __STATIC_INLINE uint32_t __get_TTBR0() {
mega64 146:03e976389d16 281 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
mega64 146:03e976389d16 282 return(__regTTBR0);
mega64 146:03e976389d16 283 }
mega64 146:03e976389d16 284
mega64 146:03e976389d16 285 /** \brief Set TTBR0
mega64 146:03e976389d16 286
mega64 146:03e976389d16 287 This function assigns the given value to the Translation Table Base Register 0.
mega64 146:03e976389d16 288
mega64 146:03e976389d16 289 \param [in] ttbr0 Translation Table Base Register 0 value to set
mega64 146:03e976389d16 290 */
mega64 146:03e976389d16 291 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
mega64 146:03e976389d16 292 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
mega64 146:03e976389d16 293 __regTTBR0 = ttbr0;
mega64 146:03e976389d16 294 __ISB();
mega64 146:03e976389d16 295 }
mega64 146:03e976389d16 296
mega64 146:03e976389d16 297 /** \brief Get DACR
mega64 146:03e976389d16 298
mega64 146:03e976389d16 299 This function returns the value of the Domain Access Control Register.
mega64 146:03e976389d16 300
mega64 146:03e976389d16 301 \return Domain Access Control Register value
mega64 146:03e976389d16 302 */
mega64 146:03e976389d16 303 __STATIC_INLINE uint32_t __get_DACR() {
mega64 146:03e976389d16 304 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
mega64 146:03e976389d16 305 return(__regDACR);
mega64 146:03e976389d16 306 }
mega64 146:03e976389d16 307
mega64 146:03e976389d16 308 /** \brief Set DACR
mega64 146:03e976389d16 309
mega64 146:03e976389d16 310 This function assigns the given value to the Domain Access Control Register.
mega64 146:03e976389d16 311
mega64 146:03e976389d16 312 \param [in] dacr Domain Access Control Register value to set
mega64 146:03e976389d16 313 */
mega64 146:03e976389d16 314 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
mega64 146:03e976389d16 315 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
mega64 146:03e976389d16 316 __regDACR = dacr;
mega64 146:03e976389d16 317 __ISB();
mega64 146:03e976389d16 318 }
mega64 146:03e976389d16 319
mega64 146:03e976389d16 320 /******************************** Cache and BTAC enable ****************************************************/
mega64 146:03e976389d16 321
mega64 146:03e976389d16 322 /** \brief Set SCTLR
mega64 146:03e976389d16 323
mega64 146:03e976389d16 324 This function assigns the given value to the System Control Register.
mega64 146:03e976389d16 325
mega64 146:03e976389d16 326 \param [in] sctlr System Control Register value to set
mega64 146:03e976389d16 327 */
mega64 146:03e976389d16 328 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
mega64 146:03e976389d16 329 {
mega64 146:03e976389d16 330 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
mega64 146:03e976389d16 331 __regSCTLR = sctlr;
mega64 146:03e976389d16 332 }
mega64 146:03e976389d16 333
mega64 146:03e976389d16 334 /** \brief Get SCTLR
mega64 146:03e976389d16 335
mega64 146:03e976389d16 336 This function returns the value of the System Control Register.
mega64 146:03e976389d16 337
mega64 146:03e976389d16 338 \return System Control Register value
mega64 146:03e976389d16 339 */
mega64 146:03e976389d16 340 __STATIC_INLINE uint32_t __get_SCTLR() {
mega64 146:03e976389d16 341 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
mega64 146:03e976389d16 342 return(__regSCTLR);
mega64 146:03e976389d16 343 }
mega64 146:03e976389d16 344
mega64 146:03e976389d16 345 /** \brief Enable Caches
mega64 146:03e976389d16 346
mega64 146:03e976389d16 347 Enable Caches
mega64 146:03e976389d16 348 */
mega64 146:03e976389d16 349 __STATIC_INLINE void __enable_caches(void) {
mega64 146:03e976389d16 350 // Set I bit 12 to enable I Cache
mega64 146:03e976389d16 351 // Set C bit 2 to enable D Cache
mega64 146:03e976389d16 352 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
mega64 146:03e976389d16 353 }
mega64 146:03e976389d16 354
mega64 146:03e976389d16 355 /** \brief Disable Caches
mega64 146:03e976389d16 356
mega64 146:03e976389d16 357 Disable Caches
mega64 146:03e976389d16 358 */
mega64 146:03e976389d16 359 __STATIC_INLINE void __disable_caches(void) {
mega64 146:03e976389d16 360 // Clear I bit 12 to disable I Cache
mega64 146:03e976389d16 361 // Clear C bit 2 to disable D Cache
mega64 146:03e976389d16 362 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
mega64 146:03e976389d16 363 __ISB();
mega64 146:03e976389d16 364 }
mega64 146:03e976389d16 365
mega64 146:03e976389d16 366 /** \brief Enable BTAC
mega64 146:03e976389d16 367
mega64 146:03e976389d16 368 Enable BTAC
mega64 146:03e976389d16 369 */
mega64 146:03e976389d16 370 __STATIC_INLINE void __enable_btac(void) {
mega64 146:03e976389d16 371 // Set Z bit 11 to enable branch prediction
mega64 146:03e976389d16 372 __set_SCTLR( __get_SCTLR() | (1 << 11));
mega64 146:03e976389d16 373 __ISB();
mega64 146:03e976389d16 374 }
mega64 146:03e976389d16 375
mega64 146:03e976389d16 376 /** \brief Disable BTAC
mega64 146:03e976389d16 377
mega64 146:03e976389d16 378 Disable BTAC
mega64 146:03e976389d16 379 */
mega64 146:03e976389d16 380 __STATIC_INLINE void __disable_btac(void) {
mega64 146:03e976389d16 381 // Clear Z bit 11 to disable branch prediction
mega64 146:03e976389d16 382 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
mega64 146:03e976389d16 383 }
mega64 146:03e976389d16 384
mega64 146:03e976389d16 385
mega64 146:03e976389d16 386 /** \brief Enable MMU
mega64 146:03e976389d16 387
mega64 146:03e976389d16 388 Enable MMU
mega64 146:03e976389d16 389 */
mega64 146:03e976389d16 390 __STATIC_INLINE void __enable_mmu(void) {
mega64 146:03e976389d16 391 // Set M bit 0 to enable the MMU
mega64 146:03e976389d16 392 // Set AFE bit to enable simplified access permissions model
mega64 146:03e976389d16 393 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
mega64 146:03e976389d16 394 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
mega64 146:03e976389d16 395 __ISB();
mega64 146:03e976389d16 396 }
mega64 146:03e976389d16 397
mega64 146:03e976389d16 398 /** \brief Disable MMU
mega64 146:03e976389d16 399
mega64 146:03e976389d16 400 Disable MMU
mega64 146:03e976389d16 401 */
mega64 146:03e976389d16 402 __STATIC_INLINE void __disable_mmu(void) {
mega64 146:03e976389d16 403 // Clear M bit 0 to disable the MMU
mega64 146:03e976389d16 404 __set_SCTLR( __get_SCTLR() & ~1);
mega64 146:03e976389d16 405 __ISB();
mega64 146:03e976389d16 406 }
mega64 146:03e976389d16 407
mega64 146:03e976389d16 408 /******************************** TLB maintenance operations ************************************************/
mega64 146:03e976389d16 409 /** \brief Invalidate the whole tlb
mega64 146:03e976389d16 410
mega64 146:03e976389d16 411 TLBIALL. Invalidate the whole tlb
mega64 146:03e976389d16 412 */
mega64 146:03e976389d16 413
mega64 146:03e976389d16 414 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
mega64 146:03e976389d16 415 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
mega64 146:03e976389d16 416 __TLBIALL = 0;
mega64 146:03e976389d16 417 __DSB();
mega64 146:03e976389d16 418 __ISB();
mega64 146:03e976389d16 419 }
mega64 146:03e976389d16 420
mega64 146:03e976389d16 421 /******************************** BTB maintenance operations ************************************************/
mega64 146:03e976389d16 422 /** \brief Invalidate entire branch predictor array
mega64 146:03e976389d16 423
mega64 146:03e976389d16 424 BPIALL. Branch Predictor Invalidate All.
mega64 146:03e976389d16 425 */
mega64 146:03e976389d16 426
mega64 146:03e976389d16 427 __STATIC_INLINE void __v7_inv_btac(void) {
mega64 146:03e976389d16 428 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
mega64 146:03e976389d16 429 __BPIALL = 0;
mega64 146:03e976389d16 430 __DSB(); //ensure completion of the invalidation
mega64 146:03e976389d16 431 __ISB(); //ensure instruction fetch path sees new state
mega64 146:03e976389d16 432 }
mega64 146:03e976389d16 433
mega64 146:03e976389d16 434
mega64 146:03e976389d16 435 /******************************** L1 cache operations ******************************************************/
mega64 146:03e976389d16 436
mega64 146:03e976389d16 437 /** \brief Invalidate the whole I$
mega64 146:03e976389d16 438
mega64 146:03e976389d16 439 ICIALLU. Instruction Cache Invalidate All to PoU
mega64 146:03e976389d16 440 */
mega64 146:03e976389d16 441 __STATIC_INLINE void __v7_inv_icache_all(void) {
mega64 146:03e976389d16 442 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
mega64 146:03e976389d16 443 __ICIALLU = 0;
mega64 146:03e976389d16 444 __DSB(); //ensure completion of the invalidation
mega64 146:03e976389d16 445 __ISB(); //ensure instruction fetch path sees new I cache state
mega64 146:03e976389d16 446 }
mega64 146:03e976389d16 447
mega64 146:03e976389d16 448 /** \brief Clean D$ by MVA
mega64 146:03e976389d16 449
mega64 146:03e976389d16 450 DCCMVAC. Data cache clean by MVA to PoC
mega64 146:03e976389d16 451 */
mega64 146:03e976389d16 452 __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
mega64 146:03e976389d16 453 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
mega64 146:03e976389d16 454 __DCCMVAC = (uint32_t)va;
mega64 146:03e976389d16 455 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
mega64 146:03e976389d16 456 }
mega64 146:03e976389d16 457
mega64 146:03e976389d16 458 /** \brief Invalidate D$ by MVA
mega64 146:03e976389d16 459
mega64 146:03e976389d16 460 DCIMVAC. Data cache invalidate by MVA to PoC
mega64 146:03e976389d16 461 */
mega64 146:03e976389d16 462 __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
mega64 146:03e976389d16 463 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
mega64 146:03e976389d16 464 __DCIMVAC = (uint32_t)va;
mega64 146:03e976389d16 465 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
mega64 146:03e976389d16 466 }
mega64 146:03e976389d16 467
mega64 146:03e976389d16 468 /** \brief Clean and Invalidate D$ by MVA
mega64 146:03e976389d16 469
mega64 146:03e976389d16 470 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
mega64 146:03e976389d16 471 */
mega64 146:03e976389d16 472 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
mega64 146:03e976389d16 473 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
mega64 146:03e976389d16 474 __DCCIMVAC = (uint32_t)va;
mega64 146:03e976389d16 475 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
mega64 146:03e976389d16 476 }
mega64 146:03e976389d16 477
mega64 146:03e976389d16 478 /** \brief Clean and Invalidate the entire data or unified cache
mega64 146:03e976389d16 479
mega64 146:03e976389d16 480 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
mega64 146:03e976389d16 481 */
mega64 146:03e976389d16 482 #pragma push
mega64 146:03e976389d16 483 #pragma arm
mega64 146:03e976389d16 484 __STATIC_ASM void __v7_all_cache(uint32_t op) {
mega64 146:03e976389d16 485 ARM
mega64 146:03e976389d16 486
mega64 146:03e976389d16 487 PUSH {R4-R11}
mega64 146:03e976389d16 488
mega64 146:03e976389d16 489 MRC p15, 1, R6, c0, c0, 1 // Read CLIDR
mega64 146:03e976389d16 490 ANDS R3, R6, #0x07000000 // Extract coherency level
mega64 146:03e976389d16 491 MOV R3, R3, LSR #23 // Total cache levels << 1
mega64 146:03e976389d16 492 BEQ Finished // If 0, no need to clean
mega64 146:03e976389d16 493
mega64 146:03e976389d16 494 MOV R10, #0 // R10 holds current cache level << 1
mega64 146:03e976389d16 495 Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position
mega64 146:03e976389d16 496 MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level
mega64 146:03e976389d16 497 AND R1, R1, #7 // Isolate those lower 3 bits
mega64 146:03e976389d16 498 CMP R1, #2
mega64 146:03e976389d16 499 BLT Skip // No cache or only instruction cache at this level
mega64 146:03e976389d16 500
mega64 146:03e976389d16 501 MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register
mega64 146:03e976389d16 502 ISB // ISB to sync the change to the CacheSizeID reg
mega64 146:03e976389d16 503 MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register
mega64 146:03e976389d16 504 AND R2, R1, #7 // Extract the line length field
mega64 146:03e976389d16 505 ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes)
mega64 146:03e976389d16 506 LDR R4, =0x3FF
mega64 146:03e976389d16 507 ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
mega64 146:03e976389d16 508 CLZ R5, R4 // R5 is the bit position of the way size increment
mega64 146:03e976389d16 509 LDR R7, =0x7FFF
mega64 146:03e976389d16 510 ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned)
mega64 146:03e976389d16 511
mega64 146:03e976389d16 512 Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned)
mega64 146:03e976389d16 513
mega64 146:03e976389d16 514 Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11
mega64 146:03e976389d16 515 ORR R11, R11, R7, LSL R2 // Factor in the Set number
mega64 146:03e976389d16 516 CMP R0, #0
mega64 146:03e976389d16 517 BNE Dccsw
mega64 146:03e976389d16 518 MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way
mega64 146:03e976389d16 519 B cont
mega64 146:03e976389d16 520 Dccsw CMP R0, #1
mega64 146:03e976389d16 521 BNE Dccisw
mega64 146:03e976389d16 522 MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
mega64 146:03e976389d16 523 B cont
mega64 146:03e976389d16 524 Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW. Clean and Invalidate by Set/Way
mega64 146:03e976389d16 525 cont SUBS R9, R9, #1 // Decrement the Way number
mega64 146:03e976389d16 526 BGE Loop3
mega64 146:03e976389d16 527 SUBS R7, R7, #1 // Decrement the Set number
mega64 146:03e976389d16 528 BGE Loop2
mega64 146:03e976389d16 529 Skip ADD R10, R10, #2 // Increment the cache number
mega64 146:03e976389d16 530 CMP R3, R10
mega64 146:03e976389d16 531 BGT Loop1
mega64 146:03e976389d16 532
mega64 146:03e976389d16 533 Finished
mega64 146:03e976389d16 534 DSB
mega64 146:03e976389d16 535 POP {R4-R11}
mega64 146:03e976389d16 536 BX lr
mega64 146:03e976389d16 537
mega64 146:03e976389d16 538 }
mega64 146:03e976389d16 539 #pragma pop
mega64 146:03e976389d16 540
mega64 146:03e976389d16 541
mega64 146:03e976389d16 542 /** \brief Invalidate the whole D$
mega64 146:03e976389d16 543
mega64 146:03e976389d16 544 DCISW. Invalidate by Set/Way
mega64 146:03e976389d16 545 */
mega64 146:03e976389d16 546
mega64 146:03e976389d16 547 __STATIC_INLINE void __v7_inv_dcache_all(void) {
mega64 146:03e976389d16 548 __v7_all_cache(0);
mega64 146:03e976389d16 549 }
mega64 146:03e976389d16 550
mega64 146:03e976389d16 551 /** \brief Clean the whole D$
mega64 146:03e976389d16 552
mega64 146:03e976389d16 553 DCCSW. Clean by Set/Way
mega64 146:03e976389d16 554 */
mega64 146:03e976389d16 555
mega64 146:03e976389d16 556 __STATIC_INLINE void __v7_clean_dcache_all(void) {
mega64 146:03e976389d16 557 __v7_all_cache(1);
mega64 146:03e976389d16 558 }
mega64 146:03e976389d16 559
mega64 146:03e976389d16 560 /** \brief Clean and invalidate the whole D$
mega64 146:03e976389d16 561
mega64 146:03e976389d16 562 DCCISW. Clean and Invalidate by Set/Way
mega64 146:03e976389d16 563 */
mega64 146:03e976389d16 564
mega64 146:03e976389d16 565 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
mega64 146:03e976389d16 566 __v7_all_cache(2);
mega64 146:03e976389d16 567 }
mega64 146:03e976389d16 568
mega64 146:03e976389d16 569 #include "core_ca_mmu.h"
mega64 146:03e976389d16 570
mega64 146:03e976389d16 571 #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
mega64 146:03e976389d16 572
mega64 146:03e976389d16 573 #define __inline inline
mega64 146:03e976389d16 574
mega64 146:03e976389d16 575 inline static uint32_t __disable_irq_iar() {
mega64 146:03e976389d16 576 int irq_dis = __get_CPSR() & 0x80; // 7bit CPSR.I
mega64 146:03e976389d16 577 __disable_irq();
mega64 146:03e976389d16 578 return irq_dis;
mega64 146:03e976389d16 579 }
mega64 146:03e976389d16 580
mega64 146:03e976389d16 581 #define MODE_USR 0x10
mega64 146:03e976389d16 582 #define MODE_FIQ 0x11
mega64 146:03e976389d16 583 #define MODE_IRQ 0x12
mega64 146:03e976389d16 584 #define MODE_SVC 0x13
mega64 146:03e976389d16 585 #define MODE_MON 0x16
mega64 146:03e976389d16 586 #define MODE_ABT 0x17
mega64 146:03e976389d16 587 #define MODE_HYP 0x1A
mega64 146:03e976389d16 588 #define MODE_UND 0x1B
mega64 146:03e976389d16 589 #define MODE_SYS 0x1F
mega64 146:03e976389d16 590
mega64 146:03e976389d16 591 /** \brief Set Process Stack Pointer
mega64 146:03e976389d16 592
mega64 146:03e976389d16 593 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
mega64 146:03e976389d16 594
mega64 146:03e976389d16 595 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
mega64 146:03e976389d16 596 */
mega64 146:03e976389d16 597 // from rt_CMSIS.c
mega64 146:03e976389d16 598 __arm static inline void __set_PSP(uint32_t topOfProcStack) {
mega64 146:03e976389d16 599 __asm(
mega64 146:03e976389d16 600 " ARM\n"
mega64 146:03e976389d16 601 // " PRESERVE8\n"
mega64 146:03e976389d16 602
mega64 146:03e976389d16 603 " BIC R0, R0, #7 ;ensure stack is 8-byte aligned \n"
mega64 146:03e976389d16 604 " MRS R1, CPSR \n"
mega64 146:03e976389d16 605 " CPS #0x1F ;no effect in USR mode \n" // MODE_SYS
mega64 146:03e976389d16 606 " MOV SP, R0 \n"
mega64 146:03e976389d16 607 " MSR CPSR_c, R1 ;no effect in USR mode \n"
mega64 146:03e976389d16 608 " ISB \n"
mega64 146:03e976389d16 609 " BX LR \n");
mega64 146:03e976389d16 610 }
mega64 146:03e976389d16 611
mega64 146:03e976389d16 612 /** \brief Set User Mode
mega64 146:03e976389d16 613
mega64 146:03e976389d16 614 This function changes the processor state to User Mode
mega64 146:03e976389d16 615 */
mega64 146:03e976389d16 616 // from rt_CMSIS.c
mega64 146:03e976389d16 617 __arm static inline void __set_CPS_USR(void) {
mega64 146:03e976389d16 618 __asm(
mega64 146:03e976389d16 619 " ARM \n"
mega64 146:03e976389d16 620
mega64 146:03e976389d16 621 " CPS #0x10 \n" // MODE_USR
mega64 146:03e976389d16 622 " BX LR\n");
mega64 146:03e976389d16 623 }
mega64 146:03e976389d16 624
mega64 146:03e976389d16 625 /** \brief Set TTBR0
mega64 146:03e976389d16 626
mega64 146:03e976389d16 627 This function assigns the given value to the Translation Table Base Register 0.
mega64 146:03e976389d16 628
mega64 146:03e976389d16 629 \param [in] ttbr0 Translation Table Base Register 0 value to set
mega64 146:03e976389d16 630 */
mega64 146:03e976389d16 631 // from mmu_Renesas_RZ_A1.c
mega64 146:03e976389d16 632 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
mega64 146:03e976389d16 633 __MCR(15, 0, ttbr0, 2, 0, 0); // reg to cp15
mega64 146:03e976389d16 634 __ISB();
mega64 146:03e976389d16 635 }
mega64 146:03e976389d16 636
mega64 146:03e976389d16 637 /** \brief Set DACR
mega64 146:03e976389d16 638
mega64 146:03e976389d16 639 This function assigns the given value to the Domain Access Control Register.
mega64 146:03e976389d16 640
mega64 146:03e976389d16 641 \param [in] dacr Domain Access Control Register value to set
mega64 146:03e976389d16 642 */
mega64 146:03e976389d16 643 // from mmu_Renesas_RZ_A1.c
mega64 146:03e976389d16 644 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
mega64 146:03e976389d16 645 __MCR(15, 0, dacr, 3, 0, 0); // reg to cp15
mega64 146:03e976389d16 646 __ISB();
mega64 146:03e976389d16 647 }
mega64 146:03e976389d16 648
mega64 146:03e976389d16 649
mega64 146:03e976389d16 650 /******************************** Cache and BTAC enable ****************************************************/
mega64 146:03e976389d16 651 /** \brief Set SCTLR
mega64 146:03e976389d16 652
mega64 146:03e976389d16 653 This function assigns the given value to the System Control Register.
mega64 146:03e976389d16 654
mega64 146:03e976389d16 655 \param [in] sctlr System Control Register value to set
mega64 146:03e976389d16 656 */
mega64 146:03e976389d16 657 // from __enable_mmu()
mega64 146:03e976389d16 658 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr) {
mega64 146:03e976389d16 659 __MCR(15, 0, sctlr, 1, 0, 0); // reg to cp15
mega64 146:03e976389d16 660 }
mega64 146:03e976389d16 661
mega64 146:03e976389d16 662 /** \brief Get SCTLR
mega64 146:03e976389d16 663
mega64 146:03e976389d16 664 This function returns the value of the System Control Register.
mega64 146:03e976389d16 665
mega64 146:03e976389d16 666 \return System Control Register value
mega64 146:03e976389d16 667 */
mega64 146:03e976389d16 668 // from __enable_mmu()
mega64 146:03e976389d16 669 __STATIC_INLINE uint32_t __get_SCTLR() {
mega64 146:03e976389d16 670 uint32_t __regSCTLR = __MRC(15, 0, 1, 0, 0);
mega64 146:03e976389d16 671 return __regSCTLR;
mega64 146:03e976389d16 672 }
mega64 146:03e976389d16 673
mega64 146:03e976389d16 674 /** \brief Enable Caches
mega64 146:03e976389d16 675
mega64 146:03e976389d16 676 Enable Caches
mega64 146:03e976389d16 677 */
mega64 146:03e976389d16 678 // from system_Renesas_RZ_A1.c
mega64 146:03e976389d16 679 __STATIC_INLINE void __enable_caches(void) {
mega64 146:03e976389d16 680 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
mega64 146:03e976389d16 681 }
mega64 146:03e976389d16 682
mega64 146:03e976389d16 683 /** \brief Enable BTAC
mega64 146:03e976389d16 684
mega64 146:03e976389d16 685 Enable BTAC
mega64 146:03e976389d16 686 */
mega64 146:03e976389d16 687 // from system_Renesas_RZ_A1.c
mega64 146:03e976389d16 688 __STATIC_INLINE void __enable_btac(void) {
mega64 146:03e976389d16 689 __set_SCTLR( __get_SCTLR() | (1 << 11));
mega64 146:03e976389d16 690 __ISB();
mega64 146:03e976389d16 691 }
mega64 146:03e976389d16 692
mega64 146:03e976389d16 693 /** \brief Enable MMU
mega64 146:03e976389d16 694
mega64 146:03e976389d16 695 Enable MMU
mega64 146:03e976389d16 696 */
mega64 146:03e976389d16 697 // from system_Renesas_RZ_A1.c
mega64 146:03e976389d16 698 __STATIC_INLINE void __enable_mmu(void) {
mega64 146:03e976389d16 699 // Set M bit 0 to enable the MMU
mega64 146:03e976389d16 700 // Set AFE bit to enable simplified access permissions model
mega64 146:03e976389d16 701 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
mega64 146:03e976389d16 702 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
mega64 146:03e976389d16 703 __ISB();
mega64 146:03e976389d16 704 }
mega64 146:03e976389d16 705
mega64 146:03e976389d16 706 /******************************** TLB maintenance operations ************************************************/
mega64 146:03e976389d16 707 /** \brief Invalidate the whole tlb
mega64 146:03e976389d16 708
mega64 146:03e976389d16 709 TLBIALL. Invalidate the whole tlb
mega64 146:03e976389d16 710 */
mega64 146:03e976389d16 711 // from system_Renesas_RZ_A1.c
mega64 146:03e976389d16 712 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
mega64 146:03e976389d16 713 uint32_t val = 0;
mega64 146:03e976389d16 714 __MCR(15, 0, val, 8, 7, 0); // reg to cp15
mega64 146:03e976389d16 715 __MCR(15, 0, val, 8, 6, 0); // reg to cp15
mega64 146:03e976389d16 716 __MCR(15, 0, val, 8, 5, 0); // reg to cp15
mega64 146:03e976389d16 717 __DSB();
mega64 146:03e976389d16 718 __ISB();
mega64 146:03e976389d16 719 }
mega64 146:03e976389d16 720
mega64 146:03e976389d16 721 /******************************** BTB maintenance operations ************************************************/
mega64 146:03e976389d16 722 /** \brief Invalidate entire branch predictor array
mega64 146:03e976389d16 723
mega64 146:03e976389d16 724 BPIALL. Branch Predictor Invalidate All.
mega64 146:03e976389d16 725 */
mega64 146:03e976389d16 726 // from system_Renesas_RZ_A1.c
mega64 146:03e976389d16 727 __STATIC_INLINE void __v7_inv_btac(void) {
mega64 146:03e976389d16 728 uint32_t val = 0;
mega64 146:03e976389d16 729 __MCR(15, 0, val, 7, 5, 6); // reg to cp15
mega64 146:03e976389d16 730 __DSB(); //ensure completion of the invalidation
mega64 146:03e976389d16 731 __ISB(); //ensure instruction fetch path sees new state
mega64 146:03e976389d16 732 }
mega64 146:03e976389d16 733
mega64 146:03e976389d16 734
mega64 146:03e976389d16 735 /******************************** L1 cache operations ******************************************************/
mega64 146:03e976389d16 736
mega64 146:03e976389d16 737 /** \brief Invalidate the whole I$
mega64 146:03e976389d16 738
mega64 146:03e976389d16 739 ICIALLU. Instruction Cache Invalidate All to PoU
mega64 146:03e976389d16 740 */
mega64 146:03e976389d16 741 // from system_Renesas_RZ_A1.c
mega64 146:03e976389d16 742 __STATIC_INLINE void __v7_inv_icache_all(void) {
mega64 146:03e976389d16 743 uint32_t val = 0;
mega64 146:03e976389d16 744 __MCR(15, 0, val, 7, 5, 0); // reg to cp15
mega64 146:03e976389d16 745 __DSB(); //ensure completion of the invalidation
mega64 146:03e976389d16 746 __ISB(); //ensure instruction fetch path sees new I cache state
mega64 146:03e976389d16 747 }
mega64 146:03e976389d16 748
mega64 146:03e976389d16 749 // from __v7_inv_dcache_all()
mega64 146:03e976389d16 750 __arm static inline void __v7_all_cache(uint32_t op) {
mega64 146:03e976389d16 751 __asm(
mega64 146:03e976389d16 752 " ARM \n"
mega64 146:03e976389d16 753
mega64 146:03e976389d16 754 " PUSH {R4-R11} \n"
mega64 146:03e976389d16 755
mega64 146:03e976389d16 756 " MRC p15, 1, R6, c0, c0, 1\n" // Read CLIDR
mega64 146:03e976389d16 757 " ANDS R3, R6, #0x07000000\n" // Extract coherency level
mega64 146:03e976389d16 758 " MOV R3, R3, LSR #23\n" // Total cache levels << 1
mega64 146:03e976389d16 759 " BEQ Finished\n" // If 0, no need to clean
mega64 146:03e976389d16 760
mega64 146:03e976389d16 761 " MOV R10, #0\n" // R10 holds current cache level << 1
mega64 146:03e976389d16 762 "Loop1: ADD R2, R10, R10, LSR #1\n" // R2 holds cache "Set" position
mega64 146:03e976389d16 763 " MOV R1, R6, LSR R2 \n" // Bottom 3 bits are the Cache-type for this level
mega64 146:03e976389d16 764 " AND R1, R1, #7 \n" // Isolate those lower 3 bits
mega64 146:03e976389d16 765 " CMP R1, #2 \n"
mega64 146:03e976389d16 766 " BLT Skip \n" // No cache or only instruction cache at this level
mega64 146:03e976389d16 767
mega64 146:03e976389d16 768 " MCR p15, 2, R10, c0, c0, 0 \n" // Write the Cache Size selection register
mega64 146:03e976389d16 769 " ISB \n" // ISB to sync the change to the CacheSizeID reg
mega64 146:03e976389d16 770 " MRC p15, 1, R1, c0, c0, 0 \n" // Reads current Cache Size ID register
mega64 146:03e976389d16 771 " AND R2, R1, #7 \n" // Extract the line length field
mega64 146:03e976389d16 772 " ADD R2, R2, #4 \n" // Add 4 for the line length offset (log2 16 bytes)
mega64 146:03e976389d16 773 " movw R4, #0x3FF \n"
mega64 146:03e976389d16 774 " ANDS R4, R4, R1, LSR #3 \n" // R4 is the max number on the way size (right aligned)
mega64 146:03e976389d16 775 " CLZ R5, R4 \n" // R5 is the bit position of the way size increment
mega64 146:03e976389d16 776 " movw R7, #0x7FFF \n"
mega64 146:03e976389d16 777 " ANDS R7, R7, R1, LSR #13 \n" // R7 is the max number of the index size (right aligned)
mega64 146:03e976389d16 778
mega64 146:03e976389d16 779 "Loop2: MOV R9, R4 \n" // R9 working copy of the max way size (right aligned)
mega64 146:03e976389d16 780
mega64 146:03e976389d16 781 "Loop3: ORR R11, R10, R9, LSL R5 \n" // Factor in the Way number and cache number into R11
mega64 146:03e976389d16 782 " ORR R11, R11, R7, LSL R2 \n" // Factor in the Set number
mega64 146:03e976389d16 783 " CMP R0, #0 \n"
mega64 146:03e976389d16 784 " BNE Dccsw \n"
mega64 146:03e976389d16 785 " MCR p15, 0, R11, c7, c6, 2 \n" // DCISW. Invalidate by Set/Way
mega64 146:03e976389d16 786 " B cont \n"
mega64 146:03e976389d16 787 "Dccsw: CMP R0, #1 \n"
mega64 146:03e976389d16 788 " BNE Dccisw \n"
mega64 146:03e976389d16 789 " MCR p15, 0, R11, c7, c10, 2 \n" // DCCSW. Clean by Set/Way
mega64 146:03e976389d16 790 " B cont \n"
mega64 146:03e976389d16 791 "Dccisw: MCR p15, 0, R11, c7, c14, 2 \n" // DCCISW, Clean and Invalidate by Set/Way
mega64 146:03e976389d16 792 "cont: SUBS R9, R9, #1 \n" // Decrement the Way number
mega64 146:03e976389d16 793 " BGE Loop3 \n"
mega64 146:03e976389d16 794 " SUBS R7, R7, #1 \n" // Decrement the Set number
mega64 146:03e976389d16 795 " BGE Loop2 \n"
mega64 146:03e976389d16 796 "Skip: ADD R10, R10, #2 \n" // increment the cache number
mega64 146:03e976389d16 797 " CMP R3, R10 \n"
mega64 146:03e976389d16 798 " BGT Loop1 \n"
mega64 146:03e976389d16 799
mega64 146:03e976389d16 800 "Finished: \n"
mega64 146:03e976389d16 801 " DSB \n"
mega64 146:03e976389d16 802 " POP {R4-R11} \n"
mega64 146:03e976389d16 803 " BX lr \n" );
mega64 146:03e976389d16 804 }
mega64 146:03e976389d16 805
mega64 146:03e976389d16 806 /** \brief Invalidate the whole D$
mega64 146:03e976389d16 807
mega64 146:03e976389d16 808 DCISW. Invalidate by Set/Way
mega64 146:03e976389d16 809 */
mega64 146:03e976389d16 810 // from system_Renesas_RZ_A1.c
mega64 146:03e976389d16 811 __STATIC_INLINE void __v7_inv_dcache_all(void) {
mega64 146:03e976389d16 812 __v7_all_cache(0);
mega64 146:03e976389d16 813 }
mega64 146:03e976389d16 814 /** \brief Clean the whole D$
mega64 146:03e976389d16 815
mega64 146:03e976389d16 816 DCCSW. Clean by Set/Way
mega64 146:03e976389d16 817 */
mega64 146:03e976389d16 818
mega64 146:03e976389d16 819 __STATIC_INLINE void __v7_clean_dcache_all(void) {
mega64 146:03e976389d16 820 __v7_all_cache(1);
mega64 146:03e976389d16 821 }
mega64 146:03e976389d16 822
mega64 146:03e976389d16 823 /** \brief Clean and invalidate the whole D$
mega64 146:03e976389d16 824
mega64 146:03e976389d16 825 DCCISW. Clean and Invalidate by Set/Way
mega64 146:03e976389d16 826 */
mega64 146:03e976389d16 827
mega64 146:03e976389d16 828 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
mega64 146:03e976389d16 829 __v7_all_cache(2);
mega64 146:03e976389d16 830 }
mega64 146:03e976389d16 831 /** \brief Clean and Invalidate D$ by MVA
mega64 146:03e976389d16 832
mega64 146:03e976389d16 833 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
mega64 146:03e976389d16 834 */
mega64 146:03e976389d16 835 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
mega64 146:03e976389d16 836 __MCR(15, 0, (uint32_t)va, 7, 14, 1);
mega64 146:03e976389d16 837 __DMB();
mega64 146:03e976389d16 838 }
mega64 146:03e976389d16 839
mega64 146:03e976389d16 840 #include "core_ca_mmu.h"
mega64 146:03e976389d16 841
mega64 146:03e976389d16 842 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
mega64 146:03e976389d16 843 /* GNU gcc specific functions */
mega64 146:03e976389d16 844
mega64 146:03e976389d16 845 #define MODE_USR 0x10
mega64 146:03e976389d16 846 #define MODE_FIQ 0x11
mega64 146:03e976389d16 847 #define MODE_IRQ 0x12
mega64 146:03e976389d16 848 #define MODE_SVC 0x13
mega64 146:03e976389d16 849 #define MODE_MON 0x16
mega64 146:03e976389d16 850 #define MODE_ABT 0x17
mega64 146:03e976389d16 851 #define MODE_HYP 0x1A
mega64 146:03e976389d16 852 #define MODE_UND 0x1B
mega64 146:03e976389d16 853 #define MODE_SYS 0x1F
mega64 146:03e976389d16 854
mega64 146:03e976389d16 855
mega64 146:03e976389d16 856 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
mega64 146:03e976389d16 857 {
mega64 146:03e976389d16 858 __ASM volatile ("cpsie i");
mega64 146:03e976389d16 859 }
mega64 146:03e976389d16 860
mega64 146:03e976389d16 861 /** \brief Disable IRQ Interrupts
mega64 146:03e976389d16 862
mega64 146:03e976389d16 863 This function disables IRQ interrupts by setting the I-bit in the CPSR.
mega64 146:03e976389d16 864 Can only be executed in Privileged modes.
mega64 146:03e976389d16 865 */
mega64 146:03e976389d16 866 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void)
mega64 146:03e976389d16 867 {
mega64 146:03e976389d16 868 uint32_t result;
mega64 146:03e976389d16 869
mega64 146:03e976389d16 870 __ASM volatile ("mrs %0, cpsr" : "=r" (result));
mega64 146:03e976389d16 871 __ASM volatile ("cpsid i");
mega64 146:03e976389d16 872 return(result & 0x80);
mega64 146:03e976389d16 873 }
mega64 146:03e976389d16 874
mega64 146:03e976389d16 875
mega64 146:03e976389d16 876 /** \brief Get APSR Register
mega64 146:03e976389d16 877
mega64 146:03e976389d16 878 This function returns the content of the APSR Register.
mega64 146:03e976389d16 879
mega64 146:03e976389d16 880 \return APSR Register value
mega64 146:03e976389d16 881 */
mega64 146:03e976389d16 882 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
mega64 146:03e976389d16 883 {
mega64 146:03e976389d16 884 #if 1
mega64 146:03e976389d16 885 register uint32_t __regAPSR;
mega64 146:03e976389d16 886 __ASM volatile ("mrs %0, apsr" : "=r" (__regAPSR) );
mega64 146:03e976389d16 887 #else
mega64 146:03e976389d16 888 register uint32_t __regAPSR __ASM("apsr");
mega64 146:03e976389d16 889 #endif
mega64 146:03e976389d16 890 return(__regAPSR);
mega64 146:03e976389d16 891 }
mega64 146:03e976389d16 892
mega64 146:03e976389d16 893
mega64 146:03e976389d16 894 /** \brief Get CPSR Register
mega64 146:03e976389d16 895
mega64 146:03e976389d16 896 This function returns the content of the CPSR Register.
mega64 146:03e976389d16 897
mega64 146:03e976389d16 898 \return CPSR Register value
mega64 146:03e976389d16 899 */
mega64 146:03e976389d16 900 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void)
mega64 146:03e976389d16 901 {
mega64 146:03e976389d16 902 #if 1
mega64 146:03e976389d16 903 register uint32_t __regCPSR;
mega64 146:03e976389d16 904 __ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR));
mega64 146:03e976389d16 905 #else
mega64 146:03e976389d16 906 register uint32_t __regCPSR __ASM("cpsr");
mega64 146:03e976389d16 907 #endif
mega64 146:03e976389d16 908 return(__regCPSR);
mega64 146:03e976389d16 909 }
mega64 146:03e976389d16 910
mega64 146:03e976389d16 911 #if 0
mega64 146:03e976389d16 912 /** \brief Set Stack Pointer
mega64 146:03e976389d16 913
mega64 146:03e976389d16 914 This function assigns the given value to the current stack pointer.
mega64 146:03e976389d16 915
mega64 146:03e976389d16 916 \param [in] topOfStack Stack Pointer value to set
mega64 146:03e976389d16 917 */
mega64 146:03e976389d16 918 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack)
mega64 146:03e976389d16 919 {
mega64 146:03e976389d16 920 register uint32_t __regSP __ASM("sp");
mega64 146:03e976389d16 921 __regSP = topOfStack;
mega64 146:03e976389d16 922 }
mega64 146:03e976389d16 923 #endif
mega64 146:03e976389d16 924
mega64 146:03e976389d16 925 /** \brief Get link register
mega64 146:03e976389d16 926
mega64 146:03e976389d16 927 This function returns the value of the link register
mega64 146:03e976389d16 928
mega64 146:03e976389d16 929 \return Value of link register
mega64 146:03e976389d16 930 */
mega64 146:03e976389d16 931 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void)
mega64 146:03e976389d16 932 {
mega64 146:03e976389d16 933 register uint32_t __reglr __ASM("lr");
mega64 146:03e976389d16 934 return(__reglr);
mega64 146:03e976389d16 935 }
mega64 146:03e976389d16 936
mega64 146:03e976389d16 937 #if 0
mega64 146:03e976389d16 938 /** \brief Set link register
mega64 146:03e976389d16 939
mega64 146:03e976389d16 940 This function sets the value of the link register
mega64 146:03e976389d16 941
mega64 146:03e976389d16 942 \param [in] lr LR value to set
mega64 146:03e976389d16 943 */
mega64 146:03e976389d16 944 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr)
mega64 146:03e976389d16 945 {
mega64 146:03e976389d16 946 register uint32_t __reglr __ASM("lr");
mega64 146:03e976389d16 947 __reglr = lr;
mega64 146:03e976389d16 948 }
mega64 146:03e976389d16 949 #endif
mega64 146:03e976389d16 950
mega64 146:03e976389d16 951 /** \brief Set Process Stack Pointer
mega64 146:03e976389d16 952
mega64 146:03e976389d16 953 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
mega64 146:03e976389d16 954
mega64 146:03e976389d16 955 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
mega64 146:03e976389d16 956 */
mega64 146:03e976389d16 957 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
mega64 146:03e976389d16 958 {
mega64 146:03e976389d16 959 __asm__ volatile (
mega64 146:03e976389d16 960 ".ARM;"
mega64 146:03e976389d16 961 ".eabi_attribute Tag_ABI_align8_preserved,1;"
mega64 146:03e976389d16 962
mega64 146:03e976389d16 963 "BIC R0, R0, #7;" /* ;ensure stack is 8-byte aligned */
mega64 146:03e976389d16 964 "MRS R1, CPSR;"
mega64 146:03e976389d16 965 "CPS %0;" /* ;no effect in USR mode */
mega64 146:03e976389d16 966 "MOV SP, R0;"
mega64 146:03e976389d16 967 "MSR CPSR_c, R1;" /* ;no effect in USR mode */
mega64 146:03e976389d16 968 "ISB;"
mega64 146:03e976389d16 969 //"BX LR;"
mega64 146:03e976389d16 970 :
mega64 146:03e976389d16 971 : "i"(MODE_SYS)
mega64 146:03e976389d16 972 : "r0", "r1");
mega64 146:03e976389d16 973 return;
mega64 146:03e976389d16 974 }
mega64 146:03e976389d16 975
mega64 146:03e976389d16 976 /** \brief Set User Mode
mega64 146:03e976389d16 977
mega64 146:03e976389d16 978 This function changes the processor state to User Mode
mega64 146:03e976389d16 979 */
mega64 146:03e976389d16 980 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPS_USR(void)
mega64 146:03e976389d16 981 {
mega64 146:03e976389d16 982 __asm__ volatile (
mega64 146:03e976389d16 983 ".ARM;"
mega64 146:03e976389d16 984
mega64 146:03e976389d16 985 "CPS %0;"
mega64 146:03e976389d16 986 //"BX LR;"
mega64 146:03e976389d16 987 :
mega64 146:03e976389d16 988 : "i"(MODE_USR)
mega64 146:03e976389d16 989 : );
mega64 146:03e976389d16 990 return;
mega64 146:03e976389d16 991 }
mega64 146:03e976389d16 992
mega64 146:03e976389d16 993
mega64 146:03e976389d16 994 /** \brief Enable FIQ
mega64 146:03e976389d16 995
mega64 146:03e976389d16 996 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
mega64 146:03e976389d16 997 Can only be executed in Privileged modes.
mega64 146:03e976389d16 998 */
mega64 146:03e976389d16 999 #define __enable_fault_irq() __asm__ volatile ("cpsie f")
mega64 146:03e976389d16 1000
mega64 146:03e976389d16 1001
mega64 146:03e976389d16 1002 /** \brief Disable FIQ
mega64 146:03e976389d16 1003
mega64 146:03e976389d16 1004 This function disables FIQ interrupts by setting the F-bit in the CPSR.
mega64 146:03e976389d16 1005 Can only be executed in Privileged modes.
mega64 146:03e976389d16 1006 */
mega64 146:03e976389d16 1007 #define __disable_fault_irq() __asm__ volatile ("cpsid f")
mega64 146:03e976389d16 1008
mega64 146:03e976389d16 1009
mega64 146:03e976389d16 1010 /** \brief Get FPSCR
mega64 146:03e976389d16 1011
mega64 146:03e976389d16 1012 This function returns the current value of the Floating Point Status/Control register.
mega64 146:03e976389d16 1013
mega64 146:03e976389d16 1014 \return Floating Point Status/Control register value
mega64 146:03e976389d16 1015 */
mega64 146:03e976389d16 1016 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
mega64 146:03e976389d16 1017 {
mega64 146:03e976389d16 1018 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
mega64 146:03e976389d16 1019 #if 1
mega64 146:03e976389d16 1020 uint32_t result;
mega64 146:03e976389d16 1021
mega64 146:03e976389d16 1022 __ASM volatile ("vmrs %0, fpscr" : "=r" (result) );
mega64 146:03e976389d16 1023 return (result);
mega64 146:03e976389d16 1024 #else
mega64 146:03e976389d16 1025 register uint32_t __regfpscr __ASM("fpscr");
mega64 146:03e976389d16 1026 return(__regfpscr);
mega64 146:03e976389d16 1027 #endif
mega64 146:03e976389d16 1028 #else
mega64 146:03e976389d16 1029 return(0);
mega64 146:03e976389d16 1030 #endif
mega64 146:03e976389d16 1031 }
mega64 146:03e976389d16 1032
mega64 146:03e976389d16 1033
mega64 146:03e976389d16 1034 /** \brief Set FPSCR
mega64 146:03e976389d16 1035
mega64 146:03e976389d16 1036 This function assigns the given value to the Floating Point Status/Control register.
mega64 146:03e976389d16 1037
mega64 146:03e976389d16 1038 \param [in] fpscr Floating Point Status/Control value to set
mega64 146:03e976389d16 1039 */
mega64 146:03e976389d16 1040 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
mega64 146:03e976389d16 1041 {
mega64 146:03e976389d16 1042 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
mega64 146:03e976389d16 1043 #if 1
mega64 146:03e976389d16 1044 __ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) );
mega64 146:03e976389d16 1045 #else
mega64 146:03e976389d16 1046 register uint32_t __regfpscr __ASM("fpscr");
mega64 146:03e976389d16 1047 __regfpscr = (fpscr);
mega64 146:03e976389d16 1048 #endif
mega64 146:03e976389d16 1049 #endif
mega64 146:03e976389d16 1050 }
mega64 146:03e976389d16 1051
mega64 146:03e976389d16 1052 /** \brief Get FPEXC
mega64 146:03e976389d16 1053
mega64 146:03e976389d16 1054 This function returns the current value of the Floating Point Exception Control register.
mega64 146:03e976389d16 1055
mega64 146:03e976389d16 1056 \return Floating Point Exception Control register value
mega64 146:03e976389d16 1057 */
mega64 146:03e976389d16 1058 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void)
mega64 146:03e976389d16 1059 {
mega64 146:03e976389d16 1060 #if (__FPU_PRESENT == 1)
mega64 146:03e976389d16 1061 #if 1
mega64 146:03e976389d16 1062 uint32_t result;
mega64 146:03e976389d16 1063
mega64 146:03e976389d16 1064 __ASM volatile ("vmrs %0, fpexc" : "=r" (result));
mega64 146:03e976389d16 1065 return (result);
mega64 146:03e976389d16 1066 #else
mega64 146:03e976389d16 1067 register uint32_t __regfpexc __ASM("fpexc");
mega64 146:03e976389d16 1068 return(__regfpexc);
mega64 146:03e976389d16 1069 #endif
mega64 146:03e976389d16 1070 #else
mega64 146:03e976389d16 1071 return(0);
mega64 146:03e976389d16 1072 #endif
mega64 146:03e976389d16 1073 }
mega64 146:03e976389d16 1074
mega64 146:03e976389d16 1075
mega64 146:03e976389d16 1076 /** \brief Set FPEXC
mega64 146:03e976389d16 1077
mega64 146:03e976389d16 1078 This function assigns the given value to the Floating Point Exception Control register.
mega64 146:03e976389d16 1079
mega64 146:03e976389d16 1080 \param [in] fpscr Floating Point Exception Control value to set
mega64 146:03e976389d16 1081 */
mega64 146:03e976389d16 1082 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
mega64 146:03e976389d16 1083 {
mega64 146:03e976389d16 1084 #if (__FPU_PRESENT == 1)
mega64 146:03e976389d16 1085 #if 1
mega64 146:03e976389d16 1086 __ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc));
mega64 146:03e976389d16 1087 #else
mega64 146:03e976389d16 1088 register uint32_t __regfpexc __ASM("fpexc");
mega64 146:03e976389d16 1089 __regfpexc = (fpexc);
mega64 146:03e976389d16 1090 #endif
mega64 146:03e976389d16 1091 #endif
mega64 146:03e976389d16 1092 }
mega64 146:03e976389d16 1093
mega64 146:03e976389d16 1094 /** \brief Get CPACR
mega64 146:03e976389d16 1095
mega64 146:03e976389d16 1096 This function returns the current value of the Coprocessor Access Control register.
mega64 146:03e976389d16 1097
mega64 146:03e976389d16 1098 \return Coprocessor Access Control register value
mega64 146:03e976389d16 1099 */
mega64 146:03e976389d16 1100 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void)
mega64 146:03e976389d16 1101 {
mega64 146:03e976389d16 1102 #if 1
mega64 146:03e976389d16 1103 register uint32_t __regCPACR;
mega64 146:03e976389d16 1104 __ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR));
mega64 146:03e976389d16 1105 #else
mega64 146:03e976389d16 1106 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
mega64 146:03e976389d16 1107 #endif
mega64 146:03e976389d16 1108 return __regCPACR;
mega64 146:03e976389d16 1109 }
mega64 146:03e976389d16 1110
mega64 146:03e976389d16 1111 /** \brief Set CPACR
mega64 146:03e976389d16 1112
mega64 146:03e976389d16 1113 This function assigns the given value to the Coprocessor Access Control register.
mega64 146:03e976389d16 1114
mega64 146:03e976389d16 1115 \param [in] cpacr Coprocessor Acccess Control value to set
mega64 146:03e976389d16 1116 */
mega64 146:03e976389d16 1117 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
mega64 146:03e976389d16 1118 {
mega64 146:03e976389d16 1119 #if 1
mega64 146:03e976389d16 1120 __ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr));
mega64 146:03e976389d16 1121 #else
mega64 146:03e976389d16 1122 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
mega64 146:03e976389d16 1123 __regCPACR = cpacr;
mega64 146:03e976389d16 1124 #endif
mega64 146:03e976389d16 1125 __ISB();
mega64 146:03e976389d16 1126 }
mega64 146:03e976389d16 1127
mega64 146:03e976389d16 1128 /** \brief Get CBAR
mega64 146:03e976389d16 1129
mega64 146:03e976389d16 1130 This function returns the value of the Configuration Base Address register.
mega64 146:03e976389d16 1131
mega64 146:03e976389d16 1132 \return Configuration Base Address register value
mega64 146:03e976389d16 1133 */
mega64 146:03e976389d16 1134 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() {
mega64 146:03e976389d16 1135 #if 1
mega64 146:03e976389d16 1136 register uint32_t __regCBAR;
mega64 146:03e976389d16 1137 __ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR));
mega64 146:03e976389d16 1138 #else
mega64 146:03e976389d16 1139 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
mega64 146:03e976389d16 1140 #endif
mega64 146:03e976389d16 1141 return(__regCBAR);
mega64 146:03e976389d16 1142 }
mega64 146:03e976389d16 1143
mega64 146:03e976389d16 1144 /** \brief Get TTBR0
mega64 146:03e976389d16 1145
mega64 146:03e976389d16 1146 This function returns the value of the Translation Table Base Register 0.
mega64 146:03e976389d16 1147
mega64 146:03e976389d16 1148 \return Translation Table Base Register 0 value
mega64 146:03e976389d16 1149 */
mega64 146:03e976389d16 1150 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() {
mega64 146:03e976389d16 1151 #if 1
mega64 146:03e976389d16 1152 register uint32_t __regTTBR0;
mega64 146:03e976389d16 1153 __ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0));
mega64 146:03e976389d16 1154 #else
mega64 146:03e976389d16 1155 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
mega64 146:03e976389d16 1156 #endif
mega64 146:03e976389d16 1157 return(__regTTBR0);
mega64 146:03e976389d16 1158 }
mega64 146:03e976389d16 1159
mega64 146:03e976389d16 1160 /** \brief Set TTBR0
mega64 146:03e976389d16 1161
mega64 146:03e976389d16 1162 This function assigns the given value to the Translation Table Base Register 0.
mega64 146:03e976389d16 1163
mega64 146:03e976389d16 1164 \param [in] ttbr0 Translation Table Base Register 0 value to set
mega64 146:03e976389d16 1165 */
mega64 146:03e976389d16 1166 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
mega64 146:03e976389d16 1167 #if 1
mega64 146:03e976389d16 1168 __ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0));
mega64 146:03e976389d16 1169 #else
mega64 146:03e976389d16 1170 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
mega64 146:03e976389d16 1171 __regTTBR0 = ttbr0;
mega64 146:03e976389d16 1172 #endif
mega64 146:03e976389d16 1173 __ISB();
mega64 146:03e976389d16 1174 }
mega64 146:03e976389d16 1175
mega64 146:03e976389d16 1176 /** \brief Get DACR
mega64 146:03e976389d16 1177
mega64 146:03e976389d16 1178 This function returns the value of the Domain Access Control Register.
mega64 146:03e976389d16 1179
mega64 146:03e976389d16 1180 \return Domain Access Control Register value
mega64 146:03e976389d16 1181 */
mega64 146:03e976389d16 1182 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() {
mega64 146:03e976389d16 1183 #if 1
mega64 146:03e976389d16 1184 register uint32_t __regDACR;
mega64 146:03e976389d16 1185 __ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR));
mega64 146:03e976389d16 1186 #else
mega64 146:03e976389d16 1187 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
mega64 146:03e976389d16 1188 #endif
mega64 146:03e976389d16 1189 return(__regDACR);
mega64 146:03e976389d16 1190 }
mega64 146:03e976389d16 1191
mega64 146:03e976389d16 1192 /** \brief Set DACR
mega64 146:03e976389d16 1193
mega64 146:03e976389d16 1194 This function assigns the given value to the Domain Access Control Register.
mega64 146:03e976389d16 1195
mega64 146:03e976389d16 1196 \param [in] dacr Domain Access Control Register value to set
mega64 146:03e976389d16 1197 */
mega64 146:03e976389d16 1198 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) {
mega64 146:03e976389d16 1199 #if 1
mega64 146:03e976389d16 1200 __ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr));
mega64 146:03e976389d16 1201 #else
mega64 146:03e976389d16 1202 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
mega64 146:03e976389d16 1203 __regDACR = dacr;
mega64 146:03e976389d16 1204 #endif
mega64 146:03e976389d16 1205 __ISB();
mega64 146:03e976389d16 1206 }
mega64 146:03e976389d16 1207
mega64 146:03e976389d16 1208 /******************************** Cache and BTAC enable ****************************************************/
mega64 146:03e976389d16 1209
mega64 146:03e976389d16 1210 /** \brief Set SCTLR
mega64 146:03e976389d16 1211
mega64 146:03e976389d16 1212 This function assigns the given value to the System Control Register.
mega64 146:03e976389d16 1213
mega64 146:03e976389d16 1214 \param [in] sctlr System Control Register value to set
mega64 146:03e976389d16 1215 */
mega64 146:03e976389d16 1216 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
mega64 146:03e976389d16 1217 {
mega64 146:03e976389d16 1218 #if 1
mega64 146:03e976389d16 1219 __ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr));
mega64 146:03e976389d16 1220 #else
mega64 146:03e976389d16 1221 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
mega64 146:03e976389d16 1222 __regSCTLR = sctlr;
mega64 146:03e976389d16 1223 #endif
mega64 146:03e976389d16 1224 }
mega64 146:03e976389d16 1225
mega64 146:03e976389d16 1226 /** \brief Get SCTLR
mega64 146:03e976389d16 1227
mega64 146:03e976389d16 1228 This function returns the value of the System Control Register.
mega64 146:03e976389d16 1229
mega64 146:03e976389d16 1230 \return System Control Register value
mega64 146:03e976389d16 1231 */
mega64 146:03e976389d16 1232 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() {
mega64 146:03e976389d16 1233 #if 1
mega64 146:03e976389d16 1234 register uint32_t __regSCTLR;
mega64 146:03e976389d16 1235 __ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR));
mega64 146:03e976389d16 1236 #else
mega64 146:03e976389d16 1237 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
mega64 146:03e976389d16 1238 #endif
mega64 146:03e976389d16 1239 return(__regSCTLR);
mega64 146:03e976389d16 1240 }
mega64 146:03e976389d16 1241
mega64 146:03e976389d16 1242 /** \brief Enable Caches
mega64 146:03e976389d16 1243
mega64 146:03e976389d16 1244 Enable Caches
mega64 146:03e976389d16 1245 */
mega64 146:03e976389d16 1246 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) {
mega64 146:03e976389d16 1247 // Set I bit 12 to enable I Cache
mega64 146:03e976389d16 1248 // Set C bit 2 to enable D Cache
mega64 146:03e976389d16 1249 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
mega64 146:03e976389d16 1250 }
mega64 146:03e976389d16 1251
mega64 146:03e976389d16 1252 /** \brief Disable Caches
mega64 146:03e976389d16 1253
mega64 146:03e976389d16 1254 Disable Caches
mega64 146:03e976389d16 1255 */
mega64 146:03e976389d16 1256 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) {
mega64 146:03e976389d16 1257 // Clear I bit 12 to disable I Cache
mega64 146:03e976389d16 1258 // Clear C bit 2 to disable D Cache
mega64 146:03e976389d16 1259 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
mega64 146:03e976389d16 1260 __ISB();
mega64 146:03e976389d16 1261 }
mega64 146:03e976389d16 1262
mega64 146:03e976389d16 1263 /** \brief Enable BTAC
mega64 146:03e976389d16 1264
mega64 146:03e976389d16 1265 Enable BTAC
mega64 146:03e976389d16 1266 */
mega64 146:03e976389d16 1267 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) {
mega64 146:03e976389d16 1268 // Set Z bit 11 to enable branch prediction
mega64 146:03e976389d16 1269 __set_SCTLR( __get_SCTLR() | (1 << 11));
mega64 146:03e976389d16 1270 __ISB();
mega64 146:03e976389d16 1271 }
mega64 146:03e976389d16 1272
mega64 146:03e976389d16 1273 /** \brief Disable BTAC
mega64 146:03e976389d16 1274
mega64 146:03e976389d16 1275 Disable BTAC
mega64 146:03e976389d16 1276 */
mega64 146:03e976389d16 1277 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) {
mega64 146:03e976389d16 1278 // Clear Z bit 11 to disable branch prediction
mega64 146:03e976389d16 1279 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
mega64 146:03e976389d16 1280 }
mega64 146:03e976389d16 1281
mega64 146:03e976389d16 1282
mega64 146:03e976389d16 1283 /** \brief Enable MMU
mega64 146:03e976389d16 1284
mega64 146:03e976389d16 1285 Enable MMU
mega64 146:03e976389d16 1286 */
mega64 146:03e976389d16 1287 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) {
mega64 146:03e976389d16 1288 // Set M bit 0 to enable the MMU
mega64 146:03e976389d16 1289 // Set AFE bit to enable simplified access permissions model
mega64 146:03e976389d16 1290 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
mega64 146:03e976389d16 1291 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
mega64 146:03e976389d16 1292 __ISB();
mega64 146:03e976389d16 1293 }
mega64 146:03e976389d16 1294
mega64 146:03e976389d16 1295 /** \brief Disable MMU
mega64 146:03e976389d16 1296
mega64 146:03e976389d16 1297 Disable MMU
mega64 146:03e976389d16 1298 */
mega64 146:03e976389d16 1299 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) {
mega64 146:03e976389d16 1300 // Clear M bit 0 to disable the MMU
mega64 146:03e976389d16 1301 __set_SCTLR( __get_SCTLR() & ~1);
mega64 146:03e976389d16 1302 __ISB();
mega64 146:03e976389d16 1303 }
mega64 146:03e976389d16 1304
mega64 146:03e976389d16 1305 /******************************** TLB maintenance operations ************************************************/
mega64 146:03e976389d16 1306 /** \brief Invalidate the whole tlb
mega64 146:03e976389d16 1307
mega64 146:03e976389d16 1308 TLBIALL. Invalidate the whole tlb
mega64 146:03e976389d16 1309 */
mega64 146:03e976389d16 1310
mega64 146:03e976389d16 1311 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
mega64 146:03e976389d16 1312 #if 1
mega64 146:03e976389d16 1313 __ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
mega64 146:03e976389d16 1314 #else
mega64 146:03e976389d16 1315 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
mega64 146:03e976389d16 1316 __TLBIALL = 0;
mega64 146:03e976389d16 1317 #endif
mega64 146:03e976389d16 1318 __DSB();
mega64 146:03e976389d16 1319 __ISB();
mega64 146:03e976389d16 1320 }
mega64 146:03e976389d16 1321
mega64 146:03e976389d16 1322 /******************************** BTB maintenance operations ************************************************/
mega64 146:03e976389d16 1323 /** \brief Invalidate entire branch predictor array
mega64 146:03e976389d16 1324
mega64 146:03e976389d16 1325 BPIALL. Branch Predictor Invalidate All.
mega64 146:03e976389d16 1326 */
mega64 146:03e976389d16 1327
mega64 146:03e976389d16 1328 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) {
mega64 146:03e976389d16 1329 #if 1
mega64 146:03e976389d16 1330 __ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
mega64 146:03e976389d16 1331 #else
mega64 146:03e976389d16 1332 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
mega64 146:03e976389d16 1333 __BPIALL = 0;
mega64 146:03e976389d16 1334 #endif
mega64 146:03e976389d16 1335 __DSB(); //ensure completion of the invalidation
mega64 146:03e976389d16 1336 __ISB(); //ensure instruction fetch path sees new state
mega64 146:03e976389d16 1337 }
mega64 146:03e976389d16 1338
mega64 146:03e976389d16 1339
mega64 146:03e976389d16 1340 /******************************** L1 cache operations ******************************************************/
mega64 146:03e976389d16 1341
mega64 146:03e976389d16 1342 /** \brief Invalidate the whole I$
mega64 146:03e976389d16 1343
mega64 146:03e976389d16 1344 ICIALLU. Instruction Cache Invalidate All to PoU
mega64 146:03e976389d16 1345 */
mega64 146:03e976389d16 1346 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) {
mega64 146:03e976389d16 1347 #if 1
mega64 146:03e976389d16 1348 __ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
mega64 146:03e976389d16 1349 #else
mega64 146:03e976389d16 1350 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
mega64 146:03e976389d16 1351 __ICIALLU = 0;
mega64 146:03e976389d16 1352 #endif
mega64 146:03e976389d16 1353 __DSB(); //ensure completion of the invalidation
mega64 146:03e976389d16 1354 __ISB(); //ensure instruction fetch path sees new I cache state
mega64 146:03e976389d16 1355 }
mega64 146:03e976389d16 1356
mega64 146:03e976389d16 1357 /** \brief Clean D$ by MVA
mega64 146:03e976389d16 1358
mega64 146:03e976389d16 1359 DCCMVAC. Data cache clean by MVA to PoC
mega64 146:03e976389d16 1360 */
mega64 146:03e976389d16 1361 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
mega64 146:03e976389d16 1362 #if 1
mega64 146:03e976389d16 1363 __ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va));
mega64 146:03e976389d16 1364 #else
mega64 146:03e976389d16 1365 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
mega64 146:03e976389d16 1366 __DCCMVAC = (uint32_t)va;
mega64 146:03e976389d16 1367 #endif
mega64 146:03e976389d16 1368 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
mega64 146:03e976389d16 1369 }
mega64 146:03e976389d16 1370
mega64 146:03e976389d16 1371 /** \brief Invalidate D$ by MVA
mega64 146:03e976389d16 1372
mega64 146:03e976389d16 1373 DCIMVAC. Data cache invalidate by MVA to PoC
mega64 146:03e976389d16 1374 */
mega64 146:03e976389d16 1375 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
mega64 146:03e976389d16 1376 #if 1
mega64 146:03e976389d16 1377 __ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va));
mega64 146:03e976389d16 1378 #else
mega64 146:03e976389d16 1379 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
mega64 146:03e976389d16 1380 __DCIMVAC = (uint32_t)va;
mega64 146:03e976389d16 1381 #endif
mega64 146:03e976389d16 1382 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
mega64 146:03e976389d16 1383 }
mega64 146:03e976389d16 1384
mega64 146:03e976389d16 1385 /** \brief Clean and Invalidate D$ by MVA
mega64 146:03e976389d16 1386
mega64 146:03e976389d16 1387 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
mega64 146:03e976389d16 1388 */
mega64 146:03e976389d16 1389 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
mega64 146:03e976389d16 1390 #if 1
mega64 146:03e976389d16 1391 __ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va));
mega64 146:03e976389d16 1392 #else
mega64 146:03e976389d16 1393 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
mega64 146:03e976389d16 1394 __DCCIMVAC = (uint32_t)va;
mega64 146:03e976389d16 1395 #endif
mega64 146:03e976389d16 1396 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
mega64 146:03e976389d16 1397 }
mega64 146:03e976389d16 1398
mega64 146:03e976389d16 1399 /** \brief Clean and Invalidate the entire data or unified cache
mega64 146:03e976389d16 1400
mega64 146:03e976389d16 1401 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
mega64 146:03e976389d16 1402 */
mega64 146:03e976389d16 1403 extern void __v7_all_cache(uint32_t op);
mega64 146:03e976389d16 1404
mega64 146:03e976389d16 1405
mega64 146:03e976389d16 1406 /** \brief Invalidate the whole D$
mega64 146:03e976389d16 1407
mega64 146:03e976389d16 1408 DCISW. Invalidate by Set/Way
mega64 146:03e976389d16 1409 */
mega64 146:03e976389d16 1410
mega64 146:03e976389d16 1411 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) {
mega64 146:03e976389d16 1412 __v7_all_cache(0);
mega64 146:03e976389d16 1413 }
mega64 146:03e976389d16 1414
mega64 146:03e976389d16 1415 /** \brief Clean the whole D$
mega64 146:03e976389d16 1416
mega64 146:03e976389d16 1417 DCCSW. Clean by Set/Way
mega64 146:03e976389d16 1418 */
mega64 146:03e976389d16 1419
mega64 146:03e976389d16 1420 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) {
mega64 146:03e976389d16 1421 __v7_all_cache(1);
mega64 146:03e976389d16 1422 }
mega64 146:03e976389d16 1423
mega64 146:03e976389d16 1424 /** \brief Clean and invalidate the whole D$
mega64 146:03e976389d16 1425
mega64 146:03e976389d16 1426 DCCISW. Clean and Invalidate by Set/Way
mega64 146:03e976389d16 1427 */
mega64 146:03e976389d16 1428
mega64 146:03e976389d16 1429 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
mega64 146:03e976389d16 1430 __v7_all_cache(2);
mega64 146:03e976389d16 1431 }
mega64 146:03e976389d16 1432
mega64 146:03e976389d16 1433 #include "core_ca_mmu.h"
mega64 146:03e976389d16 1434
mega64 146:03e976389d16 1435 #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
mega64 146:03e976389d16 1436
mega64 146:03e976389d16 1437 #error TASKING Compiler support not implemented for Cortex-A
mega64 146:03e976389d16 1438
mega64 146:03e976389d16 1439 #endif
mega64 146:03e976389d16 1440
mega64 146:03e976389d16 1441 /*@} end of CMSIS_Core_RegAccFunctions */
mega64 146:03e976389d16 1442
mega64 146:03e976389d16 1443
mega64 146:03e976389d16 1444 #endif /* __CORE_CAFUNC_H__ */