Micah B / mbed

mbed

Dependents:   DHTSensor_Test K64F_eCompass_OneNET_JW

TARGET_ARCH_GPRS/core_cm0plus.h@0:2cc6bb4d7fea, 2015-02-25 (annotated)

Committer:
mbotkinl
Date:
Wed Feb 25 20:22:22 2015 +0000
Revision:
0:2cc6bb4d7fea
Working code to read Temperature and Humidity readings

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbotkinl 0:2cc6bb4d7fea 1 /**************************************************************************//**
mbotkinl 0:2cc6bb4d7fea 2 * @file core_cm0plus.h
mbotkinl 0:2cc6bb4d7fea 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
mbotkinl 0:2cc6bb4d7fea 4 * @version V3.20
mbotkinl 0:2cc6bb4d7fea 5 * @date 25. February 2013
mbotkinl 0:2cc6bb4d7fea 6 *
mbotkinl 0:2cc6bb4d7fea 7 * @note
mbotkinl 0:2cc6bb4d7fea 8 *
mbotkinl 0:2cc6bb4d7fea 9 ******************************************************************************/
mbotkinl 0:2cc6bb4d7fea 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
mbotkinl 0:2cc6bb4d7fea 11
mbotkinl 0:2cc6bb4d7fea 12 All rights reserved.
mbotkinl 0:2cc6bb4d7fea 13 Redistribution and use in source and binary forms, with or without
mbotkinl 0:2cc6bb4d7fea 14 modification, are permitted provided that the following conditions are met:
mbotkinl 0:2cc6bb4d7fea 15 - Redistributions of source code must retain the above copyright
mbotkinl 0:2cc6bb4d7fea 16 notice, this list of conditions and the following disclaimer.
mbotkinl 0:2cc6bb4d7fea 17 - Redistributions in binary form must reproduce the above copyright
mbotkinl 0:2cc6bb4d7fea 18 notice, this list of conditions and the following disclaimer in the
mbotkinl 0:2cc6bb4d7fea 19 documentation and/or other materials provided with the distribution.
mbotkinl 0:2cc6bb4d7fea 20 - Neither the name of ARM nor the names of its contributors may be used
mbotkinl 0:2cc6bb4d7fea 21 to endorse or promote products derived from this software without
mbotkinl 0:2cc6bb4d7fea 22 specific prior written permission.
mbotkinl 0:2cc6bb4d7fea 23 *
mbotkinl 0:2cc6bb4d7fea 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbotkinl 0:2cc6bb4d7fea 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbotkinl 0:2cc6bb4d7fea 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
mbotkinl 0:2cc6bb4d7fea 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
mbotkinl 0:2cc6bb4d7fea 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
mbotkinl 0:2cc6bb4d7fea 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
mbotkinl 0:2cc6bb4d7fea 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mbotkinl 0:2cc6bb4d7fea 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mbotkinl 0:2cc6bb4d7fea 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
mbotkinl 0:2cc6bb4d7fea 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mbotkinl 0:2cc6bb4d7fea 34 POSSIBILITY OF SUCH DAMAGE.
mbotkinl 0:2cc6bb4d7fea 35 ---------------------------------------------------------------------------*/
mbotkinl 0:2cc6bb4d7fea 36
mbotkinl 0:2cc6bb4d7fea 37
mbotkinl 0:2cc6bb4d7fea 38 #if defined ( __ICCARM__ )
mbotkinl 0:2cc6bb4d7fea 39 #pragma system_include /* treat file as system include file for MISRA check */
mbotkinl 0:2cc6bb4d7fea 40 #endif
mbotkinl 0:2cc6bb4d7fea 41
mbotkinl 0:2cc6bb4d7fea 42 #ifdef __cplusplus
mbotkinl 0:2cc6bb4d7fea 43 extern "C" {
mbotkinl 0:2cc6bb4d7fea 44 #endif
mbotkinl 0:2cc6bb4d7fea 45
mbotkinl 0:2cc6bb4d7fea 46 #ifndef __CORE_CM0PLUS_H_GENERIC
mbotkinl 0:2cc6bb4d7fea 47 #define __CORE_CM0PLUS_H_GENERIC
mbotkinl 0:2cc6bb4d7fea 48
mbotkinl 0:2cc6bb4d7fea 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
mbotkinl 0:2cc6bb4d7fea 50 CMSIS violates the following MISRA-C:2004 rules:
mbotkinl 0:2cc6bb4d7fea 51
mbotkinl 0:2cc6bb4d7fea 52 \li Required Rule 8.5, object/function definition in header file.<br>
mbotkinl 0:2cc6bb4d7fea 53 Function definitions in header files are used to allow 'inlining'.
mbotkinl 0:2cc6bb4d7fea 54
mbotkinl 0:2cc6bb4d7fea 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
mbotkinl 0:2cc6bb4d7fea 56 Unions are used for effective representation of core registers.
mbotkinl 0:2cc6bb4d7fea 57
mbotkinl 0:2cc6bb4d7fea 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
mbotkinl 0:2cc6bb4d7fea 59 Function-like macros are used to allow more efficient code.
mbotkinl 0:2cc6bb4d7fea 60 */
mbotkinl 0:2cc6bb4d7fea 61
mbotkinl 0:2cc6bb4d7fea 62
mbotkinl 0:2cc6bb4d7fea 63 /*******************************************************************************
mbotkinl 0:2cc6bb4d7fea 64 * CMSIS definitions
mbotkinl 0:2cc6bb4d7fea 65 ******************************************************************************/
mbotkinl 0:2cc6bb4d7fea 66 /** \ingroup Cortex-M0+
mbotkinl 0:2cc6bb4d7fea 67 @{
mbotkinl 0:2cc6bb4d7fea 68 */
mbotkinl 0:2cc6bb4d7fea 69
mbotkinl 0:2cc6bb4d7fea 70 /* CMSIS CM0P definitions */
mbotkinl 0:2cc6bb4d7fea 71 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
mbotkinl 0:2cc6bb4d7fea 72 #define __CM0PLUS_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
mbotkinl 0:2cc6bb4d7fea 73 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
mbotkinl 0:2cc6bb4d7fea 74 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
mbotkinl 0:2cc6bb4d7fea 75
mbotkinl 0:2cc6bb4d7fea 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
mbotkinl 0:2cc6bb4d7fea 77
mbotkinl 0:2cc6bb4d7fea 78
mbotkinl 0:2cc6bb4d7fea 79 #if defined ( __CC_ARM )
mbotkinl 0:2cc6bb4d7fea 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
mbotkinl 0:2cc6bb4d7fea 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
mbotkinl 0:2cc6bb4d7fea 82 #define __STATIC_INLINE static __inline
mbotkinl 0:2cc6bb4d7fea 83
mbotkinl 0:2cc6bb4d7fea 84 #elif defined ( __ICCARM__ )
mbotkinl 0:2cc6bb4d7fea 85 #define __ASM __asm /*!< asm keyword for IAR Compiler */
mbotkinl 0:2cc6bb4d7fea 86 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
mbotkinl 0:2cc6bb4d7fea 87 #define __STATIC_INLINE static inline
mbotkinl 0:2cc6bb4d7fea 88
mbotkinl 0:2cc6bb4d7fea 89 #elif defined ( __GNUC__ )
mbotkinl 0:2cc6bb4d7fea 90 #define __ASM __asm /*!< asm keyword for GNU Compiler */
mbotkinl 0:2cc6bb4d7fea 91 #define __INLINE inline /*!< inline keyword for GNU Compiler */
mbotkinl 0:2cc6bb4d7fea 92 #define __STATIC_INLINE static inline
mbotkinl 0:2cc6bb4d7fea 93
mbotkinl 0:2cc6bb4d7fea 94 #elif defined ( __TASKING__ )
mbotkinl 0:2cc6bb4d7fea 95 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
mbotkinl 0:2cc6bb4d7fea 96 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
mbotkinl 0:2cc6bb4d7fea 97 #define __STATIC_INLINE static inline
mbotkinl 0:2cc6bb4d7fea 98
mbotkinl 0:2cc6bb4d7fea 99 #endif
mbotkinl 0:2cc6bb4d7fea 100
mbotkinl 0:2cc6bb4d7fea 101 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
mbotkinl 0:2cc6bb4d7fea 102 */
mbotkinl 0:2cc6bb4d7fea 103 #define __FPU_USED 0
mbotkinl 0:2cc6bb4d7fea 104
mbotkinl 0:2cc6bb4d7fea 105 #if defined ( __CC_ARM )
mbotkinl 0:2cc6bb4d7fea 106 #if defined __TARGET_FPU_VFP
mbotkinl 0:2cc6bb4d7fea 107 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbotkinl 0:2cc6bb4d7fea 108 #endif
mbotkinl 0:2cc6bb4d7fea 109
mbotkinl 0:2cc6bb4d7fea 110 #elif defined ( __ICCARM__ )
mbotkinl 0:2cc6bb4d7fea 111 #if defined __ARMVFP__
mbotkinl 0:2cc6bb4d7fea 112 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbotkinl 0:2cc6bb4d7fea 113 #endif
mbotkinl 0:2cc6bb4d7fea 114
mbotkinl 0:2cc6bb4d7fea 115 #elif defined ( __GNUC__ )
mbotkinl 0:2cc6bb4d7fea 116 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
mbotkinl 0:2cc6bb4d7fea 117 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbotkinl 0:2cc6bb4d7fea 118 #endif
mbotkinl 0:2cc6bb4d7fea 119
mbotkinl 0:2cc6bb4d7fea 120 #elif defined ( __TASKING__ )
mbotkinl 0:2cc6bb4d7fea 121 #if defined __FPU_VFP__
mbotkinl 0:2cc6bb4d7fea 122 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbotkinl 0:2cc6bb4d7fea 123 #endif
mbotkinl 0:2cc6bb4d7fea 124 #endif
mbotkinl 0:2cc6bb4d7fea 125
mbotkinl 0:2cc6bb4d7fea 126 #include <stdint.h> /* standard types definitions */
mbotkinl 0:2cc6bb4d7fea 127 #include <core_cmInstr.h> /* Core Instruction Access */
mbotkinl 0:2cc6bb4d7fea 128 #include <core_cmFunc.h> /* Core Function Access */
mbotkinl 0:2cc6bb4d7fea 129
mbotkinl 0:2cc6bb4d7fea 130 #endif /* __CORE_CM0PLUS_H_GENERIC */
mbotkinl 0:2cc6bb4d7fea 131
mbotkinl 0:2cc6bb4d7fea 132 #ifndef __CMSIS_GENERIC
mbotkinl 0:2cc6bb4d7fea 133
mbotkinl 0:2cc6bb4d7fea 134 #ifndef __CORE_CM0PLUS_H_DEPENDANT
mbotkinl 0:2cc6bb4d7fea 135 #define __CORE_CM0PLUS_H_DEPENDANT
mbotkinl 0:2cc6bb4d7fea 136
mbotkinl 0:2cc6bb4d7fea 137 /* check device defines and use defaults */
mbotkinl 0:2cc6bb4d7fea 138 #if defined __CHECK_DEVICE_DEFINES
mbotkinl 0:2cc6bb4d7fea 139 #ifndef __CM0PLUS_REV
mbotkinl 0:2cc6bb4d7fea 140 #define __CM0PLUS_REV 0x0000
mbotkinl 0:2cc6bb4d7fea 141 #warning "__CM0PLUS_REV not defined in device header file; using default!"
mbotkinl 0:2cc6bb4d7fea 142 #endif
mbotkinl 0:2cc6bb4d7fea 143
mbotkinl 0:2cc6bb4d7fea 144 #ifndef __MPU_PRESENT
mbotkinl 0:2cc6bb4d7fea 145 #define __MPU_PRESENT 0
mbotkinl 0:2cc6bb4d7fea 146 #warning "__MPU_PRESENT not defined in device header file; using default!"
mbotkinl 0:2cc6bb4d7fea 147 #endif
mbotkinl 0:2cc6bb4d7fea 148
mbotkinl 0:2cc6bb4d7fea 149 #ifndef __VTOR_PRESENT
mbotkinl 0:2cc6bb4d7fea 150 #define __VTOR_PRESENT 0
mbotkinl 0:2cc6bb4d7fea 151 #warning "__VTOR_PRESENT not defined in device header file; using default!"
mbotkinl 0:2cc6bb4d7fea 152 #endif
mbotkinl 0:2cc6bb4d7fea 153
mbotkinl 0:2cc6bb4d7fea 154 #ifndef __NVIC_PRIO_BITS
mbotkinl 0:2cc6bb4d7fea 155 #define __NVIC_PRIO_BITS 2
mbotkinl 0:2cc6bb4d7fea 156 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
mbotkinl 0:2cc6bb4d7fea 157 #endif
mbotkinl 0:2cc6bb4d7fea 158
mbotkinl 0:2cc6bb4d7fea 159 #ifndef __Vendor_SysTickConfig
mbotkinl 0:2cc6bb4d7fea 160 #define __Vendor_SysTickConfig 0
mbotkinl 0:2cc6bb4d7fea 161 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
mbotkinl 0:2cc6bb4d7fea 162 #endif
mbotkinl 0:2cc6bb4d7fea 163 #endif
mbotkinl 0:2cc6bb4d7fea 164
mbotkinl 0:2cc6bb4d7fea 165 /* IO definitions (access restrictions to peripheral registers) */
mbotkinl 0:2cc6bb4d7fea 166 /**
mbotkinl 0:2cc6bb4d7fea 167 \defgroup CMSIS_glob_defs CMSIS Global Defines
mbotkinl 0:2cc6bb4d7fea 168
mbotkinl 0:2cc6bb4d7fea 169 <strong>IO Type Qualifiers</strong> are used
mbotkinl 0:2cc6bb4d7fea 170 \li to specify the access to peripheral variables.
mbotkinl 0:2cc6bb4d7fea 171 \li for automatic generation of peripheral register debug information.
mbotkinl 0:2cc6bb4d7fea 172 */
mbotkinl 0:2cc6bb4d7fea 173 #ifdef __cplusplus
mbotkinl 0:2cc6bb4d7fea 174 #define __I volatile /*!< Defines 'read only' permissions */
mbotkinl 0:2cc6bb4d7fea 175 #else
mbotkinl 0:2cc6bb4d7fea 176 #define __I volatile const /*!< Defines 'read only' permissions */
mbotkinl 0:2cc6bb4d7fea 177 #endif
mbotkinl 0:2cc6bb4d7fea 178 #define __O volatile /*!< Defines 'write only' permissions */
mbotkinl 0:2cc6bb4d7fea 179 #define __IO volatile /*!< Defines 'read / write' permissions */
mbotkinl 0:2cc6bb4d7fea 180
mbotkinl 0:2cc6bb4d7fea 181 /*@} end of group Cortex-M0+ */
mbotkinl 0:2cc6bb4d7fea 182
mbotkinl 0:2cc6bb4d7fea 183
mbotkinl 0:2cc6bb4d7fea 184
mbotkinl 0:2cc6bb4d7fea 185 /*******************************************************************************
mbotkinl 0:2cc6bb4d7fea 186 * Register Abstraction
mbotkinl 0:2cc6bb4d7fea 187 Core Register contain:
mbotkinl 0:2cc6bb4d7fea 188 - Core Register
mbotkinl 0:2cc6bb4d7fea 189 - Core NVIC Register
mbotkinl 0:2cc6bb4d7fea 190 - Core SCB Register
mbotkinl 0:2cc6bb4d7fea 191 - Core SysTick Register
mbotkinl 0:2cc6bb4d7fea 192 - Core MPU Register
mbotkinl 0:2cc6bb4d7fea 193 ******************************************************************************/
mbotkinl 0:2cc6bb4d7fea 194 /** \defgroup CMSIS_core_register Defines and Type Definitions
mbotkinl 0:2cc6bb4d7fea 195 \brief Type definitions and defines for Cortex-M processor based devices.
mbotkinl 0:2cc6bb4d7fea 196 */
mbotkinl 0:2cc6bb4d7fea 197
mbotkinl 0:2cc6bb4d7fea 198 /** \ingroup CMSIS_core_register
mbotkinl 0:2cc6bb4d7fea 199 \defgroup CMSIS_CORE Status and Control Registers
mbotkinl 0:2cc6bb4d7fea 200 \brief Core Register type definitions.
mbotkinl 0:2cc6bb4d7fea 201 @{
mbotkinl 0:2cc6bb4d7fea 202 */
mbotkinl 0:2cc6bb4d7fea 203
mbotkinl 0:2cc6bb4d7fea 204 /** \brief Union type to access the Application Program Status Register (APSR).
mbotkinl 0:2cc6bb4d7fea 205 */
mbotkinl 0:2cc6bb4d7fea 206 typedef union
mbotkinl 0:2cc6bb4d7fea 207 {
mbotkinl 0:2cc6bb4d7fea 208 struct
mbotkinl 0:2cc6bb4d7fea 209 {
mbotkinl 0:2cc6bb4d7fea 210 #if (__CORTEX_M != 0x04)
mbotkinl 0:2cc6bb4d7fea 211 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
mbotkinl 0:2cc6bb4d7fea 212 #else
mbotkinl 0:2cc6bb4d7fea 213 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
mbotkinl 0:2cc6bb4d7fea 214 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
mbotkinl 0:2cc6bb4d7fea 215 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
mbotkinl 0:2cc6bb4d7fea 216 #endif
mbotkinl 0:2cc6bb4d7fea 217 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
mbotkinl 0:2cc6bb4d7fea 218 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
mbotkinl 0:2cc6bb4d7fea 219 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
mbotkinl 0:2cc6bb4d7fea 220 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
mbotkinl 0:2cc6bb4d7fea 221 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
mbotkinl 0:2cc6bb4d7fea 222 } b; /*!< Structure used for bit access */
mbotkinl 0:2cc6bb4d7fea 223 uint32_t w; /*!< Type used for word access */
mbotkinl 0:2cc6bb4d7fea 224 } APSR_Type;
mbotkinl 0:2cc6bb4d7fea 225
mbotkinl 0:2cc6bb4d7fea 226
mbotkinl 0:2cc6bb4d7fea 227 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
mbotkinl 0:2cc6bb4d7fea 228 */
mbotkinl 0:2cc6bb4d7fea 229 typedef union
mbotkinl 0:2cc6bb4d7fea 230 {
mbotkinl 0:2cc6bb4d7fea 231 struct
mbotkinl 0:2cc6bb4d7fea 232 {
mbotkinl 0:2cc6bb4d7fea 233 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
mbotkinl 0:2cc6bb4d7fea 234 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
mbotkinl 0:2cc6bb4d7fea 235 } b; /*!< Structure used for bit access */
mbotkinl 0:2cc6bb4d7fea 236 uint32_t w; /*!< Type used for word access */
mbotkinl 0:2cc6bb4d7fea 237 } IPSR_Type;
mbotkinl 0:2cc6bb4d7fea 238
mbotkinl 0:2cc6bb4d7fea 239
mbotkinl 0:2cc6bb4d7fea 240 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
mbotkinl 0:2cc6bb4d7fea 241 */
mbotkinl 0:2cc6bb4d7fea 242 typedef union
mbotkinl 0:2cc6bb4d7fea 243 {
mbotkinl 0:2cc6bb4d7fea 244 struct
mbotkinl 0:2cc6bb4d7fea 245 {
mbotkinl 0:2cc6bb4d7fea 246 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
mbotkinl 0:2cc6bb4d7fea 247 #if (__CORTEX_M != 0x04)
mbotkinl 0:2cc6bb4d7fea 248 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
mbotkinl 0:2cc6bb4d7fea 249 #else
mbotkinl 0:2cc6bb4d7fea 250 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
mbotkinl 0:2cc6bb4d7fea 251 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
mbotkinl 0:2cc6bb4d7fea 252 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
mbotkinl 0:2cc6bb4d7fea 253 #endif
mbotkinl 0:2cc6bb4d7fea 254 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
mbotkinl 0:2cc6bb4d7fea 255 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
mbotkinl 0:2cc6bb4d7fea 256 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
mbotkinl 0:2cc6bb4d7fea 257 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
mbotkinl 0:2cc6bb4d7fea 258 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
mbotkinl 0:2cc6bb4d7fea 259 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
mbotkinl 0:2cc6bb4d7fea 260 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
mbotkinl 0:2cc6bb4d7fea 261 } b; /*!< Structure used for bit access */
mbotkinl 0:2cc6bb4d7fea 262 uint32_t w; /*!< Type used for word access */
mbotkinl 0:2cc6bb4d7fea 263 } xPSR_Type;
mbotkinl 0:2cc6bb4d7fea 264
mbotkinl 0:2cc6bb4d7fea 265
mbotkinl 0:2cc6bb4d7fea 266 /** \brief Union type to access the Control Registers (CONTROL).
mbotkinl 0:2cc6bb4d7fea 267 */
mbotkinl 0:2cc6bb4d7fea 268 typedef union
mbotkinl 0:2cc6bb4d7fea 269 {
mbotkinl 0:2cc6bb4d7fea 270 struct
mbotkinl 0:2cc6bb4d7fea 271 {
mbotkinl 0:2cc6bb4d7fea 272 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
mbotkinl 0:2cc6bb4d7fea 273 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
mbotkinl 0:2cc6bb4d7fea 274 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
mbotkinl 0:2cc6bb4d7fea 275 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
mbotkinl 0:2cc6bb4d7fea 276 } b; /*!< Structure used for bit access */
mbotkinl 0:2cc6bb4d7fea 277 uint32_t w; /*!< Type used for word access */
mbotkinl 0:2cc6bb4d7fea 278 } CONTROL_Type;
mbotkinl 0:2cc6bb4d7fea 279
mbotkinl 0:2cc6bb4d7fea 280 /*@} end of group CMSIS_CORE */
mbotkinl 0:2cc6bb4d7fea 281
mbotkinl 0:2cc6bb4d7fea 282
mbotkinl 0:2cc6bb4d7fea 283 /** \ingroup CMSIS_core_register
mbotkinl 0:2cc6bb4d7fea 284 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
mbotkinl 0:2cc6bb4d7fea 285 \brief Type definitions for the NVIC Registers
mbotkinl 0:2cc6bb4d7fea 286 @{
mbotkinl 0:2cc6bb4d7fea 287 */
mbotkinl 0:2cc6bb4d7fea 288
mbotkinl 0:2cc6bb4d7fea 289 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
mbotkinl 0:2cc6bb4d7fea 290 */
mbotkinl 0:2cc6bb4d7fea 291 typedef struct
mbotkinl 0:2cc6bb4d7fea 292 {
mbotkinl 0:2cc6bb4d7fea 293 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
mbotkinl 0:2cc6bb4d7fea 294 uint32_t RESERVED0[31];
mbotkinl 0:2cc6bb4d7fea 295 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
mbotkinl 0:2cc6bb4d7fea 296 uint32_t RSERVED1[31];
mbotkinl 0:2cc6bb4d7fea 297 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
mbotkinl 0:2cc6bb4d7fea 298 uint32_t RESERVED2[31];
mbotkinl 0:2cc6bb4d7fea 299 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
mbotkinl 0:2cc6bb4d7fea 300 uint32_t RESERVED3[31];
mbotkinl 0:2cc6bb4d7fea 301 uint32_t RESERVED4[64];
mbotkinl 0:2cc6bb4d7fea 302 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
mbotkinl 0:2cc6bb4d7fea 303 } NVIC_Type;
mbotkinl 0:2cc6bb4d7fea 304
mbotkinl 0:2cc6bb4d7fea 305 /*@} end of group CMSIS_NVIC */
mbotkinl 0:2cc6bb4d7fea 306
mbotkinl 0:2cc6bb4d7fea 307
mbotkinl 0:2cc6bb4d7fea 308 /** \ingroup CMSIS_core_register
mbotkinl 0:2cc6bb4d7fea 309 \defgroup CMSIS_SCB System Control Block (SCB)
mbotkinl 0:2cc6bb4d7fea 310 \brief Type definitions for the System Control Block Registers
mbotkinl 0:2cc6bb4d7fea 311 @{
mbotkinl 0:2cc6bb4d7fea 312 */
mbotkinl 0:2cc6bb4d7fea 313
mbotkinl 0:2cc6bb4d7fea 314 /** \brief Structure type to access the System Control Block (SCB).
mbotkinl 0:2cc6bb4d7fea 315 */
mbotkinl 0:2cc6bb4d7fea 316 typedef struct
mbotkinl 0:2cc6bb4d7fea 317 {
mbotkinl 0:2cc6bb4d7fea 318 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
mbotkinl 0:2cc6bb4d7fea 319 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
mbotkinl 0:2cc6bb4d7fea 320 #if (__VTOR_PRESENT == 1)
mbotkinl 0:2cc6bb4d7fea 321 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
mbotkinl 0:2cc6bb4d7fea 322 #else
mbotkinl 0:2cc6bb4d7fea 323 uint32_t RESERVED0;
mbotkinl 0:2cc6bb4d7fea 324 #endif
mbotkinl 0:2cc6bb4d7fea 325 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
mbotkinl 0:2cc6bb4d7fea 326 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
mbotkinl 0:2cc6bb4d7fea 327 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
mbotkinl 0:2cc6bb4d7fea 328 uint32_t RESERVED1;
mbotkinl 0:2cc6bb4d7fea 329 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
mbotkinl 0:2cc6bb4d7fea 330 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
mbotkinl 0:2cc6bb4d7fea 331 } SCB_Type;
mbotkinl 0:2cc6bb4d7fea 332
mbotkinl 0:2cc6bb4d7fea 333 /* SCB CPUID Register Definitions */
mbotkinl 0:2cc6bb4d7fea 334 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
mbotkinl 0:2cc6bb4d7fea 335 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
mbotkinl 0:2cc6bb4d7fea 336
mbotkinl 0:2cc6bb4d7fea 337 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
mbotkinl 0:2cc6bb4d7fea 338 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
mbotkinl 0:2cc6bb4d7fea 339
mbotkinl 0:2cc6bb4d7fea 340 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
mbotkinl 0:2cc6bb4d7fea 341 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
mbotkinl 0:2cc6bb4d7fea 342
mbotkinl 0:2cc6bb4d7fea 343 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
mbotkinl 0:2cc6bb4d7fea 344 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
mbotkinl 0:2cc6bb4d7fea 345
mbotkinl 0:2cc6bb4d7fea 346 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
mbotkinl 0:2cc6bb4d7fea 347 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
mbotkinl 0:2cc6bb4d7fea 348
mbotkinl 0:2cc6bb4d7fea 349 /* SCB Interrupt Control State Register Definitions */
mbotkinl 0:2cc6bb4d7fea 350 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
mbotkinl 0:2cc6bb4d7fea 351 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
mbotkinl 0:2cc6bb4d7fea 352
mbotkinl 0:2cc6bb4d7fea 353 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
mbotkinl 0:2cc6bb4d7fea 354 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
mbotkinl 0:2cc6bb4d7fea 355
mbotkinl 0:2cc6bb4d7fea 356 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
mbotkinl 0:2cc6bb4d7fea 357 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
mbotkinl 0:2cc6bb4d7fea 358
mbotkinl 0:2cc6bb4d7fea 359 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
mbotkinl 0:2cc6bb4d7fea 360 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
mbotkinl 0:2cc6bb4d7fea 361
mbotkinl 0:2cc6bb4d7fea 362 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
mbotkinl 0:2cc6bb4d7fea 363 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
mbotkinl 0:2cc6bb4d7fea 364
mbotkinl 0:2cc6bb4d7fea 365 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
mbotkinl 0:2cc6bb4d7fea 366 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
mbotkinl 0:2cc6bb4d7fea 367
mbotkinl 0:2cc6bb4d7fea 368 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
mbotkinl 0:2cc6bb4d7fea 369 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
mbotkinl 0:2cc6bb4d7fea 370
mbotkinl 0:2cc6bb4d7fea 371 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
mbotkinl 0:2cc6bb4d7fea 372 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
mbotkinl 0:2cc6bb4d7fea 373
mbotkinl 0:2cc6bb4d7fea 374 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
mbotkinl 0:2cc6bb4d7fea 375 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
mbotkinl 0:2cc6bb4d7fea 376
mbotkinl 0:2cc6bb4d7fea 377 #if (__VTOR_PRESENT == 1)
mbotkinl 0:2cc6bb4d7fea 378 /* SCB Interrupt Control State Register Definitions */
mbotkinl 0:2cc6bb4d7fea 379 #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
mbotkinl 0:2cc6bb4d7fea 380 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
mbotkinl 0:2cc6bb4d7fea 381 #endif
mbotkinl 0:2cc6bb4d7fea 382
mbotkinl 0:2cc6bb4d7fea 383 /* SCB Application Interrupt and Reset Control Register Definitions */
mbotkinl 0:2cc6bb4d7fea 384 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
mbotkinl 0:2cc6bb4d7fea 385 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
mbotkinl 0:2cc6bb4d7fea 386
mbotkinl 0:2cc6bb4d7fea 387 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
mbotkinl 0:2cc6bb4d7fea 388 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
mbotkinl 0:2cc6bb4d7fea 389
mbotkinl 0:2cc6bb4d7fea 390 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
mbotkinl 0:2cc6bb4d7fea 391 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
mbotkinl 0:2cc6bb4d7fea 392
mbotkinl 0:2cc6bb4d7fea 393 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
mbotkinl 0:2cc6bb4d7fea 394 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
mbotkinl 0:2cc6bb4d7fea 395
mbotkinl 0:2cc6bb4d7fea 396 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
mbotkinl 0:2cc6bb4d7fea 397 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
mbotkinl 0:2cc6bb4d7fea 398
mbotkinl 0:2cc6bb4d7fea 399 /* SCB System Control Register Definitions */
mbotkinl 0:2cc6bb4d7fea 400 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
mbotkinl 0:2cc6bb4d7fea 401 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
mbotkinl 0:2cc6bb4d7fea 402
mbotkinl 0:2cc6bb4d7fea 403 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
mbotkinl 0:2cc6bb4d7fea 404 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
mbotkinl 0:2cc6bb4d7fea 405
mbotkinl 0:2cc6bb4d7fea 406 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
mbotkinl 0:2cc6bb4d7fea 407 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
mbotkinl 0:2cc6bb4d7fea 408
mbotkinl 0:2cc6bb4d7fea 409 /* SCB Configuration Control Register Definitions */
mbotkinl 0:2cc6bb4d7fea 410 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
mbotkinl 0:2cc6bb4d7fea 411 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
mbotkinl 0:2cc6bb4d7fea 412
mbotkinl 0:2cc6bb4d7fea 413 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
mbotkinl 0:2cc6bb4d7fea 414 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
mbotkinl 0:2cc6bb4d7fea 415
mbotkinl 0:2cc6bb4d7fea 416 /* SCB System Handler Control and State Register Definitions */
mbotkinl 0:2cc6bb4d7fea 417 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
mbotkinl 0:2cc6bb4d7fea 418 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
mbotkinl 0:2cc6bb4d7fea 419
mbotkinl 0:2cc6bb4d7fea 420 /*@} end of group CMSIS_SCB */
mbotkinl 0:2cc6bb4d7fea 421
mbotkinl 0:2cc6bb4d7fea 422
mbotkinl 0:2cc6bb4d7fea 423 /** \ingroup CMSIS_core_register
mbotkinl 0:2cc6bb4d7fea 424 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
mbotkinl 0:2cc6bb4d7fea 425 \brief Type definitions for the System Timer Registers.
mbotkinl 0:2cc6bb4d7fea 426 @{
mbotkinl 0:2cc6bb4d7fea 427 */
mbotkinl 0:2cc6bb4d7fea 428
mbotkinl 0:2cc6bb4d7fea 429 /** \brief Structure type to access the System Timer (SysTick).
mbotkinl 0:2cc6bb4d7fea 430 */
mbotkinl 0:2cc6bb4d7fea 431 typedef struct
mbotkinl 0:2cc6bb4d7fea 432 {
mbotkinl 0:2cc6bb4d7fea 433 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
mbotkinl 0:2cc6bb4d7fea 434 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
mbotkinl 0:2cc6bb4d7fea 435 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
mbotkinl 0:2cc6bb4d7fea 436 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
mbotkinl 0:2cc6bb4d7fea 437 } SysTick_Type;
mbotkinl 0:2cc6bb4d7fea 438
mbotkinl 0:2cc6bb4d7fea 439 /* SysTick Control / Status Register Definitions */
mbotkinl 0:2cc6bb4d7fea 440 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
mbotkinl 0:2cc6bb4d7fea 441 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
mbotkinl 0:2cc6bb4d7fea 442
mbotkinl 0:2cc6bb4d7fea 443 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
mbotkinl 0:2cc6bb4d7fea 444 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
mbotkinl 0:2cc6bb4d7fea 445
mbotkinl 0:2cc6bb4d7fea 446 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
mbotkinl 0:2cc6bb4d7fea 447 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
mbotkinl 0:2cc6bb4d7fea 448
mbotkinl 0:2cc6bb4d7fea 449 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
mbotkinl 0:2cc6bb4d7fea 450 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
mbotkinl 0:2cc6bb4d7fea 451
mbotkinl 0:2cc6bb4d7fea 452 /* SysTick Reload Register Definitions */
mbotkinl 0:2cc6bb4d7fea 453 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
mbotkinl 0:2cc6bb4d7fea 454 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
mbotkinl 0:2cc6bb4d7fea 455
mbotkinl 0:2cc6bb4d7fea 456 /* SysTick Current Register Definitions */
mbotkinl 0:2cc6bb4d7fea 457 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
mbotkinl 0:2cc6bb4d7fea 458 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
mbotkinl 0:2cc6bb4d7fea 459
mbotkinl 0:2cc6bb4d7fea 460 /* SysTick Calibration Register Definitions */
mbotkinl 0:2cc6bb4d7fea 461 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
mbotkinl 0:2cc6bb4d7fea 462 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
mbotkinl 0:2cc6bb4d7fea 463
mbotkinl 0:2cc6bb4d7fea 464 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
mbotkinl 0:2cc6bb4d7fea 465 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
mbotkinl 0:2cc6bb4d7fea 466
mbotkinl 0:2cc6bb4d7fea 467 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
mbotkinl 0:2cc6bb4d7fea 468 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
mbotkinl 0:2cc6bb4d7fea 469
mbotkinl 0:2cc6bb4d7fea 470 /*@} end of group CMSIS_SysTick */
mbotkinl 0:2cc6bb4d7fea 471
mbotkinl 0:2cc6bb4d7fea 472 #if (__MPU_PRESENT == 1)
mbotkinl 0:2cc6bb4d7fea 473 /** \ingroup CMSIS_core_register
mbotkinl 0:2cc6bb4d7fea 474 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
mbotkinl 0:2cc6bb4d7fea 475 \brief Type definitions for the Memory Protection Unit (MPU)
mbotkinl 0:2cc6bb4d7fea 476 @{
mbotkinl 0:2cc6bb4d7fea 477 */
mbotkinl 0:2cc6bb4d7fea 478
mbotkinl 0:2cc6bb4d7fea 479 /** \brief Structure type to access the Memory Protection Unit (MPU).
mbotkinl 0:2cc6bb4d7fea 480 */
mbotkinl 0:2cc6bb4d7fea 481 typedef struct
mbotkinl 0:2cc6bb4d7fea 482 {
mbotkinl 0:2cc6bb4d7fea 483 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
mbotkinl 0:2cc6bb4d7fea 484 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
mbotkinl 0:2cc6bb4d7fea 485 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
mbotkinl 0:2cc6bb4d7fea 486 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
mbotkinl 0:2cc6bb4d7fea 487 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
mbotkinl 0:2cc6bb4d7fea 488 } MPU_Type;
mbotkinl 0:2cc6bb4d7fea 489
mbotkinl 0:2cc6bb4d7fea 490 /* MPU Type Register */
mbotkinl 0:2cc6bb4d7fea 491 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
mbotkinl 0:2cc6bb4d7fea 492 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
mbotkinl 0:2cc6bb4d7fea 493
mbotkinl 0:2cc6bb4d7fea 494 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
mbotkinl 0:2cc6bb4d7fea 495 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
mbotkinl 0:2cc6bb4d7fea 496
mbotkinl 0:2cc6bb4d7fea 497 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
mbotkinl 0:2cc6bb4d7fea 498 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
mbotkinl 0:2cc6bb4d7fea 499
mbotkinl 0:2cc6bb4d7fea 500 /* MPU Control Register */
mbotkinl 0:2cc6bb4d7fea 501 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
mbotkinl 0:2cc6bb4d7fea 502 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
mbotkinl 0:2cc6bb4d7fea 503
mbotkinl 0:2cc6bb4d7fea 504 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
mbotkinl 0:2cc6bb4d7fea 505 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
mbotkinl 0:2cc6bb4d7fea 506
mbotkinl 0:2cc6bb4d7fea 507 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
mbotkinl 0:2cc6bb4d7fea 508 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
mbotkinl 0:2cc6bb4d7fea 509
mbotkinl 0:2cc6bb4d7fea 510 /* MPU Region Number Register */
mbotkinl 0:2cc6bb4d7fea 511 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
mbotkinl 0:2cc6bb4d7fea 512 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
mbotkinl 0:2cc6bb4d7fea 513
mbotkinl 0:2cc6bb4d7fea 514 /* MPU Region Base Address Register */
mbotkinl 0:2cc6bb4d7fea 515 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
mbotkinl 0:2cc6bb4d7fea 516 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
mbotkinl 0:2cc6bb4d7fea 517
mbotkinl 0:2cc6bb4d7fea 518 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
mbotkinl 0:2cc6bb4d7fea 519 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
mbotkinl 0:2cc6bb4d7fea 520
mbotkinl 0:2cc6bb4d7fea 521 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
mbotkinl 0:2cc6bb4d7fea 522 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
mbotkinl 0:2cc6bb4d7fea 523
mbotkinl 0:2cc6bb4d7fea 524 /* MPU Region Attribute and Size Register */
mbotkinl 0:2cc6bb4d7fea 525 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
mbotkinl 0:2cc6bb4d7fea 526 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
mbotkinl 0:2cc6bb4d7fea 527
mbotkinl 0:2cc6bb4d7fea 528 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
mbotkinl 0:2cc6bb4d7fea 529 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
mbotkinl 0:2cc6bb4d7fea 530
mbotkinl 0:2cc6bb4d7fea 531 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
mbotkinl 0:2cc6bb4d7fea 532 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
mbotkinl 0:2cc6bb4d7fea 533
mbotkinl 0:2cc6bb4d7fea 534 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
mbotkinl 0:2cc6bb4d7fea 535 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
mbotkinl 0:2cc6bb4d7fea 536
mbotkinl 0:2cc6bb4d7fea 537 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
mbotkinl 0:2cc6bb4d7fea 538 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
mbotkinl 0:2cc6bb4d7fea 539
mbotkinl 0:2cc6bb4d7fea 540 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
mbotkinl 0:2cc6bb4d7fea 541 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
mbotkinl 0:2cc6bb4d7fea 542
mbotkinl 0:2cc6bb4d7fea 543 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
mbotkinl 0:2cc6bb4d7fea 544 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
mbotkinl 0:2cc6bb4d7fea 545
mbotkinl 0:2cc6bb4d7fea 546 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
mbotkinl 0:2cc6bb4d7fea 547 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
mbotkinl 0:2cc6bb4d7fea 548
mbotkinl 0:2cc6bb4d7fea 549 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
mbotkinl 0:2cc6bb4d7fea 550 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
mbotkinl 0:2cc6bb4d7fea 551
mbotkinl 0:2cc6bb4d7fea 552 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
mbotkinl 0:2cc6bb4d7fea 553 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
mbotkinl 0:2cc6bb4d7fea 554
mbotkinl 0:2cc6bb4d7fea 555 /*@} end of group CMSIS_MPU */
mbotkinl 0:2cc6bb4d7fea 556 #endif
mbotkinl 0:2cc6bb4d7fea 557
mbotkinl 0:2cc6bb4d7fea 558
mbotkinl 0:2cc6bb4d7fea 559 /** \ingroup CMSIS_core_register
mbotkinl 0:2cc6bb4d7fea 560 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
mbotkinl 0:2cc6bb4d7fea 561 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
mbotkinl 0:2cc6bb4d7fea 562 are only accessible over DAP and not via processor. Therefore
mbotkinl 0:2cc6bb4d7fea 563 they are not covered by the Cortex-M0 header file.
mbotkinl 0:2cc6bb4d7fea 564 @{
mbotkinl 0:2cc6bb4d7fea 565 */
mbotkinl 0:2cc6bb4d7fea 566 /*@} end of group CMSIS_CoreDebug */
mbotkinl 0:2cc6bb4d7fea 567
mbotkinl 0:2cc6bb4d7fea 568
mbotkinl 0:2cc6bb4d7fea 569 /** \ingroup CMSIS_core_register
mbotkinl 0:2cc6bb4d7fea 570 \defgroup CMSIS_core_base Core Definitions
mbotkinl 0:2cc6bb4d7fea 571 \brief Definitions for base addresses, unions, and structures.
mbotkinl 0:2cc6bb4d7fea 572 @{
mbotkinl 0:2cc6bb4d7fea 573 */
mbotkinl 0:2cc6bb4d7fea 574
mbotkinl 0:2cc6bb4d7fea 575 /* Memory mapping of Cortex-M0+ Hardware */
mbotkinl 0:2cc6bb4d7fea 576 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
mbotkinl 0:2cc6bb4d7fea 577 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
mbotkinl 0:2cc6bb4d7fea 578 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
mbotkinl 0:2cc6bb4d7fea 579 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
mbotkinl 0:2cc6bb4d7fea 580
mbotkinl 0:2cc6bb4d7fea 581 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
mbotkinl 0:2cc6bb4d7fea 582 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
mbotkinl 0:2cc6bb4d7fea 583 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
mbotkinl 0:2cc6bb4d7fea 584
mbotkinl 0:2cc6bb4d7fea 585 #if (__MPU_PRESENT == 1)
mbotkinl 0:2cc6bb4d7fea 586 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
mbotkinl 0:2cc6bb4d7fea 587 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
mbotkinl 0:2cc6bb4d7fea 588 #endif
mbotkinl 0:2cc6bb4d7fea 589
mbotkinl 0:2cc6bb4d7fea 590 /*@} */
mbotkinl 0:2cc6bb4d7fea 591
mbotkinl 0:2cc6bb4d7fea 592
mbotkinl 0:2cc6bb4d7fea 593
mbotkinl 0:2cc6bb4d7fea 594 /*******************************************************************************
mbotkinl 0:2cc6bb4d7fea 595 * Hardware Abstraction Layer
mbotkinl 0:2cc6bb4d7fea 596 Core Function Interface contains:
mbotkinl 0:2cc6bb4d7fea 597 - Core NVIC Functions
mbotkinl 0:2cc6bb4d7fea 598 - Core SysTick Functions
mbotkinl 0:2cc6bb4d7fea 599 - Core Register Access Functions
mbotkinl 0:2cc6bb4d7fea 600 ******************************************************************************/
mbotkinl 0:2cc6bb4d7fea 601 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
mbotkinl 0:2cc6bb4d7fea 602 */
mbotkinl 0:2cc6bb4d7fea 603
mbotkinl 0:2cc6bb4d7fea 604
mbotkinl 0:2cc6bb4d7fea 605
mbotkinl 0:2cc6bb4d7fea 606 /* ########################## NVIC functions #################################### */
mbotkinl 0:2cc6bb4d7fea 607 /** \ingroup CMSIS_Core_FunctionInterface
mbotkinl 0:2cc6bb4d7fea 608 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
mbotkinl 0:2cc6bb4d7fea 609 \brief Functions that manage interrupts and exceptions via the NVIC.
mbotkinl 0:2cc6bb4d7fea 610 @{
mbotkinl 0:2cc6bb4d7fea 611 */
mbotkinl 0:2cc6bb4d7fea 612
mbotkinl 0:2cc6bb4d7fea 613 /* Interrupt Priorities are WORD accessible only under ARMv6M */
mbotkinl 0:2cc6bb4d7fea 614 /* The following MACROS handle generation of the register offset and byte masks */
mbotkinl 0:2cc6bb4d7fea 615 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
mbotkinl 0:2cc6bb4d7fea 616 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
mbotkinl 0:2cc6bb4d7fea 617 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
mbotkinl 0:2cc6bb4d7fea 618
mbotkinl 0:2cc6bb4d7fea 619
mbotkinl 0:2cc6bb4d7fea 620 /** \brief Enable External Interrupt
mbotkinl 0:2cc6bb4d7fea 621
mbotkinl 0:2cc6bb4d7fea 622 The function enables a device-specific interrupt in the NVIC interrupt controller.
mbotkinl 0:2cc6bb4d7fea 623
mbotkinl 0:2cc6bb4d7fea 624 \param [in] IRQn External interrupt number. Value cannot be negative.
mbotkinl 0:2cc6bb4d7fea 625 */
mbotkinl 0:2cc6bb4d7fea 626 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
mbotkinl 0:2cc6bb4d7fea 627 {
mbotkinl 0:2cc6bb4d7fea 628 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
mbotkinl 0:2cc6bb4d7fea 629 }
mbotkinl 0:2cc6bb4d7fea 630
mbotkinl 0:2cc6bb4d7fea 631
mbotkinl 0:2cc6bb4d7fea 632 /** \brief Disable External Interrupt
mbotkinl 0:2cc6bb4d7fea 633
mbotkinl 0:2cc6bb4d7fea 634 The function disables a device-specific interrupt in the NVIC interrupt controller.
mbotkinl 0:2cc6bb4d7fea 635
mbotkinl 0:2cc6bb4d7fea 636 \param [in] IRQn External interrupt number. Value cannot be negative.
mbotkinl 0:2cc6bb4d7fea 637 */
mbotkinl 0:2cc6bb4d7fea 638 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
mbotkinl 0:2cc6bb4d7fea 639 {
mbotkinl 0:2cc6bb4d7fea 640 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
mbotkinl 0:2cc6bb4d7fea 641 }
mbotkinl 0:2cc6bb4d7fea 642
mbotkinl 0:2cc6bb4d7fea 643
mbotkinl 0:2cc6bb4d7fea 644 /** \brief Get Pending Interrupt
mbotkinl 0:2cc6bb4d7fea 645
mbotkinl 0:2cc6bb4d7fea 646 The function reads the pending register in the NVIC and returns the pending bit
mbotkinl 0:2cc6bb4d7fea 647 for the specified interrupt.
mbotkinl 0:2cc6bb4d7fea 648
mbotkinl 0:2cc6bb4d7fea 649 \param [in] IRQn Interrupt number.
mbotkinl 0:2cc6bb4d7fea 650
mbotkinl 0:2cc6bb4d7fea 651 \return 0 Interrupt status is not pending.
mbotkinl 0:2cc6bb4d7fea 652 \return 1 Interrupt status is pending.
mbotkinl 0:2cc6bb4d7fea 653 */
mbotkinl 0:2cc6bb4d7fea 654 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
mbotkinl 0:2cc6bb4d7fea 655 {
mbotkinl 0:2cc6bb4d7fea 656 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
mbotkinl 0:2cc6bb4d7fea 657 }
mbotkinl 0:2cc6bb4d7fea 658
mbotkinl 0:2cc6bb4d7fea 659
mbotkinl 0:2cc6bb4d7fea 660 /** \brief Set Pending Interrupt
mbotkinl 0:2cc6bb4d7fea 661
mbotkinl 0:2cc6bb4d7fea 662 The function sets the pending bit of an external interrupt.
mbotkinl 0:2cc6bb4d7fea 663
mbotkinl 0:2cc6bb4d7fea 664 \param [in] IRQn Interrupt number. Value cannot be negative.
mbotkinl 0:2cc6bb4d7fea 665 */
mbotkinl 0:2cc6bb4d7fea 666 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
mbotkinl 0:2cc6bb4d7fea 667 {
mbotkinl 0:2cc6bb4d7fea 668 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
mbotkinl 0:2cc6bb4d7fea 669 }
mbotkinl 0:2cc6bb4d7fea 670
mbotkinl 0:2cc6bb4d7fea 671
mbotkinl 0:2cc6bb4d7fea 672 /** \brief Clear Pending Interrupt
mbotkinl 0:2cc6bb4d7fea 673
mbotkinl 0:2cc6bb4d7fea 674 The function clears the pending bit of an external interrupt.
mbotkinl 0:2cc6bb4d7fea 675
mbotkinl 0:2cc6bb4d7fea 676 \param [in] IRQn External interrupt number. Value cannot be negative.
mbotkinl 0:2cc6bb4d7fea 677 */
mbotkinl 0:2cc6bb4d7fea 678 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
mbotkinl 0:2cc6bb4d7fea 679 {
mbotkinl 0:2cc6bb4d7fea 680 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
mbotkinl 0:2cc6bb4d7fea 681 }
mbotkinl 0:2cc6bb4d7fea 682
mbotkinl 0:2cc6bb4d7fea 683
mbotkinl 0:2cc6bb4d7fea 684 /** \brief Set Interrupt Priority
mbotkinl 0:2cc6bb4d7fea 685
mbotkinl 0:2cc6bb4d7fea 686 The function sets the priority of an interrupt.
mbotkinl 0:2cc6bb4d7fea 687
mbotkinl 0:2cc6bb4d7fea 688 \note The priority cannot be set for every core interrupt.
mbotkinl 0:2cc6bb4d7fea 689
mbotkinl 0:2cc6bb4d7fea 690 \param [in] IRQn Interrupt number.
mbotkinl 0:2cc6bb4d7fea 691 \param [in] priority Priority to set.
mbotkinl 0:2cc6bb4d7fea 692 */
mbotkinl 0:2cc6bb4d7fea 693 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
mbotkinl 0:2cc6bb4d7fea 694 {
mbotkinl 0:2cc6bb4d7fea 695 if(IRQn < 0) {
mbotkinl 0:2cc6bb4d7fea 696 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
mbotkinl 0:2cc6bb4d7fea 697 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
mbotkinl 0:2cc6bb4d7fea 698 else {
mbotkinl 0:2cc6bb4d7fea 699 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
mbotkinl 0:2cc6bb4d7fea 700 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
mbotkinl 0:2cc6bb4d7fea 701 }
mbotkinl 0:2cc6bb4d7fea 702
mbotkinl 0:2cc6bb4d7fea 703
mbotkinl 0:2cc6bb4d7fea 704 /** \brief Get Interrupt Priority
mbotkinl 0:2cc6bb4d7fea 705
mbotkinl 0:2cc6bb4d7fea 706 The function reads the priority of an interrupt. The interrupt
mbotkinl 0:2cc6bb4d7fea 707 number can be positive to specify an external (device specific)
mbotkinl 0:2cc6bb4d7fea 708 interrupt, or negative to specify an internal (core) interrupt.
mbotkinl 0:2cc6bb4d7fea 709
mbotkinl 0:2cc6bb4d7fea 710
mbotkinl 0:2cc6bb4d7fea 711 \param [in] IRQn Interrupt number.
mbotkinl 0:2cc6bb4d7fea 712 \return Interrupt Priority. Value is aligned automatically to the implemented
mbotkinl 0:2cc6bb4d7fea 713 priority bits of the microcontroller.
mbotkinl 0:2cc6bb4d7fea 714 */
mbotkinl 0:2cc6bb4d7fea 715 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
mbotkinl 0:2cc6bb4d7fea 716 {
mbotkinl 0:2cc6bb4d7fea 717
mbotkinl 0:2cc6bb4d7fea 718 if(IRQn < 0) {
mbotkinl 0:2cc6bb4d7fea 719 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
mbotkinl 0:2cc6bb4d7fea 720 else {
mbotkinl 0:2cc6bb4d7fea 721 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
mbotkinl 0:2cc6bb4d7fea 722 }
mbotkinl 0:2cc6bb4d7fea 723
mbotkinl 0:2cc6bb4d7fea 724
mbotkinl 0:2cc6bb4d7fea 725 /** \brief System Reset
mbotkinl 0:2cc6bb4d7fea 726
mbotkinl 0:2cc6bb4d7fea 727 The function initiates a system reset request to reset the MCU.
mbotkinl 0:2cc6bb4d7fea 728 */
mbotkinl 0:2cc6bb4d7fea 729 __STATIC_INLINE void NVIC_SystemReset(void)
mbotkinl 0:2cc6bb4d7fea 730 {
mbotkinl 0:2cc6bb4d7fea 731 __DSB(); /* Ensure all outstanding memory accesses included
mbotkinl 0:2cc6bb4d7fea 732 buffered write are completed before reset */
mbotkinl 0:2cc6bb4d7fea 733 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
mbotkinl 0:2cc6bb4d7fea 734 SCB_AIRCR_SYSRESETREQ_Msk);
mbotkinl 0:2cc6bb4d7fea 735 __DSB(); /* Ensure completion of memory access */
mbotkinl 0:2cc6bb4d7fea 736 while(1); /* wait until reset */
mbotkinl 0:2cc6bb4d7fea 737 }
mbotkinl 0:2cc6bb4d7fea 738
mbotkinl 0:2cc6bb4d7fea 739 /*@} end of CMSIS_Core_NVICFunctions */
mbotkinl 0:2cc6bb4d7fea 740
mbotkinl 0:2cc6bb4d7fea 741
mbotkinl 0:2cc6bb4d7fea 742
mbotkinl 0:2cc6bb4d7fea 743 /* ################################## SysTick function ############################################ */
mbotkinl 0:2cc6bb4d7fea 744 /** \ingroup CMSIS_Core_FunctionInterface
mbotkinl 0:2cc6bb4d7fea 745 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
mbotkinl 0:2cc6bb4d7fea 746 \brief Functions that configure the System.
mbotkinl 0:2cc6bb4d7fea 747 @{
mbotkinl 0:2cc6bb4d7fea 748 */
mbotkinl 0:2cc6bb4d7fea 749
mbotkinl 0:2cc6bb4d7fea 750 #if (__Vendor_SysTickConfig == 0)
mbotkinl 0:2cc6bb4d7fea 751
mbotkinl 0:2cc6bb4d7fea 752 /** \brief System Tick Configuration
mbotkinl 0:2cc6bb4d7fea 753
mbotkinl 0:2cc6bb4d7fea 754 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
mbotkinl 0:2cc6bb4d7fea 755 Counter is in free running mode to generate periodic interrupts.
mbotkinl 0:2cc6bb4d7fea 756
mbotkinl 0:2cc6bb4d7fea 757 \param [in] ticks Number of ticks between two interrupts.
mbotkinl 0:2cc6bb4d7fea 758
mbotkinl 0:2cc6bb4d7fea 759 \return 0 Function succeeded.
mbotkinl 0:2cc6bb4d7fea 760 \return 1 Function failed.
mbotkinl 0:2cc6bb4d7fea 761
mbotkinl 0:2cc6bb4d7fea 762 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
mbotkinl 0:2cc6bb4d7fea 763 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
mbotkinl 0:2cc6bb4d7fea 764 must contain a vendor-specific implementation of this function.
mbotkinl 0:2cc6bb4d7fea 765
mbotkinl 0:2cc6bb4d7fea 766 */
mbotkinl 0:2cc6bb4d7fea 767 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
mbotkinl 0:2cc6bb4d7fea 768 {
mbotkinl 0:2cc6bb4d7fea 769 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
mbotkinl 0:2cc6bb4d7fea 770
mbotkinl 0:2cc6bb4d7fea 771 SysTick->LOAD = ticks - 1; /* set reload register */
mbotkinl 0:2cc6bb4d7fea 772 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
mbotkinl 0:2cc6bb4d7fea 773 SysTick->VAL = 0; /* Load the SysTick Counter Value */
mbotkinl 0:2cc6bb4d7fea 774 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
mbotkinl 0:2cc6bb4d7fea 775 SysTick_CTRL_TICKINT_Msk |
mbotkinl 0:2cc6bb4d7fea 776 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
mbotkinl 0:2cc6bb4d7fea 777 return (0); /* Function successful */
mbotkinl 0:2cc6bb4d7fea 778 }
mbotkinl 0:2cc6bb4d7fea 779
mbotkinl 0:2cc6bb4d7fea 780 #endif
mbotkinl 0:2cc6bb4d7fea 781
mbotkinl 0:2cc6bb4d7fea 782 /*@} end of CMSIS_Core_SysTickFunctions */
mbotkinl 0:2cc6bb4d7fea 783
mbotkinl 0:2cc6bb4d7fea 784
mbotkinl 0:2cc6bb4d7fea 785
mbotkinl 0:2cc6bb4d7fea 786
mbotkinl 0:2cc6bb4d7fea 787 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
mbotkinl 0:2cc6bb4d7fea 788
mbotkinl 0:2cc6bb4d7fea 789 #endif /* __CMSIS_GENERIC */
mbotkinl 0:2cc6bb4d7fea 790
mbotkinl 0:2cc6bb4d7fea 791 #ifdef __cplusplus
mbotkinl 0:2cc6bb4d7fea 792 }
mbotkinl 0:2cc6bb4d7fea 793 #endif