Micah B / mbed

mbed

Dependents:   DHTSensor_Test K64F_eCompass_OneNET_JW

TARGET_ARCH_GPRS/core_cm0.h@0:2cc6bb4d7fea, 2015-02-25 (annotated)

Committer:
mbotkinl
Date:
Wed Feb 25 20:22:22 2015 +0000
Revision:
0:2cc6bb4d7fea
Working code to read Temperature and Humidity readings

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbotkinl 0:2cc6bb4d7fea 1 /**************************************************************************//**
mbotkinl 0:2cc6bb4d7fea 2 * @file core_cm0.h
mbotkinl 0:2cc6bb4d7fea 3 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
mbotkinl 0:2cc6bb4d7fea 4 * @version V3.20
mbotkinl 0:2cc6bb4d7fea 5 * @date 25. February 2013
mbotkinl 0:2cc6bb4d7fea 6 *
mbotkinl 0:2cc6bb4d7fea 7 * @note
mbotkinl 0:2cc6bb4d7fea 8 *
mbotkinl 0:2cc6bb4d7fea 9 ******************************************************************************/
mbotkinl 0:2cc6bb4d7fea 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
mbotkinl 0:2cc6bb4d7fea 11
mbotkinl 0:2cc6bb4d7fea 12 All rights reserved.
mbotkinl 0:2cc6bb4d7fea 13 Redistribution and use in source and binary forms, with or without
mbotkinl 0:2cc6bb4d7fea 14 modification, are permitted provided that the following conditions are met:
mbotkinl 0:2cc6bb4d7fea 15 - Redistributions of source code must retain the above copyright
mbotkinl 0:2cc6bb4d7fea 16 notice, this list of conditions and the following disclaimer.
mbotkinl 0:2cc6bb4d7fea 17 - Redistributions in binary form must reproduce the above copyright
mbotkinl 0:2cc6bb4d7fea 18 notice, this list of conditions and the following disclaimer in the
mbotkinl 0:2cc6bb4d7fea 19 documentation and/or other materials provided with the distribution.
mbotkinl 0:2cc6bb4d7fea 20 - Neither the name of ARM nor the names of its contributors may be used
mbotkinl 0:2cc6bb4d7fea 21 to endorse or promote products derived from this software without
mbotkinl 0:2cc6bb4d7fea 22 specific prior written permission.
mbotkinl 0:2cc6bb4d7fea 23 *
mbotkinl 0:2cc6bb4d7fea 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbotkinl 0:2cc6bb4d7fea 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbotkinl 0:2cc6bb4d7fea 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
mbotkinl 0:2cc6bb4d7fea 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
mbotkinl 0:2cc6bb4d7fea 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
mbotkinl 0:2cc6bb4d7fea 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
mbotkinl 0:2cc6bb4d7fea 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mbotkinl 0:2cc6bb4d7fea 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mbotkinl 0:2cc6bb4d7fea 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
mbotkinl 0:2cc6bb4d7fea 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mbotkinl 0:2cc6bb4d7fea 34 POSSIBILITY OF SUCH DAMAGE.
mbotkinl 0:2cc6bb4d7fea 35 ---------------------------------------------------------------------------*/
mbotkinl 0:2cc6bb4d7fea 36
mbotkinl 0:2cc6bb4d7fea 37
mbotkinl 0:2cc6bb4d7fea 38 #if defined ( __ICCARM__ )
mbotkinl 0:2cc6bb4d7fea 39 #pragma system_include /* treat file as system include file for MISRA check */
mbotkinl 0:2cc6bb4d7fea 40 #endif
mbotkinl 0:2cc6bb4d7fea 41
mbotkinl 0:2cc6bb4d7fea 42 #ifdef __cplusplus
mbotkinl 0:2cc6bb4d7fea 43 extern "C" {
mbotkinl 0:2cc6bb4d7fea 44 #endif
mbotkinl 0:2cc6bb4d7fea 45
mbotkinl 0:2cc6bb4d7fea 46 #ifndef __CORE_CM0_H_GENERIC
mbotkinl 0:2cc6bb4d7fea 47 #define __CORE_CM0_H_GENERIC
mbotkinl 0:2cc6bb4d7fea 48
mbotkinl 0:2cc6bb4d7fea 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
mbotkinl 0:2cc6bb4d7fea 50 CMSIS violates the following MISRA-C:2004 rules:
mbotkinl 0:2cc6bb4d7fea 51
mbotkinl 0:2cc6bb4d7fea 52 \li Required Rule 8.5, object/function definition in header file.<br>
mbotkinl 0:2cc6bb4d7fea 53 Function definitions in header files are used to allow 'inlining'.
mbotkinl 0:2cc6bb4d7fea 54
mbotkinl 0:2cc6bb4d7fea 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
mbotkinl 0:2cc6bb4d7fea 56 Unions are used for effective representation of core registers.
mbotkinl 0:2cc6bb4d7fea 57
mbotkinl 0:2cc6bb4d7fea 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
mbotkinl 0:2cc6bb4d7fea 59 Function-like macros are used to allow more efficient code.
mbotkinl 0:2cc6bb4d7fea 60 */
mbotkinl 0:2cc6bb4d7fea 61
mbotkinl 0:2cc6bb4d7fea 62
mbotkinl 0:2cc6bb4d7fea 63 /*******************************************************************************
mbotkinl 0:2cc6bb4d7fea 64 * CMSIS definitions
mbotkinl 0:2cc6bb4d7fea 65 ******************************************************************************/
mbotkinl 0:2cc6bb4d7fea 66 /** \ingroup Cortex_M0
mbotkinl 0:2cc6bb4d7fea 67 @{
mbotkinl 0:2cc6bb4d7fea 68 */
mbotkinl 0:2cc6bb4d7fea 69
mbotkinl 0:2cc6bb4d7fea 70 /* CMSIS CM0 definitions */
mbotkinl 0:2cc6bb4d7fea 71 #define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
mbotkinl 0:2cc6bb4d7fea 72 #define __CM0_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
mbotkinl 0:2cc6bb4d7fea 73 #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
mbotkinl 0:2cc6bb4d7fea 74 __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
mbotkinl 0:2cc6bb4d7fea 75
mbotkinl 0:2cc6bb4d7fea 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
mbotkinl 0:2cc6bb4d7fea 77
mbotkinl 0:2cc6bb4d7fea 78
mbotkinl 0:2cc6bb4d7fea 79 #if defined ( __CC_ARM )
mbotkinl 0:2cc6bb4d7fea 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
mbotkinl 0:2cc6bb4d7fea 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
mbotkinl 0:2cc6bb4d7fea 82 #define __STATIC_INLINE static __inline
mbotkinl 0:2cc6bb4d7fea 83
mbotkinl 0:2cc6bb4d7fea 84 #elif defined ( __ICCARM__ )
mbotkinl 0:2cc6bb4d7fea 85 #define __ASM __asm /*!< asm keyword for IAR Compiler */
mbotkinl 0:2cc6bb4d7fea 86 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
mbotkinl 0:2cc6bb4d7fea 87 #define __STATIC_INLINE static inline
mbotkinl 0:2cc6bb4d7fea 88
mbotkinl 0:2cc6bb4d7fea 89 #elif defined ( __GNUC__ )
mbotkinl 0:2cc6bb4d7fea 90 #define __ASM __asm /*!< asm keyword for GNU Compiler */
mbotkinl 0:2cc6bb4d7fea 91 #define __INLINE inline /*!< inline keyword for GNU Compiler */
mbotkinl 0:2cc6bb4d7fea 92 #define __STATIC_INLINE static inline
mbotkinl 0:2cc6bb4d7fea 93
mbotkinl 0:2cc6bb4d7fea 94 #elif defined ( __TASKING__ )
mbotkinl 0:2cc6bb4d7fea 95 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
mbotkinl 0:2cc6bb4d7fea 96 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
mbotkinl 0:2cc6bb4d7fea 97 #define __STATIC_INLINE static inline
mbotkinl 0:2cc6bb4d7fea 98
mbotkinl 0:2cc6bb4d7fea 99 #endif
mbotkinl 0:2cc6bb4d7fea 100
mbotkinl 0:2cc6bb4d7fea 101 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
mbotkinl 0:2cc6bb4d7fea 102 */
mbotkinl 0:2cc6bb4d7fea 103 #define __FPU_USED 0
mbotkinl 0:2cc6bb4d7fea 104
mbotkinl 0:2cc6bb4d7fea 105 #if defined ( __CC_ARM )
mbotkinl 0:2cc6bb4d7fea 106 #if defined __TARGET_FPU_VFP
mbotkinl 0:2cc6bb4d7fea 107 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbotkinl 0:2cc6bb4d7fea 108 #endif
mbotkinl 0:2cc6bb4d7fea 109
mbotkinl 0:2cc6bb4d7fea 110 #elif defined ( __ICCARM__ )
mbotkinl 0:2cc6bb4d7fea 111 #if defined __ARMVFP__
mbotkinl 0:2cc6bb4d7fea 112 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbotkinl 0:2cc6bb4d7fea 113 #endif
mbotkinl 0:2cc6bb4d7fea 114
mbotkinl 0:2cc6bb4d7fea 115 #elif defined ( __GNUC__ )
mbotkinl 0:2cc6bb4d7fea 116 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
mbotkinl 0:2cc6bb4d7fea 117 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbotkinl 0:2cc6bb4d7fea 118 #endif
mbotkinl 0:2cc6bb4d7fea 119
mbotkinl 0:2cc6bb4d7fea 120 #elif defined ( __TASKING__ )
mbotkinl 0:2cc6bb4d7fea 121 #if defined __FPU_VFP__
mbotkinl 0:2cc6bb4d7fea 122 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbotkinl 0:2cc6bb4d7fea 123 #endif
mbotkinl 0:2cc6bb4d7fea 124 #endif
mbotkinl 0:2cc6bb4d7fea 125
mbotkinl 0:2cc6bb4d7fea 126 #include <stdint.h> /* standard types definitions */
mbotkinl 0:2cc6bb4d7fea 127 #include <core_cmInstr.h> /* Core Instruction Access */
mbotkinl 0:2cc6bb4d7fea 128 #include <core_cmFunc.h> /* Core Function Access */
mbotkinl 0:2cc6bb4d7fea 129
mbotkinl 0:2cc6bb4d7fea 130 #endif /* __CORE_CM0_H_GENERIC */
mbotkinl 0:2cc6bb4d7fea 131
mbotkinl 0:2cc6bb4d7fea 132 #ifndef __CMSIS_GENERIC
mbotkinl 0:2cc6bb4d7fea 133
mbotkinl 0:2cc6bb4d7fea 134 #ifndef __CORE_CM0_H_DEPENDANT
mbotkinl 0:2cc6bb4d7fea 135 #define __CORE_CM0_H_DEPENDANT
mbotkinl 0:2cc6bb4d7fea 136
mbotkinl 0:2cc6bb4d7fea 137 /* check device defines and use defaults */
mbotkinl 0:2cc6bb4d7fea 138 #if defined __CHECK_DEVICE_DEFINES
mbotkinl 0:2cc6bb4d7fea 139 #ifndef __CM0_REV
mbotkinl 0:2cc6bb4d7fea 140 #define __CM0_REV 0x0000
mbotkinl 0:2cc6bb4d7fea 141 #warning "__CM0_REV not defined in device header file; using default!"
mbotkinl 0:2cc6bb4d7fea 142 #endif
mbotkinl 0:2cc6bb4d7fea 143
mbotkinl 0:2cc6bb4d7fea 144 #ifndef __NVIC_PRIO_BITS
mbotkinl 0:2cc6bb4d7fea 145 #define __NVIC_PRIO_BITS 2
mbotkinl 0:2cc6bb4d7fea 146 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
mbotkinl 0:2cc6bb4d7fea 147 #endif
mbotkinl 0:2cc6bb4d7fea 148
mbotkinl 0:2cc6bb4d7fea 149 #ifndef __Vendor_SysTickConfig
mbotkinl 0:2cc6bb4d7fea 150 #define __Vendor_SysTickConfig 0
mbotkinl 0:2cc6bb4d7fea 151 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
mbotkinl 0:2cc6bb4d7fea 152 #endif
mbotkinl 0:2cc6bb4d7fea 153 #endif
mbotkinl 0:2cc6bb4d7fea 154
mbotkinl 0:2cc6bb4d7fea 155 /* IO definitions (access restrictions to peripheral registers) */
mbotkinl 0:2cc6bb4d7fea 156 /**
mbotkinl 0:2cc6bb4d7fea 157 \defgroup CMSIS_glob_defs CMSIS Global Defines
mbotkinl 0:2cc6bb4d7fea 158
mbotkinl 0:2cc6bb4d7fea 159 <strong>IO Type Qualifiers</strong> are used
mbotkinl 0:2cc6bb4d7fea 160 \li to specify the access to peripheral variables.
mbotkinl 0:2cc6bb4d7fea 161 \li for automatic generation of peripheral register debug information.
mbotkinl 0:2cc6bb4d7fea 162 */
mbotkinl 0:2cc6bb4d7fea 163 #ifdef __cplusplus
mbotkinl 0:2cc6bb4d7fea 164 #define __I volatile /*!< Defines 'read only' permissions */
mbotkinl 0:2cc6bb4d7fea 165 #else
mbotkinl 0:2cc6bb4d7fea 166 #define __I volatile const /*!< Defines 'read only' permissions */
mbotkinl 0:2cc6bb4d7fea 167 #endif
mbotkinl 0:2cc6bb4d7fea 168 #define __O volatile /*!< Defines 'write only' permissions */
mbotkinl 0:2cc6bb4d7fea 169 #define __IO volatile /*!< Defines 'read / write' permissions */
mbotkinl 0:2cc6bb4d7fea 170
mbotkinl 0:2cc6bb4d7fea 171 /*@} end of group Cortex_M0 */
mbotkinl 0:2cc6bb4d7fea 172
mbotkinl 0:2cc6bb4d7fea 173
mbotkinl 0:2cc6bb4d7fea 174
mbotkinl 0:2cc6bb4d7fea 175 /*******************************************************************************
mbotkinl 0:2cc6bb4d7fea 176 * Register Abstraction
mbotkinl 0:2cc6bb4d7fea 177 Core Register contain:
mbotkinl 0:2cc6bb4d7fea 178 - Core Register
mbotkinl 0:2cc6bb4d7fea 179 - Core NVIC Register
mbotkinl 0:2cc6bb4d7fea 180 - Core SCB Register
mbotkinl 0:2cc6bb4d7fea 181 - Core SysTick Register
mbotkinl 0:2cc6bb4d7fea 182 ******************************************************************************/
mbotkinl 0:2cc6bb4d7fea 183 /** \defgroup CMSIS_core_register Defines and Type Definitions
mbotkinl 0:2cc6bb4d7fea 184 \brief Type definitions and defines for Cortex-M processor based devices.
mbotkinl 0:2cc6bb4d7fea 185 */
mbotkinl 0:2cc6bb4d7fea 186
mbotkinl 0:2cc6bb4d7fea 187 /** \ingroup CMSIS_core_register
mbotkinl 0:2cc6bb4d7fea 188 \defgroup CMSIS_CORE Status and Control Registers
mbotkinl 0:2cc6bb4d7fea 189 \brief Core Register type definitions.
mbotkinl 0:2cc6bb4d7fea 190 @{
mbotkinl 0:2cc6bb4d7fea 191 */
mbotkinl 0:2cc6bb4d7fea 192
mbotkinl 0:2cc6bb4d7fea 193 /** \brief Union type to access the Application Program Status Register (APSR).
mbotkinl 0:2cc6bb4d7fea 194 */
mbotkinl 0:2cc6bb4d7fea 195 typedef union
mbotkinl 0:2cc6bb4d7fea 196 {
mbotkinl 0:2cc6bb4d7fea 197 struct
mbotkinl 0:2cc6bb4d7fea 198 {
mbotkinl 0:2cc6bb4d7fea 199 #if (__CORTEX_M != 0x04)
mbotkinl 0:2cc6bb4d7fea 200 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
mbotkinl 0:2cc6bb4d7fea 201 #else
mbotkinl 0:2cc6bb4d7fea 202 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
mbotkinl 0:2cc6bb4d7fea 203 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
mbotkinl 0:2cc6bb4d7fea 204 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
mbotkinl 0:2cc6bb4d7fea 205 #endif
mbotkinl 0:2cc6bb4d7fea 206 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
mbotkinl 0:2cc6bb4d7fea 207 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
mbotkinl 0:2cc6bb4d7fea 208 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
mbotkinl 0:2cc6bb4d7fea 209 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
mbotkinl 0:2cc6bb4d7fea 210 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
mbotkinl 0:2cc6bb4d7fea 211 } b; /*!< Structure used for bit access */
mbotkinl 0:2cc6bb4d7fea 212 uint32_t w; /*!< Type used for word access */
mbotkinl 0:2cc6bb4d7fea 213 } APSR_Type;
mbotkinl 0:2cc6bb4d7fea 214
mbotkinl 0:2cc6bb4d7fea 215
mbotkinl 0:2cc6bb4d7fea 216 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
mbotkinl 0:2cc6bb4d7fea 217 */
mbotkinl 0:2cc6bb4d7fea 218 typedef union
mbotkinl 0:2cc6bb4d7fea 219 {
mbotkinl 0:2cc6bb4d7fea 220 struct
mbotkinl 0:2cc6bb4d7fea 221 {
mbotkinl 0:2cc6bb4d7fea 222 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
mbotkinl 0:2cc6bb4d7fea 223 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
mbotkinl 0:2cc6bb4d7fea 224 } b; /*!< Structure used for bit access */
mbotkinl 0:2cc6bb4d7fea 225 uint32_t w; /*!< Type used for word access */
mbotkinl 0:2cc6bb4d7fea 226 } IPSR_Type;
mbotkinl 0:2cc6bb4d7fea 227
mbotkinl 0:2cc6bb4d7fea 228
mbotkinl 0:2cc6bb4d7fea 229 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
mbotkinl 0:2cc6bb4d7fea 230 */
mbotkinl 0:2cc6bb4d7fea 231 typedef union
mbotkinl 0:2cc6bb4d7fea 232 {
mbotkinl 0:2cc6bb4d7fea 233 struct
mbotkinl 0:2cc6bb4d7fea 234 {
mbotkinl 0:2cc6bb4d7fea 235 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
mbotkinl 0:2cc6bb4d7fea 236 #if (__CORTEX_M != 0x04)
mbotkinl 0:2cc6bb4d7fea 237 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
mbotkinl 0:2cc6bb4d7fea 238 #else
mbotkinl 0:2cc6bb4d7fea 239 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
mbotkinl 0:2cc6bb4d7fea 240 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
mbotkinl 0:2cc6bb4d7fea 241 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
mbotkinl 0:2cc6bb4d7fea 242 #endif
mbotkinl 0:2cc6bb4d7fea 243 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
mbotkinl 0:2cc6bb4d7fea 244 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
mbotkinl 0:2cc6bb4d7fea 245 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
mbotkinl 0:2cc6bb4d7fea 246 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
mbotkinl 0:2cc6bb4d7fea 247 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
mbotkinl 0:2cc6bb4d7fea 248 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
mbotkinl 0:2cc6bb4d7fea 249 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
mbotkinl 0:2cc6bb4d7fea 250 } b; /*!< Structure used for bit access */
mbotkinl 0:2cc6bb4d7fea 251 uint32_t w; /*!< Type used for word access */
mbotkinl 0:2cc6bb4d7fea 252 } xPSR_Type;
mbotkinl 0:2cc6bb4d7fea 253
mbotkinl 0:2cc6bb4d7fea 254
mbotkinl 0:2cc6bb4d7fea 255 /** \brief Union type to access the Control Registers (CONTROL).
mbotkinl 0:2cc6bb4d7fea 256 */
mbotkinl 0:2cc6bb4d7fea 257 typedef union
mbotkinl 0:2cc6bb4d7fea 258 {
mbotkinl 0:2cc6bb4d7fea 259 struct
mbotkinl 0:2cc6bb4d7fea 260 {
mbotkinl 0:2cc6bb4d7fea 261 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
mbotkinl 0:2cc6bb4d7fea 262 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
mbotkinl 0:2cc6bb4d7fea 263 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
mbotkinl 0:2cc6bb4d7fea 264 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
mbotkinl 0:2cc6bb4d7fea 265 } b; /*!< Structure used for bit access */
mbotkinl 0:2cc6bb4d7fea 266 uint32_t w; /*!< Type used for word access */
mbotkinl 0:2cc6bb4d7fea 267 } CONTROL_Type;
mbotkinl 0:2cc6bb4d7fea 268
mbotkinl 0:2cc6bb4d7fea 269 /*@} end of group CMSIS_CORE */
mbotkinl 0:2cc6bb4d7fea 270
mbotkinl 0:2cc6bb4d7fea 271
mbotkinl 0:2cc6bb4d7fea 272 /** \ingroup CMSIS_core_register
mbotkinl 0:2cc6bb4d7fea 273 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
mbotkinl 0:2cc6bb4d7fea 274 \brief Type definitions for the NVIC Registers
mbotkinl 0:2cc6bb4d7fea 275 @{
mbotkinl 0:2cc6bb4d7fea 276 */
mbotkinl 0:2cc6bb4d7fea 277
mbotkinl 0:2cc6bb4d7fea 278 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
mbotkinl 0:2cc6bb4d7fea 279 */
mbotkinl 0:2cc6bb4d7fea 280 typedef struct
mbotkinl 0:2cc6bb4d7fea 281 {
mbotkinl 0:2cc6bb4d7fea 282 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
mbotkinl 0:2cc6bb4d7fea 283 uint32_t RESERVED0[31];
mbotkinl 0:2cc6bb4d7fea 284 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
mbotkinl 0:2cc6bb4d7fea 285 uint32_t RSERVED1[31];
mbotkinl 0:2cc6bb4d7fea 286 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
mbotkinl 0:2cc6bb4d7fea 287 uint32_t RESERVED2[31];
mbotkinl 0:2cc6bb4d7fea 288 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
mbotkinl 0:2cc6bb4d7fea 289 uint32_t RESERVED3[31];
mbotkinl 0:2cc6bb4d7fea 290 uint32_t RESERVED4[64];
mbotkinl 0:2cc6bb4d7fea 291 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
mbotkinl 0:2cc6bb4d7fea 292 } NVIC_Type;
mbotkinl 0:2cc6bb4d7fea 293
mbotkinl 0:2cc6bb4d7fea 294 /*@} end of group CMSIS_NVIC */
mbotkinl 0:2cc6bb4d7fea 295
mbotkinl 0:2cc6bb4d7fea 296
mbotkinl 0:2cc6bb4d7fea 297 /** \ingroup CMSIS_core_register
mbotkinl 0:2cc6bb4d7fea 298 \defgroup CMSIS_SCB System Control Block (SCB)
mbotkinl 0:2cc6bb4d7fea 299 \brief Type definitions for the System Control Block Registers
mbotkinl 0:2cc6bb4d7fea 300 @{
mbotkinl 0:2cc6bb4d7fea 301 */
mbotkinl 0:2cc6bb4d7fea 302
mbotkinl 0:2cc6bb4d7fea 303 /** \brief Structure type to access the System Control Block (SCB).
mbotkinl 0:2cc6bb4d7fea 304 */
mbotkinl 0:2cc6bb4d7fea 305 typedef struct
mbotkinl 0:2cc6bb4d7fea 306 {
mbotkinl 0:2cc6bb4d7fea 307 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
mbotkinl 0:2cc6bb4d7fea 308 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
mbotkinl 0:2cc6bb4d7fea 309 uint32_t RESERVED0;
mbotkinl 0:2cc6bb4d7fea 310 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
mbotkinl 0:2cc6bb4d7fea 311 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
mbotkinl 0:2cc6bb4d7fea 312 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
mbotkinl 0:2cc6bb4d7fea 313 uint32_t RESERVED1;
mbotkinl 0:2cc6bb4d7fea 314 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
mbotkinl 0:2cc6bb4d7fea 315 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
mbotkinl 0:2cc6bb4d7fea 316 } SCB_Type;
mbotkinl 0:2cc6bb4d7fea 317
mbotkinl 0:2cc6bb4d7fea 318 /* SCB CPUID Register Definitions */
mbotkinl 0:2cc6bb4d7fea 319 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
mbotkinl 0:2cc6bb4d7fea 320 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
mbotkinl 0:2cc6bb4d7fea 321
mbotkinl 0:2cc6bb4d7fea 322 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
mbotkinl 0:2cc6bb4d7fea 323 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
mbotkinl 0:2cc6bb4d7fea 324
mbotkinl 0:2cc6bb4d7fea 325 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
mbotkinl 0:2cc6bb4d7fea 326 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
mbotkinl 0:2cc6bb4d7fea 327
mbotkinl 0:2cc6bb4d7fea 328 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
mbotkinl 0:2cc6bb4d7fea 329 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
mbotkinl 0:2cc6bb4d7fea 330
mbotkinl 0:2cc6bb4d7fea 331 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
mbotkinl 0:2cc6bb4d7fea 332 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
mbotkinl 0:2cc6bb4d7fea 333
mbotkinl 0:2cc6bb4d7fea 334 /* SCB Interrupt Control State Register Definitions */
mbotkinl 0:2cc6bb4d7fea 335 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
mbotkinl 0:2cc6bb4d7fea 336 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
mbotkinl 0:2cc6bb4d7fea 337
mbotkinl 0:2cc6bb4d7fea 338 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
mbotkinl 0:2cc6bb4d7fea 339 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
mbotkinl 0:2cc6bb4d7fea 340
mbotkinl 0:2cc6bb4d7fea 341 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
mbotkinl 0:2cc6bb4d7fea 342 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
mbotkinl 0:2cc6bb4d7fea 343
mbotkinl 0:2cc6bb4d7fea 344 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
mbotkinl 0:2cc6bb4d7fea 345 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
mbotkinl 0:2cc6bb4d7fea 346
mbotkinl 0:2cc6bb4d7fea 347 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
mbotkinl 0:2cc6bb4d7fea 348 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
mbotkinl 0:2cc6bb4d7fea 349
mbotkinl 0:2cc6bb4d7fea 350 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
mbotkinl 0:2cc6bb4d7fea 351 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
mbotkinl 0:2cc6bb4d7fea 352
mbotkinl 0:2cc6bb4d7fea 353 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
mbotkinl 0:2cc6bb4d7fea 354 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
mbotkinl 0:2cc6bb4d7fea 355
mbotkinl 0:2cc6bb4d7fea 356 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
mbotkinl 0:2cc6bb4d7fea 357 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
mbotkinl 0:2cc6bb4d7fea 358
mbotkinl 0:2cc6bb4d7fea 359 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
mbotkinl 0:2cc6bb4d7fea 360 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
mbotkinl 0:2cc6bb4d7fea 361
mbotkinl 0:2cc6bb4d7fea 362 /* SCB Application Interrupt and Reset Control Register Definitions */
mbotkinl 0:2cc6bb4d7fea 363 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
mbotkinl 0:2cc6bb4d7fea 364 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
mbotkinl 0:2cc6bb4d7fea 365
mbotkinl 0:2cc6bb4d7fea 366 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
mbotkinl 0:2cc6bb4d7fea 367 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
mbotkinl 0:2cc6bb4d7fea 368
mbotkinl 0:2cc6bb4d7fea 369 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
mbotkinl 0:2cc6bb4d7fea 370 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
mbotkinl 0:2cc6bb4d7fea 371
mbotkinl 0:2cc6bb4d7fea 372 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
mbotkinl 0:2cc6bb4d7fea 373 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
mbotkinl 0:2cc6bb4d7fea 374
mbotkinl 0:2cc6bb4d7fea 375 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
mbotkinl 0:2cc6bb4d7fea 376 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
mbotkinl 0:2cc6bb4d7fea 377
mbotkinl 0:2cc6bb4d7fea 378 /* SCB System Control Register Definitions */
mbotkinl 0:2cc6bb4d7fea 379 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
mbotkinl 0:2cc6bb4d7fea 380 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
mbotkinl 0:2cc6bb4d7fea 381
mbotkinl 0:2cc6bb4d7fea 382 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
mbotkinl 0:2cc6bb4d7fea 383 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
mbotkinl 0:2cc6bb4d7fea 384
mbotkinl 0:2cc6bb4d7fea 385 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
mbotkinl 0:2cc6bb4d7fea 386 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
mbotkinl 0:2cc6bb4d7fea 387
mbotkinl 0:2cc6bb4d7fea 388 /* SCB Configuration Control Register Definitions */
mbotkinl 0:2cc6bb4d7fea 389 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
mbotkinl 0:2cc6bb4d7fea 390 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
mbotkinl 0:2cc6bb4d7fea 391
mbotkinl 0:2cc6bb4d7fea 392 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
mbotkinl 0:2cc6bb4d7fea 393 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
mbotkinl 0:2cc6bb4d7fea 394
mbotkinl 0:2cc6bb4d7fea 395 /* SCB System Handler Control and State Register Definitions */
mbotkinl 0:2cc6bb4d7fea 396 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
mbotkinl 0:2cc6bb4d7fea 397 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
mbotkinl 0:2cc6bb4d7fea 398
mbotkinl 0:2cc6bb4d7fea 399 /*@} end of group CMSIS_SCB */
mbotkinl 0:2cc6bb4d7fea 400
mbotkinl 0:2cc6bb4d7fea 401
mbotkinl 0:2cc6bb4d7fea 402 /** \ingroup CMSIS_core_register
mbotkinl 0:2cc6bb4d7fea 403 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
mbotkinl 0:2cc6bb4d7fea 404 \brief Type definitions for the System Timer Registers.
mbotkinl 0:2cc6bb4d7fea 405 @{
mbotkinl 0:2cc6bb4d7fea 406 */
mbotkinl 0:2cc6bb4d7fea 407
mbotkinl 0:2cc6bb4d7fea 408 /** \brief Structure type to access the System Timer (SysTick).
mbotkinl 0:2cc6bb4d7fea 409 */
mbotkinl 0:2cc6bb4d7fea 410 typedef struct
mbotkinl 0:2cc6bb4d7fea 411 {
mbotkinl 0:2cc6bb4d7fea 412 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
mbotkinl 0:2cc6bb4d7fea 413 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
mbotkinl 0:2cc6bb4d7fea 414 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
mbotkinl 0:2cc6bb4d7fea 415 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
mbotkinl 0:2cc6bb4d7fea 416 } SysTick_Type;
mbotkinl 0:2cc6bb4d7fea 417
mbotkinl 0:2cc6bb4d7fea 418 /* SysTick Control / Status Register Definitions */
mbotkinl 0:2cc6bb4d7fea 419 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
mbotkinl 0:2cc6bb4d7fea 420 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
mbotkinl 0:2cc6bb4d7fea 421
mbotkinl 0:2cc6bb4d7fea 422 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
mbotkinl 0:2cc6bb4d7fea 423 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
mbotkinl 0:2cc6bb4d7fea 424
mbotkinl 0:2cc6bb4d7fea 425 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
mbotkinl 0:2cc6bb4d7fea 426 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
mbotkinl 0:2cc6bb4d7fea 427
mbotkinl 0:2cc6bb4d7fea 428 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
mbotkinl 0:2cc6bb4d7fea 429 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
mbotkinl 0:2cc6bb4d7fea 430
mbotkinl 0:2cc6bb4d7fea 431 /* SysTick Reload Register Definitions */
mbotkinl 0:2cc6bb4d7fea 432 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
mbotkinl 0:2cc6bb4d7fea 433 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
mbotkinl 0:2cc6bb4d7fea 434
mbotkinl 0:2cc6bb4d7fea 435 /* SysTick Current Register Definitions */
mbotkinl 0:2cc6bb4d7fea 436 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
mbotkinl 0:2cc6bb4d7fea 437 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
mbotkinl 0:2cc6bb4d7fea 438
mbotkinl 0:2cc6bb4d7fea 439 /* SysTick Calibration Register Definitions */
mbotkinl 0:2cc6bb4d7fea 440 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
mbotkinl 0:2cc6bb4d7fea 441 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
mbotkinl 0:2cc6bb4d7fea 442
mbotkinl 0:2cc6bb4d7fea 443 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
mbotkinl 0:2cc6bb4d7fea 444 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
mbotkinl 0:2cc6bb4d7fea 445
mbotkinl 0:2cc6bb4d7fea 446 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
mbotkinl 0:2cc6bb4d7fea 447 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
mbotkinl 0:2cc6bb4d7fea 448
mbotkinl 0:2cc6bb4d7fea 449 /*@} end of group CMSIS_SysTick */
mbotkinl 0:2cc6bb4d7fea 450
mbotkinl 0:2cc6bb4d7fea 451
mbotkinl 0:2cc6bb4d7fea 452 /** \ingroup CMSIS_core_register
mbotkinl 0:2cc6bb4d7fea 453 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
mbotkinl 0:2cc6bb4d7fea 454 \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
mbotkinl 0:2cc6bb4d7fea 455 are only accessible over DAP and not via processor. Therefore
mbotkinl 0:2cc6bb4d7fea 456 they are not covered by the Cortex-M0 header file.
mbotkinl 0:2cc6bb4d7fea 457 @{
mbotkinl 0:2cc6bb4d7fea 458 */
mbotkinl 0:2cc6bb4d7fea 459 /*@} end of group CMSIS_CoreDebug */
mbotkinl 0:2cc6bb4d7fea 460
mbotkinl 0:2cc6bb4d7fea 461
mbotkinl 0:2cc6bb4d7fea 462 /** \ingroup CMSIS_core_register
mbotkinl 0:2cc6bb4d7fea 463 \defgroup CMSIS_core_base Core Definitions
mbotkinl 0:2cc6bb4d7fea 464 \brief Definitions for base addresses, unions, and structures.
mbotkinl 0:2cc6bb4d7fea 465 @{
mbotkinl 0:2cc6bb4d7fea 466 */
mbotkinl 0:2cc6bb4d7fea 467
mbotkinl 0:2cc6bb4d7fea 468 /* Memory mapping of Cortex-M0 Hardware */
mbotkinl 0:2cc6bb4d7fea 469 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
mbotkinl 0:2cc6bb4d7fea 470 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
mbotkinl 0:2cc6bb4d7fea 471 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
mbotkinl 0:2cc6bb4d7fea 472 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
mbotkinl 0:2cc6bb4d7fea 473
mbotkinl 0:2cc6bb4d7fea 474 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
mbotkinl 0:2cc6bb4d7fea 475 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
mbotkinl 0:2cc6bb4d7fea 476 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
mbotkinl 0:2cc6bb4d7fea 477
mbotkinl 0:2cc6bb4d7fea 478
mbotkinl 0:2cc6bb4d7fea 479 /*@} */
mbotkinl 0:2cc6bb4d7fea 480
mbotkinl 0:2cc6bb4d7fea 481
mbotkinl 0:2cc6bb4d7fea 482
mbotkinl 0:2cc6bb4d7fea 483 /*******************************************************************************
mbotkinl 0:2cc6bb4d7fea 484 * Hardware Abstraction Layer
mbotkinl 0:2cc6bb4d7fea 485 Core Function Interface contains:
mbotkinl 0:2cc6bb4d7fea 486 - Core NVIC Functions
mbotkinl 0:2cc6bb4d7fea 487 - Core SysTick Functions
mbotkinl 0:2cc6bb4d7fea 488 - Core Register Access Functions
mbotkinl 0:2cc6bb4d7fea 489 ******************************************************************************/
mbotkinl 0:2cc6bb4d7fea 490 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
mbotkinl 0:2cc6bb4d7fea 491 */
mbotkinl 0:2cc6bb4d7fea 492
mbotkinl 0:2cc6bb4d7fea 493
mbotkinl 0:2cc6bb4d7fea 494
mbotkinl 0:2cc6bb4d7fea 495 /* ########################## NVIC functions #################################### */
mbotkinl 0:2cc6bb4d7fea 496 /** \ingroup CMSIS_Core_FunctionInterface
mbotkinl 0:2cc6bb4d7fea 497 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
mbotkinl 0:2cc6bb4d7fea 498 \brief Functions that manage interrupts and exceptions via the NVIC.
mbotkinl 0:2cc6bb4d7fea 499 @{
mbotkinl 0:2cc6bb4d7fea 500 */
mbotkinl 0:2cc6bb4d7fea 501
mbotkinl 0:2cc6bb4d7fea 502 /* Interrupt Priorities are WORD accessible only under ARMv6M */
mbotkinl 0:2cc6bb4d7fea 503 /* The following MACROS handle generation of the register offset and byte masks */
mbotkinl 0:2cc6bb4d7fea 504 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
mbotkinl 0:2cc6bb4d7fea 505 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
mbotkinl 0:2cc6bb4d7fea 506 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
mbotkinl 0:2cc6bb4d7fea 507
mbotkinl 0:2cc6bb4d7fea 508
mbotkinl 0:2cc6bb4d7fea 509 /** \brief Enable External Interrupt
mbotkinl 0:2cc6bb4d7fea 510
mbotkinl 0:2cc6bb4d7fea 511 The function enables a device-specific interrupt in the NVIC interrupt controller.
mbotkinl 0:2cc6bb4d7fea 512
mbotkinl 0:2cc6bb4d7fea 513 \param [in] IRQn External interrupt number. Value cannot be negative.
mbotkinl 0:2cc6bb4d7fea 514 */
mbotkinl 0:2cc6bb4d7fea 515 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
mbotkinl 0:2cc6bb4d7fea 516 {
mbotkinl 0:2cc6bb4d7fea 517 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
mbotkinl 0:2cc6bb4d7fea 518 }
mbotkinl 0:2cc6bb4d7fea 519
mbotkinl 0:2cc6bb4d7fea 520
mbotkinl 0:2cc6bb4d7fea 521 /** \brief Disable External Interrupt
mbotkinl 0:2cc6bb4d7fea 522
mbotkinl 0:2cc6bb4d7fea 523 The function disables a device-specific interrupt in the NVIC interrupt controller.
mbotkinl 0:2cc6bb4d7fea 524
mbotkinl 0:2cc6bb4d7fea 525 \param [in] IRQn External interrupt number. Value cannot be negative.
mbotkinl 0:2cc6bb4d7fea 526 */
mbotkinl 0:2cc6bb4d7fea 527 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
mbotkinl 0:2cc6bb4d7fea 528 {
mbotkinl 0:2cc6bb4d7fea 529 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
mbotkinl 0:2cc6bb4d7fea 530 }
mbotkinl 0:2cc6bb4d7fea 531
mbotkinl 0:2cc6bb4d7fea 532
mbotkinl 0:2cc6bb4d7fea 533 /** \brief Get Pending Interrupt
mbotkinl 0:2cc6bb4d7fea 534
mbotkinl 0:2cc6bb4d7fea 535 The function reads the pending register in the NVIC and returns the pending bit
mbotkinl 0:2cc6bb4d7fea 536 for the specified interrupt.
mbotkinl 0:2cc6bb4d7fea 537
mbotkinl 0:2cc6bb4d7fea 538 \param [in] IRQn Interrupt number.
mbotkinl 0:2cc6bb4d7fea 539
mbotkinl 0:2cc6bb4d7fea 540 \return 0 Interrupt status is not pending.
mbotkinl 0:2cc6bb4d7fea 541 \return 1 Interrupt status is pending.
mbotkinl 0:2cc6bb4d7fea 542 */
mbotkinl 0:2cc6bb4d7fea 543 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
mbotkinl 0:2cc6bb4d7fea 544 {
mbotkinl 0:2cc6bb4d7fea 545 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
mbotkinl 0:2cc6bb4d7fea 546 }
mbotkinl 0:2cc6bb4d7fea 547
mbotkinl 0:2cc6bb4d7fea 548
mbotkinl 0:2cc6bb4d7fea 549 /** \brief Set Pending Interrupt
mbotkinl 0:2cc6bb4d7fea 550
mbotkinl 0:2cc6bb4d7fea 551 The function sets the pending bit of an external interrupt.
mbotkinl 0:2cc6bb4d7fea 552
mbotkinl 0:2cc6bb4d7fea 553 \param [in] IRQn Interrupt number. Value cannot be negative.
mbotkinl 0:2cc6bb4d7fea 554 */
mbotkinl 0:2cc6bb4d7fea 555 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
mbotkinl 0:2cc6bb4d7fea 556 {
mbotkinl 0:2cc6bb4d7fea 557 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
mbotkinl 0:2cc6bb4d7fea 558 }
mbotkinl 0:2cc6bb4d7fea 559
mbotkinl 0:2cc6bb4d7fea 560
mbotkinl 0:2cc6bb4d7fea 561 /** \brief Clear Pending Interrupt
mbotkinl 0:2cc6bb4d7fea 562
mbotkinl 0:2cc6bb4d7fea 563 The function clears the pending bit of an external interrupt.
mbotkinl 0:2cc6bb4d7fea 564
mbotkinl 0:2cc6bb4d7fea 565 \param [in] IRQn External interrupt number. Value cannot be negative.
mbotkinl 0:2cc6bb4d7fea 566 */
mbotkinl 0:2cc6bb4d7fea 567 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
mbotkinl 0:2cc6bb4d7fea 568 {
mbotkinl 0:2cc6bb4d7fea 569 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
mbotkinl 0:2cc6bb4d7fea 570 }
mbotkinl 0:2cc6bb4d7fea 571
mbotkinl 0:2cc6bb4d7fea 572
mbotkinl 0:2cc6bb4d7fea 573 /** \brief Set Interrupt Priority
mbotkinl 0:2cc6bb4d7fea 574
mbotkinl 0:2cc6bb4d7fea 575 The function sets the priority of an interrupt.
mbotkinl 0:2cc6bb4d7fea 576
mbotkinl 0:2cc6bb4d7fea 577 \note The priority cannot be set for every core interrupt.
mbotkinl 0:2cc6bb4d7fea 578
mbotkinl 0:2cc6bb4d7fea 579 \param [in] IRQn Interrupt number.
mbotkinl 0:2cc6bb4d7fea 580 \param [in] priority Priority to set.
mbotkinl 0:2cc6bb4d7fea 581 */
mbotkinl 0:2cc6bb4d7fea 582 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
mbotkinl 0:2cc6bb4d7fea 583 {
mbotkinl 0:2cc6bb4d7fea 584 if(IRQn < 0) {
mbotkinl 0:2cc6bb4d7fea 585 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
mbotkinl 0:2cc6bb4d7fea 586 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
mbotkinl 0:2cc6bb4d7fea 587 else {
mbotkinl 0:2cc6bb4d7fea 588 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
mbotkinl 0:2cc6bb4d7fea 589 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
mbotkinl 0:2cc6bb4d7fea 590 }
mbotkinl 0:2cc6bb4d7fea 591
mbotkinl 0:2cc6bb4d7fea 592
mbotkinl 0:2cc6bb4d7fea 593 /** \brief Get Interrupt Priority
mbotkinl 0:2cc6bb4d7fea 594
mbotkinl 0:2cc6bb4d7fea 595 The function reads the priority of an interrupt. The interrupt
mbotkinl 0:2cc6bb4d7fea 596 number can be positive to specify an external (device specific)
mbotkinl 0:2cc6bb4d7fea 597 interrupt, or negative to specify an internal (core) interrupt.
mbotkinl 0:2cc6bb4d7fea 598
mbotkinl 0:2cc6bb4d7fea 599
mbotkinl 0:2cc6bb4d7fea 600 \param [in] IRQn Interrupt number.
mbotkinl 0:2cc6bb4d7fea 601 \return Interrupt Priority. Value is aligned automatically to the implemented
mbotkinl 0:2cc6bb4d7fea 602 priority bits of the microcontroller.
mbotkinl 0:2cc6bb4d7fea 603 */
mbotkinl 0:2cc6bb4d7fea 604 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
mbotkinl 0:2cc6bb4d7fea 605 {
mbotkinl 0:2cc6bb4d7fea 606
mbotkinl 0:2cc6bb4d7fea 607 if(IRQn < 0) {
mbotkinl 0:2cc6bb4d7fea 608 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
mbotkinl 0:2cc6bb4d7fea 609 else {
mbotkinl 0:2cc6bb4d7fea 610 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
mbotkinl 0:2cc6bb4d7fea 611 }
mbotkinl 0:2cc6bb4d7fea 612
mbotkinl 0:2cc6bb4d7fea 613
mbotkinl 0:2cc6bb4d7fea 614 /** \brief System Reset
mbotkinl 0:2cc6bb4d7fea 615
mbotkinl 0:2cc6bb4d7fea 616 The function initiates a system reset request to reset the MCU.
mbotkinl 0:2cc6bb4d7fea 617 */
mbotkinl 0:2cc6bb4d7fea 618 __STATIC_INLINE void NVIC_SystemReset(void)
mbotkinl 0:2cc6bb4d7fea 619 {
mbotkinl 0:2cc6bb4d7fea 620 __DSB(); /* Ensure all outstanding memory accesses included
mbotkinl 0:2cc6bb4d7fea 621 buffered write are completed before reset */
mbotkinl 0:2cc6bb4d7fea 622 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
mbotkinl 0:2cc6bb4d7fea 623 SCB_AIRCR_SYSRESETREQ_Msk);
mbotkinl 0:2cc6bb4d7fea 624 __DSB(); /* Ensure completion of memory access */
mbotkinl 0:2cc6bb4d7fea 625 while(1); /* wait until reset */
mbotkinl 0:2cc6bb4d7fea 626 }
mbotkinl 0:2cc6bb4d7fea 627
mbotkinl 0:2cc6bb4d7fea 628 /*@} end of CMSIS_Core_NVICFunctions */
mbotkinl 0:2cc6bb4d7fea 629
mbotkinl 0:2cc6bb4d7fea 630
mbotkinl 0:2cc6bb4d7fea 631
mbotkinl 0:2cc6bb4d7fea 632 /* ################################## SysTick function ############################################ */
mbotkinl 0:2cc6bb4d7fea 633 /** \ingroup CMSIS_Core_FunctionInterface
mbotkinl 0:2cc6bb4d7fea 634 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
mbotkinl 0:2cc6bb4d7fea 635 \brief Functions that configure the System.
mbotkinl 0:2cc6bb4d7fea 636 @{
mbotkinl 0:2cc6bb4d7fea 637 */
mbotkinl 0:2cc6bb4d7fea 638
mbotkinl 0:2cc6bb4d7fea 639 #if (__Vendor_SysTickConfig == 0)
mbotkinl 0:2cc6bb4d7fea 640
mbotkinl 0:2cc6bb4d7fea 641 /** \brief System Tick Configuration
mbotkinl 0:2cc6bb4d7fea 642
mbotkinl 0:2cc6bb4d7fea 643 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
mbotkinl 0:2cc6bb4d7fea 644 Counter is in free running mode to generate periodic interrupts.
mbotkinl 0:2cc6bb4d7fea 645
mbotkinl 0:2cc6bb4d7fea 646 \param [in] ticks Number of ticks between two interrupts.
mbotkinl 0:2cc6bb4d7fea 647
mbotkinl 0:2cc6bb4d7fea 648 \return 0 Function succeeded.
mbotkinl 0:2cc6bb4d7fea 649 \return 1 Function failed.
mbotkinl 0:2cc6bb4d7fea 650
mbotkinl 0:2cc6bb4d7fea 651 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
mbotkinl 0:2cc6bb4d7fea 652 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
mbotkinl 0:2cc6bb4d7fea 653 must contain a vendor-specific implementation of this function.
mbotkinl 0:2cc6bb4d7fea 654
mbotkinl 0:2cc6bb4d7fea 655 */
mbotkinl 0:2cc6bb4d7fea 656 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
mbotkinl 0:2cc6bb4d7fea 657 {
mbotkinl 0:2cc6bb4d7fea 658 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
mbotkinl 0:2cc6bb4d7fea 659
mbotkinl 0:2cc6bb4d7fea 660 SysTick->LOAD = ticks - 1; /* set reload register */
mbotkinl 0:2cc6bb4d7fea 661 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
mbotkinl 0:2cc6bb4d7fea 662 SysTick->VAL = 0; /* Load the SysTick Counter Value */
mbotkinl 0:2cc6bb4d7fea 663 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
mbotkinl 0:2cc6bb4d7fea 664 SysTick_CTRL_TICKINT_Msk |
mbotkinl 0:2cc6bb4d7fea 665 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
mbotkinl 0:2cc6bb4d7fea 666 return (0); /* Function successful */
mbotkinl 0:2cc6bb4d7fea 667 }
mbotkinl 0:2cc6bb4d7fea 668
mbotkinl 0:2cc6bb4d7fea 669 #endif
mbotkinl 0:2cc6bb4d7fea 670
mbotkinl 0:2cc6bb4d7fea 671 /*@} end of CMSIS_Core_SysTickFunctions */
mbotkinl 0:2cc6bb4d7fea 672
mbotkinl 0:2cc6bb4d7fea 673
mbotkinl 0:2cc6bb4d7fea 674
mbotkinl 0:2cc6bb4d7fea 675
mbotkinl 0:2cc6bb4d7fea 676 #endif /* __CORE_CM0_H_DEPENDANT */
mbotkinl 0:2cc6bb4d7fea 677
mbotkinl 0:2cc6bb4d7fea 678 #endif /* __CMSIS_GENERIC */
mbotkinl 0:2cc6bb4d7fea 679
mbotkinl 0:2cc6bb4d7fea 680 #ifdef __cplusplus
mbotkinl 0:2cc6bb4d7fea 681 }
mbotkinl 0:2cc6bb4d7fea 682 #endif