Micah B / mbed

mbed

Dependents:   DHTSensor_Test K64F_eCompass_OneNET_JW

TARGET_ARCH_GPRS/core_caFunc.h@0:2cc6bb4d7fea, 2015-02-25 (annotated)

Committer:
mbotkinl
Date:
Wed Feb 25 20:22:22 2015 +0000
Revision:
0:2cc6bb4d7fea
Working code to read Temperature and Humidity readings

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbotkinl 0:2cc6bb4d7fea 1 /**************************************************************************//**
mbotkinl 0:2cc6bb4d7fea 2 * @file core_caFunc.h
mbotkinl 0:2cc6bb4d7fea 3 * @brief CMSIS Cortex-A Core Function Access Header File
mbotkinl 0:2cc6bb4d7fea 4 * @version V3.10
mbotkinl 0:2cc6bb4d7fea 5 * @date 9 May 2013
mbotkinl 0:2cc6bb4d7fea 6 *
mbotkinl 0:2cc6bb4d7fea 7 * @note
mbotkinl 0:2cc6bb4d7fea 8 *
mbotkinl 0:2cc6bb4d7fea 9 ******************************************************************************/
mbotkinl 0:2cc6bb4d7fea 10 /* Copyright (c) 2009 - 2012 ARM LIMITED
mbotkinl 0:2cc6bb4d7fea 11
mbotkinl 0:2cc6bb4d7fea 12 All rights reserved.
mbotkinl 0:2cc6bb4d7fea 13 Redistribution and use in source and binary forms, with or without
mbotkinl 0:2cc6bb4d7fea 14 modification, are permitted provided that the following conditions are met:
mbotkinl 0:2cc6bb4d7fea 15 - Redistributions of source code must retain the above copyright
mbotkinl 0:2cc6bb4d7fea 16 notice, this list of conditions and the following disclaimer.
mbotkinl 0:2cc6bb4d7fea 17 - Redistributions in binary form must reproduce the above copyright
mbotkinl 0:2cc6bb4d7fea 18 notice, this list of conditions and the following disclaimer in the
mbotkinl 0:2cc6bb4d7fea 19 documentation and/or other materials provided with the distribution.
mbotkinl 0:2cc6bb4d7fea 20 - Neither the name of ARM nor the names of its contributors may be used
mbotkinl 0:2cc6bb4d7fea 21 to endorse or promote products derived from this software without
mbotkinl 0:2cc6bb4d7fea 22 specific prior written permission.
mbotkinl 0:2cc6bb4d7fea 23 *
mbotkinl 0:2cc6bb4d7fea 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbotkinl 0:2cc6bb4d7fea 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbotkinl 0:2cc6bb4d7fea 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
mbotkinl 0:2cc6bb4d7fea 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
mbotkinl 0:2cc6bb4d7fea 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
mbotkinl 0:2cc6bb4d7fea 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
mbotkinl 0:2cc6bb4d7fea 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mbotkinl 0:2cc6bb4d7fea 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mbotkinl 0:2cc6bb4d7fea 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
mbotkinl 0:2cc6bb4d7fea 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mbotkinl 0:2cc6bb4d7fea 34 POSSIBILITY OF SUCH DAMAGE.
mbotkinl 0:2cc6bb4d7fea 35 ---------------------------------------------------------------------------*/
mbotkinl 0:2cc6bb4d7fea 36
mbotkinl 0:2cc6bb4d7fea 37
mbotkinl 0:2cc6bb4d7fea 38 #ifndef __CORE_CAFUNC_H__
mbotkinl 0:2cc6bb4d7fea 39 #define __CORE_CAFUNC_H__
mbotkinl 0:2cc6bb4d7fea 40
mbotkinl 0:2cc6bb4d7fea 41
mbotkinl 0:2cc6bb4d7fea 42 /* ########################### Core Function Access ########################### */
mbotkinl 0:2cc6bb4d7fea 43 /** \ingroup CMSIS_Core_FunctionInterface
mbotkinl 0:2cc6bb4d7fea 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
mbotkinl 0:2cc6bb4d7fea 45 @{
mbotkinl 0:2cc6bb4d7fea 46 */
mbotkinl 0:2cc6bb4d7fea 47
mbotkinl 0:2cc6bb4d7fea 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
mbotkinl 0:2cc6bb4d7fea 49 /* ARM armcc specific functions */
mbotkinl 0:2cc6bb4d7fea 50
mbotkinl 0:2cc6bb4d7fea 51 #if (__ARMCC_VERSION < 400677)
mbotkinl 0:2cc6bb4d7fea 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
mbotkinl 0:2cc6bb4d7fea 53 #endif
mbotkinl 0:2cc6bb4d7fea 54
mbotkinl 0:2cc6bb4d7fea 55 #define MODE_USR 0x10
mbotkinl 0:2cc6bb4d7fea 56 #define MODE_FIQ 0x11
mbotkinl 0:2cc6bb4d7fea 57 #define MODE_IRQ 0x12
mbotkinl 0:2cc6bb4d7fea 58 #define MODE_SVC 0x13
mbotkinl 0:2cc6bb4d7fea 59 #define MODE_MON 0x16
mbotkinl 0:2cc6bb4d7fea 60 #define MODE_ABT 0x17
mbotkinl 0:2cc6bb4d7fea 61 #define MODE_HYP 0x1A
mbotkinl 0:2cc6bb4d7fea 62 #define MODE_UND 0x1B
mbotkinl 0:2cc6bb4d7fea 63 #define MODE_SYS 0x1F
mbotkinl 0:2cc6bb4d7fea 64
mbotkinl 0:2cc6bb4d7fea 65 /** \brief Get APSR Register
mbotkinl 0:2cc6bb4d7fea 66
mbotkinl 0:2cc6bb4d7fea 67 This function returns the content of the APSR Register.
mbotkinl 0:2cc6bb4d7fea 68
mbotkinl 0:2cc6bb4d7fea 69 \return APSR Register value
mbotkinl 0:2cc6bb4d7fea 70 */
mbotkinl 0:2cc6bb4d7fea 71 __STATIC_INLINE uint32_t __get_APSR(void)
mbotkinl 0:2cc6bb4d7fea 72 {
mbotkinl 0:2cc6bb4d7fea 73 register uint32_t __regAPSR __ASM("apsr");
mbotkinl 0:2cc6bb4d7fea 74 return(__regAPSR);
mbotkinl 0:2cc6bb4d7fea 75 }
mbotkinl 0:2cc6bb4d7fea 76
mbotkinl 0:2cc6bb4d7fea 77
mbotkinl 0:2cc6bb4d7fea 78 /** \brief Get CPSR Register
mbotkinl 0:2cc6bb4d7fea 79
mbotkinl 0:2cc6bb4d7fea 80 This function returns the content of the CPSR Register.
mbotkinl 0:2cc6bb4d7fea 81
mbotkinl 0:2cc6bb4d7fea 82 \return CPSR Register value
mbotkinl 0:2cc6bb4d7fea 83 */
mbotkinl 0:2cc6bb4d7fea 84 __STATIC_INLINE uint32_t __get_CPSR(void)
mbotkinl 0:2cc6bb4d7fea 85 {
mbotkinl 0:2cc6bb4d7fea 86 register uint32_t __regCPSR __ASM("cpsr");
mbotkinl 0:2cc6bb4d7fea 87 return(__regCPSR);
mbotkinl 0:2cc6bb4d7fea 88 }
mbotkinl 0:2cc6bb4d7fea 89
mbotkinl 0:2cc6bb4d7fea 90 /** \brief Set Stack Pointer
mbotkinl 0:2cc6bb4d7fea 91
mbotkinl 0:2cc6bb4d7fea 92 This function assigns the given value to the current stack pointer.
mbotkinl 0:2cc6bb4d7fea 93
mbotkinl 0:2cc6bb4d7fea 94 \param [in] topOfStack Stack Pointer value to set
mbotkinl 0:2cc6bb4d7fea 95 */
mbotkinl 0:2cc6bb4d7fea 96 register uint32_t __regSP __ASM("sp");
mbotkinl 0:2cc6bb4d7fea 97 __STATIC_INLINE void __set_SP(uint32_t topOfStack)
mbotkinl 0:2cc6bb4d7fea 98 {
mbotkinl 0:2cc6bb4d7fea 99 __regSP = topOfStack;
mbotkinl 0:2cc6bb4d7fea 100 }
mbotkinl 0:2cc6bb4d7fea 101
mbotkinl 0:2cc6bb4d7fea 102
mbotkinl 0:2cc6bb4d7fea 103 /** \brief Get link register
mbotkinl 0:2cc6bb4d7fea 104
mbotkinl 0:2cc6bb4d7fea 105 This function returns the value of the link register
mbotkinl 0:2cc6bb4d7fea 106
mbotkinl 0:2cc6bb4d7fea 107 \return Value of link register
mbotkinl 0:2cc6bb4d7fea 108 */
mbotkinl 0:2cc6bb4d7fea 109 register uint32_t __reglr __ASM("lr");
mbotkinl 0:2cc6bb4d7fea 110 __STATIC_INLINE uint32_t __get_LR(void)
mbotkinl 0:2cc6bb4d7fea 111 {
mbotkinl 0:2cc6bb4d7fea 112 return(__reglr);
mbotkinl 0:2cc6bb4d7fea 113 }
mbotkinl 0:2cc6bb4d7fea 114
mbotkinl 0:2cc6bb4d7fea 115 /** \brief Set link register
mbotkinl 0:2cc6bb4d7fea 116
mbotkinl 0:2cc6bb4d7fea 117 This function sets the value of the link register
mbotkinl 0:2cc6bb4d7fea 118
mbotkinl 0:2cc6bb4d7fea 119 \param [in] lr LR value to set
mbotkinl 0:2cc6bb4d7fea 120 */
mbotkinl 0:2cc6bb4d7fea 121 __STATIC_INLINE void __set_LR(uint32_t lr)
mbotkinl 0:2cc6bb4d7fea 122 {
mbotkinl 0:2cc6bb4d7fea 123 __reglr = lr;
mbotkinl 0:2cc6bb4d7fea 124 }
mbotkinl 0:2cc6bb4d7fea 125
mbotkinl 0:2cc6bb4d7fea 126 /** \brief Set Process Stack Pointer
mbotkinl 0:2cc6bb4d7fea 127
mbotkinl 0:2cc6bb4d7fea 128 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
mbotkinl 0:2cc6bb4d7fea 129
mbotkinl 0:2cc6bb4d7fea 130 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
mbotkinl 0:2cc6bb4d7fea 131 */
mbotkinl 0:2cc6bb4d7fea 132 __STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
mbotkinl 0:2cc6bb4d7fea 133 {
mbotkinl 0:2cc6bb4d7fea 134 ARM
mbotkinl 0:2cc6bb4d7fea 135 PRESERVE8
mbotkinl 0:2cc6bb4d7fea 136
mbotkinl 0:2cc6bb4d7fea 137 BIC R0, R0, #7 ;ensure stack is 8-byte aligned
mbotkinl 0:2cc6bb4d7fea 138 MRS R1, CPSR
mbotkinl 0:2cc6bb4d7fea 139 CPS #MODE_SYS ;no effect in USR mode
mbotkinl 0:2cc6bb4d7fea 140 MOV SP, R0
mbotkinl 0:2cc6bb4d7fea 141 MSR CPSR_c, R1 ;no effect in USR mode
mbotkinl 0:2cc6bb4d7fea 142 ISB
mbotkinl 0:2cc6bb4d7fea 143 BX LR
mbotkinl 0:2cc6bb4d7fea 144
mbotkinl 0:2cc6bb4d7fea 145 }
mbotkinl 0:2cc6bb4d7fea 146
mbotkinl 0:2cc6bb4d7fea 147 /** \brief Set User Mode
mbotkinl 0:2cc6bb4d7fea 148
mbotkinl 0:2cc6bb4d7fea 149 This function changes the processor state to User Mode
mbotkinl 0:2cc6bb4d7fea 150
mbotkinl 0:2cc6bb4d7fea 151 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
mbotkinl 0:2cc6bb4d7fea 152 */
mbotkinl 0:2cc6bb4d7fea 153 __STATIC_ASM void __set_CPS_USR(void)
mbotkinl 0:2cc6bb4d7fea 154 {
mbotkinl 0:2cc6bb4d7fea 155 ARM
mbotkinl 0:2cc6bb4d7fea 156
mbotkinl 0:2cc6bb4d7fea 157 CPS #MODE_USR
mbotkinl 0:2cc6bb4d7fea 158 BX LR
mbotkinl 0:2cc6bb4d7fea 159 }
mbotkinl 0:2cc6bb4d7fea 160
mbotkinl 0:2cc6bb4d7fea 161
mbotkinl 0:2cc6bb4d7fea 162 /** \brief Enable FIQ
mbotkinl 0:2cc6bb4d7fea 163
mbotkinl 0:2cc6bb4d7fea 164 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
mbotkinl 0:2cc6bb4d7fea 165 Can only be executed in Privileged modes.
mbotkinl 0:2cc6bb4d7fea 166 */
mbotkinl 0:2cc6bb4d7fea 167 #define __enable_fault_irq __enable_fiq
mbotkinl 0:2cc6bb4d7fea 168
mbotkinl 0:2cc6bb4d7fea 169
mbotkinl 0:2cc6bb4d7fea 170 /** \brief Disable FIQ
mbotkinl 0:2cc6bb4d7fea 171
mbotkinl 0:2cc6bb4d7fea 172 This function disables FIQ interrupts by setting the F-bit in the CPSR.
mbotkinl 0:2cc6bb4d7fea 173 Can only be executed in Privileged modes.
mbotkinl 0:2cc6bb4d7fea 174 */
mbotkinl 0:2cc6bb4d7fea 175 #define __disable_fault_irq __disable_fiq
mbotkinl 0:2cc6bb4d7fea 176
mbotkinl 0:2cc6bb4d7fea 177
mbotkinl 0:2cc6bb4d7fea 178 /** \brief Get FPSCR
mbotkinl 0:2cc6bb4d7fea 179
mbotkinl 0:2cc6bb4d7fea 180 This function returns the current value of the Floating Point Status/Control register.
mbotkinl 0:2cc6bb4d7fea 181
mbotkinl 0:2cc6bb4d7fea 182 \return Floating Point Status/Control register value
mbotkinl 0:2cc6bb4d7fea 183 */
mbotkinl 0:2cc6bb4d7fea 184 __STATIC_INLINE uint32_t __get_FPSCR(void)
mbotkinl 0:2cc6bb4d7fea 185 {
mbotkinl 0:2cc6bb4d7fea 186 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
mbotkinl 0:2cc6bb4d7fea 187 register uint32_t __regfpscr __ASM("fpscr");
mbotkinl 0:2cc6bb4d7fea 188 return(__regfpscr);
mbotkinl 0:2cc6bb4d7fea 189 #else
mbotkinl 0:2cc6bb4d7fea 190 return(0);
mbotkinl 0:2cc6bb4d7fea 191 #endif
mbotkinl 0:2cc6bb4d7fea 192 }
mbotkinl 0:2cc6bb4d7fea 193
mbotkinl 0:2cc6bb4d7fea 194
mbotkinl 0:2cc6bb4d7fea 195 /** \brief Set FPSCR
mbotkinl 0:2cc6bb4d7fea 196
mbotkinl 0:2cc6bb4d7fea 197 This function assigns the given value to the Floating Point Status/Control register.
mbotkinl 0:2cc6bb4d7fea 198
mbotkinl 0:2cc6bb4d7fea 199 \param [in] fpscr Floating Point Status/Control value to set
mbotkinl 0:2cc6bb4d7fea 200 */
mbotkinl 0:2cc6bb4d7fea 201 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
mbotkinl 0:2cc6bb4d7fea 202 {
mbotkinl 0:2cc6bb4d7fea 203 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
mbotkinl 0:2cc6bb4d7fea 204 register uint32_t __regfpscr __ASM("fpscr");
mbotkinl 0:2cc6bb4d7fea 205 __regfpscr = (fpscr);
mbotkinl 0:2cc6bb4d7fea 206 #endif
mbotkinl 0:2cc6bb4d7fea 207 }
mbotkinl 0:2cc6bb4d7fea 208
mbotkinl 0:2cc6bb4d7fea 209 /** \brief Get FPEXC
mbotkinl 0:2cc6bb4d7fea 210
mbotkinl 0:2cc6bb4d7fea 211 This function returns the current value of the Floating Point Exception Control register.
mbotkinl 0:2cc6bb4d7fea 212
mbotkinl 0:2cc6bb4d7fea 213 \return Floating Point Exception Control register value
mbotkinl 0:2cc6bb4d7fea 214 */
mbotkinl 0:2cc6bb4d7fea 215 __STATIC_INLINE uint32_t __get_FPEXC(void)
mbotkinl 0:2cc6bb4d7fea 216 {
mbotkinl 0:2cc6bb4d7fea 217 #if (__FPU_PRESENT == 1)
mbotkinl 0:2cc6bb4d7fea 218 register uint32_t __regfpexc __ASM("fpexc");
mbotkinl 0:2cc6bb4d7fea 219 return(__regfpexc);
mbotkinl 0:2cc6bb4d7fea 220 #else
mbotkinl 0:2cc6bb4d7fea 221 return(0);
mbotkinl 0:2cc6bb4d7fea 222 #endif
mbotkinl 0:2cc6bb4d7fea 223 }
mbotkinl 0:2cc6bb4d7fea 224
mbotkinl 0:2cc6bb4d7fea 225
mbotkinl 0:2cc6bb4d7fea 226 /** \brief Set FPEXC
mbotkinl 0:2cc6bb4d7fea 227
mbotkinl 0:2cc6bb4d7fea 228 This function assigns the given value to the Floating Point Exception Control register.
mbotkinl 0:2cc6bb4d7fea 229
mbotkinl 0:2cc6bb4d7fea 230 \param [in] fpscr Floating Point Exception Control value to set
mbotkinl 0:2cc6bb4d7fea 231 */
mbotkinl 0:2cc6bb4d7fea 232 __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
mbotkinl 0:2cc6bb4d7fea 233 {
mbotkinl 0:2cc6bb4d7fea 234 #if (__FPU_PRESENT == 1)
mbotkinl 0:2cc6bb4d7fea 235 register uint32_t __regfpexc __ASM("fpexc");
mbotkinl 0:2cc6bb4d7fea 236 __regfpexc = (fpexc);
mbotkinl 0:2cc6bb4d7fea 237 #endif
mbotkinl 0:2cc6bb4d7fea 238 }
mbotkinl 0:2cc6bb4d7fea 239
mbotkinl 0:2cc6bb4d7fea 240 /** \brief Get CPACR
mbotkinl 0:2cc6bb4d7fea 241
mbotkinl 0:2cc6bb4d7fea 242 This function returns the current value of the Coprocessor Access Control register.
mbotkinl 0:2cc6bb4d7fea 243
mbotkinl 0:2cc6bb4d7fea 244 \return Coprocessor Access Control register value
mbotkinl 0:2cc6bb4d7fea 245 */
mbotkinl 0:2cc6bb4d7fea 246 __STATIC_INLINE uint32_t __get_CPACR(void)
mbotkinl 0:2cc6bb4d7fea 247 {
mbotkinl 0:2cc6bb4d7fea 248 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
mbotkinl 0:2cc6bb4d7fea 249 return __regCPACR;
mbotkinl 0:2cc6bb4d7fea 250 }
mbotkinl 0:2cc6bb4d7fea 251
mbotkinl 0:2cc6bb4d7fea 252 /** \brief Set CPACR
mbotkinl 0:2cc6bb4d7fea 253
mbotkinl 0:2cc6bb4d7fea 254 This function assigns the given value to the Coprocessor Access Control register.
mbotkinl 0:2cc6bb4d7fea 255
mbotkinl 0:2cc6bb4d7fea 256 \param [in] cpacr Coporcessor Acccess Control value to set
mbotkinl 0:2cc6bb4d7fea 257 */
mbotkinl 0:2cc6bb4d7fea 258 __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
mbotkinl 0:2cc6bb4d7fea 259 {
mbotkinl 0:2cc6bb4d7fea 260 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
mbotkinl 0:2cc6bb4d7fea 261 __regCPACR = cpacr;
mbotkinl 0:2cc6bb4d7fea 262 __ISB();
mbotkinl 0:2cc6bb4d7fea 263 }
mbotkinl 0:2cc6bb4d7fea 264
mbotkinl 0:2cc6bb4d7fea 265 /** \brief Get CBAR
mbotkinl 0:2cc6bb4d7fea 266
mbotkinl 0:2cc6bb4d7fea 267 This function returns the value of the Configuration Base Address register.
mbotkinl 0:2cc6bb4d7fea 268
mbotkinl 0:2cc6bb4d7fea 269 \return Configuration Base Address register value
mbotkinl 0:2cc6bb4d7fea 270 */
mbotkinl 0:2cc6bb4d7fea 271 __STATIC_INLINE uint32_t __get_CBAR() {
mbotkinl 0:2cc6bb4d7fea 272 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
mbotkinl 0:2cc6bb4d7fea 273 return(__regCBAR);
mbotkinl 0:2cc6bb4d7fea 274 }
mbotkinl 0:2cc6bb4d7fea 275
mbotkinl 0:2cc6bb4d7fea 276 /** \brief Get TTBR0
mbotkinl 0:2cc6bb4d7fea 277
mbotkinl 0:2cc6bb4d7fea 278 This function returns the value of the Configuration Base Address register.
mbotkinl 0:2cc6bb4d7fea 279
mbotkinl 0:2cc6bb4d7fea 280 \return Translation Table Base Register 0 value
mbotkinl 0:2cc6bb4d7fea 281 */
mbotkinl 0:2cc6bb4d7fea 282 __STATIC_INLINE uint32_t __get_TTBR0() {
mbotkinl 0:2cc6bb4d7fea 283 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
mbotkinl 0:2cc6bb4d7fea 284 return(__regTTBR0);
mbotkinl 0:2cc6bb4d7fea 285 }
mbotkinl 0:2cc6bb4d7fea 286
mbotkinl 0:2cc6bb4d7fea 287 /** \brief Set TTBR0
mbotkinl 0:2cc6bb4d7fea 288
mbotkinl 0:2cc6bb4d7fea 289 This function assigns the given value to the Coprocessor Access Control register.
mbotkinl 0:2cc6bb4d7fea 290
mbotkinl 0:2cc6bb4d7fea 291 \param [in] ttbr0 Translation Table Base Register 0 value to set
mbotkinl 0:2cc6bb4d7fea 292 */
mbotkinl 0:2cc6bb4d7fea 293 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
mbotkinl 0:2cc6bb4d7fea 294 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
mbotkinl 0:2cc6bb4d7fea 295 __regTTBR0 = ttbr0;
mbotkinl 0:2cc6bb4d7fea 296 __ISB();
mbotkinl 0:2cc6bb4d7fea 297 }
mbotkinl 0:2cc6bb4d7fea 298
mbotkinl 0:2cc6bb4d7fea 299 /** \brief Get DACR
mbotkinl 0:2cc6bb4d7fea 300
mbotkinl 0:2cc6bb4d7fea 301 This function returns the value of the Domain Access Control Register.
mbotkinl 0:2cc6bb4d7fea 302
mbotkinl 0:2cc6bb4d7fea 303 \return Domain Access Control Register value
mbotkinl 0:2cc6bb4d7fea 304 */
mbotkinl 0:2cc6bb4d7fea 305 __STATIC_INLINE uint32_t __get_DACR() {
mbotkinl 0:2cc6bb4d7fea 306 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
mbotkinl 0:2cc6bb4d7fea 307 return(__regDACR);
mbotkinl 0:2cc6bb4d7fea 308 }
mbotkinl 0:2cc6bb4d7fea 309
mbotkinl 0:2cc6bb4d7fea 310 /** \brief Set DACR
mbotkinl 0:2cc6bb4d7fea 311
mbotkinl 0:2cc6bb4d7fea 312 This function assigns the given value to the Coprocessor Access Control register.
mbotkinl 0:2cc6bb4d7fea 313
mbotkinl 0:2cc6bb4d7fea 314 \param [in] dacr Domain Access Control Register value to set
mbotkinl 0:2cc6bb4d7fea 315 */
mbotkinl 0:2cc6bb4d7fea 316 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
mbotkinl 0:2cc6bb4d7fea 317 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
mbotkinl 0:2cc6bb4d7fea 318 __regDACR = dacr;
mbotkinl 0:2cc6bb4d7fea 319 __ISB();
mbotkinl 0:2cc6bb4d7fea 320 }
mbotkinl 0:2cc6bb4d7fea 321
mbotkinl 0:2cc6bb4d7fea 322 /******************************** Cache and BTAC enable ****************************************************/
mbotkinl 0:2cc6bb4d7fea 323
mbotkinl 0:2cc6bb4d7fea 324 /** \brief Set SCTLR
mbotkinl 0:2cc6bb4d7fea 325
mbotkinl 0:2cc6bb4d7fea 326 This function assigns the given value to the System Control Register.
mbotkinl 0:2cc6bb4d7fea 327
mbotkinl 0:2cc6bb4d7fea 328 \param [in] sctlr System Control Register, value to set
mbotkinl 0:2cc6bb4d7fea 329 */
mbotkinl 0:2cc6bb4d7fea 330 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
mbotkinl 0:2cc6bb4d7fea 331 {
mbotkinl 0:2cc6bb4d7fea 332 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
mbotkinl 0:2cc6bb4d7fea 333 __regSCTLR = sctlr;
mbotkinl 0:2cc6bb4d7fea 334 }
mbotkinl 0:2cc6bb4d7fea 335
mbotkinl 0:2cc6bb4d7fea 336 /** \brief Get SCTLR
mbotkinl 0:2cc6bb4d7fea 337
mbotkinl 0:2cc6bb4d7fea 338 This function returns the value of the System Control Register.
mbotkinl 0:2cc6bb4d7fea 339
mbotkinl 0:2cc6bb4d7fea 340 \return System Control Register value
mbotkinl 0:2cc6bb4d7fea 341 */
mbotkinl 0:2cc6bb4d7fea 342 __STATIC_INLINE uint32_t __get_SCTLR() {
mbotkinl 0:2cc6bb4d7fea 343 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
mbotkinl 0:2cc6bb4d7fea 344 return(__regSCTLR);
mbotkinl 0:2cc6bb4d7fea 345 }
mbotkinl 0:2cc6bb4d7fea 346
mbotkinl 0:2cc6bb4d7fea 347 /** \brief Enable Caches
mbotkinl 0:2cc6bb4d7fea 348
mbotkinl 0:2cc6bb4d7fea 349 Enable Caches
mbotkinl 0:2cc6bb4d7fea 350 */
mbotkinl 0:2cc6bb4d7fea 351 __STATIC_INLINE void __enable_caches(void) {
mbotkinl 0:2cc6bb4d7fea 352 // Set I bit 12 to enable I Cache
mbotkinl 0:2cc6bb4d7fea 353 // Set C bit 2 to enable D Cache
mbotkinl 0:2cc6bb4d7fea 354 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
mbotkinl 0:2cc6bb4d7fea 355 }
mbotkinl 0:2cc6bb4d7fea 356
mbotkinl 0:2cc6bb4d7fea 357 /** \brief Disable Caches
mbotkinl 0:2cc6bb4d7fea 358
mbotkinl 0:2cc6bb4d7fea 359 Disable Caches
mbotkinl 0:2cc6bb4d7fea 360 */
mbotkinl 0:2cc6bb4d7fea 361 __STATIC_INLINE void __disable_caches(void) {
mbotkinl 0:2cc6bb4d7fea 362 // Clear I bit 12 to disable I Cache
mbotkinl 0:2cc6bb4d7fea 363 // Clear C bit 2 to disable D Cache
mbotkinl 0:2cc6bb4d7fea 364 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
mbotkinl 0:2cc6bb4d7fea 365 __ISB();
mbotkinl 0:2cc6bb4d7fea 366 }
mbotkinl 0:2cc6bb4d7fea 367
mbotkinl 0:2cc6bb4d7fea 368 /** \brief Enable BTAC
mbotkinl 0:2cc6bb4d7fea 369
mbotkinl 0:2cc6bb4d7fea 370 Enable BTAC
mbotkinl 0:2cc6bb4d7fea 371 */
mbotkinl 0:2cc6bb4d7fea 372 __STATIC_INLINE void __enable_btac(void) {
mbotkinl 0:2cc6bb4d7fea 373 // Set Z bit 11 to enable branch prediction
mbotkinl 0:2cc6bb4d7fea 374 __set_SCTLR( __get_SCTLR() | (1 << 11));
mbotkinl 0:2cc6bb4d7fea 375 __ISB();
mbotkinl 0:2cc6bb4d7fea 376 }
mbotkinl 0:2cc6bb4d7fea 377
mbotkinl 0:2cc6bb4d7fea 378 /** \brief Disable BTAC
mbotkinl 0:2cc6bb4d7fea 379
mbotkinl 0:2cc6bb4d7fea 380 Disable BTAC
mbotkinl 0:2cc6bb4d7fea 381 */
mbotkinl 0:2cc6bb4d7fea 382 __STATIC_INLINE void __disable_btac(void) {
mbotkinl 0:2cc6bb4d7fea 383 // Clear Z bit 11 to disable branch prediction
mbotkinl 0:2cc6bb4d7fea 384 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
mbotkinl 0:2cc6bb4d7fea 385 }
mbotkinl 0:2cc6bb4d7fea 386
mbotkinl 0:2cc6bb4d7fea 387
mbotkinl 0:2cc6bb4d7fea 388 /** \brief Enable MMU
mbotkinl 0:2cc6bb4d7fea 389
mbotkinl 0:2cc6bb4d7fea 390 Enable MMU
mbotkinl 0:2cc6bb4d7fea 391 */
mbotkinl 0:2cc6bb4d7fea 392 __STATIC_INLINE void __enable_mmu(void) {
mbotkinl 0:2cc6bb4d7fea 393 // Set M bit 0 to enable the MMU
mbotkinl 0:2cc6bb4d7fea 394 // Set AFE bit to enable simplified access permissions model
mbotkinl 0:2cc6bb4d7fea 395 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
mbotkinl 0:2cc6bb4d7fea 396 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
mbotkinl 0:2cc6bb4d7fea 397 __ISB();
mbotkinl 0:2cc6bb4d7fea 398 }
mbotkinl 0:2cc6bb4d7fea 399
mbotkinl 0:2cc6bb4d7fea 400 /** \brief Enable MMU
mbotkinl 0:2cc6bb4d7fea 401
mbotkinl 0:2cc6bb4d7fea 402 Enable MMU
mbotkinl 0:2cc6bb4d7fea 403 */
mbotkinl 0:2cc6bb4d7fea 404 __STATIC_INLINE void __disable_mmu(void) {
mbotkinl 0:2cc6bb4d7fea 405 // Clear M bit 0 to disable the MMU
mbotkinl 0:2cc6bb4d7fea 406 __set_SCTLR( __get_SCTLR() & ~1);
mbotkinl 0:2cc6bb4d7fea 407 __ISB();
mbotkinl 0:2cc6bb4d7fea 408 }
mbotkinl 0:2cc6bb4d7fea 409
mbotkinl 0:2cc6bb4d7fea 410 /******************************** TLB maintenance operations ************************************************/
mbotkinl 0:2cc6bb4d7fea 411 /** \brief Invalidate the whole tlb
mbotkinl 0:2cc6bb4d7fea 412
mbotkinl 0:2cc6bb4d7fea 413 TLBIALL. Invalidate the whole tlb
mbotkinl 0:2cc6bb4d7fea 414 */
mbotkinl 0:2cc6bb4d7fea 415
mbotkinl 0:2cc6bb4d7fea 416 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
mbotkinl 0:2cc6bb4d7fea 417 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
mbotkinl 0:2cc6bb4d7fea 418 __TLBIALL = 0;
mbotkinl 0:2cc6bb4d7fea 419 __DSB();
mbotkinl 0:2cc6bb4d7fea 420 __ISB();
mbotkinl 0:2cc6bb4d7fea 421 }
mbotkinl 0:2cc6bb4d7fea 422
mbotkinl 0:2cc6bb4d7fea 423 /******************************** BTB maintenance operations ************************************************/
mbotkinl 0:2cc6bb4d7fea 424 /** \brief Invalidate entire branch predictor array
mbotkinl 0:2cc6bb4d7fea 425
mbotkinl 0:2cc6bb4d7fea 426 BPIALL. Branch Predictor Invalidate All.
mbotkinl 0:2cc6bb4d7fea 427 */
mbotkinl 0:2cc6bb4d7fea 428
mbotkinl 0:2cc6bb4d7fea 429 __STATIC_INLINE void __v7_inv_btac(void) {
mbotkinl 0:2cc6bb4d7fea 430 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
mbotkinl 0:2cc6bb4d7fea 431 __BPIALL = 0;
mbotkinl 0:2cc6bb4d7fea 432 __DSB(); //ensure completion of the invalidation
mbotkinl 0:2cc6bb4d7fea 433 __ISB(); //ensure instruction fetch path sees new state
mbotkinl 0:2cc6bb4d7fea 434 }
mbotkinl 0:2cc6bb4d7fea 435
mbotkinl 0:2cc6bb4d7fea 436
mbotkinl 0:2cc6bb4d7fea 437 /******************************** L1 cache operations ******************************************************/
mbotkinl 0:2cc6bb4d7fea 438
mbotkinl 0:2cc6bb4d7fea 439 /** \brief Invalidate the whole I$
mbotkinl 0:2cc6bb4d7fea 440
mbotkinl 0:2cc6bb4d7fea 441 ICIALLU. Instruction Cache Invalidate All to PoU
mbotkinl 0:2cc6bb4d7fea 442 */
mbotkinl 0:2cc6bb4d7fea 443 __STATIC_INLINE void __v7_inv_icache_all(void) {
mbotkinl 0:2cc6bb4d7fea 444 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
mbotkinl 0:2cc6bb4d7fea 445 __ICIALLU = 0;
mbotkinl 0:2cc6bb4d7fea 446 __DSB(); //ensure completion of the invalidation
mbotkinl 0:2cc6bb4d7fea 447 __ISB(); //ensure instruction fetch path sees new I cache state
mbotkinl 0:2cc6bb4d7fea 448 }
mbotkinl 0:2cc6bb4d7fea 449
mbotkinl 0:2cc6bb4d7fea 450 /** \brief Clean D$ by MVA
mbotkinl 0:2cc6bb4d7fea 451
mbotkinl 0:2cc6bb4d7fea 452 DCCMVAC. Data cache clean by MVA to PoC
mbotkinl 0:2cc6bb4d7fea 453 */
mbotkinl 0:2cc6bb4d7fea 454 __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
mbotkinl 0:2cc6bb4d7fea 455 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
mbotkinl 0:2cc6bb4d7fea 456 __DCCMVAC = (uint32_t)va;
mbotkinl 0:2cc6bb4d7fea 457 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
mbotkinl 0:2cc6bb4d7fea 458 }
mbotkinl 0:2cc6bb4d7fea 459
mbotkinl 0:2cc6bb4d7fea 460 /** \brief Invalidate D$ by MVA
mbotkinl 0:2cc6bb4d7fea 461
mbotkinl 0:2cc6bb4d7fea 462 DCIMVAC. Data cache invalidate by MVA to PoC
mbotkinl 0:2cc6bb4d7fea 463 */
mbotkinl 0:2cc6bb4d7fea 464 __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
mbotkinl 0:2cc6bb4d7fea 465 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
mbotkinl 0:2cc6bb4d7fea 466 __DCIMVAC = (uint32_t)va;
mbotkinl 0:2cc6bb4d7fea 467 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
mbotkinl 0:2cc6bb4d7fea 468 }
mbotkinl 0:2cc6bb4d7fea 469
mbotkinl 0:2cc6bb4d7fea 470 /** \brief Clean and Invalidate D$ by MVA
mbotkinl 0:2cc6bb4d7fea 471
mbotkinl 0:2cc6bb4d7fea 472 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
mbotkinl 0:2cc6bb4d7fea 473 */
mbotkinl 0:2cc6bb4d7fea 474 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
mbotkinl 0:2cc6bb4d7fea 475 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
mbotkinl 0:2cc6bb4d7fea 476 __DCCIMVAC = (uint32_t)va;
mbotkinl 0:2cc6bb4d7fea 477 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
mbotkinl 0:2cc6bb4d7fea 478 }
mbotkinl 0:2cc6bb4d7fea 479
mbotkinl 0:2cc6bb4d7fea 480 /** \brief
mbotkinl 0:2cc6bb4d7fea 481 * Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
mbotkinl 0:2cc6bb4d7fea 482 */
mbotkinl 0:2cc6bb4d7fea 483 #pragma push
mbotkinl 0:2cc6bb4d7fea 484 #pragma arm
mbotkinl 0:2cc6bb4d7fea 485 __STATIC_ASM void __v7_all_cache(uint32_t op) {
mbotkinl 0:2cc6bb4d7fea 486 ARM
mbotkinl 0:2cc6bb4d7fea 487
mbotkinl 0:2cc6bb4d7fea 488 PUSH {R4-R11}
mbotkinl 0:2cc6bb4d7fea 489
mbotkinl 0:2cc6bb4d7fea 490 MRC p15, 1, R6, c0, c0, 1 // Read CLIDR
mbotkinl 0:2cc6bb4d7fea 491 ANDS R3, R6, #0x07000000 // Extract coherency level
mbotkinl 0:2cc6bb4d7fea 492 MOV R3, R3, LSR #23 // Total cache levels << 1
mbotkinl 0:2cc6bb4d7fea 493 BEQ Finished // If 0, no need to clean
mbotkinl 0:2cc6bb4d7fea 494
mbotkinl 0:2cc6bb4d7fea 495 MOV R10, #0 // R10 holds current cache level << 1
mbotkinl 0:2cc6bb4d7fea 496 Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position
mbotkinl 0:2cc6bb4d7fea 497 MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level
mbotkinl 0:2cc6bb4d7fea 498 AND R1, R1, #7 // Isolate those lower 3 bits
mbotkinl 0:2cc6bb4d7fea 499 CMP R1, #2
mbotkinl 0:2cc6bb4d7fea 500 BLT Skip // No cache or only instruction cache at this level
mbotkinl 0:2cc6bb4d7fea 501
mbotkinl 0:2cc6bb4d7fea 502 MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register
mbotkinl 0:2cc6bb4d7fea 503 ISB // ISB to sync the change to the CacheSizeID reg
mbotkinl 0:2cc6bb4d7fea 504 MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register
mbotkinl 0:2cc6bb4d7fea 505 AND R2, R1, #7 // Extract the line length field
mbotkinl 0:2cc6bb4d7fea 506 ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes)
mbotkinl 0:2cc6bb4d7fea 507 LDR R4, =0x3FF
mbotkinl 0:2cc6bb4d7fea 508 ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
mbotkinl 0:2cc6bb4d7fea 509 CLZ R5, R4 // R5 is the bit position of the way size increment
mbotkinl 0:2cc6bb4d7fea 510 LDR R7, =0x7FFF
mbotkinl 0:2cc6bb4d7fea 511 ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned)
mbotkinl 0:2cc6bb4d7fea 512
mbotkinl 0:2cc6bb4d7fea 513 Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned)
mbotkinl 0:2cc6bb4d7fea 514
mbotkinl 0:2cc6bb4d7fea 515 Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11
mbotkinl 0:2cc6bb4d7fea 516 ORR R11, R11, R7, LSL R2 // Factor in the Set number
mbotkinl 0:2cc6bb4d7fea 517 CMP R0, #0
mbotkinl 0:2cc6bb4d7fea 518 BNE Dccsw
mbotkinl 0:2cc6bb4d7fea 519 MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way
mbotkinl 0:2cc6bb4d7fea 520 B cont
mbotkinl 0:2cc6bb4d7fea 521 Dccsw CMP R0, #1
mbotkinl 0:2cc6bb4d7fea 522 BNE Dccisw
mbotkinl 0:2cc6bb4d7fea 523 MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
mbotkinl 0:2cc6bb4d7fea 524 B cont
mbotkinl 0:2cc6bb4d7fea 525 Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW, Clean and Invalidate by Set/Way
mbotkinl 0:2cc6bb4d7fea 526 cont SUBS R9, R9, #1 // Decrement the Way number
mbotkinl 0:2cc6bb4d7fea 527 BGE Loop3
mbotkinl 0:2cc6bb4d7fea 528 SUBS R7, R7, #1 // Decrement the Set number
mbotkinl 0:2cc6bb4d7fea 529 BGE Loop2
mbotkinl 0:2cc6bb4d7fea 530 Skip ADD R10, R10, #2 // increment the cache number
mbotkinl 0:2cc6bb4d7fea 531 CMP R3, R10
mbotkinl 0:2cc6bb4d7fea 532 BGT Loop1
mbotkinl 0:2cc6bb4d7fea 533
mbotkinl 0:2cc6bb4d7fea 534 Finished
mbotkinl 0:2cc6bb4d7fea 535 DSB
mbotkinl 0:2cc6bb4d7fea 536 POP {R4-R11}
mbotkinl 0:2cc6bb4d7fea 537 BX lr
mbotkinl 0:2cc6bb4d7fea 538
mbotkinl 0:2cc6bb4d7fea 539 }
mbotkinl 0:2cc6bb4d7fea 540 #pragma pop
mbotkinl 0:2cc6bb4d7fea 541
mbotkinl 0:2cc6bb4d7fea 542 /** \brief __v7_all_cache - helper function
mbotkinl 0:2cc6bb4d7fea 543
mbotkinl 0:2cc6bb4d7fea 544 */
mbotkinl 0:2cc6bb4d7fea 545
mbotkinl 0:2cc6bb4d7fea 546 /** \brief Invalidate the whole D$
mbotkinl 0:2cc6bb4d7fea 547
mbotkinl 0:2cc6bb4d7fea 548 DCISW. Invalidate by Set/Way
mbotkinl 0:2cc6bb4d7fea 549 */
mbotkinl 0:2cc6bb4d7fea 550
mbotkinl 0:2cc6bb4d7fea 551 __STATIC_INLINE void __v7_inv_dcache_all(void) {
mbotkinl 0:2cc6bb4d7fea 552 __v7_all_cache(0);
mbotkinl 0:2cc6bb4d7fea 553 }
mbotkinl 0:2cc6bb4d7fea 554
mbotkinl 0:2cc6bb4d7fea 555 /** \brief Clean the whole D$
mbotkinl 0:2cc6bb4d7fea 556
mbotkinl 0:2cc6bb4d7fea 557 DCCSW. Clean by Set/Way
mbotkinl 0:2cc6bb4d7fea 558 */
mbotkinl 0:2cc6bb4d7fea 559
mbotkinl 0:2cc6bb4d7fea 560 __STATIC_INLINE void __v7_clean_dcache_all(void) {
mbotkinl 0:2cc6bb4d7fea 561 __v7_all_cache(1);
mbotkinl 0:2cc6bb4d7fea 562 }
mbotkinl 0:2cc6bb4d7fea 563
mbotkinl 0:2cc6bb4d7fea 564 /** \brief Clean and invalidate the whole D$
mbotkinl 0:2cc6bb4d7fea 565
mbotkinl 0:2cc6bb4d7fea 566 DCCISW. Clean and Invalidate by Set/Way
mbotkinl 0:2cc6bb4d7fea 567 */
mbotkinl 0:2cc6bb4d7fea 568
mbotkinl 0:2cc6bb4d7fea 569 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
mbotkinl 0:2cc6bb4d7fea 570 __v7_all_cache(2);
mbotkinl 0:2cc6bb4d7fea 571 }
mbotkinl 0:2cc6bb4d7fea 572
mbotkinl 0:2cc6bb4d7fea 573 #include "core_ca_mmu.h"
mbotkinl 0:2cc6bb4d7fea 574
mbotkinl 0:2cc6bb4d7fea 575 #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
mbotkinl 0:2cc6bb4d7fea 576
mbotkinl 0:2cc6bb4d7fea 577 #error IAR Compiler support not implemented for Cortex-A
mbotkinl 0:2cc6bb4d7fea 578
mbotkinl 0:2cc6bb4d7fea 579 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
mbotkinl 0:2cc6bb4d7fea 580
mbotkinl 0:2cc6bb4d7fea 581 //#error GNU Compiler support not implemented for Cortex-A
mbotkinl 0:2cc6bb4d7fea 582
mbotkinl 0:2cc6bb4d7fea 583 #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
mbotkinl 0:2cc6bb4d7fea 584
mbotkinl 0:2cc6bb4d7fea 585 #error TASKING Compiler support not implemented for Cortex-A
mbotkinl 0:2cc6bb4d7fea 586
mbotkinl 0:2cc6bb4d7fea 587 #endif
mbotkinl 0:2cc6bb4d7fea 588
mbotkinl 0:2cc6bb4d7fea 589 /*@} end of CMSIS_Core_RegAccFunctions */
mbotkinl 0:2cc6bb4d7fea 590
mbotkinl 0:2cc6bb4d7fea 591
mbotkinl 0:2cc6bb4d7fea 592 #endif /* __CORE_CAFUNC_H__ */