Diff: TARGET_NUCLEO_L073RZ/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device/stm32l0xx.h

Revision:

130:d75b3fe1f5cb

Parent:

128:9bcdf88f62b0

diff -r 0ab6a29f35bf -r d75b3fe1f5cb TARGET_NUCLEO_L073RZ/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device/stm32l0xx.h
--- a/TARGET_NUCLEO_L073RZ/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device/stm32l0xx.h	Tue Nov 08 17:28:34 2016 +0000
+++ b/TARGET_NUCLEO_L073RZ/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device/stm32l0xx.h	Thu Nov 24 11:01:25 2016 +0000
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32l0xx.h
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    01-October-2015
+  * @version V1.7.0
+  * @date    31-May-2016
   * @brief   CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. 
   *          This file contains all the peripheral register's definitions, bits 
   *          definitions and memory mapping for STM32L0xx devices.            
@@ -12,8 +12,8 @@
   *          is using in the C source code, usually in main.c. This file contains:
   *           - Configuration section that allows to select:
   *              - The device used in the target application
-  *              - To use or not the peripheral’s drivers in application code(i.e. 
-  *                code will be based on direct access to peripheral’s registers 
+  *              - To use or not the peripheral's drivers in application code(i.e. 
+  *                code will be based on direct access to peripheral's registers 
   *                rather than drivers API), this option is controlled by 
   *                "#define USE_HAL_DRIVER"
   *  
@@ -95,7 +95,7 @@
   /* #define STM32L063xx */   /*!< STM32L063C8, STM32L063R8 */ 
   /* #define STM32L071xx */   /*!< */
   /* #define STM32L072xx */   /*!< */
-#define STM32L073xx           /*!< STM32L073V8, STM32L073VB, STM32L073RB, STM32L073VZ, STM32L073RZ Devices */
+  #define STM32L073xx   /*!< STM32L073V8, STM32L073VB, STM32L073RB, STM32L073VZ, STM32L073RZ Devices */
   /* #define STM32L081xx */   /*!< */
   /* #define STM32L082xx */   /*!< */
   /* #define STM32L083xx */   /*!< */ 
@@ -114,16 +114,16 @@
 #endif /* USE_HAL_DRIVER */
 
 /**
-  * @brief CMSIS Device version number V1.2.0RC1
+  * @brief CMSIS Device version number V1.7.0
   */
-#define __STM32L0xx_CMSIS_DEVICE_VERSION_MAIN   (0x01) /*!< [31:24] main version */                                  
-#define __STM32L0xx_CMSIS_DEVICE_VERSION_SUB1   (0x03) /*!< [23:16] sub1 version */
-#define __STM32L0xx_CMSIS_DEVICE_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
-#define __STM32L0xx_CMSIS_DEVICE_VERSION_RC     (0x01) /*!< [7:0]  release candidate */
-#define __STM32L0xx_CMSIS_DEVICE_VERSION        ((__CMSIS_DEVICE_VERSION_MAIN     << 24)\
-                                      |(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
-                                      |(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\
-                                      |(__CMSIS_DEVICE_HAL_VERSION_RC))
+#define __STM32L0xx_CMSIS_VERSION_MAIN   (0x01) /*!< [31:24] main version */
+#define __STM32L0xx_CMSIS_VERSION_SUB1   (0x07) /*!< [23:16] sub1 version */
+#define __STM32L0xx_CMSIS_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
+#define __STM32L0xx_CMSIS_VERSION_RC     (0x00) /*!< [7:0]  release candidate */
+#define __STM32L0xx_CMSIS_VERSION        ((__STM32L0xx_CMSIS_VERSION_MAIN     << 24)\
+                                      |(__STM32L0xx_CMSIS_VERSION_SUB1 << 16)\
+                                      |(__STM32L0xx_CMSIS_VERSION_SUB2 << 8 )\
+                                      |(__STM32L0xx_CMSIS_VERSION_RC))
                                              
 /**
   * @}
@@ -216,8 +216,6 @@
 
 #define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
 
-#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL)))
-
 /**
   * @}
   */