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Dependents: hello SerialTestv11 SerialTestv12 Sierpinski ... more
Diff: TARGET_NUCLEO_F412ZG/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cec.h
- Revision:
- 145:64910690c574
- Parent:
- 132:9baf128c2fab
diff -r 0f02307a0877 -r 64910690c574 TARGET_NUCLEO_F412ZG/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cec.h
--- a/TARGET_NUCLEO_F412ZG/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cec.h Thu Jun 08 14:53:05 2017 +0100
+++ b/TARGET_NUCLEO_F412ZG/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cec.h Wed Jun 21 17:31:38 2017 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_cec.h
* @author MCD Application Team
- * @version V1.5.0
- * @date 06-May-2016
+ * @version V1.7.1
+ * @date 14-April-2017
* @brief Header file of CEC HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -220,7 +220,7 @@
/** @defgroup CEC_Error_Code CEC Error Code
* @{
*/
-#define HAL_CEC_ERROR_NONE ((uint32_t)0x00000000U)/*!< no error */
+#define HAL_CEC_ERROR_NONE 0x00000000U /*!< no error */
#define HAL_CEC_ERROR_RXOVR CEC_ISR_RXOVR /*!< CEC Rx-Overrun */
#define HAL_CEC_ERROR_BRE CEC_ISR_BRE /*!< CEC Rx Bit Rising Error */
#define HAL_CEC_ERROR_SBPE CEC_ISR_SBPE /*!< CEC Rx Short Bit period Error */
@@ -237,14 +237,14 @@
/** @defgroup CEC_Signal_Free_Time CEC Signal Free Time setting parameter
* @{
*/
-#define CEC_DEFAULT_SFT ((uint32_t)0x00000000U)
-#define CEC_0_5_BITPERIOD_SFT ((uint32_t)0x00000001U)
-#define CEC_1_5_BITPERIOD_SFT ((uint32_t)0x00000002U)
-#define CEC_2_5_BITPERIOD_SFT ((uint32_t)0x00000003U)
-#define CEC_3_5_BITPERIOD_SFT ((uint32_t)0x00000004U)
-#define CEC_4_5_BITPERIOD_SFT ((uint32_t)0x00000005U)
-#define CEC_5_5_BITPERIOD_SFT ((uint32_t)0x00000006U)
-#define CEC_6_5_BITPERIOD_SFT ((uint32_t)0x00000007U)
+#define CEC_DEFAULT_SFT 0x00000000U
+#define CEC_0_5_BITPERIOD_SFT 0x00000001U
+#define CEC_1_5_BITPERIOD_SFT 0x00000002U
+#define CEC_2_5_BITPERIOD_SFT 0x00000003U
+#define CEC_3_5_BITPERIOD_SFT 0x00000004U
+#define CEC_4_5_BITPERIOD_SFT 0x00000005U
+#define CEC_5_5_BITPERIOD_SFT 0x00000006U
+#define CEC_6_5_BITPERIOD_SFT 0x00000007U
/**
* @}
*/
@@ -252,7 +252,7 @@
/** @defgroup CEC_Tolerance CEC Receiver Tolerance
* @{
*/
-#define CEC_STANDARD_TOLERANCE ((uint32_t)0x00000000U)
+#define CEC_STANDARD_TOLERANCE 0x00000000U
#define CEC_EXTENDED_TOLERANCE ((uint32_t)CEC_CFGR_RXTOL)
/**
* @}
@@ -261,7 +261,7 @@
/** @defgroup CEC_BRERxStop CEC Reception Stop on Error
* @{
*/
-#define CEC_NO_RX_STOP_ON_BRE ((uint32_t)0x00000000U)
+#define CEC_NO_RX_STOP_ON_BRE 0x00000000U
#define CEC_RX_STOP_ON_BRE ((uint32_t)CEC_CFGR_BRESTP)
/**
* @}
@@ -270,7 +270,7 @@
/** @defgroup CEC_BREErrorBitGen CEC Error Bit Generation if Bit Rise Error reported
* @{
*/
-#define CEC_BRE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000U)
+#define CEC_BRE_ERRORBIT_NO_GENERATION 0x00000000U
#define CEC_BRE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BREGEN)
/**
* @}
@@ -279,7 +279,7 @@
/** @defgroup CEC_LBPEErrorBitGen CEC Error Bit Generation if Long Bit Period Error reported
* @{
*/
-#define CEC_LBPE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000U)
+#define CEC_LBPE_ERRORBIT_NO_GENERATION 0x00000000U
#define CEC_LBPE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_LBPEGEN)
/**
* @}
@@ -288,7 +288,7 @@
/** @defgroup CEC_BroadCastMsgErrorBitGen CEC Error Bit Generation on Broadcast message
* @{
*/
-#define CEC_BROADCASTERROR_ERRORBIT_GENERATION ((uint32_t)0x00000000U)
+#define CEC_BROADCASTERROR_ERRORBIT_GENERATION 0x00000000U
#define CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BRDNOGEN)
/**
* @}
@@ -297,7 +297,7 @@
/** @defgroup CEC_SFT_Option CEC Signal Free Time start option
* @{
*/
-#define CEC_SFT_START_ON_TXSOM ((uint32_t)0x00000000U)
+#define CEC_SFT_START_ON_TXSOM 0x00000000U
#define CEC_SFT_START_ON_TX_RX_END ((uint32_t)CEC_CFGR_SFTOPT)
/**
* @}
@@ -306,7 +306,7 @@
/** @defgroup CEC_Listening_Mode CEC Listening mode option
* @{
*/
-#define CEC_REDUCED_LISTENING_MODE ((uint32_t)0x00000000U)
+#define CEC_REDUCED_LISTENING_MODE 0x00000000U
#define CEC_FULL_LISTENING_MODE ((uint32_t)CEC_CFGR_LSTN)
/**
* @}
@@ -315,7 +315,7 @@
/** @defgroup CEC_OAR_Position CEC Device Own Address position in CEC CFGR register
* @{
*/
-#define CEC_CFGR_OAR_LSB_POS ((uint32_t) 16U)
+#define CEC_CFGR_OAR_LSB_POS 16U
/**
* @}
*/
@@ -323,7 +323,7 @@
/** @defgroup CEC_Initiator_Position CEC Initiator logical address position in message header
* @{
*/
-#define CEC_INITIATOR_LSB_POS ((uint32_t) 4U)
+#define CEC_INITIATOR_LSB_POS 4U
/**
* @}
*/
@@ -331,22 +331,22 @@
/** @defgroup CEC_OWN_ADDRESS CEC Own Address
* @{
*/
-#define CEC_OWN_ADDRESS_NONE ((uint16_t) 0x0000U) /* Reset value */
-#define CEC_OWN_ADDRESS_0 ((uint16_t) 0x0001U) /* Logical Address 0 */
-#define CEC_OWN_ADDRESS_1 ((uint16_t) 0x0002U) /* Logical Address 1 */
-#define CEC_OWN_ADDRESS_2 ((uint16_t) 0x0004U) /* Logical Address 2 */
-#define CEC_OWN_ADDRESS_3 ((uint16_t) 0x0008U) /* Logical Address 3 */
-#define CEC_OWN_ADDRESS_4 ((uint16_t) 0x0010U) /* Logical Address 4 */
-#define CEC_OWN_ADDRESS_5 ((uint16_t) 0x0020U) /* Logical Address 5 */
-#define CEC_OWN_ADDRESS_6 ((uint16_t) 0x0040U) /* Logical Address 6 */
-#define CEC_OWN_ADDRESS_7 ((uint16_t) 0x0080U) /* Logical Address 7 */
-#define CEC_OWN_ADDRESS_8 ((uint16_t) 0x0100U) /* Logical Address 9 */
-#define CEC_OWN_ADDRESS_9 ((uint16_t) 0x0200U) /* Logical Address 10 */
-#define CEC_OWN_ADDRESS_10 ((uint16_t) 0x0400U) /* Logical Address 11 */
-#define CEC_OWN_ADDRESS_11 ((uint16_t) 0x0800U) /* Logical Address 12 */
-#define CEC_OWN_ADDRESS_12 ((uint16_t) 0x1000U) /* Logical Address 13 */
-#define CEC_OWN_ADDRESS_13 ((uint16_t) 0x2000U) /* Logical Address 14 */
-#define CEC_OWN_ADDRESS_14 ((uint16_t) 0x4000U) /* Logical Address 15 */
+#define CEC_OWN_ADDRESS_NONE ((uint16_t)0x0000) /* Reset value */
+#define CEC_OWN_ADDRESS_0 ((uint16_t)0x0001) /* Logical Address 0 */
+#define CEC_OWN_ADDRESS_1 ((uint16_t)0x0002) /* Logical Address 1 */
+#define CEC_OWN_ADDRESS_2 ((uint16_t)0x0004) /* Logical Address 2 */
+#define CEC_OWN_ADDRESS_3 ((uint16_t)0x0008) /* Logical Address 3 */
+#define CEC_OWN_ADDRESS_4 ((uint16_t)0x0010) /* Logical Address 4 */
+#define CEC_OWN_ADDRESS_5 ((uint16_t)0x0020) /* Logical Address 5 */
+#define CEC_OWN_ADDRESS_6 ((uint16_t)0x0040) /* Logical Address 6 */
+#define CEC_OWN_ADDRESS_7 ((uint16_t)0x0080) /* Logical Address 7 */
+#define CEC_OWN_ADDRESS_8 ((uint16_t)0x0100) /* Logical Address 9 */
+#define CEC_OWN_ADDRESS_9 ((uint16_t)0x0200) /* Logical Address 10 */
+#define CEC_OWN_ADDRESS_10 ((uint16_t)0x0400) /* Logical Address 11 */
+#define CEC_OWN_ADDRESS_11 ((uint16_t)0x0800) /* Logical Address 12 */
+#define CEC_OWN_ADDRESS_12 ((uint16_t)0x1000) /* Logical Address 13 */
+#define CEC_OWN_ADDRESS_13 ((uint16_t)0x2000) /* Logical Address 14 */
+#define CEC_OWN_ADDRESS_14 ((uint16_t)0x4000) /* Logical Address 15 */
/**
* @}
*/
@@ -702,7 +702,7 @@
* @param __SIZE__: CEC message size.
* @retval Test result (TRUE or FALSE).
*/
-#define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10)
+#define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10U)
/** @brief Check CEC device Own Address Register (OAR) setting.
* OAR address is written in a 15-bit field within CEC_CFGR register.
