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Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

TARGET_NUCLEO_F042K6/stm32f0xx_hal_pwr_ex.h@122:f9eeca106725, 2016-07-07 (annotated)

Committer:
Kojto
Date:
Thu Jul 07 14:34:11 2016 +0100
Revision:
122:f9eeca106725
Parent:
109:9296ab0bfc11 
Release 122 of the mbed library



Changes:

- new targets - Nucleo L432KC, Beetle, Nucleo F446ZE, Nucleo L011K4

- Thread safety addition - mbed API should contain a statement about thread safety

- critical section API addition

- CAS API (core_util_atomic_incr/decr)

- DEVICE_ are generated from targets.json file, device.h deprecated

- Callback replaces FunctionPointer to provide std like interface

- mbed HAL API docs improvements

- toolchain - prexif attributes with MBED_

            - add new attributes - packed, weak, forcedinline, align

- target.json - contains targets definitions

- ST - L1XX - Cube update to 1.5

     - SPI clock selection fix (clock from APB domain)

     - F7 - Cube update v1.4.0

     - L0 -  baudrate init fix

     - L1 - Cube update v1.5

     - F3 - baudrate init fix, 3 targets CAN support

     - F4 - Cube update v1.12.0, 3 targets CAN support

     - L4XX - Cube update v1.5.1

     - F0 - update Cube to v1.5.0

     - L4 - 2 targets (L476RG/VG) CAN support

- NXP - pwm clock fix for KSDK2 MCU

      - LPC2368 - remove ARM toolchain support - due to regression

      - KSDK2 - fix SPI , I2C address and repeat start

- Silabs - some fixes backported from mbed 3

- Renesas - RZ_A1H - SystemCoreClockUpdate addition

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 109:9296ab0bfc11 1 /**
Kojto 109:9296ab0bfc11 2 ******************************************************************************
Kojto 109:9296ab0bfc11 3 * @file stm32f0xx_hal_pwr_ex.h
Kojto 109:9296ab0bfc11 4 * @author MCD Application Team
Kojto 122:f9eeca106725 5 * @version V1.4.0
Kojto 122:f9eeca106725 6 * @date 27-May-2016
Kojto 109:9296ab0bfc11 7 * @brief Header file of PWR HAL Extension module.
Kojto 109:9296ab0bfc11 8 ******************************************************************************
Kojto 109:9296ab0bfc11 9 * @attention
Kojto 109:9296ab0bfc11 10 *
Kojto 122:f9eeca106725 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
Kojto 109:9296ab0bfc11 12 *
Kojto 109:9296ab0bfc11 13 * Redistribution and use in source and binary forms, with or without modification,
Kojto 109:9296ab0bfc11 14 * are permitted provided that the following conditions are met:
Kojto 109:9296ab0bfc11 15 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 109:9296ab0bfc11 16 * this list of conditions and the following disclaimer.
Kojto 109:9296ab0bfc11 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 109:9296ab0bfc11 18 * this list of conditions and the following disclaimer in the documentation
Kojto 109:9296ab0bfc11 19 * and/or other materials provided with the distribution.
Kojto 109:9296ab0bfc11 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto 109:9296ab0bfc11 21 * may be used to endorse or promote products derived from this software
Kojto 109:9296ab0bfc11 22 * without specific prior written permission.
Kojto 109:9296ab0bfc11 23 *
Kojto 109:9296ab0bfc11 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 109:9296ab0bfc11 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 109:9296ab0bfc11 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 109:9296ab0bfc11 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 109:9296ab0bfc11 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 109:9296ab0bfc11 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 109:9296ab0bfc11 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 109:9296ab0bfc11 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 109:9296ab0bfc11 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 109:9296ab0bfc11 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 109:9296ab0bfc11 34 *
Kojto 109:9296ab0bfc11 35 ******************************************************************************
Kojto 109:9296ab0bfc11 36 */
Kojto 109:9296ab0bfc11 37
Kojto 109:9296ab0bfc11 38 /* Define to prevent recursive inclusion -------------------------------------*/
Kojto 109:9296ab0bfc11 39 #ifndef __STM32F0xx_HAL_PWR_EX_H
Kojto 109:9296ab0bfc11 40 #define __STM32F0xx_HAL_PWR_EX_H
Kojto 109:9296ab0bfc11 41
Kojto 109:9296ab0bfc11 42 #ifdef __cplusplus
Kojto 109:9296ab0bfc11 43 extern "C" {
Kojto 109:9296ab0bfc11 44 #endif
Kojto 109:9296ab0bfc11 45
Kojto 109:9296ab0bfc11 46 /* Includes ------------------------------------------------------------------*/
Kojto 109:9296ab0bfc11 47 #include "stm32f0xx_hal_def.h"
Kojto 109:9296ab0bfc11 48
Kojto 109:9296ab0bfc11 49 /** @addtogroup STM32F0xx_HAL_Driver
Kojto 109:9296ab0bfc11 50 * @{
Kojto 109:9296ab0bfc11 51 */
Kojto 109:9296ab0bfc11 52
Kojto 109:9296ab0bfc11 53 /** @addtogroup PWREx
Kojto 109:9296ab0bfc11 54 * @{
Kojto 109:9296ab0bfc11 55 */
Kojto 109:9296ab0bfc11 56
Kojto 109:9296ab0bfc11 57 /* Exported types ------------------------------------------------------------*/
Kojto 109:9296ab0bfc11 58
Kojto 109:9296ab0bfc11 59 /** @defgroup PWREx_Exported_Types PWREx Exported Types
Kojto 109:9296ab0bfc11 60 * @{
Kojto 109:9296ab0bfc11 61 */
Kojto 109:9296ab0bfc11 62
Kojto 109:9296ab0bfc11 63 #if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \
Kojto 109:9296ab0bfc11 64 defined (STM32F071xB) || defined (STM32F072xB) || \
Kojto 109:9296ab0bfc11 65 defined (STM32F091xC)
Kojto 109:9296ab0bfc11 66
Kojto 109:9296ab0bfc11 67 /**
Kojto 109:9296ab0bfc11 68 * @brief PWR PVD configuration structure definition
Kojto 109:9296ab0bfc11 69 */
Kojto 109:9296ab0bfc11 70 typedef struct
Kojto 109:9296ab0bfc11 71 {
Kojto 109:9296ab0bfc11 72 uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level
Kojto 109:9296ab0bfc11 73 This parameter can be a value of @ref PWREx_PVD_detection_level */
Kojto 109:9296ab0bfc11 74
Kojto 109:9296ab0bfc11 75 uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
Kojto 109:9296ab0bfc11 76 This parameter can be a value of @ref PWREx_PVD_Mode */
Kojto 109:9296ab0bfc11 77 }PWR_PVDTypeDef;
Kojto 109:9296ab0bfc11 78
Kojto 109:9296ab0bfc11 79 #endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */
Kojto 109:9296ab0bfc11 80 /* defined (STM32F071xB) || defined (STM32F072xB) || */
Kojto 109:9296ab0bfc11 81 /* defined (STM32F091xC) */
Kojto 109:9296ab0bfc11 82 /**
Kojto 109:9296ab0bfc11 83 * @}
Kojto 109:9296ab0bfc11 84 */
Kojto 109:9296ab0bfc11 85 /* Exported constants --------------------------------------------------------*/
Kojto 109:9296ab0bfc11 86
Kojto 109:9296ab0bfc11 87 /** @defgroup PWREx_Exported_Constants PWREx Exported Constants
Kojto 109:9296ab0bfc11 88 * @{
Kojto 109:9296ab0bfc11 89 */
Kojto 109:9296ab0bfc11 90
Kojto 109:9296ab0bfc11 91
Kojto 109:9296ab0bfc11 92 /** @defgroup PWREx_WakeUp_Pins PWREx Wakeup Pins
Kojto 109:9296ab0bfc11 93 * @{
Kojto 109:9296ab0bfc11 94 */
Kojto 122:f9eeca106725 95 #if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
Kojto 122:f9eeca106725 96 defined (STM32F091xC) || defined (STM32F098xx)
Kojto 122:f9eeca106725 97 #define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1)
Kojto 122:f9eeca106725 98 #define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2)
Kojto 122:f9eeca106725 99 #define PWR_WAKEUP_PIN3 ((uint32_t)PWR_CSR_EWUP3)
Kojto 122:f9eeca106725 100 #define PWR_WAKEUP_PIN4 ((uint32_t)PWR_CSR_EWUP4)
Kojto 122:f9eeca106725 101 #define PWR_WAKEUP_PIN5 ((uint32_t)PWR_CSR_EWUP5)
Kojto 122:f9eeca106725 102 #define PWR_WAKEUP_PIN6 ((uint32_t)PWR_CSR_EWUP6)
Kojto 122:f9eeca106725 103 #define PWR_WAKEUP_PIN7 ((uint32_t)PWR_CSR_EWUP7)
Kojto 122:f9eeca106725 104 #define PWR_WAKEUP_PIN8 ((uint32_t)PWR_CSR_EWUP8)
Kojto 109:9296ab0bfc11 105
Kojto 109:9296ab0bfc11 106 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
Kojto 109:9296ab0bfc11 107 ((PIN) == PWR_WAKEUP_PIN2) || \
Kojto 109:9296ab0bfc11 108 ((PIN) == PWR_WAKEUP_PIN3) || \
Kojto 109:9296ab0bfc11 109 ((PIN) == PWR_WAKEUP_PIN4) || \
Kojto 109:9296ab0bfc11 110 ((PIN) == PWR_WAKEUP_PIN5) || \
Kojto 109:9296ab0bfc11 111 ((PIN) == PWR_WAKEUP_PIN6) || \
Kojto 109:9296ab0bfc11 112 ((PIN) == PWR_WAKEUP_PIN7) || \
Kojto 109:9296ab0bfc11 113 ((PIN) == PWR_WAKEUP_PIN8))
Kojto 122:f9eeca106725 114
Kojto 122:f9eeca106725 115 #elif defined(STM32F030xC) || defined (STM32F070xB)
Kojto 122:f9eeca106725 116 #define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1)
Kojto 122:f9eeca106725 117 #define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2)
Kojto 122:f9eeca106725 118 #define PWR_WAKEUP_PIN4 ((uint32_t)PWR_CSR_EWUP4)
Kojto 122:f9eeca106725 119 #define PWR_WAKEUP_PIN5 ((uint32_t)PWR_CSR_EWUP5)
Kojto 122:f9eeca106725 120 #define PWR_WAKEUP_PIN6 ((uint32_t)PWR_CSR_EWUP6)
Kojto 122:f9eeca106725 121 #define PWR_WAKEUP_PIN7 ((uint32_t)PWR_CSR_EWUP7)
Kojto 122:f9eeca106725 122
Kojto 122:f9eeca106725 123 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
Kojto 122:f9eeca106725 124 ((PIN) == PWR_WAKEUP_PIN2) || \
Kojto 122:f9eeca106725 125 ((PIN) == PWR_WAKEUP_PIN4) || \
Kojto 122:f9eeca106725 126 ((PIN) == PWR_WAKEUP_PIN5) || \
Kojto 122:f9eeca106725 127 ((PIN) == PWR_WAKEUP_PIN6) || \
Kojto 122:f9eeca106725 128 ((PIN) == PWR_WAKEUP_PIN7))
Kojto 122:f9eeca106725 129
Kojto 122:f9eeca106725 130 #elif defined(STM32F042x6) || defined (STM32F048xx)
Kojto 122:f9eeca106725 131 #define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1)
Kojto 122:f9eeca106725 132 #define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2)
Kojto 122:f9eeca106725 133 #define PWR_WAKEUP_PIN4 ((uint32_t)PWR_CSR_EWUP4)
Kojto 122:f9eeca106725 134 #define PWR_WAKEUP_PIN6 ((uint32_t)PWR_CSR_EWUP6)
Kojto 122:f9eeca106725 135 #define PWR_WAKEUP_PIN7 ((uint32_t)PWR_CSR_EWUP7)
Kojto 122:f9eeca106725 136
Kojto 122:f9eeca106725 137 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
Kojto 122:f9eeca106725 138 ((PIN) == PWR_WAKEUP_PIN2) || \
Kojto 122:f9eeca106725 139 ((PIN) == PWR_WAKEUP_PIN4) || \
Kojto 122:f9eeca106725 140 ((PIN) == PWR_WAKEUP_PIN6) || \
Kojto 122:f9eeca106725 141 ((PIN) == PWR_WAKEUP_PIN7))
Kojto 122:f9eeca106725 142
Kojto 122:f9eeca106725 143 #else
Kojto 122:f9eeca106725 144 #define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1)
Kojto 122:f9eeca106725 145 #define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2)
Kojto 122:f9eeca106725 146
Kojto 109:9296ab0bfc11 147
Kojto 109:9296ab0bfc11 148 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
Kojto 109:9296ab0bfc11 149 ((PIN) == PWR_WAKEUP_PIN2))
Kojto 122:f9eeca106725 150
Kojto 122:f9eeca106725 151 #endif
Kojto 122:f9eeca106725 152
Kojto 109:9296ab0bfc11 153 /**
Kojto 109:9296ab0bfc11 154 * @}
Kojto 109:9296ab0bfc11 155 */
Kojto 109:9296ab0bfc11 156
Kojto 109:9296ab0bfc11 157 /** @defgroup PWREx_EXTI_Line PWREx EXTI Line
Kojto 109:9296ab0bfc11 158 * @{
Kojto 109:9296ab0bfc11 159 */
Kojto 109:9296ab0bfc11 160 #if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \
Kojto 109:9296ab0bfc11 161 defined (STM32F071xB) || defined (STM32F072xB) || \
Kojto 109:9296ab0bfc11 162 defined (STM32F091xC)
Kojto 109:9296ab0bfc11 163
Kojto 109:9296ab0bfc11 164 #define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR_MR16) /*!< External interrupt line 16 Connected to the PVD EXTI Line */
Kojto 109:9296ab0bfc11 165
Kojto 109:9296ab0bfc11 166 #endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */
Kojto 109:9296ab0bfc11 167 /* defined (STM32F071xB) || defined (STM32F072xB) || */
Kojto 109:9296ab0bfc11 168 /* defined (STM32F091xC) */
Kojto 109:9296ab0bfc11 169
Kojto 109:9296ab0bfc11 170 #if defined (STM32F042x6) || defined (STM32F048xx) || \
Kojto 109:9296ab0bfc11 171 defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
Kojto 109:9296ab0bfc11 172 defined (STM32F091xC) || defined (STM32F098xx)
Kojto 109:9296ab0bfc11 173
Kojto 109:9296ab0bfc11 174 #define PWR_EXTI_LINE_VDDIO2 ((uint32_t)EXTI_IMR_MR31) /*!< External interrupt line 31 Connected to the Vddio2 Monitor EXTI Line */
Kojto 109:9296ab0bfc11 175
Kojto 109:9296ab0bfc11 176 #endif /* defined (STM32F042x6) || defined (STM32F048xx) ||\
Kojto 109:9296ab0bfc11 177 defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
Kojto 109:9296ab0bfc11 178 defined (STM32F091xC) || defined (STM32F098xx) ||*/
Kojto 109:9296ab0bfc11 179 /**
Kojto 109:9296ab0bfc11 180 * @}
Kojto 109:9296ab0bfc11 181 */
Kojto 109:9296ab0bfc11 182
Kojto 109:9296ab0bfc11 183 #if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \
Kojto 109:9296ab0bfc11 184 defined (STM32F071xB) || defined (STM32F072xB) || \
Kojto 109:9296ab0bfc11 185 defined (STM32F091xC)
Kojto 109:9296ab0bfc11 186 /** @defgroup PWREx_PVD_detection_level PWREx PVD detection level
Kojto 109:9296ab0bfc11 187 * @{
Kojto 109:9296ab0bfc11 188 */
Kojto 109:9296ab0bfc11 189 #define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0
Kojto 109:9296ab0bfc11 190 #define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1
Kojto 109:9296ab0bfc11 191 #define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2
Kojto 109:9296ab0bfc11 192 #define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3
Kojto 109:9296ab0bfc11 193 #define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4
Kojto 109:9296ab0bfc11 194 #define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5
Kojto 109:9296ab0bfc11 195 #define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6
Kojto 109:9296ab0bfc11 196 #define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7
Kojto 109:9296ab0bfc11 197 #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
Kojto 109:9296ab0bfc11 198 ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
Kojto 109:9296ab0bfc11 199 ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
Kojto 109:9296ab0bfc11 200 ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
Kojto 109:9296ab0bfc11 201 /**
Kojto 109:9296ab0bfc11 202 * @}
Kojto 109:9296ab0bfc11 203 */
Kojto 109:9296ab0bfc11 204
Kojto 109:9296ab0bfc11 205 /** @defgroup PWREx_PVD_Mode PWREx PVD Mode
Kojto 109:9296ab0bfc11 206 * @{
Kojto 109:9296ab0bfc11 207 */
Kojto 109:9296ab0bfc11 208 #define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000) /*!< basic mode is used */
Kojto 109:9296ab0bfc11 209 #define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */
Kojto 109:9296ab0bfc11 210 #define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */
Kojto 109:9296ab0bfc11 211 #define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
Kojto 109:9296ab0bfc11 212 #define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */
Kojto 109:9296ab0bfc11 213 #define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */
Kojto 109:9296ab0bfc11 214 #define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */
Kojto 109:9296ab0bfc11 215
Kojto 109:9296ab0bfc11 216 #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
Kojto 109:9296ab0bfc11 217 ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
Kojto 109:9296ab0bfc11 218 ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
Kojto 109:9296ab0bfc11 219 ((MODE) == PWR_PVD_MODE_NORMAL))
Kojto 109:9296ab0bfc11 220 /**
Kojto 109:9296ab0bfc11 221 * @}
Kojto 109:9296ab0bfc11 222 */
Kojto 109:9296ab0bfc11 223 #endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */
Kojto 109:9296ab0bfc11 224 /* defined (STM32F071xB) || defined (STM32F072xB) || */
Kojto 109:9296ab0bfc11 225 /* defined (STM32F091xC) */
Kojto 109:9296ab0bfc11 226
Kojto 109:9296ab0bfc11 227 /** @defgroup PWREx_Flag PWREx Flag
Kojto 109:9296ab0bfc11 228 * @{
Kojto 109:9296ab0bfc11 229 */
Kojto 109:9296ab0bfc11 230 #if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \
Kojto 109:9296ab0bfc11 231 defined (STM32F071xB) || defined (STM32F072xB) || \
Kojto 109:9296ab0bfc11 232 defined (STM32F091xC)
Kojto 109:9296ab0bfc11 233
Kojto 109:9296ab0bfc11 234 #define PWR_FLAG_WU PWR_CSR_WUF
Kojto 109:9296ab0bfc11 235 #define PWR_FLAG_SB PWR_CSR_SBF
Kojto 109:9296ab0bfc11 236 #define PWR_FLAG_PVDO PWR_CSR_PVDO
Kojto 109:9296ab0bfc11 237 #define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF
Kojto 109:9296ab0bfc11 238 #elif defined (STM32F070x6) || defined (STM32F070xB) || defined (STM32F030xC)
Kojto 109:9296ab0bfc11 239 #define PWR_FLAG_WU PWR_CSR_WUF
Kojto 109:9296ab0bfc11 240 #define PWR_FLAG_SB PWR_CSR_SBF
Kojto 109:9296ab0bfc11 241 #define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF
Kojto 109:9296ab0bfc11 242 #else
Kojto 109:9296ab0bfc11 243 #define PWR_FLAG_WU PWR_CSR_WUF
Kojto 109:9296ab0bfc11 244 #define PWR_FLAG_SB PWR_CSR_SBF
Kojto 109:9296ab0bfc11 245
Kojto 109:9296ab0bfc11 246 #endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */
Kojto 109:9296ab0bfc11 247 /* defined (STM32F071xB) || defined (STM32F072xB) || */
Kojto 109:9296ab0bfc11 248 /* defined (STM32F091xC) */
Kojto 109:9296ab0bfc11 249 /**
Kojto 109:9296ab0bfc11 250 * @}
Kojto 109:9296ab0bfc11 251 */
Kojto 109:9296ab0bfc11 252
Kojto 109:9296ab0bfc11 253 /**
Kojto 109:9296ab0bfc11 254 * @}
Kojto 109:9296ab0bfc11 255 */
Kojto 109:9296ab0bfc11 256
Kojto 109:9296ab0bfc11 257 /* Exported macro ------------------------------------------------------------*/
Kojto 109:9296ab0bfc11 258 /** @defgroup PWREx_Exported_Macros PWREx Exported Macros
Kojto 109:9296ab0bfc11 259 * @{
Kojto 109:9296ab0bfc11 260 */
Kojto 109:9296ab0bfc11 261 #if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \
Kojto 109:9296ab0bfc11 262 defined (STM32F071xB) || defined (STM32F072xB) || \
Kojto 109:9296ab0bfc11 263 defined (STM32F091xC)
Kojto 109:9296ab0bfc11 264 /**
Kojto 109:9296ab0bfc11 265 * @brief Enable interrupt on PVD Exti Line 16.
Kojto 109:9296ab0bfc11 266 * @retval None.
Kojto 109:9296ab0bfc11 267 */
Kojto 109:9296ab0bfc11 268 #define __HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_PVD))
Kojto 109:9296ab0bfc11 269
Kojto 109:9296ab0bfc11 270 /**
Kojto 109:9296ab0bfc11 271 * @brief Disable interrupt on PVD Exti Line 16.
Kojto 109:9296ab0bfc11 272 * @retval None.
Kojto 109:9296ab0bfc11 273 */
Kojto 109:9296ab0bfc11 274 #define __HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD))
Kojto 109:9296ab0bfc11 275
Kojto 109:9296ab0bfc11 276 /**
Kojto 109:9296ab0bfc11 277 * @brief Enable event on PVD Exti Line 16.
Kojto 109:9296ab0bfc11 278 * @retval None.
Kojto 109:9296ab0bfc11 279 */
Kojto 109:9296ab0bfc11 280 #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI->EMR |= (PWR_EXTI_LINE_PVD))
Kojto 109:9296ab0bfc11 281
Kojto 109:9296ab0bfc11 282 /**
Kojto 109:9296ab0bfc11 283 * @brief Disable event on PVD Exti Line 16.
Kojto 109:9296ab0bfc11 284 * @retval None.
Kojto 109:9296ab0bfc11 285 */
Kojto 109:9296ab0bfc11 286 #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD))
Kojto 109:9296ab0bfc11 287
Kojto 109:9296ab0bfc11 288 /**
Kojto 109:9296ab0bfc11 289 * @brief Disable the PVD Extended Interrupt Rising Trigger.
Kojto 109:9296ab0bfc11 290 * @retval None.
Kojto 109:9296ab0bfc11 291 */
Kojto 109:9296ab0bfc11 292 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
Kojto 109:9296ab0bfc11 293
Kojto 109:9296ab0bfc11 294 /**
Kojto 109:9296ab0bfc11 295 * @brief Disable the PVD Extended Interrupt Falling Trigger.
Kojto 109:9296ab0bfc11 296 * @retval None.
Kojto 109:9296ab0bfc11 297 */
Kojto 109:9296ab0bfc11 298 #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
Kojto 109:9296ab0bfc11 299
Kojto 109:9296ab0bfc11 300 /**
Kojto 109:9296ab0bfc11 301 * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
Kojto 109:9296ab0bfc11 302 * @retval None
Kojto 109:9296ab0bfc11 303 */
Kojto 109:9296ab0bfc11 304 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
Kojto 109:9296ab0bfc11 305
Kojto 109:9296ab0bfc11 306
Kojto 109:9296ab0bfc11 307 /**
Kojto 109:9296ab0bfc11 308 * @brief PVD EXTI line configuration: set falling edge trigger.
Kojto 109:9296ab0bfc11 309 * @retval None.
Kojto 109:9296ab0bfc11 310 */
Kojto 109:9296ab0bfc11 311 #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() EXTI->FTSR |= (PWR_EXTI_LINE_PVD)
Kojto 109:9296ab0bfc11 312
Kojto 109:9296ab0bfc11 313 /**
Kojto 109:9296ab0bfc11 314 * @brief PVD EXTI line configuration: set rising edge trigger.
Kojto 109:9296ab0bfc11 315 * @retval None.
Kojto 109:9296ab0bfc11 316 */
Kojto 109:9296ab0bfc11 317 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() EXTI->RTSR |= (PWR_EXTI_LINE_PVD)
Kojto 109:9296ab0bfc11 318
Kojto 109:9296ab0bfc11 319 /**
Kojto 109:9296ab0bfc11 320 * @brief Enable the PVD Extended Interrupt Rising & Falling Trigger.
Kojto 109:9296ab0bfc11 321 * @retval None
Kojto 109:9296ab0bfc11 322 */
Kojto 109:9296ab0bfc11 323 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
Kojto 109:9296ab0bfc11 324
Kojto 109:9296ab0bfc11 325 /**
Kojto 109:9296ab0bfc11 326 * @brief Check whether the specified PVD EXTI interrupt flag is set or not.
Kojto 109:9296ab0bfc11 327 * @retval EXTI PVD Line Status.
Kojto 109:9296ab0bfc11 328 */
Kojto 109:9296ab0bfc11 329 #define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD))
Kojto 109:9296ab0bfc11 330
Kojto 109:9296ab0bfc11 331 /**
Kojto 109:9296ab0bfc11 332 * @brief Clear the PVD EXTI flag.
Kojto 109:9296ab0bfc11 333 * @retval None.
Kojto 109:9296ab0bfc11 334 */
Kojto 109:9296ab0bfc11 335 #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD))
Kojto 109:9296ab0bfc11 336
Kojto 109:9296ab0bfc11 337 /**
Kojto 109:9296ab0bfc11 338 * @brief Generate a Software interrupt on selected EXTI line.
Kojto 109:9296ab0bfc11 339 * @retval None.
Kojto 109:9296ab0bfc11 340 */
Kojto 109:9296ab0bfc11 341 #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD))
Kojto 109:9296ab0bfc11 342
Kojto 109:9296ab0bfc11 343 #endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */
Kojto 109:9296ab0bfc11 344 /* defined (STM32F071xB) || defined (STM32F072xB) || */
Kojto 109:9296ab0bfc11 345 /* defined (STM32F091xC) */
Kojto 109:9296ab0bfc11 346
Kojto 109:9296ab0bfc11 347
Kojto 109:9296ab0bfc11 348 #if defined (STM32F042x6) || defined (STM32F048xx) || \
Kojto 109:9296ab0bfc11 349 defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
Kojto 109:9296ab0bfc11 350 defined (STM32F091xC) || defined (STM32F098xx)
Kojto 109:9296ab0bfc11 351 /**
Kojto 109:9296ab0bfc11 352 * @brief Enable interrupt on Vddio2 Monitor Exti Line 31.
Kojto 109:9296ab0bfc11 353 * @retval None.
Kojto 109:9296ab0bfc11 354 */
Kojto 109:9296ab0bfc11 355 #define __HAL_PWR_VDDIO2_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_VDDIO2))
Kojto 109:9296ab0bfc11 356
Kojto 109:9296ab0bfc11 357 /**
Kojto 109:9296ab0bfc11 358 * @brief Disable interrupt on Vddio2 Monitor Exti Line 31.
Kojto 109:9296ab0bfc11 359 * @retval None.
Kojto 109:9296ab0bfc11 360 */
Kojto 109:9296ab0bfc11 361 #define __HAL_PWR_VDDIO2_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_VDDIO2))
Kojto 109:9296ab0bfc11 362
Kojto 109:9296ab0bfc11 363 /**
Kojto 109:9296ab0bfc11 364 * @brief Vddio2 Monitor EXTI line configuration: clear falling edge and rising edge trigger.
Kojto 109:9296ab0bfc11 365 * @retval None.
Kojto 109:9296ab0bfc11 366 */
Kojto 122:f9eeca106725 367 #define __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE() \
Kojto 122:f9eeca106725 368 do{ \
Kojto 122:f9eeca106725 369 EXTI->FTSR &= ~(PWR_EXTI_LINE_VDDIO2); \
Kojto 122:f9eeca106725 370 EXTI->RTSR &= ~(PWR_EXTI_LINE_VDDIO2); \
Kojto 122:f9eeca106725 371 } while(0)
Kojto 122:f9eeca106725 372
Kojto 109:9296ab0bfc11 373 /**
Kojto 109:9296ab0bfc11 374 * @brief Vddio2 Monitor EXTI line configuration: set falling edge trigger.
Kojto 109:9296ab0bfc11 375 * @retval None.
Kojto 109:9296ab0bfc11 376 */
Kojto 109:9296ab0bfc11 377 #define __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE() EXTI->FTSR |= (PWR_EXTI_LINE_VDDIO2)
Kojto 109:9296ab0bfc11 378
Kojto 109:9296ab0bfc11 379 /**
Kojto 109:9296ab0bfc11 380 * @brief Check whether the specified VDDIO2 monitor EXTI interrupt flag is set or not.
Kojto 109:9296ab0bfc11 381 * @retval EXTI VDDIO2 Monitor Line Status.
Kojto 109:9296ab0bfc11 382 */
Kojto 109:9296ab0bfc11 383 #define __HAL_PWR_VDDIO2_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_VDDIO2))
Kojto 109:9296ab0bfc11 384
Kojto 109:9296ab0bfc11 385 /**
Kojto 109:9296ab0bfc11 386 * @brief Clear the VDDIO2 Monitor EXTI flag.
Kojto 109:9296ab0bfc11 387 * @retval None.
Kojto 109:9296ab0bfc11 388 */
Kojto 109:9296ab0bfc11 389 #define __HAL_PWR_VDDIO2_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_VDDIO2))
Kojto 109:9296ab0bfc11 390
Kojto 109:9296ab0bfc11 391 /**
Kojto 109:9296ab0bfc11 392 * @brief Generate a Software interrupt on selected EXTI line.
Kojto 109:9296ab0bfc11 393 * @retval None.
Kojto 109:9296ab0bfc11 394 */
Kojto 109:9296ab0bfc11 395 #define __HAL_PWR_VDDIO2_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_VDDIO2))
Kojto 109:9296ab0bfc11 396
Kojto 109:9296ab0bfc11 397
Kojto 109:9296ab0bfc11 398 #endif /* defined (STM32F042x6) || defined (STM32F048xx) ||\
Kojto 109:9296ab0bfc11 399 defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
Kojto 109:9296ab0bfc11 400 defined (STM32F091xC) || defined (STM32F098xx) */
Kojto 109:9296ab0bfc11 401
Kojto 109:9296ab0bfc11 402 /**
Kojto 109:9296ab0bfc11 403 * @}
Kojto 109:9296ab0bfc11 404 */
Kojto 109:9296ab0bfc11 405
Kojto 109:9296ab0bfc11 406 /* Exported functions --------------------------------------------------------*/
Kojto 109:9296ab0bfc11 407
Kojto 109:9296ab0bfc11 408 /** @addtogroup PWREx_Exported_Functions PWREx Exported Functions
Kojto 109:9296ab0bfc11 409 * @{
Kojto 109:9296ab0bfc11 410 */
Kojto 109:9296ab0bfc11 411
Kojto 109:9296ab0bfc11 412 /** @addtogroup PWREx_Exported_Functions_Group1
Kojto 109:9296ab0bfc11 413 * @{
Kojto 109:9296ab0bfc11 414 */
Kojto 109:9296ab0bfc11 415 /* I/O operation functions ***************************************************/
Kojto 109:9296ab0bfc11 416 #if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \
Kojto 109:9296ab0bfc11 417 defined (STM32F071xB) || defined (STM32F072xB) || \
Kojto 109:9296ab0bfc11 418 defined (STM32F091xC)
Kojto 109:9296ab0bfc11 419 void HAL_PWR_PVD_IRQHandler(void);
Kojto 109:9296ab0bfc11 420 void HAL_PWR_PVDCallback(void);
Kojto 109:9296ab0bfc11 421 #endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */
Kojto 109:9296ab0bfc11 422 /* defined (STM32F071xB) || defined (STM32F072xB) || */
Kojto 109:9296ab0bfc11 423 /* defined (STM32F091xC) */
Kojto 109:9296ab0bfc11 424
Kojto 109:9296ab0bfc11 425 #if defined (STM32F042x6) || defined (STM32F048xx) || \
Kojto 109:9296ab0bfc11 426 defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
Kojto 109:9296ab0bfc11 427 defined (STM32F091xC) || defined (STM32F098xx)
Kojto 109:9296ab0bfc11 428 void HAL_PWREx_Vddio2Monitor_IRQHandler(void);
Kojto 109:9296ab0bfc11 429 void HAL_PWREx_Vddio2MonitorCallback(void);
Kojto 109:9296ab0bfc11 430 #endif /* defined (STM32F042x6) || defined (STM32F048xx) || \
Kojto 109:9296ab0bfc11 431 defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
Kojto 109:9296ab0bfc11 432 defined (STM32F091xC) || defined (STM32F098xx) */
Kojto 109:9296ab0bfc11 433
Kojto 109:9296ab0bfc11 434 /* Peripheral Control functions **********************************************/
Kojto 109:9296ab0bfc11 435 #if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \
Kojto 109:9296ab0bfc11 436 defined (STM32F071xB) || defined (STM32F072xB) || \
Kojto 109:9296ab0bfc11 437 defined (STM32F091xC)
Kojto 109:9296ab0bfc11 438 void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
Kojto 109:9296ab0bfc11 439 void HAL_PWR_EnablePVD(void);
Kojto 109:9296ab0bfc11 440 void HAL_PWR_DisablePVD(void);
Kojto 109:9296ab0bfc11 441 #endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */
Kojto 109:9296ab0bfc11 442 /* defined (STM32F071xB) || defined (STM32F072xB) || */
Kojto 109:9296ab0bfc11 443 /* defined (STM32F091xC) */
Kojto 109:9296ab0bfc11 444
Kojto 109:9296ab0bfc11 445 #if defined (STM32F042x6) || defined (STM32F048xx) || \
Kojto 109:9296ab0bfc11 446 defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
Kojto 109:9296ab0bfc11 447 defined (STM32F091xC) || defined (STM32F098xx)
Kojto 109:9296ab0bfc11 448 void HAL_PWREx_EnableVddio2Monitor(void);
Kojto 109:9296ab0bfc11 449 void HAL_PWREx_DisableVddio2Monitor(void);
Kojto 109:9296ab0bfc11 450 #endif /* defined (STM32F042x6) || defined (STM32F048xx) || \
Kojto 109:9296ab0bfc11 451 defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
Kojto 109:9296ab0bfc11 452 defined (STM32F091xC) || defined (STM32F098xx) */
Kojto 109:9296ab0bfc11 453
Kojto 109:9296ab0bfc11 454 /**
Kojto 109:9296ab0bfc11 455 * @}
Kojto 109:9296ab0bfc11 456 */
Kojto 109:9296ab0bfc11 457
Kojto 109:9296ab0bfc11 458 /**
Kojto 109:9296ab0bfc11 459 * @}
Kojto 109:9296ab0bfc11 460 */
Kojto 109:9296ab0bfc11 461
Kojto 109:9296ab0bfc11 462 /**
Kojto 109:9296ab0bfc11 463 * @}
Kojto 109:9296ab0bfc11 464 */
Kojto 109:9296ab0bfc11 465
Kojto 109:9296ab0bfc11 466 /**
Kojto 109:9296ab0bfc11 467 * @}
Kojto 109:9296ab0bfc11 468 */
Kojto 109:9296ab0bfc11 469
Kojto 109:9296ab0bfc11 470 #ifdef __cplusplus
Kojto 109:9296ab0bfc11 471 }
Kojto 109:9296ab0bfc11 472 #endif
Kojto 109:9296ab0bfc11 473
Kojto 109:9296ab0bfc11 474 #endif /* __STM32F0xx_HAL_PWR_EX_H */
Kojto 109:9296ab0bfc11 475
Kojto 109:9296ab0bfc11 476 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Kojto 109:9296ab0bfc11 477