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Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

TARGET_NUCLEO_F030R8/stm32f030x8.h@122:f9eeca106725, 2016-07-07 (annotated)

Committer:
Kojto
Date:
Thu Jul 07 14:34:11 2016 +0100
Revision:
122:f9eeca106725
Parent:
108:34e6b704fe68 
Release 122 of the mbed library



Changes:

- new targets - Nucleo L432KC, Beetle, Nucleo F446ZE, Nucleo L011K4

- Thread safety addition - mbed API should contain a statement about thread safety

- critical section API addition

- CAS API (core_util_atomic_incr/decr)

- DEVICE_ are generated from targets.json file, device.h deprecated

- Callback replaces FunctionPointer to provide std like interface

- mbed HAL API docs improvements

- toolchain - prexif attributes with MBED_

            - add new attributes - packed, weak, forcedinline, align

- target.json - contains targets definitions

- ST - L1XX - Cube update to 1.5

     - SPI clock selection fix (clock from APB domain)

     - F7 - Cube update v1.4.0

     - L0 -  baudrate init fix

     - L1 - Cube update v1.5

     - F3 - baudrate init fix, 3 targets CAN support

     - F4 - Cube update v1.12.0, 3 targets CAN support

     - L4XX - Cube update v1.5.1

     - F0 - update Cube to v1.5.0

     - L4 - 2 targets (L476RG/VG) CAN support

- NXP - pwm clock fix for KSDK2 MCU

      - LPC2368 - remove ARM toolchain support - due to regression

      - KSDK2 - fix SPI , I2C address and repeat start

- Silabs - some fixes backported from mbed 3

- Renesas - RZ_A1H - SystemCoreClockUpdate addition

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 90:cb3d968589d8 1 /**
Kojto 90:cb3d968589d8 2 ******************************************************************************
Kojto 90:cb3d968589d8 3 * @file stm32f030x8.h
Kojto 90:cb3d968589d8 4 * @author MCD Application Team
Kojto 122:f9eeca106725 5 * @version V2.3.0
Kojto 122:f9eeca106725 6 * @date 27-May-2016
Kojto 122:f9eeca106725 7 * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File.
Kojto 122:f9eeca106725 8 * This file contains all the peripheral register's definitions, bits
Kojto 122:f9eeca106725 9 * definitions and memory mapping for STM32F0xx devices.
Kojto 122:f9eeca106725 10 *
Kojto 90:cb3d968589d8 11 * This file contains:
Kojto 90:cb3d968589d8 12 * - Data structures and the address mapping for all peripherals
Kojto 90:cb3d968589d8 13 * - Peripheral's registers declarations and bits definition
Kojto 90:cb3d968589d8 14 * - Macros to access peripheral’s registers hardware
Kojto 122:f9eeca106725 15 *
Kojto 90:cb3d968589d8 16 ******************************************************************************
Kojto 90:cb3d968589d8 17 * @attention
Kojto 90:cb3d968589d8 18 *
Kojto 122:f9eeca106725 19 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
Kojto 90:cb3d968589d8 20 *
Kojto 90:cb3d968589d8 21 * Redistribution and use in source and binary forms, with or without modification,
Kojto 90:cb3d968589d8 22 * are permitted provided that the following conditions are met:
Kojto 90:cb3d968589d8 23 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 90:cb3d968589d8 24 * this list of conditions and the following disclaimer.
Kojto 90:cb3d968589d8 25 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 90:cb3d968589d8 26 * this list of conditions and the following disclaimer in the documentation
Kojto 90:cb3d968589d8 27 * and/or other materials provided with the distribution.
Kojto 90:cb3d968589d8 28 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto 90:cb3d968589d8 29 * may be used to endorse or promote products derived from this software
Kojto 90:cb3d968589d8 30 * without specific prior written permission.
Kojto 90:cb3d968589d8 31 *
Kojto 90:cb3d968589d8 32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 90:cb3d968589d8 33 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 90:cb3d968589d8 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 90:cb3d968589d8 35 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 90:cb3d968589d8 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 90:cb3d968589d8 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 90:cb3d968589d8 38 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 90:cb3d968589d8 39 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 90:cb3d968589d8 40 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 90:cb3d968589d8 41 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 90:cb3d968589d8 42 *
Kojto 90:cb3d968589d8 43 ******************************************************************************
Kojto 90:cb3d968589d8 44 */
Kojto 122:f9eeca106725 45
Kojto 122:f9eeca106725 46 /** @addtogroup CMSIS
Kojto 90:cb3d968589d8 47 * @{
Kojto 90:cb3d968589d8 48 */
Kojto 90:cb3d968589d8 49
Kojto 90:cb3d968589d8 50 /** @addtogroup stm32f030x8
Kojto 90:cb3d968589d8 51 * @{
Kojto 90:cb3d968589d8 52 */
Kojto 122:f9eeca106725 53
Kojto 90:cb3d968589d8 54 #ifndef __STM32F030x8_H
Kojto 90:cb3d968589d8 55 #define __STM32F030x8_H
Kojto 90:cb3d968589d8 56
Kojto 90:cb3d968589d8 57 #ifdef __cplusplus
Kojto 90:cb3d968589d8 58 extern "C" {
Kojto 90:cb3d968589d8 59 #endif /* __cplusplus */
Kojto 90:cb3d968589d8 60
Kojto 122:f9eeca106725 61 /** @addtogroup Configuration_section_for_CMSIS
Kojto 90:cb3d968589d8 62 * @{
Kojto 90:cb3d968589d8 63 */
Kojto 90:cb3d968589d8 64 /**
Kojto 90:cb3d968589d8 65 * @brief Configuration of the Cortex-M0 Processor and Core Peripherals
Kojto 90:cb3d968589d8 66 */
Kojto 90:cb3d968589d8 67 #define __CM0_REV 0 /*!< Core Revision r0p0 */
Kojto 90:cb3d968589d8 68 #define __MPU_PRESENT 0 /*!< STM32F0xx do not provide MPU */
Kojto 90:cb3d968589d8 69 #define __NVIC_PRIO_BITS 2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */
Kojto 122:f9eeca106725 70 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
Kojto 122:f9eeca106725 71
Kojto 90:cb3d968589d8 72 /**
Kojto 90:cb3d968589d8 73 * @}
Kojto 90:cb3d968589d8 74 */
Kojto 90:cb3d968589d8 75
Kojto 90:cb3d968589d8 76 /** @addtogroup Peripheral_interrupt_number_definition
Kojto 90:cb3d968589d8 77 * @{
Kojto 90:cb3d968589d8 78 */
Kojto 90:cb3d968589d8 79
Kojto 90:cb3d968589d8 80 /**
Kojto 122:f9eeca106725 81 * @brief STM32F0xx Interrupt Number Definition, according to the selected device
Kojto 122:f9eeca106725 82 * in @ref Library_configuration_section
Kojto 90:cb3d968589d8 83 */
Kojto 122:f9eeca106725 84
Kojto 122:f9eeca106725 85 /*!< Interrupt Number Definition */
Kojto 90:cb3d968589d8 86 typedef enum
Kojto 90:cb3d968589d8 87 {
Kojto 90:cb3d968589d8 88 /****** Cortex-M0 Processor Exceptions Numbers **************************************************************/
Kojto 90:cb3d968589d8 89 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
Kojto 90:cb3d968589d8 90 HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
Kojto 90:cb3d968589d8 91 SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
Kojto 90:cb3d968589d8 92 PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
Kojto 90:cb3d968589d8 93 SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
Kojto 90:cb3d968589d8 94
Kojto 122:f9eeca106725 95 /****** STM32F0 specific Interrupt Numbers ******************************************************************/
Kojto 122:f9eeca106725 96 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
Kojto 90:cb3d968589d8 97 RTC_IRQn = 2, /*!< RTC Interrupt through EXTI Lines 17, 19 and 20 */
Kojto 90:cb3d968589d8 98 FLASH_IRQn = 3, /*!< FLASH global Interrupt */
Kojto 90:cb3d968589d8 99 RCC_IRQn = 4, /*!< RCC global Interrupt */
Kojto 122:f9eeca106725 100 EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupt */
Kojto 122:f9eeca106725 101 EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupt */
Kojto 122:f9eeca106725 102 EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupt */
Kojto 90:cb3d968589d8 103 DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
Kojto 122:f9eeca106725 104 DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupt */
Kojto 122:f9eeca106725 105 DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupt */
Kojto 122:f9eeca106725 106 ADC1_IRQn = 12, /*!< ADC1 Interrupt */
Kojto 122:f9eeca106725 107 TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupt */
Kojto 90:cb3d968589d8 108 TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */
Kojto 90:cb3d968589d8 109 TIM3_IRQn = 16, /*!< TIM3 global Interrupt */
Kojto 90:cb3d968589d8 110 TIM6_IRQn = 17, /*!< TIM6 global Interrupt */
Kojto 90:cb3d968589d8 111 TIM14_IRQn = 19, /*!< TIM14 global Interrupt */
Kojto 90:cb3d968589d8 112 TIM15_IRQn = 20, /*!< TIM15 global Interrupt */
Kojto 90:cb3d968589d8 113 TIM16_IRQn = 21, /*!< TIM16 global Interrupt */
Kojto 90:cb3d968589d8 114 TIM17_IRQn = 22, /*!< TIM17 global Interrupt */
Kojto 90:cb3d968589d8 115 I2C1_IRQn = 23, /*!< I2C1 Event Interrupt */
Kojto 90:cb3d968589d8 116 I2C2_IRQn = 24, /*!< I2C2 Event Interrupt */
Kojto 90:cb3d968589d8 117 SPI1_IRQn = 25, /*!< SPI1 global Interrupt */
Kojto 90:cb3d968589d8 118 SPI2_IRQn = 26, /*!< SPI2 global Interrupt */
Kojto 122:f9eeca106725 119 USART1_IRQn = 27, /*!< USART1 global Interrupt */
Kojto 90:cb3d968589d8 120 USART2_IRQn = 28 /*!< USART2 global Interrupt */
Kojto 90:cb3d968589d8 121 } IRQn_Type;
Kojto 90:cb3d968589d8 122
Kojto 90:cb3d968589d8 123 /**
Kojto 90:cb3d968589d8 124 * @}
Kojto 90:cb3d968589d8 125 */
Kojto 90:cb3d968589d8 126
Kojto 90:cb3d968589d8 127 #include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
Kojto 90:cb3d968589d8 128 #include "system_stm32f0xx.h" /* STM32F0xx System Header */
Kojto 90:cb3d968589d8 129 #include <stdint.h>
Kojto 90:cb3d968589d8 130
Kojto 90:cb3d968589d8 131 /** @addtogroup Peripheral_registers_structures
Kojto 90:cb3d968589d8 132 * @{
Kojto 90:cb3d968589d8 133 */
Kojto 90:cb3d968589d8 134
Kojto 90:cb3d968589d8 135 /**
Kojto 90:cb3d968589d8 136 * @brief Analog to Digital Converter
Kojto 90:cb3d968589d8 137 */
Kojto 90:cb3d968589d8 138
Kojto 90:cb3d968589d8 139 typedef struct
Kojto 90:cb3d968589d8 140 {
Kojto 122:f9eeca106725 141 __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */
Kojto 122:f9eeca106725 142 __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */
Kojto 122:f9eeca106725 143 __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
Kojto 122:f9eeca106725 144 __IO uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x0C */
Kojto 122:f9eeca106725 145 __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */
Kojto 122:f9eeca106725 146 __IO uint32_t SMPR; /*!< ADC sampling time register, Address offset: 0x14 */
Kojto 122:f9eeca106725 147 uint32_t RESERVED1; /*!< Reserved, 0x18 */
Kojto 122:f9eeca106725 148 uint32_t RESERVED2; /*!< Reserved, 0x1C */
Kojto 122:f9eeca106725 149 __IO uint32_t TR; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */
Kojto 122:f9eeca106725 150 uint32_t RESERVED3; /*!< Reserved, 0x24 */
Kojto 122:f9eeca106725 151 __IO uint32_t CHSELR; /*!< ADC group regular sequencer register, Address offset: 0x28 */
Kojto 122:f9eeca106725 152 uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */
Kojto 122:f9eeca106725 153 __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */
Kojto 122:f9eeca106725 154 } ADC_TypeDef;
Kojto 90:cb3d968589d8 155
Kojto 90:cb3d968589d8 156 typedef struct
Kojto 90:cb3d968589d8 157 {
Kojto 122:f9eeca106725 158 __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */
Kojto 122:f9eeca106725 159 } ADC_Common_TypeDef;
Kojto 122:f9eeca106725 160
Kojto 122:f9eeca106725 161 /**
Kojto 90:cb3d968589d8 162 * @brief CRC calculation unit
Kojto 90:cb3d968589d8 163 */
Kojto 90:cb3d968589d8 164
Kojto 90:cb3d968589d8 165 typedef struct
Kojto 90:cb3d968589d8 166 {
Kojto 90:cb3d968589d8 167 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
Kojto 90:cb3d968589d8 168 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
Kojto 90:cb3d968589d8 169 uint8_t RESERVED0; /*!< Reserved, 0x05 */
Kojto 90:cb3d968589d8 170 uint16_t RESERVED1; /*!< Reserved, 0x06 */
Kojto 122:f9eeca106725 171 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
Kojto 90:cb3d968589d8 172 uint32_t RESERVED2; /*!< Reserved, 0x0C */
Kojto 90:cb3d968589d8 173 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
Kojto 122:f9eeca106725 174 __IO uint32_t RESERVED3; /*!< Reserved, 0x14 */
Kojto 122:f9eeca106725 175 } CRC_TypeDef;
Kojto 122:f9eeca106725 176
Kojto 122:f9eeca106725 177 /**
Kojto 90:cb3d968589d8 178 * @brief Debug MCU
Kojto 90:cb3d968589d8 179 */
Kojto 90:cb3d968589d8 180
Kojto 90:cb3d968589d8 181 typedef struct
Kojto 90:cb3d968589d8 182 {
Kojto 90:cb3d968589d8 183 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
Kojto 90:cb3d968589d8 184 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
Kojto 90:cb3d968589d8 185 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
Kojto 90:cb3d968589d8 186 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
Kojto 90:cb3d968589d8 187 }DBGMCU_TypeDef;
Kojto 90:cb3d968589d8 188
Kojto 122:f9eeca106725 189 /**
Kojto 90:cb3d968589d8 190 * @brief DMA Controller
Kojto 90:cb3d968589d8 191 */
Kojto 90:cb3d968589d8 192
Kojto 90:cb3d968589d8 193 typedef struct
Kojto 90:cb3d968589d8 194 {
Kojto 122:f9eeca106725 195 __IO uint32_t CCR; /*!< DMA channel x configuration register */
Kojto 122:f9eeca106725 196 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
Kojto 122:f9eeca106725 197 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
Kojto 122:f9eeca106725 198 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
Kojto 122:f9eeca106725 199 } DMA_Channel_TypeDef;
Kojto 90:cb3d968589d8 200
Kojto 90:cb3d968589d8 201 typedef struct
Kojto 90:cb3d968589d8 202 {
Kojto 122:f9eeca106725 203 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
Kojto 122:f9eeca106725 204 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
Kojto 122:f9eeca106725 205 } DMA_TypeDef;
Kojto 90:cb3d968589d8 206
Kojto 90:cb3d968589d8 207 /**
Kojto 90:cb3d968589d8 208 * @brief External Interrupt/Event Controller
Kojto 90:cb3d968589d8 209 */
Kojto 90:cb3d968589d8 210
Kojto 90:cb3d968589d8 211 typedef struct
Kojto 90:cb3d968589d8 212 {
Kojto 122:f9eeca106725 213 __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
Kojto 122:f9eeca106725 214 __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
Kojto 122:f9eeca106725 215 __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
Kojto 122:f9eeca106725 216 __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
Kojto 122:f9eeca106725 217 __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
Kojto 122:f9eeca106725 218 __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
Kojto 122:f9eeca106725 219 } EXTI_TypeDef;
Kojto 90:cb3d968589d8 220
Kojto 90:cb3d968589d8 221 /**
Kojto 90:cb3d968589d8 222 * @brief FLASH Registers
Kojto 90:cb3d968589d8 223 */
Kojto 90:cb3d968589d8 224 typedef struct
Kojto 90:cb3d968589d8 225 {
Kojto 90:cb3d968589d8 226 __IO uint32_t ACR; /*!<FLASH access control register, Address offset: 0x00 */
Kojto 90:cb3d968589d8 227 __IO uint32_t KEYR; /*!<FLASH key register, Address offset: 0x04 */
Kojto 90:cb3d968589d8 228 __IO uint32_t OPTKEYR; /*!<FLASH OPT key register, Address offset: 0x08 */
Kojto 90:cb3d968589d8 229 __IO uint32_t SR; /*!<FLASH status register, Address offset: 0x0C */
Kojto 90:cb3d968589d8 230 __IO uint32_t CR; /*!<FLASH control register, Address offset: 0x10 */
Kojto 90:cb3d968589d8 231 __IO uint32_t AR; /*!<FLASH address register, Address offset: 0x14 */
Kojto 90:cb3d968589d8 232 __IO uint32_t RESERVED; /*!< Reserved, 0x18 */
Kojto 90:cb3d968589d8 233 __IO uint32_t OBR; /*!<FLASH option bytes register, Address offset: 0x1C */
Kojto 90:cb3d968589d8 234 __IO uint32_t WRPR; /*!<FLASH option bytes register, Address offset: 0x20 */
Kojto 122:f9eeca106725 235 } FLASH_TypeDef;
Kojto 90:cb3d968589d8 236
Kojto 90:cb3d968589d8 237 /**
Kojto 90:cb3d968589d8 238 * @brief Option Bytes Registers
Kojto 90:cb3d968589d8 239 */
Kojto 90:cb3d968589d8 240 typedef struct
Kojto 90:cb3d968589d8 241 {
Kojto 122:f9eeca106725 242 __IO uint16_t RDP; /*!< FLASH option byte Read protection, Address offset: 0x00 */
Kojto 122:f9eeca106725 243 __IO uint16_t USER; /*!< FLASH option byte user options, Address offset: 0x02 */
Kojto 122:f9eeca106725 244 __IO uint16_t DATA0; /*!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 */
Kojto 122:f9eeca106725 245 __IO uint16_t DATA1; /*!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 */
Kojto 122:f9eeca106725 246 __IO uint16_t WRP0; /*!< FLASH option byte write protection 0, Address offset: 0x08 */
Kojto 122:f9eeca106725 247 __IO uint16_t WRP1; /*!< FLASH option byte write protection 1, Address offset: 0x0A */
Kojto 122:f9eeca106725 248 } OB_TypeDef;
Kojto 122:f9eeca106725 249
Kojto 122:f9eeca106725 250 /**
Kojto 90:cb3d968589d8 251 * @brief General Purpose I/O
Kojto 90:cb3d968589d8 252 */
Kojto 90:cb3d968589d8 253
Kojto 90:cb3d968589d8 254 typedef struct
Kojto 90:cb3d968589d8 255 {
Kojto 122:f9eeca106725 256 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
Kojto 122:f9eeca106725 257 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
Kojto 122:f9eeca106725 258 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
Kojto 122:f9eeca106725 259 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
Kojto 122:f9eeca106725 260 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
Kojto 122:f9eeca106725 261 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
Kojto 90:cb3d968589d8 262 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */
Kojto 122:f9eeca106725 263 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
bogdanm 92:4fc01daae5a5 264 __IO uint32_t AFR[2]; /*!< GPIO alternate function low register, Address offset: 0x20-0x24 */
Kojto 122:f9eeca106725 265 __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
Kojto 122:f9eeca106725 266 } GPIO_TypeDef;
Kojto 122:f9eeca106725 267
Kojto 122:f9eeca106725 268 /**
Kojto 90:cb3d968589d8 269 * @brief SysTem Configuration
Kojto 90:cb3d968589d8 270 */
Kojto 90:cb3d968589d8 271
Kojto 90:cb3d968589d8 272 typedef struct
Kojto 90:cb3d968589d8 273 {
Kojto 90:cb3d968589d8 274 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
Kojto 90:cb3d968589d8 275 uint32_t RESERVED; /*!< Reserved, 0x04 */
Kojto 90:cb3d968589d8 276 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */
Kojto 90:cb3d968589d8 277 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
Kojto 122:f9eeca106725 278 } SYSCFG_TypeDef;
Kojto 90:cb3d968589d8 279
Kojto 90:cb3d968589d8 280 /**
Kojto 90:cb3d968589d8 281 * @brief Inter-integrated Circuit Interface
Kojto 90:cb3d968589d8 282 */
Kojto 90:cb3d968589d8 283
Kojto 90:cb3d968589d8 284 typedef struct
Kojto 90:cb3d968589d8 285 {
Kojto 122:f9eeca106725 286 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
Kojto 122:f9eeca106725 287 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
Kojto 90:cb3d968589d8 288 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
Kojto 90:cb3d968589d8 289 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
Kojto 90:cb3d968589d8 290 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
Kojto 90:cb3d968589d8 291 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
Kojto 90:cb3d968589d8 292 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
Kojto 90:cb3d968589d8 293 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
Kojto 90:cb3d968589d8 294 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
Kojto 90:cb3d968589d8 295 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
Kojto 90:cb3d968589d8 296 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
Kojto 122:f9eeca106725 297 } I2C_TypeDef;
Kojto 122:f9eeca106725 298
Kojto 122:f9eeca106725 299 /**
Kojto 90:cb3d968589d8 300 * @brief Independent WATCHDOG
Kojto 90:cb3d968589d8 301 */
Kojto 90:cb3d968589d8 302
Kojto 90:cb3d968589d8 303 typedef struct
Kojto 90:cb3d968589d8 304 {
Kojto 90:cb3d968589d8 305 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
Kojto 90:cb3d968589d8 306 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
Kojto 90:cb3d968589d8 307 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
Kojto 90:cb3d968589d8 308 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
Kojto 90:cb3d968589d8 309 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
Kojto 122:f9eeca106725 310 } IWDG_TypeDef;
Kojto 122:f9eeca106725 311
Kojto 122:f9eeca106725 312 /**
Kojto 90:cb3d968589d8 313 * @brief Power Control
Kojto 90:cb3d968589d8 314 */
Kojto 90:cb3d968589d8 315
Kojto 90:cb3d968589d8 316 typedef struct
Kojto 90:cb3d968589d8 317 {
Kojto 122:f9eeca106725 318 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
Kojto 122:f9eeca106725 319 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
Kojto 122:f9eeca106725 320 } PWR_TypeDef;
Kojto 122:f9eeca106725 321
Kojto 122:f9eeca106725 322 /**
Kojto 90:cb3d968589d8 323 * @brief Reset and Clock Control
Kojto 90:cb3d968589d8 324 */
Kojto 108:34e6b704fe68 325
Kojto 90:cb3d968589d8 326 typedef struct
Kojto 90:cb3d968589d8 327 {
Kojto 122:f9eeca106725 328 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
Kojto 90:cb3d968589d8 329 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */
Kojto 90:cb3d968589d8 330 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */
Kojto 90:cb3d968589d8 331 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */
Kojto 90:cb3d968589d8 332 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */
Kojto 90:cb3d968589d8 333 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */
Kojto 90:cb3d968589d8 334 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */
Kojto 90:cb3d968589d8 335 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */
Kojto 90:cb3d968589d8 336 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */
Kojto 90:cb3d968589d8 337 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */
Kojto 90:cb3d968589d8 338 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */
Kojto 90:cb3d968589d8 339 __IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */
Kojto 90:cb3d968589d8 340 __IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */
Kojto 90:cb3d968589d8 341 __IO uint32_t CR2; /*!< RCC clock control register 2, Address offset: 0x34 */
Kojto 122:f9eeca106725 342 } RCC_TypeDef;
Kojto 90:cb3d968589d8 343
Kojto 90:cb3d968589d8 344 /**
Kojto 90:cb3d968589d8 345 * @brief Real-Time Clock
Kojto 90:cb3d968589d8 346 */
Kojto 90:cb3d968589d8 347 typedef struct
Kojto 90:cb3d968589d8 348 {
Kojto 122:f9eeca106725 349 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
Kojto 122:f9eeca106725 350 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
Kojto 122:f9eeca106725 351 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
Kojto 122:f9eeca106725 352 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
Kojto 122:f9eeca106725 353 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
Kojto 122:f9eeca106725 354 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
Kojto 122:f9eeca106725 355 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x18 */
Kojto 122:f9eeca106725 356 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
Kojto 122:f9eeca106725 357 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x20 */
Kojto 122:f9eeca106725 358 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
Kojto 122:f9eeca106725 359 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
Kojto 122:f9eeca106725 360 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
Kojto 122:f9eeca106725 361 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
Kojto 122:f9eeca106725 362 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
Kojto 122:f9eeca106725 363 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
Kojto 122:f9eeca106725 364 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
Kojto 122:f9eeca106725 365 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
Kojto 122:f9eeca106725 366 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
Kojto 122:f9eeca106725 367 } RTC_TypeDef;
Kojto 122:f9eeca106725 368
Kojto 122:f9eeca106725 369 /**
Kojto 90:cb3d968589d8 370 * @brief Serial Peripheral Interface
Kojto 90:cb3d968589d8 371 */
Kojto 90:cb3d968589d8 372
Kojto 90:cb3d968589d8 373 typedef struct
Kojto 90:cb3d968589d8 374 {
Kojto 122:f9eeca106725 375 __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
Kojto 122:f9eeca106725 376 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
Kojto 122:f9eeca106725 377 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
Kojto 122:f9eeca106725 378 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
Kojto 122:f9eeca106725 379 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
Kojto 122:f9eeca106725 380 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
Kojto 122:f9eeca106725 381 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
Kojto 122:f9eeca106725 382 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
Kojto 122:f9eeca106725 383 } SPI_TypeDef;
Kojto 122:f9eeca106725 384
Kojto 122:f9eeca106725 385 /**
Kojto 90:cb3d968589d8 386 * @brief TIM
Kojto 90:cb3d968589d8 387 */
Kojto 90:cb3d968589d8 388 typedef struct
Kojto 90:cb3d968589d8 389 {
Kojto 122:f9eeca106725 390 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
Kojto 122:f9eeca106725 391 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
Kojto 122:f9eeca106725 392 __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
Kojto 122:f9eeca106725 393 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
Kojto 122:f9eeca106725 394 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
Kojto 122:f9eeca106725 395 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
Kojto 122:f9eeca106725 396 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
Kojto 122:f9eeca106725 397 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
Kojto 122:f9eeca106725 398 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
Kojto 122:f9eeca106725 399 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
Kojto 122:f9eeca106725 400 __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
Kojto 122:f9eeca106725 401 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
Kojto 90:cb3d968589d8 402 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
Kojto 122:f9eeca106725 403 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
Kojto 122:f9eeca106725 404 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
Kojto 122:f9eeca106725 405 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
Kojto 122:f9eeca106725 406 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
Kojto 90:cb3d968589d8 407 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
Kojto 122:f9eeca106725 408 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
Kojto 90:cb3d968589d8 409 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
Kojto 122:f9eeca106725 410 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
Kojto 122:f9eeca106725 411 } TIM_TypeDef;
Kojto 122:f9eeca106725 412
Kojto 122:f9eeca106725 413 /**
Kojto 90:cb3d968589d8 414 * @brief Universal Synchronous Asynchronous Receiver Transmitter
Kojto 90:cb3d968589d8 415 */
Kojto 122:f9eeca106725 416
Kojto 90:cb3d968589d8 417 typedef struct
Kojto 90:cb3d968589d8 418 {
Kojto 90:cb3d968589d8 419 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
Kojto 90:cb3d968589d8 420 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
Kojto 90:cb3d968589d8 421 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
Kojto 90:cb3d968589d8 422 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
Kojto 90:cb3d968589d8 423 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
Kojto 90:cb3d968589d8 424 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
Kojto 90:cb3d968589d8 425 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
Kojto 90:cb3d968589d8 426 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
Kojto 90:cb3d968589d8 427 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
Kojto 90:cb3d968589d8 428 __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
Kojto 90:cb3d968589d8 429 uint16_t RESERVED1; /*!< Reserved, 0x26 */
Kojto 90:cb3d968589d8 430 __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
Kojto 90:cb3d968589d8 431 uint16_t RESERVED2; /*!< Reserved, 0x2A */
Kojto 122:f9eeca106725 432 } USART_TypeDef;
Kojto 122:f9eeca106725 433
Kojto 122:f9eeca106725 434 /**
Kojto 90:cb3d968589d8 435 * @brief Window WATCHDOG
Kojto 90:cb3d968589d8 436 */
Kojto 90:cb3d968589d8 437 typedef struct
Kojto 90:cb3d968589d8 438 {
Kojto 90:cb3d968589d8 439 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
Kojto 90:cb3d968589d8 440 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
Kojto 90:cb3d968589d8 441 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
Kojto 122:f9eeca106725 442 } WWDG_TypeDef;
Kojto 122:f9eeca106725 443
Kojto 122:f9eeca106725 444 /**
Kojto 90:cb3d968589d8 445 * @}
Kojto 90:cb3d968589d8 446 */
Kojto 90:cb3d968589d8 447
Kojto 90:cb3d968589d8 448 /** @addtogroup Peripheral_memory_map
Kojto 90:cb3d968589d8 449 * @{
Kojto 90:cb3d968589d8 450 */
Kojto 90:cb3d968589d8 451
Kojto 122:f9eeca106725 452 #define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH base address in the alias region */
Kojto 122:f9eeca106725 453 #define FLASH_BANK1_END ((uint32_t)0x0800FFFFU) /*!< FLASH END address of bank1 */
Kojto 122:f9eeca106725 454 #define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM base address in the alias region */
Kojto 122:f9eeca106725 455 #define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address in the alias region */
Kojto 90:cb3d968589d8 456
Kojto 90:cb3d968589d8 457 /*!< Peripheral memory map */
Kojto 90:cb3d968589d8 458 #define APBPERIPH_BASE PERIPH_BASE
Kojto 90:cb3d968589d8 459 #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000)
Kojto 90:cb3d968589d8 460 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
Kojto 90:cb3d968589d8 461
Kojto 122:f9eeca106725 462 /*!< APB peripherals */
Kojto 90:cb3d968589d8 463 #define TIM3_BASE (APBPERIPH_BASE + 0x00000400)
Kojto 90:cb3d968589d8 464 #define TIM6_BASE (APBPERIPH_BASE + 0x00001000)
Kojto 90:cb3d968589d8 465 #define TIM14_BASE (APBPERIPH_BASE + 0x00002000)
Kojto 90:cb3d968589d8 466 #define RTC_BASE (APBPERIPH_BASE + 0x00002800)
Kojto 90:cb3d968589d8 467 #define WWDG_BASE (APBPERIPH_BASE + 0x00002C00)
Kojto 90:cb3d968589d8 468 #define IWDG_BASE (APBPERIPH_BASE + 0x00003000)
Kojto 90:cb3d968589d8 469 #define SPI2_BASE (APBPERIPH_BASE + 0x00003800)
Kojto 90:cb3d968589d8 470 #define USART2_BASE (APBPERIPH_BASE + 0x00004400)
Kojto 90:cb3d968589d8 471 #define I2C1_BASE (APBPERIPH_BASE + 0x00005400)
Kojto 90:cb3d968589d8 472 #define I2C2_BASE (APBPERIPH_BASE + 0x00005800)
Kojto 90:cb3d968589d8 473 #define PWR_BASE (APBPERIPH_BASE + 0x00007000)
Kojto 90:cb3d968589d8 474 #define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
Kojto 90:cb3d968589d8 475 #define EXTI_BASE (APBPERIPH_BASE + 0x00010400)
Kojto 90:cb3d968589d8 476 #define ADC1_BASE (APBPERIPH_BASE + 0x00012400)
Kojto 90:cb3d968589d8 477 #define ADC_BASE (APBPERIPH_BASE + 0x00012708)
Kojto 90:cb3d968589d8 478 #define TIM1_BASE (APBPERIPH_BASE + 0x00012C00)
Kojto 90:cb3d968589d8 479 #define SPI1_BASE (APBPERIPH_BASE + 0x00013000)
Kojto 90:cb3d968589d8 480 #define USART1_BASE (APBPERIPH_BASE + 0x00013800)
Kojto 90:cb3d968589d8 481 #define TIM15_BASE (APBPERIPH_BASE + 0x00014000)
Kojto 90:cb3d968589d8 482 #define TIM16_BASE (APBPERIPH_BASE + 0x00014400)
Kojto 90:cb3d968589d8 483 #define TIM17_BASE (APBPERIPH_BASE + 0x00014800)
Kojto 90:cb3d968589d8 484 #define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800)
Kojto 90:cb3d968589d8 485
Kojto 122:f9eeca106725 486 /*!< AHB peripherals */
Kojto 90:cb3d968589d8 487 #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000)
Kojto 90:cb3d968589d8 488 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008)
Kojto 90:cb3d968589d8 489 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C)
Kojto 90:cb3d968589d8 490 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030)
Kojto 90:cb3d968589d8 491 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044)
Kojto 90:cb3d968589d8 492 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058)
Kojto 90:cb3d968589d8 493
Kojto 90:cb3d968589d8 494 #define RCC_BASE (AHBPERIPH_BASE + 0x00001000)
Kojto 90:cb3d968589d8 495 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */
Kojto 122:f9eeca106725 496 #define OB_BASE ((uint32_t)0x1FFFF800U) /*!< FLASH Option Bytes base address */
Kojto 122:f9eeca106725 497 #define FLASHSIZE_BASE ((uint32_t)0x1FFFF7CCU) /*!< FLASH Size register base address */
Kojto 122:f9eeca106725 498 #define UID_BASE ((uint32_t)0x1FFFF7ACU) /*!< Unique device ID register base address */
Kojto 90:cb3d968589d8 499 #define CRC_BASE (AHBPERIPH_BASE + 0x00003000)
Kojto 90:cb3d968589d8 500
Kojto 122:f9eeca106725 501 /*!< AHB2 peripherals */
Kojto 90:cb3d968589d8 502 #define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000)
Kojto 90:cb3d968589d8 503 #define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400)
Kojto 90:cb3d968589d8 504 #define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800)
Kojto 90:cb3d968589d8 505 #define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00)
Kojto 90:cb3d968589d8 506 #define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400)
Kojto 90:cb3d968589d8 507
Kojto 90:cb3d968589d8 508 /**
Kojto 90:cb3d968589d8 509 * @}
Kojto 90:cb3d968589d8 510 */
Kojto 122:f9eeca106725 511
Kojto 90:cb3d968589d8 512 /** @addtogroup Peripheral_declaration
Kojto 90:cb3d968589d8 513 * @{
Kojto 122:f9eeca106725 514 */
Kojto 90:cb3d968589d8 515
Kojto 90:cb3d968589d8 516 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
Kojto 90:cb3d968589d8 517 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
Kojto 90:cb3d968589d8 518 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
Kojto 90:cb3d968589d8 519 #define RTC ((RTC_TypeDef *) RTC_BASE)
Kojto 90:cb3d968589d8 520 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
Kojto 90:cb3d968589d8 521 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
Kojto 90:cb3d968589d8 522 #define USART2 ((USART_TypeDef *) USART2_BASE)
Kojto 90:cb3d968589d8 523 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
Kojto 90:cb3d968589d8 524 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
Kojto 90:cb3d968589d8 525 #define PWR ((PWR_TypeDef *) PWR_BASE)
Kojto 90:cb3d968589d8 526 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
Kojto 90:cb3d968589d8 527 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
Kojto 90:cb3d968589d8 528 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
Kojto 122:f9eeca106725 529 #define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE)
Kojto 122:f9eeca106725 530 #define ADC ((ADC_Common_TypeDef *) ADC_BASE) /* Kept for legacy purpose */
Kojto 90:cb3d968589d8 531 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
Kojto 90:cb3d968589d8 532 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
Kojto 122:f9eeca106725 533 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
Kojto 90:cb3d968589d8 534 #define USART1 ((USART_TypeDef *) USART1_BASE)
Kojto 90:cb3d968589d8 535 #define TIM15 ((TIM_TypeDef *) TIM15_BASE)
Kojto 90:cb3d968589d8 536 #define TIM16 ((TIM_TypeDef *) TIM16_BASE)
Kojto 90:cb3d968589d8 537 #define TIM17 ((TIM_TypeDef *) TIM17_BASE)
Kojto 90:cb3d968589d8 538 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
Kojto 90:cb3d968589d8 539 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
Kojto 90:cb3d968589d8 540 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
Kojto 90:cb3d968589d8 541 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
Kojto 90:cb3d968589d8 542 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
Kojto 90:cb3d968589d8 543 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
Kojto 90:cb3d968589d8 544 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
Kojto 90:cb3d968589d8 545 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
Kojto 90:cb3d968589d8 546 #define OB ((OB_TypeDef *) OB_BASE)
Kojto 90:cb3d968589d8 547 #define RCC ((RCC_TypeDef *) RCC_BASE)
Kojto 90:cb3d968589d8 548 #define CRC ((CRC_TypeDef *) CRC_BASE)
Kojto 90:cb3d968589d8 549 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
Kojto 90:cb3d968589d8 550 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
Kojto 90:cb3d968589d8 551 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
Kojto 90:cb3d968589d8 552 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
Kojto 90:cb3d968589d8 553 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
Kojto 90:cb3d968589d8 554 /**
Kojto 90:cb3d968589d8 555 * @}
Kojto 90:cb3d968589d8 556 */
Kojto 90:cb3d968589d8 557
Kojto 90:cb3d968589d8 558 /** @addtogroup Exported_constants
Kojto 90:cb3d968589d8 559 * @{
Kojto 90:cb3d968589d8 560 */
Kojto 90:cb3d968589d8 561
Kojto 90:cb3d968589d8 562 /** @addtogroup Peripheral_Registers_Bits_Definition
Kojto 90:cb3d968589d8 563 * @{
Kojto 90:cb3d968589d8 564 */
Kojto 90:cb3d968589d8 565
Kojto 90:cb3d968589d8 566 /******************************************************************************/
Kojto 90:cb3d968589d8 567 /* Peripheral Registers Bits Definition */
Kojto 90:cb3d968589d8 568 /******************************************************************************/
Kojto 122:f9eeca106725 569
Kojto 90:cb3d968589d8 570 /******************************************************************************/
Kojto 90:cb3d968589d8 571 /* */
Kojto 90:cb3d968589d8 572 /* Analog to Digital Converter (ADC) */
Kojto 90:cb3d968589d8 573 /* */
Kojto 90:cb3d968589d8 574 /******************************************************************************/
Kojto 122:f9eeca106725 575
Kojto 122:f9eeca106725 576 /*
Kojto 122:f9eeca106725 577 * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
Kojto 122:f9eeca106725 578 */
Kojto 122:f9eeca106725 579 /* Note: No specific macro feature on this device */
Kojto 122:f9eeca106725 580
Kojto 90:cb3d968589d8 581 /******************** Bits definition for ADC_ISR register ******************/
Kojto 122:f9eeca106725 582 #define ADC_ISR_ADRDY_Pos (0U)
Kojto 122:f9eeca106725 583 #define ADC_ISR_ADRDY_Msk (0x1U << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 584 #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */
Kojto 122:f9eeca106725 585 #define ADC_ISR_EOSMP_Pos (1U)
Kojto 122:f9eeca106725 586 #define ADC_ISR_EOSMP_Msk (0x1U << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 587 #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */
Kojto 122:f9eeca106725 588 #define ADC_ISR_EOC_Pos (2U)
Kojto 122:f9eeca106725 589 #define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 590 #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */
Kojto 122:f9eeca106725 591 #define ADC_ISR_EOS_Pos (3U)
Kojto 122:f9eeca106725 592 #define ADC_ISR_EOS_Msk (0x1U << ADC_ISR_EOS_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 593 #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */
Kojto 122:f9eeca106725 594 #define ADC_ISR_OVR_Pos (4U)
Kojto 122:f9eeca106725 595 #define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 596 #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */
Kojto 122:f9eeca106725 597 #define ADC_ISR_AWD1_Pos (7U)
Kojto 122:f9eeca106725 598 #define ADC_ISR_AWD1_Msk (0x1U << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 599 #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */
Kojto 122:f9eeca106725 600
Kojto 122:f9eeca106725 601 /* Legacy defines */
Kojto 122:f9eeca106725 602 #define ADC_ISR_AWD (ADC_ISR_AWD1)
Kojto 122:f9eeca106725 603 #define ADC_ISR_EOSEQ (ADC_ISR_EOS)
Kojto 90:cb3d968589d8 604
Kojto 90:cb3d968589d8 605 /******************** Bits definition for ADC_IER register ******************/
Kojto 122:f9eeca106725 606 #define ADC_IER_ADRDYIE_Pos (0U)
Kojto 122:f9eeca106725 607 #define ADC_IER_ADRDYIE_Msk (0x1U << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 608 #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */
Kojto 122:f9eeca106725 609 #define ADC_IER_EOSMPIE_Pos (1U)
Kojto 122:f9eeca106725 610 #define ADC_IER_EOSMPIE_Msk (0x1U << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 611 #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */
Kojto 122:f9eeca106725 612 #define ADC_IER_EOCIE_Pos (2U)
Kojto 122:f9eeca106725 613 #define ADC_IER_EOCIE_Msk (0x1U << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 614 #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */
Kojto 122:f9eeca106725 615 #define ADC_IER_EOSIE_Pos (3U)
Kojto 122:f9eeca106725 616 #define ADC_IER_EOSIE_Msk (0x1U << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 617 #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */
Kojto 122:f9eeca106725 618 #define ADC_IER_OVRIE_Pos (4U)
Kojto 122:f9eeca106725 619 #define ADC_IER_OVRIE_Msk (0x1U << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 620 #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */
Kojto 122:f9eeca106725 621 #define ADC_IER_AWD1IE_Pos (7U)
Kojto 122:f9eeca106725 622 #define ADC_IER_AWD1IE_Msk (0x1U << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 623 #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */
Kojto 122:f9eeca106725 624
Kojto 122:f9eeca106725 625 /* Legacy defines */
Kojto 122:f9eeca106725 626 #define ADC_IER_AWDIE (ADC_IER_AWD1IE)
Kojto 122:f9eeca106725 627 #define ADC_IER_EOSEQIE (ADC_IER_EOSIE)
Kojto 90:cb3d968589d8 628
Kojto 90:cb3d968589d8 629 /******************** Bits definition for ADC_CR register *******************/
Kojto 122:f9eeca106725 630 #define ADC_CR_ADEN_Pos (0U)
Kojto 122:f9eeca106725 631 #define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 632 #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */
Kojto 122:f9eeca106725 633 #define ADC_CR_ADDIS_Pos (1U)
Kojto 122:f9eeca106725 634 #define ADC_CR_ADDIS_Msk (0x1U << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 635 #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */
Kojto 122:f9eeca106725 636 #define ADC_CR_ADSTART_Pos (2U)
Kojto 122:f9eeca106725 637 #define ADC_CR_ADSTART_Msk (0x1U << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 638 #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */
Kojto 122:f9eeca106725 639 #define ADC_CR_ADSTP_Pos (4U)
Kojto 122:f9eeca106725 640 #define ADC_CR_ADSTP_Msk (0x1U << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 641 #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */
Kojto 122:f9eeca106725 642 #define ADC_CR_ADCAL_Pos (31U)
Kojto 122:f9eeca106725 643 #define ADC_CR_ADCAL_Msk (0x1U << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 644 #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
Kojto 90:cb3d968589d8 645
Kojto 90:cb3d968589d8 646 /******************* Bits definition for ADC_CFGR1 register *****************/
Kojto 122:f9eeca106725 647 #define ADC_CFGR1_DMAEN_Pos (0U)
Kojto 122:f9eeca106725 648 #define ADC_CFGR1_DMAEN_Msk (0x1U << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 649 #define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */
Kojto 122:f9eeca106725 650 #define ADC_CFGR1_DMACFG_Pos (1U)
Kojto 122:f9eeca106725 651 #define ADC_CFGR1_DMACFG_Msk (0x1U << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 652 #define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */
Kojto 122:f9eeca106725 653 #define ADC_CFGR1_SCANDIR_Pos (2U)
Kojto 122:f9eeca106725 654 #define ADC_CFGR1_SCANDIR_Msk (0x1U << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 655 #define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */
Kojto 122:f9eeca106725 656
Kojto 122:f9eeca106725 657 #define ADC_CFGR1_RES_Pos (3U)
Kojto 122:f9eeca106725 658 #define ADC_CFGR1_RES_Msk (0x3U << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */
Kojto 122:f9eeca106725 659 #define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC data resolution */
Kojto 122:f9eeca106725 660 #define ADC_CFGR1_RES_0 (0x1U << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 661 #define ADC_CFGR1_RES_1 (0x2U << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 662
Kojto 122:f9eeca106725 663 #define ADC_CFGR1_ALIGN_Pos (5U)
Kojto 122:f9eeca106725 664 #define ADC_CFGR1_ALIGN_Msk (0x1U << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 665 #define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignement */
Kojto 122:f9eeca106725 666
Kojto 122:f9eeca106725 667 #define ADC_CFGR1_EXTSEL_Pos (6U)
Kojto 122:f9eeca106725 668 #define ADC_CFGR1_EXTSEL_Msk (0x7U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */
Kojto 122:f9eeca106725 669 #define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */
Kojto 122:f9eeca106725 670 #define ADC_CFGR1_EXTSEL_0 (0x1U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 671 #define ADC_CFGR1_EXTSEL_1 (0x2U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 672 #define ADC_CFGR1_EXTSEL_2 (0x4U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 673
Kojto 122:f9eeca106725 674 #define ADC_CFGR1_EXTEN_Pos (10U)
Kojto 122:f9eeca106725 675 #define ADC_CFGR1_EXTEN_Msk (0x3U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */
Kojto 122:f9eeca106725 676 #define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */
Kojto 122:f9eeca106725 677 #define ADC_CFGR1_EXTEN_0 (0x1U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 678 #define ADC_CFGR1_EXTEN_1 (0x2U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 679
Kojto 122:f9eeca106725 680 #define ADC_CFGR1_OVRMOD_Pos (12U)
Kojto 122:f9eeca106725 681 #define ADC_CFGR1_OVRMOD_Msk (0x1U << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 682 #define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */
Kojto 122:f9eeca106725 683 #define ADC_CFGR1_CONT_Pos (13U)
Kojto 122:f9eeca106725 684 #define ADC_CFGR1_CONT_Msk (0x1U << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 685 #define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */
Kojto 122:f9eeca106725 686 #define ADC_CFGR1_WAIT_Pos (14U)
Kojto 122:f9eeca106725 687 #define ADC_CFGR1_WAIT_Msk (0x1U << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 688 #define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC low power auto wait */
Kojto 122:f9eeca106725 689 #define ADC_CFGR1_AUTOFF_Pos (15U)
Kojto 122:f9eeca106725 690 #define ADC_CFGR1_AUTOFF_Msk (0x1U << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 691 #define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC low power auto power off */
Kojto 122:f9eeca106725 692 #define ADC_CFGR1_DISCEN_Pos (16U)
Kojto 122:f9eeca106725 693 #define ADC_CFGR1_DISCEN_Msk (0x1U << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 694 #define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
Kojto 122:f9eeca106725 695
Kojto 122:f9eeca106725 696 #define ADC_CFGR1_AWD1SGL_Pos (22U)
Kojto 122:f9eeca106725 697 #define ADC_CFGR1_AWD1SGL_Msk (0x1U << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 698 #define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
Kojto 122:f9eeca106725 699 #define ADC_CFGR1_AWD1EN_Pos (23U)
Kojto 122:f9eeca106725 700 #define ADC_CFGR1_AWD1EN_Msk (0x1U << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 701 #define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
Kojto 122:f9eeca106725 702
Kojto 122:f9eeca106725 703 #define ADC_CFGR1_AWD1CH_Pos (26U)
Kojto 122:f9eeca106725 704 #define ADC_CFGR1_AWD1CH_Msk (0x1FU << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */
Kojto 122:f9eeca106725 705 #define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
Kojto 122:f9eeca106725 706 #define ADC_CFGR1_AWD1CH_0 (0x01U << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 707 #define ADC_CFGR1_AWD1CH_1 (0x02U << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 708 #define ADC_CFGR1_AWD1CH_2 (0x04U << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 709 #define ADC_CFGR1_AWD1CH_3 (0x08U << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 710 #define ADC_CFGR1_AWD1CH_4 (0x10U << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 711
Kojto 122:f9eeca106725 712 /* Legacy defines */
Kojto 122:f9eeca106725 713 #define ADC_CFGR1_AUTDLY (ADC_CFGR1_WAIT)
Kojto 122:f9eeca106725 714 #define ADC_CFGR1_AWDSGL (ADC_CFGR1_AWD1SGL)
Kojto 122:f9eeca106725 715 #define ADC_CFGR1_AWDEN (ADC_CFGR1_AWD1EN)
Kojto 122:f9eeca106725 716 #define ADC_CFGR1_AWDCH (ADC_CFGR1_AWD1CH)
Kojto 122:f9eeca106725 717 #define ADC_CFGR1_AWDCH_0 (ADC_CFGR1_AWD1CH_0)
Kojto 122:f9eeca106725 718 #define ADC_CFGR1_AWDCH_1 (ADC_CFGR1_AWD1CH_1)
Kojto 122:f9eeca106725 719 #define ADC_CFGR1_AWDCH_2 (ADC_CFGR1_AWD1CH_2)
Kojto 122:f9eeca106725 720 #define ADC_CFGR1_AWDCH_3 (ADC_CFGR1_AWD1CH_3)
Kojto 122:f9eeca106725 721 #define ADC_CFGR1_AWDCH_4 (ADC_CFGR1_AWD1CH_4)
Kojto 90:cb3d968589d8 722
Kojto 90:cb3d968589d8 723 /******************* Bits definition for ADC_CFGR2 register *****************/
Kojto 122:f9eeca106725 724 #define ADC_CFGR2_CKMODE_Pos (30U)
Kojto 122:f9eeca106725 725 #define ADC_CFGR2_CKMODE_Msk (0x3U << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */
Kojto 122:f9eeca106725 726 #define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< ADC clock source and prescaler (prescaler only for clock source synchronous) */
Kojto 122:f9eeca106725 727 #define ADC_CFGR2_CKMODE_1 (0x2U << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 728 #define ADC_CFGR2_CKMODE_0 (0x1U << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 729
Kojto 122:f9eeca106725 730 /* Legacy defines */
Kojto 122:f9eeca106725 731 #define ADC_CFGR2_JITOFFDIV4 (ADC_CFGR2_CKMODE_1) /*!< ADC clocked by PCLK div4 */
Kojto 122:f9eeca106725 732 #define ADC_CFGR2_JITOFFDIV2 (ADC_CFGR2_CKMODE_0) /*!< ADC clocked by PCLK div2 */
Kojto 90:cb3d968589d8 733
Kojto 90:cb3d968589d8 734 /****************** Bit definition for ADC_SMPR register ********************/
Kojto 122:f9eeca106725 735 #define ADC_SMPR_SMP_Pos (0U)
Kojto 122:f9eeca106725 736 #define ADC_SMPR_SMP_Msk (0x7U << ADC_SMPR_SMP_Pos) /*!< 0x00000007 */
Kojto 122:f9eeca106725 737 #define ADC_SMPR_SMP ADC_SMPR_SMP_Msk /*!< ADC group of channels sampling time 2 */
Kojto 122:f9eeca106725 738 #define ADC_SMPR_SMP_0 (0x1U << ADC_SMPR_SMP_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 739 #define ADC_SMPR_SMP_1 (0x2U << ADC_SMPR_SMP_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 740 #define ADC_SMPR_SMP_2 (0x4U << ADC_SMPR_SMP_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 741
Kojto 122:f9eeca106725 742 /* Legacy defines */
Kojto 122:f9eeca106725 743 #define ADC_SMPR1_SMPR (ADC_SMPR_SMP) /*!< SMP[2:0] bits (Sampling time selection) */
Kojto 122:f9eeca106725 744 #define ADC_SMPR1_SMPR_0 (ADC_SMPR_SMP_0) /*!< bit 0 */
Kojto 122:f9eeca106725 745 #define ADC_SMPR1_SMPR_1 (ADC_SMPR_SMP_1) /*!< bit 1 */
Kojto 122:f9eeca106725 746 #define ADC_SMPR1_SMPR_2 (ADC_SMPR_SMP_2) /*!< bit 2 */
Kojto 90:cb3d968589d8 747
Kojto 90:cb3d968589d8 748 /******************* Bit definition for ADC_TR register ********************/
Kojto 122:f9eeca106725 749 #define ADC_TR1_LT1_Pos (0U)
Kojto 122:f9eeca106725 750 #define ADC_TR1_LT1_Msk (0xFFFU << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */
Kojto 122:f9eeca106725 751 #define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */
Kojto 122:f9eeca106725 752 #define ADC_TR1_LT1_0 (0x001U << ADC_TR1_LT1_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 753 #define ADC_TR1_LT1_1 (0x002U << ADC_TR1_LT1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 754 #define ADC_TR1_LT1_2 (0x004U << ADC_TR1_LT1_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 755 #define ADC_TR1_LT1_3 (0x008U << ADC_TR1_LT1_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 756 #define ADC_TR1_LT1_4 (0x010U << ADC_TR1_LT1_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 757 #define ADC_TR1_LT1_5 (0x020U << ADC_TR1_LT1_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 758 #define ADC_TR1_LT1_6 (0x040U << ADC_TR1_LT1_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 759 #define ADC_TR1_LT1_7 (0x080U << ADC_TR1_LT1_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 760 #define ADC_TR1_LT1_8 (0x100U << ADC_TR1_LT1_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 761 #define ADC_TR1_LT1_9 (0x200U << ADC_TR1_LT1_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 762 #define ADC_TR1_LT1_10 (0x400U << ADC_TR1_LT1_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 763 #define ADC_TR1_LT1_11 (0x800U << ADC_TR1_LT1_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 764
Kojto 122:f9eeca106725 765 #define ADC_TR1_HT1_Pos (16U)
Kojto 122:f9eeca106725 766 #define ADC_TR1_HT1_Msk (0xFFFU << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */
Kojto 122:f9eeca106725 767 #define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */
Kojto 122:f9eeca106725 768 #define ADC_TR1_HT1_0 (0x001U << ADC_TR1_HT1_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 769 #define ADC_TR1_HT1_1 (0x002U << ADC_TR1_HT1_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 770 #define ADC_TR1_HT1_2 (0x004U << ADC_TR1_HT1_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 771 #define ADC_TR1_HT1_3 (0x008U << ADC_TR1_HT1_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 772 #define ADC_TR1_HT1_4 (0x010U << ADC_TR1_HT1_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 773 #define ADC_TR1_HT1_5 (0x020U << ADC_TR1_HT1_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 774 #define ADC_TR1_HT1_6 (0x040U << ADC_TR1_HT1_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 775 #define ADC_TR1_HT1_7 (0x080U << ADC_TR1_HT1_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 776 #define ADC_TR1_HT1_8 (0x100U << ADC_TR1_HT1_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 777 #define ADC_TR1_HT1_9 (0x200U << ADC_TR1_HT1_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 778 #define ADC_TR1_HT1_10 (0x400U << ADC_TR1_HT1_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 779 #define ADC_TR1_HT1_11 (0x800U << ADC_TR1_HT1_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 780
Kojto 122:f9eeca106725 781 /* Legacy defines */
Kojto 122:f9eeca106725 782 #define ADC_TR_HT (ADC_TR1_HT1)
Kojto 122:f9eeca106725 783 #define ADC_TR_LT (ADC_TR1_LT1)
Kojto 122:f9eeca106725 784 #define ADC_HTR_HT (ADC_TR1_HT1)
Kojto 122:f9eeca106725 785 #define ADC_LTR_LT (ADC_TR1_LT1)
Kojto 90:cb3d968589d8 786
Kojto 90:cb3d968589d8 787 /****************** Bit definition for ADC_CHSELR register ******************/
Kojto 122:f9eeca106725 788 #define ADC_CHSELR_CHSEL_Pos (0U)
Kojto 122:f9eeca106725 789 #define ADC_CHSELR_CHSEL_Msk (0x7FFFFU << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */
Kojto 122:f9eeca106725 790 #define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */
Kojto 122:f9eeca106725 791 #define ADC_CHSELR_CHSEL18_Pos (18U)
Kojto 122:f9eeca106725 792 #define ADC_CHSELR_CHSEL18_Msk (0x1U << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 793 #define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */
Kojto 122:f9eeca106725 794 #define ADC_CHSELR_CHSEL17_Pos (17U)
Kojto 122:f9eeca106725 795 #define ADC_CHSELR_CHSEL17_Msk (0x1U << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 796 #define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */
Kojto 122:f9eeca106725 797 #define ADC_CHSELR_CHSEL16_Pos (16U)
Kojto 122:f9eeca106725 798 #define ADC_CHSELR_CHSEL16_Msk (0x1U << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 799 #define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */
Kojto 122:f9eeca106725 800 #define ADC_CHSELR_CHSEL15_Pos (15U)
Kojto 122:f9eeca106725 801 #define ADC_CHSELR_CHSEL15_Msk (0x1U << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 802 #define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */
Kojto 122:f9eeca106725 803 #define ADC_CHSELR_CHSEL14_Pos (14U)
Kojto 122:f9eeca106725 804 #define ADC_CHSELR_CHSEL14_Msk (0x1U << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 805 #define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */
Kojto 122:f9eeca106725 806 #define ADC_CHSELR_CHSEL13_Pos (13U)
Kojto 122:f9eeca106725 807 #define ADC_CHSELR_CHSEL13_Msk (0x1U << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 808 #define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */
Kojto 122:f9eeca106725 809 #define ADC_CHSELR_CHSEL12_Pos (12U)
Kojto 122:f9eeca106725 810 #define ADC_CHSELR_CHSEL12_Msk (0x1U << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 811 #define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */
Kojto 122:f9eeca106725 812 #define ADC_CHSELR_CHSEL11_Pos (11U)
Kojto 122:f9eeca106725 813 #define ADC_CHSELR_CHSEL11_Msk (0x1U << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 814 #define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */
Kojto 122:f9eeca106725 815 #define ADC_CHSELR_CHSEL10_Pos (10U)
Kojto 122:f9eeca106725 816 #define ADC_CHSELR_CHSEL10_Msk (0x1U << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 817 #define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */
Kojto 122:f9eeca106725 818 #define ADC_CHSELR_CHSEL9_Pos (9U)
Kojto 122:f9eeca106725 819 #define ADC_CHSELR_CHSEL9_Msk (0x1U << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 820 #define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */
Kojto 122:f9eeca106725 821 #define ADC_CHSELR_CHSEL8_Pos (8U)
Kojto 122:f9eeca106725 822 #define ADC_CHSELR_CHSEL8_Msk (0x1U << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 823 #define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */
Kojto 122:f9eeca106725 824 #define ADC_CHSELR_CHSEL7_Pos (7U)
Kojto 122:f9eeca106725 825 #define ADC_CHSELR_CHSEL7_Msk (0x1U << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 826 #define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */
Kojto 122:f9eeca106725 827 #define ADC_CHSELR_CHSEL6_Pos (6U)
Kojto 122:f9eeca106725 828 #define ADC_CHSELR_CHSEL6_Msk (0x1U << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 829 #define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */
Kojto 122:f9eeca106725 830 #define ADC_CHSELR_CHSEL5_Pos (5U)
Kojto 122:f9eeca106725 831 #define ADC_CHSELR_CHSEL5_Msk (0x1U << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 832 #define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */
Kojto 122:f9eeca106725 833 #define ADC_CHSELR_CHSEL4_Pos (4U)
Kojto 122:f9eeca106725 834 #define ADC_CHSELR_CHSEL4_Msk (0x1U << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 835 #define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */
Kojto 122:f9eeca106725 836 #define ADC_CHSELR_CHSEL3_Pos (3U)
Kojto 122:f9eeca106725 837 #define ADC_CHSELR_CHSEL3_Msk (0x1U << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 838 #define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */
Kojto 122:f9eeca106725 839 #define ADC_CHSELR_CHSEL2_Pos (2U)
Kojto 122:f9eeca106725 840 #define ADC_CHSELR_CHSEL2_Msk (0x1U << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 841 #define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */
Kojto 122:f9eeca106725 842 #define ADC_CHSELR_CHSEL1_Pos (1U)
Kojto 122:f9eeca106725 843 #define ADC_CHSELR_CHSEL1_Msk (0x1U << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 844 #define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */
Kojto 122:f9eeca106725 845 #define ADC_CHSELR_CHSEL0_Pos (0U)
Kojto 122:f9eeca106725 846 #define ADC_CHSELR_CHSEL0_Msk (0x1U << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 847 #define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */
Kojto 90:cb3d968589d8 848
Kojto 90:cb3d968589d8 849 /******************** Bit definition for ADC_DR register ********************/
Kojto 122:f9eeca106725 850 #define ADC_DR_DATA_Pos (0U)
Kojto 122:f9eeca106725 851 #define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 852 #define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */
Kojto 122:f9eeca106725 853 #define ADC_DR_DATA_0 (0x0001U << ADC_DR_DATA_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 854 #define ADC_DR_DATA_1 (0x0002U << ADC_DR_DATA_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 855 #define ADC_DR_DATA_2 (0x0004U << ADC_DR_DATA_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 856 #define ADC_DR_DATA_3 (0x0008U << ADC_DR_DATA_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 857 #define ADC_DR_DATA_4 (0x0010U << ADC_DR_DATA_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 858 #define ADC_DR_DATA_5 (0x0020U << ADC_DR_DATA_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 859 #define ADC_DR_DATA_6 (0x0040U << ADC_DR_DATA_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 860 #define ADC_DR_DATA_7 (0x0080U << ADC_DR_DATA_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 861 #define ADC_DR_DATA_8 (0x0100U << ADC_DR_DATA_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 862 #define ADC_DR_DATA_9 (0x0200U << ADC_DR_DATA_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 863 #define ADC_DR_DATA_10 (0x0400U << ADC_DR_DATA_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 864 #define ADC_DR_DATA_11 (0x0800U << ADC_DR_DATA_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 865 #define ADC_DR_DATA_12 (0x1000U << ADC_DR_DATA_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 866 #define ADC_DR_DATA_13 (0x2000U << ADC_DR_DATA_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 867 #define ADC_DR_DATA_14 (0x4000U << ADC_DR_DATA_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 868 #define ADC_DR_DATA_15 (0x8000U << ADC_DR_DATA_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 869
Kojto 122:f9eeca106725 870 /************************* ADC Common registers *****************************/
Kojto 90:cb3d968589d8 871 /******************* Bit definition for ADC_CCR register ********************/
Kojto 122:f9eeca106725 872 #define ADC_CCR_VREFEN_Pos (22U)
Kojto 122:f9eeca106725 873 #define ADC_CCR_VREFEN_Msk (0x1U << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 874 #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */
Kojto 122:f9eeca106725 875 #define ADC_CCR_TSEN_Pos (23U)
Kojto 122:f9eeca106725 876 #define ADC_CCR_TSEN_Msk (0x1U << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 877 #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */
Kojto 122:f9eeca106725 878
Kojto 90:cb3d968589d8 879
Kojto 90:cb3d968589d8 880 /******************************************************************************/
Kojto 90:cb3d968589d8 881 /* */
Kojto 90:cb3d968589d8 882 /* CRC calculation unit (CRC) */
Kojto 90:cb3d968589d8 883 /* */
Kojto 90:cb3d968589d8 884 /******************************************************************************/
Kojto 90:cb3d968589d8 885 /******************* Bit definition for CRC_DR register *********************/
Kojto 122:f9eeca106725 886 #define CRC_DR_DR_Pos (0U)
Kojto 122:f9eeca106725 887 #define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 888 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
Kojto 90:cb3d968589d8 889
Kojto 90:cb3d968589d8 890 /******************* Bit definition for CRC_IDR register ********************/
Kojto 122:f9eeca106725 891 #define CRC_IDR_IDR ((uint8_t)0xFFU) /*!< General-purpose 8-bit data register bits */
Kojto 90:cb3d968589d8 892
Kojto 90:cb3d968589d8 893 /******************** Bit definition for CRC_CR register ********************/
Kojto 122:f9eeca106725 894 #define CRC_CR_RESET_Pos (0U)
Kojto 122:f9eeca106725 895 #define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 896 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
Kojto 122:f9eeca106725 897 #define CRC_CR_REV_IN_Pos (5U)
Kojto 122:f9eeca106725 898 #define CRC_CR_REV_IN_Msk (0x3U << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
Kojto 122:f9eeca106725 899 #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
Kojto 122:f9eeca106725 900 #define CRC_CR_REV_IN_0 (0x1U << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 901 #define CRC_CR_REV_IN_1 (0x2U << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 902 #define CRC_CR_REV_OUT_Pos (7U)
Kojto 122:f9eeca106725 903 #define CRC_CR_REV_OUT_Msk (0x1U << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 904 #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
Kojto 90:cb3d968589d8 905
Kojto 90:cb3d968589d8 906 /******************* Bit definition for CRC_INIT register *******************/
Kojto 122:f9eeca106725 907 #define CRC_INIT_INIT_Pos (0U)
Kojto 122:f9eeca106725 908 #define CRC_INIT_INIT_Msk (0xFFFFFFFFU << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 909 #define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
Kojto 90:cb3d968589d8 910
Kojto 90:cb3d968589d8 911 /******************************************************************************/
Kojto 90:cb3d968589d8 912 /* */
Kojto 90:cb3d968589d8 913 /* Debug MCU (DBGMCU) */
Kojto 90:cb3d968589d8 914 /* */
Kojto 90:cb3d968589d8 915 /******************************************************************************/
Kojto 90:cb3d968589d8 916
Kojto 90:cb3d968589d8 917 /**************** Bit definition for DBGMCU_IDCODE register *****************/
Kojto 122:f9eeca106725 918 #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
Kojto 122:f9eeca106725 919 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
Kojto 122:f9eeca106725 920 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */
Kojto 122:f9eeca106725 921
Kojto 122:f9eeca106725 922 #define DBGMCU_IDCODE_REV_ID_Pos (16U)
Kojto 122:f9eeca106725 923 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
Kojto 122:f9eeca106725 924 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */
Kojto 122:f9eeca106725 925 #define DBGMCU_IDCODE_REV_ID_0 (0x0001U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 926 #define DBGMCU_IDCODE_REV_ID_1 (0x0002U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 927 #define DBGMCU_IDCODE_REV_ID_2 (0x0004U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 928 #define DBGMCU_IDCODE_REV_ID_3 (0x0008U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 929 #define DBGMCU_IDCODE_REV_ID_4 (0x0010U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 930 #define DBGMCU_IDCODE_REV_ID_5 (0x0020U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 931 #define DBGMCU_IDCODE_REV_ID_6 (0x0040U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 932 #define DBGMCU_IDCODE_REV_ID_7 (0x0080U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 933 #define DBGMCU_IDCODE_REV_ID_8 (0x0100U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 934 #define DBGMCU_IDCODE_REV_ID_9 (0x0200U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 935 #define DBGMCU_IDCODE_REV_ID_10 (0x0400U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 936 #define DBGMCU_IDCODE_REV_ID_11 (0x0800U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 937 #define DBGMCU_IDCODE_REV_ID_12 (0x1000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 938 #define DBGMCU_IDCODE_REV_ID_13 (0x2000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 939 #define DBGMCU_IDCODE_REV_ID_14 (0x4000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 940 #define DBGMCU_IDCODE_REV_ID_15 (0x8000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
Kojto 90:cb3d968589d8 941
Kojto 90:cb3d968589d8 942 /****************** Bit definition for DBGMCU_CR register *******************/
Kojto 122:f9eeca106725 943 #define DBGMCU_CR_DBG_STOP_Pos (1U)
Kojto 122:f9eeca106725 944 #define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 945 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */
Kojto 122:f9eeca106725 946 #define DBGMCU_CR_DBG_STANDBY_Pos (2U)
Kojto 122:f9eeca106725 947 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 948 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */
Kojto 90:cb3d968589d8 949
Kojto 90:cb3d968589d8 950 /****************** Bit definition for DBGMCU_APB1_FZ register **************/
Kojto 122:f9eeca106725 951 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
Kojto 122:f9eeca106725 952 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 953 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */
Kojto 122:f9eeca106725 954 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
Kojto 122:f9eeca106725 955 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 956 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
Kojto 122:f9eeca106725 957 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U)
Kojto 122:f9eeca106725 958 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 959 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk /*!< TIM14 counter stopped when core is halted */
Kojto 122:f9eeca106725 960 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
Kojto 122:f9eeca106725 961 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 962 #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */
Kojto 122:f9eeca106725 963 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
Kojto 122:f9eeca106725 964 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 965 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
Kojto 122:f9eeca106725 966 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
Kojto 122:f9eeca106725 967 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 968 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
Kojto 122:f9eeca106725 969 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
Kojto 122:f9eeca106725 970 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 971 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
Kojto 90:cb3d968589d8 972
Kojto 90:cb3d968589d8 973 /****************** Bit definition for DBGMCU_APB2_FZ register **************/
Kojto 122:f9eeca106725 974 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (11U)
Kojto 122:f9eeca106725 975 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 976 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk /*!< TIM1 counter stopped when core is halted */
Kojto 122:f9eeca106725 977 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP_Pos (16U)
Kojto 122:f9eeca106725 978 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM15_STOP_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 979 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP DBGMCU_APB2_FZ_DBG_TIM15_STOP_Msk /*!< TIM15 counter stopped when core is halted */
Kojto 122:f9eeca106725 980 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos (17U)
Kojto 122:f9eeca106725 981 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 982 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk /*!< TIM16 counter stopped when core is halted */
Kojto 122:f9eeca106725 983 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos (18U)
Kojto 122:f9eeca106725 984 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 985 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk /*!< TIM17 counter stopped when core is halted */
Kojto 90:cb3d968589d8 986
Kojto 90:cb3d968589d8 987 /******************************************************************************/
Kojto 90:cb3d968589d8 988 /* */
Kojto 90:cb3d968589d8 989 /* DMA Controller (DMA) */
Kojto 90:cb3d968589d8 990 /* */
Kojto 90:cb3d968589d8 991 /******************************************************************************/
Kojto 90:cb3d968589d8 992 /******************* Bit definition for DMA_ISR register ********************/
Kojto 122:f9eeca106725 993 #define DMA_ISR_GIF1_Pos (0U)
Kojto 122:f9eeca106725 994 #define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 995 #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
Kojto 122:f9eeca106725 996 #define DMA_ISR_TCIF1_Pos (1U)
Kojto 122:f9eeca106725 997 #define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 998 #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
Kojto 122:f9eeca106725 999 #define DMA_ISR_HTIF1_Pos (2U)
Kojto 122:f9eeca106725 1000 #define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1001 #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
Kojto 122:f9eeca106725 1002 #define DMA_ISR_TEIF1_Pos (3U)
Kojto 122:f9eeca106725 1003 #define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1004 #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
Kojto 122:f9eeca106725 1005 #define DMA_ISR_GIF2_Pos (4U)
Kojto 122:f9eeca106725 1006 #define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1007 #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
Kojto 122:f9eeca106725 1008 #define DMA_ISR_TCIF2_Pos (5U)
Kojto 122:f9eeca106725 1009 #define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 1010 #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
Kojto 122:f9eeca106725 1011 #define DMA_ISR_HTIF2_Pos (6U)
Kojto 122:f9eeca106725 1012 #define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 1013 #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
Kojto 122:f9eeca106725 1014 #define DMA_ISR_TEIF2_Pos (7U)
Kojto 122:f9eeca106725 1015 #define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 1016 #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
Kojto 122:f9eeca106725 1017 #define DMA_ISR_GIF3_Pos (8U)
Kojto 122:f9eeca106725 1018 #define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 1019 #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
Kojto 122:f9eeca106725 1020 #define DMA_ISR_TCIF3_Pos (9U)
Kojto 122:f9eeca106725 1021 #define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 1022 #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
Kojto 122:f9eeca106725 1023 #define DMA_ISR_HTIF3_Pos (10U)
Kojto 122:f9eeca106725 1024 #define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 1025 #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
Kojto 122:f9eeca106725 1026 #define DMA_ISR_TEIF3_Pos (11U)
Kojto 122:f9eeca106725 1027 #define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 1028 #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
Kojto 122:f9eeca106725 1029 #define DMA_ISR_GIF4_Pos (12U)
Kojto 122:f9eeca106725 1030 #define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 1031 #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
Kojto 122:f9eeca106725 1032 #define DMA_ISR_TCIF4_Pos (13U)
Kojto 122:f9eeca106725 1033 #define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 1034 #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
Kojto 122:f9eeca106725 1035 #define DMA_ISR_HTIF4_Pos (14U)
Kojto 122:f9eeca106725 1036 #define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 1037 #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
Kojto 122:f9eeca106725 1038 #define DMA_ISR_TEIF4_Pos (15U)
Kojto 122:f9eeca106725 1039 #define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 1040 #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
Kojto 122:f9eeca106725 1041 #define DMA_ISR_GIF5_Pos (16U)
Kojto 122:f9eeca106725 1042 #define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 1043 #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
Kojto 122:f9eeca106725 1044 #define DMA_ISR_TCIF5_Pos (17U)
Kojto 122:f9eeca106725 1045 #define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 1046 #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
Kojto 122:f9eeca106725 1047 #define DMA_ISR_HTIF5_Pos (18U)
Kojto 122:f9eeca106725 1048 #define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 1049 #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
Kojto 122:f9eeca106725 1050 #define DMA_ISR_TEIF5_Pos (19U)
Kojto 122:f9eeca106725 1051 #define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 1052 #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
Kojto 90:cb3d968589d8 1053
Kojto 90:cb3d968589d8 1054 /******************* Bit definition for DMA_IFCR register *******************/
Kojto 122:f9eeca106725 1055 #define DMA_IFCR_CGIF1_Pos (0U)
Kojto 122:f9eeca106725 1056 #define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1057 #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
Kojto 122:f9eeca106725 1058 #define DMA_IFCR_CTCIF1_Pos (1U)
Kojto 122:f9eeca106725 1059 #define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1060 #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
Kojto 122:f9eeca106725 1061 #define DMA_IFCR_CHTIF1_Pos (2U)
Kojto 122:f9eeca106725 1062 #define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1063 #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
Kojto 122:f9eeca106725 1064 #define DMA_IFCR_CTEIF1_Pos (3U)
Kojto 122:f9eeca106725 1065 #define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1066 #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
Kojto 122:f9eeca106725 1067 #define DMA_IFCR_CGIF2_Pos (4U)
Kojto 122:f9eeca106725 1068 #define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1069 #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
Kojto 122:f9eeca106725 1070 #define DMA_IFCR_CTCIF2_Pos (5U)
Kojto 122:f9eeca106725 1071 #define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 1072 #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
Kojto 122:f9eeca106725 1073 #define DMA_IFCR_CHTIF2_Pos (6U)
Kojto 122:f9eeca106725 1074 #define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 1075 #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
Kojto 122:f9eeca106725 1076 #define DMA_IFCR_CTEIF2_Pos (7U)
Kojto 122:f9eeca106725 1077 #define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 1078 #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
Kojto 122:f9eeca106725 1079 #define DMA_IFCR_CGIF3_Pos (8U)
Kojto 122:f9eeca106725 1080 #define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 1081 #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
Kojto 122:f9eeca106725 1082 #define DMA_IFCR_CTCIF3_Pos (9U)
Kojto 122:f9eeca106725 1083 #define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 1084 #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
Kojto 122:f9eeca106725 1085 #define DMA_IFCR_CHTIF3_Pos (10U)
Kojto 122:f9eeca106725 1086 #define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 1087 #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
Kojto 122:f9eeca106725 1088 #define DMA_IFCR_CTEIF3_Pos (11U)
Kojto 122:f9eeca106725 1089 #define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 1090 #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
Kojto 122:f9eeca106725 1091 #define DMA_IFCR_CGIF4_Pos (12U)
Kojto 122:f9eeca106725 1092 #define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 1093 #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
Kojto 122:f9eeca106725 1094 #define DMA_IFCR_CTCIF4_Pos (13U)
Kojto 122:f9eeca106725 1095 #define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 1096 #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
Kojto 122:f9eeca106725 1097 #define DMA_IFCR_CHTIF4_Pos (14U)
Kojto 122:f9eeca106725 1098 #define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 1099 #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
Kojto 122:f9eeca106725 1100 #define DMA_IFCR_CTEIF4_Pos (15U)
Kojto 122:f9eeca106725 1101 #define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 1102 #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
Kojto 122:f9eeca106725 1103 #define DMA_IFCR_CGIF5_Pos (16U)
Kojto 122:f9eeca106725 1104 #define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 1105 #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
Kojto 122:f9eeca106725 1106 #define DMA_IFCR_CTCIF5_Pos (17U)
Kojto 122:f9eeca106725 1107 #define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 1108 #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
Kojto 122:f9eeca106725 1109 #define DMA_IFCR_CHTIF5_Pos (18U)
Kojto 122:f9eeca106725 1110 #define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 1111 #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
Kojto 122:f9eeca106725 1112 #define DMA_IFCR_CTEIF5_Pos (19U)
Kojto 122:f9eeca106725 1113 #define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 1114 #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
Kojto 90:cb3d968589d8 1115
Kojto 90:cb3d968589d8 1116 /******************* Bit definition for DMA_CCR register ********************/
Kojto 122:f9eeca106725 1117 #define DMA_CCR_EN_Pos (0U)
Kojto 122:f9eeca106725 1118 #define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1119 #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
Kojto 122:f9eeca106725 1120 #define DMA_CCR_TCIE_Pos (1U)
Kojto 122:f9eeca106725 1121 #define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1122 #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
Kojto 122:f9eeca106725 1123 #define DMA_CCR_HTIE_Pos (2U)
Kojto 122:f9eeca106725 1124 #define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1125 #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
Kojto 122:f9eeca106725 1126 #define DMA_CCR_TEIE_Pos (3U)
Kojto 122:f9eeca106725 1127 #define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1128 #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
Kojto 122:f9eeca106725 1129 #define DMA_CCR_DIR_Pos (4U)
Kojto 122:f9eeca106725 1130 #define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1131 #define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
Kojto 122:f9eeca106725 1132 #define DMA_CCR_CIRC_Pos (5U)
Kojto 122:f9eeca106725 1133 #define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 1134 #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
Kojto 122:f9eeca106725 1135 #define DMA_CCR_PINC_Pos (6U)
Kojto 122:f9eeca106725 1136 #define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 1137 #define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
Kojto 122:f9eeca106725 1138 #define DMA_CCR_MINC_Pos (7U)
Kojto 122:f9eeca106725 1139 #define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 1140 #define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
Kojto 122:f9eeca106725 1141
Kojto 122:f9eeca106725 1142 #define DMA_CCR_PSIZE_Pos (8U)
Kojto 122:f9eeca106725 1143 #define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
Kojto 122:f9eeca106725 1144 #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
Kojto 122:f9eeca106725 1145 #define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 1146 #define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 1147
Kojto 122:f9eeca106725 1148 #define DMA_CCR_MSIZE_Pos (10U)
Kojto 122:f9eeca106725 1149 #define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
Kojto 122:f9eeca106725 1150 #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
Kojto 122:f9eeca106725 1151 #define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 1152 #define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 1153
Kojto 122:f9eeca106725 1154 #define DMA_CCR_PL_Pos (12U)
Kojto 122:f9eeca106725 1155 #define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */
Kojto 122:f9eeca106725 1156 #define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
Kojto 122:f9eeca106725 1157 #define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 1158 #define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 1159
Kojto 122:f9eeca106725 1160 #define DMA_CCR_MEM2MEM_Pos (14U)
Kojto 122:f9eeca106725 1161 #define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 1162 #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
Kojto 90:cb3d968589d8 1163
Kojto 90:cb3d968589d8 1164 /****************** Bit definition for DMA_CNDTR register *******************/
Kojto 122:f9eeca106725 1165 #define DMA_CNDTR_NDT_Pos (0U)
Kojto 122:f9eeca106725 1166 #define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 1167 #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
Kojto 90:cb3d968589d8 1168
Kojto 90:cb3d968589d8 1169 /****************** Bit definition for DMA_CPAR register ********************/
Kojto 122:f9eeca106725 1170 #define DMA_CPAR_PA_Pos (0U)
Kojto 122:f9eeca106725 1171 #define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 1172 #define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
Kojto 90:cb3d968589d8 1173
Kojto 90:cb3d968589d8 1174 /****************** Bit definition for DMA_CMAR register ********************/
Kojto 122:f9eeca106725 1175 #define DMA_CMAR_MA_Pos (0U)
Kojto 122:f9eeca106725 1176 #define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 1177 #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
Kojto 90:cb3d968589d8 1178
Kojto 90:cb3d968589d8 1179 /******************************************************************************/
Kojto 90:cb3d968589d8 1180 /* */
Kojto 90:cb3d968589d8 1181 /* External Interrupt/Event Controller (EXTI) */
Kojto 90:cb3d968589d8 1182 /* */
Kojto 90:cb3d968589d8 1183 /******************************************************************************/
Kojto 90:cb3d968589d8 1184 /******************* Bit definition for EXTI_IMR register *******************/
Kojto 122:f9eeca106725 1185 #define EXTI_IMR_MR0_Pos (0U)
Kojto 122:f9eeca106725 1186 #define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1187 #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
Kojto 122:f9eeca106725 1188 #define EXTI_IMR_MR1_Pos (1U)
Kojto 122:f9eeca106725 1189 #define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1190 #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
Kojto 122:f9eeca106725 1191 #define EXTI_IMR_MR2_Pos (2U)
Kojto 122:f9eeca106725 1192 #define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1193 #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
Kojto 122:f9eeca106725 1194 #define EXTI_IMR_MR3_Pos (3U)
Kojto 122:f9eeca106725 1195 #define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1196 #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
Kojto 122:f9eeca106725 1197 #define EXTI_IMR_MR4_Pos (4U)
Kojto 122:f9eeca106725 1198 #define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1199 #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
Kojto 122:f9eeca106725 1200 #define EXTI_IMR_MR5_Pos (5U)
Kojto 122:f9eeca106725 1201 #define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 1202 #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
Kojto 122:f9eeca106725 1203 #define EXTI_IMR_MR6_Pos (6U)
Kojto 122:f9eeca106725 1204 #define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 1205 #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
Kojto 122:f9eeca106725 1206 #define EXTI_IMR_MR7_Pos (7U)
Kojto 122:f9eeca106725 1207 #define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 1208 #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
Kojto 122:f9eeca106725 1209 #define EXTI_IMR_MR8_Pos (8U)
Kojto 122:f9eeca106725 1210 #define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 1211 #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
Kojto 122:f9eeca106725 1212 #define EXTI_IMR_MR9_Pos (9U)
Kojto 122:f9eeca106725 1213 #define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 1214 #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
Kojto 122:f9eeca106725 1215 #define EXTI_IMR_MR10_Pos (10U)
Kojto 122:f9eeca106725 1216 #define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 1217 #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
Kojto 122:f9eeca106725 1218 #define EXTI_IMR_MR11_Pos (11U)
Kojto 122:f9eeca106725 1219 #define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 1220 #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
Kojto 122:f9eeca106725 1221 #define EXTI_IMR_MR12_Pos (12U)
Kojto 122:f9eeca106725 1222 #define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 1223 #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
Kojto 122:f9eeca106725 1224 #define EXTI_IMR_MR13_Pos (13U)
Kojto 122:f9eeca106725 1225 #define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 1226 #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
Kojto 122:f9eeca106725 1227 #define EXTI_IMR_MR14_Pos (14U)
Kojto 122:f9eeca106725 1228 #define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 1229 #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
Kojto 122:f9eeca106725 1230 #define EXTI_IMR_MR15_Pos (15U)
Kojto 122:f9eeca106725 1231 #define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 1232 #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
Kojto 122:f9eeca106725 1233 #define EXTI_IMR_MR17_Pos (17U)
Kojto 122:f9eeca106725 1234 #define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 1235 #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
Kojto 122:f9eeca106725 1236 #define EXTI_IMR_MR18_Pos (18U)
Kojto 122:f9eeca106725 1237 #define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 1238 #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
Kojto 122:f9eeca106725 1239 #define EXTI_IMR_MR19_Pos (19U)
Kojto 122:f9eeca106725 1240 #define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 1241 #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
Kojto 122:f9eeca106725 1242 #define EXTI_IMR_MR23_Pos (23U)
Kojto 122:f9eeca106725 1243 #define EXTI_IMR_MR23_Msk (0x1U << EXTI_IMR_MR23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 1244 #define EXTI_IMR_MR23 EXTI_IMR_MR23_Msk /*!< Interrupt Mask on line 23 */
Kojto 122:f9eeca106725 1245
Kojto 122:f9eeca106725 1246 /* References Defines */
Kojto 122:f9eeca106725 1247 #define EXTI_IMR_IM0 EXTI_IMR_MR0
Kojto 122:f9eeca106725 1248 #define EXTI_IMR_IM1 EXTI_IMR_MR1
Kojto 122:f9eeca106725 1249 #define EXTI_IMR_IM2 EXTI_IMR_MR2
Kojto 122:f9eeca106725 1250 #define EXTI_IMR_IM3 EXTI_IMR_MR3
Kojto 122:f9eeca106725 1251 #define EXTI_IMR_IM4 EXTI_IMR_MR4
Kojto 122:f9eeca106725 1252 #define EXTI_IMR_IM5 EXTI_IMR_MR5
Kojto 122:f9eeca106725 1253 #define EXTI_IMR_IM6 EXTI_IMR_MR6
Kojto 122:f9eeca106725 1254 #define EXTI_IMR_IM7 EXTI_IMR_MR7
Kojto 122:f9eeca106725 1255 #define EXTI_IMR_IM8 EXTI_IMR_MR8
Kojto 122:f9eeca106725 1256 #define EXTI_IMR_IM9 EXTI_IMR_MR9
Kojto 122:f9eeca106725 1257 #define EXTI_IMR_IM10 EXTI_IMR_MR10
Kojto 122:f9eeca106725 1258 #define EXTI_IMR_IM11 EXTI_IMR_MR11
Kojto 122:f9eeca106725 1259 #define EXTI_IMR_IM12 EXTI_IMR_MR12
Kojto 122:f9eeca106725 1260 #define EXTI_IMR_IM13 EXTI_IMR_MR13
Kojto 122:f9eeca106725 1261 #define EXTI_IMR_IM14 EXTI_IMR_MR14
Kojto 122:f9eeca106725 1262 #define EXTI_IMR_IM15 EXTI_IMR_MR15
Kojto 122:f9eeca106725 1263 #define EXTI_IMR_IM17 EXTI_IMR_MR17
Kojto 122:f9eeca106725 1264 #define EXTI_IMR_IM18 EXTI_IMR_MR18
Kojto 122:f9eeca106725 1265 #define EXTI_IMR_IM19 EXTI_IMR_MR19
Kojto 122:f9eeca106725 1266 #define EXTI_IMR_IM23 EXTI_IMR_MR23
Kojto 122:f9eeca106725 1267
Kojto 122:f9eeca106725 1268 #define EXTI_IMR_IM_Pos (0U)
Kojto 122:f9eeca106725 1269 #define EXTI_IMR_IM_Msk (0x8EFFFFU << EXTI_IMR_IM_Pos) /*!< 0x008EFFFF */
Kojto 122:f9eeca106725 1270 #define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
Kojto 122:f9eeca106725 1271
Kojto 90:cb3d968589d8 1272
Kojto 90:cb3d968589d8 1273 /****************** Bit definition for EXTI_EMR register ********************/
Kojto 122:f9eeca106725 1274 #define EXTI_EMR_MR0_Pos (0U)
Kojto 122:f9eeca106725 1275 #define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1276 #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
Kojto 122:f9eeca106725 1277 #define EXTI_EMR_MR1_Pos (1U)
Kojto 122:f9eeca106725 1278 #define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1279 #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
Kojto 122:f9eeca106725 1280 #define EXTI_EMR_MR2_Pos (2U)
Kojto 122:f9eeca106725 1281 #define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1282 #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
Kojto 122:f9eeca106725 1283 #define EXTI_EMR_MR3_Pos (3U)
Kojto 122:f9eeca106725 1284 #define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1285 #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
Kojto 122:f9eeca106725 1286 #define EXTI_EMR_MR4_Pos (4U)
Kojto 122:f9eeca106725 1287 #define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1288 #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
Kojto 122:f9eeca106725 1289 #define EXTI_EMR_MR5_Pos (5U)
Kojto 122:f9eeca106725 1290 #define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 1291 #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
Kojto 122:f9eeca106725 1292 #define EXTI_EMR_MR6_Pos (6U)
Kojto 122:f9eeca106725 1293 #define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 1294 #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
Kojto 122:f9eeca106725 1295 #define EXTI_EMR_MR7_Pos (7U)
Kojto 122:f9eeca106725 1296 #define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 1297 #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
Kojto 122:f9eeca106725 1298 #define EXTI_EMR_MR8_Pos (8U)
Kojto 122:f9eeca106725 1299 #define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 1300 #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
Kojto 122:f9eeca106725 1301 #define EXTI_EMR_MR9_Pos (9U)
Kojto 122:f9eeca106725 1302 #define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 1303 #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
Kojto 122:f9eeca106725 1304 #define EXTI_EMR_MR10_Pos (10U)
Kojto 122:f9eeca106725 1305 #define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 1306 #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
Kojto 122:f9eeca106725 1307 #define EXTI_EMR_MR11_Pos (11U)
Kojto 122:f9eeca106725 1308 #define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 1309 #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
Kojto 122:f9eeca106725 1310 #define EXTI_EMR_MR12_Pos (12U)
Kojto 122:f9eeca106725 1311 #define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 1312 #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
Kojto 122:f9eeca106725 1313 #define EXTI_EMR_MR13_Pos (13U)
Kojto 122:f9eeca106725 1314 #define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 1315 #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
Kojto 122:f9eeca106725 1316 #define EXTI_EMR_MR14_Pos (14U)
Kojto 122:f9eeca106725 1317 #define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 1318 #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
Kojto 122:f9eeca106725 1319 #define EXTI_EMR_MR15_Pos (15U)
Kojto 122:f9eeca106725 1320 #define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 1321 #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
Kojto 122:f9eeca106725 1322 #define EXTI_EMR_MR17_Pos (17U)
Kojto 122:f9eeca106725 1323 #define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 1324 #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
Kojto 122:f9eeca106725 1325 #define EXTI_EMR_MR18_Pos (18U)
Kojto 122:f9eeca106725 1326 #define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 1327 #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
Kojto 122:f9eeca106725 1328 #define EXTI_EMR_MR19_Pos (19U)
Kojto 122:f9eeca106725 1329 #define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 1330 #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
Kojto 122:f9eeca106725 1331 #define EXTI_EMR_MR23_Pos (23U)
Kojto 122:f9eeca106725 1332 #define EXTI_EMR_MR23_Msk (0x1U << EXTI_EMR_MR23_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 1333 #define EXTI_EMR_MR23 EXTI_EMR_MR23_Msk /*!< Event Mask on line 23 */
Kojto 122:f9eeca106725 1334
Kojto 122:f9eeca106725 1335 /* References Defines */
Kojto 122:f9eeca106725 1336 #define EXTI_EMR_EM0 EXTI_EMR_MR0
Kojto 122:f9eeca106725 1337 #define EXTI_EMR_EM1 EXTI_EMR_MR1
Kojto 122:f9eeca106725 1338 #define EXTI_EMR_EM2 EXTI_EMR_MR2
Kojto 122:f9eeca106725 1339 #define EXTI_EMR_EM3 EXTI_EMR_MR3
Kojto 122:f9eeca106725 1340 #define EXTI_EMR_EM4 EXTI_EMR_MR4
Kojto 122:f9eeca106725 1341 #define EXTI_EMR_EM5 EXTI_EMR_MR5
Kojto 122:f9eeca106725 1342 #define EXTI_EMR_EM6 EXTI_EMR_MR6
Kojto 122:f9eeca106725 1343 #define EXTI_EMR_EM7 EXTI_EMR_MR7
Kojto 122:f9eeca106725 1344 #define EXTI_EMR_EM8 EXTI_EMR_MR8
Kojto 122:f9eeca106725 1345 #define EXTI_EMR_EM9 EXTI_EMR_MR9
Kojto 122:f9eeca106725 1346 #define EXTI_EMR_EM10 EXTI_EMR_MR10
Kojto 122:f9eeca106725 1347 #define EXTI_EMR_EM11 EXTI_EMR_MR11
Kojto 122:f9eeca106725 1348 #define EXTI_EMR_EM12 EXTI_EMR_MR12
Kojto 122:f9eeca106725 1349 #define EXTI_EMR_EM13 EXTI_EMR_MR13
Kojto 122:f9eeca106725 1350 #define EXTI_EMR_EM14 EXTI_EMR_MR14
Kojto 122:f9eeca106725 1351 #define EXTI_EMR_EM15 EXTI_EMR_MR15
Kojto 122:f9eeca106725 1352 #define EXTI_EMR_EM17 EXTI_EMR_MR17
Kojto 122:f9eeca106725 1353 #define EXTI_EMR_EM18 EXTI_EMR_MR18
Kojto 122:f9eeca106725 1354 #define EXTI_EMR_EM19 EXTI_EMR_MR19
Kojto 122:f9eeca106725 1355 #define EXTI_EMR_EM23 EXTI_EMR_MR23
Kojto 90:cb3d968589d8 1356
Kojto 90:cb3d968589d8 1357 /******************* Bit definition for EXTI_RTSR register ******************/
Kojto 122:f9eeca106725 1358 #define EXTI_RTSR_TR0_Pos (0U)
Kojto 122:f9eeca106725 1359 #define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1360 #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
Kojto 122:f9eeca106725 1361 #define EXTI_RTSR_TR1_Pos (1U)
Kojto 122:f9eeca106725 1362 #define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1363 #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
Kojto 122:f9eeca106725 1364 #define EXTI_RTSR_TR2_Pos (2U)
Kojto 122:f9eeca106725 1365 #define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1366 #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
Kojto 122:f9eeca106725 1367 #define EXTI_RTSR_TR3_Pos (3U)
Kojto 122:f9eeca106725 1368 #define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1369 #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
Kojto 122:f9eeca106725 1370 #define EXTI_RTSR_TR4_Pos (4U)
Kojto 122:f9eeca106725 1371 #define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1372 #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
Kojto 122:f9eeca106725 1373 #define EXTI_RTSR_TR5_Pos (5U)
Kojto 122:f9eeca106725 1374 #define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 1375 #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
Kojto 122:f9eeca106725 1376 #define EXTI_RTSR_TR6_Pos (6U)
Kojto 122:f9eeca106725 1377 #define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 1378 #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
Kojto 122:f9eeca106725 1379 #define EXTI_RTSR_TR7_Pos (7U)
Kojto 122:f9eeca106725 1380 #define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 1381 #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
Kojto 122:f9eeca106725 1382 #define EXTI_RTSR_TR8_Pos (8U)
Kojto 122:f9eeca106725 1383 #define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 1384 #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
Kojto 122:f9eeca106725 1385 #define EXTI_RTSR_TR9_Pos (9U)
Kojto 122:f9eeca106725 1386 #define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 1387 #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
Kojto 122:f9eeca106725 1388 #define EXTI_RTSR_TR10_Pos (10U)
Kojto 122:f9eeca106725 1389 #define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 1390 #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
Kojto 122:f9eeca106725 1391 #define EXTI_RTSR_TR11_Pos (11U)
Kojto 122:f9eeca106725 1392 #define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 1393 #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
Kojto 122:f9eeca106725 1394 #define EXTI_RTSR_TR12_Pos (12U)
Kojto 122:f9eeca106725 1395 #define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 1396 #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
Kojto 122:f9eeca106725 1397 #define EXTI_RTSR_TR13_Pos (13U)
Kojto 122:f9eeca106725 1398 #define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 1399 #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
Kojto 122:f9eeca106725 1400 #define EXTI_RTSR_TR14_Pos (14U)
Kojto 122:f9eeca106725 1401 #define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 1402 #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
Kojto 122:f9eeca106725 1403 #define EXTI_RTSR_TR15_Pos (15U)
Kojto 122:f9eeca106725 1404 #define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 1405 #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
Kojto 122:f9eeca106725 1406 #define EXTI_RTSR_TR16_Pos (16U)
Kojto 122:f9eeca106725 1407 #define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 1408 #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
Kojto 122:f9eeca106725 1409 #define EXTI_RTSR_TR17_Pos (17U)
Kojto 122:f9eeca106725 1410 #define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 1411 #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
Kojto 122:f9eeca106725 1412 #define EXTI_RTSR_TR19_Pos (19U)
Kojto 122:f9eeca106725 1413 #define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 1414 #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
Kojto 122:f9eeca106725 1415
Kojto 122:f9eeca106725 1416 /* References Defines */
Kojto 122:f9eeca106725 1417 #define EXTI_RTSR_RT0 EXTI_RTSR_TR0
Kojto 122:f9eeca106725 1418 #define EXTI_RTSR_RT1 EXTI_RTSR_TR1
Kojto 122:f9eeca106725 1419 #define EXTI_RTSR_RT2 EXTI_RTSR_TR2
Kojto 122:f9eeca106725 1420 #define EXTI_RTSR_RT3 EXTI_RTSR_TR3
Kojto 122:f9eeca106725 1421 #define EXTI_RTSR_RT4 EXTI_RTSR_TR4
Kojto 122:f9eeca106725 1422 #define EXTI_RTSR_RT5 EXTI_RTSR_TR5
Kojto 122:f9eeca106725 1423 #define EXTI_RTSR_RT6 EXTI_RTSR_TR6
Kojto 122:f9eeca106725 1424 #define EXTI_RTSR_RT7 EXTI_RTSR_TR7
Kojto 122:f9eeca106725 1425 #define EXTI_RTSR_RT8 EXTI_RTSR_TR8
Kojto 122:f9eeca106725 1426 #define EXTI_RTSR_RT9 EXTI_RTSR_TR9
Kojto 122:f9eeca106725 1427 #define EXTI_RTSR_RT10 EXTI_RTSR_TR10
Kojto 122:f9eeca106725 1428 #define EXTI_RTSR_RT11 EXTI_RTSR_TR11
Kojto 122:f9eeca106725 1429 #define EXTI_RTSR_RT12 EXTI_RTSR_TR12
Kojto 122:f9eeca106725 1430 #define EXTI_RTSR_RT13 EXTI_RTSR_TR13
Kojto 122:f9eeca106725 1431 #define EXTI_RTSR_RT14 EXTI_RTSR_TR14
Kojto 122:f9eeca106725 1432 #define EXTI_RTSR_RT15 EXTI_RTSR_TR15
Kojto 122:f9eeca106725 1433 #define EXTI_RTSR_RT16 EXTI_RTSR_TR16
Kojto 122:f9eeca106725 1434 #define EXTI_RTSR_RT17 EXTI_RTSR_TR17
Kojto 122:f9eeca106725 1435 #define EXTI_RTSR_RT19 EXTI_RTSR_TR19
Kojto 90:cb3d968589d8 1436
Kojto 90:cb3d968589d8 1437 /******************* Bit definition for EXTI_FTSR register *******************/
Kojto 122:f9eeca106725 1438 #define EXTI_FTSR_TR0_Pos (0U)
Kojto 122:f9eeca106725 1439 #define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1440 #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
Kojto 122:f9eeca106725 1441 #define EXTI_FTSR_TR1_Pos (1U)
Kojto 122:f9eeca106725 1442 #define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1443 #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
Kojto 122:f9eeca106725 1444 #define EXTI_FTSR_TR2_Pos (2U)
Kojto 122:f9eeca106725 1445 #define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1446 #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
Kojto 122:f9eeca106725 1447 #define EXTI_FTSR_TR3_Pos (3U)
Kojto 122:f9eeca106725 1448 #define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1449 #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
Kojto 122:f9eeca106725 1450 #define EXTI_FTSR_TR4_Pos (4U)
Kojto 122:f9eeca106725 1451 #define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1452 #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
Kojto 122:f9eeca106725 1453 #define EXTI_FTSR_TR5_Pos (5U)
Kojto 122:f9eeca106725 1454 #define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 1455 #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
Kojto 122:f9eeca106725 1456 #define EXTI_FTSR_TR6_Pos (6U)
Kojto 122:f9eeca106725 1457 #define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 1458 #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
Kojto 122:f9eeca106725 1459 #define EXTI_FTSR_TR7_Pos (7U)
Kojto 122:f9eeca106725 1460 #define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 1461 #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
Kojto 122:f9eeca106725 1462 #define EXTI_FTSR_TR8_Pos (8U)
Kojto 122:f9eeca106725 1463 #define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 1464 #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
Kojto 122:f9eeca106725 1465 #define EXTI_FTSR_TR9_Pos (9U)
Kojto 122:f9eeca106725 1466 #define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 1467 #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
Kojto 122:f9eeca106725 1468 #define EXTI_FTSR_TR10_Pos (10U)
Kojto 122:f9eeca106725 1469 #define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 1470 #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
Kojto 122:f9eeca106725 1471 #define EXTI_FTSR_TR11_Pos (11U)
Kojto 122:f9eeca106725 1472 #define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 1473 #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
Kojto 122:f9eeca106725 1474 #define EXTI_FTSR_TR12_Pos (12U)
Kojto 122:f9eeca106725 1475 #define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 1476 #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
Kojto 122:f9eeca106725 1477 #define EXTI_FTSR_TR13_Pos (13U)
Kojto 122:f9eeca106725 1478 #define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 1479 #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
Kojto 122:f9eeca106725 1480 #define EXTI_FTSR_TR14_Pos (14U)
Kojto 122:f9eeca106725 1481 #define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 1482 #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
Kojto 122:f9eeca106725 1483 #define EXTI_FTSR_TR15_Pos (15U)
Kojto 122:f9eeca106725 1484 #define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 1485 #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
Kojto 122:f9eeca106725 1486 #define EXTI_FTSR_TR16_Pos (16U)
Kojto 122:f9eeca106725 1487 #define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 1488 #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
Kojto 122:f9eeca106725 1489 #define EXTI_FTSR_TR17_Pos (17U)
Kojto 122:f9eeca106725 1490 #define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 1491 #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
Kojto 122:f9eeca106725 1492 #define EXTI_FTSR_TR19_Pos (19U)
Kojto 122:f9eeca106725 1493 #define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 1494 #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
Kojto 122:f9eeca106725 1495
Kojto 122:f9eeca106725 1496 /* References Defines */
Kojto 122:f9eeca106725 1497 #define EXTI_FTSR_FT0 EXTI_FTSR_TR0
Kojto 122:f9eeca106725 1498 #define EXTI_FTSR_FT1 EXTI_FTSR_TR1
Kojto 122:f9eeca106725 1499 #define EXTI_FTSR_FT2 EXTI_FTSR_TR2
Kojto 122:f9eeca106725 1500 #define EXTI_FTSR_FT3 EXTI_FTSR_TR3
Kojto 122:f9eeca106725 1501 #define EXTI_FTSR_FT4 EXTI_FTSR_TR4
Kojto 122:f9eeca106725 1502 #define EXTI_FTSR_FT5 EXTI_FTSR_TR5
Kojto 122:f9eeca106725 1503 #define EXTI_FTSR_FT6 EXTI_FTSR_TR6
Kojto 122:f9eeca106725 1504 #define EXTI_FTSR_FT7 EXTI_FTSR_TR7
Kojto 122:f9eeca106725 1505 #define EXTI_FTSR_FT8 EXTI_FTSR_TR8
Kojto 122:f9eeca106725 1506 #define EXTI_FTSR_FT9 EXTI_FTSR_TR9
Kojto 122:f9eeca106725 1507 #define EXTI_FTSR_FT10 EXTI_FTSR_TR10
Kojto 122:f9eeca106725 1508 #define EXTI_FTSR_FT11 EXTI_FTSR_TR11
Kojto 122:f9eeca106725 1509 #define EXTI_FTSR_FT12 EXTI_FTSR_TR12
Kojto 122:f9eeca106725 1510 #define EXTI_FTSR_FT13 EXTI_FTSR_TR13
Kojto 122:f9eeca106725 1511 #define EXTI_FTSR_FT14 EXTI_FTSR_TR14
Kojto 122:f9eeca106725 1512 #define EXTI_FTSR_FT15 EXTI_FTSR_TR15
Kojto 122:f9eeca106725 1513 #define EXTI_FTSR_FT16 EXTI_FTSR_TR16
Kojto 122:f9eeca106725 1514 #define EXTI_FTSR_FT17 EXTI_FTSR_TR17
Kojto 122:f9eeca106725 1515 #define EXTI_FTSR_FT19 EXTI_FTSR_TR19
Kojto 90:cb3d968589d8 1516
Kojto 90:cb3d968589d8 1517 /******************* Bit definition for EXTI_SWIER register *******************/
Kojto 122:f9eeca106725 1518 #define EXTI_SWIER_SWIER0_Pos (0U)
Kojto 122:f9eeca106725 1519 #define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1520 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
Kojto 122:f9eeca106725 1521 #define EXTI_SWIER_SWIER1_Pos (1U)
Kojto 122:f9eeca106725 1522 #define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1523 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
Kojto 122:f9eeca106725 1524 #define EXTI_SWIER_SWIER2_Pos (2U)
Kojto 122:f9eeca106725 1525 #define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1526 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
Kojto 122:f9eeca106725 1527 #define EXTI_SWIER_SWIER3_Pos (3U)
Kojto 122:f9eeca106725 1528 #define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1529 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
Kojto 122:f9eeca106725 1530 #define EXTI_SWIER_SWIER4_Pos (4U)
Kojto 122:f9eeca106725 1531 #define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1532 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
Kojto 122:f9eeca106725 1533 #define EXTI_SWIER_SWIER5_Pos (5U)
Kojto 122:f9eeca106725 1534 #define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 1535 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
Kojto 122:f9eeca106725 1536 #define EXTI_SWIER_SWIER6_Pos (6U)
Kojto 122:f9eeca106725 1537 #define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 1538 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
Kojto 122:f9eeca106725 1539 #define EXTI_SWIER_SWIER7_Pos (7U)
Kojto 122:f9eeca106725 1540 #define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 1541 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
Kojto 122:f9eeca106725 1542 #define EXTI_SWIER_SWIER8_Pos (8U)
Kojto 122:f9eeca106725 1543 #define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 1544 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
Kojto 122:f9eeca106725 1545 #define EXTI_SWIER_SWIER9_Pos (9U)
Kojto 122:f9eeca106725 1546 #define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 1547 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
Kojto 122:f9eeca106725 1548 #define EXTI_SWIER_SWIER10_Pos (10U)
Kojto 122:f9eeca106725 1549 #define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 1550 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
Kojto 122:f9eeca106725 1551 #define EXTI_SWIER_SWIER11_Pos (11U)
Kojto 122:f9eeca106725 1552 #define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 1553 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
Kojto 122:f9eeca106725 1554 #define EXTI_SWIER_SWIER12_Pos (12U)
Kojto 122:f9eeca106725 1555 #define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 1556 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
Kojto 122:f9eeca106725 1557 #define EXTI_SWIER_SWIER13_Pos (13U)
Kojto 122:f9eeca106725 1558 #define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 1559 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
Kojto 122:f9eeca106725 1560 #define EXTI_SWIER_SWIER14_Pos (14U)
Kojto 122:f9eeca106725 1561 #define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 1562 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
Kojto 122:f9eeca106725 1563 #define EXTI_SWIER_SWIER15_Pos (15U)
Kojto 122:f9eeca106725 1564 #define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 1565 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
Kojto 122:f9eeca106725 1566 #define EXTI_SWIER_SWIER16_Pos (16U)
Kojto 122:f9eeca106725 1567 #define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 1568 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
Kojto 122:f9eeca106725 1569 #define EXTI_SWIER_SWIER17_Pos (17U)
Kojto 122:f9eeca106725 1570 #define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 1571 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
Kojto 122:f9eeca106725 1572 #define EXTI_SWIER_SWIER19_Pos (19U)
Kojto 122:f9eeca106725 1573 #define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 1574 #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
Kojto 122:f9eeca106725 1575
Kojto 122:f9eeca106725 1576 /* References Defines */
Kojto 122:f9eeca106725 1577 #define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
Kojto 122:f9eeca106725 1578 #define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
Kojto 122:f9eeca106725 1579 #define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
Kojto 122:f9eeca106725 1580 #define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
Kojto 122:f9eeca106725 1581 #define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
Kojto 122:f9eeca106725 1582 #define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
Kojto 122:f9eeca106725 1583 #define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
Kojto 122:f9eeca106725 1584 #define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
Kojto 122:f9eeca106725 1585 #define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
Kojto 122:f9eeca106725 1586 #define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
Kojto 122:f9eeca106725 1587 #define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
Kojto 122:f9eeca106725 1588 #define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
Kojto 122:f9eeca106725 1589 #define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
Kojto 122:f9eeca106725 1590 #define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
Kojto 122:f9eeca106725 1591 #define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
Kojto 122:f9eeca106725 1592 #define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
Kojto 122:f9eeca106725 1593 #define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
Kojto 122:f9eeca106725 1594 #define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
Kojto 122:f9eeca106725 1595 #define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
Kojto 90:cb3d968589d8 1596
Kojto 90:cb3d968589d8 1597 /****************** Bit definition for EXTI_PR register *********************/
Kojto 122:f9eeca106725 1598 #define EXTI_PR_PR0_Pos (0U)
Kojto 122:f9eeca106725 1599 #define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1600 #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit 0 */
Kojto 122:f9eeca106725 1601 #define EXTI_PR_PR1_Pos (1U)
Kojto 122:f9eeca106725 1602 #define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1603 #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit 1 */
Kojto 122:f9eeca106725 1604 #define EXTI_PR_PR2_Pos (2U)
Kojto 122:f9eeca106725 1605 #define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1606 #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit 2 */
Kojto 122:f9eeca106725 1607 #define EXTI_PR_PR3_Pos (3U)
Kojto 122:f9eeca106725 1608 #define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1609 #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit 3 */
Kojto 122:f9eeca106725 1610 #define EXTI_PR_PR4_Pos (4U)
Kojto 122:f9eeca106725 1611 #define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1612 #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit 4 */
Kojto 122:f9eeca106725 1613 #define EXTI_PR_PR5_Pos (5U)
Kojto 122:f9eeca106725 1614 #define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 1615 #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit 5 */
Kojto 122:f9eeca106725 1616 #define EXTI_PR_PR6_Pos (6U)
Kojto 122:f9eeca106725 1617 #define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 1618 #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit 6 */
Kojto 122:f9eeca106725 1619 #define EXTI_PR_PR7_Pos (7U)
Kojto 122:f9eeca106725 1620 #define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 1621 #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit 7 */
Kojto 122:f9eeca106725 1622 #define EXTI_PR_PR8_Pos (8U)
Kojto 122:f9eeca106725 1623 #define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 1624 #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit 8 */
Kojto 122:f9eeca106725 1625 #define EXTI_PR_PR9_Pos (9U)
Kojto 122:f9eeca106725 1626 #define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 1627 #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit 9 */
Kojto 122:f9eeca106725 1628 #define EXTI_PR_PR10_Pos (10U)
Kojto 122:f9eeca106725 1629 #define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 1630 #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit 10 */
Kojto 122:f9eeca106725 1631 #define EXTI_PR_PR11_Pos (11U)
Kojto 122:f9eeca106725 1632 #define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 1633 #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit 11 */
Kojto 122:f9eeca106725 1634 #define EXTI_PR_PR12_Pos (12U)
Kojto 122:f9eeca106725 1635 #define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 1636 #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit 12 */
Kojto 122:f9eeca106725 1637 #define EXTI_PR_PR13_Pos (13U)
Kojto 122:f9eeca106725 1638 #define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 1639 #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit 13 */
Kojto 122:f9eeca106725 1640 #define EXTI_PR_PR14_Pos (14U)
Kojto 122:f9eeca106725 1641 #define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 1642 #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit 14 */
Kojto 122:f9eeca106725 1643 #define EXTI_PR_PR15_Pos (15U)
Kojto 122:f9eeca106725 1644 #define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 1645 #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit 15 */
Kojto 122:f9eeca106725 1646 #define EXTI_PR_PR16_Pos (16U)
Kojto 122:f9eeca106725 1647 #define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 1648 #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit 16 */
Kojto 122:f9eeca106725 1649 #define EXTI_PR_PR17_Pos (17U)
Kojto 122:f9eeca106725 1650 #define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 1651 #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit 17 */
Kojto 122:f9eeca106725 1652 #define EXTI_PR_PR19_Pos (19U)
Kojto 122:f9eeca106725 1653 #define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 1654 #define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit 19 */
Kojto 122:f9eeca106725 1655
Kojto 122:f9eeca106725 1656 /* References Defines */
Kojto 122:f9eeca106725 1657 #define EXTI_PR_PIF0 EXTI_PR_PR0
Kojto 122:f9eeca106725 1658 #define EXTI_PR_PIF1 EXTI_PR_PR1
Kojto 122:f9eeca106725 1659 #define EXTI_PR_PIF2 EXTI_PR_PR2
Kojto 122:f9eeca106725 1660 #define EXTI_PR_PIF3 EXTI_PR_PR3
Kojto 122:f9eeca106725 1661 #define EXTI_PR_PIF4 EXTI_PR_PR4
Kojto 122:f9eeca106725 1662 #define EXTI_PR_PIF5 EXTI_PR_PR5
Kojto 122:f9eeca106725 1663 #define EXTI_PR_PIF6 EXTI_PR_PR6
Kojto 122:f9eeca106725 1664 #define EXTI_PR_PIF7 EXTI_PR_PR7
Kojto 122:f9eeca106725 1665 #define EXTI_PR_PIF8 EXTI_PR_PR8
Kojto 122:f9eeca106725 1666 #define EXTI_PR_PIF9 EXTI_PR_PR9
Kojto 122:f9eeca106725 1667 #define EXTI_PR_PIF10 EXTI_PR_PR10
Kojto 122:f9eeca106725 1668 #define EXTI_PR_PIF11 EXTI_PR_PR11
Kojto 122:f9eeca106725 1669 #define EXTI_PR_PIF12 EXTI_PR_PR12
Kojto 122:f9eeca106725 1670 #define EXTI_PR_PIF13 EXTI_PR_PR13
Kojto 122:f9eeca106725 1671 #define EXTI_PR_PIF14 EXTI_PR_PR14
Kojto 122:f9eeca106725 1672 #define EXTI_PR_PIF15 EXTI_PR_PR15
Kojto 122:f9eeca106725 1673 #define EXTI_PR_PIF16 EXTI_PR_PR16
Kojto 122:f9eeca106725 1674 #define EXTI_PR_PIF17 EXTI_PR_PR17
Kojto 122:f9eeca106725 1675 #define EXTI_PR_PIF19 EXTI_PR_PR19
Kojto 90:cb3d968589d8 1676
Kojto 90:cb3d968589d8 1677 /******************************************************************************/
Kojto 90:cb3d968589d8 1678 /* */
Kojto 90:cb3d968589d8 1679 /* FLASH and Option Bytes Registers */
Kojto 90:cb3d968589d8 1680 /* */
Kojto 90:cb3d968589d8 1681 /******************************************************************************/
Kojto 90:cb3d968589d8 1682
Kojto 90:cb3d968589d8 1683 /******************* Bit definition for FLASH_ACR register ******************/
Kojto 122:f9eeca106725 1684 #define FLASH_ACR_LATENCY_Pos (0U)
Kojto 122:f9eeca106725 1685 #define FLASH_ACR_LATENCY_Msk (0x1U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1686 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY bit (Latency) */
Kojto 122:f9eeca106725 1687
Kojto 122:f9eeca106725 1688 #define FLASH_ACR_PRFTBE_Pos (4U)
Kojto 122:f9eeca106725 1689 #define FLASH_ACR_PRFTBE_Msk (0x1U << FLASH_ACR_PRFTBE_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1690 #define FLASH_ACR_PRFTBE FLASH_ACR_PRFTBE_Msk /*!< Prefetch Buffer Enable */
Kojto 122:f9eeca106725 1691 #define FLASH_ACR_PRFTBS_Pos (5U)
Kojto 122:f9eeca106725 1692 #define FLASH_ACR_PRFTBS_Msk (0x1U << FLASH_ACR_PRFTBS_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 1693 #define FLASH_ACR_PRFTBS FLASH_ACR_PRFTBS_Msk /*!< Prefetch Buffer Status */
Kojto 90:cb3d968589d8 1694
Kojto 90:cb3d968589d8 1695 /****************** Bit definition for FLASH_KEYR register ******************/
Kojto 122:f9eeca106725 1696 #define FLASH_KEYR_FKEYR_Pos (0U)
Kojto 122:f9eeca106725 1697 #define FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFU << FLASH_KEYR_FKEYR_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 1698 #define FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk /*!< FPEC Key */
Kojto 90:cb3d968589d8 1699
Kojto 90:cb3d968589d8 1700 /***************** Bit definition for FLASH_OPTKEYR register ****************/
Kojto 122:f9eeca106725 1701 #define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
Kojto 122:f9eeca106725 1702 #define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 1703 #define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option Byte Key */
Kojto 90:cb3d968589d8 1704
Kojto 90:cb3d968589d8 1705 /****************** FLASH Keys **********************************************/
Kojto 122:f9eeca106725 1706 #define FLASH_KEY1_Pos (0U)
Kojto 122:f9eeca106725 1707 #define FLASH_KEY1_Msk (0x45670123U << FLASH_KEY1_Pos) /*!< 0x45670123 */
Kojto 122:f9eeca106725 1708 #define FLASH_KEY1 FLASH_KEY1_Msk /*!< Flash program erase key1 */
Kojto 122:f9eeca106725 1709 #define FLASH_KEY2_Pos (0U)
Kojto 122:f9eeca106725 1710 #define FLASH_KEY2_Msk (0xCDEF89ABU << FLASH_KEY2_Pos) /*!< 0xCDEF89AB */
Kojto 122:f9eeca106725 1711 #define FLASH_KEY2 FLASH_KEY2_Msk /*!< Flash program erase key2: used with FLASH_PEKEY1
Kojto 90:cb3d968589d8 1712 to unlock the write access to the FPEC. */
Kojto 90:cb3d968589d8 1713
Kojto 122:f9eeca106725 1714 #define FLASH_OPTKEY1_Pos (0U)
Kojto 122:f9eeca106725 1715 #define FLASH_OPTKEY1_Msk (0x45670123U << FLASH_OPTKEY1_Pos) /*!< 0x45670123 */
Kojto 122:f9eeca106725 1716 #define FLASH_OPTKEY1 FLASH_OPTKEY1_Msk /*!< Flash option key1 */
Kojto 122:f9eeca106725 1717 #define FLASH_OPTKEY2_Pos (0U)
Kojto 122:f9eeca106725 1718 #define FLASH_OPTKEY2_Msk (0xCDEF89ABU << FLASH_OPTKEY2_Pos) /*!< 0xCDEF89AB */
Kojto 122:f9eeca106725 1719 #define FLASH_OPTKEY2 FLASH_OPTKEY2_Msk /*!< Flash option key2: used with FLASH_OPTKEY1 to
Kojto 90:cb3d968589d8 1720 unlock the write access to the option byte block */
Kojto 90:cb3d968589d8 1721
Kojto 90:cb3d968589d8 1722 /****************** Bit definition for FLASH_SR register *******************/
Kojto 122:f9eeca106725 1723 #define FLASH_SR_BSY_Pos (0U)
Kojto 122:f9eeca106725 1724 #define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1725 #define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */
Kojto 122:f9eeca106725 1726 #define FLASH_SR_PGERR_Pos (2U)
Kojto 122:f9eeca106725 1727 #define FLASH_SR_PGERR_Msk (0x1U << FLASH_SR_PGERR_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1728 #define FLASH_SR_PGERR FLASH_SR_PGERR_Msk /*!< Programming Error */
Kojto 122:f9eeca106725 1729 #define FLASH_SR_WRPRTERR_Pos (4U)
Kojto 122:f9eeca106725 1730 #define FLASH_SR_WRPRTERR_Msk (0x1U << FLASH_SR_WRPRTERR_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1731 #define FLASH_SR_WRPRTERR FLASH_SR_WRPRTERR_Msk /*!< Write Protection Error */
Kojto 122:f9eeca106725 1732 #define FLASH_SR_EOP_Pos (5U)
Kojto 122:f9eeca106725 1733 #define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 1734 #define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End of operation */
Kojto 90:cb3d968589d8 1735 #define FLASH_SR_WRPERR FLASH_SR_WRPRTERR /*!< Legacy of Write Protection Error */
Kojto 90:cb3d968589d8 1736
Kojto 90:cb3d968589d8 1737 /******************* Bit definition for FLASH_CR register *******************/
Kojto 122:f9eeca106725 1738 #define FLASH_CR_PG_Pos (0U)
Kojto 122:f9eeca106725 1739 #define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1740 #define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Programming */
Kojto 122:f9eeca106725 1741 #define FLASH_CR_PER_Pos (1U)
Kojto 122:f9eeca106725 1742 #define FLASH_CR_PER_Msk (0x1U << FLASH_CR_PER_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1743 #define FLASH_CR_PER FLASH_CR_PER_Msk /*!< Page Erase */
Kojto 122:f9eeca106725 1744 #define FLASH_CR_MER_Pos (2U)
Kojto 122:f9eeca106725 1745 #define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1746 #define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass Erase */
Kojto 122:f9eeca106725 1747 #define FLASH_CR_OPTPG_Pos (4U)
Kojto 122:f9eeca106725 1748 #define FLASH_CR_OPTPG_Msk (0x1U << FLASH_CR_OPTPG_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1749 #define FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk /*!< Option Byte Programming */
Kojto 122:f9eeca106725 1750 #define FLASH_CR_OPTER_Pos (5U)
Kojto 122:f9eeca106725 1751 #define FLASH_CR_OPTER_Msk (0x1U << FLASH_CR_OPTER_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 1752 #define FLASH_CR_OPTER FLASH_CR_OPTER_Msk /*!< Option Byte Erase */
Kojto 122:f9eeca106725 1753 #define FLASH_CR_STRT_Pos (6U)
Kojto 122:f9eeca106725 1754 #define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 1755 #define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< Start */
Kojto 122:f9eeca106725 1756 #define FLASH_CR_LOCK_Pos (7U)
Kojto 122:f9eeca106725 1757 #define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 1758 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Lock */
Kojto 122:f9eeca106725 1759 #define FLASH_CR_OPTWRE_Pos (9U)
Kojto 122:f9eeca106725 1760 #define FLASH_CR_OPTWRE_Msk (0x1U << FLASH_CR_OPTWRE_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 1761 #define FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk /*!< Option Bytes Write Enable */
Kojto 122:f9eeca106725 1762 #define FLASH_CR_ERRIE_Pos (10U)
Kojto 122:f9eeca106725 1763 #define FLASH_CR_ERRIE_Msk (0x1U << FLASH_CR_ERRIE_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 1764 #define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk /*!< Error Interrupt Enable */
Kojto 122:f9eeca106725 1765 #define FLASH_CR_EOPIE_Pos (12U)
Kojto 122:f9eeca106725 1766 #define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 1767 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End of operation interrupt enable */
Kojto 122:f9eeca106725 1768 #define FLASH_CR_OBL_LAUNCH_Pos (13U)
Kojto 122:f9eeca106725 1769 #define FLASH_CR_OBL_LAUNCH_Msk (0x1U << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 1770 #define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk /*!< Option Bytes Loader Launch */
Kojto 90:cb3d968589d8 1771
Kojto 90:cb3d968589d8 1772 /******************* Bit definition for FLASH_AR register *******************/
Kojto 122:f9eeca106725 1773 #define FLASH_AR_FAR_Pos (0U)
Kojto 122:f9eeca106725 1774 #define FLASH_AR_FAR_Msk (0xFFFFFFFFU << FLASH_AR_FAR_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 1775 #define FLASH_AR_FAR FLASH_AR_FAR_Msk /*!< Flash Address */
Kojto 90:cb3d968589d8 1776
Kojto 90:cb3d968589d8 1777 /****************** Bit definition for FLASH_OBR register *******************/
Kojto 122:f9eeca106725 1778 #define FLASH_OBR_OPTERR_Pos (0U)
Kojto 122:f9eeca106725 1779 #define FLASH_OBR_OPTERR_Msk (0x1U << FLASH_OBR_OPTERR_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1780 #define FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk /*!< Option Byte Error */
Kojto 122:f9eeca106725 1781 #define FLASH_OBR_RDPRT1_Pos (1U)
Kojto 122:f9eeca106725 1782 #define FLASH_OBR_RDPRT1_Msk (0x1U << FLASH_OBR_RDPRT1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1783 #define FLASH_OBR_RDPRT1 FLASH_OBR_RDPRT1_Msk /*!< Read protection Level 1 */
Kojto 122:f9eeca106725 1784 #define FLASH_OBR_RDPRT2_Pos (2U)
Kojto 122:f9eeca106725 1785 #define FLASH_OBR_RDPRT2_Msk (0x1U << FLASH_OBR_RDPRT2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1786 #define FLASH_OBR_RDPRT2 FLASH_OBR_RDPRT2_Msk /*!< Read protection Level 2 */
Kojto 122:f9eeca106725 1787
Kojto 122:f9eeca106725 1788 #define FLASH_OBR_USER_Pos (8U)
Kojto 122:f9eeca106725 1789 #define FLASH_OBR_USER_Msk (0x77U << FLASH_OBR_USER_Pos) /*!< 0x00007700 */
Kojto 122:f9eeca106725 1790 #define FLASH_OBR_USER FLASH_OBR_USER_Msk /*!< User Option Bytes */
Kojto 122:f9eeca106725 1791 #define FLASH_OBR_IWDG_SW_Pos (8U)
Kojto 122:f9eeca106725 1792 #define FLASH_OBR_IWDG_SW_Msk (0x1U << FLASH_OBR_IWDG_SW_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 1793 #define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /*!< IWDG SW */
Kojto 122:f9eeca106725 1794 #define FLASH_OBR_nRST_STOP_Pos (9U)
Kojto 122:f9eeca106725 1795 #define FLASH_OBR_nRST_STOP_Msk (0x1U << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 1796 #define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /*!< nRST_STOP */
Kojto 122:f9eeca106725 1797 #define FLASH_OBR_nRST_STDBY_Pos (10U)
Kojto 122:f9eeca106725 1798 #define FLASH_OBR_nRST_STDBY_Msk (0x1U << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 1799 #define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /*!< nRST_STDBY */
Kojto 122:f9eeca106725 1800 #define FLASH_OBR_nBOOT1_Pos (12U)
Kojto 122:f9eeca106725 1801 #define FLASH_OBR_nBOOT1_Msk (0x1U << FLASH_OBR_nBOOT1_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 1802 #define FLASH_OBR_nBOOT1 FLASH_OBR_nBOOT1_Msk /*!< nBOOT1 */
Kojto 122:f9eeca106725 1803 #define FLASH_OBR_VDDA_MONITOR_Pos (13U)
Kojto 122:f9eeca106725 1804 #define FLASH_OBR_VDDA_MONITOR_Msk (0x1U << FLASH_OBR_VDDA_MONITOR_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 1805 #define FLASH_OBR_VDDA_MONITOR FLASH_OBR_VDDA_MONITOR_Msk /*!< VDDA power supply supervisor */
Kojto 122:f9eeca106725 1806 #define FLASH_OBR_RAM_PARITY_CHECK_Pos (14U)
Kojto 122:f9eeca106725 1807 #define FLASH_OBR_RAM_PARITY_CHECK_Msk (0x1U << FLASH_OBR_RAM_PARITY_CHECK_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 1808 #define FLASH_OBR_RAM_PARITY_CHECK FLASH_OBR_RAM_PARITY_CHECK_Msk /*!< RAM parity check */
Kojto 122:f9eeca106725 1809 #define FLASH_OBR_DATA0_Pos (16U)
Kojto 122:f9eeca106725 1810 #define FLASH_OBR_DATA0_Msk (0xFFU << FLASH_OBR_DATA0_Pos) /*!< 0x00FF0000 */
Kojto 122:f9eeca106725 1811 #define FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk /*!< Data0 */
Kojto 122:f9eeca106725 1812 #define FLASH_OBR_DATA1_Pos (24U)
Kojto 122:f9eeca106725 1813 #define FLASH_OBR_DATA1_Msk (0xFFU << FLASH_OBR_DATA1_Pos) /*!< 0xFF000000 */
Kojto 122:f9eeca106725 1814 #define FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk /*!< Data1 */
Kojto 90:cb3d968589d8 1815
Kojto 90:cb3d968589d8 1816 /* Old BOOT1 bit definition, maintained for legacy purpose */
Kojto 90:cb3d968589d8 1817 #define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1
Kojto 90:cb3d968589d8 1818
Kojto 90:cb3d968589d8 1819 /* Old OBR_VDDA bit definition, maintained for legacy purpose */
Kojto 90:cb3d968589d8 1820 #define FLASH_OBR_VDDA_ANALOG FLASH_OBR_VDDA_MONITOR
Kojto 90:cb3d968589d8 1821
Kojto 90:cb3d968589d8 1822 /****************** Bit definition for FLASH_WRPR register ******************/
Kojto 122:f9eeca106725 1823 #define FLASH_WRPR_WRP_Pos (0U)
Kojto 122:f9eeca106725 1824 #define FLASH_WRPR_WRP_Msk (0xFFFFU << FLASH_WRPR_WRP_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 1825 #define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protect */
Kojto 90:cb3d968589d8 1826
Kojto 90:cb3d968589d8 1827 /*----------------------------------------------------------------------------*/
Kojto 90:cb3d968589d8 1828
Kojto 90:cb3d968589d8 1829 /****************** Bit definition for OB_RDP register **********************/
Kojto 122:f9eeca106725 1830 #define OB_RDP_RDP_Pos (0U)
Kojto 122:f9eeca106725 1831 #define OB_RDP_RDP_Msk (0xFFU << OB_RDP_RDP_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 1832 #define OB_RDP_RDP OB_RDP_RDP_Msk /*!< Read protection option byte */
Kojto 122:f9eeca106725 1833 #define OB_RDP_nRDP_Pos (8U)
Kojto 122:f9eeca106725 1834 #define OB_RDP_nRDP_Msk (0xFFU << OB_RDP_nRDP_Pos) /*!< 0x0000FF00 */
Kojto 122:f9eeca106725 1835 #define OB_RDP_nRDP OB_RDP_nRDP_Msk /*!< Read protection complemented option byte */
Kojto 90:cb3d968589d8 1836
Kojto 90:cb3d968589d8 1837 /****************** Bit definition for OB_USER register *********************/
Kojto 122:f9eeca106725 1838 #define OB_USER_USER_Pos (16U)
Kojto 122:f9eeca106725 1839 #define OB_USER_USER_Msk (0xFFU << OB_USER_USER_Pos) /*!< 0x00FF0000 */
Kojto 122:f9eeca106725 1840 #define OB_USER_USER OB_USER_USER_Msk /*!< User option byte */
Kojto 122:f9eeca106725 1841 #define OB_USER_nUSER_Pos (24U)
Kojto 122:f9eeca106725 1842 #define OB_USER_nUSER_Msk (0xFFU << OB_USER_nUSER_Pos) /*!< 0xFF000000 */
Kojto 122:f9eeca106725 1843 #define OB_USER_nUSER OB_USER_nUSER_Msk /*!< User complemented option byte */
Kojto 90:cb3d968589d8 1844
Kojto 90:cb3d968589d8 1845 /****************** Bit definition for OB_WRP0 register *********************/
Kojto 122:f9eeca106725 1846 #define OB_WRP0_WRP0_Pos (0U)
Kojto 122:f9eeca106725 1847 #define OB_WRP0_WRP0_Msk (0xFFU << OB_WRP0_WRP0_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 1848 #define OB_WRP0_WRP0 OB_WRP0_WRP0_Msk /*!< Flash memory write protection option bytes */
Kojto 122:f9eeca106725 1849 #define OB_WRP0_nWRP0_Pos (8U)
Kojto 122:f9eeca106725 1850 #define OB_WRP0_nWRP0_Msk (0xFFU << OB_WRP0_nWRP0_Pos) /*!< 0x0000FF00 */
Kojto 122:f9eeca106725 1851 #define OB_WRP0_nWRP0 OB_WRP0_nWRP0_Msk /*!< Flash memory write protection complemented option bytes */
Kojto 90:cb3d968589d8 1852
Kojto 90:cb3d968589d8 1853 /****************** Bit definition for OB_WRP1 register *********************/
Kojto 122:f9eeca106725 1854 #define OB_WRP1_WRP1_Pos (16U)
Kojto 122:f9eeca106725 1855 #define OB_WRP1_WRP1_Msk (0xFFU << OB_WRP1_WRP1_Pos) /*!< 0x00FF0000 */
Kojto 122:f9eeca106725 1856 #define OB_WRP1_WRP1 OB_WRP1_WRP1_Msk /*!< Flash memory write protection option bytes */
Kojto 122:f9eeca106725 1857 #define OB_WRP1_nWRP1_Pos (24U)
Kojto 122:f9eeca106725 1858 #define OB_WRP1_nWRP1_Msk (0xFFU << OB_WRP1_nWRP1_Pos) /*!< 0xFF000000 */
Kojto 122:f9eeca106725 1859 #define OB_WRP1_nWRP1 OB_WRP1_nWRP1_Msk /*!< Flash memory write protection complemented option bytes */
Kojto 90:cb3d968589d8 1860
Kojto 90:cb3d968589d8 1861 /******************************************************************************/
Kojto 90:cb3d968589d8 1862 /* */
Kojto 90:cb3d968589d8 1863 /* General Purpose IOs (GPIO) */
Kojto 90:cb3d968589d8 1864 /* */
Kojto 90:cb3d968589d8 1865 /******************************************************************************/
Kojto 90:cb3d968589d8 1866 /******************* Bit definition for GPIO_MODER register *****************/
Kojto 122:f9eeca106725 1867 #define GPIO_MODER_MODER0_Pos (0U)
Kojto 122:f9eeca106725 1868 #define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */
Kojto 122:f9eeca106725 1869 #define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
Kojto 122:f9eeca106725 1870 #define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1871 #define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1872 #define GPIO_MODER_MODER1_Pos (2U)
Kojto 122:f9eeca106725 1873 #define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */
Kojto 122:f9eeca106725 1874 #define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
Kojto 122:f9eeca106725 1875 #define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1876 #define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1877 #define GPIO_MODER_MODER2_Pos (4U)
Kojto 122:f9eeca106725 1878 #define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */
Kojto 122:f9eeca106725 1879 #define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
Kojto 122:f9eeca106725 1880 #define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1881 #define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 1882 #define GPIO_MODER_MODER3_Pos (6U)
Kojto 122:f9eeca106725 1883 #define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */
Kojto 122:f9eeca106725 1884 #define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
Kojto 122:f9eeca106725 1885 #define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 1886 #define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 1887 #define GPIO_MODER_MODER4_Pos (8U)
Kojto 122:f9eeca106725 1888 #define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */
Kojto 122:f9eeca106725 1889 #define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
Kojto 122:f9eeca106725 1890 #define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 1891 #define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 1892 #define GPIO_MODER_MODER5_Pos (10U)
Kojto 122:f9eeca106725 1893 #define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */
Kojto 122:f9eeca106725 1894 #define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
Kojto 122:f9eeca106725 1895 #define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 1896 #define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 1897 #define GPIO_MODER_MODER6_Pos (12U)
Kojto 122:f9eeca106725 1898 #define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */
Kojto 122:f9eeca106725 1899 #define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
Kojto 122:f9eeca106725 1900 #define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 1901 #define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 1902 #define GPIO_MODER_MODER7_Pos (14U)
Kojto 122:f9eeca106725 1903 #define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */
Kojto 122:f9eeca106725 1904 #define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
Kojto 122:f9eeca106725 1905 #define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 1906 #define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 1907 #define GPIO_MODER_MODER8_Pos (16U)
Kojto 122:f9eeca106725 1908 #define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */
Kojto 122:f9eeca106725 1909 #define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
Kojto 122:f9eeca106725 1910 #define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 1911 #define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 1912 #define GPIO_MODER_MODER9_Pos (18U)
Kojto 122:f9eeca106725 1913 #define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */
Kojto 122:f9eeca106725 1914 #define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
Kojto 122:f9eeca106725 1915 #define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 1916 #define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 1917 #define GPIO_MODER_MODER10_Pos (20U)
Kojto 122:f9eeca106725 1918 #define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */
Kojto 122:f9eeca106725 1919 #define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
Kojto 122:f9eeca106725 1920 #define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 1921 #define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 1922 #define GPIO_MODER_MODER11_Pos (22U)
Kojto 122:f9eeca106725 1923 #define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */
Kojto 122:f9eeca106725 1924 #define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
Kojto 122:f9eeca106725 1925 #define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 1926 #define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 1927 #define GPIO_MODER_MODER12_Pos (24U)
Kojto 122:f9eeca106725 1928 #define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */
Kojto 122:f9eeca106725 1929 #define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
Kojto 122:f9eeca106725 1930 #define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 1931 #define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 1932 #define GPIO_MODER_MODER13_Pos (26U)
Kojto 122:f9eeca106725 1933 #define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */
Kojto 122:f9eeca106725 1934 #define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
Kojto 122:f9eeca106725 1935 #define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 1936 #define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 1937 #define GPIO_MODER_MODER14_Pos (28U)
Kojto 122:f9eeca106725 1938 #define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */
Kojto 122:f9eeca106725 1939 #define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
Kojto 122:f9eeca106725 1940 #define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 1941 #define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 1942 #define GPIO_MODER_MODER15_Pos (30U)
Kojto 122:f9eeca106725 1943 #define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */
Kojto 122:f9eeca106725 1944 #define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
Kojto 122:f9eeca106725 1945 #define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 1946 #define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
Kojto 90:cb3d968589d8 1947
Kojto 90:cb3d968589d8 1948 /****************** Bit definition for GPIO_OTYPER register *****************/
Kojto 122:f9eeca106725 1949 #define GPIO_OTYPER_OT_0 (0x00000001U)
Kojto 122:f9eeca106725 1950 #define GPIO_OTYPER_OT_1 (0x00000002U)
Kojto 122:f9eeca106725 1951 #define GPIO_OTYPER_OT_2 (0x00000004U)
Kojto 122:f9eeca106725 1952 #define GPIO_OTYPER_OT_3 (0x00000008U)
Kojto 122:f9eeca106725 1953 #define GPIO_OTYPER_OT_4 (0x00000010U)
Kojto 122:f9eeca106725 1954 #define GPIO_OTYPER_OT_5 (0x00000020U)
Kojto 122:f9eeca106725 1955 #define GPIO_OTYPER_OT_6 (0x00000040U)
Kojto 122:f9eeca106725 1956 #define GPIO_OTYPER_OT_7 (0x00000080U)
Kojto 122:f9eeca106725 1957 #define GPIO_OTYPER_OT_8 (0x00000100U)
Kojto 122:f9eeca106725 1958 #define GPIO_OTYPER_OT_9 (0x00000200U)
Kojto 122:f9eeca106725 1959 #define GPIO_OTYPER_OT_10 (0x00000400U)
Kojto 122:f9eeca106725 1960 #define GPIO_OTYPER_OT_11 (0x00000800U)
Kojto 122:f9eeca106725 1961 #define GPIO_OTYPER_OT_12 (0x00001000U)
Kojto 122:f9eeca106725 1962 #define GPIO_OTYPER_OT_13 (0x00002000U)
Kojto 122:f9eeca106725 1963 #define GPIO_OTYPER_OT_14 (0x00004000U)
Kojto 122:f9eeca106725 1964 #define GPIO_OTYPER_OT_15 (0x00008000U)
Kojto 90:cb3d968589d8 1965
Kojto 90:cb3d968589d8 1966 /**************** Bit definition for GPIO_OSPEEDR register ******************/
Kojto 122:f9eeca106725 1967 #define GPIO_OSPEEDR_OSPEEDR0_Pos (0U)
Kojto 122:f9eeca106725 1968 #define GPIO_OSPEEDR_OSPEEDR0_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000003 */
Kojto 122:f9eeca106725 1969 #define GPIO_OSPEEDR_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0_Msk
Kojto 122:f9eeca106725 1970 #define GPIO_OSPEEDR_OSPEEDR0_0 (0x1U << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 1971 #define GPIO_OSPEEDR_OSPEEDR0_1 (0x2U << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 1972 #define GPIO_OSPEEDR_OSPEEDR1_Pos (2U)
Kojto 122:f9eeca106725 1973 #define GPIO_OSPEEDR_OSPEEDR1_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x0000000C */
Kojto 122:f9eeca106725 1974 #define GPIO_OSPEEDR_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1_Msk
Kojto 122:f9eeca106725 1975 #define GPIO_OSPEEDR_OSPEEDR1_0 (0x1U << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 1976 #define GPIO_OSPEEDR_OSPEEDR1_1 (0x2U << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 1977 #define GPIO_OSPEEDR_OSPEEDR2_Pos (4U)
Kojto 122:f9eeca106725 1978 #define GPIO_OSPEEDR_OSPEEDR2_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000030 */
Kojto 122:f9eeca106725 1979 #define GPIO_OSPEEDR_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2_Msk
Kojto 122:f9eeca106725 1980 #define GPIO_OSPEEDR_OSPEEDR2_0 (0x1U << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 1981 #define GPIO_OSPEEDR_OSPEEDR2_1 (0x2U << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 1982 #define GPIO_OSPEEDR_OSPEEDR3_Pos (6U)
Kojto 122:f9eeca106725 1983 #define GPIO_OSPEEDR_OSPEEDR3_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x000000C0 */
Kojto 122:f9eeca106725 1984 #define GPIO_OSPEEDR_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3_Msk
Kojto 122:f9eeca106725 1985 #define GPIO_OSPEEDR_OSPEEDR3_0 (0x1U << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 1986 #define GPIO_OSPEEDR_OSPEEDR3_1 (0x2U << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 1987 #define GPIO_OSPEEDR_OSPEEDR4_Pos (8U)
Kojto 122:f9eeca106725 1988 #define GPIO_OSPEEDR_OSPEEDR4_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000300 */
Kojto 122:f9eeca106725 1989 #define GPIO_OSPEEDR_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4_Msk
Kojto 122:f9eeca106725 1990 #define GPIO_OSPEEDR_OSPEEDR4_0 (0x1U << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 1991 #define GPIO_OSPEEDR_OSPEEDR4_1 (0x2U << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 1992 #define GPIO_OSPEEDR_OSPEEDR5_Pos (10U)
Kojto 122:f9eeca106725 1993 #define GPIO_OSPEEDR_OSPEEDR5_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000C00 */
Kojto 122:f9eeca106725 1994 #define GPIO_OSPEEDR_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5_Msk
Kojto 122:f9eeca106725 1995 #define GPIO_OSPEEDR_OSPEEDR5_0 (0x1U << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 1996 #define GPIO_OSPEEDR_OSPEEDR5_1 (0x2U << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 1997 #define GPIO_OSPEEDR_OSPEEDR6_Pos (12U)
Kojto 122:f9eeca106725 1998 #define GPIO_OSPEEDR_OSPEEDR6_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00003000 */
Kojto 122:f9eeca106725 1999 #define GPIO_OSPEEDR_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6_Msk
Kojto 122:f9eeca106725 2000 #define GPIO_OSPEEDR_OSPEEDR6_0 (0x1U << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 2001 #define GPIO_OSPEEDR_OSPEEDR6_1 (0x2U << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 2002 #define GPIO_OSPEEDR_OSPEEDR7_Pos (14U)
Kojto 122:f9eeca106725 2003 #define GPIO_OSPEEDR_OSPEEDR7_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x0000C000 */
Kojto 122:f9eeca106725 2004 #define GPIO_OSPEEDR_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7_Msk
Kojto 122:f9eeca106725 2005 #define GPIO_OSPEEDR_OSPEEDR7_0 (0x1U << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 2006 #define GPIO_OSPEEDR_OSPEEDR7_1 (0x2U << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 2007 #define GPIO_OSPEEDR_OSPEEDR8_Pos (16U)
Kojto 122:f9eeca106725 2008 #define GPIO_OSPEEDR_OSPEEDR8_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00030000 */
Kojto 122:f9eeca106725 2009 #define GPIO_OSPEEDR_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8_Msk
Kojto 122:f9eeca106725 2010 #define GPIO_OSPEEDR_OSPEEDR8_0 (0x1U << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 2011 #define GPIO_OSPEEDR_OSPEEDR8_1 (0x2U << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 2012 #define GPIO_OSPEEDR_OSPEEDR9_Pos (18U)
Kojto 122:f9eeca106725 2013 #define GPIO_OSPEEDR_OSPEEDR9_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x000C0000 */
Kojto 122:f9eeca106725 2014 #define GPIO_OSPEEDR_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9_Msk
Kojto 122:f9eeca106725 2015 #define GPIO_OSPEEDR_OSPEEDR9_0 (0x1U << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 2016 #define GPIO_OSPEEDR_OSPEEDR9_1 (0x2U << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 2017 #define GPIO_OSPEEDR_OSPEEDR10_Pos (20U)
Kojto 122:f9eeca106725 2018 #define GPIO_OSPEEDR_OSPEEDR10_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00300000 */
Kojto 122:f9eeca106725 2019 #define GPIO_OSPEEDR_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10_Msk
Kojto 122:f9eeca106725 2020 #define GPIO_OSPEEDR_OSPEEDR10_0 (0x1U << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 2021 #define GPIO_OSPEEDR_OSPEEDR10_1 (0x2U << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 2022 #define GPIO_OSPEEDR_OSPEEDR11_Pos (22U)
Kojto 122:f9eeca106725 2023 #define GPIO_OSPEEDR_OSPEEDR11_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00C00000 */
Kojto 122:f9eeca106725 2024 #define GPIO_OSPEEDR_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11_Msk
Kojto 122:f9eeca106725 2025 #define GPIO_OSPEEDR_OSPEEDR11_0 (0x1U << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 2026 #define GPIO_OSPEEDR_OSPEEDR11_1 (0x2U << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 2027 #define GPIO_OSPEEDR_OSPEEDR12_Pos (24U)
Kojto 122:f9eeca106725 2028 #define GPIO_OSPEEDR_OSPEEDR12_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x03000000 */
Kojto 122:f9eeca106725 2029 #define GPIO_OSPEEDR_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12_Msk
Kojto 122:f9eeca106725 2030 #define GPIO_OSPEEDR_OSPEEDR12_0 (0x1U << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 2031 #define GPIO_OSPEEDR_OSPEEDR12_1 (0x2U << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 2032 #define GPIO_OSPEEDR_OSPEEDR13_Pos (26U)
Kojto 122:f9eeca106725 2033 #define GPIO_OSPEEDR_OSPEEDR13_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x0C000000 */
Kojto 122:f9eeca106725 2034 #define GPIO_OSPEEDR_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13_Msk
Kojto 122:f9eeca106725 2035 #define GPIO_OSPEEDR_OSPEEDR13_0 (0x1U << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 2036 #define GPIO_OSPEEDR_OSPEEDR13_1 (0x2U << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 2037 #define GPIO_OSPEEDR_OSPEEDR14_Pos (28U)
Kojto 122:f9eeca106725 2038 #define GPIO_OSPEEDR_OSPEEDR14_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x30000000 */
Kojto 122:f9eeca106725 2039 #define GPIO_OSPEEDR_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14_Msk
Kojto 122:f9eeca106725 2040 #define GPIO_OSPEEDR_OSPEEDR14_0 (0x1U << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 2041 #define GPIO_OSPEEDR_OSPEEDR14_1 (0x2U << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 2042 #define GPIO_OSPEEDR_OSPEEDR15_Pos (30U)
Kojto 122:f9eeca106725 2043 #define GPIO_OSPEEDR_OSPEEDR15_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0xC0000000 */
Kojto 122:f9eeca106725 2044 #define GPIO_OSPEEDR_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15_Msk
Kojto 122:f9eeca106725 2045 #define GPIO_OSPEEDR_OSPEEDR15_0 (0x1U << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 2046 #define GPIO_OSPEEDR_OSPEEDR15_1 (0x2U << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0x80000000 */
Kojto 90:cb3d968589d8 2047
Kojto 90:cb3d968589d8 2048 /* Old Bit definition for GPIO_OSPEEDR register maintained for legacy purpose */
Kojto 90:cb3d968589d8 2049 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0
Kojto 90:cb3d968589d8 2050 #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0
Kojto 90:cb3d968589d8 2051 #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1
Kojto 90:cb3d968589d8 2052 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1
Kojto 90:cb3d968589d8 2053 #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0
Kojto 90:cb3d968589d8 2054 #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1
Kojto 90:cb3d968589d8 2055 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2
Kojto 90:cb3d968589d8 2056 #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0
Kojto 90:cb3d968589d8 2057 #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1
Kojto 90:cb3d968589d8 2058 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3
Kojto 90:cb3d968589d8 2059 #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0
Kojto 90:cb3d968589d8 2060 #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1
Kojto 90:cb3d968589d8 2061 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4
Kojto 90:cb3d968589d8 2062 #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0
Kojto 90:cb3d968589d8 2063 #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1
Kojto 90:cb3d968589d8 2064 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5
Kojto 90:cb3d968589d8 2065 #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0
Kojto 90:cb3d968589d8 2066 #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1
Kojto 90:cb3d968589d8 2067 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6
Kojto 90:cb3d968589d8 2068 #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0
Kojto 90:cb3d968589d8 2069 #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1
Kojto 90:cb3d968589d8 2070 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7
Kojto 90:cb3d968589d8 2071 #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0
Kojto 90:cb3d968589d8 2072 #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1
Kojto 90:cb3d968589d8 2073 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8
Kojto 90:cb3d968589d8 2074 #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0
Kojto 90:cb3d968589d8 2075 #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1
Kojto 90:cb3d968589d8 2076 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9
Kojto 90:cb3d968589d8 2077 #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0
Kojto 90:cb3d968589d8 2078 #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1
Kojto 90:cb3d968589d8 2079 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10
Kojto 90:cb3d968589d8 2080 #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0
Kojto 90:cb3d968589d8 2081 #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1
Kojto 90:cb3d968589d8 2082 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11
Kojto 90:cb3d968589d8 2083 #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0
Kojto 90:cb3d968589d8 2084 #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1
Kojto 90:cb3d968589d8 2085 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12
Kojto 90:cb3d968589d8 2086 #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0
Kojto 90:cb3d968589d8 2087 #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1
Kojto 90:cb3d968589d8 2088 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13
Kojto 90:cb3d968589d8 2089 #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0
Kojto 90:cb3d968589d8 2090 #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1
Kojto 90:cb3d968589d8 2091 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14
Kojto 90:cb3d968589d8 2092 #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0
Kojto 90:cb3d968589d8 2093 #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1
Kojto 90:cb3d968589d8 2094 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15
Kojto 90:cb3d968589d8 2095 #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0
Kojto 90:cb3d968589d8 2096 #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1
Kojto 90:cb3d968589d8 2097
Kojto 90:cb3d968589d8 2098 /******************* Bit definition for GPIO_PUPDR register ******************/
Kojto 122:f9eeca106725 2099 #define GPIO_PUPDR_PUPDR0_Pos (0U)
Kojto 122:f9eeca106725 2100 #define GPIO_PUPDR_PUPDR0_Msk (0x3U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000003 */
Kojto 122:f9eeca106725 2101 #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPDR0_Msk
Kojto 122:f9eeca106725 2102 #define GPIO_PUPDR_PUPDR0_0 (0x1U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 2103 #define GPIO_PUPDR_PUPDR0_1 (0x2U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 2104 #define GPIO_PUPDR_PUPDR1_Pos (2U)
Kojto 122:f9eeca106725 2105 #define GPIO_PUPDR_PUPDR1_Msk (0x3U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x0000000C */
Kojto 122:f9eeca106725 2106 #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPDR1_Msk
Kojto 122:f9eeca106725 2107 #define GPIO_PUPDR_PUPDR1_0 (0x1U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 2108 #define GPIO_PUPDR_PUPDR1_1 (0x2U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 2109 #define GPIO_PUPDR_PUPDR2_Pos (4U)
Kojto 122:f9eeca106725 2110 #define GPIO_PUPDR_PUPDR2_Msk (0x3U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000030 */
Kojto 122:f9eeca106725 2111 #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPDR2_Msk
Kojto 122:f9eeca106725 2112 #define GPIO_PUPDR_PUPDR2_0 (0x1U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 2113 #define GPIO_PUPDR_PUPDR2_1 (0x2U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 2114 #define GPIO_PUPDR_PUPDR3_Pos (6U)
Kojto 122:f9eeca106725 2115 #define GPIO_PUPDR_PUPDR3_Msk (0x3U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x000000C0 */
Kojto 122:f9eeca106725 2116 #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPDR3_Msk
Kojto 122:f9eeca106725 2117 #define GPIO_PUPDR_PUPDR3_0 (0x1U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 2118 #define GPIO_PUPDR_PUPDR3_1 (0x2U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 2119 #define GPIO_PUPDR_PUPDR4_Pos (8U)
Kojto 122:f9eeca106725 2120 #define GPIO_PUPDR_PUPDR4_Msk (0x3U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000300 */
Kojto 122:f9eeca106725 2121 #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPDR4_Msk
Kojto 122:f9eeca106725 2122 #define GPIO_PUPDR_PUPDR4_0 (0x1U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 2123 #define GPIO_PUPDR_PUPDR4_1 (0x2U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 2124 #define GPIO_PUPDR_PUPDR5_Pos (10U)
Kojto 122:f9eeca106725 2125 #define GPIO_PUPDR_PUPDR5_Msk (0x3U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000C00 */
Kojto 122:f9eeca106725 2126 #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPDR5_Msk
Kojto 122:f9eeca106725 2127 #define GPIO_PUPDR_PUPDR5_0 (0x1U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 2128 #define GPIO_PUPDR_PUPDR5_1 (0x2U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 2129 #define GPIO_PUPDR_PUPDR6_Pos (12U)
Kojto 122:f9eeca106725 2130 #define GPIO_PUPDR_PUPDR6_Msk (0x3U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00003000 */
Kojto 122:f9eeca106725 2131 #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPDR6_Msk
Kojto 122:f9eeca106725 2132 #define GPIO_PUPDR_PUPDR6_0 (0x1U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 2133 #define GPIO_PUPDR_PUPDR6_1 (0x2U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 2134 #define GPIO_PUPDR_PUPDR7_Pos (14U)
Kojto 122:f9eeca106725 2135 #define GPIO_PUPDR_PUPDR7_Msk (0x3U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x0000C000 */
Kojto 122:f9eeca106725 2136 #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPDR7_Msk
Kojto 122:f9eeca106725 2137 #define GPIO_PUPDR_PUPDR7_0 (0x1U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 2138 #define GPIO_PUPDR_PUPDR7_1 (0x2U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 2139 #define GPIO_PUPDR_PUPDR8_Pos (16U)
Kojto 122:f9eeca106725 2140 #define GPIO_PUPDR_PUPDR8_Msk (0x3U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00030000 */
Kojto 122:f9eeca106725 2141 #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPDR8_Msk
Kojto 122:f9eeca106725 2142 #define GPIO_PUPDR_PUPDR8_0 (0x1U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 2143 #define GPIO_PUPDR_PUPDR8_1 (0x2U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 2144 #define GPIO_PUPDR_PUPDR9_Pos (18U)
Kojto 122:f9eeca106725 2145 #define GPIO_PUPDR_PUPDR9_Msk (0x3U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x000C0000 */
Kojto 122:f9eeca106725 2146 #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPDR9_Msk
Kojto 122:f9eeca106725 2147 #define GPIO_PUPDR_PUPDR9_0 (0x1U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 2148 #define GPIO_PUPDR_PUPDR9_1 (0x2U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 2149 #define GPIO_PUPDR_PUPDR10_Pos (20U)
Kojto 122:f9eeca106725 2150 #define GPIO_PUPDR_PUPDR10_Msk (0x3U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00300000 */
Kojto 122:f9eeca106725 2151 #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPDR10_Msk
Kojto 122:f9eeca106725 2152 #define GPIO_PUPDR_PUPDR10_0 (0x1U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 2153 #define GPIO_PUPDR_PUPDR10_1 (0x2U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 2154 #define GPIO_PUPDR_PUPDR11_Pos (22U)
Kojto 122:f9eeca106725 2155 #define GPIO_PUPDR_PUPDR11_Msk (0x3U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00C00000 */
Kojto 122:f9eeca106725 2156 #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPDR11_Msk
Kojto 122:f9eeca106725 2157 #define GPIO_PUPDR_PUPDR11_0 (0x1U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 2158 #define GPIO_PUPDR_PUPDR11_1 (0x2U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 2159 #define GPIO_PUPDR_PUPDR12_Pos (24U)
Kojto 122:f9eeca106725 2160 #define GPIO_PUPDR_PUPDR12_Msk (0x3U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x03000000 */
Kojto 122:f9eeca106725 2161 #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPDR12_Msk
Kojto 122:f9eeca106725 2162 #define GPIO_PUPDR_PUPDR12_0 (0x1U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 2163 #define GPIO_PUPDR_PUPDR12_1 (0x2U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 2164 #define GPIO_PUPDR_PUPDR13_Pos (26U)
Kojto 122:f9eeca106725 2165 #define GPIO_PUPDR_PUPDR13_Msk (0x3U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x0C000000 */
Kojto 122:f9eeca106725 2166 #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPDR13_Msk
Kojto 122:f9eeca106725 2167 #define GPIO_PUPDR_PUPDR13_0 (0x1U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 2168 #define GPIO_PUPDR_PUPDR13_1 (0x2U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 2169 #define GPIO_PUPDR_PUPDR14_Pos (28U)
Kojto 122:f9eeca106725 2170 #define GPIO_PUPDR_PUPDR14_Msk (0x3U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x30000000 */
Kojto 122:f9eeca106725 2171 #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPDR14_Msk
Kojto 122:f9eeca106725 2172 #define GPIO_PUPDR_PUPDR14_0 (0x1U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 2173 #define GPIO_PUPDR_PUPDR14_1 (0x2U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 2174 #define GPIO_PUPDR_PUPDR15_Pos (30U)
Kojto 122:f9eeca106725 2175 #define GPIO_PUPDR_PUPDR15_Msk (0x3U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0xC0000000 */
Kojto 122:f9eeca106725 2176 #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPDR15_Msk
Kojto 122:f9eeca106725 2177 #define GPIO_PUPDR_PUPDR15_0 (0x1U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 2178 #define GPIO_PUPDR_PUPDR15_1 (0x2U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */
Kojto 90:cb3d968589d8 2179
Kojto 90:cb3d968589d8 2180 /******************* Bit definition for GPIO_IDR register *******************/
Kojto 122:f9eeca106725 2181 #define GPIO_IDR_0 (0x00000001U)
Kojto 122:f9eeca106725 2182 #define GPIO_IDR_1 (0x00000002U)
Kojto 122:f9eeca106725 2183 #define GPIO_IDR_2 (0x00000004U)
Kojto 122:f9eeca106725 2184 #define GPIO_IDR_3 (0x00000008U)
Kojto 122:f9eeca106725 2185 #define GPIO_IDR_4 (0x00000010U)
Kojto 122:f9eeca106725 2186 #define GPIO_IDR_5 (0x00000020U)
Kojto 122:f9eeca106725 2187 #define GPIO_IDR_6 (0x00000040U)
Kojto 122:f9eeca106725 2188 #define GPIO_IDR_7 (0x00000080U)
Kojto 122:f9eeca106725 2189 #define GPIO_IDR_8 (0x00000100U)
Kojto 122:f9eeca106725 2190 #define GPIO_IDR_9 (0x00000200U)
Kojto 122:f9eeca106725 2191 #define GPIO_IDR_10 (0x00000400U)
Kojto 122:f9eeca106725 2192 #define GPIO_IDR_11 (0x00000800U)
Kojto 122:f9eeca106725 2193 #define GPIO_IDR_12 (0x00001000U)
Kojto 122:f9eeca106725 2194 #define GPIO_IDR_13 (0x00002000U)
Kojto 122:f9eeca106725 2195 #define GPIO_IDR_14 (0x00004000U)
Kojto 122:f9eeca106725 2196 #define GPIO_IDR_15 (0x00008000U)
Kojto 90:cb3d968589d8 2197
Kojto 90:cb3d968589d8 2198 /****************** Bit definition for GPIO_ODR register ********************/
Kojto 122:f9eeca106725 2199 #define GPIO_ODR_0 (0x00000001U)
Kojto 122:f9eeca106725 2200 #define GPIO_ODR_1 (0x00000002U)
Kojto 122:f9eeca106725 2201 #define GPIO_ODR_2 (0x00000004U)
Kojto 122:f9eeca106725 2202 #define GPIO_ODR_3 (0x00000008U)
Kojto 122:f9eeca106725 2203 #define GPIO_ODR_4 (0x00000010U)
Kojto 122:f9eeca106725 2204 #define GPIO_ODR_5 (0x00000020U)
Kojto 122:f9eeca106725 2205 #define GPIO_ODR_6 (0x00000040U)
Kojto 122:f9eeca106725 2206 #define GPIO_ODR_7 (0x00000080U)
Kojto 122:f9eeca106725 2207 #define GPIO_ODR_8 (0x00000100U)
Kojto 122:f9eeca106725 2208 #define GPIO_ODR_9 (0x00000200U)
Kojto 122:f9eeca106725 2209 #define GPIO_ODR_10 (0x00000400U)
Kojto 122:f9eeca106725 2210 #define GPIO_ODR_11 (0x00000800U)
Kojto 122:f9eeca106725 2211 #define GPIO_ODR_12 (0x00001000U)
Kojto 122:f9eeca106725 2212 #define GPIO_ODR_13 (0x00002000U)
Kojto 122:f9eeca106725 2213 #define GPIO_ODR_14 (0x00004000U)
Kojto 122:f9eeca106725 2214 #define GPIO_ODR_15 (0x00008000U)
Kojto 90:cb3d968589d8 2215
Kojto 90:cb3d968589d8 2216 /****************** Bit definition for GPIO_BSRR register ********************/
Kojto 122:f9eeca106725 2217 #define GPIO_BSRR_BS_0 (0x00000001U)
Kojto 122:f9eeca106725 2218 #define GPIO_BSRR_BS_1 (0x00000002U)
Kojto 122:f9eeca106725 2219 #define GPIO_BSRR_BS_2 (0x00000004U)
Kojto 122:f9eeca106725 2220 #define GPIO_BSRR_BS_3 (0x00000008U)
Kojto 122:f9eeca106725 2221 #define GPIO_BSRR_BS_4 (0x00000010U)
Kojto 122:f9eeca106725 2222 #define GPIO_BSRR_BS_5 (0x00000020U)
Kojto 122:f9eeca106725 2223 #define GPIO_BSRR_BS_6 (0x00000040U)
Kojto 122:f9eeca106725 2224 #define GPIO_BSRR_BS_7 (0x00000080U)
Kojto 122:f9eeca106725 2225 #define GPIO_BSRR_BS_8 (0x00000100U)
Kojto 122:f9eeca106725 2226 #define GPIO_BSRR_BS_9 (0x00000200U)
Kojto 122:f9eeca106725 2227 #define GPIO_BSRR_BS_10 (0x00000400U)
Kojto 122:f9eeca106725 2228 #define GPIO_BSRR_BS_11 (0x00000800U)
Kojto 122:f9eeca106725 2229 #define GPIO_BSRR_BS_12 (0x00001000U)
Kojto 122:f9eeca106725 2230 #define GPIO_BSRR_BS_13 (0x00002000U)
Kojto 122:f9eeca106725 2231 #define GPIO_BSRR_BS_14 (0x00004000U)
Kojto 122:f9eeca106725 2232 #define GPIO_BSRR_BS_15 (0x00008000U)
Kojto 122:f9eeca106725 2233 #define GPIO_BSRR_BR_0 (0x00010000U)
Kojto 122:f9eeca106725 2234 #define GPIO_BSRR_BR_1 (0x00020000U)
Kojto 122:f9eeca106725 2235 #define GPIO_BSRR_BR_2 (0x00040000U)
Kojto 122:f9eeca106725 2236 #define GPIO_BSRR_BR_3 (0x00080000U)
Kojto 122:f9eeca106725 2237 #define GPIO_BSRR_BR_4 (0x00100000U)
Kojto 122:f9eeca106725 2238 #define GPIO_BSRR_BR_5 (0x00200000U)
Kojto 122:f9eeca106725 2239 #define GPIO_BSRR_BR_6 (0x00400000U)
Kojto 122:f9eeca106725 2240 #define GPIO_BSRR_BR_7 (0x00800000U)
Kojto 122:f9eeca106725 2241 #define GPIO_BSRR_BR_8 (0x01000000U)
Kojto 122:f9eeca106725 2242 #define GPIO_BSRR_BR_9 (0x02000000U)
Kojto 122:f9eeca106725 2243 #define GPIO_BSRR_BR_10 (0x04000000U)
Kojto 122:f9eeca106725 2244 #define GPIO_BSRR_BR_11 (0x08000000U)
Kojto 122:f9eeca106725 2245 #define GPIO_BSRR_BR_12 (0x10000000U)
Kojto 122:f9eeca106725 2246 #define GPIO_BSRR_BR_13 (0x20000000U)
Kojto 122:f9eeca106725 2247 #define GPIO_BSRR_BR_14 (0x40000000U)
Kojto 122:f9eeca106725 2248 #define GPIO_BSRR_BR_15 (0x80000000U)
Kojto 90:cb3d968589d8 2249
Kojto 90:cb3d968589d8 2250 /****************** Bit definition for GPIO_LCKR register ********************/
Kojto 122:f9eeca106725 2251 #define GPIO_LCKR_LCK0_Pos (0U)
Kojto 122:f9eeca106725 2252 #define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 2253 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
Kojto 122:f9eeca106725 2254 #define GPIO_LCKR_LCK1_Pos (1U)
Kojto 122:f9eeca106725 2255 #define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 2256 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
Kojto 122:f9eeca106725 2257 #define GPIO_LCKR_LCK2_Pos (2U)
Kojto 122:f9eeca106725 2258 #define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 2259 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
Kojto 122:f9eeca106725 2260 #define GPIO_LCKR_LCK3_Pos (3U)
Kojto 122:f9eeca106725 2261 #define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 2262 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
Kojto 122:f9eeca106725 2263 #define GPIO_LCKR_LCK4_Pos (4U)
Kojto 122:f9eeca106725 2264 #define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 2265 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
Kojto 122:f9eeca106725 2266 #define GPIO_LCKR_LCK5_Pos (5U)
Kojto 122:f9eeca106725 2267 #define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 2268 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
Kojto 122:f9eeca106725 2269 #define GPIO_LCKR_LCK6_Pos (6U)
Kojto 122:f9eeca106725 2270 #define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 2271 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
Kojto 122:f9eeca106725 2272 #define GPIO_LCKR_LCK7_Pos (7U)
Kojto 122:f9eeca106725 2273 #define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 2274 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
Kojto 122:f9eeca106725 2275 #define GPIO_LCKR_LCK8_Pos (8U)
Kojto 122:f9eeca106725 2276 #define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 2277 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
Kojto 122:f9eeca106725 2278 #define GPIO_LCKR_LCK9_Pos (9U)
Kojto 122:f9eeca106725 2279 #define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 2280 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
Kojto 122:f9eeca106725 2281 #define GPIO_LCKR_LCK10_Pos (10U)
Kojto 122:f9eeca106725 2282 #define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 2283 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
Kojto 122:f9eeca106725 2284 #define GPIO_LCKR_LCK11_Pos (11U)
Kojto 122:f9eeca106725 2285 #define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 2286 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
Kojto 122:f9eeca106725 2287 #define GPIO_LCKR_LCK12_Pos (12U)
Kojto 122:f9eeca106725 2288 #define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 2289 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
Kojto 122:f9eeca106725 2290 #define GPIO_LCKR_LCK13_Pos (13U)
Kojto 122:f9eeca106725 2291 #define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 2292 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
Kojto 122:f9eeca106725 2293 #define GPIO_LCKR_LCK14_Pos (14U)
Kojto 122:f9eeca106725 2294 #define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 2295 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
Kojto 122:f9eeca106725 2296 #define GPIO_LCKR_LCK15_Pos (15U)
Kojto 122:f9eeca106725 2297 #define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 2298 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
Kojto 122:f9eeca106725 2299 #define GPIO_LCKR_LCKK_Pos (16U)
Kojto 122:f9eeca106725 2300 #define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 2301 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
Kojto 90:cb3d968589d8 2302
Kojto 90:cb3d968589d8 2303 /****************** Bit definition for GPIO_AFRL register ********************/
Kojto 122:f9eeca106725 2304 #define GPIO_AFRL_AFRL0_Pos (0U)
Kojto 122:f9eeca106725 2305 #define GPIO_AFRL_AFRL0_Msk (0xFU << GPIO_AFRL_AFRL0_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 2306 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk
Kojto 122:f9eeca106725 2307 #define GPIO_AFRL_AFRL1_Pos (4U)
Kojto 122:f9eeca106725 2308 #define GPIO_AFRL_AFRL1_Msk (0xFU << GPIO_AFRL_AFRL1_Pos) /*!< 0x000000F0 */
Kojto 122:f9eeca106725 2309 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk
Kojto 122:f9eeca106725 2310 #define GPIO_AFRL_AFRL2_Pos (8U)
Kojto 122:f9eeca106725 2311 #define GPIO_AFRL_AFRL2_Msk (0xFU << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000F00 */
Kojto 122:f9eeca106725 2312 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk
Kojto 122:f9eeca106725 2313 #define GPIO_AFRL_AFRL3_Pos (12U)
Kojto 122:f9eeca106725 2314 #define GPIO_AFRL_AFRL3_Msk (0xFU << GPIO_AFRL_AFRL3_Pos) /*!< 0x0000F000 */
Kojto 122:f9eeca106725 2315 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk
Kojto 122:f9eeca106725 2316 #define GPIO_AFRL_AFRL4_Pos (16U)
Kojto 122:f9eeca106725 2317 #define GPIO_AFRL_AFRL4_Msk (0xFU << GPIO_AFRL_AFRL4_Pos) /*!< 0x000F0000 */
Kojto 122:f9eeca106725 2318 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk
Kojto 122:f9eeca106725 2319 #define GPIO_AFRL_AFRL5_Pos (20U)
Kojto 122:f9eeca106725 2320 #define GPIO_AFRL_AFRL5_Msk (0xFU << GPIO_AFRL_AFRL5_Pos) /*!< 0x00F00000 */
Kojto 122:f9eeca106725 2321 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk
Kojto 122:f9eeca106725 2322 #define GPIO_AFRL_AFRL6_Pos (24U)
Kojto 122:f9eeca106725 2323 #define GPIO_AFRL_AFRL6_Msk (0xFU << GPIO_AFRL_AFRL6_Pos) /*!< 0x0F000000 */
Kojto 122:f9eeca106725 2324 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk
Kojto 122:f9eeca106725 2325 #define GPIO_AFRL_AFRL7_Pos (28U)
Kojto 122:f9eeca106725 2326 #define GPIO_AFRL_AFRL7_Msk (0xFU << GPIO_AFRL_AFRL7_Pos) /*!< 0xF0000000 */
Kojto 122:f9eeca106725 2327 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk
Kojto 90:cb3d968589d8 2328
Kojto 90:cb3d968589d8 2329 /****************** Bit definition for GPIO_AFRH register ********************/
Kojto 122:f9eeca106725 2330 #define GPIO_AFRH_AFRH0_Pos (0U)
Kojto 122:f9eeca106725 2331 #define GPIO_AFRH_AFRH0_Msk (0xFU << GPIO_AFRH_AFRH0_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 2332 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk
Kojto 122:f9eeca106725 2333 #define GPIO_AFRH_AFRH1_Pos (4U)
Kojto 122:f9eeca106725 2334 #define GPIO_AFRH_AFRH1_Msk (0xFU << GPIO_AFRH_AFRH1_Pos) /*!< 0x000000F0 */
Kojto 122:f9eeca106725 2335 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk
Kojto 122:f9eeca106725 2336 #define GPIO_AFRH_AFRH2_Pos (8U)
Kojto 122:f9eeca106725 2337 #define GPIO_AFRH_AFRH2_Msk (0xFU << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000F00 */
Kojto 122:f9eeca106725 2338 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk
Kojto 122:f9eeca106725 2339 #define GPIO_AFRH_AFRH3_Pos (12U)
Kojto 122:f9eeca106725 2340 #define GPIO_AFRH_AFRH3_Msk (0xFU << GPIO_AFRH_AFRH3_Pos) /*!< 0x0000F000 */
Kojto 122:f9eeca106725 2341 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk
Kojto 122:f9eeca106725 2342 #define GPIO_AFRH_AFRH4_Pos (16U)
Kojto 122:f9eeca106725 2343 #define GPIO_AFRH_AFRH4_Msk (0xFU << GPIO_AFRH_AFRH4_Pos) /*!< 0x000F0000 */
Kojto 122:f9eeca106725 2344 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk
Kojto 122:f9eeca106725 2345 #define GPIO_AFRH_AFRH5_Pos (20U)
Kojto 122:f9eeca106725 2346 #define GPIO_AFRH_AFRH5_Msk (0xFU << GPIO_AFRH_AFRH5_Pos) /*!< 0x00F00000 */
Kojto 122:f9eeca106725 2347 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk
Kojto 122:f9eeca106725 2348 #define GPIO_AFRH_AFRH6_Pos (24U)
Kojto 122:f9eeca106725 2349 #define GPIO_AFRH_AFRH6_Msk (0xFU << GPIO_AFRH_AFRH6_Pos) /*!< 0x0F000000 */
Kojto 122:f9eeca106725 2350 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk
Kojto 122:f9eeca106725 2351 #define GPIO_AFRH_AFRH7_Pos (28U)
Kojto 122:f9eeca106725 2352 #define GPIO_AFRH_AFRH7_Msk (0xFU << GPIO_AFRH_AFRH7_Pos) /*!< 0xF0000000 */
Kojto 122:f9eeca106725 2353 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk
Kojto 90:cb3d968589d8 2354
Kojto 90:cb3d968589d8 2355 /****************** Bit definition for GPIO_BRR register *********************/
Kojto 122:f9eeca106725 2356 #define GPIO_BRR_BR_0 (0x00000001U)
Kojto 122:f9eeca106725 2357 #define GPIO_BRR_BR_1 (0x00000002U)
Kojto 122:f9eeca106725 2358 #define GPIO_BRR_BR_2 (0x00000004U)
Kojto 122:f9eeca106725 2359 #define GPIO_BRR_BR_3 (0x00000008U)
Kojto 122:f9eeca106725 2360 #define GPIO_BRR_BR_4 (0x00000010U)
Kojto 122:f9eeca106725 2361 #define GPIO_BRR_BR_5 (0x00000020U)
Kojto 122:f9eeca106725 2362 #define GPIO_BRR_BR_6 (0x00000040U)
Kojto 122:f9eeca106725 2363 #define GPIO_BRR_BR_7 (0x00000080U)
Kojto 122:f9eeca106725 2364 #define GPIO_BRR_BR_8 (0x00000100U)
Kojto 122:f9eeca106725 2365 #define GPIO_BRR_BR_9 (0x00000200U)
Kojto 122:f9eeca106725 2366 #define GPIO_BRR_BR_10 (0x00000400U)
Kojto 122:f9eeca106725 2367 #define GPIO_BRR_BR_11 (0x00000800U)
Kojto 122:f9eeca106725 2368 #define GPIO_BRR_BR_12 (0x00001000U)
Kojto 122:f9eeca106725 2369 #define GPIO_BRR_BR_13 (0x00002000U)
Kojto 122:f9eeca106725 2370 #define GPIO_BRR_BR_14 (0x00004000U)
Kojto 122:f9eeca106725 2371 #define GPIO_BRR_BR_15 (0x00008000U)
Kojto 90:cb3d968589d8 2372
Kojto 90:cb3d968589d8 2373 /******************************************************************************/
Kojto 90:cb3d968589d8 2374 /* */
Kojto 90:cb3d968589d8 2375 /* Inter-integrated Circuit Interface (I2C) */
Kojto 90:cb3d968589d8 2376 /* */
Kojto 90:cb3d968589d8 2377 /******************************************************************************/
Kojto 90:cb3d968589d8 2378
Kojto 90:cb3d968589d8 2379 /******************* Bit definition for I2C_CR1 register *******************/
Kojto 122:f9eeca106725 2380 #define I2C_CR1_PE_Pos (0U)
Kojto 122:f9eeca106725 2381 #define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 2382 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
Kojto 122:f9eeca106725 2383 #define I2C_CR1_TXIE_Pos (1U)
Kojto 122:f9eeca106725 2384 #define I2C_CR1_TXIE_Msk (0x1U << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 2385 #define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
Kojto 122:f9eeca106725 2386 #define I2C_CR1_RXIE_Pos (2U)
Kojto 122:f9eeca106725 2387 #define I2C_CR1_RXIE_Msk (0x1U << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 2388 #define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
Kojto 122:f9eeca106725 2389 #define I2C_CR1_ADDRIE_Pos (3U)
Kojto 122:f9eeca106725 2390 #define I2C_CR1_ADDRIE_Msk (0x1U << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 2391 #define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
Kojto 122:f9eeca106725 2392 #define I2C_CR1_NACKIE_Pos (4U)
Kojto 122:f9eeca106725 2393 #define I2C_CR1_NACKIE_Msk (0x1U << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 2394 #define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
Kojto 122:f9eeca106725 2395 #define I2C_CR1_STOPIE_Pos (5U)
Kojto 122:f9eeca106725 2396 #define I2C_CR1_STOPIE_Msk (0x1U << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 2397 #define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
Kojto 122:f9eeca106725 2398 #define I2C_CR1_TCIE_Pos (6U)
Kojto 122:f9eeca106725 2399 #define I2C_CR1_TCIE_Msk (0x1U << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 2400 #define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
Kojto 122:f9eeca106725 2401 #define I2C_CR1_ERRIE_Pos (7U)
Kojto 122:f9eeca106725 2402 #define I2C_CR1_ERRIE_Msk (0x1U << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 2403 #define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
Kojto 122:f9eeca106725 2404 #define I2C_CR1_DNF_Pos (8U)
Kojto 122:f9eeca106725 2405 #define I2C_CR1_DNF_Msk (0xFU << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
Kojto 122:f9eeca106725 2406 #define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
Kojto 122:f9eeca106725 2407 #define I2C_CR1_ANFOFF_Pos (12U)
Kojto 122:f9eeca106725 2408 #define I2C_CR1_ANFOFF_Msk (0x1U << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 2409 #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
Kojto 122:f9eeca106725 2410 #define I2C_CR1_SWRST_Pos (13U)
Kojto 122:f9eeca106725 2411 #define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 2412 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */
Kojto 122:f9eeca106725 2413 #define I2C_CR1_TXDMAEN_Pos (14U)
Kojto 122:f9eeca106725 2414 #define I2C_CR1_TXDMAEN_Msk (0x1U << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 2415 #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
Kojto 122:f9eeca106725 2416 #define I2C_CR1_RXDMAEN_Pos (15U)
Kojto 122:f9eeca106725 2417 #define I2C_CR1_RXDMAEN_Msk (0x1U << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 2418 #define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
Kojto 122:f9eeca106725 2419 #define I2C_CR1_SBC_Pos (16U)
Kojto 122:f9eeca106725 2420 #define I2C_CR1_SBC_Msk (0x1U << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 2421 #define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
Kojto 122:f9eeca106725 2422 #define I2C_CR1_NOSTRETCH_Pos (17U)
Kojto 122:f9eeca106725 2423 #define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 2424 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
Kojto 122:f9eeca106725 2425 #define I2C_CR1_GCEN_Pos (19U)
Kojto 122:f9eeca106725 2426 #define I2C_CR1_GCEN_Msk (0x1U << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 2427 #define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
Kojto 122:f9eeca106725 2428 #define I2C_CR1_SMBHEN_Pos (20U)
Kojto 122:f9eeca106725 2429 #define I2C_CR1_SMBHEN_Msk (0x1U << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 2430 #define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
Kojto 122:f9eeca106725 2431 #define I2C_CR1_SMBDEN_Pos (21U)
Kojto 122:f9eeca106725 2432 #define I2C_CR1_SMBDEN_Msk (0x1U << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 2433 #define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
Kojto 122:f9eeca106725 2434 #define I2C_CR1_ALERTEN_Pos (22U)
Kojto 122:f9eeca106725 2435 #define I2C_CR1_ALERTEN_Msk (0x1U << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 2436 #define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
Kojto 122:f9eeca106725 2437 #define I2C_CR1_PECEN_Pos (23U)
Kojto 122:f9eeca106725 2438 #define I2C_CR1_PECEN_Msk (0x1U << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 2439 #define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
Kojto 90:cb3d968589d8 2440
Kojto 90:cb3d968589d8 2441 /****************** Bit definition for I2C_CR2 register ********************/
Kojto 122:f9eeca106725 2442 #define I2C_CR2_SADD_Pos (0U)
Kojto 122:f9eeca106725 2443 #define I2C_CR2_SADD_Msk (0x3FFU << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
Kojto 122:f9eeca106725 2444 #define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
Kojto 122:f9eeca106725 2445 #define I2C_CR2_RD_WRN_Pos (10U)
Kojto 122:f9eeca106725 2446 #define I2C_CR2_RD_WRN_Msk (0x1U << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 2447 #define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
Kojto 122:f9eeca106725 2448 #define I2C_CR2_ADD10_Pos (11U)
Kojto 122:f9eeca106725 2449 #define I2C_CR2_ADD10_Msk (0x1U << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 2450 #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
Kojto 122:f9eeca106725 2451 #define I2C_CR2_HEAD10R_Pos (12U)
Kojto 122:f9eeca106725 2452 #define I2C_CR2_HEAD10R_Msk (0x1U << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 2453 #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
Kojto 122:f9eeca106725 2454 #define I2C_CR2_START_Pos (13U)
Kojto 122:f9eeca106725 2455 #define I2C_CR2_START_Msk (0x1U << I2C_CR2_START_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 2456 #define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
Kojto 122:f9eeca106725 2457 #define I2C_CR2_STOP_Pos (14U)
Kojto 122:f9eeca106725 2458 #define I2C_CR2_STOP_Msk (0x1U << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 2459 #define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
Kojto 122:f9eeca106725 2460 #define I2C_CR2_NACK_Pos (15U)
Kojto 122:f9eeca106725 2461 #define I2C_CR2_NACK_Msk (0x1U << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 2462 #define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
Kojto 122:f9eeca106725 2463 #define I2C_CR2_NBYTES_Pos (16U)
Kojto 122:f9eeca106725 2464 #define I2C_CR2_NBYTES_Msk (0xFFU << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
Kojto 122:f9eeca106725 2465 #define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
Kojto 122:f9eeca106725 2466 #define I2C_CR2_RELOAD_Pos (24U)
Kojto 122:f9eeca106725 2467 #define I2C_CR2_RELOAD_Msk (0x1U << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 2468 #define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
Kojto 122:f9eeca106725 2469 #define I2C_CR2_AUTOEND_Pos (25U)
Kojto 122:f9eeca106725 2470 #define I2C_CR2_AUTOEND_Msk (0x1U << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 2471 #define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
Kojto 122:f9eeca106725 2472 #define I2C_CR2_PECBYTE_Pos (26U)
Kojto 122:f9eeca106725 2473 #define I2C_CR2_PECBYTE_Msk (0x1U << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 2474 #define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
Kojto 90:cb3d968589d8 2475
Kojto 90:cb3d968589d8 2476 /******************* Bit definition for I2C_OAR1 register ******************/
Kojto 122:f9eeca106725 2477 #define I2C_OAR1_OA1_Pos (0U)
Kojto 122:f9eeca106725 2478 #define I2C_OAR1_OA1_Msk (0x3FFU << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
Kojto 122:f9eeca106725 2479 #define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
Kojto 122:f9eeca106725 2480 #define I2C_OAR1_OA1MODE_Pos (10U)
Kojto 122:f9eeca106725 2481 #define I2C_OAR1_OA1MODE_Msk (0x1U << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 2482 #define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
Kojto 122:f9eeca106725 2483 #define I2C_OAR1_OA1EN_Pos (15U)
Kojto 122:f9eeca106725 2484 #define I2C_OAR1_OA1EN_Msk (0x1U << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 2485 #define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
Kojto 90:cb3d968589d8 2486
Kojto 90:cb3d968589d8 2487 /******************* Bit definition for I2C_OAR2 register ******************/
Kojto 122:f9eeca106725 2488 #define I2C_OAR2_OA2_Pos (1U)
Kojto 122:f9eeca106725 2489 #define I2C_OAR2_OA2_Msk (0x7FU << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
Kojto 122:f9eeca106725 2490 #define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
Kojto 122:f9eeca106725 2491 #define I2C_OAR2_OA2MSK_Pos (8U)
Kojto 122:f9eeca106725 2492 #define I2C_OAR2_OA2MSK_Msk (0x7U << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
Kojto 122:f9eeca106725 2493 #define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
Kojto 122:f9eeca106725 2494 #define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */
Kojto 122:f9eeca106725 2495 #define I2C_OAR2_OA2MASK01_Pos (8U)
Kojto 122:f9eeca106725 2496 #define I2C_OAR2_OA2MASK01_Msk (0x1U << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 2497 #define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
Kojto 122:f9eeca106725 2498 #define I2C_OAR2_OA2MASK02_Pos (9U)
Kojto 122:f9eeca106725 2499 #define I2C_OAR2_OA2MASK02_Msk (0x1U << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 2500 #define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
Kojto 122:f9eeca106725 2501 #define I2C_OAR2_OA2MASK03_Pos (8U)
Kojto 122:f9eeca106725 2502 #define I2C_OAR2_OA2MASK03_Msk (0x3U << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
Kojto 122:f9eeca106725 2503 #define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
Kojto 122:f9eeca106725 2504 #define I2C_OAR2_OA2MASK04_Pos (10U)
Kojto 122:f9eeca106725 2505 #define I2C_OAR2_OA2MASK04_Msk (0x1U << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 2506 #define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
Kojto 122:f9eeca106725 2507 #define I2C_OAR2_OA2MASK05_Pos (8U)
Kojto 122:f9eeca106725 2508 #define I2C_OAR2_OA2MASK05_Msk (0x5U << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
Kojto 122:f9eeca106725 2509 #define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
Kojto 122:f9eeca106725 2510 #define I2C_OAR2_OA2MASK06_Pos (9U)
Kojto 122:f9eeca106725 2511 #define I2C_OAR2_OA2MASK06_Msk (0x3U << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
Kojto 122:f9eeca106725 2512 #define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
Kojto 122:f9eeca106725 2513 #define I2C_OAR2_OA2MASK07_Pos (8U)
Kojto 122:f9eeca106725 2514 #define I2C_OAR2_OA2MASK07_Msk (0x7U << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
Kojto 122:f9eeca106725 2515 #define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
Kojto 122:f9eeca106725 2516 #define I2C_OAR2_OA2EN_Pos (15U)
Kojto 122:f9eeca106725 2517 #define I2C_OAR2_OA2EN_Msk (0x1U << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 2518 #define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
Kojto 90:cb3d968589d8 2519
Kojto 90:cb3d968589d8 2520 /******************* Bit definition for I2C_TIMINGR register ****************/
Kojto 122:f9eeca106725 2521 #define I2C_TIMINGR_SCLL_Pos (0U)
Kojto 122:f9eeca106725 2522 #define I2C_TIMINGR_SCLL_Msk (0xFFU << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 2523 #define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
Kojto 122:f9eeca106725 2524 #define I2C_TIMINGR_SCLH_Pos (8U)
Kojto 122:f9eeca106725 2525 #define I2C_TIMINGR_SCLH_Msk (0xFFU << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
Kojto 122:f9eeca106725 2526 #define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
Kojto 122:f9eeca106725 2527 #define I2C_TIMINGR_SDADEL_Pos (16U)
Kojto 122:f9eeca106725 2528 #define I2C_TIMINGR_SDADEL_Msk (0xFU << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
Kojto 122:f9eeca106725 2529 #define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
Kojto 122:f9eeca106725 2530 #define I2C_TIMINGR_SCLDEL_Pos (20U)
Kojto 122:f9eeca106725 2531 #define I2C_TIMINGR_SCLDEL_Msk (0xFU << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
Kojto 122:f9eeca106725 2532 #define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
Kojto 122:f9eeca106725 2533 #define I2C_TIMINGR_PRESC_Pos (28U)
Kojto 122:f9eeca106725 2534 #define I2C_TIMINGR_PRESC_Msk (0xFU << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
Kojto 122:f9eeca106725 2535 #define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
Kojto 90:cb3d968589d8 2536
Kojto 90:cb3d968589d8 2537 /******************* Bit definition for I2C_TIMEOUTR register ****************/
Kojto 122:f9eeca106725 2538 #define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
Kojto 122:f9eeca106725 2539 #define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
Kojto 122:f9eeca106725 2540 #define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
Kojto 122:f9eeca106725 2541 #define I2C_TIMEOUTR_TIDLE_Pos (12U)
Kojto 122:f9eeca106725 2542 #define I2C_TIMEOUTR_TIDLE_Msk (0x1U << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 2543 #define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
Kojto 122:f9eeca106725 2544 #define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
Kojto 122:f9eeca106725 2545 #define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1U << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 2546 #define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
Kojto 122:f9eeca106725 2547 #define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
Kojto 122:f9eeca106725 2548 #define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
Kojto 122:f9eeca106725 2549 #define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/
Kojto 122:f9eeca106725 2550 #define I2C_TIMEOUTR_TEXTEN_Pos (31U)
Kojto 122:f9eeca106725 2551 #define I2C_TIMEOUTR_TEXTEN_Msk (0x1U << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 2552 #define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
Kojto 90:cb3d968589d8 2553
Kojto 90:cb3d968589d8 2554 /****************** Bit definition for I2C_ISR register ********************/
Kojto 122:f9eeca106725 2555 #define I2C_ISR_TXE_Pos (0U)
Kojto 122:f9eeca106725 2556 #define I2C_ISR_TXE_Msk (0x1U << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 2557 #define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
Kojto 122:f9eeca106725 2558 #define I2C_ISR_TXIS_Pos (1U)
Kojto 122:f9eeca106725 2559 #define I2C_ISR_TXIS_Msk (0x1U << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 2560 #define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
Kojto 122:f9eeca106725 2561 #define I2C_ISR_RXNE_Pos (2U)
Kojto 122:f9eeca106725 2562 #define I2C_ISR_RXNE_Msk (0x1U << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 2563 #define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
Kojto 122:f9eeca106725 2564 #define I2C_ISR_ADDR_Pos (3U)
Kojto 122:f9eeca106725 2565 #define I2C_ISR_ADDR_Msk (0x1U << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 2566 #define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/
Kojto 122:f9eeca106725 2567 #define I2C_ISR_NACKF_Pos (4U)
Kojto 122:f9eeca106725 2568 #define I2C_ISR_NACKF_Msk (0x1U << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 2569 #define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
Kojto 122:f9eeca106725 2570 #define I2C_ISR_STOPF_Pos (5U)
Kojto 122:f9eeca106725 2571 #define I2C_ISR_STOPF_Msk (0x1U << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 2572 #define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
Kojto 122:f9eeca106725 2573 #define I2C_ISR_TC_Pos (6U)
Kojto 122:f9eeca106725 2574 #define I2C_ISR_TC_Msk (0x1U << I2C_ISR_TC_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 2575 #define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
Kojto 122:f9eeca106725 2576 #define I2C_ISR_TCR_Pos (7U)
Kojto 122:f9eeca106725 2577 #define I2C_ISR_TCR_Msk (0x1U << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 2578 #define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
Kojto 122:f9eeca106725 2579 #define I2C_ISR_BERR_Pos (8U)
Kojto 122:f9eeca106725 2580 #define I2C_ISR_BERR_Msk (0x1U << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 2581 #define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
Kojto 122:f9eeca106725 2582 #define I2C_ISR_ARLO_Pos (9U)
Kojto 122:f9eeca106725 2583 #define I2C_ISR_ARLO_Msk (0x1U << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 2584 #define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
Kojto 122:f9eeca106725 2585 #define I2C_ISR_OVR_Pos (10U)
Kojto 122:f9eeca106725 2586 #define I2C_ISR_OVR_Msk (0x1U << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 2587 #define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
Kojto 122:f9eeca106725 2588 #define I2C_ISR_PECERR_Pos (11U)
Kojto 122:f9eeca106725 2589 #define I2C_ISR_PECERR_Msk (0x1U << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 2590 #define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
Kojto 122:f9eeca106725 2591 #define I2C_ISR_TIMEOUT_Pos (12U)
Kojto 122:f9eeca106725 2592 #define I2C_ISR_TIMEOUT_Msk (0x1U << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 2593 #define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
Kojto 122:f9eeca106725 2594 #define I2C_ISR_ALERT_Pos (13U)
Kojto 122:f9eeca106725 2595 #define I2C_ISR_ALERT_Msk (0x1U << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 2596 #define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
Kojto 122:f9eeca106725 2597 #define I2C_ISR_BUSY_Pos (15U)
Kojto 122:f9eeca106725 2598 #define I2C_ISR_BUSY_Msk (0x1U << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 2599 #define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
Kojto 122:f9eeca106725 2600 #define I2C_ISR_DIR_Pos (16U)
Kojto 122:f9eeca106725 2601 #define I2C_ISR_DIR_Msk (0x1U << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 2602 #define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
Kojto 122:f9eeca106725 2603 #define I2C_ISR_ADDCODE_Pos (17U)
Kojto 122:f9eeca106725 2604 #define I2C_ISR_ADDCODE_Msk (0x7FU << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
Kojto 122:f9eeca106725 2605 #define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
Kojto 90:cb3d968589d8 2606
Kojto 90:cb3d968589d8 2607 /****************** Bit definition for I2C_ICR register ********************/
Kojto 122:f9eeca106725 2608 #define I2C_ICR_ADDRCF_Pos (3U)
Kojto 122:f9eeca106725 2609 #define I2C_ICR_ADDRCF_Msk (0x1U << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 2610 #define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
Kojto 122:f9eeca106725 2611 #define I2C_ICR_NACKCF_Pos (4U)
Kojto 122:f9eeca106725 2612 #define I2C_ICR_NACKCF_Msk (0x1U << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 2613 #define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
Kojto 122:f9eeca106725 2614 #define I2C_ICR_STOPCF_Pos (5U)
Kojto 122:f9eeca106725 2615 #define I2C_ICR_STOPCF_Msk (0x1U << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 2616 #define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
Kojto 122:f9eeca106725 2617 #define I2C_ICR_BERRCF_Pos (8U)
Kojto 122:f9eeca106725 2618 #define I2C_ICR_BERRCF_Msk (0x1U << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 2619 #define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
Kojto 122:f9eeca106725 2620 #define I2C_ICR_ARLOCF_Pos (9U)
Kojto 122:f9eeca106725 2621 #define I2C_ICR_ARLOCF_Msk (0x1U << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 2622 #define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
Kojto 122:f9eeca106725 2623 #define I2C_ICR_OVRCF_Pos (10U)
Kojto 122:f9eeca106725 2624 #define I2C_ICR_OVRCF_Msk (0x1U << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 2625 #define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
Kojto 122:f9eeca106725 2626 #define I2C_ICR_PECCF_Pos (11U)
Kojto 122:f9eeca106725 2627 #define I2C_ICR_PECCF_Msk (0x1U << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 2628 #define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
Kojto 122:f9eeca106725 2629 #define I2C_ICR_TIMOUTCF_Pos (12U)
Kojto 122:f9eeca106725 2630 #define I2C_ICR_TIMOUTCF_Msk (0x1U << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 2631 #define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
Kojto 122:f9eeca106725 2632 #define I2C_ICR_ALERTCF_Pos (13U)
Kojto 122:f9eeca106725 2633 #define I2C_ICR_ALERTCF_Msk (0x1U << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 2634 #define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
Kojto 90:cb3d968589d8 2635
Kojto 90:cb3d968589d8 2636 /****************** Bit definition for I2C_PECR register *******************/
Kojto 122:f9eeca106725 2637 #define I2C_PECR_PEC_Pos (0U)
Kojto 122:f9eeca106725 2638 #define I2C_PECR_PEC_Msk (0xFFU << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 2639 #define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
Kojto 90:cb3d968589d8 2640
Kojto 90:cb3d968589d8 2641 /****************** Bit definition for I2C_RXDR register *********************/
Kojto 122:f9eeca106725 2642 #define I2C_RXDR_RXDATA_Pos (0U)
Kojto 122:f9eeca106725 2643 #define I2C_RXDR_RXDATA_Msk (0xFFU << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 2644 #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
Kojto 90:cb3d968589d8 2645
Kojto 90:cb3d968589d8 2646 /****************** Bit definition for I2C_TXDR register *******************/
Kojto 122:f9eeca106725 2647 #define I2C_TXDR_TXDATA_Pos (0U)
Kojto 122:f9eeca106725 2648 #define I2C_TXDR_TXDATA_Msk (0xFFU << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 2649 #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
Kojto 90:cb3d968589d8 2650
Kojto 90:cb3d968589d8 2651 /*****************************************************************************/
Kojto 90:cb3d968589d8 2652 /* */
Kojto 90:cb3d968589d8 2653 /* Independent WATCHDOG (IWDG) */
Kojto 90:cb3d968589d8 2654 /* */
Kojto 90:cb3d968589d8 2655 /*****************************************************************************/
Kojto 90:cb3d968589d8 2656 /******************* Bit definition for IWDG_KR register *******************/
Kojto 122:f9eeca106725 2657 #define IWDG_KR_KEY_Pos (0U)
Kojto 122:f9eeca106725 2658 #define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 2659 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */
Kojto 90:cb3d968589d8 2660
Kojto 90:cb3d968589d8 2661 /******************* Bit definition for IWDG_PR register *******************/
Kojto 122:f9eeca106725 2662 #define IWDG_PR_PR_Pos (0U)
Kojto 122:f9eeca106725 2663 #define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
Kojto 122:f9eeca106725 2664 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */
Kojto 122:f9eeca106725 2665 #define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x01 */
Kojto 122:f9eeca106725 2666 #define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x02 */
Kojto 122:f9eeca106725 2667 #define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x04 */
Kojto 90:cb3d968589d8 2668
Kojto 90:cb3d968589d8 2669 /******************* Bit definition for IWDG_RLR register ******************/
Kojto 122:f9eeca106725 2670 #define IWDG_RLR_RL_Pos (0U)
Kojto 122:f9eeca106725 2671 #define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
Kojto 122:f9eeca106725 2672 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */
Kojto 90:cb3d968589d8 2673
Kojto 90:cb3d968589d8 2674 /******************* Bit definition for IWDG_SR register *******************/
Kojto 122:f9eeca106725 2675 #define IWDG_SR_PVU_Pos (0U)
Kojto 122:f9eeca106725 2676 #define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 2677 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
Kojto 122:f9eeca106725 2678 #define IWDG_SR_RVU_Pos (1U)
Kojto 122:f9eeca106725 2679 #define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 2680 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
Kojto 122:f9eeca106725 2681 #define IWDG_SR_WVU_Pos (2U)
Kojto 122:f9eeca106725 2682 #define IWDG_SR_WVU_Msk (0x1U << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 2683 #define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
Kojto 90:cb3d968589d8 2684
Kojto 90:cb3d968589d8 2685 /******************* Bit definition for IWDG_KR register *******************/
Kojto 122:f9eeca106725 2686 #define IWDG_WINR_WIN_Pos (0U)
Kojto 122:f9eeca106725 2687 #define IWDG_WINR_WIN_Msk (0xFFFU << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
Kojto 122:f9eeca106725 2688 #define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
Kojto 90:cb3d968589d8 2689
Kojto 90:cb3d968589d8 2690 /*****************************************************************************/
Kojto 90:cb3d968589d8 2691 /* */
Kojto 90:cb3d968589d8 2692 /* Power Control (PWR) */
Kojto 90:cb3d968589d8 2693 /* */
Kojto 90:cb3d968589d8 2694 /*****************************************************************************/
Kojto 90:cb3d968589d8 2695
Kojto 122:f9eeca106725 2696 /* Note: No specific macro feature on this device */
Kojto 122:f9eeca106725 2697
Kojto 122:f9eeca106725 2698
Kojto 90:cb3d968589d8 2699 /******************** Bit definition for PWR_CR register *******************/
Kojto 122:f9eeca106725 2700 #define PWR_CR_LPDS_Pos (0U)
Kojto 122:f9eeca106725 2701 #define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 2702 #define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-power Deepsleep */
Kojto 122:f9eeca106725 2703 #define PWR_CR_PDDS_Pos (1U)
Kojto 122:f9eeca106725 2704 #define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 2705 #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
Kojto 122:f9eeca106725 2706 #define PWR_CR_CWUF_Pos (2U)
Kojto 122:f9eeca106725 2707 #define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 2708 #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
Kojto 122:f9eeca106725 2709 #define PWR_CR_CSBF_Pos (3U)
Kojto 122:f9eeca106725 2710 #define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 2711 #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
Kojto 122:f9eeca106725 2712 #define PWR_CR_DBP_Pos (8U)
Kojto 122:f9eeca106725 2713 #define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 2714 #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
Kojto 90:cb3d968589d8 2715
Kojto 90:cb3d968589d8 2716 /******************* Bit definition for PWR_CSR register *******************/
Kojto 122:f9eeca106725 2717 #define PWR_CSR_WUF_Pos (0U)
Kojto 122:f9eeca106725 2718 #define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 2719 #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
Kojto 122:f9eeca106725 2720 #define PWR_CSR_SBF_Pos (1U)
Kojto 122:f9eeca106725 2721 #define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 2722 #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
Kojto 122:f9eeca106725 2723
Kojto 122:f9eeca106725 2724 #define PWR_CSR_EWUP1_Pos (8U)
Kojto 122:f9eeca106725 2725 #define PWR_CSR_EWUP1_Msk (0x1U << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 2726 #define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */
Kojto 122:f9eeca106725 2727 #define PWR_CSR_EWUP2_Pos (9U)
Kojto 122:f9eeca106725 2728 #define PWR_CSR_EWUP2_Msk (0x1U << PWR_CSR_EWUP2_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 2729 #define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */
Kojto 90:cb3d968589d8 2730
Kojto 90:cb3d968589d8 2731 /*****************************************************************************/
Kojto 90:cb3d968589d8 2732 /* */
Kojto 90:cb3d968589d8 2733 /* Reset and Clock Control */
Kojto 90:cb3d968589d8 2734 /* */
Kojto 90:cb3d968589d8 2735 /*****************************************************************************/
Kojto 122:f9eeca106725 2736 /*
Kojto 122:f9eeca106725 2737 * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
Kojto 122:f9eeca106725 2738 */
Kojto 90:cb3d968589d8 2739
Kojto 90:cb3d968589d8 2740 /******************** Bit definition for RCC_CR register *******************/
Kojto 122:f9eeca106725 2741 #define RCC_CR_HSION_Pos (0U)
Kojto 122:f9eeca106725 2742 #define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 2743 #define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */
Kojto 122:f9eeca106725 2744 #define RCC_CR_HSIRDY_Pos (1U)
Kojto 122:f9eeca106725 2745 #define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 2746 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
Kojto 122:f9eeca106725 2747
Kojto 122:f9eeca106725 2748 #define RCC_CR_HSITRIM_Pos (3U)
Kojto 122:f9eeca106725 2749 #define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
Kojto 122:f9eeca106725 2750 #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk /*!< Internal High Speed clock trimming */
Kojto 122:f9eeca106725 2751 #define RCC_CR_HSITRIM_0 (0x01U << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 2752 #define RCC_CR_HSITRIM_1 (0x02U << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 2753 #define RCC_CR_HSITRIM_2 (0x04U << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 2754 #define RCC_CR_HSITRIM_3 (0x08U << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 2755 #define RCC_CR_HSITRIM_4 (0x10U << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 2756
Kojto 122:f9eeca106725 2757 #define RCC_CR_HSICAL_Pos (8U)
Kojto 122:f9eeca106725 2758 #define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
Kojto 122:f9eeca106725 2759 #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk /*!< Internal High Speed clock Calibration */
Kojto 122:f9eeca106725 2760 #define RCC_CR_HSICAL_0 (0x01U << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 2761 #define RCC_CR_HSICAL_1 (0x02U << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 2762 #define RCC_CR_HSICAL_2 (0x04U << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 2763 #define RCC_CR_HSICAL_3 (0x08U << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 2764 #define RCC_CR_HSICAL_4 (0x10U << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 2765 #define RCC_CR_HSICAL_5 (0x20U << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 2766 #define RCC_CR_HSICAL_6 (0x40U << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 2767 #define RCC_CR_HSICAL_7 (0x80U << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 2768
Kojto 122:f9eeca106725 2769 #define RCC_CR_HSEON_Pos (16U)
Kojto 122:f9eeca106725 2770 #define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 2771 #define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */
Kojto 122:f9eeca106725 2772 #define RCC_CR_HSERDY_Pos (17U)
Kojto 122:f9eeca106725 2773 #define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 2774 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */
Kojto 122:f9eeca106725 2775 #define RCC_CR_HSEBYP_Pos (18U)
Kojto 122:f9eeca106725 2776 #define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 2777 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
Kojto 122:f9eeca106725 2778 #define RCC_CR_CSSON_Pos (19U)
Kojto 122:f9eeca106725 2779 #define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 2780 #define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< Clock Security System enable */
Kojto 122:f9eeca106725 2781 #define RCC_CR_PLLON_Pos (24U)
Kojto 122:f9eeca106725 2782 #define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 2783 #define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */
Kojto 122:f9eeca106725 2784 #define RCC_CR_PLLRDY_Pos (25U)
Kojto 122:f9eeca106725 2785 #define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 2786 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */
Kojto 90:cb3d968589d8 2787
Kojto 90:cb3d968589d8 2788 /******************** Bit definition for RCC_CFGR register *****************/
Kojto 90:cb3d968589d8 2789 /*!< SW configuration */
Kojto 122:f9eeca106725 2790 #define RCC_CFGR_SW_Pos (0U)
Kojto 122:f9eeca106725 2791 #define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
Kojto 122:f9eeca106725 2792 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
Kojto 122:f9eeca106725 2793 #define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 2794 #define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 2795
Kojto 122:f9eeca106725 2796 #define RCC_CFGR_SW_HSI (0x00000000U) /*!< HSI selected as system clock */
Kojto 122:f9eeca106725 2797 #define RCC_CFGR_SW_HSE (0x00000001U) /*!< HSE selected as system clock */
Kojto 122:f9eeca106725 2798 #define RCC_CFGR_SW_PLL (0x00000002U) /*!< PLL selected as system clock */
Kojto 90:cb3d968589d8 2799
Kojto 90:cb3d968589d8 2800 /*!< SWS configuration */
Kojto 122:f9eeca106725 2801 #define RCC_CFGR_SWS_Pos (2U)
Kojto 122:f9eeca106725 2802 #define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
Kojto 122:f9eeca106725 2803 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
Kojto 122:f9eeca106725 2804 #define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 2805 #define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 2806
Kojto 122:f9eeca106725 2807 #define RCC_CFGR_SWS_HSI (0x00000000U) /*!< HSI oscillator used as system clock */
Kojto 122:f9eeca106725 2808 #define RCC_CFGR_SWS_HSE (0x00000004U) /*!< HSE oscillator used as system clock */
Kojto 122:f9eeca106725 2809 #define RCC_CFGR_SWS_PLL (0x00000008U) /*!< PLL used as system clock */
Kojto 90:cb3d968589d8 2810
Kojto 90:cb3d968589d8 2811 /*!< HPRE configuration */
Kojto 122:f9eeca106725 2812 #define RCC_CFGR_HPRE_Pos (4U)
Kojto 122:f9eeca106725 2813 #define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
Kojto 122:f9eeca106725 2814 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
Kojto 122:f9eeca106725 2815 #define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 2816 #define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 2817 #define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 2818 #define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 2819
Kojto 122:f9eeca106725 2820 #define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */
Kojto 122:f9eeca106725 2821 #define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */
Kojto 122:f9eeca106725 2822 #define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */
Kojto 122:f9eeca106725 2823 #define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */
Kojto 122:f9eeca106725 2824 #define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */
Kojto 122:f9eeca106725 2825 #define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */
Kojto 122:f9eeca106725 2826 #define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */
Kojto 122:f9eeca106725 2827 #define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */
Kojto 122:f9eeca106725 2828 #define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */
Kojto 90:cb3d968589d8 2829
Kojto 90:cb3d968589d8 2830 /*!< PPRE configuration */
Kojto 122:f9eeca106725 2831 #define RCC_CFGR_PPRE_Pos (8U)
Kojto 122:f9eeca106725 2832 #define RCC_CFGR_PPRE_Msk (0x7U << RCC_CFGR_PPRE_Pos) /*!< 0x00000700 */
Kojto 122:f9eeca106725 2833 #define RCC_CFGR_PPRE RCC_CFGR_PPRE_Msk /*!< PRE[2:0] bits (APB prescaler) */
Kojto 122:f9eeca106725 2834 #define RCC_CFGR_PPRE_0 (0x1U << RCC_CFGR_PPRE_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 2835 #define RCC_CFGR_PPRE_1 (0x2U << RCC_CFGR_PPRE_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 2836 #define RCC_CFGR_PPRE_2 (0x4U << RCC_CFGR_PPRE_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 2837
Kojto 122:f9eeca106725 2838 #define RCC_CFGR_PPRE_DIV1 (0x00000000U) /*!< HCLK not divided */
Kojto 122:f9eeca106725 2839 #define RCC_CFGR_PPRE_DIV2_Pos (10U)
Kojto 122:f9eeca106725 2840 #define RCC_CFGR_PPRE_DIV2_Msk (0x1U << RCC_CFGR_PPRE_DIV2_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 2841 #define RCC_CFGR_PPRE_DIV2 RCC_CFGR_PPRE_DIV2_Msk /*!< HCLK divided by 2 */
Kojto 122:f9eeca106725 2842 #define RCC_CFGR_PPRE_DIV4_Pos (8U)
Kojto 122:f9eeca106725 2843 #define RCC_CFGR_PPRE_DIV4_Msk (0x5U << RCC_CFGR_PPRE_DIV4_Pos) /*!< 0x00000500 */
Kojto 122:f9eeca106725 2844 #define RCC_CFGR_PPRE_DIV4 RCC_CFGR_PPRE_DIV4_Msk /*!< HCLK divided by 4 */
Kojto 122:f9eeca106725 2845 #define RCC_CFGR_PPRE_DIV8_Pos (9U)
Kojto 122:f9eeca106725 2846 #define RCC_CFGR_PPRE_DIV8_Msk (0x3U << RCC_CFGR_PPRE_DIV8_Pos) /*!< 0x00000600 */
Kojto 122:f9eeca106725 2847 #define RCC_CFGR_PPRE_DIV8 RCC_CFGR_PPRE_DIV8_Msk /*!< HCLK divided by 8 */
Kojto 122:f9eeca106725 2848 #define RCC_CFGR_PPRE_DIV16_Pos (8U)
Kojto 122:f9eeca106725 2849 #define RCC_CFGR_PPRE_DIV16_Msk (0x7U << RCC_CFGR_PPRE_DIV16_Pos) /*!< 0x00000700 */
Kojto 122:f9eeca106725 2850 #define RCC_CFGR_PPRE_DIV16 RCC_CFGR_PPRE_DIV16_Msk /*!< HCLK divided by 16 */
Kojto 90:cb3d968589d8 2851
Kojto 90:cb3d968589d8 2852 /*!< ADCPPRE configuration */
Kojto 122:f9eeca106725 2853 #define RCC_CFGR_ADCPRE_Pos (14U)
Kojto 122:f9eeca106725 2854 #define RCC_CFGR_ADCPRE_Msk (0x1U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 2855 #define RCC_CFGR_ADCPRE RCC_CFGR_ADCPRE_Msk /*!< ADCPRE bit (ADC prescaler) */
Kojto 122:f9eeca106725 2856
Kojto 122:f9eeca106725 2857 #define RCC_CFGR_ADCPRE_DIV2 (0x00000000U) /*!< PCLK divided by 2 */
Kojto 122:f9eeca106725 2858 #define RCC_CFGR_ADCPRE_DIV4 (0x00004000U) /*!< PCLK divided by 4 */
Kojto 122:f9eeca106725 2859
Kojto 122:f9eeca106725 2860 #define RCC_CFGR_PLLSRC_Pos (16U)
Kojto 122:f9eeca106725 2861 #define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 2862 #define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */
Kojto 122:f9eeca106725 2863 #define RCC_CFGR_PLLSRC_HSI_DIV2 (0x00000000U) /*!< HSI clock divided by 2 selected as PLL entry clock source */
Kojto 122:f9eeca106725 2864 #define RCC_CFGR_PLLSRC_HSE_PREDIV (0x00010000U) /*!< HSE/PREDIV clock selected as PLL entry clock source */
Kojto 122:f9eeca106725 2865
Kojto 122:f9eeca106725 2866 #define RCC_CFGR_PLLXTPRE_Pos (17U)
Kojto 122:f9eeca106725 2867 #define RCC_CFGR_PLLXTPRE_Msk (0x1U << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 2868 #define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /*!< HSE divider for PLL entry */
Kojto 122:f9eeca106725 2869 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 (0x00000000U) /*!< HSE/PREDIV clock not divided for PLL entry */
Kojto 122:f9eeca106725 2870 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2 (0x00020000U) /*!< HSE/PREDIV clock divided by 2 for PLL entry */
Kojto 90:cb3d968589d8 2871
Kojto 90:cb3d968589d8 2872 /*!< PLLMUL configuration */
Kojto 122:f9eeca106725 2873 #define RCC_CFGR_PLLMUL_Pos (18U)
Kojto 122:f9eeca106725 2874 #define RCC_CFGR_PLLMUL_Msk (0xFU << RCC_CFGR_PLLMUL_Pos) /*!< 0x003C0000 */
Kojto 122:f9eeca106725 2875 #define RCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
Kojto 122:f9eeca106725 2876 #define RCC_CFGR_PLLMUL_0 (0x1U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 2877 #define RCC_CFGR_PLLMUL_1 (0x2U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 2878 #define RCC_CFGR_PLLMUL_2 (0x4U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 2879 #define RCC_CFGR_PLLMUL_3 (0x8U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 2880
Kojto 122:f9eeca106725 2881 #define RCC_CFGR_PLLMUL2 (0x00000000U) /*!< PLL input clock*2 */
Kojto 122:f9eeca106725 2882 #define RCC_CFGR_PLLMUL3 (0x00040000U) /*!< PLL input clock*3 */
Kojto 122:f9eeca106725 2883 #define RCC_CFGR_PLLMUL4 (0x00080000U) /*!< PLL input clock*4 */
Kojto 122:f9eeca106725 2884 #define RCC_CFGR_PLLMUL5 (0x000C0000U) /*!< PLL input clock*5 */
Kojto 122:f9eeca106725 2885 #define RCC_CFGR_PLLMUL6 (0x00100000U) /*!< PLL input clock*6 */
Kojto 122:f9eeca106725 2886 #define RCC_CFGR_PLLMUL7 (0x00140000U) /*!< PLL input clock*7 */
Kojto 122:f9eeca106725 2887 #define RCC_CFGR_PLLMUL8 (0x00180000U) /*!< PLL input clock*8 */
Kojto 122:f9eeca106725 2888 #define RCC_CFGR_PLLMUL9 (0x001C0000U) /*!< PLL input clock*9 */
Kojto 122:f9eeca106725 2889 #define RCC_CFGR_PLLMUL10 (0x00200000U) /*!< PLL input clock10 */
Kojto 122:f9eeca106725 2890 #define RCC_CFGR_PLLMUL11 (0x00240000U) /*!< PLL input clock*11 */
Kojto 122:f9eeca106725 2891 #define RCC_CFGR_PLLMUL12 (0x00280000U) /*!< PLL input clock*12 */
Kojto 122:f9eeca106725 2892 #define RCC_CFGR_PLLMUL13 (0x002C0000U) /*!< PLL input clock*13 */
Kojto 122:f9eeca106725 2893 #define RCC_CFGR_PLLMUL14 (0x00300000U) /*!< PLL input clock*14 */
Kojto 122:f9eeca106725 2894 #define RCC_CFGR_PLLMUL15 (0x00340000U) /*!< PLL input clock*15 */
Kojto 122:f9eeca106725 2895 #define RCC_CFGR_PLLMUL16 (0x00380000U) /*!< PLL input clock*16 */
Kojto 90:cb3d968589d8 2896
Kojto 90:cb3d968589d8 2897 /*!< MCO configuration */
Kojto 122:f9eeca106725 2898 #define RCC_CFGR_MCO_Pos (24U)
Kojto 122:f9eeca106725 2899 #define RCC_CFGR_MCO_Msk (0xFU << RCC_CFGR_MCO_Pos) /*!< 0x0F000000 */
Kojto 122:f9eeca106725 2900 #define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /*!< MCO[3:0] bits (Microcontroller Clock Output) */
Kojto 122:f9eeca106725 2901 #define RCC_CFGR_MCO_0 (0x1U << RCC_CFGR_MCO_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 2902 #define RCC_CFGR_MCO_1 (0x2U << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 2903 #define RCC_CFGR_MCO_2 (0x4U << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 2904
Kojto 122:f9eeca106725 2905 #define RCC_CFGR_MCO_NOCLOCK (0x00000000U) /*!< No clock */
Kojto 122:f9eeca106725 2906 #define RCC_CFGR_MCO_HSI14 (0x01000000U) /*!< HSI14 clock selected as MCO source */
Kojto 122:f9eeca106725 2907 #define RCC_CFGR_MCO_LSI (0x02000000U) /*!< LSI clock selected as MCO source */
Kojto 122:f9eeca106725 2908 #define RCC_CFGR_MCO_LSE (0x03000000U) /*!< LSE clock selected as MCO source */
Kojto 122:f9eeca106725 2909 #define RCC_CFGR_MCO_SYSCLK (0x04000000U) /*!< System clock selected as MCO source */
Kojto 122:f9eeca106725 2910 #define RCC_CFGR_MCO_HSI (0x05000000U) /*!< HSI clock selected as MCO source */
Kojto 122:f9eeca106725 2911 #define RCC_CFGR_MCO_HSE (0x06000000U) /*!< HSE clock selected as MCO source */
Kojto 122:f9eeca106725 2912 #define RCC_CFGR_MCO_PLL (0x07000000U) /*!< PLL clock divided by 2 selected as MCO source */
Kojto 122:f9eeca106725 2913
Kojto 122:f9eeca106725 2914 /* Reference defines */
Kojto 122:f9eeca106725 2915 #define RCC_CFGR_MCOSEL RCC_CFGR_MCO
Kojto 122:f9eeca106725 2916 #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0
Kojto 122:f9eeca106725 2917 #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1
Kojto 122:f9eeca106725 2918 #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2
Kojto 122:f9eeca106725 2919 #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK
Kojto 122:f9eeca106725 2920 #define RCC_CFGR_MCOSEL_HSI14 RCC_CFGR_MCO_HSI14
Kojto 122:f9eeca106725 2921 #define RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCO_LSI
Kojto 122:f9eeca106725 2922 #define RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCO_LSE
Kojto 122:f9eeca106725 2923 #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK
Kojto 122:f9eeca106725 2924 #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI
Kojto 122:f9eeca106725 2925 #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE
Kojto 122:f9eeca106725 2926 #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLL
Kojto 90:cb3d968589d8 2927
Kojto 90:cb3d968589d8 2928 /*!<****************** Bit definition for RCC_CIR register *****************/
Kojto 122:f9eeca106725 2929 #define RCC_CIR_LSIRDYF_Pos (0U)
Kojto 122:f9eeca106725 2930 #define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 2931 #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */
Kojto 122:f9eeca106725 2932 #define RCC_CIR_LSERDYF_Pos (1U)
Kojto 122:f9eeca106725 2933 #define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 2934 #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */
Kojto 122:f9eeca106725 2935 #define RCC_CIR_HSIRDYF_Pos (2U)
Kojto 122:f9eeca106725 2936 #define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 2937 #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */
Kojto 122:f9eeca106725 2938 #define RCC_CIR_HSERDYF_Pos (3U)
Kojto 122:f9eeca106725 2939 #define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 2940 #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */
Kojto 122:f9eeca106725 2941 #define RCC_CIR_PLLRDYF_Pos (4U)
Kojto 122:f9eeca106725 2942 #define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 2943 #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */
Kojto 122:f9eeca106725 2944 #define RCC_CIR_HSI14RDYF_Pos (5U)
Kojto 122:f9eeca106725 2945 #define RCC_CIR_HSI14RDYF_Msk (0x1U << RCC_CIR_HSI14RDYF_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 2946 #define RCC_CIR_HSI14RDYF RCC_CIR_HSI14RDYF_Msk /*!< HSI14 Ready Interrupt flag */
Kojto 122:f9eeca106725 2947 #define RCC_CIR_CSSF_Pos (7U)
Kojto 122:f9eeca106725 2948 #define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 2949 #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */
Kojto 122:f9eeca106725 2950 #define RCC_CIR_LSIRDYIE_Pos (8U)
Kojto 122:f9eeca106725 2951 #define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 2952 #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */
Kojto 122:f9eeca106725 2953 #define RCC_CIR_LSERDYIE_Pos (9U)
Kojto 122:f9eeca106725 2954 #define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 2955 #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */
Kojto 122:f9eeca106725 2956 #define RCC_CIR_HSIRDYIE_Pos (10U)
Kojto 122:f9eeca106725 2957 #define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 2958 #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */
Kojto 122:f9eeca106725 2959 #define RCC_CIR_HSERDYIE_Pos (11U)
Kojto 122:f9eeca106725 2960 #define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 2961 #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */
Kojto 122:f9eeca106725 2962 #define RCC_CIR_PLLRDYIE_Pos (12U)
Kojto 122:f9eeca106725 2963 #define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 2964 #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */
Kojto 122:f9eeca106725 2965 #define RCC_CIR_HSI14RDYIE_Pos (13U)
Kojto 122:f9eeca106725 2966 #define RCC_CIR_HSI14RDYIE_Msk (0x1U << RCC_CIR_HSI14RDYIE_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 2967 #define RCC_CIR_HSI14RDYIE RCC_CIR_HSI14RDYIE_Msk /*!< HSI14 Ready Interrupt Enable */
Kojto 122:f9eeca106725 2968 #define RCC_CIR_LSIRDYC_Pos (16U)
Kojto 122:f9eeca106725 2969 #define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 2970 #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */
Kojto 122:f9eeca106725 2971 #define RCC_CIR_LSERDYC_Pos (17U)
Kojto 122:f9eeca106725 2972 #define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 2973 #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */
Kojto 122:f9eeca106725 2974 #define RCC_CIR_HSIRDYC_Pos (18U)
Kojto 122:f9eeca106725 2975 #define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 2976 #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */
Kojto 122:f9eeca106725 2977 #define RCC_CIR_HSERDYC_Pos (19U)
Kojto 122:f9eeca106725 2978 #define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 2979 #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */
Kojto 122:f9eeca106725 2980 #define RCC_CIR_PLLRDYC_Pos (20U)
Kojto 122:f9eeca106725 2981 #define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 2982 #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */
Kojto 122:f9eeca106725 2983 #define RCC_CIR_HSI14RDYC_Pos (21U)
Kojto 122:f9eeca106725 2984 #define RCC_CIR_HSI14RDYC_Msk (0x1U << RCC_CIR_HSI14RDYC_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 2985 #define RCC_CIR_HSI14RDYC RCC_CIR_HSI14RDYC_Msk /*!< HSI14 Ready Interrupt Clear */
Kojto 122:f9eeca106725 2986 #define RCC_CIR_CSSC_Pos (23U)
Kojto 122:f9eeca106725 2987 #define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 2988 #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */
Kojto 90:cb3d968589d8 2989
Kojto 90:cb3d968589d8 2990 /***************** Bit definition for RCC_APB2RSTR register ****************/
Kojto 122:f9eeca106725 2991 #define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
Kojto 122:f9eeca106725 2992 #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 2993 #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG clock reset */
Kojto 122:f9eeca106725 2994 #define RCC_APB2RSTR_ADCRST_Pos (9U)
Kojto 122:f9eeca106725 2995 #define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 2996 #define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC clock reset */
Kojto 122:f9eeca106725 2997 #define RCC_APB2RSTR_TIM1RST_Pos (11U)
Kojto 122:f9eeca106725 2998 #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 2999 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 clock reset */
Kojto 122:f9eeca106725 3000 #define RCC_APB2RSTR_SPI1RST_Pos (12U)
Kojto 122:f9eeca106725 3001 #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 3002 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 clock reset */
Kojto 122:f9eeca106725 3003 #define RCC_APB2RSTR_USART1RST_Pos (14U)
Kojto 122:f9eeca106725 3004 #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 3005 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 clock reset */
Kojto 122:f9eeca106725 3006 #define RCC_APB2RSTR_TIM15RST_Pos (16U)
Kojto 122:f9eeca106725 3007 #define RCC_APB2RSTR_TIM15RST_Msk (0x1U << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 3008 #define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /*!< TIM15 clock reset */
Kojto 122:f9eeca106725 3009 #define RCC_APB2RSTR_TIM16RST_Pos (17U)
Kojto 122:f9eeca106725 3010 #define RCC_APB2RSTR_TIM16RST_Msk (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 3011 #define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 clock reset */
Kojto 122:f9eeca106725 3012 #define RCC_APB2RSTR_TIM17RST_Pos (18U)
Kojto 122:f9eeca106725 3013 #define RCC_APB2RSTR_TIM17RST_Msk (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 3014 #define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 clock reset */
Kojto 122:f9eeca106725 3015 #define RCC_APB2RSTR_DBGMCURST_Pos (22U)
Kojto 122:f9eeca106725 3016 #define RCC_APB2RSTR_DBGMCURST_Msk (0x1U << RCC_APB2RSTR_DBGMCURST_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 3017 #define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGMCURST_Msk /*!< DBGMCU clock reset */
Kojto 90:cb3d968589d8 3018
Kojto 90:cb3d968589d8 3019 /*!< Old ADC1 clock reset bit definition maintained for legacy purpose */
Kojto 90:cb3d968589d8 3020 #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST
Kojto 90:cb3d968589d8 3021
Kojto 90:cb3d968589d8 3022 /***************** Bit definition for RCC_APB1RSTR register ****************/
Kojto 122:f9eeca106725 3023 #define RCC_APB1RSTR_TIM3RST_Pos (1U)
Kojto 122:f9eeca106725 3024 #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 3025 #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 clock reset */
Kojto 122:f9eeca106725 3026 #define RCC_APB1RSTR_TIM6RST_Pos (4U)
Kojto 122:f9eeca106725 3027 #define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 3028 #define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 clock reset */
Kojto 122:f9eeca106725 3029 #define RCC_APB1RSTR_TIM14RST_Pos (8U)
Kojto 122:f9eeca106725 3030 #define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 3031 #define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk /*!< Timer 14 clock reset */
Kojto 122:f9eeca106725 3032 #define RCC_APB1RSTR_WWDGRST_Pos (11U)
Kojto 122:f9eeca106725 3033 #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 3034 #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog clock reset */
Kojto 122:f9eeca106725 3035 #define RCC_APB1RSTR_SPI2RST_Pos (14U)
Kojto 122:f9eeca106725 3036 #define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 3037 #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI2 clock reset */
Kojto 122:f9eeca106725 3038 #define RCC_APB1RSTR_USART2RST_Pos (17U)
Kojto 122:f9eeca106725 3039 #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 3040 #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 clock reset */
Kojto 122:f9eeca106725 3041 #define RCC_APB1RSTR_I2C1RST_Pos (21U)
Kojto 122:f9eeca106725 3042 #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 3043 #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 clock reset */
Kojto 122:f9eeca106725 3044 #define RCC_APB1RSTR_I2C2RST_Pos (22U)
Kojto 122:f9eeca106725 3045 #define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 3046 #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 clock reset */
Kojto 122:f9eeca106725 3047 #define RCC_APB1RSTR_PWRRST_Pos (28U)
Kojto 122:f9eeca106725 3048 #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 3049 #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR clock reset */
Kojto 90:cb3d968589d8 3050
Kojto 90:cb3d968589d8 3051 /****************** Bit definition for RCC_AHBENR register *****************/
Kojto 122:f9eeca106725 3052 #define RCC_AHBENR_DMAEN_Pos (0U)
Kojto 122:f9eeca106725 3053 #define RCC_AHBENR_DMAEN_Msk (0x1U << RCC_AHBENR_DMAEN_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 3054 #define RCC_AHBENR_DMAEN RCC_AHBENR_DMAEN_Msk /*!< DMA1 clock enable */
Kojto 122:f9eeca106725 3055 #define RCC_AHBENR_SRAMEN_Pos (2U)
Kojto 122:f9eeca106725 3056 #define RCC_AHBENR_SRAMEN_Msk (0x1U << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 3057 #define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /*!< SRAM interface clock enable */
Kojto 122:f9eeca106725 3058 #define RCC_AHBENR_FLITFEN_Pos (4U)
Kojto 122:f9eeca106725 3059 #define RCC_AHBENR_FLITFEN_Msk (0x1U << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 3060 #define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable */
Kojto 122:f9eeca106725 3061 #define RCC_AHBENR_CRCEN_Pos (6U)
Kojto 122:f9eeca106725 3062 #define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 3063 #define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */
Kojto 122:f9eeca106725 3064 #define RCC_AHBENR_GPIOAEN_Pos (17U)
Kojto 122:f9eeca106725 3065 #define RCC_AHBENR_GPIOAEN_Msk (0x1U << RCC_AHBENR_GPIOAEN_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 3066 #define RCC_AHBENR_GPIOAEN RCC_AHBENR_GPIOAEN_Msk /*!< GPIOA clock enable */
Kojto 122:f9eeca106725 3067 #define RCC_AHBENR_GPIOBEN_Pos (18U)
Kojto 122:f9eeca106725 3068 #define RCC_AHBENR_GPIOBEN_Msk (0x1U << RCC_AHBENR_GPIOBEN_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 3069 #define RCC_AHBENR_GPIOBEN RCC_AHBENR_GPIOBEN_Msk /*!< GPIOB clock enable */
Kojto 122:f9eeca106725 3070 #define RCC_AHBENR_GPIOCEN_Pos (19U)
Kojto 122:f9eeca106725 3071 #define RCC_AHBENR_GPIOCEN_Msk (0x1U << RCC_AHBENR_GPIOCEN_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 3072 #define RCC_AHBENR_GPIOCEN RCC_AHBENR_GPIOCEN_Msk /*!< GPIOC clock enable */
Kojto 122:f9eeca106725 3073 #define RCC_AHBENR_GPIODEN_Pos (20U)
Kojto 122:f9eeca106725 3074 #define RCC_AHBENR_GPIODEN_Msk (0x1U << RCC_AHBENR_GPIODEN_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 3075 #define RCC_AHBENR_GPIODEN RCC_AHBENR_GPIODEN_Msk /*!< GPIOD clock enable */
Kojto 122:f9eeca106725 3076 #define RCC_AHBENR_GPIOFEN_Pos (22U)
Kojto 122:f9eeca106725 3077 #define RCC_AHBENR_GPIOFEN_Msk (0x1U << RCC_AHBENR_GPIOFEN_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 3078 #define RCC_AHBENR_GPIOFEN RCC_AHBENR_GPIOFEN_Msk /*!< GPIOF clock enable */
Kojto 90:cb3d968589d8 3079
Kojto 90:cb3d968589d8 3080 /* Old Bit definition maintained for legacy purpose */
Kojto 90:cb3d968589d8 3081 #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */
Kojto 90:cb3d968589d8 3082 #define RCC_AHBENR_TSEN RCC_AHBENR_TSCEN /*!< TS clock enable */
Kojto 90:cb3d968589d8 3083
Kojto 90:cb3d968589d8 3084 /***************** Bit definition for RCC_APB2ENR register *****************/
Kojto 122:f9eeca106725 3085 #define RCC_APB2ENR_SYSCFGCOMPEN_Pos (0U)
Kojto 122:f9eeca106725 3086 #define RCC_APB2ENR_SYSCFGCOMPEN_Msk (0x1U << RCC_APB2ENR_SYSCFGCOMPEN_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 3087 #define RCC_APB2ENR_SYSCFGCOMPEN RCC_APB2ENR_SYSCFGCOMPEN_Msk /*!< SYSCFG and comparator clock enable */
Kojto 122:f9eeca106725 3088 #define RCC_APB2ENR_ADCEN_Pos (9U)
Kojto 122:f9eeca106725 3089 #define RCC_APB2ENR_ADCEN_Msk (0x1U << RCC_APB2ENR_ADCEN_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 3090 #define RCC_APB2ENR_ADCEN RCC_APB2ENR_ADCEN_Msk /*!< ADC1 clock enable */
Kojto 122:f9eeca106725 3091 #define RCC_APB2ENR_TIM1EN_Pos (11U)
Kojto 122:f9eeca106725 3092 #define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 3093 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 clock enable */
Kojto 122:f9eeca106725 3094 #define RCC_APB2ENR_SPI1EN_Pos (12U)
Kojto 122:f9eeca106725 3095 #define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 3096 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 clock enable */
Kojto 122:f9eeca106725 3097 #define RCC_APB2ENR_USART1EN_Pos (14U)
Kojto 122:f9eeca106725 3098 #define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 3099 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */
Kojto 122:f9eeca106725 3100 #define RCC_APB2ENR_TIM15EN_Pos (16U)
Kojto 122:f9eeca106725 3101 #define RCC_APB2ENR_TIM15EN_Msk (0x1U << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 3102 #define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk /*!< TIM15 clock enable */
Kojto 122:f9eeca106725 3103 #define RCC_APB2ENR_TIM16EN_Pos (17U)
Kojto 122:f9eeca106725 3104 #define RCC_APB2ENR_TIM16EN_Msk (0x1U << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 3105 #define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk /*!< TIM16 clock enable */
Kojto 122:f9eeca106725 3106 #define RCC_APB2ENR_TIM17EN_Pos (18U)
Kojto 122:f9eeca106725 3107 #define RCC_APB2ENR_TIM17EN_Msk (0x1U << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 3108 #define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk /*!< TIM17 clock enable */
Kojto 122:f9eeca106725 3109 #define RCC_APB2ENR_DBGMCUEN_Pos (22U)
Kojto 122:f9eeca106725 3110 #define RCC_APB2ENR_DBGMCUEN_Msk (0x1U << RCC_APB2ENR_DBGMCUEN_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 3111 #define RCC_APB2ENR_DBGMCUEN RCC_APB2ENR_DBGMCUEN_Msk /*!< DBGMCU clock enable */
Kojto 90:cb3d968589d8 3112
Kojto 90:cb3d968589d8 3113 /* Old Bit definition maintained for legacy purpose */
Kojto 90:cb3d968589d8 3114 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGCOMPEN /*!< SYSCFG clock enable */
Kojto 90:cb3d968589d8 3115 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */
Kojto 90:cb3d968589d8 3116
Kojto 90:cb3d968589d8 3117 /***************** Bit definition for RCC_APB1ENR register *****************/
Kojto 122:f9eeca106725 3118 #define RCC_APB1ENR_TIM3EN_Pos (1U)
Kojto 122:f9eeca106725 3119 #define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 3120 #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */
Kojto 122:f9eeca106725 3121 #define RCC_APB1ENR_TIM6EN_Pos (4U)
Kojto 122:f9eeca106725 3122 #define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 3123 #define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk /*!< Timer 6 clock enable */
Kojto 122:f9eeca106725 3124 #define RCC_APB1ENR_TIM14EN_Pos (8U)
Kojto 122:f9eeca106725 3125 #define RCC_APB1ENR_TIM14EN_Msk (0x1U << RCC_APB1ENR_TIM14EN_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 3126 #define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk /*!< Timer 14 clock enable */
Kojto 122:f9eeca106725 3127 #define RCC_APB1ENR_WWDGEN_Pos (11U)
Kojto 122:f9eeca106725 3128 #define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 3129 #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */
Kojto 122:f9eeca106725 3130 #define RCC_APB1ENR_SPI2EN_Pos (14U)
Kojto 122:f9eeca106725 3131 #define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 3132 #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI2 clock enable */
Kojto 122:f9eeca106725 3133 #define RCC_APB1ENR_USART2EN_Pos (17U)
Kojto 122:f9eeca106725 3134 #define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 3135 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART2 clock enable */
Kojto 122:f9eeca106725 3136 #define RCC_APB1ENR_I2C1EN_Pos (21U)
Kojto 122:f9eeca106725 3137 #define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 3138 #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C1 clock enable */
Kojto 122:f9eeca106725 3139 #define RCC_APB1ENR_I2C2EN_Pos (22U)
Kojto 122:f9eeca106725 3140 #define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 3141 #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C2 clock enable */
Kojto 122:f9eeca106725 3142 #define RCC_APB1ENR_PWREN_Pos (28U)
Kojto 122:f9eeca106725 3143 #define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 3144 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< PWR clock enable */
Kojto 90:cb3d968589d8 3145
Kojto 90:cb3d968589d8 3146 /******************* Bit definition for RCC_BDCR register ******************/
Kojto 122:f9eeca106725 3147 #define RCC_BDCR_LSEON_Pos (0U)
Kojto 122:f9eeca106725 3148 #define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 3149 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< External Low Speed oscillator enable */
Kojto 122:f9eeca106725 3150 #define RCC_BDCR_LSERDY_Pos (1U)
Kojto 122:f9eeca106725 3151 #define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 3152 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< External Low Speed oscillator Ready */
Kojto 122:f9eeca106725 3153 #define RCC_BDCR_LSEBYP_Pos (2U)
Kojto 122:f9eeca106725 3154 #define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 3155 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */
Kojto 122:f9eeca106725 3156
Kojto 122:f9eeca106725 3157 #define RCC_BDCR_LSEDRV_Pos (3U)
Kojto 122:f9eeca106725 3158 #define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */
Kojto 122:f9eeca106725 3159 #define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
Kojto 122:f9eeca106725 3160 #define RCC_BDCR_LSEDRV_0 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 3161 #define RCC_BDCR_LSEDRV_1 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 3162
Kojto 122:f9eeca106725 3163 #define RCC_BDCR_RTCSEL_Pos (8U)
Kojto 122:f9eeca106725 3164 #define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
Kojto 122:f9eeca106725 3165 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */
Kojto 122:f9eeca106725 3166 #define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 3167 #define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
Kojto 90:cb3d968589d8 3168
Kojto 90:cb3d968589d8 3169 /*!< RTC configuration */
Kojto 122:f9eeca106725 3170 #define RCC_BDCR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */
Kojto 122:f9eeca106725 3171 #define RCC_BDCR_RTCSEL_LSE (0x00000100U) /*!< LSE oscillator clock used as RTC clock */
Kojto 122:f9eeca106725 3172 #define RCC_BDCR_RTCSEL_LSI (0x00000200U) /*!< LSI oscillator clock used as RTC clock */
Kojto 122:f9eeca106725 3173 #define RCC_BDCR_RTCSEL_HSE (0x00000300U) /*!< HSE oscillator clock divided by 128 used as RTC clock */
Kojto 122:f9eeca106725 3174
Kojto 122:f9eeca106725 3175 #define RCC_BDCR_RTCEN_Pos (15U)
Kojto 122:f9eeca106725 3176 #define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 3177 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /*!< RTC clock enable */
Kojto 122:f9eeca106725 3178 #define RCC_BDCR_BDRST_Pos (16U)
Kojto 122:f9eeca106725 3179 #define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 3180 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /*!< Backup domain software reset */
Kojto 90:cb3d968589d8 3181
Kojto 90:cb3d968589d8 3182 /******************* Bit definition for RCC_CSR register *******************/
Kojto 122:f9eeca106725 3183 #define RCC_CSR_LSION_Pos (0U)
Kojto 122:f9eeca106725 3184 #define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 3185 #define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */
Kojto 122:f9eeca106725 3186 #define RCC_CSR_LSIRDY_Pos (1U)
Kojto 122:f9eeca106725 3187 #define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 3188 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */
Kojto 122:f9eeca106725 3189 #define RCC_CSR_V18PWRRSTF_Pos (23U)
Kojto 122:f9eeca106725 3190 #define RCC_CSR_V18PWRRSTF_Msk (0x1U << RCC_CSR_V18PWRRSTF_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 3191 #define RCC_CSR_V18PWRRSTF RCC_CSR_V18PWRRSTF_Msk /*!< V1.8 power domain reset flag */
Kojto 122:f9eeca106725 3192 #define RCC_CSR_RMVF_Pos (24U)
Kojto 122:f9eeca106725 3193 #define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 3194 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */
Kojto 122:f9eeca106725 3195 #define RCC_CSR_OBLRSTF_Pos (25U)
Kojto 122:f9eeca106725 3196 #define RCC_CSR_OBLRSTF_Msk (0x1U << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 3197 #define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk /*!< OBL reset flag */
Kojto 122:f9eeca106725 3198 #define RCC_CSR_PINRSTF_Pos (26U)
Kojto 122:f9eeca106725 3199 #define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 3200 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */
Kojto 122:f9eeca106725 3201 #define RCC_CSR_PORRSTF_Pos (27U)
Kojto 122:f9eeca106725 3202 #define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 3203 #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */
Kojto 122:f9eeca106725 3204 #define RCC_CSR_SFTRSTF_Pos (28U)
Kojto 122:f9eeca106725 3205 #define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 3206 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */
Kojto 122:f9eeca106725 3207 #define RCC_CSR_IWDGRSTF_Pos (29U)
Kojto 122:f9eeca106725 3208 #define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 3209 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */
Kojto 122:f9eeca106725 3210 #define RCC_CSR_WWDGRSTF_Pos (30U)
Kojto 122:f9eeca106725 3211 #define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 3212 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */
Kojto 122:f9eeca106725 3213 #define RCC_CSR_LPWRRSTF_Pos (31U)
Kojto 122:f9eeca106725 3214 #define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 3215 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */
Kojto 90:cb3d968589d8 3216
Kojto 90:cb3d968589d8 3217 /* Old Bit definition maintained for legacy purpose */
Kojto 90:cb3d968589d8 3218 #define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */
Kojto 90:cb3d968589d8 3219
Kojto 90:cb3d968589d8 3220 /******************* Bit definition for RCC_AHBRSTR register ***************/
Kojto 122:f9eeca106725 3221 #define RCC_AHBRSTR_GPIOARST_Pos (17U)
Kojto 122:f9eeca106725 3222 #define RCC_AHBRSTR_GPIOARST_Msk (0x1U << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 3223 #define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIOA clock reset */
Kojto 122:f9eeca106725 3224 #define RCC_AHBRSTR_GPIOBRST_Pos (18U)
Kojto 122:f9eeca106725 3225 #define RCC_AHBRSTR_GPIOBRST_Msk (0x1U << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 3226 #define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIOB clock reset */
Kojto 122:f9eeca106725 3227 #define RCC_AHBRSTR_GPIOCRST_Pos (19U)
Kojto 122:f9eeca106725 3228 #define RCC_AHBRSTR_GPIOCRST_Msk (0x1U << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 3229 #define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIOC clock reset */
Kojto 122:f9eeca106725 3230 #define RCC_AHBRSTR_GPIODRST_Pos (20U)
Kojto 122:f9eeca106725 3231 #define RCC_AHBRSTR_GPIODRST_Msk (0x1U << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 3232 #define RCC_AHBRSTR_GPIODRST RCC_AHBRSTR_GPIODRST_Msk /*!< GPIOD clock reset */
Kojto 122:f9eeca106725 3233 #define RCC_AHBRSTR_GPIOFRST_Pos (22U)
Kojto 122:f9eeca106725 3234 #define RCC_AHBRSTR_GPIOFRST_Msk (0x1U << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 3235 #define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk /*!< GPIOF clock reset */
Kojto 90:cb3d968589d8 3236
Kojto 90:cb3d968589d8 3237 /******************* Bit definition for RCC_CFGR2 register *****************/
Kojto 90:cb3d968589d8 3238 /*!< PREDIV configuration */
Kojto 122:f9eeca106725 3239 #define RCC_CFGR2_PREDIV_Pos (0U)
Kojto 122:f9eeca106725 3240 #define RCC_CFGR2_PREDIV_Msk (0xFU << RCC_CFGR2_PREDIV_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 3241 #define RCC_CFGR2_PREDIV RCC_CFGR2_PREDIV_Msk /*!< PREDIV[3:0] bits */
Kojto 122:f9eeca106725 3242 #define RCC_CFGR2_PREDIV_0 (0x1U << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 3243 #define RCC_CFGR2_PREDIV_1 (0x2U << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 3244 #define RCC_CFGR2_PREDIV_2 (0x4U << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 3245 #define RCC_CFGR2_PREDIV_3 (0x8U << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 3246
Kojto 122:f9eeca106725 3247 #define RCC_CFGR2_PREDIV_DIV1 (0x00000000U) /*!< PREDIV input clock not divided */
Kojto 122:f9eeca106725 3248 #define RCC_CFGR2_PREDIV_DIV2 (0x00000001U) /*!< PREDIV input clock divided by 2 */
Kojto 122:f9eeca106725 3249 #define RCC_CFGR2_PREDIV_DIV3 (0x00000002U) /*!< PREDIV input clock divided by 3 */
Kojto 122:f9eeca106725 3250 #define RCC_CFGR2_PREDIV_DIV4 (0x00000003U) /*!< PREDIV input clock divided by 4 */
Kojto 122:f9eeca106725 3251 #define RCC_CFGR2_PREDIV_DIV5 (0x00000004U) /*!< PREDIV input clock divided by 5 */
Kojto 122:f9eeca106725 3252 #define RCC_CFGR2_PREDIV_DIV6 (0x00000005U) /*!< PREDIV input clock divided by 6 */
Kojto 122:f9eeca106725 3253 #define RCC_CFGR2_PREDIV_DIV7 (0x00000006U) /*!< PREDIV input clock divided by 7 */
Kojto 122:f9eeca106725 3254 #define RCC_CFGR2_PREDIV_DIV8 (0x00000007U) /*!< PREDIV input clock divided by 8 */
Kojto 122:f9eeca106725 3255 #define RCC_CFGR2_PREDIV_DIV9 (0x00000008U) /*!< PREDIV input clock divided by 9 */
Kojto 122:f9eeca106725 3256 #define RCC_CFGR2_PREDIV_DIV10 (0x00000009U) /*!< PREDIV input clock divided by 10 */
Kojto 122:f9eeca106725 3257 #define RCC_CFGR2_PREDIV_DIV11 (0x0000000AU) /*!< PREDIV input clock divided by 11 */
Kojto 122:f9eeca106725 3258 #define RCC_CFGR2_PREDIV_DIV12 (0x0000000BU) /*!< PREDIV input clock divided by 12 */
Kojto 122:f9eeca106725 3259 #define RCC_CFGR2_PREDIV_DIV13 (0x0000000CU) /*!< PREDIV input clock divided by 13 */
Kojto 122:f9eeca106725 3260 #define RCC_CFGR2_PREDIV_DIV14 (0x0000000DU) /*!< PREDIV input clock divided by 14 */
Kojto 122:f9eeca106725 3261 #define RCC_CFGR2_PREDIV_DIV15 (0x0000000EU) /*!< PREDIV input clock divided by 15 */
Kojto 122:f9eeca106725 3262 #define RCC_CFGR2_PREDIV_DIV16 (0x0000000FU) /*!< PREDIV input clock divided by 16 */
Kojto 90:cb3d968589d8 3263
Kojto 90:cb3d968589d8 3264 /******************* Bit definition for RCC_CFGR3 register *****************/
Kojto 90:cb3d968589d8 3265 /*!< USART1 Clock source selection */
Kojto 122:f9eeca106725 3266 #define RCC_CFGR3_USART1SW_Pos (0U)
Kojto 122:f9eeca106725 3267 #define RCC_CFGR3_USART1SW_Msk (0x3U << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000003 */
Kojto 122:f9eeca106725 3268 #define RCC_CFGR3_USART1SW RCC_CFGR3_USART1SW_Msk /*!< USART1SW[1:0] bits */
Kojto 122:f9eeca106725 3269 #define RCC_CFGR3_USART1SW_0 (0x1U << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 3270 #define RCC_CFGR3_USART1SW_1 (0x2U << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 3271
Kojto 122:f9eeca106725 3272 #define RCC_CFGR3_USART1SW_PCLK (0x00000000U) /*!< PCLK clock used as USART1 clock source */
Kojto 122:f9eeca106725 3273 #define RCC_CFGR3_USART1SW_SYSCLK (0x00000001U) /*!< System clock selected as USART1 clock source */
Kojto 122:f9eeca106725 3274 #define RCC_CFGR3_USART1SW_LSE (0x00000002U) /*!< LSE oscillator clock used as USART1 clock source */
Kojto 122:f9eeca106725 3275 #define RCC_CFGR3_USART1SW_HSI (0x00000003U) /*!< HSI oscillator clock used as USART1 clock source */
Kojto 90:cb3d968589d8 3276
Kojto 90:cb3d968589d8 3277 /*!< I2C1 Clock source selection */
Kojto 122:f9eeca106725 3278 #define RCC_CFGR3_I2C1SW_Pos (4U)
Kojto 122:f9eeca106725 3279 #define RCC_CFGR3_I2C1SW_Msk (0x1U << RCC_CFGR3_I2C1SW_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 3280 #define RCC_CFGR3_I2C1SW RCC_CFGR3_I2C1SW_Msk /*!< I2C1SW bits */
Kojto 122:f9eeca106725 3281
Kojto 122:f9eeca106725 3282 #define RCC_CFGR3_I2C1SW_HSI (0x00000000U) /*!< HSI oscillator clock used as I2C1 clock source */
Kojto 122:f9eeca106725 3283 #define RCC_CFGR3_I2C1SW_SYSCLK_Pos (4U)
Kojto 122:f9eeca106725 3284 #define RCC_CFGR3_I2C1SW_SYSCLK_Msk (0x1U << RCC_CFGR3_I2C1SW_SYSCLK_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 3285 #define RCC_CFGR3_I2C1SW_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK_Msk /*!< System clock selected as I2C1 clock source */
Kojto 90:cb3d968589d8 3286
Kojto 90:cb3d968589d8 3287 /******************* Bit definition for RCC_CR2 register *******************/
Kojto 122:f9eeca106725 3288 #define RCC_CR2_HSI14ON_Pos (0U)
Kojto 122:f9eeca106725 3289 #define RCC_CR2_HSI14ON_Msk (0x1U << RCC_CR2_HSI14ON_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 3290 #define RCC_CR2_HSI14ON RCC_CR2_HSI14ON_Msk /*!< Internal High Speed 14MHz clock enable */
Kojto 122:f9eeca106725 3291 #define RCC_CR2_HSI14RDY_Pos (1U)
Kojto 122:f9eeca106725 3292 #define RCC_CR2_HSI14RDY_Msk (0x1U << RCC_CR2_HSI14RDY_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 3293 #define RCC_CR2_HSI14RDY RCC_CR2_HSI14RDY_Msk /*!< Internal High Speed 14MHz clock ready flag */
Kojto 122:f9eeca106725 3294 #define RCC_CR2_HSI14DIS_Pos (2U)
Kojto 122:f9eeca106725 3295 #define RCC_CR2_HSI14DIS_Msk (0x1U << RCC_CR2_HSI14DIS_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 3296 #define RCC_CR2_HSI14DIS RCC_CR2_HSI14DIS_Msk /*!< Internal High Speed 14MHz clock disable */
Kojto 122:f9eeca106725 3297 #define RCC_CR2_HSI14TRIM_Pos (3U)
Kojto 122:f9eeca106725 3298 #define RCC_CR2_HSI14TRIM_Msk (0x1FU << RCC_CR2_HSI14TRIM_Pos) /*!< 0x000000F8 */
Kojto 122:f9eeca106725 3299 #define RCC_CR2_HSI14TRIM RCC_CR2_HSI14TRIM_Msk /*!< Internal High Speed 14MHz clock trimming */
Kojto 122:f9eeca106725 3300 #define RCC_CR2_HSI14CAL_Pos (8U)
Kojto 122:f9eeca106725 3301 #define RCC_CR2_HSI14CAL_Msk (0xFFU << RCC_CR2_HSI14CAL_Pos) /*!< 0x0000FF00 */
Kojto 122:f9eeca106725 3302 #define RCC_CR2_HSI14CAL RCC_CR2_HSI14CAL_Msk /*!< Internal High Speed 14MHz clock Calibration */
Kojto 90:cb3d968589d8 3303
Kojto 90:cb3d968589d8 3304 /*****************************************************************************/
Kojto 90:cb3d968589d8 3305 /* */
Kojto 90:cb3d968589d8 3306 /* Real-Time Clock (RTC) */
Kojto 90:cb3d968589d8 3307 /* */
Kojto 90:cb3d968589d8 3308 /*****************************************************************************/
Kojto 122:f9eeca106725 3309 /*
Kojto 122:f9eeca106725 3310 * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
Kojto 122:f9eeca106725 3311 */
Kojto 122:f9eeca106725 3312 #define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */
Kojto 122:f9eeca106725 3313 #define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
Kojto 122:f9eeca106725 3314
Kojto 90:cb3d968589d8 3315 /******************** Bits definition for RTC_TR register ******************/
Kojto 122:f9eeca106725 3316 #define RTC_TR_PM_Pos (22U)
Kojto 122:f9eeca106725 3317 #define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 3318 #define RTC_TR_PM RTC_TR_PM_Msk
Kojto 122:f9eeca106725 3319 #define RTC_TR_HT_Pos (20U)
Kojto 122:f9eeca106725 3320 #define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
Kojto 122:f9eeca106725 3321 #define RTC_TR_HT RTC_TR_HT_Msk
Kojto 122:f9eeca106725 3322 #define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 3323 #define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 3324 #define RTC_TR_HU_Pos (16U)
Kojto 122:f9eeca106725 3325 #define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
Kojto 122:f9eeca106725 3326 #define RTC_TR_HU RTC_TR_HU_Msk
Kojto 122:f9eeca106725 3327 #define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 3328 #define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 3329 #define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 3330 #define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 3331 #define RTC_TR_MNT_Pos (12U)
Kojto 122:f9eeca106725 3332 #define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
Kojto 122:f9eeca106725 3333 #define RTC_TR_MNT RTC_TR_MNT_Msk
Kojto 122:f9eeca106725 3334 #define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 3335 #define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 3336 #define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 3337 #define RTC_TR_MNU_Pos (8U)
Kojto 122:f9eeca106725 3338 #define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
Kojto 122:f9eeca106725 3339 #define RTC_TR_MNU RTC_TR_MNU_Msk
Kojto 122:f9eeca106725 3340 #define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 3341 #define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 3342 #define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 3343 #define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 3344 #define RTC_TR_ST_Pos (4U)
Kojto 122:f9eeca106725 3345 #define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
Kojto 122:f9eeca106725 3346 #define RTC_TR_ST RTC_TR_ST_Msk
Kojto 122:f9eeca106725 3347 #define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 3348 #define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 3349 #define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 3350 #define RTC_TR_SU_Pos (0U)
Kojto 122:f9eeca106725 3351 #define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 3352 #define RTC_TR_SU RTC_TR_SU_Msk
Kojto 122:f9eeca106725 3353 #define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 3354 #define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 3355 #define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 3356 #define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
Kojto 90:cb3d968589d8 3357
Kojto 90:cb3d968589d8 3358 /******************** Bits definition for RTC_DR register ******************/
Kojto 122:f9eeca106725 3359 #define RTC_DR_YT_Pos (20U)
Kojto 122:f9eeca106725 3360 #define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
Kojto 122:f9eeca106725 3361 #define RTC_DR_YT RTC_DR_YT_Msk
Kojto 122:f9eeca106725 3362 #define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 3363 #define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 3364 #define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 3365 #define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 3366 #define RTC_DR_YU_Pos (16U)
Kojto 122:f9eeca106725 3367 #define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
Kojto 122:f9eeca106725 3368 #define RTC_DR_YU RTC_DR_YU_Msk
Kojto 122:f9eeca106725 3369 #define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 3370 #define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 3371 #define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 3372 #define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 3373 #define RTC_DR_WDU_Pos (13U)
Kojto 122:f9eeca106725 3374 #define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
Kojto 122:f9eeca106725 3375 #define RTC_DR_WDU RTC_DR_WDU_Msk
Kojto 122:f9eeca106725 3376 #define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 3377 #define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 3378 #define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 3379 #define RTC_DR_MT_Pos (12U)
Kojto 122:f9eeca106725 3380 #define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 3381 #define RTC_DR_MT RTC_DR_MT_Msk
Kojto 122:f9eeca106725 3382 #define RTC_DR_MU_Pos (8U)
Kojto 122:f9eeca106725 3383 #define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
Kojto 122:f9eeca106725 3384 #define RTC_DR_MU RTC_DR_MU_Msk
Kojto 122:f9eeca106725 3385 #define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 3386 #define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 3387 #define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 3388 #define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 3389 #define RTC_DR_DT_Pos (4U)
Kojto 122:f9eeca106725 3390 #define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
Kojto 122:f9eeca106725 3391 #define RTC_DR_DT RTC_DR_DT_Msk
Kojto 122:f9eeca106725 3392 #define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 3393 #define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 3394 #define RTC_DR_DU_Pos (0U)
Kojto 122:f9eeca106725 3395 #define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 3396 #define RTC_DR_DU RTC_DR_DU_Msk
Kojto 122:f9eeca106725 3397 #define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 3398 #define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 3399 #define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 3400 #define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
Kojto 90:cb3d968589d8 3401
Kojto 90:cb3d968589d8 3402 /******************** Bits definition for RTC_CR register ******************/
Kojto 122:f9eeca106725 3403 #define RTC_CR_COE_Pos (23U)
Kojto 122:f9eeca106725 3404 #define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 3405 #define RTC_CR_COE RTC_CR_COE_Msk
Kojto 122:f9eeca106725 3406 #define RTC_CR_OSEL_Pos (21U)
Kojto 122:f9eeca106725 3407 #define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
Kojto 122:f9eeca106725 3408 #define RTC_CR_OSEL RTC_CR_OSEL_Msk
Kojto 122:f9eeca106725 3409 #define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 3410 #define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 3411 #define RTC_CR_POL_Pos (20U)
Kojto 122:f9eeca106725 3412 #define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 3413 #define RTC_CR_POL RTC_CR_POL_Msk
Kojto 122:f9eeca106725 3414 #define RTC_CR_COSEL_Pos (19U)
Kojto 122:f9eeca106725 3415 #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 3416 #define RTC_CR_COSEL RTC_CR_COSEL_Msk
Kojto 122:f9eeca106725 3417 #define RTC_CR_BCK_Pos (18U)
Kojto 122:f9eeca106725 3418 #define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 3419 #define RTC_CR_BCK RTC_CR_BCK_Msk
Kojto 122:f9eeca106725 3420 #define RTC_CR_SUB1H_Pos (17U)
Kojto 122:f9eeca106725 3421 #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 3422 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
Kojto 122:f9eeca106725 3423 #define RTC_CR_ADD1H_Pos (16U)
Kojto 122:f9eeca106725 3424 #define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 3425 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
Kojto 122:f9eeca106725 3426 #define RTC_CR_TSIE_Pos (15U)
Kojto 122:f9eeca106725 3427 #define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 3428 #define RTC_CR_TSIE RTC_CR_TSIE_Msk
Kojto 122:f9eeca106725 3429 #define RTC_CR_ALRAIE_Pos (12U)
Kojto 122:f9eeca106725 3430 #define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 3431 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
Kojto 122:f9eeca106725 3432 #define RTC_CR_TSE_Pos (11U)
Kojto 122:f9eeca106725 3433 #define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 3434 #define RTC_CR_TSE RTC_CR_TSE_Msk
Kojto 122:f9eeca106725 3435 #define RTC_CR_ALRAE_Pos (8U)
Kojto 122:f9eeca106725 3436 #define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 3437 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
Kojto 122:f9eeca106725 3438 #define RTC_CR_FMT_Pos (6U)
Kojto 122:f9eeca106725 3439 #define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 3440 #define RTC_CR_FMT RTC_CR_FMT_Msk
Kojto 122:f9eeca106725 3441 #define RTC_CR_BYPSHAD_Pos (5U)
Kojto 122:f9eeca106725 3442 #define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 3443 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
Kojto 122:f9eeca106725 3444 #define RTC_CR_REFCKON_Pos (4U)
Kojto 122:f9eeca106725 3445 #define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 3446 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
Kojto 122:f9eeca106725 3447 #define RTC_CR_TSEDGE_Pos (3U)
Kojto 122:f9eeca106725 3448 #define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 3449 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
Kojto 90:cb3d968589d8 3450
Kojto 90:cb3d968589d8 3451 /******************** Bits definition for RTC_ISR register *****************/
Kojto 122:f9eeca106725 3452 #define RTC_ISR_RECALPF_Pos (16U)
Kojto 122:f9eeca106725 3453 #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 3454 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
Kojto 122:f9eeca106725 3455 #define RTC_ISR_TAMP2F_Pos (14U)
Kojto 122:f9eeca106725 3456 #define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 3457 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
Kojto 122:f9eeca106725 3458 #define RTC_ISR_TAMP1F_Pos (13U)
Kojto 122:f9eeca106725 3459 #define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 3460 #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
Kojto 122:f9eeca106725 3461 #define RTC_ISR_TSOVF_Pos (12U)
Kojto 122:f9eeca106725 3462 #define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 3463 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
Kojto 122:f9eeca106725 3464 #define RTC_ISR_TSF_Pos (11U)
Kojto 122:f9eeca106725 3465 #define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 3466 #define RTC_ISR_TSF RTC_ISR_TSF_Msk
Kojto 122:f9eeca106725 3467 #define RTC_ISR_ALRAF_Pos (8U)
Kojto 122:f9eeca106725 3468 #define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 3469 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
Kojto 122:f9eeca106725 3470 #define RTC_ISR_INIT_Pos (7U)
Kojto 122:f9eeca106725 3471 #define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 3472 #define RTC_ISR_INIT RTC_ISR_INIT_Msk
Kojto 122:f9eeca106725 3473 #define RTC_ISR_INITF_Pos (6U)
Kojto 122:f9eeca106725 3474 #define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 3475 #define RTC_ISR_INITF RTC_ISR_INITF_Msk
Kojto 122:f9eeca106725 3476 #define RTC_ISR_RSF_Pos (5U)
Kojto 122:f9eeca106725 3477 #define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 3478 #define RTC_ISR_RSF RTC_ISR_RSF_Msk
Kojto 122:f9eeca106725 3479 #define RTC_ISR_INITS_Pos (4U)
Kojto 122:f9eeca106725 3480 #define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 3481 #define RTC_ISR_INITS RTC_ISR_INITS_Msk
Kojto 122:f9eeca106725 3482 #define RTC_ISR_SHPF_Pos (3U)
Kojto 122:f9eeca106725 3483 #define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 3484 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
Kojto 122:f9eeca106725 3485 #define RTC_ISR_ALRAWF_Pos (0U)
Kojto 122:f9eeca106725 3486 #define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 3487 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
Kojto 90:cb3d968589d8 3488
Kojto 90:cb3d968589d8 3489 /******************** Bits definition for RTC_PRER register ****************/
Kojto 122:f9eeca106725 3490 #define RTC_PRER_PREDIV_A_Pos (16U)
Kojto 122:f9eeca106725 3491 #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
Kojto 122:f9eeca106725 3492 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
Kojto 122:f9eeca106725 3493 #define RTC_PRER_PREDIV_S_Pos (0U)
Kojto 122:f9eeca106725 3494 #define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
Kojto 122:f9eeca106725 3495 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
Kojto 90:cb3d968589d8 3496
Kojto 90:cb3d968589d8 3497 /******************** Bits definition for RTC_ALRMAR register **************/
Kojto 122:f9eeca106725 3498 #define RTC_ALRMAR_MSK4_Pos (31U)
Kojto 122:f9eeca106725 3499 #define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 3500 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
Kojto 122:f9eeca106725 3501 #define RTC_ALRMAR_WDSEL_Pos (30U)
Kojto 122:f9eeca106725 3502 #define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
Kojto 122:f9eeca106725 3503 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
Kojto 122:f9eeca106725 3504 #define RTC_ALRMAR_DT_Pos (28U)
Kojto 122:f9eeca106725 3505 #define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
Kojto 122:f9eeca106725 3506 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
Kojto 122:f9eeca106725 3507 #define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
Kojto 122:f9eeca106725 3508 #define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
Kojto 122:f9eeca106725 3509 #define RTC_ALRMAR_DU_Pos (24U)
Kojto 122:f9eeca106725 3510 #define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
Kojto 122:f9eeca106725 3511 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
Kojto 122:f9eeca106725 3512 #define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 3513 #define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 3514 #define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 3515 #define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 3516 #define RTC_ALRMAR_MSK3_Pos (23U)
Kojto 122:f9eeca106725 3517 #define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 3518 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
Kojto 122:f9eeca106725 3519 #define RTC_ALRMAR_PM_Pos (22U)
Kojto 122:f9eeca106725 3520 #define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 3521 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
Kojto 122:f9eeca106725 3522 #define RTC_ALRMAR_HT_Pos (20U)
Kojto 122:f9eeca106725 3523 #define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
Kojto 122:f9eeca106725 3524 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
Kojto 122:f9eeca106725 3525 #define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 3526 #define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 3527 #define RTC_ALRMAR_HU_Pos (16U)
Kojto 122:f9eeca106725 3528 #define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
Kojto 122:f9eeca106725 3529 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
Kojto 122:f9eeca106725 3530 #define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 3531 #define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 3532 #define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 3533 #define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 3534 #define RTC_ALRMAR_MSK2_Pos (15U)
Kojto 122:f9eeca106725 3535 #define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 3536 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
Kojto 122:f9eeca106725 3537 #define RTC_ALRMAR_MNT_Pos (12U)
Kojto 122:f9eeca106725 3538 #define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
Kojto 122:f9eeca106725 3539 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
Kojto 122:f9eeca106725 3540 #define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 3541 #define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 3542 #define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 3543 #define RTC_ALRMAR_MNU_Pos (8U)
Kojto 122:f9eeca106725 3544 #define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
Kojto 122:f9eeca106725 3545 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
Kojto 122:f9eeca106725 3546 #define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 3547 #define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 3548 #define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 3549 #define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 3550 #define RTC_ALRMAR_MSK1_Pos (7U)
Kojto 122:f9eeca106725 3551 #define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 3552 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
Kojto 122:f9eeca106725 3553 #define RTC_ALRMAR_ST_Pos (4U)
Kojto 122:f9eeca106725 3554 #define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
Kojto 122:f9eeca106725 3555 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
Kojto 122:f9eeca106725 3556 #define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 3557 #define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 3558 #define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 3559 #define RTC_ALRMAR_SU_Pos (0U)
Kojto 122:f9eeca106725 3560 #define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 3561 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
Kojto 122:f9eeca106725 3562 #define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 3563 #define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 3564 #define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 3565 #define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
Kojto 90:cb3d968589d8 3566
Kojto 90:cb3d968589d8 3567 /******************** Bits definition for RTC_WPR register *****************/
Kojto 122:f9eeca106725 3568 #define RTC_WPR_KEY_Pos (0U)
Kojto 122:f9eeca106725 3569 #define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 3570 #define RTC_WPR_KEY RTC_WPR_KEY_Msk
Kojto 90:cb3d968589d8 3571
Kojto 90:cb3d968589d8 3572 /******************** Bits definition for RTC_SSR register *****************/
Kojto 122:f9eeca106725 3573 #define RTC_SSR_SS_Pos (0U)
Kojto 122:f9eeca106725 3574 #define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 3575 #define RTC_SSR_SS RTC_SSR_SS_Msk
Kojto 90:cb3d968589d8 3576
Kojto 90:cb3d968589d8 3577 /******************** Bits definition for RTC_SHIFTR register **************/
Kojto 122:f9eeca106725 3578 #define RTC_SHIFTR_SUBFS_Pos (0U)
Kojto 122:f9eeca106725 3579 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
Kojto 122:f9eeca106725 3580 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
Kojto 122:f9eeca106725 3581 #define RTC_SHIFTR_ADD1S_Pos (31U)
Kojto 122:f9eeca106725 3582 #define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
Kojto 122:f9eeca106725 3583 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
Kojto 90:cb3d968589d8 3584
Kojto 90:cb3d968589d8 3585 /******************** Bits definition for RTC_TSTR register ****************/
Kojto 122:f9eeca106725 3586 #define RTC_TSTR_PM_Pos (22U)
Kojto 122:f9eeca106725 3587 #define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 3588 #define RTC_TSTR_PM RTC_TSTR_PM_Msk
Kojto 122:f9eeca106725 3589 #define RTC_TSTR_HT_Pos (20U)
Kojto 122:f9eeca106725 3590 #define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
Kojto 122:f9eeca106725 3591 #define RTC_TSTR_HT RTC_TSTR_HT_Msk
Kojto 122:f9eeca106725 3592 #define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 3593 #define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 3594 #define RTC_TSTR_HU_Pos (16U)
Kojto 122:f9eeca106725 3595 #define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
Kojto 122:f9eeca106725 3596 #define RTC_TSTR_HU RTC_TSTR_HU_Msk
Kojto 122:f9eeca106725 3597 #define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 3598 #define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 3599 #define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 3600 #define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 3601 #define RTC_TSTR_MNT_Pos (12U)
Kojto 122:f9eeca106725 3602 #define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
Kojto 122:f9eeca106725 3603 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
Kojto 122:f9eeca106725 3604 #define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 3605 #define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 3606 #define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 3607 #define RTC_TSTR_MNU_Pos (8U)
Kojto 122:f9eeca106725 3608 #define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
Kojto 122:f9eeca106725 3609 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
Kojto 122:f9eeca106725 3610 #define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 3611 #define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 3612 #define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 3613 #define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 3614 #define RTC_TSTR_ST_Pos (4U)
Kojto 122:f9eeca106725 3615 #define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
Kojto 122:f9eeca106725 3616 #define RTC_TSTR_ST RTC_TSTR_ST_Msk
Kojto 122:f9eeca106725 3617 #define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 3618 #define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 3619 #define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 3620 #define RTC_TSTR_SU_Pos (0U)
Kojto 122:f9eeca106725 3621 #define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 3622 #define RTC_TSTR_SU RTC_TSTR_SU_Msk
Kojto 122:f9eeca106725 3623 #define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 3624 #define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 3625 #define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 3626 #define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
Kojto 90:cb3d968589d8 3627
Kojto 90:cb3d968589d8 3628 /******************** Bits definition for RTC_TSDR register ****************/
Kojto 122:f9eeca106725 3629 #define RTC_TSDR_WDU_Pos (13U)
Kojto 122:f9eeca106725 3630 #define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
Kojto 122:f9eeca106725 3631 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
Kojto 122:f9eeca106725 3632 #define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 3633 #define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 3634 #define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 3635 #define RTC_TSDR_MT_Pos (12U)
Kojto 122:f9eeca106725 3636 #define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 3637 #define RTC_TSDR_MT RTC_TSDR_MT_Msk
Kojto 122:f9eeca106725 3638 #define RTC_TSDR_MU_Pos (8U)
Kojto 122:f9eeca106725 3639 #define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
Kojto 122:f9eeca106725 3640 #define RTC_TSDR_MU RTC_TSDR_MU_Msk
Kojto 122:f9eeca106725 3641 #define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 3642 #define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 3643 #define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 3644 #define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 3645 #define RTC_TSDR_DT_Pos (4U)
Kojto 122:f9eeca106725 3646 #define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
Kojto 122:f9eeca106725 3647 #define RTC_TSDR_DT RTC_TSDR_DT_Msk
Kojto 122:f9eeca106725 3648 #define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 3649 #define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 3650 #define RTC_TSDR_DU_Pos (0U)
Kojto 122:f9eeca106725 3651 #define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 3652 #define RTC_TSDR_DU RTC_TSDR_DU_Msk
Kojto 122:f9eeca106725 3653 #define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 3654 #define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 3655 #define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 3656 #define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
Kojto 90:cb3d968589d8 3657
Kojto 90:cb3d968589d8 3658 /******************** Bits definition for RTC_TSSSR register ***************/
Kojto 122:f9eeca106725 3659 #define RTC_TSSSR_SS_Pos (0U)
Kojto 122:f9eeca106725 3660 #define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 3661 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
Kojto 90:cb3d968589d8 3662
Kojto 90:cb3d968589d8 3663 /******************** Bits definition for RTC_CALR register ****************/
Kojto 122:f9eeca106725 3664 #define RTC_CALR_CALP_Pos (15U)
Kojto 122:f9eeca106725 3665 #define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 3666 #define RTC_CALR_CALP RTC_CALR_CALP_Msk
Kojto 122:f9eeca106725 3667 #define RTC_CALR_CALW8_Pos (14U)
Kojto 122:f9eeca106725 3668 #define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 3669 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
Kojto 122:f9eeca106725 3670 #define RTC_CALR_CALW16_Pos (13U)
Kojto 122:f9eeca106725 3671 #define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 3672 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
Kojto 122:f9eeca106725 3673 #define RTC_CALR_CALM_Pos (0U)
Kojto 122:f9eeca106725 3674 #define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
Kojto 122:f9eeca106725 3675 #define RTC_CALR_CALM RTC_CALR_CALM_Msk
Kojto 122:f9eeca106725 3676 #define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 3677 #define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 3678 #define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 3679 #define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 3680 #define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 3681 #define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 3682 #define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 3683 #define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 3684 #define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
Kojto 90:cb3d968589d8 3685
Kojto 90:cb3d968589d8 3686 /******************** Bits definition for RTC_TAFCR register ***************/
Kojto 122:f9eeca106725 3687 #define RTC_TAFCR_PC15MODE_Pos (23U)
Kojto 122:f9eeca106725 3688 #define RTC_TAFCR_PC15MODE_Msk (0x1U << RTC_TAFCR_PC15MODE_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 3689 #define RTC_TAFCR_PC15MODE RTC_TAFCR_PC15MODE_Msk
Kojto 122:f9eeca106725 3690 #define RTC_TAFCR_PC15VALUE_Pos (22U)
Kojto 122:f9eeca106725 3691 #define RTC_TAFCR_PC15VALUE_Msk (0x1U << RTC_TAFCR_PC15VALUE_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 3692 #define RTC_TAFCR_PC15VALUE RTC_TAFCR_PC15VALUE_Msk
Kojto 122:f9eeca106725 3693 #define RTC_TAFCR_PC14MODE_Pos (21U)
Kojto 122:f9eeca106725 3694 #define RTC_TAFCR_PC14MODE_Msk (0x1U << RTC_TAFCR_PC14MODE_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 3695 #define RTC_TAFCR_PC14MODE RTC_TAFCR_PC14MODE_Msk
Kojto 122:f9eeca106725 3696 #define RTC_TAFCR_PC14VALUE_Pos (20U)
Kojto 122:f9eeca106725 3697 #define RTC_TAFCR_PC14VALUE_Msk (0x1U << RTC_TAFCR_PC14VALUE_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 3698 #define RTC_TAFCR_PC14VALUE RTC_TAFCR_PC14VALUE_Msk
Kojto 122:f9eeca106725 3699 #define RTC_TAFCR_PC13MODE_Pos (19U)
Kojto 122:f9eeca106725 3700 #define RTC_TAFCR_PC13MODE_Msk (0x1U << RTC_TAFCR_PC13MODE_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 3701 #define RTC_TAFCR_PC13MODE RTC_TAFCR_PC13MODE_Msk
Kojto 122:f9eeca106725 3702 #define RTC_TAFCR_PC13VALUE_Pos (18U)
Kojto 122:f9eeca106725 3703 #define RTC_TAFCR_PC13VALUE_Msk (0x1U << RTC_TAFCR_PC13VALUE_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 3704 #define RTC_TAFCR_PC13VALUE RTC_TAFCR_PC13VALUE_Msk
Kojto 122:f9eeca106725 3705 #define RTC_TAFCR_TAMPPUDIS_Pos (15U)
Kojto 122:f9eeca106725 3706 #define RTC_TAFCR_TAMPPUDIS_Msk (0x1U << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 3707 #define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
Kojto 122:f9eeca106725 3708 #define RTC_TAFCR_TAMPPRCH_Pos (13U)
Kojto 122:f9eeca106725 3709 #define RTC_TAFCR_TAMPPRCH_Msk (0x3U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */
Kojto 122:f9eeca106725 3710 #define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
Kojto 122:f9eeca106725 3711 #define RTC_TAFCR_TAMPPRCH_0 (0x1U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 3712 #define RTC_TAFCR_TAMPPRCH_1 (0x2U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 3713 #define RTC_TAFCR_TAMPFLT_Pos (11U)
Kojto 122:f9eeca106725 3714 #define RTC_TAFCR_TAMPFLT_Msk (0x3U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */
Kojto 122:f9eeca106725 3715 #define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
Kojto 122:f9eeca106725 3716 #define RTC_TAFCR_TAMPFLT_0 (0x1U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 3717 #define RTC_TAFCR_TAMPFLT_1 (0x2U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 3718 #define RTC_TAFCR_TAMPFREQ_Pos (8U)
Kojto 122:f9eeca106725 3719 #define RTC_TAFCR_TAMPFREQ_Msk (0x7U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */
Kojto 122:f9eeca106725 3720 #define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
Kojto 122:f9eeca106725 3721 #define RTC_TAFCR_TAMPFREQ_0 (0x1U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 3722 #define RTC_TAFCR_TAMPFREQ_1 (0x2U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 3723 #define RTC_TAFCR_TAMPFREQ_2 (0x4U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 3724 #define RTC_TAFCR_TAMPTS_Pos (7U)
Kojto 122:f9eeca106725 3725 #define RTC_TAFCR_TAMPTS_Msk (0x1U << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 3726 #define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
Kojto 122:f9eeca106725 3727 #define RTC_TAFCR_TAMP2TRG_Pos (4U)
Kojto 122:f9eeca106725 3728 #define RTC_TAFCR_TAMP2TRG_Msk (0x1U << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 3729 #define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
Kojto 122:f9eeca106725 3730 #define RTC_TAFCR_TAMP2E_Pos (3U)
Kojto 122:f9eeca106725 3731 #define RTC_TAFCR_TAMP2E_Msk (0x1U << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 3732 #define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
Kojto 122:f9eeca106725 3733 #define RTC_TAFCR_TAMPIE_Pos (2U)
Kojto 122:f9eeca106725 3734 #define RTC_TAFCR_TAMPIE_Msk (0x1U << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 3735 #define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
Kojto 122:f9eeca106725 3736 #define RTC_TAFCR_TAMP1TRG_Pos (1U)
Kojto 122:f9eeca106725 3737 #define RTC_TAFCR_TAMP1TRG_Msk (0x1U << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 3738 #define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
Kojto 122:f9eeca106725 3739 #define RTC_TAFCR_TAMP1E_Pos (0U)
Kojto 122:f9eeca106725 3740 #define RTC_TAFCR_TAMP1E_Msk (0x1U << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 3741 #define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
Kojto 122:f9eeca106725 3742
Kojto 122:f9eeca106725 3743 /* Reference defines */
Kojto 122:f9eeca106725 3744 #define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_PC13VALUE
Kojto 90:cb3d968589d8 3745
Kojto 90:cb3d968589d8 3746 /******************** Bits definition for RTC_ALRMASSR register ************/
Kojto 122:f9eeca106725 3747 #define RTC_ALRMASSR_MASKSS_Pos (24U)
Kojto 122:f9eeca106725 3748 #define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
Kojto 122:f9eeca106725 3749 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
Kojto 122:f9eeca106725 3750 #define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 3751 #define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 3752 #define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 3753 #define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 3754 #define RTC_ALRMASSR_SS_Pos (0U)
Kojto 122:f9eeca106725 3755 #define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
Kojto 122:f9eeca106725 3756 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
Kojto 90:cb3d968589d8 3757
Kojto 90:cb3d968589d8 3758 /*****************************************************************************/
Kojto 90:cb3d968589d8 3759 /* */
Kojto 90:cb3d968589d8 3760 /* Serial Peripheral Interface (SPI) */
Kojto 90:cb3d968589d8 3761 /* */
Kojto 90:cb3d968589d8 3762 /*****************************************************************************/
Kojto 122:f9eeca106725 3763
Kojto 122:f9eeca106725 3764 /*
Kojto 122:f9eeca106725 3765 * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
Kojto 122:f9eeca106725 3766 */
Kojto 122:f9eeca106725 3767 /* Note: No specific macro feature on this device */
Kojto 122:f9eeca106725 3768
Kojto 90:cb3d968589d8 3769 /******************* Bit definition for SPI_CR1 register *******************/
Kojto 122:f9eeca106725 3770 #define SPI_CR1_CPHA_Pos (0U)
Kojto 122:f9eeca106725 3771 #define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 3772 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
Kojto 122:f9eeca106725 3773 #define SPI_CR1_CPOL_Pos (1U)
Kojto 122:f9eeca106725 3774 #define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 3775 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */
Kojto 122:f9eeca106725 3776 #define SPI_CR1_MSTR_Pos (2U)
Kojto 122:f9eeca106725 3777 #define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 3778 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */
Kojto 122:f9eeca106725 3779 #define SPI_CR1_BR_Pos (3U)
Kojto 122:f9eeca106725 3780 #define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
Kojto 122:f9eeca106725 3781 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */
Kojto 122:f9eeca106725 3782 #define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 3783 #define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 3784 #define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 3785 #define SPI_CR1_SPE_Pos (6U)
Kojto 122:f9eeca106725 3786 #define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 3787 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
Kojto 122:f9eeca106725 3788 #define SPI_CR1_LSBFIRST_Pos (7U)
Kojto 122:f9eeca106725 3789 #define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 3790 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */
Kojto 122:f9eeca106725 3791 #define SPI_CR1_SSI_Pos (8U)
Kojto 122:f9eeca106725 3792 #define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 3793 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */
Kojto 122:f9eeca106725 3794 #define SPI_CR1_SSM_Pos (9U)
Kojto 122:f9eeca106725 3795 #define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 3796 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */
Kojto 122:f9eeca106725 3797 #define SPI_CR1_RXONLY_Pos (10U)
Kojto 122:f9eeca106725 3798 #define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 3799 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */
Kojto 122:f9eeca106725 3800 #define SPI_CR1_CRCL_Pos (11U)
Kojto 122:f9eeca106725 3801 #define SPI_CR1_CRCL_Msk (0x1U << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 3802 #define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */
Kojto 122:f9eeca106725 3803 #define SPI_CR1_CRCNEXT_Pos (12U)
Kojto 122:f9eeca106725 3804 #define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 3805 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */
Kojto 122:f9eeca106725 3806 #define SPI_CR1_CRCEN_Pos (13U)
Kojto 122:f9eeca106725 3807 #define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 3808 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */
Kojto 122:f9eeca106725 3809 #define SPI_CR1_BIDIOE_Pos (14U)
Kojto 122:f9eeca106725 3810 #define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 3811 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */
Kojto 122:f9eeca106725 3812 #define SPI_CR1_BIDIMODE_Pos (15U)
Kojto 122:f9eeca106725 3813 #define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 3814 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */
Kojto 90:cb3d968589d8 3815
Kojto 90:cb3d968589d8 3816 /******************* Bit definition for SPI_CR2 register *******************/
Kojto 122:f9eeca106725 3817 #define SPI_CR2_RXDMAEN_Pos (0U)
Kojto 122:f9eeca106725 3818 #define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 3819 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
Kojto 122:f9eeca106725 3820 #define SPI_CR2_TXDMAEN_Pos (1U)
Kojto 122:f9eeca106725 3821 #define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 3822 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
Kojto 122:f9eeca106725 3823 #define SPI_CR2_SSOE_Pos (2U)
Kojto 122:f9eeca106725 3824 #define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 3825 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
Kojto 122:f9eeca106725 3826 #define SPI_CR2_NSSP_Pos (3U)
Kojto 122:f9eeca106725 3827 #define SPI_CR2_NSSP_Msk (0x1U << SPI_CR2_NSSP_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 3828 #define SPI_CR2_NSSP SPI_CR2_NSSP_Msk /*!< NSS pulse management Enable */
Kojto 122:f9eeca106725 3829 #define SPI_CR2_FRF_Pos (4U)
Kojto 122:f9eeca106725 3830 #define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 3831 #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */
Kojto 122:f9eeca106725 3832 #define SPI_CR2_ERRIE_Pos (5U)
Kojto 122:f9eeca106725 3833 #define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 3834 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
Kojto 122:f9eeca106725 3835 #define SPI_CR2_RXNEIE_Pos (6U)
Kojto 122:f9eeca106725 3836 #define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 3837 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
Kojto 122:f9eeca106725 3838 #define SPI_CR2_TXEIE_Pos (7U)
Kojto 122:f9eeca106725 3839 #define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 3840 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
Kojto 122:f9eeca106725 3841 #define SPI_CR2_DS_Pos (8U)
Kojto 122:f9eeca106725 3842 #define SPI_CR2_DS_Msk (0xFU << SPI_CR2_DS_Pos) /*!< 0x00000F00 */
Kojto 122:f9eeca106725 3843 #define SPI_CR2_DS SPI_CR2_DS_Msk /*!< DS[3:0] Data Size */
Kojto 122:f9eeca106725 3844 #define SPI_CR2_DS_0 (0x1U << SPI_CR2_DS_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 3845 #define SPI_CR2_DS_1 (0x2U << SPI_CR2_DS_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 3846 #define SPI_CR2_DS_2 (0x4U << SPI_CR2_DS_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 3847 #define SPI_CR2_DS_3 (0x8U << SPI_CR2_DS_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 3848 #define SPI_CR2_FRXTH_Pos (12U)
Kojto 122:f9eeca106725 3849 #define SPI_CR2_FRXTH_Msk (0x1U << SPI_CR2_FRXTH_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 3850 #define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk /*!< FIFO reception Threshold */
Kojto 122:f9eeca106725 3851 #define SPI_CR2_LDMARX_Pos (13U)
Kojto 122:f9eeca106725 3852 #define SPI_CR2_LDMARX_Msk (0x1U << SPI_CR2_LDMARX_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 3853 #define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk /*!< Last DMA transfer for reception */
Kojto 122:f9eeca106725 3854 #define SPI_CR2_LDMATX_Pos (14U)
Kojto 122:f9eeca106725 3855 #define SPI_CR2_LDMATX_Msk (0x1U << SPI_CR2_LDMATX_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 3856 #define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk /*!< Last DMA transfer for transmission */
Kojto 90:cb3d968589d8 3857
Kojto 90:cb3d968589d8 3858 /******************** Bit definition for SPI_SR register *******************/
Kojto 122:f9eeca106725 3859 #define SPI_SR_RXNE_Pos (0U)
Kojto 122:f9eeca106725 3860 #define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 3861 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
Kojto 122:f9eeca106725 3862 #define SPI_SR_TXE_Pos (1U)
Kojto 122:f9eeca106725 3863 #define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 3864 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
Kojto 122:f9eeca106725 3865 #define SPI_SR_CRCERR_Pos (4U)
Kojto 122:f9eeca106725 3866 #define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 3867 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
Kojto 122:f9eeca106725 3868 #define SPI_SR_MODF_Pos (5U)
Kojto 122:f9eeca106725 3869 #define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 3870 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
Kojto 122:f9eeca106725 3871 #define SPI_SR_OVR_Pos (6U)
Kojto 122:f9eeca106725 3872 #define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 3873 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
Kojto 122:f9eeca106725 3874 #define SPI_SR_BSY_Pos (7U)
Kojto 122:f9eeca106725 3875 #define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 3876 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
Kojto 122:f9eeca106725 3877 #define SPI_SR_FRE_Pos (8U)
Kojto 122:f9eeca106725 3878 #define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 3879 #define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */
Kojto 122:f9eeca106725 3880 #define SPI_SR_FRLVL_Pos (9U)
Kojto 122:f9eeca106725 3881 #define SPI_SR_FRLVL_Msk (0x3U << SPI_SR_FRLVL_Pos) /*!< 0x00000600 */
Kojto 122:f9eeca106725 3882 #define SPI_SR_FRLVL SPI_SR_FRLVL_Msk /*!< FIFO Reception Level */
Kojto 122:f9eeca106725 3883 #define SPI_SR_FRLVL_0 (0x1U << SPI_SR_FRLVL_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 3884 #define SPI_SR_FRLVL_1 (0x2U << SPI_SR_FRLVL_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 3885 #define SPI_SR_FTLVL_Pos (11U)
Kojto 122:f9eeca106725 3886 #define SPI_SR_FTLVL_Msk (0x3U << SPI_SR_FTLVL_Pos) /*!< 0x00001800 */
Kojto 122:f9eeca106725 3887 #define SPI_SR_FTLVL SPI_SR_FTLVL_Msk /*!< FIFO Transmission Level */
Kojto 122:f9eeca106725 3888 #define SPI_SR_FTLVL_0 (0x1U << SPI_SR_FTLVL_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 3889 #define SPI_SR_FTLVL_1 (0x2U << SPI_SR_FTLVL_Pos) /*!< 0x00001000 */
Kojto 90:cb3d968589d8 3890
Kojto 90:cb3d968589d8 3891 /******************** Bit definition for SPI_DR register *******************/
Kojto 122:f9eeca106725 3892 #define SPI_DR_DR_Pos (0U)
Kojto 122:f9eeca106725 3893 #define SPI_DR_DR_Msk (0xFFFFFFFFU << SPI_DR_DR_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 3894 #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
Kojto 90:cb3d968589d8 3895
Kojto 90:cb3d968589d8 3896 /******************* Bit definition for SPI_CRCPR register *****************/
Kojto 122:f9eeca106725 3897 #define SPI_CRCPR_CRCPOLY_Pos (0U)
Kojto 122:f9eeca106725 3898 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 3899 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */
Kojto 90:cb3d968589d8 3900
Kojto 90:cb3d968589d8 3901 /****************** Bit definition for SPI_RXCRCR register *****************/
Kojto 122:f9eeca106725 3902 #define SPI_RXCRCR_RXCRC_Pos (0U)
Kojto 122:f9eeca106725 3903 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 3904 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */
Kojto 90:cb3d968589d8 3905
Kojto 90:cb3d968589d8 3906 /****************** Bit definition for SPI_TXCRCR register *****************/
Kojto 122:f9eeca106725 3907 #define SPI_TXCRCR_TXCRC_Pos (0U)
Kojto 122:f9eeca106725 3908 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 3909 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
Kojto 90:cb3d968589d8 3910
Kojto 90:cb3d968589d8 3911 /****************** Bit definition for SPI_I2SCFGR register ****************/
Kojto 122:f9eeca106725 3912 #define SPI_I2SCFGR_I2SMOD_Pos (11U)
Kojto 122:f9eeca106725 3913 #define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 3914 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< Keep for compatibility */
Kojto 90:cb3d968589d8 3915
Kojto 90:cb3d968589d8 3916 /*****************************************************************************/
Kojto 90:cb3d968589d8 3917 /* */
Kojto 90:cb3d968589d8 3918 /* System Configuration (SYSCFG) */
Kojto 90:cb3d968589d8 3919 /* */
Kojto 90:cb3d968589d8 3920 /*****************************************************************************/
Kojto 90:cb3d968589d8 3921 /***************** Bit definition for SYSCFG_CFGR1 register ****************/
Kojto 122:f9eeca106725 3922 #define SYSCFG_CFGR1_MEM_MODE_Pos (0U)
Kojto 122:f9eeca106725 3923 #define SYSCFG_CFGR1_MEM_MODE_Msk (0x3U << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */
Kojto 122:f9eeca106725 3924 #define SYSCFG_CFGR1_MEM_MODE SYSCFG_CFGR1_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
Kojto 122:f9eeca106725 3925 #define SYSCFG_CFGR1_MEM_MODE_0 (0x1U << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 3926 #define SYSCFG_CFGR1_MEM_MODE_1 (0x2U << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 3927
Kojto 122:f9eeca106725 3928 #define SYSCFG_CFGR1_DMA_RMP_Pos (8U)
Kojto 122:f9eeca106725 3929 #define SYSCFG_CFGR1_DMA_RMP_Msk (0x1FU << SYSCFG_CFGR1_DMA_RMP_Pos) /*!< 0x00001F00 */
Kojto 122:f9eeca106725 3930 #define SYSCFG_CFGR1_DMA_RMP SYSCFG_CFGR1_DMA_RMP_Msk /*!< DMA remap mask */
Kojto 122:f9eeca106725 3931 #define SYSCFG_CFGR1_ADC_DMA_RMP_Pos (8U)
Kojto 122:f9eeca106725 3932 #define SYSCFG_CFGR1_ADC_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_ADC_DMA_RMP_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 3933 #define SYSCFG_CFGR1_ADC_DMA_RMP SYSCFG_CFGR1_ADC_DMA_RMP_Msk /*!< ADC DMA remap */
Kojto 122:f9eeca106725 3934 #define SYSCFG_CFGR1_USART1TX_DMA_RMP_Pos (9U)
Kojto 122:f9eeca106725 3935 #define SYSCFG_CFGR1_USART1TX_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_USART1TX_DMA_RMP_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 3936 #define SYSCFG_CFGR1_USART1TX_DMA_RMP SYSCFG_CFGR1_USART1TX_DMA_RMP_Msk /*!< USART1 TX DMA remap */
Kojto 122:f9eeca106725 3937 #define SYSCFG_CFGR1_USART1RX_DMA_RMP_Pos (10U)
Kojto 122:f9eeca106725 3938 #define SYSCFG_CFGR1_USART1RX_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_USART1RX_DMA_RMP_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 3939 #define SYSCFG_CFGR1_USART1RX_DMA_RMP SYSCFG_CFGR1_USART1RX_DMA_RMP_Msk /*!< USART1 RX DMA remap */
Kojto 122:f9eeca106725 3940 #define SYSCFG_CFGR1_TIM16_DMA_RMP_Pos (11U)
Kojto 122:f9eeca106725 3941 #define SYSCFG_CFGR1_TIM16_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_TIM16_DMA_RMP_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 3942 #define SYSCFG_CFGR1_TIM16_DMA_RMP SYSCFG_CFGR1_TIM16_DMA_RMP_Msk /*!< Timer 16 DMA remap */
Kojto 122:f9eeca106725 3943 #define SYSCFG_CFGR1_TIM17_DMA_RMP_Pos (12U)
Kojto 122:f9eeca106725 3944 #define SYSCFG_CFGR1_TIM17_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_TIM17_DMA_RMP_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 3945 #define SYSCFG_CFGR1_TIM17_DMA_RMP SYSCFG_CFGR1_TIM17_DMA_RMP_Msk /*!< Timer 17 DMA remap */
Kojto 122:f9eeca106725 3946
Kojto 122:f9eeca106725 3947 #define SYSCFG_CFGR1_I2C_FMP_PB6_Pos (16U)
Kojto 122:f9eeca106725 3948 #define SYSCFG_CFGR1_I2C_FMP_PB6_Msk (0x1U << SYSCFG_CFGR1_I2C_FMP_PB6_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 3949 #define SYSCFG_CFGR1_I2C_FMP_PB6 SYSCFG_CFGR1_I2C_FMP_PB6_Msk /*!< I2C PB6 Fast mode plus */
Kojto 122:f9eeca106725 3950 #define SYSCFG_CFGR1_I2C_FMP_PB7_Pos (17U)
Kojto 122:f9eeca106725 3951 #define SYSCFG_CFGR1_I2C_FMP_PB7_Msk (0x1U << SYSCFG_CFGR1_I2C_FMP_PB7_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 3952 #define SYSCFG_CFGR1_I2C_FMP_PB7 SYSCFG_CFGR1_I2C_FMP_PB7_Msk /*!< I2C PB7 Fast mode plus */
Kojto 122:f9eeca106725 3953 #define SYSCFG_CFGR1_I2C_FMP_PB8_Pos (18U)
Kojto 122:f9eeca106725 3954 #define SYSCFG_CFGR1_I2C_FMP_PB8_Msk (0x1U << SYSCFG_CFGR1_I2C_FMP_PB8_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 3955 #define SYSCFG_CFGR1_I2C_FMP_PB8 SYSCFG_CFGR1_I2C_FMP_PB8_Msk /*!< I2C PB8 Fast mode plus */
Kojto 122:f9eeca106725 3956 #define SYSCFG_CFGR1_I2C_FMP_PB9_Pos (19U)
Kojto 122:f9eeca106725 3957 #define SYSCFG_CFGR1_I2C_FMP_PB9_Msk (0x1U << SYSCFG_CFGR1_I2C_FMP_PB9_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 3958 #define SYSCFG_CFGR1_I2C_FMP_PB9 SYSCFG_CFGR1_I2C_FMP_PB9_Msk /*!< I2C PB9 Fast mode plus */
Kojto 108:34e6b704fe68 3959
Kojto 90:cb3d968589d8 3960 /***************** Bit definition for SYSCFG_EXTICR1 register **************/
Kojto 122:f9eeca106725 3961 #define SYSCFG_EXTICR1_EXTI0_Pos (0U)
Kojto 122:f9eeca106725 3962 #define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 3963 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */
Kojto 122:f9eeca106725 3964 #define SYSCFG_EXTICR1_EXTI1_Pos (4U)
Kojto 122:f9eeca106725 3965 #define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
Kojto 122:f9eeca106725 3966 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */
Kojto 122:f9eeca106725 3967 #define SYSCFG_EXTICR1_EXTI2_Pos (8U)
Kojto 122:f9eeca106725 3968 #define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
Kojto 122:f9eeca106725 3969 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */
Kojto 122:f9eeca106725 3970 #define SYSCFG_EXTICR1_EXTI3_Pos (12U)
Kojto 122:f9eeca106725 3971 #define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
Kojto 122:f9eeca106725 3972 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
Kojto 90:cb3d968589d8 3973
Kojto 90:cb3d968589d8 3974 /**
Kojto 90:cb3d968589d8 3975 * @brief EXTI0 configuration
Kojto 90:cb3d968589d8 3976 */
Kojto 122:f9eeca106725 3977 #define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!< PA[0] pin */
Kojto 122:f9eeca106725 3978 #define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!< PB[0] pin */
Kojto 122:f9eeca106725 3979 #define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!< PC[0] pin */
Kojto 122:f9eeca106725 3980 #define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!< PD[0] pin */
Kojto 122:f9eeca106725 3981 #define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!< PF[0] pin */
Kojto 90:cb3d968589d8 3982
Kojto 90:cb3d968589d8 3983 /**
Kojto 90:cb3d968589d8 3984 * @brief EXTI1 configuration
Kojto 90:cb3d968589d8 3985 */
Kojto 122:f9eeca106725 3986 #define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!< PA[1] pin */
Kojto 122:f9eeca106725 3987 #define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!< PB[1] pin */
Kojto 122:f9eeca106725 3988 #define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!< PC[1] pin */
Kojto 122:f9eeca106725 3989 #define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!< PD[1] pin */
Kojto 122:f9eeca106725 3990 #define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!< PF[1] pin */
Kojto 90:cb3d968589d8 3991
Kojto 90:cb3d968589d8 3992 /**
Kojto 90:cb3d968589d8 3993 * @brief EXTI2 configuration
Kojto 90:cb3d968589d8 3994 */
Kojto 122:f9eeca106725 3995 #define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!< PA[2] pin */
Kojto 122:f9eeca106725 3996 #define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!< PB[2] pin */
Kojto 122:f9eeca106725 3997 #define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!< PC[2] pin */
Kojto 122:f9eeca106725 3998 #define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!< PD[2] pin */
Kojto 122:f9eeca106725 3999 #define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!< PF[2] pin */
Kojto 90:cb3d968589d8 4000
Kojto 90:cb3d968589d8 4001 /**
Kojto 90:cb3d968589d8 4002 * @brief EXTI3 configuration
Kojto 90:cb3d968589d8 4003 */
Kojto 122:f9eeca106725 4004 #define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!< PA[3] pin */
Kojto 122:f9eeca106725 4005 #define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!< PB[3] pin */
Kojto 122:f9eeca106725 4006 #define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */
Kojto 122:f9eeca106725 4007 #define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!< PD[3] pin */
Kojto 122:f9eeca106725 4008 #define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!< PF[3] pin */
Kojto 90:cb3d968589d8 4009
Kojto 90:cb3d968589d8 4010 /***************** Bit definition for SYSCFG_EXTICR2 register **************/
Kojto 122:f9eeca106725 4011 #define SYSCFG_EXTICR2_EXTI4_Pos (0U)
Kojto 122:f9eeca106725 4012 #define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 4013 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */
Kojto 122:f9eeca106725 4014 #define SYSCFG_EXTICR2_EXTI5_Pos (4U)
Kojto 122:f9eeca106725 4015 #define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
Kojto 122:f9eeca106725 4016 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */
Kojto 122:f9eeca106725 4017 #define SYSCFG_EXTICR2_EXTI6_Pos (8U)
Kojto 122:f9eeca106725 4018 #define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
Kojto 122:f9eeca106725 4019 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */
Kojto 122:f9eeca106725 4020 #define SYSCFG_EXTICR2_EXTI7_Pos (12U)
Kojto 122:f9eeca106725 4021 #define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
Kojto 122:f9eeca106725 4022 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
Kojto 90:cb3d968589d8 4023
Kojto 90:cb3d968589d8 4024 /**
Kojto 90:cb3d968589d8 4025 * @brief EXTI4 configuration
Kojto 90:cb3d968589d8 4026 */
Kojto 122:f9eeca106725 4027 #define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!< PA[4] pin */
Kojto 122:f9eeca106725 4028 #define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!< PB[4] pin */
Kojto 122:f9eeca106725 4029 #define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!< PC[4] pin */
Kojto 122:f9eeca106725 4030 #define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!< PD[4] pin */
Kojto 122:f9eeca106725 4031 #define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!< PF[4] pin */
Kojto 90:cb3d968589d8 4032
Kojto 90:cb3d968589d8 4033 /**
Kojto 90:cb3d968589d8 4034 * @brief EXTI5 configuration
Kojto 90:cb3d968589d8 4035 */
Kojto 122:f9eeca106725 4036 #define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!< PA[5] pin */
Kojto 122:f9eeca106725 4037 #define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!< PB[5] pin */
Kojto 122:f9eeca106725 4038 #define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!< PC[5] pin */
Kojto 122:f9eeca106725 4039 #define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!< PD[5] pin */
Kojto 122:f9eeca106725 4040 #define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!< PF[5] pin */
Kojto 90:cb3d968589d8 4041
Kojto 90:cb3d968589d8 4042 /**
Kojto 90:cb3d968589d8 4043 * @brief EXTI6 configuration
Kojto 90:cb3d968589d8 4044 */
Kojto 122:f9eeca106725 4045 #define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!< PA[6] pin */
Kojto 122:f9eeca106725 4046 #define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!< PB[6] pin */
Kojto 122:f9eeca106725 4047 #define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!< PC[6] pin */
Kojto 122:f9eeca106725 4048 #define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!< PD[6] pin */
Kojto 122:f9eeca106725 4049 #define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!< PF[6] pin */
Kojto 90:cb3d968589d8 4050
Kojto 90:cb3d968589d8 4051 /**
Kojto 90:cb3d968589d8 4052 * @brief EXTI7 configuration
Kojto 90:cb3d968589d8 4053 */
Kojto 122:f9eeca106725 4054 #define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!< PA[7] pin */
Kojto 122:f9eeca106725 4055 #define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!< PB[7] pin */
Kojto 122:f9eeca106725 4056 #define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!< PC[7] pin */
Kojto 122:f9eeca106725 4057 #define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!< PD[7] pin */
Kojto 122:f9eeca106725 4058 #define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!< PF[7] pin */
Kojto 90:cb3d968589d8 4059
Kojto 90:cb3d968589d8 4060 /***************** Bit definition for SYSCFG_EXTICR3 register **************/
Kojto 122:f9eeca106725 4061 #define SYSCFG_EXTICR3_EXTI8_Pos (0U)
Kojto 122:f9eeca106725 4062 #define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 4063 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */
Kojto 122:f9eeca106725 4064 #define SYSCFG_EXTICR3_EXTI9_Pos (4U)
Kojto 122:f9eeca106725 4065 #define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
Kojto 122:f9eeca106725 4066 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */
Kojto 122:f9eeca106725 4067 #define SYSCFG_EXTICR3_EXTI10_Pos (8U)
Kojto 122:f9eeca106725 4068 #define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
Kojto 122:f9eeca106725 4069 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */
Kojto 122:f9eeca106725 4070 #define SYSCFG_EXTICR3_EXTI11_Pos (12U)
Kojto 122:f9eeca106725 4071 #define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
Kojto 122:f9eeca106725 4072 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
Kojto 90:cb3d968589d8 4073
Kojto 90:cb3d968589d8 4074 /**
Kojto 90:cb3d968589d8 4075 * @brief EXTI8 configuration
Kojto 90:cb3d968589d8 4076 */
Kojto 122:f9eeca106725 4077 #define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!< PA[8] pin */
Kojto 122:f9eeca106725 4078 #define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!< PB[8] pin */
Kojto 122:f9eeca106725 4079 #define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!< PC[8] pin */
Kojto 122:f9eeca106725 4080 #define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!< PD[8] pin */
Kojto 122:f9eeca106725 4081 #define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!< PF[8] pin */
Kojto 122:f9eeca106725 4082
Kojto 90:cb3d968589d8 4083
Kojto 90:cb3d968589d8 4084 /**
Kojto 90:cb3d968589d8 4085 * @brief EXTI9 configuration
Kojto 90:cb3d968589d8 4086 */
Kojto 122:f9eeca106725 4087 #define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!< PA[9] pin */
Kojto 122:f9eeca106725 4088 #define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!< PB[9] pin */
Kojto 122:f9eeca106725 4089 #define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!< PC[9] pin */
Kojto 122:f9eeca106725 4090 #define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!< PD[9] pin */
Kojto 122:f9eeca106725 4091 #define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!< PF[9] pin */
Kojto 90:cb3d968589d8 4092
Kojto 90:cb3d968589d8 4093 /**
Kojto 90:cb3d968589d8 4094 * @brief EXTI10 configuration
Kojto 90:cb3d968589d8 4095 */
Kojto 122:f9eeca106725 4096 #define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!< PA[10] pin */
Kojto 122:f9eeca106725 4097 #define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!< PB[10] pin */
Kojto 122:f9eeca106725 4098 #define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!< PC[10] pin */
Kojto 122:f9eeca106725 4099 #define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!< PD[10] pin */
Kojto 122:f9eeca106725 4100 #define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!< PF[10] pin */
Kojto 90:cb3d968589d8 4101
Kojto 90:cb3d968589d8 4102 /**
Kojto 90:cb3d968589d8 4103 * @brief EXTI11 configuration
Kojto 90:cb3d968589d8 4104 */
Kojto 122:f9eeca106725 4105 #define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!< PA[11] pin */
Kojto 122:f9eeca106725 4106 #define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!< PB[11] pin */
Kojto 122:f9eeca106725 4107 #define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!< PC[11] pin */
Kojto 122:f9eeca106725 4108 #define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!< PD[11] pin */
Kojto 122:f9eeca106725 4109 #define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!< PF[11] pin */
Kojto 90:cb3d968589d8 4110
Kojto 90:cb3d968589d8 4111 /***************** Bit definition for SYSCFG_EXTICR4 register **************/
Kojto 122:f9eeca106725 4112 #define SYSCFG_EXTICR4_EXTI12_Pos (0U)
Kojto 122:f9eeca106725 4113 #define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 4114 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */
Kojto 122:f9eeca106725 4115 #define SYSCFG_EXTICR4_EXTI13_Pos (4U)
Kojto 122:f9eeca106725 4116 #define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
Kojto 122:f9eeca106725 4117 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */
Kojto 122:f9eeca106725 4118 #define SYSCFG_EXTICR4_EXTI14_Pos (8U)
Kojto 122:f9eeca106725 4119 #define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
Kojto 122:f9eeca106725 4120 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */
Kojto 122:f9eeca106725 4121 #define SYSCFG_EXTICR4_EXTI15_Pos (12U)
Kojto 122:f9eeca106725 4122 #define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
Kojto 122:f9eeca106725 4123 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
Kojto 90:cb3d968589d8 4124
Kojto 90:cb3d968589d8 4125 /**
Kojto 90:cb3d968589d8 4126 * @brief EXTI12 configuration
Kojto 90:cb3d968589d8 4127 */
Kojto 122:f9eeca106725 4128 #define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!< PA[12] pin */
Kojto 122:f9eeca106725 4129 #define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!< PB[12] pin */
Kojto 122:f9eeca106725 4130 #define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!< PC[12] pin */
Kojto 122:f9eeca106725 4131 #define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!< PD[12] pin */
Kojto 122:f9eeca106725 4132 #define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!< PF[12] pin */
Kojto 90:cb3d968589d8 4133
Kojto 90:cb3d968589d8 4134 /**
Kojto 90:cb3d968589d8 4135 * @brief EXTI13 configuration
Kojto 90:cb3d968589d8 4136 */
Kojto 122:f9eeca106725 4137 #define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!< PA[13] pin */
Kojto 122:f9eeca106725 4138 #define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!< PB[13] pin */
Kojto 122:f9eeca106725 4139 #define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!< PC[13] pin */
Kojto 122:f9eeca106725 4140 #define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!< PD[13] pin */
Kojto 122:f9eeca106725 4141 #define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!< PF[13] pin */
Kojto 90:cb3d968589d8 4142
Kojto 90:cb3d968589d8 4143 /**
Kojto 90:cb3d968589d8 4144 * @brief EXTI14 configuration
Kojto 90:cb3d968589d8 4145 */
Kojto 122:f9eeca106725 4146 #define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!< PA[14] pin */
Kojto 122:f9eeca106725 4147 #define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!< PB[14] pin */
Kojto 122:f9eeca106725 4148 #define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!< PC[14] pin */
Kojto 122:f9eeca106725 4149 #define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!< PD[14] pin */
Kojto 122:f9eeca106725 4150 #define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!< PF[14] pin */
Kojto 90:cb3d968589d8 4151
Kojto 90:cb3d968589d8 4152 /**
Kojto 90:cb3d968589d8 4153 * @brief EXTI15 configuration
Kojto 90:cb3d968589d8 4154 */
Kojto 122:f9eeca106725 4155 #define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!< PA[15] pin */
Kojto 122:f9eeca106725 4156 #define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!< PB[15] pin */
Kojto 122:f9eeca106725 4157 #define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!< PC[15] pin */
Kojto 122:f9eeca106725 4158 #define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!< PD[15] pin */
Kojto 122:f9eeca106725 4159 #define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!< PF[15] pin */
Kojto 90:cb3d968589d8 4160
Kojto 90:cb3d968589d8 4161 /***************** Bit definition for SYSCFG_CFGR2 register ****************/
Kojto 122:f9eeca106725 4162 #define SYSCFG_CFGR2_LOCKUP_LOCK_Pos (0U)
Kojto 122:f9eeca106725 4163 #define SYSCFG_CFGR2_LOCKUP_LOCK_Msk (0x1U << SYSCFG_CFGR2_LOCKUP_LOCK_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 4164 #define SYSCFG_CFGR2_LOCKUP_LOCK SYSCFG_CFGR2_LOCKUP_LOCK_Msk /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */
Kojto 122:f9eeca106725 4165 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK_Pos (1U)
Kojto 122:f9eeca106725 4166 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK_Msk (0x1U << SYSCFG_CFGR2_SRAM_PARITY_LOCK_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 4167 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK SYSCFG_CFGR2_SRAM_PARITY_LOCK_Msk /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 */
Kojto 122:f9eeca106725 4168 #define SYSCFG_CFGR2_SRAM_PEF_Pos (8U)
Kojto 122:f9eeca106725 4169 #define SYSCFG_CFGR2_SRAM_PEF_Msk (0x1U << SYSCFG_CFGR2_SRAM_PEF_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 4170 #define SYSCFG_CFGR2_SRAM_PEF SYSCFG_CFGR2_SRAM_PEF_Msk /*!< SRAM Parity error flag */
Kojto 122:f9eeca106725 4171 #define SYSCFG_CFGR2_SRAM_PE SYSCFG_CFGR2_SRAM_PEF /*!< SRAM Parity error flag (define maintained for legacy purpose) */
Kojto 90:cb3d968589d8 4172
Kojto 90:cb3d968589d8 4173 /*****************************************************************************/
Kojto 90:cb3d968589d8 4174 /* */
Kojto 90:cb3d968589d8 4175 /* Timers (TIM) */
Kojto 90:cb3d968589d8 4176 /* */
Kojto 90:cb3d968589d8 4177 /*****************************************************************************/
Kojto 90:cb3d968589d8 4178 /******************* Bit definition for TIM_CR1 register *******************/
Kojto 122:f9eeca106725 4179 #define TIM_CR1_CEN_Pos (0U)
Kojto 122:f9eeca106725 4180 #define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 4181 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
Kojto 122:f9eeca106725 4182 #define TIM_CR1_UDIS_Pos (1U)
Kojto 122:f9eeca106725 4183 #define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 4184 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
Kojto 122:f9eeca106725 4185 #define TIM_CR1_URS_Pos (2U)
Kojto 122:f9eeca106725 4186 #define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 4187 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
Kojto 122:f9eeca106725 4188 #define TIM_CR1_OPM_Pos (3U)
Kojto 122:f9eeca106725 4189 #define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 4190 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
Kojto 122:f9eeca106725 4191 #define TIM_CR1_DIR_Pos (4U)
Kojto 122:f9eeca106725 4192 #define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 4193 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
Kojto 122:f9eeca106725 4194
Kojto 122:f9eeca106725 4195 #define TIM_CR1_CMS_Pos (5U)
Kojto 122:f9eeca106725 4196 #define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
Kojto 122:f9eeca106725 4197 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
Kojto 122:f9eeca106725 4198 #define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 4199 #define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 4200
Kojto 122:f9eeca106725 4201 #define TIM_CR1_ARPE_Pos (7U)
Kojto 122:f9eeca106725 4202 #define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 4203 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
Kojto 122:f9eeca106725 4204
Kojto 122:f9eeca106725 4205 #define TIM_CR1_CKD_Pos (8U)
Kojto 122:f9eeca106725 4206 #define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
Kojto 122:f9eeca106725 4207 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
Kojto 122:f9eeca106725 4208 #define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 4209 #define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
Kojto 90:cb3d968589d8 4210
Kojto 90:cb3d968589d8 4211 /******************* Bit definition for TIM_CR2 register *******************/
Kojto 122:f9eeca106725 4212 #define TIM_CR2_CCPC_Pos (0U)
Kojto 122:f9eeca106725 4213 #define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 4214 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
Kojto 122:f9eeca106725 4215 #define TIM_CR2_CCUS_Pos (2U)
Kojto 122:f9eeca106725 4216 #define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 4217 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
Kojto 122:f9eeca106725 4218 #define TIM_CR2_CCDS_Pos (3U)
Kojto 122:f9eeca106725 4219 #define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 4220 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
Kojto 122:f9eeca106725 4221
Kojto 122:f9eeca106725 4222 #define TIM_CR2_MMS_Pos (4U)
Kojto 122:f9eeca106725 4223 #define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
Kojto 122:f9eeca106725 4224 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
Kojto 122:f9eeca106725 4225 #define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 4226 #define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 4227 #define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 4228
Kojto 122:f9eeca106725 4229 #define TIM_CR2_TI1S_Pos (7U)
Kojto 122:f9eeca106725 4230 #define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 4231 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
Kojto 122:f9eeca106725 4232 #define TIM_CR2_OIS1_Pos (8U)
Kojto 122:f9eeca106725 4233 #define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 4234 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
Kojto 122:f9eeca106725 4235 #define TIM_CR2_OIS1N_Pos (9U)
Kojto 122:f9eeca106725 4236 #define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 4237 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
Kojto 122:f9eeca106725 4238 #define TIM_CR2_OIS2_Pos (10U)
Kojto 122:f9eeca106725 4239 #define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 4240 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
Kojto 122:f9eeca106725 4241 #define TIM_CR2_OIS2N_Pos (11U)
Kojto 122:f9eeca106725 4242 #define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 4243 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
Kojto 122:f9eeca106725 4244 #define TIM_CR2_OIS3_Pos (12U)
Kojto 122:f9eeca106725 4245 #define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 4246 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
Kojto 122:f9eeca106725 4247 #define TIM_CR2_OIS3N_Pos (13U)
Kojto 122:f9eeca106725 4248 #define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 4249 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
Kojto 122:f9eeca106725 4250 #define TIM_CR2_OIS4_Pos (14U)
Kojto 122:f9eeca106725 4251 #define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 4252 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
Kojto 90:cb3d968589d8 4253
Kojto 90:cb3d968589d8 4254 /******************* Bit definition for TIM_SMCR register ******************/
Kojto 122:f9eeca106725 4255 #define TIM_SMCR_SMS_Pos (0U)
Kojto 122:f9eeca106725 4256 #define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
Kojto 122:f9eeca106725 4257 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
Kojto 122:f9eeca106725 4258 #define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 4259 #define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 4260 #define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 4261
Kojto 122:f9eeca106725 4262 #define TIM_SMCR_OCCS_Pos (3U)
Kojto 122:f9eeca106725 4263 #define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 4264 #define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
Kojto 122:f9eeca106725 4265
Kojto 122:f9eeca106725 4266 #define TIM_SMCR_TS_Pos (4U)
Kojto 122:f9eeca106725 4267 #define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
Kojto 122:f9eeca106725 4268 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
Kojto 122:f9eeca106725 4269 #define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 4270 #define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 4271 #define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 4272
Kojto 122:f9eeca106725 4273 #define TIM_SMCR_MSM_Pos (7U)
Kojto 122:f9eeca106725 4274 #define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 4275 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
Kojto 122:f9eeca106725 4276
Kojto 122:f9eeca106725 4277 #define TIM_SMCR_ETF_Pos (8U)
Kojto 122:f9eeca106725 4278 #define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
Kojto 122:f9eeca106725 4279 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
Kojto 122:f9eeca106725 4280 #define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 4281 #define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 4282 #define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 4283 #define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 4284
Kojto 122:f9eeca106725 4285 #define TIM_SMCR_ETPS_Pos (12U)
Kojto 122:f9eeca106725 4286 #define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
Kojto 122:f9eeca106725 4287 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
Kojto 122:f9eeca106725 4288 #define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 4289 #define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 4290
Kojto 122:f9eeca106725 4291 #define TIM_SMCR_ECE_Pos (14U)
Kojto 122:f9eeca106725 4292 #define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 4293 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
Kojto 122:f9eeca106725 4294 #define TIM_SMCR_ETP_Pos (15U)
Kojto 122:f9eeca106725 4295 #define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 4296 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
Kojto 90:cb3d968589d8 4297
Kojto 90:cb3d968589d8 4298 /******************* Bit definition for TIM_DIER register ******************/
Kojto 122:f9eeca106725 4299 #define TIM_DIER_UIE_Pos (0U)
Kojto 122:f9eeca106725 4300 #define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 4301 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
Kojto 122:f9eeca106725 4302 #define TIM_DIER_CC1IE_Pos (1U)
Kojto 122:f9eeca106725 4303 #define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 4304 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
Kojto 122:f9eeca106725 4305 #define TIM_DIER_CC2IE_Pos (2U)
Kojto 122:f9eeca106725 4306 #define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 4307 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
Kojto 122:f9eeca106725 4308 #define TIM_DIER_CC3IE_Pos (3U)
Kojto 122:f9eeca106725 4309 #define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 4310 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
Kojto 122:f9eeca106725 4311 #define TIM_DIER_CC4IE_Pos (4U)
Kojto 122:f9eeca106725 4312 #define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 4313 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
Kojto 122:f9eeca106725 4314 #define TIM_DIER_COMIE_Pos (5U)
Kojto 122:f9eeca106725 4315 #define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 4316 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
Kojto 122:f9eeca106725 4317 #define TIM_DIER_TIE_Pos (6U)
Kojto 122:f9eeca106725 4318 #define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 4319 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
Kojto 122:f9eeca106725 4320 #define TIM_DIER_BIE_Pos (7U)
Kojto 122:f9eeca106725 4321 #define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 4322 #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
Kojto 122:f9eeca106725 4323 #define TIM_DIER_UDE_Pos (8U)
Kojto 122:f9eeca106725 4324 #define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 4325 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
Kojto 122:f9eeca106725 4326 #define TIM_DIER_CC1DE_Pos (9U)
Kojto 122:f9eeca106725 4327 #define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 4328 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
Kojto 122:f9eeca106725 4329 #define TIM_DIER_CC2DE_Pos (10U)
Kojto 122:f9eeca106725 4330 #define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 4331 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
Kojto 122:f9eeca106725 4332 #define TIM_DIER_CC3DE_Pos (11U)
Kojto 122:f9eeca106725 4333 #define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 4334 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
Kojto 122:f9eeca106725 4335 #define TIM_DIER_CC4DE_Pos (12U)
Kojto 122:f9eeca106725 4336 #define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 4337 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
Kojto 122:f9eeca106725 4338 #define TIM_DIER_COMDE_Pos (13U)
Kojto 122:f9eeca106725 4339 #define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 4340 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
Kojto 122:f9eeca106725 4341 #define TIM_DIER_TDE_Pos (14U)
Kojto 122:f9eeca106725 4342 #define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 4343 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
Kojto 90:cb3d968589d8 4344
Kojto 90:cb3d968589d8 4345 /******************** Bit definition for TIM_SR register *******************/
Kojto 122:f9eeca106725 4346 #define TIM_SR_UIF_Pos (0U)
Kojto 122:f9eeca106725 4347 #define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 4348 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
Kojto 122:f9eeca106725 4349 #define TIM_SR_CC1IF_Pos (1U)
Kojto 122:f9eeca106725 4350 #define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 4351 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
Kojto 122:f9eeca106725 4352 #define TIM_SR_CC2IF_Pos (2U)
Kojto 122:f9eeca106725 4353 #define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 4354 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
Kojto 122:f9eeca106725 4355 #define TIM_SR_CC3IF_Pos (3U)
Kojto 122:f9eeca106725 4356 #define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 4357 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
Kojto 122:f9eeca106725 4358 #define TIM_SR_CC4IF_Pos (4U)
Kojto 122:f9eeca106725 4359 #define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 4360 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
Kojto 122:f9eeca106725 4361 #define TIM_SR_COMIF_Pos (5U)
Kojto 122:f9eeca106725 4362 #define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 4363 #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
Kojto 122:f9eeca106725 4364 #define TIM_SR_TIF_Pos (6U)
Kojto 122:f9eeca106725 4365 #define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 4366 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
Kojto 122:f9eeca106725 4367 #define TIM_SR_BIF_Pos (7U)
Kojto 122:f9eeca106725 4368 #define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 4369 #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
Kojto 122:f9eeca106725 4370 #define TIM_SR_CC1OF_Pos (9U)
Kojto 122:f9eeca106725 4371 #define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 4372 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
Kojto 122:f9eeca106725 4373 #define TIM_SR_CC2OF_Pos (10U)
Kojto 122:f9eeca106725 4374 #define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 4375 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
Kojto 122:f9eeca106725 4376 #define TIM_SR_CC3OF_Pos (11U)
Kojto 122:f9eeca106725 4377 #define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 4378 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
Kojto 122:f9eeca106725 4379 #define TIM_SR_CC4OF_Pos (12U)
Kojto 122:f9eeca106725 4380 #define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 4381 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
Kojto 90:cb3d968589d8 4382
Kojto 90:cb3d968589d8 4383 /******************* Bit definition for TIM_EGR register *******************/
Kojto 122:f9eeca106725 4384 #define TIM_EGR_UG_Pos (0U)
Kojto 122:f9eeca106725 4385 #define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 4386 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
Kojto 122:f9eeca106725 4387 #define TIM_EGR_CC1G_Pos (1U)
Kojto 122:f9eeca106725 4388 #define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 4389 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
Kojto 122:f9eeca106725 4390 #define TIM_EGR_CC2G_Pos (2U)
Kojto 122:f9eeca106725 4391 #define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 4392 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
Kojto 122:f9eeca106725 4393 #define TIM_EGR_CC3G_Pos (3U)
Kojto 122:f9eeca106725 4394 #define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 4395 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
Kojto 122:f9eeca106725 4396 #define TIM_EGR_CC4G_Pos (4U)
Kojto 122:f9eeca106725 4397 #define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 4398 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
Kojto 122:f9eeca106725 4399 #define TIM_EGR_COMG_Pos (5U)
Kojto 122:f9eeca106725 4400 #define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 4401 #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
Kojto 122:f9eeca106725 4402 #define TIM_EGR_TG_Pos (6U)
Kojto 122:f9eeca106725 4403 #define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 4404 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
Kojto 122:f9eeca106725 4405 #define TIM_EGR_BG_Pos (7U)
Kojto 122:f9eeca106725 4406 #define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 4407 #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
Kojto 90:cb3d968589d8 4408
Kojto 90:cb3d968589d8 4409 /****************** Bit definition for TIM_CCMR1 register ******************/
Kojto 122:f9eeca106725 4410 #define TIM_CCMR1_CC1S_Pos (0U)
Kojto 122:f9eeca106725 4411 #define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
Kojto 122:f9eeca106725 4412 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
Kojto 122:f9eeca106725 4413 #define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 4414 #define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 4415
Kojto 122:f9eeca106725 4416 #define TIM_CCMR1_OC1FE_Pos (2U)
Kojto 122:f9eeca106725 4417 #define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 4418 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
Kojto 122:f9eeca106725 4419 #define TIM_CCMR1_OC1PE_Pos (3U)
Kojto 122:f9eeca106725 4420 #define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 4421 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
Kojto 122:f9eeca106725 4422
Kojto 122:f9eeca106725 4423 #define TIM_CCMR1_OC1M_Pos (4U)
Kojto 122:f9eeca106725 4424 #define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
Kojto 122:f9eeca106725 4425 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
Kojto 122:f9eeca106725 4426 #define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 4427 #define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 4428 #define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 4429
Kojto 122:f9eeca106725 4430 #define TIM_CCMR1_OC1CE_Pos (7U)
Kojto 122:f9eeca106725 4431 #define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 4432 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
Kojto 122:f9eeca106725 4433
Kojto 122:f9eeca106725 4434 #define TIM_CCMR1_CC2S_Pos (8U)
Kojto 122:f9eeca106725 4435 #define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
Kojto 122:f9eeca106725 4436 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
Kojto 122:f9eeca106725 4437 #define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 4438 #define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 4439
Kojto 122:f9eeca106725 4440 #define TIM_CCMR1_OC2FE_Pos (10U)
Kojto 122:f9eeca106725 4441 #define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 4442 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
Kojto 122:f9eeca106725 4443 #define TIM_CCMR1_OC2PE_Pos (11U)
Kojto 122:f9eeca106725 4444 #define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 4445 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
Kojto 122:f9eeca106725 4446
Kojto 122:f9eeca106725 4447 #define TIM_CCMR1_OC2M_Pos (12U)
Kojto 122:f9eeca106725 4448 #define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
Kojto 122:f9eeca106725 4449 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
Kojto 122:f9eeca106725 4450 #define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 4451 #define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 4452 #define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 4453
Kojto 122:f9eeca106725 4454 #define TIM_CCMR1_OC2CE_Pos (15U)
Kojto 122:f9eeca106725 4455 #define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 4456 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
Kojto 90:cb3d968589d8 4457
Kojto 90:cb3d968589d8 4458 /*---------------------------------------------------------------------------*/
Kojto 90:cb3d968589d8 4459
Kojto 122:f9eeca106725 4460 #define TIM_CCMR1_IC1PSC_Pos (2U)
Kojto 122:f9eeca106725 4461 #define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
Kojto 122:f9eeca106725 4462 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
Kojto 122:f9eeca106725 4463 #define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 4464 #define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 4465
Kojto 122:f9eeca106725 4466 #define TIM_CCMR1_IC1F_Pos (4U)
Kojto 122:f9eeca106725 4467 #define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
Kojto 122:f9eeca106725 4468 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
Kojto 122:f9eeca106725 4469 #define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 4470 #define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 4471 #define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 4472 #define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 4473
Kojto 122:f9eeca106725 4474 #define TIM_CCMR1_IC2PSC_Pos (10U)
Kojto 122:f9eeca106725 4475 #define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
Kojto 122:f9eeca106725 4476 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
Kojto 122:f9eeca106725 4477 #define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 4478 #define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 4479
Kojto 122:f9eeca106725 4480 #define TIM_CCMR1_IC2F_Pos (12U)
Kojto 122:f9eeca106725 4481 #define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
Kojto 122:f9eeca106725 4482 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
Kojto 122:f9eeca106725 4483 #define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 4484 #define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 4485 #define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 4486 #define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
Kojto 90:cb3d968589d8 4487
Kojto 90:cb3d968589d8 4488 /****************** Bit definition for TIM_CCMR2 register ******************/
Kojto 122:f9eeca106725 4489 #define TIM_CCMR2_CC3S_Pos (0U)
Kojto 122:f9eeca106725 4490 #define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
Kojto 122:f9eeca106725 4491 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
Kojto 122:f9eeca106725 4492 #define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 4493 #define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 4494
Kojto 122:f9eeca106725 4495 #define TIM_CCMR2_OC3FE_Pos (2U)
Kojto 122:f9eeca106725 4496 #define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 4497 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
Kojto 122:f9eeca106725 4498 #define TIM_CCMR2_OC3PE_Pos (3U)
Kojto 122:f9eeca106725 4499 #define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 4500 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
Kojto 122:f9eeca106725 4501
Kojto 122:f9eeca106725 4502 #define TIM_CCMR2_OC3M_Pos (4U)
Kojto 122:f9eeca106725 4503 #define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
Kojto 122:f9eeca106725 4504 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
Kojto 122:f9eeca106725 4505 #define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 4506 #define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 4507 #define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 4508
Kojto 122:f9eeca106725 4509 #define TIM_CCMR2_OC3CE_Pos (7U)
Kojto 122:f9eeca106725 4510 #define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 4511 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
Kojto 122:f9eeca106725 4512
Kojto 122:f9eeca106725 4513 #define TIM_CCMR2_CC4S_Pos (8U)
Kojto 122:f9eeca106725 4514 #define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
Kojto 122:f9eeca106725 4515 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
Kojto 122:f9eeca106725 4516 #define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 4517 #define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 4518
Kojto 122:f9eeca106725 4519 #define TIM_CCMR2_OC4FE_Pos (10U)
Kojto 122:f9eeca106725 4520 #define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 4521 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
Kojto 122:f9eeca106725 4522 #define TIM_CCMR2_OC4PE_Pos (11U)
Kojto 122:f9eeca106725 4523 #define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 4524 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
Kojto 122:f9eeca106725 4525
Kojto 122:f9eeca106725 4526 #define TIM_CCMR2_OC4M_Pos (12U)
Kojto 122:f9eeca106725 4527 #define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
Kojto 122:f9eeca106725 4528 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
Kojto 122:f9eeca106725 4529 #define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 4530 #define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 4531 #define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 4532
Kojto 122:f9eeca106725 4533 #define TIM_CCMR2_OC4CE_Pos (15U)
Kojto 122:f9eeca106725 4534 #define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 4535 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
Kojto 90:cb3d968589d8 4536
Kojto 90:cb3d968589d8 4537 /*---------------------------------------------------------------------------*/
Kojto 90:cb3d968589d8 4538
Kojto 122:f9eeca106725 4539 #define TIM_CCMR2_IC3PSC_Pos (2U)
Kojto 122:f9eeca106725 4540 #define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
Kojto 122:f9eeca106725 4541 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
Kojto 122:f9eeca106725 4542 #define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 4543 #define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 4544
Kojto 122:f9eeca106725 4545 #define TIM_CCMR2_IC3F_Pos (4U)
Kojto 122:f9eeca106725 4546 #define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
Kojto 122:f9eeca106725 4547 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
Kojto 122:f9eeca106725 4548 #define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 4549 #define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 4550 #define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 4551 #define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 4552
Kojto 122:f9eeca106725 4553 #define TIM_CCMR2_IC4PSC_Pos (10U)
Kojto 122:f9eeca106725 4554 #define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
Kojto 122:f9eeca106725 4555 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
Kojto 122:f9eeca106725 4556 #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 4557 #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 4558
Kojto 122:f9eeca106725 4559 #define TIM_CCMR2_IC4F_Pos (12U)
Kojto 122:f9eeca106725 4560 #define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
Kojto 122:f9eeca106725 4561 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
Kojto 122:f9eeca106725 4562 #define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 4563 #define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 4564 #define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 4565 #define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
Kojto 90:cb3d968589d8 4566
Kojto 90:cb3d968589d8 4567 /******************* Bit definition for TIM_CCER register ******************/
Kojto 122:f9eeca106725 4568 #define TIM_CCER_CC1E_Pos (0U)
Kojto 122:f9eeca106725 4569 #define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 4570 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
Kojto 122:f9eeca106725 4571 #define TIM_CCER_CC1P_Pos (1U)
Kojto 122:f9eeca106725 4572 #define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 4573 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
Kojto 122:f9eeca106725 4574 #define TIM_CCER_CC1NE_Pos (2U)
Kojto 122:f9eeca106725 4575 #define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 4576 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
Kojto 122:f9eeca106725 4577 #define TIM_CCER_CC1NP_Pos (3U)
Kojto 122:f9eeca106725 4578 #define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 4579 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
Kojto 122:f9eeca106725 4580 #define TIM_CCER_CC2E_Pos (4U)
Kojto 122:f9eeca106725 4581 #define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 4582 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
Kojto 122:f9eeca106725 4583 #define TIM_CCER_CC2P_Pos (5U)
Kojto 122:f9eeca106725 4584 #define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 4585 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
Kojto 122:f9eeca106725 4586 #define TIM_CCER_CC2NE_Pos (6U)
Kojto 122:f9eeca106725 4587 #define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 4588 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
Kojto 122:f9eeca106725 4589 #define TIM_CCER_CC2NP_Pos (7U)
Kojto 122:f9eeca106725 4590 #define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 4591 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
Kojto 122:f9eeca106725 4592 #define TIM_CCER_CC3E_Pos (8U)
Kojto 122:f9eeca106725 4593 #define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 4594 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
Kojto 122:f9eeca106725 4595 #define TIM_CCER_CC3P_Pos (9U)
Kojto 122:f9eeca106725 4596 #define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 4597 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
Kojto 122:f9eeca106725 4598 #define TIM_CCER_CC3NE_Pos (10U)
Kojto 122:f9eeca106725 4599 #define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 4600 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
Kojto 122:f9eeca106725 4601 #define TIM_CCER_CC3NP_Pos (11U)
Kojto 122:f9eeca106725 4602 #define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 4603 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
Kojto 122:f9eeca106725 4604 #define TIM_CCER_CC4E_Pos (12U)
Kojto 122:f9eeca106725 4605 #define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 4606 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
Kojto 122:f9eeca106725 4607 #define TIM_CCER_CC4P_Pos (13U)
Kojto 122:f9eeca106725 4608 #define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 4609 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
Kojto 122:f9eeca106725 4610 #define TIM_CCER_CC4NP_Pos (15U)
Kojto 122:f9eeca106725 4611 #define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 4612 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
Kojto 90:cb3d968589d8 4613
Kojto 90:cb3d968589d8 4614 /******************* Bit definition for TIM_CNT register *******************/
Kojto 122:f9eeca106725 4615 #define TIM_CNT_CNT_Pos (0U)
Kojto 122:f9eeca106725 4616 #define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 4617 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
Kojto 90:cb3d968589d8 4618
Kojto 90:cb3d968589d8 4619 /******************* Bit definition for TIM_PSC register *******************/
Kojto 122:f9eeca106725 4620 #define TIM_PSC_PSC_Pos (0U)
Kojto 122:f9eeca106725 4621 #define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 4622 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
Kojto 90:cb3d968589d8 4623
Kojto 90:cb3d968589d8 4624 /******************* Bit definition for TIM_ARR register *******************/
Kojto 122:f9eeca106725 4625 #define TIM_ARR_ARR_Pos (0U)
Kojto 122:f9eeca106725 4626 #define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
Kojto 122:f9eeca106725 4627 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
Kojto 90:cb3d968589d8 4628
Kojto 90:cb3d968589d8 4629 /******************* Bit definition for TIM_RCR register *******************/
Kojto 122:f9eeca106725 4630 #define TIM_RCR_REP_Pos (0U)
Kojto 122:f9eeca106725 4631 #define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 4632 #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
Kojto 90:cb3d968589d8 4633
Kojto 90:cb3d968589d8 4634 /******************* Bit definition for TIM_CCR1 register ******************/
Kojto 122:f9eeca106725 4635 #define TIM_CCR1_CCR1_Pos (0U)
Kojto 122:f9eeca106725 4636 #define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 4637 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
Kojto 90:cb3d968589d8 4638
Kojto 90:cb3d968589d8 4639 /******************* Bit definition for TIM_CCR2 register ******************/
Kojto 122:f9eeca106725 4640 #define TIM_CCR2_CCR2_Pos (0U)
Kojto 122:f9eeca106725 4641 #define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 4642 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
Kojto 90:cb3d968589d8 4643
Kojto 90:cb3d968589d8 4644 /******************* Bit definition for TIM_CCR3 register ******************/
Kojto 122:f9eeca106725 4645 #define TIM_CCR3_CCR3_Pos (0U)
Kojto 122:f9eeca106725 4646 #define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 4647 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
Kojto 90:cb3d968589d8 4648
Kojto 90:cb3d968589d8 4649 /******************* Bit definition for TIM_CCR4 register ******************/
Kojto 122:f9eeca106725 4650 #define TIM_CCR4_CCR4_Pos (0U)
Kojto 122:f9eeca106725 4651 #define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 4652 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
Kojto 90:cb3d968589d8 4653
Kojto 90:cb3d968589d8 4654 /******************* Bit definition for TIM_BDTR register ******************/
Kojto 122:f9eeca106725 4655 #define TIM_BDTR_DTG_Pos (0U)
Kojto 122:f9eeca106725 4656 #define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 4657 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
Kojto 122:f9eeca106725 4658 #define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 4659 #define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 4660 #define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 4661 #define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 4662 #define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 4663 #define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 4664 #define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 4665 #define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 4666
Kojto 122:f9eeca106725 4667 #define TIM_BDTR_LOCK_Pos (8U)
Kojto 122:f9eeca106725 4668 #define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
Kojto 122:f9eeca106725 4669 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
Kojto 122:f9eeca106725 4670 #define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 4671 #define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 4672
Kojto 122:f9eeca106725 4673 #define TIM_BDTR_OSSI_Pos (10U)
Kojto 122:f9eeca106725 4674 #define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 4675 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
Kojto 122:f9eeca106725 4676 #define TIM_BDTR_OSSR_Pos (11U)
Kojto 122:f9eeca106725 4677 #define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 4678 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
Kojto 122:f9eeca106725 4679 #define TIM_BDTR_BKE_Pos (12U)
Kojto 122:f9eeca106725 4680 #define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 4681 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
Kojto 122:f9eeca106725 4682 #define TIM_BDTR_BKP_Pos (13U)
Kojto 122:f9eeca106725 4683 #define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 4684 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
Kojto 122:f9eeca106725 4685 #define TIM_BDTR_AOE_Pos (14U)
Kojto 122:f9eeca106725 4686 #define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 4687 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
Kojto 122:f9eeca106725 4688 #define TIM_BDTR_MOE_Pos (15U)
Kojto 122:f9eeca106725 4689 #define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 4690 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
Kojto 90:cb3d968589d8 4691
Kojto 90:cb3d968589d8 4692 /******************* Bit definition for TIM_DCR register *******************/
Kojto 122:f9eeca106725 4693 #define TIM_DCR_DBA_Pos (0U)
Kojto 122:f9eeca106725 4694 #define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
Kojto 122:f9eeca106725 4695 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
Kojto 122:f9eeca106725 4696 #define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 4697 #define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 4698 #define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 4699 #define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 4700 #define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 4701
Kojto 122:f9eeca106725 4702 #define TIM_DCR_DBL_Pos (8U)
Kojto 122:f9eeca106725 4703 #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
Kojto 122:f9eeca106725 4704 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
Kojto 122:f9eeca106725 4705 #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 4706 #define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 4707 #define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 4708 #define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 4709 #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
Kojto 90:cb3d968589d8 4710
Kojto 90:cb3d968589d8 4711 /******************* Bit definition for TIM_DMAR register ******************/
Kojto 122:f9eeca106725 4712 #define TIM_DMAR_DMAB_Pos (0U)
Kojto 122:f9eeca106725 4713 #define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
Kojto 122:f9eeca106725 4714 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
Kojto 90:cb3d968589d8 4715
Kojto 90:cb3d968589d8 4716 /******************* Bit definition for TIM14_OR register ********************/
Kojto 122:f9eeca106725 4717 #define TIM14_OR_TI1_RMP_Pos (0U)
Kojto 122:f9eeca106725 4718 #define TIM14_OR_TI1_RMP_Msk (0x3U << TIM14_OR_TI1_RMP_Pos) /*!< 0x00000003 */
Kojto 122:f9eeca106725 4719 #define TIM14_OR_TI1_RMP TIM14_OR_TI1_RMP_Msk /*!<TI1_RMP[1:0] bits (TIM14 Input 4 remap) */
Kojto 122:f9eeca106725 4720 #define TIM14_OR_TI1_RMP_0 (0x1U << TIM14_OR_TI1_RMP_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 4721 #define TIM14_OR_TI1_RMP_1 (0x2U << TIM14_OR_TI1_RMP_Pos) /*!< 0x00000002 */
Kojto 90:cb3d968589d8 4722
Kojto 90:cb3d968589d8 4723 /******************************************************************************/
Kojto 90:cb3d968589d8 4724 /* */
Kojto 90:cb3d968589d8 4725 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
Kojto 90:cb3d968589d8 4726 /* */
Kojto 90:cb3d968589d8 4727 /******************************************************************************/
Kojto 90:cb3d968589d8 4728 /****************** Bit definition for USART_CR1 register *******************/
Kojto 122:f9eeca106725 4729 #define USART_CR1_UE_Pos (0U)
Kojto 122:f9eeca106725 4730 #define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 4731 #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
Kojto 122:f9eeca106725 4732 #define USART_CR1_RE_Pos (2U)
Kojto 122:f9eeca106725 4733 #define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 4734 #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
Kojto 122:f9eeca106725 4735 #define USART_CR1_TE_Pos (3U)
Kojto 122:f9eeca106725 4736 #define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 4737 #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
Kojto 122:f9eeca106725 4738 #define USART_CR1_IDLEIE_Pos (4U)
Kojto 122:f9eeca106725 4739 #define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 4740 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
Kojto 122:f9eeca106725 4741 #define USART_CR1_RXNEIE_Pos (5U)
Kojto 122:f9eeca106725 4742 #define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 4743 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
Kojto 122:f9eeca106725 4744 #define USART_CR1_TCIE_Pos (6U)
Kojto 122:f9eeca106725 4745 #define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 4746 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
Kojto 122:f9eeca106725 4747 #define USART_CR1_TXEIE_Pos (7U)
Kojto 122:f9eeca106725 4748 #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 4749 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */
Kojto 122:f9eeca106725 4750 #define USART_CR1_PEIE_Pos (8U)
Kojto 122:f9eeca106725 4751 #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 4752 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
Kojto 122:f9eeca106725 4753 #define USART_CR1_PS_Pos (9U)
Kojto 122:f9eeca106725 4754 #define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 4755 #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
Kojto 122:f9eeca106725 4756 #define USART_CR1_PCE_Pos (10U)
Kojto 122:f9eeca106725 4757 #define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 4758 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
Kojto 122:f9eeca106725 4759 #define USART_CR1_WAKE_Pos (11U)
Kojto 122:f9eeca106725 4760 #define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 4761 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
Kojto 122:f9eeca106725 4762 #define USART_CR1_M_Pos (12U)
Kojto 122:f9eeca106725 4763 #define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 4764 #define USART_CR1_M USART_CR1_M_Msk /*!< Word Length */
Kojto 122:f9eeca106725 4765 #define USART_CR1_MME_Pos (13U)
Kojto 122:f9eeca106725 4766 #define USART_CR1_MME_Msk (0x1U << USART_CR1_MME_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 4767 #define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
Kojto 122:f9eeca106725 4768 #define USART_CR1_CMIE_Pos (14U)
Kojto 122:f9eeca106725 4769 #define USART_CR1_CMIE_Msk (0x1U << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 4770 #define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
Kojto 122:f9eeca106725 4771 #define USART_CR1_OVER8_Pos (15U)
Kojto 122:f9eeca106725 4772 #define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 4773 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
Kojto 122:f9eeca106725 4774 #define USART_CR1_DEDT_Pos (16U)
Kojto 122:f9eeca106725 4775 #define USART_CR1_DEDT_Msk (0x1FU << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
Kojto 122:f9eeca106725 4776 #define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
Kojto 122:f9eeca106725 4777 #define USART_CR1_DEDT_0 (0x01U << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 4778 #define USART_CR1_DEDT_1 (0x02U << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 4779 #define USART_CR1_DEDT_2 (0x04U << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 4780 #define USART_CR1_DEDT_3 (0x08U << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 4781 #define USART_CR1_DEDT_4 (0x10U << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 4782 #define USART_CR1_DEAT_Pos (21U)
Kojto 122:f9eeca106725 4783 #define USART_CR1_DEAT_Msk (0x1FU << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
Kojto 122:f9eeca106725 4784 #define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
Kojto 122:f9eeca106725 4785 #define USART_CR1_DEAT_0 (0x01U << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 4786 #define USART_CR1_DEAT_1 (0x02U << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 4787 #define USART_CR1_DEAT_2 (0x04U << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 4788 #define USART_CR1_DEAT_3 (0x08U << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
Kojto 122:f9eeca106725 4789 #define USART_CR1_DEAT_4 (0x10U << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
Kojto 122:f9eeca106725 4790 #define USART_CR1_RTOIE_Pos (26U)
Kojto 122:f9eeca106725 4791 #define USART_CR1_RTOIE_Msk (0x1U << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
Kojto 122:f9eeca106725 4792 #define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
Kojto 122:f9eeca106725 4793 #define USART_CR1_EOBIE_Pos (27U)
Kojto 122:f9eeca106725 4794 #define USART_CR1_EOBIE_Msk (0x1U << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
Kojto 122:f9eeca106725 4795 #define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
Kojto 90:cb3d968589d8 4796
Kojto 90:cb3d968589d8 4797 /****************** Bit definition for USART_CR2 register *******************/
Kojto 122:f9eeca106725 4798 #define USART_CR2_ADDM7_Pos (4U)
Kojto 122:f9eeca106725 4799 #define USART_CR2_ADDM7_Msk (0x1U << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 4800 #define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
Kojto 122:f9eeca106725 4801 #define USART_CR2_LBCL_Pos (8U)
Kojto 122:f9eeca106725 4802 #define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 4803 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
Kojto 122:f9eeca106725 4804 #define USART_CR2_CPHA_Pos (9U)
Kojto 122:f9eeca106725 4805 #define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 4806 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
Kojto 122:f9eeca106725 4807 #define USART_CR2_CPOL_Pos (10U)
Kojto 122:f9eeca106725 4808 #define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 4809 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
Kojto 122:f9eeca106725 4810 #define USART_CR2_CLKEN_Pos (11U)
Kojto 122:f9eeca106725 4811 #define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 4812 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
Kojto 122:f9eeca106725 4813 #define USART_CR2_STOP_Pos (12U)
Kojto 122:f9eeca106725 4814 #define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
Kojto 122:f9eeca106725 4815 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
Kojto 122:f9eeca106725 4816 #define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 4817 #define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 4818 #define USART_CR2_SWAP_Pos (15U)
Kojto 122:f9eeca106725 4819 #define USART_CR2_SWAP_Msk (0x1U << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 4820 #define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
Kojto 122:f9eeca106725 4821 #define USART_CR2_RXINV_Pos (16U)
Kojto 122:f9eeca106725 4822 #define USART_CR2_RXINV_Msk (0x1U << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 4823 #define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
Kojto 122:f9eeca106725 4824 #define USART_CR2_TXINV_Pos (17U)
Kojto 122:f9eeca106725 4825 #define USART_CR2_TXINV_Msk (0x1U << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 4826 #define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
Kojto 122:f9eeca106725 4827 #define USART_CR2_DATAINV_Pos (18U)
Kojto 122:f9eeca106725 4828 #define USART_CR2_DATAINV_Msk (0x1U << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 4829 #define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
Kojto 122:f9eeca106725 4830 #define USART_CR2_MSBFIRST_Pos (19U)
Kojto 122:f9eeca106725 4831 #define USART_CR2_MSBFIRST_Msk (0x1U << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 4832 #define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
Kojto 122:f9eeca106725 4833 #define USART_CR2_ABREN_Pos (20U)
Kojto 122:f9eeca106725 4834 #define USART_CR2_ABREN_Msk (0x1U << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
Kojto 122:f9eeca106725 4835 #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/
Kojto 122:f9eeca106725 4836 #define USART_CR2_ABRMODE_Pos (21U)
Kojto 122:f9eeca106725 4837 #define USART_CR2_ABRMODE_Msk (0x3U << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
Kojto 122:f9eeca106725 4838 #define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
Kojto 122:f9eeca106725 4839 #define USART_CR2_ABRMODE_0 (0x1U << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 4840 #define USART_CR2_ABRMODE_1 (0x2U << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 4841 #define USART_CR2_RTOEN_Pos (23U)
Kojto 122:f9eeca106725 4842 #define USART_CR2_RTOEN_Msk (0x1U << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
Kojto 122:f9eeca106725 4843 #define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
Kojto 122:f9eeca106725 4844 #define USART_CR2_ADD_Pos (24U)
Kojto 122:f9eeca106725 4845 #define USART_CR2_ADD_Msk (0xFFU << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
Kojto 122:f9eeca106725 4846 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
Kojto 90:cb3d968589d8 4847
Kojto 90:cb3d968589d8 4848 /****************** Bit definition for USART_CR3 register *******************/
Kojto 122:f9eeca106725 4849 #define USART_CR3_EIE_Pos (0U)
Kojto 122:f9eeca106725 4850 #define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 4851 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
Kojto 122:f9eeca106725 4852 #define USART_CR3_HDSEL_Pos (3U)
Kojto 122:f9eeca106725 4853 #define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 4854 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
Kojto 122:f9eeca106725 4855 #define USART_CR3_DMAR_Pos (6U)
Kojto 122:f9eeca106725 4856 #define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 4857 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
Kojto 122:f9eeca106725 4858 #define USART_CR3_DMAT_Pos (7U)
Kojto 122:f9eeca106725 4859 #define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 4860 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
Kojto 122:f9eeca106725 4861 #define USART_CR3_RTSE_Pos (8U)
Kojto 122:f9eeca106725 4862 #define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 4863 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
Kojto 122:f9eeca106725 4864 #define USART_CR3_CTSE_Pos (9U)
Kojto 122:f9eeca106725 4865 #define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 4866 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
Kojto 122:f9eeca106725 4867 #define USART_CR3_CTSIE_Pos (10U)
Kojto 122:f9eeca106725 4868 #define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 4869 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
Kojto 122:f9eeca106725 4870 #define USART_CR3_ONEBIT_Pos (11U)
Kojto 122:f9eeca106725 4871 #define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 4872 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
Kojto 122:f9eeca106725 4873 #define USART_CR3_OVRDIS_Pos (12U)
Kojto 122:f9eeca106725 4874 #define USART_CR3_OVRDIS_Msk (0x1U << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
Kojto 122:f9eeca106725 4875 #define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
Kojto 122:f9eeca106725 4876 #define USART_CR3_DDRE_Pos (13U)
Kojto 122:f9eeca106725 4877 #define USART_CR3_DDRE_Msk (0x1U << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
Kojto 122:f9eeca106725 4878 #define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
Kojto 122:f9eeca106725 4879 #define USART_CR3_DEM_Pos (14U)
Kojto 122:f9eeca106725 4880 #define USART_CR3_DEM_Msk (0x1U << USART_CR3_DEM_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 4881 #define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
Kojto 122:f9eeca106725 4882 #define USART_CR3_DEP_Pos (15U)
Kojto 122:f9eeca106725 4883 #define USART_CR3_DEP_Msk (0x1U << USART_CR3_DEP_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 4884 #define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
Kojto 90:cb3d968589d8 4885
Kojto 90:cb3d968589d8 4886 /****************** Bit definition for USART_BRR register *******************/
Kojto 122:f9eeca106725 4887 #define USART_BRR_DIV_FRACTION_Pos (0U)
Kojto 122:f9eeca106725 4888 #define USART_BRR_DIV_FRACTION_Msk (0xFU << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
Kojto 122:f9eeca106725 4889 #define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
Kojto 122:f9eeca106725 4890 #define USART_BRR_DIV_MANTISSA_Pos (4U)
Kojto 122:f9eeca106725 4891 #define USART_BRR_DIV_MANTISSA_Msk (0xFFFU << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
Kojto 122:f9eeca106725 4892 #define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
Kojto 90:cb3d968589d8 4893
Kojto 90:cb3d968589d8 4894 /****************** Bit definition for USART_GTPR register ******************/
Kojto 122:f9eeca106725 4895 #define USART_GTPR_PSC_Pos (0U)
Kojto 122:f9eeca106725 4896 #define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
Kojto 122:f9eeca106725 4897 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
Kojto 122:f9eeca106725 4898 #define USART_GTPR_GT_Pos (8U)
Kojto 122:f9eeca106725 4899 #define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
Kojto 122:f9eeca106725 4900 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
Kojto 90:cb3d968589d8 4901
Kojto 90:cb3d968589d8 4902
Kojto 90:cb3d968589d8 4903 /******************* Bit definition for USART_RTOR register *****************/
Kojto 122:f9eeca106725 4904 #define USART_RTOR_RTO_Pos (0U)
Kojto 122:f9eeca106725 4905 #define USART_RTOR_RTO_Msk (0xFFFFFFU << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
Kojto 122:f9eeca106725 4906 #define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
Kojto 122:f9eeca106725 4907 #define USART_RTOR_BLEN_Pos (24U)
Kojto 122:f9eeca106725 4908 #define USART_RTOR_BLEN_Msk (0xFFU << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
Kojto 122:f9eeca106725 4909 #define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
Kojto 90:cb3d968589d8 4910
Kojto 90:cb3d968589d8 4911 /******************* Bit definition for USART_RQR register ******************/
Kojto 122:f9eeca106725 4912 #define USART_RQR_ABRRQ_Pos (0U)
Kojto 122:f9eeca106725 4913 #define USART_RQR_ABRRQ_Msk (0x1U << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 4914 #define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */
Kojto 122:f9eeca106725 4915 #define USART_RQR_SBKRQ_Pos (1U)
Kojto 122:f9eeca106725 4916 #define USART_RQR_SBKRQ_Msk (0x1U << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 4917 #define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */
Kojto 122:f9eeca106725 4918 #define USART_RQR_MMRQ_Pos (2U)
Kojto 122:f9eeca106725 4919 #define USART_RQR_MMRQ_Msk (0x1U << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 4920 #define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */
Kojto 122:f9eeca106725 4921 #define USART_RQR_RXFRQ_Pos (3U)
Kojto 122:f9eeca106725 4922 #define USART_RQR_RXFRQ_Msk (0x1U << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 4923 #define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */
Kojto 90:cb3d968589d8 4924
Kojto 90:cb3d968589d8 4925 /******************* Bit definition for USART_ISR register ******************/
Kojto 122:f9eeca106725 4926 #define USART_ISR_PE_Pos (0U)
Kojto 122:f9eeca106725 4927 #define USART_ISR_PE_Msk (0x1U << USART_ISR_PE_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 4928 #define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
Kojto 122:f9eeca106725 4929 #define USART_ISR_FE_Pos (1U)
Kojto 122:f9eeca106725 4930 #define USART_ISR_FE_Msk (0x1U << USART_ISR_FE_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 4931 #define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
Kojto 122:f9eeca106725 4932 #define USART_ISR_NE_Pos (2U)
Kojto 122:f9eeca106725 4933 #define USART_ISR_NE_Msk (0x1U << USART_ISR_NE_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 4934 #define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
Kojto 122:f9eeca106725 4935 #define USART_ISR_ORE_Pos (3U)
Kojto 122:f9eeca106725 4936 #define USART_ISR_ORE_Msk (0x1U << USART_ISR_ORE_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 4937 #define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
Kojto 122:f9eeca106725 4938 #define USART_ISR_IDLE_Pos (4U)
Kojto 122:f9eeca106725 4939 #define USART_ISR_IDLE_Msk (0x1U << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 4940 #define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
Kojto 122:f9eeca106725 4941 #define USART_ISR_RXNE_Pos (5U)
Kojto 122:f9eeca106725 4942 #define USART_ISR_RXNE_Msk (0x1U << USART_ISR_RXNE_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 4943 #define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */
Kojto 122:f9eeca106725 4944 #define USART_ISR_TC_Pos (6U)
Kojto 122:f9eeca106725 4945 #define USART_ISR_TC_Msk (0x1U << USART_ISR_TC_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 4946 #define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
Kojto 122:f9eeca106725 4947 #define USART_ISR_TXE_Pos (7U)
Kojto 122:f9eeca106725 4948 #define USART_ISR_TXE_Msk (0x1U << USART_ISR_TXE_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 4949 #define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */
Kojto 122:f9eeca106725 4950 #define USART_ISR_CTSIF_Pos (9U)
Kojto 122:f9eeca106725 4951 #define USART_ISR_CTSIF_Msk (0x1U << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 4952 #define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
Kojto 122:f9eeca106725 4953 #define USART_ISR_CTS_Pos (10U)
Kojto 122:f9eeca106725 4954 #define USART_ISR_CTS_Msk (0x1U << USART_ISR_CTS_Pos) /*!< 0x00000400 */
Kojto 122:f9eeca106725 4955 #define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
Kojto 122:f9eeca106725 4956 #define USART_ISR_RTOF_Pos (11U)
Kojto 122:f9eeca106725 4957 #define USART_ISR_RTOF_Msk (0x1U << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 4958 #define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
Kojto 122:f9eeca106725 4959 #define USART_ISR_ABRE_Pos (14U)
Kojto 122:f9eeca106725 4960 #define USART_ISR_ABRE_Msk (0x1U << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
Kojto 122:f9eeca106725 4961 #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
Kojto 122:f9eeca106725 4962 #define USART_ISR_ABRF_Pos (15U)
Kojto 122:f9eeca106725 4963 #define USART_ISR_ABRF_Msk (0x1U << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
Kojto 122:f9eeca106725 4964 #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
Kojto 122:f9eeca106725 4965 #define USART_ISR_BUSY_Pos (16U)
Kojto 122:f9eeca106725 4966 #define USART_ISR_BUSY_Msk (0x1U << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
Kojto 122:f9eeca106725 4967 #define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
Kojto 122:f9eeca106725 4968 #define USART_ISR_CMF_Pos (17U)
Kojto 122:f9eeca106725 4969 #define USART_ISR_CMF_Msk (0x1U << USART_ISR_CMF_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 4970 #define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
Kojto 122:f9eeca106725 4971 #define USART_ISR_SBKF_Pos (18U)
Kojto 122:f9eeca106725 4972 #define USART_ISR_SBKF_Msk (0x1U << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
Kojto 122:f9eeca106725 4973 #define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
Kojto 122:f9eeca106725 4974 #define USART_ISR_RWU_Pos (19U)
Kojto 122:f9eeca106725 4975 #define USART_ISR_RWU_Msk (0x1U << USART_ISR_RWU_Pos) /*!< 0x00080000 */
Kojto 122:f9eeca106725 4976 #define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
Kojto 122:f9eeca106725 4977 #define USART_ISR_TEACK_Pos (21U)
Kojto 122:f9eeca106725 4978 #define USART_ISR_TEACK_Msk (0x1U << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
Kojto 122:f9eeca106725 4979 #define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
Kojto 122:f9eeca106725 4980 #define USART_ISR_REACK_Pos (22U)
Kojto 122:f9eeca106725 4981 #define USART_ISR_REACK_Msk (0x1U << USART_ISR_REACK_Pos) /*!< 0x00400000 */
Kojto 122:f9eeca106725 4982 #define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
Kojto 90:cb3d968589d8 4983
Kojto 90:cb3d968589d8 4984 /******************* Bit definition for USART_ICR register ******************/
Kojto 122:f9eeca106725 4985 #define USART_ICR_PECF_Pos (0U)
Kojto 122:f9eeca106725 4986 #define USART_ICR_PECF_Msk (0x1U << USART_ICR_PECF_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 4987 #define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
Kojto 122:f9eeca106725 4988 #define USART_ICR_FECF_Pos (1U)
Kojto 122:f9eeca106725 4989 #define USART_ICR_FECF_Msk (0x1U << USART_ICR_FECF_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 4990 #define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
Kojto 122:f9eeca106725 4991 #define USART_ICR_NCF_Pos (2U)
Kojto 122:f9eeca106725 4992 #define USART_ICR_NCF_Msk (0x1U << USART_ICR_NCF_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 4993 #define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */
Kojto 122:f9eeca106725 4994 #define USART_ICR_ORECF_Pos (3U)
Kojto 122:f9eeca106725 4995 #define USART_ICR_ORECF_Msk (0x1U << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 4996 #define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
Kojto 122:f9eeca106725 4997 #define USART_ICR_IDLECF_Pos (4U)
Kojto 122:f9eeca106725 4998 #define USART_ICR_IDLECF_Msk (0x1U << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 4999 #define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
Kojto 122:f9eeca106725 5000 #define USART_ICR_TCCF_Pos (6U)
Kojto 122:f9eeca106725 5001 #define USART_ICR_TCCF_Msk (0x1U << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 5002 #define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
Kojto 122:f9eeca106725 5003 #define USART_ICR_CTSCF_Pos (9U)
Kojto 122:f9eeca106725 5004 #define USART_ICR_CTSCF_Msk (0x1U << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 5005 #define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
Kojto 122:f9eeca106725 5006 #define USART_ICR_RTOCF_Pos (11U)
Kojto 122:f9eeca106725 5007 #define USART_ICR_RTOCF_Msk (0x1U << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
Kojto 122:f9eeca106725 5008 #define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
Kojto 122:f9eeca106725 5009 #define USART_ICR_CMCF_Pos (17U)
Kojto 122:f9eeca106725 5010 #define USART_ICR_CMCF_Msk (0x1U << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
Kojto 122:f9eeca106725 5011 #define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
Kojto 90:cb3d968589d8 5012
Kojto 90:cb3d968589d8 5013 /******************* Bit definition for USART_RDR register ******************/
Kojto 122:f9eeca106725 5014 #define USART_RDR_RDR ((uint16_t)0x01FFU) /*!< RDR[8:0] bits (Receive Data value) */
Kojto 90:cb3d968589d8 5015
Kojto 90:cb3d968589d8 5016 /******************* Bit definition for USART_TDR register ******************/
Kojto 122:f9eeca106725 5017 #define USART_TDR_TDR ((uint16_t)0x01FFU) /*!< TDR[8:0] bits (Transmit Data value) */
Kojto 90:cb3d968589d8 5018
Kojto 90:cb3d968589d8 5019 /******************************************************************************/
Kojto 90:cb3d968589d8 5020 /* */
Kojto 90:cb3d968589d8 5021 /* Window WATCHDOG (WWDG) */
Kojto 90:cb3d968589d8 5022 /* */
Kojto 90:cb3d968589d8 5023 /******************************************************************************/
Kojto 122:f9eeca106725 5024
Kojto 90:cb3d968589d8 5025 /******************* Bit definition for WWDG_CR register ********************/
Kojto 122:f9eeca106725 5026 #define WWDG_CR_T_Pos (0U)
Kojto 122:f9eeca106725 5027 #define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
Kojto 122:f9eeca106725 5028 #define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
Kojto 122:f9eeca106725 5029 #define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 5030 #define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 5031 #define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 5032 #define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 5033 #define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 5034 #define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 5035 #define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 5036
Kojto 122:f9eeca106725 5037 /* Legacy defines */
Kojto 122:f9eeca106725 5038 #define WWDG_CR_T0 WWDG_CR_T_0
Kojto 122:f9eeca106725 5039 #define WWDG_CR_T1 WWDG_CR_T_1
Kojto 122:f9eeca106725 5040 #define WWDG_CR_T2 WWDG_CR_T_2
Kojto 122:f9eeca106725 5041 #define WWDG_CR_T3 WWDG_CR_T_3
Kojto 122:f9eeca106725 5042 #define WWDG_CR_T4 WWDG_CR_T_4
Kojto 122:f9eeca106725 5043 #define WWDG_CR_T5 WWDG_CR_T_5
Kojto 122:f9eeca106725 5044 #define WWDG_CR_T6 WWDG_CR_T_6
Kojto 122:f9eeca106725 5045
Kojto 122:f9eeca106725 5046 #define WWDG_CR_WDGA_Pos (7U)
Kojto 122:f9eeca106725 5047 #define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 5048 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */
Kojto 90:cb3d968589d8 5049
Kojto 90:cb3d968589d8 5050 /******************* Bit definition for WWDG_CFR register *******************/
Kojto 122:f9eeca106725 5051 #define WWDG_CFR_W_Pos (0U)
Kojto 122:f9eeca106725 5052 #define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
Kojto 122:f9eeca106725 5053 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */
Kojto 122:f9eeca106725 5054 #define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 5055 #define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x00000002 */
Kojto 122:f9eeca106725 5056 #define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x00000004 */
Kojto 122:f9eeca106725 5057 #define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x00000008 */
Kojto 122:f9eeca106725 5058 #define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x00000010 */
Kojto 122:f9eeca106725 5059 #define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x00000020 */
Kojto 122:f9eeca106725 5060 #define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x00000040 */
Kojto 122:f9eeca106725 5061
Kojto 122:f9eeca106725 5062 /* Legacy defines */
Kojto 122:f9eeca106725 5063 #define WWDG_CFR_W0 WWDG_CFR_W_0
Kojto 122:f9eeca106725 5064 #define WWDG_CFR_W1 WWDG_CFR_W_1
Kojto 122:f9eeca106725 5065 #define WWDG_CFR_W2 WWDG_CFR_W_2
Kojto 122:f9eeca106725 5066 #define WWDG_CFR_W3 WWDG_CFR_W_3
Kojto 122:f9eeca106725 5067 #define WWDG_CFR_W4 WWDG_CFR_W_4
Kojto 122:f9eeca106725 5068 #define WWDG_CFR_W5 WWDG_CFR_W_5
Kojto 122:f9eeca106725 5069 #define WWDG_CFR_W6 WWDG_CFR_W_6
Kojto 122:f9eeca106725 5070
Kojto 122:f9eeca106725 5071 #define WWDG_CFR_WDGTB_Pos (7U)
Kojto 122:f9eeca106725 5072 #define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
Kojto 122:f9eeca106725 5073 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */
Kojto 122:f9eeca106725 5074 #define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */
Kojto 122:f9eeca106725 5075 #define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */
Kojto 122:f9eeca106725 5076
Kojto 122:f9eeca106725 5077 /* Legacy defines */
Kojto 122:f9eeca106725 5078 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
Kojto 122:f9eeca106725 5079 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
Kojto 122:f9eeca106725 5080
Kojto 122:f9eeca106725 5081 #define WWDG_CFR_EWI_Pos (9U)
Kojto 122:f9eeca106725 5082 #define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
Kojto 122:f9eeca106725 5083 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */
Kojto 90:cb3d968589d8 5084
Kojto 90:cb3d968589d8 5085 /******************* Bit definition for WWDG_SR register ********************/
Kojto 122:f9eeca106725 5086 #define WWDG_SR_EWIF_Pos (0U)
Kojto 122:f9eeca106725 5087 #define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
Kojto 122:f9eeca106725 5088 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */
Kojto 90:cb3d968589d8 5089
Kojto 90:cb3d968589d8 5090 /**
Kojto 90:cb3d968589d8 5091 * @}
Kojto 90:cb3d968589d8 5092 */
Kojto 90:cb3d968589d8 5093
Kojto 90:cb3d968589d8 5094 /**
Kojto 90:cb3d968589d8 5095 * @}
Kojto 90:cb3d968589d8 5096 */
Kojto 90:cb3d968589d8 5097
Kojto 90:cb3d968589d8 5098
Kojto 90:cb3d968589d8 5099 /** @addtogroup Exported_macro
Kojto 90:cb3d968589d8 5100 * @{
Kojto 90:cb3d968589d8 5101 */
Kojto 90:cb3d968589d8 5102
Kojto 90:cb3d968589d8 5103 /****************************** ADC Instances *********************************/
Kojto 90:cb3d968589d8 5104 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
Kojto 90:cb3d968589d8 5105
Kojto 90:cb3d968589d8 5106 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC)
Kojto 90:cb3d968589d8 5107
Kojto 90:cb3d968589d8 5108 /****************************** CRC Instances *********************************/
Kojto 90:cb3d968589d8 5109 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
Kojto 122:f9eeca106725 5110
Kojto 122:f9eeca106725 5111 /******************************* DMA Instances ********************************/
Kojto 90:cb3d968589d8 5112 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
Kojto 90:cb3d968589d8 5113 ((INSTANCE) == DMA1_Channel2) || \
Kojto 90:cb3d968589d8 5114 ((INSTANCE) == DMA1_Channel3) || \
Kojto 90:cb3d968589d8 5115 ((INSTANCE) == DMA1_Channel4) || \
Kojto 90:cb3d968589d8 5116 ((INSTANCE) == DMA1_Channel5))
Kojto 90:cb3d968589d8 5117
Kojto 90:cb3d968589d8 5118 /****************************** GPIO Instances ********************************/
Kojto 93:e188a91d3eaa 5119 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
Kojto 93:e188a91d3eaa 5120 ((INSTANCE) == GPIOB) || \
Kojto 93:e188a91d3eaa 5121 ((INSTANCE) == GPIOC) || \
Kojto 93:e188a91d3eaa 5122 ((INSTANCE) == GPIOD) || \
Kojto 93:e188a91d3eaa 5123 ((INSTANCE) == GPIOF))
Kojto 122:f9eeca106725 5124
Kojto 122:f9eeca106725 5125 /**************************** GPIO Alternate Function Instances ***************/
Kojto 93:e188a91d3eaa 5126 #define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
Kojto 93:e188a91d3eaa 5127 ((INSTANCE) == GPIOB))
Kojto 93:e188a91d3eaa 5128
Kojto 122:f9eeca106725 5129 /****************************** GPIO Lock Instances ***************************/
Kojto 90:cb3d968589d8 5130 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
Kojto 90:cb3d968589d8 5131 ((INSTANCE) == GPIOB))
Kojto 90:cb3d968589d8 5132
Kojto 90:cb3d968589d8 5133 /****************************** I2C Instances *********************************/
Kojto 90:cb3d968589d8 5134 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
Kojto 90:cb3d968589d8 5135 ((INSTANCE) == I2C2))
Kojto 90:cb3d968589d8 5136
Kojto 108:34e6b704fe68 5137
Kojto 90:cb3d968589d8 5138 /****************************** IWDG Instances ********************************/
Kojto 90:cb3d968589d8 5139 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
Kojto 90:cb3d968589d8 5140
Kojto 90:cb3d968589d8 5141 /****************************** RTC Instances *********************************/
Kojto 90:cb3d968589d8 5142 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
Kojto 90:cb3d968589d8 5143
Kojto 90:cb3d968589d8 5144 /****************************** SMBUS Instances *********************************/
Kojto 90:cb3d968589d8 5145 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
Kojto 90:cb3d968589d8 5146
Kojto 90:cb3d968589d8 5147 /****************************** SPI Instances *********************************/
Kojto 90:cb3d968589d8 5148 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
Kojto 90:cb3d968589d8 5149 ((INSTANCE) == SPI2))
Kojto 90:cb3d968589d8 5150
Kojto 90:cb3d968589d8 5151 /****************************** TIM Instances *********************************/
Kojto 90:cb3d968589d8 5152 #define IS_TIM_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 5153 (((INSTANCE) == TIM1) || \
Kojto 90:cb3d968589d8 5154 ((INSTANCE) == TIM3) || \
Kojto 90:cb3d968589d8 5155 ((INSTANCE) == TIM6) || \
Kojto 90:cb3d968589d8 5156 ((INSTANCE) == TIM14) || \
Kojto 90:cb3d968589d8 5157 ((INSTANCE) == TIM15) || \
Kojto 90:cb3d968589d8 5158 ((INSTANCE) == TIM16) || \
Kojto 90:cb3d968589d8 5159 ((INSTANCE) == TIM17))
Kojto 90:cb3d968589d8 5160
Kojto 90:cb3d968589d8 5161 #define IS_TIM_CC1_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 5162 (((INSTANCE) == TIM1) || \
Kojto 90:cb3d968589d8 5163 ((INSTANCE) == TIM3) || \
Kojto 90:cb3d968589d8 5164 ((INSTANCE) == TIM14) || \
Kojto 90:cb3d968589d8 5165 ((INSTANCE) == TIM15) || \
Kojto 90:cb3d968589d8 5166 ((INSTANCE) == TIM16) || \
Kojto 90:cb3d968589d8 5167 ((INSTANCE) == TIM17))
Kojto 90:cb3d968589d8 5168
Kojto 90:cb3d968589d8 5169 #define IS_TIM_CC2_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 5170 (((INSTANCE) == TIM1) || \
Kojto 90:cb3d968589d8 5171 ((INSTANCE) == TIM3) || \
Kojto 90:cb3d968589d8 5172 ((INSTANCE) == TIM15))
Kojto 90:cb3d968589d8 5173
Kojto 90:cb3d968589d8 5174 #define IS_TIM_CC3_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 5175 (((INSTANCE) == TIM1) || \
Kojto 90:cb3d968589d8 5176 ((INSTANCE) == TIM3))
Kojto 90:cb3d968589d8 5177
Kojto 90:cb3d968589d8 5178 #define IS_TIM_CC4_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 5179 (((INSTANCE) == TIM1) || \
Kojto 90:cb3d968589d8 5180 ((INSTANCE) == TIM3))
Kojto 90:cb3d968589d8 5181
Kojto 90:cb3d968589d8 5182 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 5183 (((INSTANCE) == TIM1) || \
Kojto 90:cb3d968589d8 5184 ((INSTANCE) == TIM3))
Kojto 90:cb3d968589d8 5185
Kojto 90:cb3d968589d8 5186 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 5187 (((INSTANCE) == TIM1) || \
Kojto 90:cb3d968589d8 5188 ((INSTANCE) == TIM3))
Kojto 90:cb3d968589d8 5189
Kojto 90:cb3d968589d8 5190 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 5191 (((INSTANCE) == TIM1) || \
Kojto 90:cb3d968589d8 5192 ((INSTANCE) == TIM3) || \
Kojto 90:cb3d968589d8 5193 ((INSTANCE) == TIM15))
Kojto 90:cb3d968589d8 5194
Kojto 90:cb3d968589d8 5195 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 5196 (((INSTANCE) == TIM1) || \
Kojto 90:cb3d968589d8 5197 ((INSTANCE) == TIM3) || \
Kojto 90:cb3d968589d8 5198 ((INSTANCE) == TIM15))
Kojto 90:cb3d968589d8 5199
Kojto 90:cb3d968589d8 5200 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 5201 (((INSTANCE) == TIM1) || \
Kojto 90:cb3d968589d8 5202 ((INSTANCE) == TIM3))
Kojto 90:cb3d968589d8 5203
Kojto 90:cb3d968589d8 5204 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 5205 (((INSTANCE) == TIM1) || \
Kojto 90:cb3d968589d8 5206 ((INSTANCE) == TIM3))
Kojto 90:cb3d968589d8 5207
Kojto 90:cb3d968589d8 5208 #define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 5209 (((INSTANCE) == TIM1))
Kojto 122:f9eeca106725 5210
Kojto 122:f9eeca106725 5211 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)\
Kojto 122:f9eeca106725 5212 (((INSTANCE) == TIM1))
Kojto 90:cb3d968589d8 5213
Kojto 90:cb3d968589d8 5214 #define IS_TIM_XOR_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 5215 (((INSTANCE) == TIM1) || \
Kojto 90:cb3d968589d8 5216 ((INSTANCE) == TIM3))
Kojto 90:cb3d968589d8 5217
Kojto 90:cb3d968589d8 5218 #define IS_TIM_MASTER_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 5219 (((INSTANCE) == TIM1) || \
Kojto 90:cb3d968589d8 5220 ((INSTANCE) == TIM3) || \
Kojto 90:cb3d968589d8 5221 ((INSTANCE) == TIM15))
Kojto 90:cb3d968589d8 5222
Kojto 90:cb3d968589d8 5223 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 5224 (((INSTANCE) == TIM1) || \
Kojto 90:cb3d968589d8 5225 ((INSTANCE) == TIM3) || \
Kojto 90:cb3d968589d8 5226 ((INSTANCE) == TIM15))
Kojto 90:cb3d968589d8 5227
Kojto 90:cb3d968589d8 5228 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (0)
Kojto 90:cb3d968589d8 5229
Kojto 90:cb3d968589d8 5230 #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 5231 (((INSTANCE) == TIM1) || \
Kojto 90:cb3d968589d8 5232 ((INSTANCE) == TIM3) || \
Kojto 90:cb3d968589d8 5233 ((INSTANCE) == TIM15) || \
Kojto 90:cb3d968589d8 5234 ((INSTANCE) == TIM16) || \
Kojto 90:cb3d968589d8 5235 ((INSTANCE) == TIM17))
Kojto 90:cb3d968589d8 5236
Kojto 90:cb3d968589d8 5237 #define IS_TIM_BREAK_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 5238 (((INSTANCE) == TIM1) || \
Kojto 90:cb3d968589d8 5239 ((INSTANCE) == TIM15) || \
Kojto 90:cb3d968589d8 5240 ((INSTANCE) == TIM16) || \
Kojto 90:cb3d968589d8 5241 ((INSTANCE) == TIM17))
Kojto 90:cb3d968589d8 5242
Kojto 90:cb3d968589d8 5243 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
Kojto 90:cb3d968589d8 5244 ((((INSTANCE) == TIM1) && \
Kojto 90:cb3d968589d8 5245 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 90:cb3d968589d8 5246 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 90:cb3d968589d8 5247 ((CHANNEL) == TIM_CHANNEL_3) || \
Kojto 90:cb3d968589d8 5248 ((CHANNEL) == TIM_CHANNEL_4))) \
Kojto 90:cb3d968589d8 5249 || \
Kojto 90:cb3d968589d8 5250 (((INSTANCE) == TIM3) && \
Kojto 90:cb3d968589d8 5251 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 90:cb3d968589d8 5252 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 90:cb3d968589d8 5253 ((CHANNEL) == TIM_CHANNEL_3) || \
Kojto 90:cb3d968589d8 5254 ((CHANNEL) == TIM_CHANNEL_4))) \
Kojto 90:cb3d968589d8 5255 || \
Kojto 90:cb3d968589d8 5256 (((INSTANCE) == TIM14) && \
Kojto 90:cb3d968589d8 5257 (((CHANNEL) == TIM_CHANNEL_1))) \
Kojto 90:cb3d968589d8 5258 || \
Kojto 90:cb3d968589d8 5259 (((INSTANCE) == TIM15) && \
Kojto 90:cb3d968589d8 5260 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 90:cb3d968589d8 5261 ((CHANNEL) == TIM_CHANNEL_2))) \
Kojto 90:cb3d968589d8 5262 || \
Kojto 90:cb3d968589d8 5263 (((INSTANCE) == TIM16) && \
Kojto 90:cb3d968589d8 5264 (((CHANNEL) == TIM_CHANNEL_1))) \
Kojto 90:cb3d968589d8 5265 || \
Kojto 90:cb3d968589d8 5266 (((INSTANCE) == TIM17) && \
Kojto 90:cb3d968589d8 5267 (((CHANNEL) == TIM_CHANNEL_1))))
Kojto 90:cb3d968589d8 5268
Kojto 90:cb3d968589d8 5269 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
Kojto 90:cb3d968589d8 5270 ((((INSTANCE) == TIM1) && \
Kojto 90:cb3d968589d8 5271 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 90:cb3d968589d8 5272 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 90:cb3d968589d8 5273 ((CHANNEL) == TIM_CHANNEL_3))) \
Kojto 90:cb3d968589d8 5274 || \
Kojto 90:cb3d968589d8 5275 (((INSTANCE) == TIM15) && \
Kojto 90:cb3d968589d8 5276 ((CHANNEL) == TIM_CHANNEL_1)) \
Kojto 90:cb3d968589d8 5277 || \
Kojto 90:cb3d968589d8 5278 (((INSTANCE) == TIM16) && \
Kojto 90:cb3d968589d8 5279 ((CHANNEL) == TIM_CHANNEL_1)) \
Kojto 90:cb3d968589d8 5280 || \
Kojto 90:cb3d968589d8 5281 (((INSTANCE) == TIM17) && \
Kojto 90:cb3d968589d8 5282 ((CHANNEL) == TIM_CHANNEL_1)))
Kojto 90:cb3d968589d8 5283
Kojto 90:cb3d968589d8 5284 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 5285 (((INSTANCE) == TIM1) || \
Kojto 90:cb3d968589d8 5286 ((INSTANCE) == TIM3))
Kojto 90:cb3d968589d8 5287
Kojto 90:cb3d968589d8 5288 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 5289 (((INSTANCE) == TIM1) || \
Kojto 90:cb3d968589d8 5290 ((INSTANCE) == TIM15) || \
Kojto 90:cb3d968589d8 5291 ((INSTANCE) == TIM16) || \
Kojto 90:cb3d968589d8 5292 ((INSTANCE) == TIM17))
Kojto 90:cb3d968589d8 5293
Kojto 90:cb3d968589d8 5294 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 5295 (((INSTANCE) == TIM1) || \
Kojto 90:cb3d968589d8 5296 ((INSTANCE) == TIM3) || \
Kojto 90:cb3d968589d8 5297 ((INSTANCE) == TIM14) || \
Kojto 90:cb3d968589d8 5298 ((INSTANCE) == TIM15) || \
Kojto 90:cb3d968589d8 5299 ((INSTANCE) == TIM16) || \
Kojto 90:cb3d968589d8 5300 ((INSTANCE) == TIM17))
Kojto 90:cb3d968589d8 5301
Kojto 90:cb3d968589d8 5302 #define IS_TIM_DMA_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 5303 (((INSTANCE) == TIM1) || \
Kojto 90:cb3d968589d8 5304 ((INSTANCE) == TIM3) || \
Kojto 90:cb3d968589d8 5305 ((INSTANCE) == TIM6) || \
Kojto 90:cb3d968589d8 5306 ((INSTANCE) == TIM15) || \
Kojto 90:cb3d968589d8 5307 ((INSTANCE) == TIM16) || \
Kojto 90:cb3d968589d8 5308 ((INSTANCE) == TIM17))
Kojto 90:cb3d968589d8 5309
Kojto 90:cb3d968589d8 5310 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 5311 (((INSTANCE) == TIM1) || \
Kojto 90:cb3d968589d8 5312 ((INSTANCE) == TIM3) || \
Kojto 90:cb3d968589d8 5313 ((INSTANCE) == TIM15) || \
Kojto 90:cb3d968589d8 5314 ((INSTANCE) == TIM16) || \
Kojto 90:cb3d968589d8 5315 ((INSTANCE) == TIM17))
Kojto 90:cb3d968589d8 5316
Kojto 90:cb3d968589d8 5317 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 5318 (((INSTANCE) == TIM1) || \
Kojto 90:cb3d968589d8 5319 ((INSTANCE) == TIM15) || \
Kojto 90:cb3d968589d8 5320 ((INSTANCE) == TIM16) || \
Kojto 90:cb3d968589d8 5321 ((INSTANCE) == TIM17))
Kojto 90:cb3d968589d8 5322
Kojto 90:cb3d968589d8 5323 #define IS_TIM_REMAP_INSTANCE(INSTANCE)\
Kojto 90:cb3d968589d8 5324 ((INSTANCE) == TIM14)
Kojto 122:f9eeca106725 5325
Kojto 90:cb3d968589d8 5326 /******************** USART Instances : Synchronous mode **********************/
Kojto 90:cb3d968589d8 5327 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 90:cb3d968589d8 5328 ((INSTANCE) == USART2))
Kojto 90:cb3d968589d8 5329
Kojto 90:cb3d968589d8 5330 /******************** USART Instances : auto Baud rate detection **************/
Kojto 90:cb3d968589d8 5331 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
Kojto 90:cb3d968589d8 5332
Kojto 90:cb3d968589d8 5333 /******************** UART Instances : Asynchronous mode **********************/
Kojto 90:cb3d968589d8 5334 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 90:cb3d968589d8 5335 ((INSTANCE) == USART2))
Kojto 90:cb3d968589d8 5336
Kojto 90:cb3d968589d8 5337 /******************** UART Instances : Half-Duplex mode **********************/
Kojto 90:cb3d968589d8 5338 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 90:cb3d968589d8 5339 ((INSTANCE) == USART2))
Kojto 90:cb3d968589d8 5340
Kojto 90:cb3d968589d8 5341 /****************** UART Instances : Hardware Flow control ********************/
Kojto 90:cb3d968589d8 5342 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 90:cb3d968589d8 5343 ((INSTANCE) == USART2))
Kojto 90:cb3d968589d8 5344
Kojto 90:cb3d968589d8 5345 /****************** UART Instances : Driver enable detection ********************/
Kojto 90:cb3d968589d8 5346 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 90:cb3d968589d8 5347 ((INSTANCE) == USART2))
Kojto 122:f9eeca106725 5348
Kojto 90:cb3d968589d8 5349 /****************************** WWDG Instances ********************************/
Kojto 90:cb3d968589d8 5350 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
Kojto 90:cb3d968589d8 5351
Kojto 90:cb3d968589d8 5352 /**
Kojto 90:cb3d968589d8 5353 * @}
Kojto 90:cb3d968589d8 5354 */
Kojto 90:cb3d968589d8 5355
Kojto 90:cb3d968589d8 5356
Kojto 90:cb3d968589d8 5357 /******************************************************************************/
Kojto 90:cb3d968589d8 5358 /* For a painless codes migration between the STM32F0xx device product */
Kojto 90:cb3d968589d8 5359 /* lines, the aliases defined below are put in place to overcome the */
Kojto 90:cb3d968589d8 5360 /* differences in the interrupt handlers and IRQn definitions. */
Kojto 90:cb3d968589d8 5361 /* No need to update developed interrupt code when moving across */
Kojto 90:cb3d968589d8 5362 /* product lines within the same STM32F0 Family */
Kojto 90:cb3d968589d8 5363 /******************************************************************************/
Kojto 90:cb3d968589d8 5364
Kojto 90:cb3d968589d8 5365 /* Aliases for __IRQn */
Kojto 122:f9eeca106725 5366 #define ADC1_COMP_IRQn ADC1_IRQn
Kojto 122:f9eeca106725 5367 #define DMA1_Ch1_IRQn DMA1_Channel1_IRQn
Kojto 122:f9eeca106725 5368 #define DMA1_Ch2_3_DMA2_Ch1_2_IRQn DMA1_Channel2_3_IRQn
Kojto 122:f9eeca106725 5369 #define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn
Kojto 122:f9eeca106725 5370 #define DMA1_Ch4_7_DMA2_Ch3_5_IRQn DMA1_Channel4_5_IRQn
Kojto 122:f9eeca106725 5371 #define RCC_CRS_IRQn RCC_IRQn
Kojto 122:f9eeca106725 5372 #define TIM6_DAC_IRQn TIM6_IRQn
Kojto 122:f9eeca106725 5373
Kojto 90:cb3d968589d8 5374
Kojto 90:cb3d968589d8 5375 /* Aliases for __IRQHandler */
Kojto 122:f9eeca106725 5376 #define ADC1_COMP_IRQHandler ADC1_IRQHandler
Kojto 122:f9eeca106725 5377 #define DMA1_Ch1_IRQHandler DMA1_Channel1_IRQHandler
Kojto 122:f9eeca106725 5378 #define DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler DMA1_Channel2_3_IRQHandler
Kojto 122:f9eeca106725 5379 #define DMA1_Channel4_5_6_7_IRQHandler DMA1_Channel4_5_IRQHandler
Kojto 122:f9eeca106725 5380 #define DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler DMA1_Channel4_5_IRQHandler
Kojto 122:f9eeca106725 5381 #define RCC_CRS_IRQHandler RCC_IRQHandler
Kojto 122:f9eeca106725 5382 #define TIM6_DAC_IRQHandler TIM6_IRQHandler
Kojto 122:f9eeca106725 5383
Kojto 90:cb3d968589d8 5384
Kojto 90:cb3d968589d8 5385 #ifdef __cplusplus
Kojto 90:cb3d968589d8 5386 }
Kojto 90:cb3d968589d8 5387 #endif /* __cplusplus */
Kojto 90:cb3d968589d8 5388
Kojto 90:cb3d968589d8 5389 #endif /* __STM32F030x8_H */
Kojto 90:cb3d968589d8 5390
Kojto 90:cb3d968589d8 5391 /**
Kojto 90:cb3d968589d8 5392 * @}
Kojto 90:cb3d968589d8 5393 */
Kojto 90:cb3d968589d8 5394
Kojto 90:cb3d968589d8 5395 /**
Kojto 90:cb3d968589d8 5396 * @}
Kojto 90:cb3d968589d8 5397 */
Kojto 90:cb3d968589d8 5398
Kojto 90:cb3d968589d8 5399 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/