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Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

TARGET_MTS_MDOT_F405RG/stm32f4xx_hal_dma.h@122:f9eeca106725, 2016-07-07 (annotated)

Committer:
Kojto
Date:
Thu Jul 07 14:34:11 2016 +0100
Revision:
122:f9eeca106725
Parent:
110:165afa46840b 
Release 122 of the mbed library



Changes:

- new targets - Nucleo L432KC, Beetle, Nucleo F446ZE, Nucleo L011K4

- Thread safety addition - mbed API should contain a statement about thread safety

- critical section API addition

- CAS API (core_util_atomic_incr/decr)

- DEVICE_ are generated from targets.json file, device.h deprecated

- Callback replaces FunctionPointer to provide std like interface

- mbed HAL API docs improvements

- toolchain - prexif attributes with MBED_

            - add new attributes - packed, weak, forcedinline, align

- target.json - contains targets definitions

- ST - L1XX - Cube update to 1.5

     - SPI clock selection fix (clock from APB domain)

     - F7 - Cube update v1.4.0

     - L0 -  baudrate init fix

     - L1 - Cube update v1.5

     - F3 - baudrate init fix, 3 targets CAN support

     - F4 - Cube update v1.12.0, 3 targets CAN support

     - L4XX - Cube update v1.5.1

     - F0 - update Cube to v1.5.0

     - L4 - 2 targets (L476RG/VG) CAN support

- NXP - pwm clock fix for KSDK2 MCU

      - LPC2368 - remove ARM toolchain support - due to regression

      - KSDK2 - fix SPI , I2C address and repeat start

- Silabs - some fixes backported from mbed 3

- Renesas - RZ_A1H - SystemCoreClockUpdate addition

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 92:4fc01daae5a5 1 /**
bogdanm 92:4fc01daae5a5 2 ******************************************************************************
bogdanm 92:4fc01daae5a5 3 * @file stm32f4xx_hal_dma.h
bogdanm 92:4fc01daae5a5 4 * @author MCD Application Team
Kojto 122:f9eeca106725 5 * @version V1.5.0
Kojto 122:f9eeca106725 6 * @date 06-May-2016
bogdanm 92:4fc01daae5a5 7 * @brief Header file of DMA HAL module.
bogdanm 92:4fc01daae5a5 8 ******************************************************************************
bogdanm 92:4fc01daae5a5 9 * @attention
bogdanm 92:4fc01daae5a5 10 *
Kojto 122:f9eeca106725 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
bogdanm 92:4fc01daae5a5 12 *
bogdanm 92:4fc01daae5a5 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 92:4fc01daae5a5 14 * are permitted provided that the following conditions are met:
bogdanm 92:4fc01daae5a5 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 92:4fc01daae5a5 16 * this list of conditions and the following disclaimer.
bogdanm 92:4fc01daae5a5 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 92:4fc01daae5a5 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 92:4fc01daae5a5 19 * and/or other materials provided with the distribution.
bogdanm 92:4fc01daae5a5 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 92:4fc01daae5a5 21 * may be used to endorse or promote products derived from this software
bogdanm 92:4fc01daae5a5 22 * without specific prior written permission.
bogdanm 92:4fc01daae5a5 23 *
bogdanm 92:4fc01daae5a5 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 92:4fc01daae5a5 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 92:4fc01daae5a5 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 92:4fc01daae5a5 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 92:4fc01daae5a5 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 92:4fc01daae5a5 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 92:4fc01daae5a5 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 92:4fc01daae5a5 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 92:4fc01daae5a5 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 92:4fc01daae5a5 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 92:4fc01daae5a5 34 *
bogdanm 92:4fc01daae5a5 35 ******************************************************************************
bogdanm 92:4fc01daae5a5 36 */
bogdanm 92:4fc01daae5a5 37
bogdanm 92:4fc01daae5a5 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 92:4fc01daae5a5 39 #ifndef __STM32F4xx_HAL_DMA_H
bogdanm 92:4fc01daae5a5 40 #define __STM32F4xx_HAL_DMA_H
bogdanm 92:4fc01daae5a5 41
bogdanm 92:4fc01daae5a5 42 #ifdef __cplusplus
bogdanm 92:4fc01daae5a5 43 extern "C" {
bogdanm 92:4fc01daae5a5 44 #endif
bogdanm 92:4fc01daae5a5 45
bogdanm 92:4fc01daae5a5 46 /* Includes ------------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 47 #include "stm32f4xx_hal_def.h"
bogdanm 92:4fc01daae5a5 48
bogdanm 92:4fc01daae5a5 49 /** @addtogroup STM32F4xx_HAL_Driver
bogdanm 92:4fc01daae5a5 50 * @{
bogdanm 92:4fc01daae5a5 51 */
bogdanm 92:4fc01daae5a5 52
bogdanm 92:4fc01daae5a5 53 /** @addtogroup DMA
bogdanm 92:4fc01daae5a5 54 * @{
bogdanm 92:4fc01daae5a5 55 */
bogdanm 92:4fc01daae5a5 56
bogdanm 92:4fc01daae5a5 57 /* Exported types ------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 58
Kojto 99:dbbf35b96557 59 /** @defgroup DMA_Exported_Types DMA Exported Types
Kojto 99:dbbf35b96557 60 * @brief DMA Exported Types
Kojto 99:dbbf35b96557 61 * @{
Kojto 99:dbbf35b96557 62 */
Kojto 99:dbbf35b96557 63
bogdanm 92:4fc01daae5a5 64 /**
bogdanm 92:4fc01daae5a5 65 * @brief DMA Configuration Structure definition
bogdanm 92:4fc01daae5a5 66 */
bogdanm 92:4fc01daae5a5 67 typedef struct
bogdanm 92:4fc01daae5a5 68 {
bogdanm 92:4fc01daae5a5 69 uint32_t Channel; /*!< Specifies the channel used for the specified stream.
bogdanm 92:4fc01daae5a5 70 This parameter can be a value of @ref DMA_Channel_selection */
bogdanm 92:4fc01daae5a5 71
bogdanm 92:4fc01daae5a5 72 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
bogdanm 92:4fc01daae5a5 73 from memory to memory or from peripheral to memory.
bogdanm 92:4fc01daae5a5 74 This parameter can be a value of @ref DMA_Data_transfer_direction */
bogdanm 92:4fc01daae5a5 75
bogdanm 92:4fc01daae5a5 76 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
bogdanm 92:4fc01daae5a5 77 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
bogdanm 92:4fc01daae5a5 78
bogdanm 92:4fc01daae5a5 79 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
bogdanm 92:4fc01daae5a5 80 This parameter can be a value of @ref DMA_Memory_incremented_mode */
bogdanm 92:4fc01daae5a5 81
bogdanm 92:4fc01daae5a5 82 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
bogdanm 92:4fc01daae5a5 83 This parameter can be a value of @ref DMA_Peripheral_data_size */
bogdanm 92:4fc01daae5a5 84
bogdanm 92:4fc01daae5a5 85 uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
bogdanm 92:4fc01daae5a5 86 This parameter can be a value of @ref DMA_Memory_data_size */
bogdanm 92:4fc01daae5a5 87
bogdanm 92:4fc01daae5a5 88 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx.
bogdanm 92:4fc01daae5a5 89 This parameter can be a value of @ref DMA_mode
bogdanm 92:4fc01daae5a5 90 @note The circular buffer mode cannot be used if the memory-to-memory
bogdanm 92:4fc01daae5a5 91 data transfer is configured on the selected Stream */
bogdanm 92:4fc01daae5a5 92
bogdanm 92:4fc01daae5a5 93 uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx.
bogdanm 92:4fc01daae5a5 94 This parameter can be a value of @ref DMA_Priority_level */
bogdanm 92:4fc01daae5a5 95
bogdanm 92:4fc01daae5a5 96 uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
bogdanm 92:4fc01daae5a5 97 This parameter can be a value of @ref DMA_FIFO_direct_mode
bogdanm 92:4fc01daae5a5 98 @note The Direct mode (FIFO mode disabled) cannot be used if the
bogdanm 92:4fc01daae5a5 99 memory-to-memory data transfer is configured on the selected stream */
bogdanm 92:4fc01daae5a5 100
bogdanm 92:4fc01daae5a5 101 uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level.
bogdanm 92:4fc01daae5a5 102 This parameter can be a value of @ref DMA_FIFO_threshold_level */
bogdanm 92:4fc01daae5a5 103
bogdanm 92:4fc01daae5a5 104 uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
Kojto 99:dbbf35b96557 105 It specifies the amount of data to be transferred in a single non interruptible
bogdanm 92:4fc01daae5a5 106 transaction.
bogdanm 92:4fc01daae5a5 107 This parameter can be a value of @ref DMA_Memory_burst
bogdanm 92:4fc01daae5a5 108 @note The burst mode is possible only if the address Increment mode is enabled. */
bogdanm 92:4fc01daae5a5 109
bogdanm 92:4fc01daae5a5 110 uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
Kojto 122:f9eeca106725 111 It specifies the amount of data to be transferred in a single non interruptible
bogdanm 92:4fc01daae5a5 112 transaction.
bogdanm 92:4fc01daae5a5 113 This parameter can be a value of @ref DMA_Peripheral_burst
bogdanm 92:4fc01daae5a5 114 @note The burst mode is possible only if the address Increment mode is enabled. */
bogdanm 92:4fc01daae5a5 115 }DMA_InitTypeDef;
bogdanm 92:4fc01daae5a5 116
Kojto 99:dbbf35b96557 117
bogdanm 92:4fc01daae5a5 118 /**
bogdanm 92:4fc01daae5a5 119 * @brief HAL DMA State structures definition
bogdanm 92:4fc01daae5a5 120 */
bogdanm 92:4fc01daae5a5 121 typedef enum
bogdanm 92:4fc01daae5a5 122 {
Kojto 122:f9eeca106725 123 HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
Kojto 122:f9eeca106725 124 HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */
Kojto 122:f9eeca106725 125 HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
Kojto 122:f9eeca106725 126 HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */
Kojto 122:f9eeca106725 127 HAL_DMA_STATE_ERROR = 0x04U, /*!< DMA error state */
Kojto 122:f9eeca106725 128 HAL_DMA_STATE_ABORT = 0x05U, /*!< DMA Abort state */
bogdanm 92:4fc01daae5a5 129 }HAL_DMA_StateTypeDef;
bogdanm 92:4fc01daae5a5 130
bogdanm 92:4fc01daae5a5 131 /**
bogdanm 92:4fc01daae5a5 132 * @brief HAL DMA Error Code structure definition
bogdanm 92:4fc01daae5a5 133 */
bogdanm 92:4fc01daae5a5 134 typedef enum
bogdanm 92:4fc01daae5a5 135 {
Kojto 122:f9eeca106725 136 HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
Kojto 122:f9eeca106725 137 HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */
bogdanm 92:4fc01daae5a5 138 }HAL_DMA_LevelCompleteTypeDef;
bogdanm 92:4fc01daae5a5 139
bogdanm 92:4fc01daae5a5 140 /**
Kojto 122:f9eeca106725 141 * @brief HAL DMA Error Code structure definition
Kojto 122:f9eeca106725 142 */
Kojto 122:f9eeca106725 143 typedef enum
Kojto 122:f9eeca106725 144 {
Kojto 122:f9eeca106725 145 HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */
Kojto 122:f9eeca106725 146 HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half Transfer */
Kojto 122:f9eeca106725 147 HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U, /*!< M1 Full Transfer */
Kojto 122:f9eeca106725 148 HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U, /*!< M1 Half Transfer */
Kojto 122:f9eeca106725 149 HAL_DMA_XFER_ERROR_CB_ID = 0x04U, /*!< Error */
Kojto 122:f9eeca106725 150 HAL_DMA_XFER_ABORT_CB_ID = 0x05U, /*!< Abort */
Kojto 122:f9eeca106725 151 HAL_DMA_XFER_ALL_CB_ID = 0x06U /*!< All */
Kojto 122:f9eeca106725 152 }HAL_DMA_CallbackIDTypeDef;
Kojto 122:f9eeca106725 153
Kojto 122:f9eeca106725 154 /**
bogdanm 92:4fc01daae5a5 155 * @brief DMA handle Structure definition
bogdanm 92:4fc01daae5a5 156 */
bogdanm 92:4fc01daae5a5 157 typedef struct __DMA_HandleTypeDef
bogdanm 92:4fc01daae5a5 158 {
bogdanm 92:4fc01daae5a5 159 DMA_Stream_TypeDef *Instance; /*!< Register base address */
bogdanm 92:4fc01daae5a5 160
bogdanm 92:4fc01daae5a5 161 DMA_InitTypeDef Init; /*!< DMA communication parameters */
bogdanm 92:4fc01daae5a5 162
bogdanm 92:4fc01daae5a5 163 HAL_LockTypeDef Lock; /*!< DMA locking object */
bogdanm 92:4fc01daae5a5 164
bogdanm 92:4fc01daae5a5 165 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
bogdanm 92:4fc01daae5a5 166
Kojto 122:f9eeca106725 167 void *Parent; /*!< Parent object state */
bogdanm 92:4fc01daae5a5 168
bogdanm 92:4fc01daae5a5 169 void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
bogdanm 92:4fc01daae5a5 170
bogdanm 92:4fc01daae5a5 171 void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
bogdanm 92:4fc01daae5a5 172
bogdanm 92:4fc01daae5a5 173 void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */
Kojto 122:f9eeca106725 174
Kojto 122:f9eeca106725 175 void (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Half complete Memory1 callback */
Kojto 122:f9eeca106725 176
bogdanm 92:4fc01daae5a5 177 void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
Kojto 122:f9eeca106725 178
Kojto 122:f9eeca106725 179 void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Abort callback */
bogdanm 92:4fc01daae5a5 180
Kojto 122:f9eeca106725 181 __IO uint32_t ErrorCode; /*!< DMA Error code */
Kojto 122:f9eeca106725 182
Kojto 110:165afa46840b 183 uint32_t StreamBaseAddress; /*!< DMA Stream Base Address */
Kojto 110:165afa46840b 184
Kojto 122:f9eeca106725 185 uint32_t StreamIndex; /*!< DMA Stream Index */
Kojto 122:f9eeca106725 186
bogdanm 92:4fc01daae5a5 187 }DMA_HandleTypeDef;
bogdanm 92:4fc01daae5a5 188
Kojto 99:dbbf35b96557 189 /**
Kojto 99:dbbf35b96557 190 * @}
Kojto 99:dbbf35b96557 191 */
Kojto 99:dbbf35b96557 192
bogdanm 92:4fc01daae5a5 193 /* Exported constants --------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 194
Kojto 99:dbbf35b96557 195 /** @defgroup DMA_Exported_Constants DMA Exported Constants
Kojto 99:dbbf35b96557 196 * @brief DMA Exported constants
bogdanm 92:4fc01daae5a5 197 * @{
bogdanm 92:4fc01daae5a5 198 */
bogdanm 92:4fc01daae5a5 199
Kojto 99:dbbf35b96557 200 /** @defgroup DMA_Error_Code DMA Error Code
Kojto 99:dbbf35b96557 201 * @brief DMA Error Code
bogdanm 92:4fc01daae5a5 202 * @{
bogdanm 92:4fc01daae5a5 203 */
Kojto 122:f9eeca106725 204 #define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
Kojto 122:f9eeca106725 205 #define HAL_DMA_ERROR_TE ((uint32_t)0x00000001U) /*!< Transfer error */
Kojto 122:f9eeca106725 206 #define HAL_DMA_ERROR_FE ((uint32_t)0x00000002U) /*!< FIFO error */
Kojto 122:f9eeca106725 207 #define HAL_DMA_ERROR_DME ((uint32_t)0x00000004U) /*!< Direct Mode error */
Kojto 122:f9eeca106725 208 #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout error */
Kojto 122:f9eeca106725 209 #define HAL_DMA_ERROR_PARAM ((uint32_t)0x00000040U) /*!< Parameter error */
Kojto 122:f9eeca106725 210 #define HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000080U) /*!< Abort requested with no Xfer ongoing */
Kojto 122:f9eeca106725 211 #define HAL_DMA_ERROR_NOT_SUPPORTED ((uint32_t)0x00000100U) /*!< Not supported mode */
bogdanm 92:4fc01daae5a5 212 /**
bogdanm 92:4fc01daae5a5 213 * @}
bogdanm 92:4fc01daae5a5 214 */
bogdanm 92:4fc01daae5a5 215
Kojto 99:dbbf35b96557 216 /** @defgroup DMA_Channel_selection DMA Channel selection
Kojto 99:dbbf35b96557 217 * @brief DMA channel selection
bogdanm 92:4fc01daae5a5 218 * @{
bogdanm 92:4fc01daae5a5 219 */
Kojto 122:f9eeca106725 220 #define DMA_CHANNEL_0 ((uint32_t)0x00000000U) /*!< DMA Channel 0 */
Kojto 122:f9eeca106725 221 #define DMA_CHANNEL_1 ((uint32_t)0x02000000U) /*!< DMA Channel 1 */
Kojto 122:f9eeca106725 222 #define DMA_CHANNEL_2 ((uint32_t)0x04000000U) /*!< DMA Channel 2 */
Kojto 122:f9eeca106725 223 #define DMA_CHANNEL_3 ((uint32_t)0x06000000U) /*!< DMA Channel 3 */
Kojto 122:f9eeca106725 224 #define DMA_CHANNEL_4 ((uint32_t)0x08000000U) /*!< DMA Channel 4 */
Kojto 122:f9eeca106725 225 #define DMA_CHANNEL_5 ((uint32_t)0x0A000000U) /*!< DMA Channel 5 */
Kojto 122:f9eeca106725 226 #define DMA_CHANNEL_6 ((uint32_t)0x0C000000U) /*!< DMA Channel 6 */
Kojto 122:f9eeca106725 227 #define DMA_CHANNEL_7 ((uint32_t)0x0E000000U) /*!< DMA Channel 7 */
bogdanm 92:4fc01daae5a5 228 /**
bogdanm 92:4fc01daae5a5 229 * @}
bogdanm 92:4fc01daae5a5 230 */
bogdanm 92:4fc01daae5a5 231
Kojto 99:dbbf35b96557 232 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
Kojto 99:dbbf35b96557 233 * @brief DMA data transfer direction
bogdanm 92:4fc01daae5a5 234 * @{
bogdanm 92:4fc01daae5a5 235 */
Kojto 122:f9eeca106725 236 #define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000U) /*!< Peripheral to memory direction */
bogdanm 92:4fc01daae5a5 237 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */
bogdanm 92:4fc01daae5a5 238 #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */
bogdanm 92:4fc01daae5a5 239 /**
bogdanm 92:4fc01daae5a5 240 * @}
Kojto 122:f9eeca106725 241 */
bogdanm 92:4fc01daae5a5 242
Kojto 99:dbbf35b96557 243 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
Kojto 99:dbbf35b96557 244 * @brief DMA peripheral incremented mode
bogdanm 92:4fc01daae5a5 245 * @{
bogdanm 92:4fc01daae5a5 246 */
bogdanm 92:4fc01daae5a5 247 #define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */
Kojto 122:f9eeca106725 248 #define DMA_PINC_DISABLE ((uint32_t)0x00000000U) /*!< Peripheral increment mode disable */
bogdanm 92:4fc01daae5a5 249 /**
bogdanm 92:4fc01daae5a5 250 * @}
bogdanm 92:4fc01daae5a5 251 */
bogdanm 92:4fc01daae5a5 252
Kojto 99:dbbf35b96557 253 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
Kojto 99:dbbf35b96557 254 * @brief DMA memory incremented mode
bogdanm 92:4fc01daae5a5 255 * @{
bogdanm 92:4fc01daae5a5 256 */
bogdanm 92:4fc01daae5a5 257 #define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */
Kojto 122:f9eeca106725 258 #define DMA_MINC_DISABLE ((uint32_t)0x00000000U) /*!< Memory increment mode disable */
bogdanm 92:4fc01daae5a5 259 /**
bogdanm 92:4fc01daae5a5 260 * @}
bogdanm 92:4fc01daae5a5 261 */
bogdanm 92:4fc01daae5a5 262
Kojto 99:dbbf35b96557 263 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
Kojto 99:dbbf35b96557 264 * @brief DMA peripheral data size
bogdanm 92:4fc01daae5a5 265 * @{
bogdanm 92:4fc01daae5a5 266 */
Kojto 122:f9eeca106725 267 #define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Peripheral data alignment: Byte */
bogdanm 92:4fc01daae5a5 268 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */
bogdanm 92:4fc01daae5a5 269 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */
bogdanm 92:4fc01daae5a5 270 /**
bogdanm 92:4fc01daae5a5 271 * @}
bogdanm 92:4fc01daae5a5 272 */
bogdanm 92:4fc01daae5a5 273
Kojto 99:dbbf35b96557 274 /** @defgroup DMA_Memory_data_size DMA Memory data size
Kojto 99:dbbf35b96557 275 * @brief DMA memory data size
bogdanm 92:4fc01daae5a5 276 * @{
bogdanm 92:4fc01daae5a5 277 */
Kojto 122:f9eeca106725 278 #define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Memory data alignment: Byte */
bogdanm 92:4fc01daae5a5 279 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */
bogdanm 92:4fc01daae5a5 280 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */
bogdanm 92:4fc01daae5a5 281 /**
bogdanm 92:4fc01daae5a5 282 * @}
bogdanm 92:4fc01daae5a5 283 */
bogdanm 92:4fc01daae5a5 284
Kojto 99:dbbf35b96557 285 /** @defgroup DMA_mode DMA mode
Kojto 99:dbbf35b96557 286 * @brief DMA mode
bogdanm 92:4fc01daae5a5 287 * @{
bogdanm 92:4fc01daae5a5 288 */
Kojto 122:f9eeca106725 289 #define DMA_NORMAL ((uint32_t)0x00000000U) /*!< Normal mode */
bogdanm 92:4fc01daae5a5 290 #define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */
bogdanm 92:4fc01daae5a5 291 #define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */
bogdanm 92:4fc01daae5a5 292 /**
bogdanm 92:4fc01daae5a5 293 * @}
bogdanm 92:4fc01daae5a5 294 */
bogdanm 92:4fc01daae5a5 295
Kojto 99:dbbf35b96557 296 /** @defgroup DMA_Priority_level DMA Priority level
Kojto 99:dbbf35b96557 297 * @brief DMA priority levels
bogdanm 92:4fc01daae5a5 298 * @{
bogdanm 92:4fc01daae5a5 299 */
Kojto 122:f9eeca106725 300 #define DMA_PRIORITY_LOW ((uint32_t)0x00000000U) /*!< Priority level: Low */
bogdanm 92:4fc01daae5a5 301 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */
bogdanm 92:4fc01daae5a5 302 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */
bogdanm 92:4fc01daae5a5 303 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */
bogdanm 92:4fc01daae5a5 304 /**
bogdanm 92:4fc01daae5a5 305 * @}
bogdanm 92:4fc01daae5a5 306 */
bogdanm 92:4fc01daae5a5 307
Kojto 99:dbbf35b96557 308 /** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode
Kojto 99:dbbf35b96557 309 * @brief DMA FIFO direct mode
bogdanm 92:4fc01daae5a5 310 * @{
bogdanm 92:4fc01daae5a5 311 */
Kojto 122:f9eeca106725 312 #define DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000U) /*!< FIFO mode disable */
bogdanm 92:4fc01daae5a5 313 #define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */
bogdanm 92:4fc01daae5a5 314 /**
bogdanm 92:4fc01daae5a5 315 * @}
bogdanm 92:4fc01daae5a5 316 */
bogdanm 92:4fc01daae5a5 317
Kojto 99:dbbf35b96557 318 /** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level
Kojto 99:dbbf35b96557 319 * @brief DMA FIFO level
bogdanm 92:4fc01daae5a5 320 * @{
bogdanm 92:4fc01daae5a5 321 */
Kojto 122:f9eeca106725 322 #define DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000U) /*!< FIFO threshold 1 quart full configuration */
bogdanm 92:4fc01daae5a5 323 #define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */
bogdanm 92:4fc01daae5a5 324 #define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */
bogdanm 92:4fc01daae5a5 325 #define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */
bogdanm 92:4fc01daae5a5 326 /**
bogdanm 92:4fc01daae5a5 327 * @}
bogdanm 92:4fc01daae5a5 328 */
bogdanm 92:4fc01daae5a5 329
Kojto 99:dbbf35b96557 330 /** @defgroup DMA_Memory_burst DMA Memory burst
Kojto 99:dbbf35b96557 331 * @brief DMA memory burst
bogdanm 92:4fc01daae5a5 332 * @{
bogdanm 92:4fc01daae5a5 333 */
Kojto 122:f9eeca106725 334 #define DMA_MBURST_SINGLE ((uint32_t)0x00000000U)
bogdanm 92:4fc01daae5a5 335 #define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0)
bogdanm 92:4fc01daae5a5 336 #define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1)
bogdanm 92:4fc01daae5a5 337 #define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST)
bogdanm 92:4fc01daae5a5 338 /**
bogdanm 92:4fc01daae5a5 339 * @}
bogdanm 92:4fc01daae5a5 340 */
bogdanm 92:4fc01daae5a5 341
Kojto 99:dbbf35b96557 342 /** @defgroup DMA_Peripheral_burst DMA Peripheral burst
Kojto 99:dbbf35b96557 343 * @brief DMA peripheral burst
bogdanm 92:4fc01daae5a5 344 * @{
bogdanm 92:4fc01daae5a5 345 */
Kojto 122:f9eeca106725 346 #define DMA_PBURST_SINGLE ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 347 #define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0)
Kojto 122:f9eeca106725 348 #define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1)
Kojto 122:f9eeca106725 349 #define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST)
bogdanm 92:4fc01daae5a5 350 /**
bogdanm 92:4fc01daae5a5 351 * @}
bogdanm 92:4fc01daae5a5 352 */
bogdanm 92:4fc01daae5a5 353
Kojto 99:dbbf35b96557 354 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
Kojto 99:dbbf35b96557 355 * @brief DMA interrupts definition
bogdanm 92:4fc01daae5a5 356 * @{
bogdanm 92:4fc01daae5a5 357 */
bogdanm 92:4fc01daae5a5 358 #define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE)
bogdanm 92:4fc01daae5a5 359 #define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE)
bogdanm 92:4fc01daae5a5 360 #define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE)
bogdanm 92:4fc01daae5a5 361 #define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE)
Kojto 122:f9eeca106725 362 #define DMA_IT_FE ((uint32_t)0x00000080U)
bogdanm 92:4fc01daae5a5 363 /**
bogdanm 92:4fc01daae5a5 364 * @}
bogdanm 92:4fc01daae5a5 365 */
bogdanm 92:4fc01daae5a5 366
Kojto 99:dbbf35b96557 367 /** @defgroup DMA_flag_definitions DMA flag definitions
Kojto 99:dbbf35b96557 368 * @brief DMA flag definitions
bogdanm 92:4fc01daae5a5 369 * @{
bogdanm 92:4fc01daae5a5 370 */
Kojto 122:f9eeca106725 371 #define DMA_FLAG_FEIF0_4 ((uint32_t)0x00800001U)
Kojto 122:f9eeca106725 372 #define DMA_FLAG_DMEIF0_4 ((uint32_t)0x00800004U)
Kojto 122:f9eeca106725 373 #define DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008U)
Kojto 122:f9eeca106725 374 #define DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010U)
Kojto 122:f9eeca106725 375 #define DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020U)
Kojto 122:f9eeca106725 376 #define DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040U)
Kojto 122:f9eeca106725 377 #define DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100U)
Kojto 122:f9eeca106725 378 #define DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200U)
Kojto 122:f9eeca106725 379 #define DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400U)
Kojto 122:f9eeca106725 380 #define DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800U)
Kojto 122:f9eeca106725 381 #define DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000U)
Kojto 122:f9eeca106725 382 #define DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000U)
Kojto 122:f9eeca106725 383 #define DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000U)
Kojto 122:f9eeca106725 384 #define DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000U)
Kojto 122:f9eeca106725 385 #define DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000U)
Kojto 122:f9eeca106725 386 #define DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000U)
Kojto 122:f9eeca106725 387 #define DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000U)
Kojto 122:f9eeca106725 388 #define DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000U)
Kojto 122:f9eeca106725 389 #define DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000U)
Kojto 122:f9eeca106725 390 #define DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000U)
bogdanm 92:4fc01daae5a5 391 /**
bogdanm 92:4fc01daae5a5 392 * @}
bogdanm 92:4fc01daae5a5 393 */
Kojto 99:dbbf35b96557 394
bogdanm 92:4fc01daae5a5 395 /**
bogdanm 92:4fc01daae5a5 396 * @}
bogdanm 92:4fc01daae5a5 397 */
Kojto 99:dbbf35b96557 398
bogdanm 92:4fc01daae5a5 399 /* Exported macro ------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 400
bogdanm 92:4fc01daae5a5 401 /** @brief Reset DMA handle state
bogdanm 92:4fc01daae5a5 402 * @param __HANDLE__: specifies the DMA handle.
bogdanm 92:4fc01daae5a5 403 * @retval None
bogdanm 92:4fc01daae5a5 404 */
bogdanm 92:4fc01daae5a5 405 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
bogdanm 92:4fc01daae5a5 406
bogdanm 92:4fc01daae5a5 407 /**
bogdanm 92:4fc01daae5a5 408 * @brief Return the current DMA Stream FIFO filled level.
bogdanm 92:4fc01daae5a5 409 * @param __HANDLE__: DMA handle
bogdanm 92:4fc01daae5a5 410 * @retval The FIFO filling state.
bogdanm 92:4fc01daae5a5 411 * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full
bogdanm 92:4fc01daae5a5 412 * and not empty.
bogdanm 92:4fc01daae5a5 413 * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
bogdanm 92:4fc01daae5a5 414 * - DMA_FIFOStatus_HalfFull: if more than 1 half-full.
bogdanm 92:4fc01daae5a5 415 * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
bogdanm 92:4fc01daae5a5 416 * - DMA_FIFOStatus_Empty: when FIFO is empty
bogdanm 92:4fc01daae5a5 417 * - DMA_FIFOStatus_Full: when FIFO is full
bogdanm 92:4fc01daae5a5 418 */
bogdanm 92:4fc01daae5a5 419 #define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))
bogdanm 92:4fc01daae5a5 420
bogdanm 92:4fc01daae5a5 421 /**
bogdanm 92:4fc01daae5a5 422 * @brief Enable the specified DMA Stream.
bogdanm 92:4fc01daae5a5 423 * @param __HANDLE__: DMA handle
bogdanm 92:4fc01daae5a5 424 * @retval None
bogdanm 92:4fc01daae5a5 425 */
bogdanm 92:4fc01daae5a5 426 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN)
bogdanm 92:4fc01daae5a5 427
bogdanm 92:4fc01daae5a5 428 /**
bogdanm 92:4fc01daae5a5 429 * @brief Disable the specified DMA Stream.
bogdanm 92:4fc01daae5a5 430 * @param __HANDLE__: DMA handle
bogdanm 92:4fc01daae5a5 431 * @retval None
bogdanm 92:4fc01daae5a5 432 */
bogdanm 92:4fc01daae5a5 433 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN)
bogdanm 92:4fc01daae5a5 434
bogdanm 92:4fc01daae5a5 435 /* Interrupt & Flag management */
bogdanm 92:4fc01daae5a5 436
bogdanm 92:4fc01daae5a5 437 /**
bogdanm 92:4fc01daae5a5 438 * @brief Return the current DMA Stream transfer complete flag.
bogdanm 92:4fc01daae5a5 439 * @param __HANDLE__: DMA handle
bogdanm 92:4fc01daae5a5 440 * @retval The specified transfer complete flag index.
bogdanm 92:4fc01daae5a5 441 */
bogdanm 92:4fc01daae5a5 442 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
bogdanm 92:4fc01daae5a5 443 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
bogdanm 92:4fc01daae5a5 444 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
bogdanm 92:4fc01daae5a5 445 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
bogdanm 92:4fc01daae5a5 446 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
bogdanm 92:4fc01daae5a5 447 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
bogdanm 92:4fc01daae5a5 448 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
bogdanm 92:4fc01daae5a5 449 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
bogdanm 92:4fc01daae5a5 450 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
bogdanm 92:4fc01daae5a5 451 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
bogdanm 92:4fc01daae5a5 452 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
bogdanm 92:4fc01daae5a5 453 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
bogdanm 92:4fc01daae5a5 454 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
bogdanm 92:4fc01daae5a5 455 DMA_FLAG_TCIF3_7)
bogdanm 92:4fc01daae5a5 456
bogdanm 92:4fc01daae5a5 457 /**
bogdanm 92:4fc01daae5a5 458 * @brief Return the current DMA Stream half transfer complete flag.
bogdanm 92:4fc01daae5a5 459 * @param __HANDLE__: DMA handle
bogdanm 92:4fc01daae5a5 460 * @retval The specified half transfer complete flag index.
bogdanm 92:4fc01daae5a5 461 */
bogdanm 92:4fc01daae5a5 462 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
bogdanm 92:4fc01daae5a5 463 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
bogdanm 92:4fc01daae5a5 464 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
bogdanm 92:4fc01daae5a5 465 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
bogdanm 92:4fc01daae5a5 466 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
bogdanm 92:4fc01daae5a5 467 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
bogdanm 92:4fc01daae5a5 468 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
bogdanm 92:4fc01daae5a5 469 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
bogdanm 92:4fc01daae5a5 470 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
bogdanm 92:4fc01daae5a5 471 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
bogdanm 92:4fc01daae5a5 472 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
bogdanm 92:4fc01daae5a5 473 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
bogdanm 92:4fc01daae5a5 474 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
bogdanm 92:4fc01daae5a5 475 DMA_FLAG_HTIF3_7)
bogdanm 92:4fc01daae5a5 476
bogdanm 92:4fc01daae5a5 477 /**
bogdanm 92:4fc01daae5a5 478 * @brief Return the current DMA Stream transfer error flag.
bogdanm 92:4fc01daae5a5 479 * @param __HANDLE__: DMA handle
bogdanm 92:4fc01daae5a5 480 * @retval The specified transfer error flag index.
bogdanm 92:4fc01daae5a5 481 */
bogdanm 92:4fc01daae5a5 482 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
bogdanm 92:4fc01daae5a5 483 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
bogdanm 92:4fc01daae5a5 484 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
bogdanm 92:4fc01daae5a5 485 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
bogdanm 92:4fc01daae5a5 486 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
bogdanm 92:4fc01daae5a5 487 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
bogdanm 92:4fc01daae5a5 488 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
bogdanm 92:4fc01daae5a5 489 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
bogdanm 92:4fc01daae5a5 490 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
bogdanm 92:4fc01daae5a5 491 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
bogdanm 92:4fc01daae5a5 492 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
bogdanm 92:4fc01daae5a5 493 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
bogdanm 92:4fc01daae5a5 494 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
bogdanm 92:4fc01daae5a5 495 DMA_FLAG_TEIF3_7)
bogdanm 92:4fc01daae5a5 496
bogdanm 92:4fc01daae5a5 497 /**
bogdanm 92:4fc01daae5a5 498 * @brief Return the current DMA Stream FIFO error flag.
bogdanm 92:4fc01daae5a5 499 * @param __HANDLE__: DMA handle
bogdanm 92:4fc01daae5a5 500 * @retval The specified FIFO error flag index.
bogdanm 92:4fc01daae5a5 501 */
bogdanm 92:4fc01daae5a5 502 #define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\
bogdanm 92:4fc01daae5a5 503 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\
bogdanm 92:4fc01daae5a5 504 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\
bogdanm 92:4fc01daae5a5 505 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\
bogdanm 92:4fc01daae5a5 506 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\
bogdanm 92:4fc01daae5a5 507 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\
bogdanm 92:4fc01daae5a5 508 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\
bogdanm 92:4fc01daae5a5 509 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
bogdanm 92:4fc01daae5a5 510 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\
bogdanm 92:4fc01daae5a5 511 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\
bogdanm 92:4fc01daae5a5 512 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\
bogdanm 92:4fc01daae5a5 513 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\
bogdanm 92:4fc01daae5a5 514 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\
bogdanm 92:4fc01daae5a5 515 DMA_FLAG_FEIF3_7)
bogdanm 92:4fc01daae5a5 516
bogdanm 92:4fc01daae5a5 517 /**
bogdanm 92:4fc01daae5a5 518 * @brief Return the current DMA Stream direct mode error flag.
bogdanm 92:4fc01daae5a5 519 * @param __HANDLE__: DMA handle
bogdanm 92:4fc01daae5a5 520 * @retval The specified direct mode error flag index.
bogdanm 92:4fc01daae5a5 521 */
bogdanm 92:4fc01daae5a5 522 #define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\
bogdanm 92:4fc01daae5a5 523 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\
bogdanm 92:4fc01daae5a5 524 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\
bogdanm 92:4fc01daae5a5 525 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\
bogdanm 92:4fc01daae5a5 526 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\
bogdanm 92:4fc01daae5a5 527 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\
bogdanm 92:4fc01daae5a5 528 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\
bogdanm 92:4fc01daae5a5 529 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
bogdanm 92:4fc01daae5a5 530 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\
bogdanm 92:4fc01daae5a5 531 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\
bogdanm 92:4fc01daae5a5 532 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\
bogdanm 92:4fc01daae5a5 533 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\
bogdanm 92:4fc01daae5a5 534 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\
bogdanm 92:4fc01daae5a5 535 DMA_FLAG_DMEIF3_7)
bogdanm 92:4fc01daae5a5 536
bogdanm 92:4fc01daae5a5 537 /**
bogdanm 92:4fc01daae5a5 538 * @brief Get the DMA Stream pending flags.
bogdanm 92:4fc01daae5a5 539 * @param __HANDLE__: DMA handle
bogdanm 92:4fc01daae5a5 540 * @param __FLAG__: Get the specified flag.
bogdanm 92:4fc01daae5a5 541 * This parameter can be any combination of the following values:
bogdanm 92:4fc01daae5a5 542 * @arg DMA_FLAG_TCIFx: Transfer complete flag.
bogdanm 92:4fc01daae5a5 543 * @arg DMA_FLAG_HTIFx: Half transfer complete flag.
bogdanm 92:4fc01daae5a5 544 * @arg DMA_FLAG_TEIFx: Transfer error flag.
bogdanm 92:4fc01daae5a5 545 * @arg DMA_FLAG_DMEIFx: Direct mode error flag.
bogdanm 92:4fc01daae5a5 546 * @arg DMA_FLAG_FEIFx: FIFO error flag.
bogdanm 92:4fc01daae5a5 547 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
bogdanm 92:4fc01daae5a5 548 * @retval The state of FLAG (SET or RESET).
bogdanm 92:4fc01daae5a5 549 */
bogdanm 92:4fc01daae5a5 550 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
bogdanm 92:4fc01daae5a5 551 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
bogdanm 92:4fc01daae5a5 552 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
bogdanm 92:4fc01daae5a5 553 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
bogdanm 92:4fc01daae5a5 554
bogdanm 92:4fc01daae5a5 555 /**
bogdanm 92:4fc01daae5a5 556 * @brief Clear the DMA Stream pending flags.
bogdanm 92:4fc01daae5a5 557 * @param __HANDLE__: DMA handle
bogdanm 92:4fc01daae5a5 558 * @param __FLAG__: specifies the flag to clear.
bogdanm 92:4fc01daae5a5 559 * This parameter can be any combination of the following values:
bogdanm 92:4fc01daae5a5 560 * @arg DMA_FLAG_TCIFx: Transfer complete flag.
bogdanm 92:4fc01daae5a5 561 * @arg DMA_FLAG_HTIFx: Half transfer complete flag.
bogdanm 92:4fc01daae5a5 562 * @arg DMA_FLAG_TEIFx: Transfer error flag.
bogdanm 92:4fc01daae5a5 563 * @arg DMA_FLAG_DMEIFx: Direct mode error flag.
bogdanm 92:4fc01daae5a5 564 * @arg DMA_FLAG_FEIFx: FIFO error flag.
bogdanm 92:4fc01daae5a5 565 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
bogdanm 92:4fc01daae5a5 566 * @retval None
bogdanm 92:4fc01daae5a5 567 */
bogdanm 92:4fc01daae5a5 568 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
bogdanm 92:4fc01daae5a5 569 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
bogdanm 92:4fc01daae5a5 570 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
bogdanm 92:4fc01daae5a5 571 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
bogdanm 92:4fc01daae5a5 572
bogdanm 92:4fc01daae5a5 573 /**
bogdanm 92:4fc01daae5a5 574 * @brief Enable the specified DMA Stream interrupts.
bogdanm 92:4fc01daae5a5 575 * @param __HANDLE__: DMA handle
bogdanm 92:4fc01daae5a5 576 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
bogdanm 92:4fc01daae5a5 577 * This parameter can be any combination of the following values:
bogdanm 92:4fc01daae5a5 578 * @arg DMA_IT_TC: Transfer complete interrupt mask.
bogdanm 92:4fc01daae5a5 579 * @arg DMA_IT_HT: Half transfer complete interrupt mask.
bogdanm 92:4fc01daae5a5 580 * @arg DMA_IT_TE: Transfer error interrupt mask.
bogdanm 92:4fc01daae5a5 581 * @arg DMA_IT_FE: FIFO error interrupt mask.
bogdanm 92:4fc01daae5a5 582 * @arg DMA_IT_DME: Direct mode error interrupt.
bogdanm 92:4fc01daae5a5 583 * @retval None
bogdanm 92:4fc01daae5a5 584 */
bogdanm 92:4fc01daae5a5 585 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
bogdanm 92:4fc01daae5a5 586 ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__)))
bogdanm 92:4fc01daae5a5 587
bogdanm 92:4fc01daae5a5 588 /**
bogdanm 92:4fc01daae5a5 589 * @brief Disable the specified DMA Stream interrupts.
bogdanm 92:4fc01daae5a5 590 * @param __HANDLE__: DMA handle
bogdanm 92:4fc01daae5a5 591 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
bogdanm 92:4fc01daae5a5 592 * This parameter can be any combination of the following values:
bogdanm 92:4fc01daae5a5 593 * @arg DMA_IT_TC: Transfer complete interrupt mask.
bogdanm 92:4fc01daae5a5 594 * @arg DMA_IT_HT: Half transfer complete interrupt mask.
bogdanm 92:4fc01daae5a5 595 * @arg DMA_IT_TE: Transfer error interrupt mask.
bogdanm 92:4fc01daae5a5 596 * @arg DMA_IT_FE: FIFO error interrupt mask.
bogdanm 92:4fc01daae5a5 597 * @arg DMA_IT_DME: Direct mode error interrupt.
bogdanm 92:4fc01daae5a5 598 * @retval None
bogdanm 92:4fc01daae5a5 599 */
bogdanm 92:4fc01daae5a5 600 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
bogdanm 92:4fc01daae5a5 601 ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__)))
bogdanm 92:4fc01daae5a5 602
bogdanm 92:4fc01daae5a5 603 /**
Kojto 106:ba1f97679dad 604 * @brief Check whether the specified DMA Stream interrupt is enabled or disabled.
bogdanm 92:4fc01daae5a5 605 * @param __HANDLE__: DMA handle
bogdanm 92:4fc01daae5a5 606 * @param __INTERRUPT__: specifies the DMA interrupt source to check.
bogdanm 92:4fc01daae5a5 607 * This parameter can be one of the following values:
bogdanm 92:4fc01daae5a5 608 * @arg DMA_IT_TC: Transfer complete interrupt mask.
bogdanm 92:4fc01daae5a5 609 * @arg DMA_IT_HT: Half transfer complete interrupt mask.
bogdanm 92:4fc01daae5a5 610 * @arg DMA_IT_TE: Transfer error interrupt mask.
bogdanm 92:4fc01daae5a5 611 * @arg DMA_IT_FE: FIFO error interrupt mask.
bogdanm 92:4fc01daae5a5 612 * @arg DMA_IT_DME: Direct mode error interrupt.
bogdanm 92:4fc01daae5a5 613 * @retval The state of DMA_IT.
bogdanm 92:4fc01daae5a5 614 */
bogdanm 92:4fc01daae5a5 615 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
bogdanm 92:4fc01daae5a5 616 ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \
bogdanm 92:4fc01daae5a5 617 ((__HANDLE__)->Instance->FCR & (__INTERRUPT__)))
bogdanm 92:4fc01daae5a5 618
bogdanm 92:4fc01daae5a5 619 /**
bogdanm 92:4fc01daae5a5 620 * @brief Writes the number of data units to be transferred on the DMA Stream.
bogdanm 92:4fc01daae5a5 621 * @param __HANDLE__: DMA handle
bogdanm 92:4fc01daae5a5 622 * @param __COUNTER__: Number of data units to be transferred (from 0 to 65535)
bogdanm 92:4fc01daae5a5 623 * Number of data items depends only on the Peripheral data format.
bogdanm 92:4fc01daae5a5 624 *
bogdanm 92:4fc01daae5a5 625 * @note If Peripheral data format is Bytes: number of data units is equal
bogdanm 92:4fc01daae5a5 626 * to total number of bytes to be transferred.
bogdanm 92:4fc01daae5a5 627 *
bogdanm 92:4fc01daae5a5 628 * @note If Peripheral data format is Half-Word: number of data units is
bogdanm 92:4fc01daae5a5 629 * equal to total number of bytes to be transferred / 2.
bogdanm 92:4fc01daae5a5 630 *
bogdanm 92:4fc01daae5a5 631 * @note If Peripheral data format is Word: number of data units is equal
bogdanm 92:4fc01daae5a5 632 * to total number of bytes to be transferred / 4.
bogdanm 92:4fc01daae5a5 633 *
bogdanm 92:4fc01daae5a5 634 * @retval The number of remaining data units in the current DMAy Streamx transfer.
bogdanm 92:4fc01daae5a5 635 */
bogdanm 92:4fc01daae5a5 636 #define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__))
bogdanm 92:4fc01daae5a5 637
bogdanm 92:4fc01daae5a5 638 /**
bogdanm 92:4fc01daae5a5 639 * @brief Returns the number of remaining data units in the current DMAy Streamx transfer.
bogdanm 92:4fc01daae5a5 640 * @param __HANDLE__: DMA handle
bogdanm 92:4fc01daae5a5 641 *
bogdanm 92:4fc01daae5a5 642 * @retval The number of remaining data units in the current DMA Stream transfer.
bogdanm 92:4fc01daae5a5 643 */
bogdanm 92:4fc01daae5a5 644 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR)
bogdanm 92:4fc01daae5a5 645
bogdanm 92:4fc01daae5a5 646
bogdanm 92:4fc01daae5a5 647 /* Include DMA HAL Extension module */
bogdanm 92:4fc01daae5a5 648 #include "stm32f4xx_hal_dma_ex.h"
bogdanm 92:4fc01daae5a5 649
bogdanm 92:4fc01daae5a5 650 /* Exported functions --------------------------------------------------------*/
Kojto 99:dbbf35b96557 651
Kojto 99:dbbf35b96557 652 /** @defgroup DMA_Exported_Functions DMA Exported Functions
Kojto 99:dbbf35b96557 653 * @brief DMA Exported functions
Kojto 99:dbbf35b96557 654 * @{
Kojto 99:dbbf35b96557 655 */
Kojto 99:dbbf35b96557 656
Kojto 99:dbbf35b96557 657 /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
Kojto 99:dbbf35b96557 658 * @brief Initialization and de-initialization functions
Kojto 99:dbbf35b96557 659 * @{
Kojto 99:dbbf35b96557 660 */
bogdanm 92:4fc01daae5a5 661 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
bogdanm 92:4fc01daae5a5 662 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
Kojto 99:dbbf35b96557 663 /**
Kojto 99:dbbf35b96557 664 * @}
Kojto 99:dbbf35b96557 665 */
bogdanm 92:4fc01daae5a5 666
Kojto 99:dbbf35b96557 667 /** @defgroup DMA_Exported_Functions_Group2 I/O operation functions
Kojto 99:dbbf35b96557 668 * @brief I/O operation functions
Kojto 99:dbbf35b96557 669 * @{
Kojto 99:dbbf35b96557 670 */
bogdanm 92:4fc01daae5a5 671 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
bogdanm 92:4fc01daae5a5 672 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
bogdanm 92:4fc01daae5a5 673 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
Kojto 122:f9eeca106725 674 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
Kojto 122:f9eeca106725 675 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
bogdanm 92:4fc01daae5a5 676 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
Kojto 122:f9eeca106725 677 HAL_StatusTypeDef HAL_DMA_CleanCallbacks(DMA_HandleTypeDef *hdma);
Kojto 122:f9eeca106725 678 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
Kojto 122:f9eeca106725 679 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
Kojto 122:f9eeca106725 680
Kojto 99:dbbf35b96557 681 /**
Kojto 99:dbbf35b96557 682 * @}
Kojto 99:dbbf35b96557 683 */
bogdanm 92:4fc01daae5a5 684
Kojto 99:dbbf35b96557 685 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
Kojto 99:dbbf35b96557 686 * @brief Peripheral State functions
Kojto 99:dbbf35b96557 687 * @{
Kojto 99:dbbf35b96557 688 */
bogdanm 92:4fc01daae5a5 689 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
bogdanm 92:4fc01daae5a5 690 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
Kojto 99:dbbf35b96557 691 /**
Kojto 99:dbbf35b96557 692 * @}
Kojto 99:dbbf35b96557 693 */
Kojto 99:dbbf35b96557 694 /**
Kojto 99:dbbf35b96557 695 * @}
Kojto 99:dbbf35b96557 696 */
Kojto 99:dbbf35b96557 697 /* Private Constants -------------------------------------------------------------*/
Kojto 99:dbbf35b96557 698 /** @defgroup DMA_Private_Constants DMA Private Constants
Kojto 99:dbbf35b96557 699 * @brief DMA private defines and constants
Kojto 99:dbbf35b96557 700 * @{
Kojto 99:dbbf35b96557 701 */
Kojto 99:dbbf35b96557 702 /**
Kojto 99:dbbf35b96557 703 * @}
Kojto 99:dbbf35b96557 704 */
Kojto 99:dbbf35b96557 705
Kojto 99:dbbf35b96557 706 /* Private macros ------------------------------------------------------------*/
Kojto 99:dbbf35b96557 707 /** @defgroup DMA_Private_Macros DMA Private Macros
Kojto 99:dbbf35b96557 708 * @brief DMA private macros
Kojto 99:dbbf35b96557 709 * @{
Kojto 99:dbbf35b96557 710 */
Kojto 99:dbbf35b96557 711 #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
Kojto 99:dbbf35b96557 712 ((CHANNEL) == DMA_CHANNEL_1) || \
Kojto 99:dbbf35b96557 713 ((CHANNEL) == DMA_CHANNEL_2) || \
Kojto 99:dbbf35b96557 714 ((CHANNEL) == DMA_CHANNEL_3) || \
Kojto 99:dbbf35b96557 715 ((CHANNEL) == DMA_CHANNEL_4) || \
Kojto 99:dbbf35b96557 716 ((CHANNEL) == DMA_CHANNEL_5) || \
Kojto 99:dbbf35b96557 717 ((CHANNEL) == DMA_CHANNEL_6) || \
Kojto 99:dbbf35b96557 718 ((CHANNEL) == DMA_CHANNEL_7))
Kojto 99:dbbf35b96557 719
Kojto 99:dbbf35b96557 720 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
Kojto 99:dbbf35b96557 721 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
Kojto 99:dbbf35b96557 722 ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
Kojto 99:dbbf35b96557 723
Kojto 122:f9eeca106725 724 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U))
Kojto 99:dbbf35b96557 725
Kojto 99:dbbf35b96557 726 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
Kojto 99:dbbf35b96557 727 ((STATE) == DMA_PINC_DISABLE))
Kojto 99:dbbf35b96557 728
Kojto 99:dbbf35b96557 729 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
Kojto 99:dbbf35b96557 730 ((STATE) == DMA_MINC_DISABLE))
Kojto 99:dbbf35b96557 731
Kojto 99:dbbf35b96557 732 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
Kojto 99:dbbf35b96557 733 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
Kojto 99:dbbf35b96557 734 ((SIZE) == DMA_PDATAALIGN_WORD))
Kojto 99:dbbf35b96557 735
Kojto 99:dbbf35b96557 736 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
Kojto 99:dbbf35b96557 737 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
Kojto 99:dbbf35b96557 738 ((SIZE) == DMA_MDATAALIGN_WORD ))
Kojto 99:dbbf35b96557 739
Kojto 99:dbbf35b96557 740 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
Kojto 99:dbbf35b96557 741 ((MODE) == DMA_CIRCULAR) || \
Kojto 99:dbbf35b96557 742 ((MODE) == DMA_PFCTRL))
Kojto 99:dbbf35b96557 743
Kojto 99:dbbf35b96557 744 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
Kojto 99:dbbf35b96557 745 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
Kojto 99:dbbf35b96557 746 ((PRIORITY) == DMA_PRIORITY_HIGH) || \
Kojto 99:dbbf35b96557 747 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
Kojto 99:dbbf35b96557 748
Kojto 99:dbbf35b96557 749 #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \
Kojto 99:dbbf35b96557 750 ((STATE) == DMA_FIFOMODE_ENABLE))
Kojto 99:dbbf35b96557 751
Kojto 99:dbbf35b96557 752 #define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \
Kojto 99:dbbf35b96557 753 ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \
Kojto 99:dbbf35b96557 754 ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \
Kojto 99:dbbf35b96557 755 ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))
Kojto 99:dbbf35b96557 756
Kojto 99:dbbf35b96557 757 #define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \
Kojto 99:dbbf35b96557 758 ((BURST) == DMA_MBURST_INC4) || \
Kojto 99:dbbf35b96557 759 ((BURST) == DMA_MBURST_INC8) || \
Kojto 99:dbbf35b96557 760 ((BURST) == DMA_MBURST_INC16))
Kojto 99:dbbf35b96557 761
Kojto 99:dbbf35b96557 762 #define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \
Kojto 99:dbbf35b96557 763 ((BURST) == DMA_PBURST_INC4) || \
Kojto 99:dbbf35b96557 764 ((BURST) == DMA_PBURST_INC8) || \
Kojto 99:dbbf35b96557 765 ((BURST) == DMA_PBURST_INC16))
Kojto 99:dbbf35b96557 766 /**
Kojto 99:dbbf35b96557 767 * @}
Kojto 99:dbbf35b96557 768 */
Kojto 99:dbbf35b96557 769
Kojto 99:dbbf35b96557 770 /* Private functions ---------------------------------------------------------*/
Kojto 99:dbbf35b96557 771 /** @defgroup DMA_Private_Functions DMA Private Functions
Kojto 99:dbbf35b96557 772 * @brief DMA private functions
Kojto 99:dbbf35b96557 773 * @{
Kojto 99:dbbf35b96557 774 */
Kojto 99:dbbf35b96557 775 /**
Kojto 99:dbbf35b96557 776 * @}
Kojto 99:dbbf35b96557 777 */
bogdanm 92:4fc01daae5a5 778
bogdanm 92:4fc01daae5a5 779 /**
bogdanm 92:4fc01daae5a5 780 * @}
bogdanm 92:4fc01daae5a5 781 */
bogdanm 92:4fc01daae5a5 782
bogdanm 92:4fc01daae5a5 783 /**
bogdanm 92:4fc01daae5a5 784 * @}
bogdanm 92:4fc01daae5a5 785 */
bogdanm 92:4fc01daae5a5 786
bogdanm 92:4fc01daae5a5 787 #ifdef __cplusplus
bogdanm 92:4fc01daae5a5 788 }
bogdanm 92:4fc01daae5a5 789 #endif
bogdanm 92:4fc01daae5a5 790
bogdanm 92:4fc01daae5a5 791 #endif /* __STM32F4xx_HAL_DMA_H */
bogdanm 92:4fc01daae5a5 792
bogdanm 92:4fc01daae5a5 793 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/