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TARGET_NUCLEO_F042K6/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rcc_ex.h@157:e7ca05fa8600, 2017-11-09 (annotated)

Committer:: AnnaBridge
Date:: Thu Nov 09 11:14:10 2017 +0000
Revision:: 157:e7ca05fa8600
Parent:: 156:ff21514d8981
Child:: 160:5571c4ff569f

Release 155 of the mbed library.

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	156:ff21514d8981	1	/**
AnnaBridge	156:ff21514d8981	2	******************************************************************************
AnnaBridge	156:ff21514d8981	3	* @file stm32f0xx_hal_rcc_ex.h
AnnaBridge	156:ff21514d8981	4	* @author MCD Application Team
AnnaBridge	156:ff21514d8981	5	* @version V1.5.0
AnnaBridge	156:ff21514d8981	6	* @date 04-November-2016
AnnaBridge	156:ff21514d8981	7	* @brief Header file of RCC HAL Extension module.
AnnaBridge	156:ff21514d8981	8	******************************************************************************
AnnaBridge	156:ff21514d8981	9	* @attention
AnnaBridge	156:ff21514d8981	10	*
AnnaBridge	156:ff21514d8981	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge	156:ff21514d8981	12	*
AnnaBridge	156:ff21514d8981	13	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	156:ff21514d8981	14	* are permitted provided that the following conditions are met:
AnnaBridge	156:ff21514d8981	15	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	156:ff21514d8981	16	* this list of conditions and the following disclaimer.
AnnaBridge	156:ff21514d8981	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	156:ff21514d8981	18	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	156:ff21514d8981	19	* and/or other materials provided with the distribution.
AnnaBridge	156:ff21514d8981	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	156:ff21514d8981	21	* may be used to endorse or promote products derived from this software
AnnaBridge	156:ff21514d8981	22	* without specific prior written permission.
AnnaBridge	156:ff21514d8981	23	*
AnnaBridge	156:ff21514d8981	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	156:ff21514d8981	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	156:ff21514d8981	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	156:ff21514d8981	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	156:ff21514d8981	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	156:ff21514d8981	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	156:ff21514d8981	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	156:ff21514d8981	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	156:ff21514d8981	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	156:ff21514d8981	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	156:ff21514d8981	34	*
AnnaBridge	156:ff21514d8981	35	******************************************************************************
AnnaBridge	156:ff21514d8981	36	*/
AnnaBridge	156:ff21514d8981	37
AnnaBridge	156:ff21514d8981	38	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	156:ff21514d8981	39	#ifndef __STM32F0xx_HAL_RCC_EX_H
AnnaBridge	156:ff21514d8981	40	#define __STM32F0xx_HAL_RCC_EX_H
AnnaBridge	156:ff21514d8981	41
AnnaBridge	156:ff21514d8981	42	#ifdef __cplusplus
AnnaBridge	156:ff21514d8981	43	extern "C" {
AnnaBridge	156:ff21514d8981	44	#endif
AnnaBridge	156:ff21514d8981	45
AnnaBridge	156:ff21514d8981	46	/* Includes ------------------------------------------------------------------*/
AnnaBridge	156:ff21514d8981	47	#include "stm32f0xx_hal_def.h"
AnnaBridge	156:ff21514d8981	48
AnnaBridge	156:ff21514d8981	49	/** @addtogroup STM32F0xx_HAL_Driver
AnnaBridge	156:ff21514d8981	50	* @{
AnnaBridge	156:ff21514d8981	51	*/
AnnaBridge	156:ff21514d8981	52
AnnaBridge	156:ff21514d8981	53	/** @addtogroup RCC
AnnaBridge	156:ff21514d8981	54	* @{
AnnaBridge	156:ff21514d8981	55	*/
AnnaBridge	156:ff21514d8981	56
AnnaBridge	156:ff21514d8981	57	/** @addtogroup RCC_Private_Macros
AnnaBridge	156:ff21514d8981	58	* @{
AnnaBridge	156:ff21514d8981	59	*/
AnnaBridge	156:ff21514d8981	60	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	156:ff21514d8981	61	#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) \|\| \
AnnaBridge	156:ff21514d8981	62	(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) \|\| \
AnnaBridge	156:ff21514d8981	63	(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) \|\| \
AnnaBridge	156:ff21514d8981	64	(((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) \|\| \
AnnaBridge	156:ff21514d8981	65	(((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) \|\| \
AnnaBridge	156:ff21514d8981	66	(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14) \|\| \
AnnaBridge	156:ff21514d8981	67	(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48))
AnnaBridge	156:ff21514d8981	68
AnnaBridge	156:ff21514d8981	69	#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) \|\| \
AnnaBridge	156:ff21514d8981	70	((SOURCE) == RCC_SYSCLKSOURCE_HSE) \|\| \
AnnaBridge	156:ff21514d8981	71	((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) \|\| \
AnnaBridge	156:ff21514d8981	72	((SOURCE) == RCC_SYSCLKSOURCE_HSI48))
AnnaBridge	156:ff21514d8981	73
AnnaBridge	156:ff21514d8981	74	#define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) \|\| \
AnnaBridge	156:ff21514d8981	75	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) \|\| \
AnnaBridge	156:ff21514d8981	76	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK) \|\| \
AnnaBridge	156:ff21514d8981	77	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI48))
AnnaBridge	156:ff21514d8981	78
AnnaBridge	156:ff21514d8981	79	#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) \|\| \
AnnaBridge	156:ff21514d8981	80	((SOURCE) == RCC_PLLSOURCE_HSI48) \|\| \
AnnaBridge	156:ff21514d8981	81	((SOURCE) == RCC_PLLSOURCE_HSE))
AnnaBridge	156:ff21514d8981	82
AnnaBridge	156:ff21514d8981	83	#define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF) \|\| ((HSI48) == RCC_HSI48_ON))
AnnaBridge	156:ff21514d8981	84
AnnaBridge	156:ff21514d8981	85	#else
AnnaBridge	156:ff21514d8981	86
AnnaBridge	156:ff21514d8981	87	#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) \|\| \
AnnaBridge	156:ff21514d8981	88	(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) \|\| \
AnnaBridge	156:ff21514d8981	89	(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) \|\| \
AnnaBridge	156:ff21514d8981	90	(((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) \|\| \
AnnaBridge	156:ff21514d8981	91	(((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) \|\| \
AnnaBridge	156:ff21514d8981	92	(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14))
AnnaBridge	156:ff21514d8981	93	#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) \|\| \
AnnaBridge	156:ff21514d8981	94	((SOURCE) == RCC_SYSCLKSOURCE_HSE) \|\| \
AnnaBridge	156:ff21514d8981	95	((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
AnnaBridge	156:ff21514d8981	96
AnnaBridge	156:ff21514d8981	97	#define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) \|\| \
AnnaBridge	156:ff21514d8981	98	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) \|\| \
AnnaBridge	156:ff21514d8981	99	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
AnnaBridge	156:ff21514d8981	100	#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) \|\| \
AnnaBridge	156:ff21514d8981	101	((SOURCE) == RCC_PLLSOURCE_HSE))
AnnaBridge	156:ff21514d8981	102
AnnaBridge	156:ff21514d8981	103	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	156:ff21514d8981	104
AnnaBridge	156:ff21514d8981	105	#if defined(RCC_CFGR_PLLNODIV) && !defined(RCC_CFGR_MCO_HSI48)
AnnaBridge	156:ff21514d8981	106
AnnaBridge	156:ff21514d8981	107	#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) \|\| \
AnnaBridge	156:ff21514d8981	108	((SOURCE) == RCC_MCO1SOURCE_LSI) \|\| \
AnnaBridge	156:ff21514d8981	109	((SOURCE) == RCC_MCO1SOURCE_LSE) \|\| \
AnnaBridge	156:ff21514d8981	110	((SOURCE) == RCC_MCO1SOURCE_SYSCLK) \|\| \
AnnaBridge	156:ff21514d8981	111	((SOURCE) == RCC_MCO1SOURCE_HSI) \|\| \
AnnaBridge	156:ff21514d8981	112	((SOURCE) == RCC_MCO1SOURCE_HSE) \|\| \
AnnaBridge	156:ff21514d8981	113	((SOURCE) == RCC_MCO1SOURCE_PLLCLK) \|\| \
AnnaBridge	156:ff21514d8981	114	((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2) \|\| \
AnnaBridge	156:ff21514d8981	115	((SOURCE) == RCC_MCO1SOURCE_HSI14))
AnnaBridge	156:ff21514d8981	116
AnnaBridge	156:ff21514d8981	117	#elif defined(RCC_CFGR_PLLNODIV) && defined(RCC_CFGR_MCO_HSI48)
AnnaBridge	156:ff21514d8981	118
AnnaBridge	156:ff21514d8981	119	#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) \|\| \
AnnaBridge	156:ff21514d8981	120	((SOURCE) == RCC_MCO1SOURCE_LSI) \|\| \
AnnaBridge	156:ff21514d8981	121	((SOURCE) == RCC_MCO1SOURCE_LSE) \|\| \
AnnaBridge	156:ff21514d8981	122	((SOURCE) == RCC_MCO1SOURCE_SYSCLK) \|\| \
AnnaBridge	156:ff21514d8981	123	((SOURCE) == RCC_MCO1SOURCE_HSI) \|\| \
AnnaBridge	156:ff21514d8981	124	((SOURCE) == RCC_MCO1SOURCE_HSE) \|\| \
AnnaBridge	156:ff21514d8981	125	((SOURCE) == RCC_MCO1SOURCE_PLLCLK) \|\| \
AnnaBridge	156:ff21514d8981	126	((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2) \|\| \
AnnaBridge	156:ff21514d8981	127	((SOURCE) == RCC_MCO1SOURCE_HSI14) \|\| \
AnnaBridge	156:ff21514d8981	128	((SOURCE) == RCC_MCO1SOURCE_HSI48))
AnnaBridge	156:ff21514d8981	129
AnnaBridge	156:ff21514d8981	130	#elif !defined(RCC_CFGR_PLLNODIV) && !defined(RCC_CFGR_MCO_HSI48)
AnnaBridge	156:ff21514d8981	131
AnnaBridge	156:ff21514d8981	132	#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) \|\| \
AnnaBridge	156:ff21514d8981	133	((SOURCE) == RCC_MCO1SOURCE_LSI) \|\| \
AnnaBridge	156:ff21514d8981	134	((SOURCE) == RCC_MCO1SOURCE_LSE) \|\| \
AnnaBridge	156:ff21514d8981	135	((SOURCE) == RCC_MCO1SOURCE_SYSCLK) \|\| \
AnnaBridge	156:ff21514d8981	136	((SOURCE) == RCC_MCO1SOURCE_HSI) \|\| \
AnnaBridge	156:ff21514d8981	137	((SOURCE) == RCC_MCO1SOURCE_HSE) \|\| \
AnnaBridge	156:ff21514d8981	138	((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2) \|\| \
AnnaBridge	156:ff21514d8981	139	((SOURCE) == RCC_MCO1SOURCE_HSI14))
AnnaBridge	156:ff21514d8981	140
AnnaBridge	156:ff21514d8981	141	#endif /* RCC_CFGR_PLLNODIV && !RCC_CFGR_MCO_HSI48 */
AnnaBridge	156:ff21514d8981	142
AnnaBridge	156:ff21514d8981	143	/**
AnnaBridge	156:ff21514d8981	144	* @}
AnnaBridge	156:ff21514d8981	145	*/
AnnaBridge	156:ff21514d8981	146
AnnaBridge	156:ff21514d8981	147	/** @addtogroup RCC_Exported_Constants
AnnaBridge	156:ff21514d8981	148	* @{
AnnaBridge	156:ff21514d8981	149	*/
AnnaBridge	156:ff21514d8981	150	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	156:ff21514d8981	151
AnnaBridge	156:ff21514d8981	152	/** @addtogroup RCC_PLL_Clock_Source
AnnaBridge	156:ff21514d8981	153	* @{
AnnaBridge	156:ff21514d8981	154	*/
AnnaBridge	156:ff21514d8981	155	#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV
AnnaBridge	156:ff21514d8981	156	#define RCC_PLLSOURCE_HSI48 RCC_CFGR_PLLSRC_HSI48_PREDIV
AnnaBridge	156:ff21514d8981	157
AnnaBridge	156:ff21514d8981	158	/**
AnnaBridge	156:ff21514d8981	159	* @}
AnnaBridge	156:ff21514d8981	160	*/
AnnaBridge	156:ff21514d8981	161
AnnaBridge	156:ff21514d8981	162	/** @addtogroup RCC_Interrupt
AnnaBridge	156:ff21514d8981	163	* @{
AnnaBridge	156:ff21514d8981	164	*/
AnnaBridge	156:ff21514d8981	165	#define RCC_IT_HSI48 RCC_CIR_HSI48RDYF /!< HSI48 Ready Interrupt flag /
AnnaBridge	156:ff21514d8981	166	/**
AnnaBridge	156:ff21514d8981	167	* @}
AnnaBridge	156:ff21514d8981	168	*/
AnnaBridge	156:ff21514d8981	169
AnnaBridge	156:ff21514d8981	170	/** @addtogroup RCC_Flag
AnnaBridge	156:ff21514d8981	171	* @{
AnnaBridge	156:ff21514d8981	172	*/
AnnaBridge	156:ff21514d8981	173	#define RCC_FLAG_HSI48RDY ((uint8_t)((CR2_REG_INDEX << 5U) \| RCC_CR2_HSI48RDY_BitNumber))
AnnaBridge	156:ff21514d8981	174	/**
AnnaBridge	156:ff21514d8981	175	* @}
AnnaBridge	156:ff21514d8981	176	*/
AnnaBridge	156:ff21514d8981	177
AnnaBridge	156:ff21514d8981	178	/** @addtogroup RCC_System_Clock_Source
AnnaBridge	156:ff21514d8981	179	* @{
AnnaBridge	156:ff21514d8981	180	*/
AnnaBridge	156:ff21514d8981	181	#define RCC_SYSCLKSOURCE_HSI48 RCC_CFGR_SW_HSI48
AnnaBridge	156:ff21514d8981	182	/**
AnnaBridge	156:ff21514d8981	183	* @}
AnnaBridge	156:ff21514d8981	184	*/
AnnaBridge	156:ff21514d8981	185
AnnaBridge	156:ff21514d8981	186	/** @addtogroup RCC_System_Clock_Source_Status
AnnaBridge	156:ff21514d8981	187	* @{
AnnaBridge	156:ff21514d8981	188	*/
AnnaBridge	156:ff21514d8981	189	#define RCC_SYSCLKSOURCE_STATUS_HSI48 RCC_CFGR_SWS_HSI48
AnnaBridge	156:ff21514d8981	190	/**
AnnaBridge	156:ff21514d8981	191	* @}
AnnaBridge	156:ff21514d8981	192	*/
AnnaBridge	156:ff21514d8981	193
AnnaBridge	156:ff21514d8981	194	#else
AnnaBridge	156:ff21514d8981	195	/** @addtogroup RCC_PLL_Clock_Source
AnnaBridge	156:ff21514d8981	196	* @{
AnnaBridge	156:ff21514d8981	197	*/
AnnaBridge	156:ff21514d8981	198
AnnaBridge	156:ff21514d8981	199	#if defined(STM32F070xB) \|\| defined(STM32F070x6) \|\| defined(STM32F030xC)
AnnaBridge	156:ff21514d8981	200	#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV
AnnaBridge	156:ff21514d8981	201	#else
AnnaBridge	156:ff21514d8981	202	#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_DIV2
AnnaBridge	156:ff21514d8981	203	#endif
AnnaBridge	156:ff21514d8981	204
AnnaBridge	156:ff21514d8981	205	/**
AnnaBridge	156:ff21514d8981	206	* @}
AnnaBridge	156:ff21514d8981	207	*/
AnnaBridge	156:ff21514d8981	208
AnnaBridge	156:ff21514d8981	209	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	156:ff21514d8981	210
AnnaBridge	156:ff21514d8981	211	/** @addtogroup RCC_MCO_Clock_Source
AnnaBridge	156:ff21514d8981	212	* @{
AnnaBridge	156:ff21514d8981	213	*/
AnnaBridge	156:ff21514d8981	214
AnnaBridge	156:ff21514d8981	215	#if defined(RCC_CFGR_PLLNODIV)
AnnaBridge	156:ff21514d8981	216
AnnaBridge	156:ff21514d8981	217	#define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCO_PLL \| RCC_CFGR_PLLNODIV)
AnnaBridge	156:ff21514d8981	218
AnnaBridge	156:ff21514d8981	219	#endif /* RCC_CFGR_PLLNODIV */
AnnaBridge	156:ff21514d8981	220
AnnaBridge	156:ff21514d8981	221	#if defined(RCC_CFGR_MCO_HSI48)
AnnaBridge	156:ff21514d8981	222
AnnaBridge	156:ff21514d8981	223	#define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCO_HSI48
AnnaBridge	156:ff21514d8981	224
AnnaBridge	156:ff21514d8981	225	#endif /* SRCC_CFGR_MCO_HSI48 */
AnnaBridge	156:ff21514d8981	226	/**
AnnaBridge	156:ff21514d8981	227	* @}
AnnaBridge	156:ff21514d8981	228	*/
AnnaBridge	156:ff21514d8981	229
AnnaBridge	156:ff21514d8981	230	/**
AnnaBridge	156:ff21514d8981	231	* @}
AnnaBridge	156:ff21514d8981	232	*/
AnnaBridge	156:ff21514d8981	233
AnnaBridge	156:ff21514d8981	234	/**
AnnaBridge	156:ff21514d8981	235	* @}
AnnaBridge	156:ff21514d8981	236	*/
AnnaBridge	156:ff21514d8981	237
AnnaBridge	156:ff21514d8981	238	/** @addtogroup RCCEx
AnnaBridge	156:ff21514d8981	239	* @{
AnnaBridge	156:ff21514d8981	240	*/
AnnaBridge	156:ff21514d8981	241
AnnaBridge	156:ff21514d8981	242	/* Private Constants -------------------------------------------------------------*/
AnnaBridge	156:ff21514d8981	243	#if defined(CRS)
AnnaBridge	156:ff21514d8981	244	/** @addtogroup RCCEx_Private_Constants
AnnaBridge	156:ff21514d8981	245	* @{
AnnaBridge	156:ff21514d8981	246	*/
AnnaBridge	156:ff21514d8981	247
AnnaBridge	156:ff21514d8981	248	/* CRS IT Error Mask */
AnnaBridge	156:ff21514d8981	249	#define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF \| RCC_CRS_IT_SYNCERR \| RCC_CRS_IT_SYNCMISS))
AnnaBridge	156:ff21514d8981	250
AnnaBridge	156:ff21514d8981	251	/* CRS Flag Error Mask */
AnnaBridge	156:ff21514d8981	252	#define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF \| RCC_CRS_FLAG_SYNCERR \| RCC_CRS_FLAG_SYNCMISS))
AnnaBridge	156:ff21514d8981	253
AnnaBridge	156:ff21514d8981	254	/**
AnnaBridge	156:ff21514d8981	255	* @}
AnnaBridge	156:ff21514d8981	256	*/
AnnaBridge	156:ff21514d8981	257	#endif /* CRS */
AnnaBridge	156:ff21514d8981	258
AnnaBridge	156:ff21514d8981	259	/* Private macro -------------------------------------------------------------*/
AnnaBridge	156:ff21514d8981	260	/** @defgroup RCCEx_Private_Macros RCCEx Private Macros
AnnaBridge	156:ff21514d8981	261	* @{
AnnaBridge	156:ff21514d8981	262	*/
AnnaBridge	156:ff21514d8981	263	#if defined(STM32F030x6) \|\| defined(STM32F030x8) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx)\
AnnaBridge	156:ff21514d8981	264	\|\| defined(STM32F030xC)
AnnaBridge	156:ff21514d8981	265
AnnaBridge	156:ff21514d8981	266	#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_I2C1 \| \
AnnaBridge	156:ff21514d8981	267	RCC_PERIPHCLK_RTC))
AnnaBridge	156:ff21514d8981	268	#endif /* STM32F030x6 \|\| STM32F030x8 \|\| STM32F031x6 \|\| STM32F038xx \|\|
AnnaBridge	156:ff21514d8981	269	STM32F030xC */
AnnaBridge	156:ff21514d8981	270
AnnaBridge	156:ff21514d8981	271	#if defined(STM32F070x6) \|\| defined(STM32F070xB)
AnnaBridge	156:ff21514d8981	272
AnnaBridge	156:ff21514d8981	273	#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_I2C1 \| \
AnnaBridge	156:ff21514d8981	274	RCC_PERIPHCLK_RTC \| RCC_PERIPHCLK_USB))
AnnaBridge	156:ff21514d8981	275	#endif /* STM32F070x6 \|\| STM32F070xB */
AnnaBridge	156:ff21514d8981	276
AnnaBridge	156:ff21514d8981	277	#if defined(STM32F042x6) \|\| defined(STM32F048xx)
AnnaBridge	156:ff21514d8981	278
AnnaBridge	156:ff21514d8981	279	#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_I2C1 \| \
AnnaBridge	156:ff21514d8981	280	RCC_PERIPHCLK_CEC \| RCC_PERIPHCLK_RTC \| \
AnnaBridge	156:ff21514d8981	281	RCC_PERIPHCLK_USB))
AnnaBridge	156:ff21514d8981	282	#endif /* STM32F042x6 \|\| STM32F048xx */
AnnaBridge	156:ff21514d8981	283
AnnaBridge	156:ff21514d8981	284	#if defined(STM32F051x8) \|\| defined(STM32F058xx)
AnnaBridge	156:ff21514d8981	285
AnnaBridge	156:ff21514d8981	286	#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_I2C1 \| \
AnnaBridge	156:ff21514d8981	287	RCC_PERIPHCLK_CEC \| RCC_PERIPHCLK_RTC))
AnnaBridge	156:ff21514d8981	288	#endif /* STM32F051x8 \|\| STM32F058xx */
AnnaBridge	156:ff21514d8981	289
AnnaBridge	156:ff21514d8981	290	#if defined(STM32F071xB)
AnnaBridge	156:ff21514d8981	291
AnnaBridge	156:ff21514d8981	292	#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| \
AnnaBridge	156:ff21514d8981	293	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_CEC \| \
AnnaBridge	156:ff21514d8981	294	RCC_PERIPHCLK_RTC))
AnnaBridge	156:ff21514d8981	295	#endif /* STM32F071xB */
AnnaBridge	156:ff21514d8981	296
AnnaBridge	156:ff21514d8981	297	#if defined(STM32F072xB) \|\| defined(STM32F078xx)
AnnaBridge	156:ff21514d8981	298
AnnaBridge	156:ff21514d8981	299	#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| \
AnnaBridge	156:ff21514d8981	300	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_CEC \| \
AnnaBridge	156:ff21514d8981	301	RCC_PERIPHCLK_RTC \| RCC_PERIPHCLK_USB))
AnnaBridge	156:ff21514d8981	302	#endif /* STM32F072xB \|\| STM32F078xx */
AnnaBridge	156:ff21514d8981	303
AnnaBridge	156:ff21514d8981	304	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
AnnaBridge	156:ff21514d8981	305
AnnaBridge	156:ff21514d8981	306	#define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| \
AnnaBridge	156:ff21514d8981	307	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_CEC \| \
AnnaBridge	156:ff21514d8981	308	RCC_PERIPHCLK_RTC \| RCC_PERIPHCLK_USART3 ))
AnnaBridge	156:ff21514d8981	309	#endif /* STM32F091xC \|\| STM32F098xx */
AnnaBridge	156:ff21514d8981	310
AnnaBridge	156:ff21514d8981	311	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)
AnnaBridge	156:ff21514d8981	312
AnnaBridge	156:ff21514d8981	313	#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_HSI48) \|\| \
AnnaBridge	156:ff21514d8981	314	((SOURCE) == RCC_USBCLKSOURCE_PLL))
AnnaBridge	156:ff21514d8981	315
AnnaBridge	156:ff21514d8981	316	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F072xB \|\| STM32F078xx */
AnnaBridge	156:ff21514d8981	317
AnnaBridge	156:ff21514d8981	318	#if defined(STM32F070x6) \|\| defined(STM32F070xB)
AnnaBridge	156:ff21514d8981	319
AnnaBridge	156:ff21514d8981	320	#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_NONE) \|\| \
AnnaBridge	156:ff21514d8981	321	((SOURCE) == RCC_USBCLKSOURCE_PLL))
AnnaBridge	156:ff21514d8981	322
AnnaBridge	156:ff21514d8981	323	#endif /* STM32F070x6 \|\| STM32F070xB */
AnnaBridge	156:ff21514d8981	324
AnnaBridge	156:ff21514d8981	325	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
AnnaBridge	156:ff21514d8981	326	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
AnnaBridge	156:ff21514d8981	327
AnnaBridge	156:ff21514d8981	328	#define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) \|\| \
AnnaBridge	156:ff21514d8981	329	((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) \|\| \
AnnaBridge	156:ff21514d8981	330	((SOURCE) == RCC_USART2CLKSOURCE_LSE) \|\| \
AnnaBridge	156:ff21514d8981	331	((SOURCE) == RCC_USART2CLKSOURCE_HSI))
AnnaBridge	156:ff21514d8981	332
AnnaBridge	156:ff21514d8981	333	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
AnnaBridge	156:ff21514d8981	334	/* STM32F091xC \|\| STM32F098xx */
AnnaBridge	156:ff21514d8981	335
AnnaBridge	156:ff21514d8981	336	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
AnnaBridge	156:ff21514d8981	337
AnnaBridge	156:ff21514d8981	338	#define IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) \|\| \
AnnaBridge	156:ff21514d8981	339	((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) \|\| \
AnnaBridge	156:ff21514d8981	340	((SOURCE) == RCC_USART3CLKSOURCE_LSE) \|\| \
AnnaBridge	156:ff21514d8981	341	((SOURCE) == RCC_USART3CLKSOURCE_HSI))
AnnaBridge	156:ff21514d8981	342	#endif /* STM32F091xC \|\| STM32F098xx */
AnnaBridge	156:ff21514d8981	343
AnnaBridge	156:ff21514d8981	344
AnnaBridge	156:ff21514d8981	345	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
AnnaBridge	156:ff21514d8981	346	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
AnnaBridge	156:ff21514d8981	347	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
AnnaBridge	156:ff21514d8981	348	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
AnnaBridge	156:ff21514d8981	349
AnnaBridge	156:ff21514d8981	350	#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) \|\| \
AnnaBridge	156:ff21514d8981	351	((SOURCE) == RCC_CECCLKSOURCE_LSE))
AnnaBridge	156:ff21514d8981	352	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
AnnaBridge	156:ff21514d8981	353	/* STM32F051x8 \|\| STM32F058xx \|\| */
AnnaBridge	156:ff21514d8981	354	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
AnnaBridge	156:ff21514d8981	355	/* STM32F091xC \|\| STM32F098xx */
AnnaBridge	156:ff21514d8981	356
AnnaBridge	156:ff21514d8981	357	#if defined(RCC_CFGR_MCOPRE)
AnnaBridge	156:ff21514d8981	358
AnnaBridge	156:ff21514d8981	359	#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) \|\| ((DIV) == RCC_MCODIV_2) \|\| \
AnnaBridge	156:ff21514d8981	360	((DIV) == RCC_MCODIV_4) \|\| ((DIV) == RCC_MCODIV_8) \|\| \
AnnaBridge	156:ff21514d8981	361	((DIV) == RCC_MCODIV_16) \|\| ((DIV) == RCC_MCODIV_32) \|\| \
AnnaBridge	156:ff21514d8981	362	((DIV) == RCC_MCODIV_64) \|\| ((DIV) == RCC_MCODIV_128))
AnnaBridge	156:ff21514d8981	363	#else
AnnaBridge	156:ff21514d8981	364
AnnaBridge	156:ff21514d8981	365	#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1))
AnnaBridge	156:ff21514d8981	366
AnnaBridge	156:ff21514d8981	367	#endif /* RCC_CFGR_MCOPRE */
AnnaBridge	156:ff21514d8981	368
AnnaBridge	156:ff21514d8981	369	#define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) \|\| \
AnnaBridge	156:ff21514d8981	370	((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) \|\| \
AnnaBridge	156:ff21514d8981	371	((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) \|\| \
AnnaBridge	156:ff21514d8981	372	((__DRIVE__) == RCC_LSEDRIVE_HIGH))
AnnaBridge	156:ff21514d8981	373
AnnaBridge	156:ff21514d8981	374	#if defined(CRS)
AnnaBridge	156:ff21514d8981	375
AnnaBridge	156:ff21514d8981	376	#define IS_RCC_CRS_SYNC_SOURCE(_SOURCE_) (((_SOURCE_) == RCC_CRS_SYNC_SOURCE_GPIO) \|\| \
AnnaBridge	156:ff21514d8981	377	((_SOURCE_) == RCC_CRS_SYNC_SOURCE_LSE) \|\| \
AnnaBridge	156:ff21514d8981	378	((_SOURCE_) == RCC_CRS_SYNC_SOURCE_USB))
AnnaBridge	156:ff21514d8981	379	#define IS_RCC_CRS_SYNC_DIV(_DIV_) (((_DIV_) == RCC_CRS_SYNC_DIV1) \|\| ((_DIV_) == RCC_CRS_SYNC_DIV2) \|\| \
AnnaBridge	156:ff21514d8981	380	((_DIV_) == RCC_CRS_SYNC_DIV4) \|\| ((_DIV_) == RCC_CRS_SYNC_DIV8) \|\| \
AnnaBridge	156:ff21514d8981	381	((_DIV_) == RCC_CRS_SYNC_DIV16) \|\| ((_DIV_) == RCC_CRS_SYNC_DIV32) \|\| \
AnnaBridge	156:ff21514d8981	382	((_DIV_) == RCC_CRS_SYNC_DIV64) \|\| ((_DIV_) == RCC_CRS_SYNC_DIV128))
AnnaBridge	156:ff21514d8981	383	#define IS_RCC_CRS_SYNC_POLARITY(_POLARITY_) (((_POLARITY_) == RCC_CRS_SYNC_POLARITY_RISING) \|\| \
AnnaBridge	156:ff21514d8981	384	((_POLARITY_) == RCC_CRS_SYNC_POLARITY_FALLING))
AnnaBridge	156:ff21514d8981	385	#define IS_RCC_CRS_RELOADVALUE(_VALUE_) (((_VALUE_) <= 0xFFFFU))
AnnaBridge	156:ff21514d8981	386	#define IS_RCC_CRS_ERRORLIMIT(_VALUE_) (((_VALUE_) <= 0xFFU))
AnnaBridge	156:ff21514d8981	387	#define IS_RCC_CRS_HSI48CALIBRATION(_VALUE_) (((_VALUE_) <= 0x3FU))
AnnaBridge	156:ff21514d8981	388	#define IS_RCC_CRS_FREQERRORDIR(_DIR_) (((_DIR_) == RCC_CRS_FREQERRORDIR_UP) \|\| \
AnnaBridge	156:ff21514d8981	389	((_DIR_) == RCC_CRS_FREQERRORDIR_DOWN))
AnnaBridge	156:ff21514d8981	390	#endif /* CRS */
AnnaBridge	156:ff21514d8981	391	/**
AnnaBridge	156:ff21514d8981	392	* @}
AnnaBridge	156:ff21514d8981	393	*/
AnnaBridge	156:ff21514d8981	394
AnnaBridge	156:ff21514d8981	395	/* Exported types ------------------------------------------------------------*/
AnnaBridge	156:ff21514d8981	396
AnnaBridge	156:ff21514d8981	397	/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
AnnaBridge	156:ff21514d8981	398	* @{
AnnaBridge	156:ff21514d8981	399	*/
AnnaBridge	156:ff21514d8981	400
AnnaBridge	156:ff21514d8981	401	/**
AnnaBridge	156:ff21514d8981	402	* @brief RCC extended clocks structure definition
AnnaBridge	156:ff21514d8981	403	*/
AnnaBridge	156:ff21514d8981	404	#if defined(STM32F030x6) \|\| defined(STM32F030x8) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx)\
AnnaBridge	156:ff21514d8981	405	\|\| defined(STM32F030xC)
AnnaBridge	156:ff21514d8981	406	typedef struct
AnnaBridge	156:ff21514d8981	407	{
AnnaBridge	156:ff21514d8981	408	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
AnnaBridge	156:ff21514d8981	409	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
AnnaBridge	156:ff21514d8981	410
AnnaBridge	156:ff21514d8981	411	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
AnnaBridge	156:ff21514d8981	412	This parameter can be a value of @ref RCC_RTC_Clock_Source */
AnnaBridge	156:ff21514d8981	413
AnnaBridge	156:ff21514d8981	414	uint32_t Usart1ClockSelection; /*!< USART1 clock source
AnnaBridge	156:ff21514d8981	415	This parameter can be a value of @ref RCC_USART1_Clock_Source */
AnnaBridge	156:ff21514d8981	416
AnnaBridge	156:ff21514d8981	417	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
AnnaBridge	156:ff21514d8981	418	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
AnnaBridge	156:ff21514d8981	419
AnnaBridge	156:ff21514d8981	420	}RCC_PeriphCLKInitTypeDef;
AnnaBridge	156:ff21514d8981	421	#endif /* STM32F030x6 \|\| STM32F030x8 \|\| STM32F031x6 \|\| STM32F038xx \|\|
AnnaBridge	156:ff21514d8981	422	STM32F030xC */
AnnaBridge	156:ff21514d8981	423
AnnaBridge	156:ff21514d8981	424	#if defined(STM32F070x6) \|\| defined(STM32F070xB)
AnnaBridge	156:ff21514d8981	425	typedef struct
AnnaBridge	156:ff21514d8981	426	{
AnnaBridge	156:ff21514d8981	427	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
AnnaBridge	156:ff21514d8981	428	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
AnnaBridge	156:ff21514d8981	429
AnnaBridge	156:ff21514d8981	430	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
AnnaBridge	156:ff21514d8981	431	This parameter can be a value of @ref RCC_RTC_Clock_Source */
AnnaBridge	156:ff21514d8981	432
AnnaBridge	156:ff21514d8981	433	uint32_t Usart1ClockSelection; /*!< USART1 clock source
AnnaBridge	156:ff21514d8981	434	This parameter can be a value of @ref RCC_USART1_Clock_Source */
AnnaBridge	156:ff21514d8981	435
AnnaBridge	156:ff21514d8981	436	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
AnnaBridge	156:ff21514d8981	437	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
AnnaBridge	156:ff21514d8981	438
AnnaBridge	156:ff21514d8981	439	uint32_t UsbClockSelection; /*!< USB clock source
AnnaBridge	156:ff21514d8981	440	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
AnnaBridge	156:ff21514d8981	441
AnnaBridge	156:ff21514d8981	442	}RCC_PeriphCLKInitTypeDef;
AnnaBridge	156:ff21514d8981	443	#endif /* STM32F070x6 \|\| STM32F070xB */
AnnaBridge	156:ff21514d8981	444
AnnaBridge	156:ff21514d8981	445	#if defined(STM32F042x6) \|\| defined(STM32F048xx)
AnnaBridge	156:ff21514d8981	446	typedef struct
AnnaBridge	156:ff21514d8981	447	{
AnnaBridge	156:ff21514d8981	448	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
AnnaBridge	156:ff21514d8981	449	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
AnnaBridge	156:ff21514d8981	450
AnnaBridge	156:ff21514d8981	451	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
AnnaBridge	156:ff21514d8981	452	This parameter can be a value of @ref RCC_RTC_Clock_Source */
AnnaBridge	156:ff21514d8981	453
AnnaBridge	156:ff21514d8981	454	uint32_t Usart1ClockSelection; /*!< USART1 clock source
AnnaBridge	156:ff21514d8981	455	This parameter can be a value of @ref RCC_USART1_Clock_Source */
AnnaBridge	156:ff21514d8981	456
AnnaBridge	156:ff21514d8981	457	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
AnnaBridge	156:ff21514d8981	458	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
AnnaBridge	156:ff21514d8981	459
AnnaBridge	156:ff21514d8981	460	uint32_t CecClockSelection; /*!< HDMI CEC clock source
AnnaBridge	156:ff21514d8981	461	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
AnnaBridge	156:ff21514d8981	462
AnnaBridge	156:ff21514d8981	463	uint32_t UsbClockSelection; /*!< USB clock source
AnnaBridge	156:ff21514d8981	464	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
AnnaBridge	156:ff21514d8981	465
AnnaBridge	156:ff21514d8981	466	}RCC_PeriphCLKInitTypeDef;
AnnaBridge	156:ff21514d8981	467	#endif /* STM32F042x6 \|\| STM32F048xx */
AnnaBridge	156:ff21514d8981	468
AnnaBridge	156:ff21514d8981	469	#if defined(STM32F051x8) \|\| defined(STM32F058xx)
AnnaBridge	156:ff21514d8981	470	typedef struct
AnnaBridge	156:ff21514d8981	471	{
AnnaBridge	156:ff21514d8981	472	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
AnnaBridge	156:ff21514d8981	473	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
AnnaBridge	156:ff21514d8981	474
AnnaBridge	156:ff21514d8981	475	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
AnnaBridge	156:ff21514d8981	476	This parameter can be a value of @ref RCC_RTC_Clock_Source */
AnnaBridge	156:ff21514d8981	477
AnnaBridge	156:ff21514d8981	478	uint32_t Usart1ClockSelection; /*!< USART1 clock source
AnnaBridge	156:ff21514d8981	479	This parameter can be a value of @ref RCC_USART1_Clock_Source */
AnnaBridge	156:ff21514d8981	480
AnnaBridge	156:ff21514d8981	481	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
AnnaBridge	156:ff21514d8981	482	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
AnnaBridge	156:ff21514d8981	483
AnnaBridge	156:ff21514d8981	484	uint32_t CecClockSelection; /*!< HDMI CEC clock source
AnnaBridge	156:ff21514d8981	485	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
AnnaBridge	156:ff21514d8981	486
AnnaBridge	156:ff21514d8981	487	}RCC_PeriphCLKInitTypeDef;
AnnaBridge	156:ff21514d8981	488	#endif /* STM32F051x8 \|\| STM32F058xx */
AnnaBridge	156:ff21514d8981	489
AnnaBridge	156:ff21514d8981	490	#if defined(STM32F071xB)
AnnaBridge	156:ff21514d8981	491	typedef struct
AnnaBridge	156:ff21514d8981	492	{
AnnaBridge	156:ff21514d8981	493	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
AnnaBridge	156:ff21514d8981	494	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
AnnaBridge	156:ff21514d8981	495
AnnaBridge	156:ff21514d8981	496	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
AnnaBridge	156:ff21514d8981	497	This parameter can be a value of @ref RCC_RTC_Clock_Source */
AnnaBridge	156:ff21514d8981	498
AnnaBridge	156:ff21514d8981	499	uint32_t Usart1ClockSelection; /*!< USART1 clock source
AnnaBridge	156:ff21514d8981	500	This parameter can be a value of @ref RCC_USART1_Clock_Source */
AnnaBridge	156:ff21514d8981	501
AnnaBridge	156:ff21514d8981	502	uint32_t Usart2ClockSelection; /*!< USART2 clock source
AnnaBridge	156:ff21514d8981	503	This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
AnnaBridge	156:ff21514d8981	504
AnnaBridge	156:ff21514d8981	505	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
AnnaBridge	156:ff21514d8981	506	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
AnnaBridge	156:ff21514d8981	507
AnnaBridge	156:ff21514d8981	508	uint32_t CecClockSelection; /*!< HDMI CEC clock source
AnnaBridge	156:ff21514d8981	509	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
AnnaBridge	156:ff21514d8981	510
AnnaBridge	156:ff21514d8981	511	}RCC_PeriphCLKInitTypeDef;
AnnaBridge	156:ff21514d8981	512	#endif /* STM32F071xB */
AnnaBridge	156:ff21514d8981	513
AnnaBridge	156:ff21514d8981	514	#if defined(STM32F072xB) \|\| defined(STM32F078xx)
AnnaBridge	156:ff21514d8981	515	typedef struct
AnnaBridge	156:ff21514d8981	516	{
AnnaBridge	156:ff21514d8981	517	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
AnnaBridge	156:ff21514d8981	518	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
AnnaBridge	156:ff21514d8981	519
AnnaBridge	156:ff21514d8981	520	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
AnnaBridge	156:ff21514d8981	521	This parameter can be a value of @ref RCC_RTC_Clock_Source */
AnnaBridge	156:ff21514d8981	522
AnnaBridge	156:ff21514d8981	523	uint32_t Usart1ClockSelection; /*!< USART1 clock source
AnnaBridge	156:ff21514d8981	524	This parameter can be a value of @ref RCC_USART1_Clock_Source */
AnnaBridge	156:ff21514d8981	525
AnnaBridge	156:ff21514d8981	526	uint32_t Usart2ClockSelection; /*!< USART2 clock source
AnnaBridge	156:ff21514d8981	527	This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
AnnaBridge	156:ff21514d8981	528
AnnaBridge	156:ff21514d8981	529	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
AnnaBridge	156:ff21514d8981	530	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
AnnaBridge	156:ff21514d8981	531
AnnaBridge	156:ff21514d8981	532	uint32_t CecClockSelection; /*!< HDMI CEC clock source
AnnaBridge	156:ff21514d8981	533	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
AnnaBridge	156:ff21514d8981	534
AnnaBridge	156:ff21514d8981	535	uint32_t UsbClockSelection; /*!< USB clock source
AnnaBridge	156:ff21514d8981	536	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
AnnaBridge	156:ff21514d8981	537
AnnaBridge	156:ff21514d8981	538	}RCC_PeriphCLKInitTypeDef;
AnnaBridge	156:ff21514d8981	539	#endif /* STM32F072xB \|\| STM32F078xx */
AnnaBridge	156:ff21514d8981	540
AnnaBridge	156:ff21514d8981	541
AnnaBridge	156:ff21514d8981	542	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
AnnaBridge	156:ff21514d8981	543	typedef struct
AnnaBridge	156:ff21514d8981	544	{
AnnaBridge	156:ff21514d8981	545	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
AnnaBridge	156:ff21514d8981	546	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
AnnaBridge	156:ff21514d8981	547
AnnaBridge	156:ff21514d8981	548	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
AnnaBridge	156:ff21514d8981	549	This parameter can be a value of @ref RCC_RTC_Clock_Source */
AnnaBridge	156:ff21514d8981	550
AnnaBridge	156:ff21514d8981	551	uint32_t Usart1ClockSelection; /*!< USART1 clock source
AnnaBridge	156:ff21514d8981	552	This parameter can be a value of @ref RCC_USART1_Clock_Source */
AnnaBridge	156:ff21514d8981	553
AnnaBridge	156:ff21514d8981	554	uint32_t Usart2ClockSelection; /*!< USART2 clock source
AnnaBridge	156:ff21514d8981	555	This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
AnnaBridge	156:ff21514d8981	556
AnnaBridge	156:ff21514d8981	557	uint32_t Usart3ClockSelection; /*!< USART3 clock source
AnnaBridge	156:ff21514d8981	558	This parameter can be a value of @ref RCCEx_USART3_Clock_Source */
AnnaBridge	156:ff21514d8981	559
AnnaBridge	156:ff21514d8981	560	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
AnnaBridge	156:ff21514d8981	561	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
AnnaBridge	156:ff21514d8981	562
AnnaBridge	156:ff21514d8981	563	uint32_t CecClockSelection; /*!< HDMI CEC clock source
AnnaBridge	156:ff21514d8981	564	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
AnnaBridge	156:ff21514d8981	565
AnnaBridge	156:ff21514d8981	566	}RCC_PeriphCLKInitTypeDef;
AnnaBridge	156:ff21514d8981	567	#endif /* STM32F091xC \|\| STM32F098xx */
AnnaBridge	156:ff21514d8981	568
AnnaBridge	156:ff21514d8981	569	#if defined(CRS)
AnnaBridge	156:ff21514d8981	570
AnnaBridge	156:ff21514d8981	571	/**
AnnaBridge	156:ff21514d8981	572	* @brief RCC_CRS Init structure definition
AnnaBridge	156:ff21514d8981	573	*/
AnnaBridge	156:ff21514d8981	574	typedef struct
AnnaBridge	156:ff21514d8981	575	{
AnnaBridge	156:ff21514d8981	576	uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal.
AnnaBridge	156:ff21514d8981	577	This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */
AnnaBridge	156:ff21514d8981	578
AnnaBridge	156:ff21514d8981	579	uint32_t Source; /*!< Specifies the SYNC signal source.
AnnaBridge	156:ff21514d8981	580	This parameter can be a value of @ref RCCEx_CRS_SynchroSource */
AnnaBridge	156:ff21514d8981	581
AnnaBridge	156:ff21514d8981	582	uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source.
AnnaBridge	156:ff21514d8981	583	This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */
AnnaBridge	156:ff21514d8981	584
AnnaBridge	156:ff21514d8981	585	uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event.
AnnaBridge	156:ff21514d8981	586	It can be calculated in using macro @ref __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__)
AnnaBridge	156:ff21514d8981	587	This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/
AnnaBridge	156:ff21514d8981	588
AnnaBridge	156:ff21514d8981	589	uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value.
AnnaBridge	156:ff21514d8981	590	This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */
AnnaBridge	156:ff21514d8981	591
AnnaBridge	156:ff21514d8981	592	uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator.
AnnaBridge	156:ff21514d8981	593	This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */
AnnaBridge	156:ff21514d8981	594
AnnaBridge	156:ff21514d8981	595	}RCC_CRSInitTypeDef;
AnnaBridge	156:ff21514d8981	596
AnnaBridge	156:ff21514d8981	597	/**
AnnaBridge	156:ff21514d8981	598	* @brief RCC_CRS Synchronization structure definition
AnnaBridge	156:ff21514d8981	599	*/
AnnaBridge	156:ff21514d8981	600	typedef struct
AnnaBridge	156:ff21514d8981	601	{
AnnaBridge	156:ff21514d8981	602	uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value.
AnnaBridge	156:ff21514d8981	603	This parameter must be a number between 0 and 0xFFFF */
AnnaBridge	156:ff21514d8981	604
AnnaBridge	156:ff21514d8981	605	uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming.
AnnaBridge	156:ff21514d8981	606	This parameter must be a number between 0 and 0x3F */
AnnaBridge	156:ff21514d8981	607
AnnaBridge	156:ff21514d8981	608	uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter
AnnaBridge	156:ff21514d8981	609	value latched in the time of the last SYNC event.
AnnaBridge	156:ff21514d8981	610	This parameter must be a number between 0 and 0xFFFF */
AnnaBridge	156:ff21514d8981	611
AnnaBridge	156:ff21514d8981	612	uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the
AnnaBridge	156:ff21514d8981	613	frequency error counter latched in the time of the last SYNC event.
AnnaBridge	156:ff21514d8981	614	It shows whether the actual frequency is below or above the target.
AnnaBridge	156:ff21514d8981	615	This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/
AnnaBridge	156:ff21514d8981	616
AnnaBridge	156:ff21514d8981	617	}RCC_CRSSynchroInfoTypeDef;
AnnaBridge	156:ff21514d8981	618
AnnaBridge	156:ff21514d8981	619	#endif /* CRS */
AnnaBridge	156:ff21514d8981	620
AnnaBridge	156:ff21514d8981	621	/**
AnnaBridge	156:ff21514d8981	622	* @}
AnnaBridge	156:ff21514d8981	623	*/
AnnaBridge	156:ff21514d8981	624
AnnaBridge	156:ff21514d8981	625	/* Exported constants --------------------------------------------------------*/
AnnaBridge	156:ff21514d8981	626
AnnaBridge	156:ff21514d8981	627	/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
AnnaBridge	156:ff21514d8981	628	* @{
AnnaBridge	156:ff21514d8981	629	*/
AnnaBridge	156:ff21514d8981	630
AnnaBridge	156:ff21514d8981	631	/** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection
AnnaBridge	156:ff21514d8981	632	* @{
AnnaBridge	156:ff21514d8981	633	*/
AnnaBridge	156:ff21514d8981	634	#if defined(STM32F030x6) \|\| defined(STM32F030x8) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx)\
AnnaBridge	156:ff21514d8981	635	\|\| defined(STM32F030xC)
AnnaBridge	156:ff21514d8981	636	#define RCC_PERIPHCLK_USART1 (0x00000001U)
AnnaBridge	156:ff21514d8981	637	#define RCC_PERIPHCLK_I2C1 (0x00000020U)
AnnaBridge	156:ff21514d8981	638	#define RCC_PERIPHCLK_RTC (0x00010000U)
AnnaBridge	156:ff21514d8981	639
AnnaBridge	156:ff21514d8981	640	#endif /* STM32F030x6 \|\| STM32F030x8 \|\| STM32F031x6 \|\| STM32F038xx \|\|
AnnaBridge	156:ff21514d8981	641	STM32F030xC */
AnnaBridge	156:ff21514d8981	642
AnnaBridge	156:ff21514d8981	643	#if defined(STM32F070x6) \|\| defined(STM32F070xB)
AnnaBridge	156:ff21514d8981	644	#define RCC_PERIPHCLK_USART1 (0x00000001U)
AnnaBridge	156:ff21514d8981	645	#define RCC_PERIPHCLK_I2C1 (0x00000020U)
AnnaBridge	156:ff21514d8981	646	#define RCC_PERIPHCLK_RTC (0x00010000U)
AnnaBridge	156:ff21514d8981	647	#define RCC_PERIPHCLK_USB (0x00020000U)
AnnaBridge	156:ff21514d8981	648
AnnaBridge	156:ff21514d8981	649	#endif /* STM32F070x6 \|\| STM32F070xB */
AnnaBridge	156:ff21514d8981	650
AnnaBridge	156:ff21514d8981	651	#if defined(STM32F042x6) \|\| defined(STM32F048xx)
AnnaBridge	156:ff21514d8981	652	#define RCC_PERIPHCLK_USART1 (0x00000001U)
AnnaBridge	156:ff21514d8981	653	#define RCC_PERIPHCLK_I2C1 (0x00000020U)
AnnaBridge	156:ff21514d8981	654	#define RCC_PERIPHCLK_CEC (0x00000400U)
AnnaBridge	156:ff21514d8981	655	#define RCC_PERIPHCLK_RTC (0x00010000U)
AnnaBridge	156:ff21514d8981	656	#define RCC_PERIPHCLK_USB (0x00020000U)
AnnaBridge	156:ff21514d8981	657
AnnaBridge	156:ff21514d8981	658	#endif /* STM32F042x6 \|\| STM32F048xx */
AnnaBridge	156:ff21514d8981	659
AnnaBridge	156:ff21514d8981	660	#if defined(STM32F051x8) \|\| defined(STM32F058xx)
AnnaBridge	156:ff21514d8981	661	#define RCC_PERIPHCLK_USART1 (0x00000001U)
AnnaBridge	156:ff21514d8981	662	#define RCC_PERIPHCLK_I2C1 (0x00000020U)
AnnaBridge	156:ff21514d8981	663	#define RCC_PERIPHCLK_CEC (0x00000400U)
AnnaBridge	156:ff21514d8981	664	#define RCC_PERIPHCLK_RTC (0x00010000U)
AnnaBridge	156:ff21514d8981	665
AnnaBridge	156:ff21514d8981	666	#endif /* STM32F051x8 \|\| STM32F058xx */
AnnaBridge	156:ff21514d8981	667
AnnaBridge	156:ff21514d8981	668	#if defined(STM32F071xB)
AnnaBridge	156:ff21514d8981	669	#define RCC_PERIPHCLK_USART1 (0x00000001U)
AnnaBridge	156:ff21514d8981	670	#define RCC_PERIPHCLK_USART2 (0x00000002U)
AnnaBridge	156:ff21514d8981	671	#define RCC_PERIPHCLK_I2C1 (0x00000020U)
AnnaBridge	156:ff21514d8981	672	#define RCC_PERIPHCLK_CEC (0x00000400U)
AnnaBridge	156:ff21514d8981	673	#define RCC_PERIPHCLK_RTC (0x00010000U)
AnnaBridge	156:ff21514d8981	674
AnnaBridge	156:ff21514d8981	675	#endif /* STM32F071xB */
AnnaBridge	156:ff21514d8981	676
AnnaBridge	156:ff21514d8981	677	#if defined(STM32F072xB) \|\| defined(STM32F078xx)
AnnaBridge	156:ff21514d8981	678	#define RCC_PERIPHCLK_USART1 (0x00000001U)
AnnaBridge	156:ff21514d8981	679	#define RCC_PERIPHCLK_USART2 (0x00000002U)
AnnaBridge	156:ff21514d8981	680	#define RCC_PERIPHCLK_I2C1 (0x00000020U)
AnnaBridge	156:ff21514d8981	681	#define RCC_PERIPHCLK_CEC (0x00000400U)
AnnaBridge	156:ff21514d8981	682	#define RCC_PERIPHCLK_RTC (0x00010000U)
AnnaBridge	156:ff21514d8981	683	#define RCC_PERIPHCLK_USB (0x00020000U)
AnnaBridge	156:ff21514d8981	684
AnnaBridge	156:ff21514d8981	685	#endif /* STM32F072xB \|\| STM32F078xx */
AnnaBridge	156:ff21514d8981	686
AnnaBridge	156:ff21514d8981	687	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
AnnaBridge	156:ff21514d8981	688	#define RCC_PERIPHCLK_USART1 (0x00000001U)
AnnaBridge	156:ff21514d8981	689	#define RCC_PERIPHCLK_USART2 (0x00000002U)
AnnaBridge	156:ff21514d8981	690	#define RCC_PERIPHCLK_I2C1 (0x00000020U)
AnnaBridge	156:ff21514d8981	691	#define RCC_PERIPHCLK_CEC (0x00000400U)
AnnaBridge	156:ff21514d8981	692	#define RCC_PERIPHCLK_RTC (0x00010000U)
AnnaBridge	156:ff21514d8981	693	#define RCC_PERIPHCLK_USART3 (0x00040000U)
AnnaBridge	156:ff21514d8981	694
AnnaBridge	156:ff21514d8981	695	#endif /* STM32F091xC \|\| STM32F098xx */
AnnaBridge	156:ff21514d8981	696
AnnaBridge	156:ff21514d8981	697	/**
AnnaBridge	156:ff21514d8981	698	* @}
AnnaBridge	156:ff21514d8981	699	*/
AnnaBridge	156:ff21514d8981	700
AnnaBridge	156:ff21514d8981	701	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)
AnnaBridge	156:ff21514d8981	702
AnnaBridge	156:ff21514d8981	703	/** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source
AnnaBridge	156:ff21514d8981	704	* @{
AnnaBridge	156:ff21514d8981	705	*/
AnnaBridge	156:ff21514d8981	706	#define RCC_USBCLKSOURCE_HSI48 RCC_CFGR3_USBSW_HSI48 /!< HSI48 clock selected as USB clock source /
AnnaBridge	156:ff21514d8981	707	#define RCC_USBCLKSOURCE_PLL RCC_CFGR3_USBSW_PLLCLK /!< PLL clock (PLLCLK) selected as USB clock /
AnnaBridge	156:ff21514d8981	708
AnnaBridge	156:ff21514d8981	709	/**
AnnaBridge	156:ff21514d8981	710	* @}
AnnaBridge	156:ff21514d8981	711	*/
AnnaBridge	156:ff21514d8981	712
AnnaBridge	156:ff21514d8981	713	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F072xB \|\| STM32F078xx */
AnnaBridge	156:ff21514d8981	714
AnnaBridge	156:ff21514d8981	715	#if defined(STM32F070x6) \|\| defined(STM32F070xB)
AnnaBridge	156:ff21514d8981	716
AnnaBridge	156:ff21514d8981	717	/** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source
AnnaBridge	156:ff21514d8981	718	* @{
AnnaBridge	156:ff21514d8981	719	*/
AnnaBridge	156:ff21514d8981	720	#define RCC_USBCLKSOURCE_NONE (0x00000000U) /!< USB clock disabled /
AnnaBridge	156:ff21514d8981	721	#define RCC_USBCLKSOURCE_PLL RCC_CFGR3_USBSW_PLLCLK /!< PLL clock (PLLCLK) selected as USB clock /
AnnaBridge	156:ff21514d8981	722
AnnaBridge	156:ff21514d8981	723	/**
AnnaBridge	156:ff21514d8981	724	* @}
AnnaBridge	156:ff21514d8981	725	*/
AnnaBridge	156:ff21514d8981	726
AnnaBridge	156:ff21514d8981	727	#endif /* STM32F070x6 \|\| STM32F070xB */
AnnaBridge	156:ff21514d8981	728
AnnaBridge	156:ff21514d8981	729	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
AnnaBridge	156:ff21514d8981	730	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
AnnaBridge	156:ff21514d8981	731
AnnaBridge	156:ff21514d8981	732	/** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source
AnnaBridge	156:ff21514d8981	733	* @{
AnnaBridge	156:ff21514d8981	734	*/
AnnaBridge	156:ff21514d8981	735	#define RCC_USART2CLKSOURCE_PCLK1 RCC_CFGR3_USART2SW_PCLK
AnnaBridge	156:ff21514d8981	736	#define RCC_USART2CLKSOURCE_SYSCLK RCC_CFGR3_USART2SW_SYSCLK
AnnaBridge	156:ff21514d8981	737	#define RCC_USART2CLKSOURCE_LSE RCC_CFGR3_USART2SW_LSE
AnnaBridge	156:ff21514d8981	738	#define RCC_USART2CLKSOURCE_HSI RCC_CFGR3_USART2SW_HSI
AnnaBridge	156:ff21514d8981	739
AnnaBridge	156:ff21514d8981	740	/**
AnnaBridge	156:ff21514d8981	741	* @}
AnnaBridge	156:ff21514d8981	742	*/
AnnaBridge	156:ff21514d8981	743
AnnaBridge	156:ff21514d8981	744	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
AnnaBridge	156:ff21514d8981	745	/* STM32F091xC \|\| STM32F098xx */
AnnaBridge	156:ff21514d8981	746
AnnaBridge	156:ff21514d8981	747	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
AnnaBridge	156:ff21514d8981	748
AnnaBridge	156:ff21514d8981	749	/** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source
AnnaBridge	156:ff21514d8981	750	* @{
AnnaBridge	156:ff21514d8981	751	*/
AnnaBridge	156:ff21514d8981	752	#define RCC_USART3CLKSOURCE_PCLK1 RCC_CFGR3_USART3SW_PCLK
AnnaBridge	156:ff21514d8981	753	#define RCC_USART3CLKSOURCE_SYSCLK RCC_CFGR3_USART3SW_SYSCLK
AnnaBridge	156:ff21514d8981	754	#define RCC_USART3CLKSOURCE_LSE RCC_CFGR3_USART3SW_LSE
AnnaBridge	156:ff21514d8981	755	#define RCC_USART3CLKSOURCE_HSI RCC_CFGR3_USART3SW_HSI
AnnaBridge	156:ff21514d8981	756
AnnaBridge	156:ff21514d8981	757	/**
AnnaBridge	156:ff21514d8981	758	* @}
AnnaBridge	156:ff21514d8981	759	*/
AnnaBridge	156:ff21514d8981	760
AnnaBridge	156:ff21514d8981	761	#endif /* STM32F091xC \|\| STM32F098xx */
AnnaBridge	156:ff21514d8981	762
AnnaBridge	156:ff21514d8981	763
AnnaBridge	156:ff21514d8981	764	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
AnnaBridge	156:ff21514d8981	765	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
AnnaBridge	156:ff21514d8981	766	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
AnnaBridge	156:ff21514d8981	767	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
AnnaBridge	156:ff21514d8981	768
AnnaBridge	156:ff21514d8981	769	/** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source
AnnaBridge	156:ff21514d8981	770	* @{
AnnaBridge	156:ff21514d8981	771	*/
AnnaBridge	156:ff21514d8981	772	#define RCC_CECCLKSOURCE_HSI RCC_CFGR3_CECSW_HSI_DIV244
AnnaBridge	156:ff21514d8981	773	#define RCC_CECCLKSOURCE_LSE RCC_CFGR3_CECSW_LSE
AnnaBridge	156:ff21514d8981	774
AnnaBridge	156:ff21514d8981	775	/**
AnnaBridge	156:ff21514d8981	776	* @}
AnnaBridge	156:ff21514d8981	777	*/
AnnaBridge	156:ff21514d8981	778
AnnaBridge	156:ff21514d8981	779	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
AnnaBridge	156:ff21514d8981	780	/* STM32F051x8 \|\| STM32F058xx \|\| */
AnnaBridge	156:ff21514d8981	781	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
AnnaBridge	156:ff21514d8981	782	/* STM32F091xC \|\| STM32F098xx */
AnnaBridge	156:ff21514d8981	783
AnnaBridge	156:ff21514d8981	784	/** @defgroup RCCEx_MCOx_Clock_Prescaler RCCEx MCOx Clock Prescaler
AnnaBridge	156:ff21514d8981	785	* @{
AnnaBridge	156:ff21514d8981	786	*/
AnnaBridge	156:ff21514d8981	787
AnnaBridge	156:ff21514d8981	788	#if defined(RCC_CFGR_MCOPRE)
AnnaBridge	156:ff21514d8981	789
AnnaBridge	156:ff21514d8981	790	#define RCC_MCODIV_1 (0x00000000U)
AnnaBridge	156:ff21514d8981	791	#define RCC_MCODIV_2 (0x10000000U)
AnnaBridge	156:ff21514d8981	792	#define RCC_MCODIV_4 (0x20000000U)
AnnaBridge	156:ff21514d8981	793	#define RCC_MCODIV_8 (0x30000000U)
AnnaBridge	156:ff21514d8981	794	#define RCC_MCODIV_16 (0x40000000U)
AnnaBridge	156:ff21514d8981	795	#define RCC_MCODIV_32 (0x50000000U)
AnnaBridge	156:ff21514d8981	796	#define RCC_MCODIV_64 (0x60000000U)
AnnaBridge	156:ff21514d8981	797	#define RCC_MCODIV_128 (0x70000000U)
AnnaBridge	156:ff21514d8981	798
AnnaBridge	156:ff21514d8981	799	#else
AnnaBridge	156:ff21514d8981	800
AnnaBridge	156:ff21514d8981	801	#define RCC_MCODIV_1 (0x00000000U)
AnnaBridge	156:ff21514d8981	802
AnnaBridge	156:ff21514d8981	803	#endif /* RCC_CFGR_MCOPRE */
AnnaBridge	156:ff21514d8981	804
AnnaBridge	156:ff21514d8981	805	/**
AnnaBridge	156:ff21514d8981	806	* @}
AnnaBridge	156:ff21514d8981	807	*/
AnnaBridge	156:ff21514d8981	808
AnnaBridge	156:ff21514d8981	809	/** @defgroup RCCEx_LSEDrive_Configuration RCC LSE Drive Configuration
AnnaBridge	156:ff21514d8981	810	* @{
AnnaBridge	156:ff21514d8981	811	*/
AnnaBridge	156:ff21514d8981	812
AnnaBridge	156:ff21514d8981	813	#define RCC_LSEDRIVE_LOW (0x00000000U) /!< Xtal mode lower driving capability /
AnnaBridge	156:ff21514d8981	814	#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 /!< Xtal mode medium low driving capability /
AnnaBridge	156:ff21514d8981	815	#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 /!< Xtal mode medium high driving capability /
AnnaBridge	156:ff21514d8981	816	#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /!< Xtal mode higher driving capability /
AnnaBridge	156:ff21514d8981	817
AnnaBridge	156:ff21514d8981	818	/**
AnnaBridge	156:ff21514d8981	819	* @}
AnnaBridge	156:ff21514d8981	820	*/
AnnaBridge	156:ff21514d8981	821
AnnaBridge	156:ff21514d8981	822	#if defined(CRS)
AnnaBridge	156:ff21514d8981	823
AnnaBridge	156:ff21514d8981	824	/** @defgroup RCCEx_CRS_Status RCCEx CRS Status
AnnaBridge	156:ff21514d8981	825	* @{
AnnaBridge	156:ff21514d8981	826	*/
AnnaBridge	156:ff21514d8981	827	#define RCC_CRS_NONE (0x00000000U)
AnnaBridge	156:ff21514d8981	828	#define RCC_CRS_TIMEOUT (0x00000001U)
AnnaBridge	156:ff21514d8981	829	#define RCC_CRS_SYNCOK (0x00000002U)
AnnaBridge	156:ff21514d8981	830	#define RCC_CRS_SYNCWARN (0x00000004U)
AnnaBridge	156:ff21514d8981	831	#define RCC_CRS_SYNCERR (0x00000008U)
AnnaBridge	156:ff21514d8981	832	#define RCC_CRS_SYNCMISS (0x00000010U)
AnnaBridge	156:ff21514d8981	833	#define RCC_CRS_TRIMOVF (0x00000020U)
AnnaBridge	156:ff21514d8981	834
AnnaBridge	156:ff21514d8981	835	/**
AnnaBridge	156:ff21514d8981	836	* @}
AnnaBridge	156:ff21514d8981	837	*/
AnnaBridge	156:ff21514d8981	838
AnnaBridge	156:ff21514d8981	839	/** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS Synchronization Source
AnnaBridge	156:ff21514d8981	840	* @{
AnnaBridge	156:ff21514d8981	841	*/
AnnaBridge	156:ff21514d8981	842	#define RCC_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00000000U) /!< Synchro Signal source GPIO /
AnnaBridge	156:ff21514d8981	843	#define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /!< Synchro Signal source LSE /
AnnaBridge	156:ff21514d8981	844	#define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /!< Synchro Signal source USB SOF (default)/
AnnaBridge	156:ff21514d8981	845	/**
AnnaBridge	156:ff21514d8981	846	* @}
AnnaBridge	156:ff21514d8981	847	*/
AnnaBridge	156:ff21514d8981	848
AnnaBridge	156:ff21514d8981	849	/** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS Synchronization Divider
AnnaBridge	156:ff21514d8981	850	* @{
AnnaBridge	156:ff21514d8981	851	*/
AnnaBridge	156:ff21514d8981	852	#define RCC_CRS_SYNC_DIV1 ((uint32_t)0x00000000U) /!< Synchro Signal not divided (default) /
AnnaBridge	156:ff21514d8981	853	#define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /!< Synchro Signal divided by 2 /
AnnaBridge	156:ff21514d8981	854	#define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /!< Synchro Signal divided by 4 /
AnnaBridge	156:ff21514d8981	855	#define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 \| CRS_CFGR_SYNCDIV_0) /!< Synchro Signal divided by 8 /
AnnaBridge	156:ff21514d8981	856	#define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /!< Synchro Signal divided by 16 /
AnnaBridge	156:ff21514d8981	857	#define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 \| CRS_CFGR_SYNCDIV_0) /!< Synchro Signal divided by 32 /
AnnaBridge	156:ff21514d8981	858	#define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 \| CRS_CFGR_SYNCDIV_1) /!< Synchro Signal divided by 64 /
AnnaBridge	156:ff21514d8981	859	#define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /!< Synchro Signal divided by 128 /
AnnaBridge	156:ff21514d8981	860	/**
AnnaBridge	156:ff21514d8981	861	* @}
AnnaBridge	156:ff21514d8981	862	*/
AnnaBridge	156:ff21514d8981	863
AnnaBridge	156:ff21514d8981	864	/** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS Synchronization Polarity
AnnaBridge	156:ff21514d8981	865	* @{
AnnaBridge	156:ff21514d8981	866	*/
AnnaBridge	156:ff21514d8981	867	#define RCC_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00000000U) /!< Synchro Active on rising edge (default) /
AnnaBridge	156:ff21514d8981	868	#define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /!< Synchro Active on falling edge /
AnnaBridge	156:ff21514d8981	869	/**
AnnaBridge	156:ff21514d8981	870	* @}
AnnaBridge	156:ff21514d8981	871	*/
AnnaBridge	156:ff21514d8981	872
AnnaBridge	156:ff21514d8981	873	/** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS Default Reload Value
AnnaBridge	156:ff21514d8981	874	* @{
AnnaBridge	156:ff21514d8981	875	*/
AnnaBridge	156:ff21514d8981	876	#define RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0x0000BB7FU) /*!< The reset value of the RELOAD field corresponds
AnnaBridge	156:ff21514d8981	877	to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
AnnaBridge	156:ff21514d8981	878	/**
AnnaBridge	156:ff21514d8981	879	* @}
AnnaBridge	156:ff21514d8981	880	*/
AnnaBridge	156:ff21514d8981	881
AnnaBridge	156:ff21514d8981	882	/** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS Default Error Limit Value
AnnaBridge	156:ff21514d8981	883	* @{
AnnaBridge	156:ff21514d8981	884	*/
AnnaBridge	156:ff21514d8981	885	#define RCC_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x00000022U) /!< Default Frequency error limit /
AnnaBridge	156:ff21514d8981	886	/**
AnnaBridge	156:ff21514d8981	887	* @}
AnnaBridge	156:ff21514d8981	888	*/
AnnaBridge	156:ff21514d8981	889
AnnaBridge	156:ff21514d8981	890	/** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS Default HSI48 Calibration vakye
AnnaBridge	156:ff21514d8981	891	* @{
AnnaBridge	156:ff21514d8981	892	*/
AnnaBridge	156:ff21514d8981	893	#define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x00000020U) /*!< The default value is 32, which corresponds to the middle of the trimming interval.
AnnaBridge	156:ff21514d8981	894	The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value
AnnaBridge	156:ff21514d8981	895	corresponds to a higher output frequency */
AnnaBridge	156:ff21514d8981	896	/**
AnnaBridge	156:ff21514d8981	897	* @}
AnnaBridge	156:ff21514d8981	898	*/
AnnaBridge	156:ff21514d8981	899
AnnaBridge	156:ff21514d8981	900	/** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS Frequency Error Direction
AnnaBridge	156:ff21514d8981	901	* @{
AnnaBridge	156:ff21514d8981	902	*/
AnnaBridge	156:ff21514d8981	903	#define RCC_CRS_FREQERRORDIR_UP ((uint32_t)0x00000000U) /!< Upcounting direction, the actual frequency is above the target /
AnnaBridge	156:ff21514d8981	904	#define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /!< Downcounting direction, the actual frequency is below the target /
AnnaBridge	156:ff21514d8981	905	/**
AnnaBridge	156:ff21514d8981	906	* @}
AnnaBridge	156:ff21514d8981	907	*/
AnnaBridge	156:ff21514d8981	908
AnnaBridge	156:ff21514d8981	909	/** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources
AnnaBridge	156:ff21514d8981	910	* @{
AnnaBridge	156:ff21514d8981	911	*/
AnnaBridge	156:ff21514d8981	912	#define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE /!< SYNC event OK /
AnnaBridge	156:ff21514d8981	913	#define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE /!< SYNC warning /
AnnaBridge	156:ff21514d8981	914	#define RCC_CRS_IT_ERR CRS_CR_ERRIE /!< Error /
AnnaBridge	156:ff21514d8981	915	#define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE /!< Expected SYNC /
AnnaBridge	156:ff21514d8981	916	#define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE /!< SYNC error /
AnnaBridge	156:ff21514d8981	917	#define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE /!< SYNC missed /
AnnaBridge	156:ff21514d8981	918	#define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE /!< Trimming overflow or underflow /
AnnaBridge	156:ff21514d8981	919
AnnaBridge	156:ff21514d8981	920	/**
AnnaBridge	156:ff21514d8981	921	* @}
AnnaBridge	156:ff21514d8981	922	*/
AnnaBridge	156:ff21514d8981	923
AnnaBridge	156:ff21514d8981	924	/** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags
AnnaBridge	156:ff21514d8981	925	* @{
AnnaBridge	156:ff21514d8981	926	*/
AnnaBridge	156:ff21514d8981	927	#define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /!< SYNC event OK flag /
AnnaBridge	156:ff21514d8981	928	#define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /!< SYNC warning flag /
AnnaBridge	156:ff21514d8981	929	#define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /!< Error flag /
AnnaBridge	156:ff21514d8981	930	#define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /!< Expected SYNC flag /
AnnaBridge	156:ff21514d8981	931	#define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /!< SYNC error /
AnnaBridge	156:ff21514d8981	932	#define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /!< SYNC missed/
AnnaBridge	156:ff21514d8981	933	#define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /!< Trimming overflow or underflow /
AnnaBridge	156:ff21514d8981	934
AnnaBridge	156:ff21514d8981	935	/**
AnnaBridge	156:ff21514d8981	936	* @}
AnnaBridge	156:ff21514d8981	937	*/
AnnaBridge	156:ff21514d8981	938
AnnaBridge	156:ff21514d8981	939	#endif /* CRS */
AnnaBridge	156:ff21514d8981	940
AnnaBridge	156:ff21514d8981	941	/**
AnnaBridge	156:ff21514d8981	942	* @}
AnnaBridge	156:ff21514d8981	943	*/
AnnaBridge	156:ff21514d8981	944
AnnaBridge	156:ff21514d8981	945	/* Exported macros ------------------------------------------------------------*/
AnnaBridge	156:ff21514d8981	946	/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
AnnaBridge	156:ff21514d8981	947	* @{
AnnaBridge	156:ff21514d8981	948	*/
AnnaBridge	156:ff21514d8981	949
AnnaBridge	156:ff21514d8981	950	/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable
AnnaBridge	156:ff21514d8981	951	* @brief Enables or disables the AHB1 peripheral clock.
AnnaBridge	156:ff21514d8981	952	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	953	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	954	* using it.
AnnaBridge	156:ff21514d8981	955	* @{
AnnaBridge	156:ff21514d8981	956	*/
AnnaBridge	156:ff21514d8981	957	#if defined(GPIOD)
AnnaBridge	156:ff21514d8981	958
AnnaBridge	156:ff21514d8981	959	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	960	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	961	SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
AnnaBridge	156:ff21514d8981	962	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	963	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
AnnaBridge	156:ff21514d8981	964	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	965	} while(0)
AnnaBridge	156:ff21514d8981	966
AnnaBridge	156:ff21514d8981	967	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN))
AnnaBridge	156:ff21514d8981	968
AnnaBridge	156:ff21514d8981	969	#endif /* GPIOD */
AnnaBridge	156:ff21514d8981	970
AnnaBridge	156:ff21514d8981	971	#if defined(GPIOE)
AnnaBridge	156:ff21514d8981	972
AnnaBridge	156:ff21514d8981	973	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	974	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	975	SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
AnnaBridge	156:ff21514d8981	976	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	977	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
AnnaBridge	156:ff21514d8981	978	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	979	} while(0)
AnnaBridge	156:ff21514d8981	980
AnnaBridge	156:ff21514d8981	981	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
AnnaBridge	156:ff21514d8981	982
AnnaBridge	156:ff21514d8981	983	#endif /* GPIOE */
AnnaBridge	156:ff21514d8981	984
AnnaBridge	156:ff21514d8981	985	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
AnnaBridge	156:ff21514d8981	986	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
AnnaBridge	156:ff21514d8981	987	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
AnnaBridge	156:ff21514d8981	988	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
AnnaBridge	156:ff21514d8981	989
AnnaBridge	156:ff21514d8981	990	#define __HAL_RCC_TSC_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	991	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	992	SET_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
AnnaBridge	156:ff21514d8981	993	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	994	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
AnnaBridge	156:ff21514d8981	995	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	996	} while(0)
AnnaBridge	156:ff21514d8981	997
AnnaBridge	156:ff21514d8981	998	#define __HAL_RCC_TSC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN))
AnnaBridge	156:ff21514d8981	999
AnnaBridge	156:ff21514d8981	1000	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
AnnaBridge	156:ff21514d8981	1001	/* STM32F051x8 \|\| STM32F058xx \|\| */
AnnaBridge	156:ff21514d8981	1002	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
AnnaBridge	156:ff21514d8981	1003	/* STM32F091xC \|\| STM32F098xx */
AnnaBridge	156:ff21514d8981	1004
AnnaBridge	156:ff21514d8981	1005	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
AnnaBridge	156:ff21514d8981	1006
AnnaBridge	156:ff21514d8981	1007	#define __HAL_RCC_DMA2_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1008	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	1009	SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
AnnaBridge	156:ff21514d8981	1010	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1011	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
AnnaBridge	156:ff21514d8981	1012	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1013	} while(0)
AnnaBridge	156:ff21514d8981	1014
AnnaBridge	156:ff21514d8981	1015	#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
AnnaBridge	156:ff21514d8981	1016
AnnaBridge	156:ff21514d8981	1017	#endif /* STM32F091xC \|\| STM32F098xx */
AnnaBridge	156:ff21514d8981	1018
AnnaBridge	156:ff21514d8981	1019	/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
AnnaBridge	156:ff21514d8981	1020	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	1021	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	1022	* using it.
AnnaBridge	156:ff21514d8981	1023	*/
AnnaBridge	156:ff21514d8981	1024	#if defined(STM32F030x8)\
AnnaBridge	156:ff21514d8981	1025	\|\| defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6)\
AnnaBridge	156:ff21514d8981	1026	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
AnnaBridge	156:ff21514d8981	1027	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
AnnaBridge	156:ff21514d8981	1028	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
AnnaBridge	156:ff21514d8981	1029
AnnaBridge	156:ff21514d8981	1030	#define __HAL_RCC_USART2_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1031	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	1032	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
AnnaBridge	156:ff21514d8981	1033	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1034	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
AnnaBridge	156:ff21514d8981	1035	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1036	} while(0)
AnnaBridge	156:ff21514d8981	1037
AnnaBridge	156:ff21514d8981	1038	#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
AnnaBridge	156:ff21514d8981	1039
AnnaBridge	156:ff21514d8981	1040	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| */
AnnaBridge	156:ff21514d8981	1041	/* STM32F051x8 \|\| STM32F058xx \|\| STM32F070x6 \|\| */
AnnaBridge	156:ff21514d8981	1042	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
AnnaBridge	156:ff21514d8981	1043	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
AnnaBridge	156:ff21514d8981	1044
AnnaBridge	156:ff21514d8981	1045	#if defined(STM32F030x8)\
AnnaBridge	156:ff21514d8981	1046	\|\| defined(STM32F042x6) \|\| defined(STM32F048xx)\
AnnaBridge	156:ff21514d8981	1047	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
AnnaBridge	156:ff21514d8981	1048	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
AnnaBridge	156:ff21514d8981	1049	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
AnnaBridge	156:ff21514d8981	1050
AnnaBridge	156:ff21514d8981	1051	#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1052	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	1053	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
AnnaBridge	156:ff21514d8981	1054	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1055	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
AnnaBridge	156:ff21514d8981	1056	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1057	} while(0)
AnnaBridge	156:ff21514d8981	1058
AnnaBridge	156:ff21514d8981	1059	#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
AnnaBridge	156:ff21514d8981	1060
AnnaBridge	156:ff21514d8981	1061	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| */
AnnaBridge	156:ff21514d8981	1062	/* STM32F051x8 \|\| STM32F058xx \|\| */
AnnaBridge	156:ff21514d8981	1063	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
AnnaBridge	156:ff21514d8981	1064	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
AnnaBridge	156:ff21514d8981	1065
AnnaBridge	156:ff21514d8981	1066	#if defined(STM32F031x6) \|\| defined(STM32F038xx)\
AnnaBridge	156:ff21514d8981	1067	\|\| defined(STM32F042x6) \|\| defined(STM32F048xx)\
AnnaBridge	156:ff21514d8981	1068	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
AnnaBridge	156:ff21514d8981	1069	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
AnnaBridge	156:ff21514d8981	1070	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
AnnaBridge	156:ff21514d8981	1071
AnnaBridge	156:ff21514d8981	1072	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1073	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	1074	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
AnnaBridge	156:ff21514d8981	1075	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1076	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
AnnaBridge	156:ff21514d8981	1077	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1078	} while(0)
AnnaBridge	156:ff21514d8981	1079
AnnaBridge	156:ff21514d8981	1080	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
AnnaBridge	156:ff21514d8981	1081
AnnaBridge	156:ff21514d8981	1082	#endif /* STM32F031x6 \|\| STM32F038xx \|\| */
AnnaBridge	156:ff21514d8981	1083	/* STM32F042x6 \|\| STM32F048xx \|\| */
AnnaBridge	156:ff21514d8981	1084	/* STM32F051x8 \|\| STM32F058xx \|\| */
AnnaBridge	156:ff21514d8981	1085	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
AnnaBridge	156:ff21514d8981	1086	/* STM32F091xC \|\| STM32F098xx */
AnnaBridge	156:ff21514d8981	1087
AnnaBridge	156:ff21514d8981	1088	#if defined(STM32F030x8) \
AnnaBridge	156:ff21514d8981	1089	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
AnnaBridge	156:ff21514d8981	1090	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
AnnaBridge	156:ff21514d8981	1091	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
AnnaBridge	156:ff21514d8981	1092
AnnaBridge	156:ff21514d8981	1093	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1094	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	1095	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
AnnaBridge	156:ff21514d8981	1096	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1097	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
AnnaBridge	156:ff21514d8981	1098	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1099	} while(0)
AnnaBridge	156:ff21514d8981	1100	#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1101	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	1102	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
AnnaBridge	156:ff21514d8981	1103	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1104	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
AnnaBridge	156:ff21514d8981	1105	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1106	} while(0)
AnnaBridge	156:ff21514d8981	1107
AnnaBridge	156:ff21514d8981	1108	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
AnnaBridge	156:ff21514d8981	1109	#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
AnnaBridge	156:ff21514d8981	1110
AnnaBridge	156:ff21514d8981	1111	#endif /* STM32F030x8 \|\| */
AnnaBridge	156:ff21514d8981	1112	/* STM32F051x8 \|\| STM32F058xx \|\| */
AnnaBridge	156:ff21514d8981	1113	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
AnnaBridge	156:ff21514d8981	1114	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
AnnaBridge	156:ff21514d8981	1115
AnnaBridge	156:ff21514d8981	1116	#if defined(STM32F051x8) \|\| defined(STM32F058xx)\
AnnaBridge	156:ff21514d8981	1117	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
AnnaBridge	156:ff21514d8981	1118	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
AnnaBridge	156:ff21514d8981	1119
AnnaBridge	156:ff21514d8981	1120	#define __HAL_RCC_DAC1_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1121	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	1122	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
AnnaBridge	156:ff21514d8981	1123	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1124	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
AnnaBridge	156:ff21514d8981	1125	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1126	} while(0)
AnnaBridge	156:ff21514d8981	1127
AnnaBridge	156:ff21514d8981	1128	#define __HAL_RCC_DAC1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
AnnaBridge	156:ff21514d8981	1129
AnnaBridge	156:ff21514d8981	1130	#endif /* STM32F051x8 \|\| STM32F058xx \|\| */
AnnaBridge	156:ff21514d8981	1131	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
AnnaBridge	156:ff21514d8981	1132	/* STM32F091xC \|\| STM32F098xx */
AnnaBridge	156:ff21514d8981	1133
AnnaBridge	156:ff21514d8981	1134	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
AnnaBridge	156:ff21514d8981	1135	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
AnnaBridge	156:ff21514d8981	1136	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
AnnaBridge	156:ff21514d8981	1137	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
AnnaBridge	156:ff21514d8981	1138
AnnaBridge	156:ff21514d8981	1139	#define __HAL_RCC_CEC_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1140	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	1141	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
AnnaBridge	156:ff21514d8981	1142	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1143	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
AnnaBridge	156:ff21514d8981	1144	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1145	} while(0)
AnnaBridge	156:ff21514d8981	1146
AnnaBridge	156:ff21514d8981	1147	#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
AnnaBridge	156:ff21514d8981	1148
AnnaBridge	156:ff21514d8981	1149	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
AnnaBridge	156:ff21514d8981	1150	/* STM32F051x8 \|\| STM32F058xx \|\| */
AnnaBridge	156:ff21514d8981	1151	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
AnnaBridge	156:ff21514d8981	1152	/* STM32F091xC \|\| STM32F098xx */
AnnaBridge	156:ff21514d8981	1153
AnnaBridge	156:ff21514d8981	1154	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
AnnaBridge	156:ff21514d8981	1155	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
AnnaBridge	156:ff21514d8981	1156
AnnaBridge	156:ff21514d8981	1157	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1158	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	1159	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
AnnaBridge	156:ff21514d8981	1160	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1161	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
AnnaBridge	156:ff21514d8981	1162	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1163	} while(0)
AnnaBridge	156:ff21514d8981	1164	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1165	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	1166	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
AnnaBridge	156:ff21514d8981	1167	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1168	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
AnnaBridge	156:ff21514d8981	1169	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1170	} while(0)
AnnaBridge	156:ff21514d8981	1171	#define __HAL_RCC_USART4_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1172	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	1173	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART4EN);\
AnnaBridge	156:ff21514d8981	1174	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1175	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART4EN);\
AnnaBridge	156:ff21514d8981	1176	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1177	} while(0)
AnnaBridge	156:ff21514d8981	1178
AnnaBridge	156:ff21514d8981	1179	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
AnnaBridge	156:ff21514d8981	1180	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
AnnaBridge	156:ff21514d8981	1181	#define __HAL_RCC_USART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART4EN))
AnnaBridge	156:ff21514d8981	1182
AnnaBridge	156:ff21514d8981	1183	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
AnnaBridge	156:ff21514d8981	1184	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
AnnaBridge	156:ff21514d8981	1185
AnnaBridge	156:ff21514d8981	1186	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6)\
AnnaBridge	156:ff21514d8981	1187	\|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)
AnnaBridge	156:ff21514d8981	1188
AnnaBridge	156:ff21514d8981	1189	#define __HAL_RCC_USB_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1190	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	1191	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
AnnaBridge	156:ff21514d8981	1192	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1193	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
AnnaBridge	156:ff21514d8981	1194	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1195	} while(0)
AnnaBridge	156:ff21514d8981	1196
AnnaBridge	156:ff21514d8981	1197	#define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
AnnaBridge	156:ff21514d8981	1198
AnnaBridge	156:ff21514d8981	1199	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F070x6 \|\| */
AnnaBridge	156:ff21514d8981	1200	/* STM32F072xB \|\| STM32F078xx \|\| STM32F070xB */
AnnaBridge	156:ff21514d8981	1201
AnnaBridge	156:ff21514d8981	1202	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F072xB)\
AnnaBridge	156:ff21514d8981	1203	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
AnnaBridge	156:ff21514d8981	1204
AnnaBridge	156:ff21514d8981	1205	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1206	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	1207	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\
AnnaBridge	156:ff21514d8981	1208	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1209	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\
AnnaBridge	156:ff21514d8981	1210	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1211	} while(0)
AnnaBridge	156:ff21514d8981	1212	#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CANEN))
AnnaBridge	156:ff21514d8981	1213
AnnaBridge	156:ff21514d8981	1214	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F072xB \|\| */
AnnaBridge	156:ff21514d8981	1215	/* STM32F091xC \|\| STM32F098xx */
AnnaBridge	156:ff21514d8981	1216
AnnaBridge	156:ff21514d8981	1217	#if defined(CRS)
AnnaBridge	156:ff21514d8981	1218
AnnaBridge	156:ff21514d8981	1219	#define __HAL_RCC_CRS_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1220	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	1221	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CRSEN);\
AnnaBridge	156:ff21514d8981	1222	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1223	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CRSEN);\
AnnaBridge	156:ff21514d8981	1224	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1225	} while(0)
AnnaBridge	156:ff21514d8981	1226
AnnaBridge	156:ff21514d8981	1227	#define __HAL_RCC_CRS_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CRSEN))
AnnaBridge	156:ff21514d8981	1228
AnnaBridge	156:ff21514d8981	1229	#endif /* CRS */
AnnaBridge	156:ff21514d8981	1230
AnnaBridge	156:ff21514d8981	1231	#if defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
AnnaBridge	156:ff21514d8981	1232
AnnaBridge	156:ff21514d8981	1233	#define __HAL_RCC_USART5_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1234	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	1235	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART5EN);\
AnnaBridge	156:ff21514d8981	1236	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1237	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART5EN);\
AnnaBridge	156:ff21514d8981	1238	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1239	} while(0)
AnnaBridge	156:ff21514d8981	1240
AnnaBridge	156:ff21514d8981	1241	#define __HAL_RCC_USART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART5EN))
AnnaBridge	156:ff21514d8981	1242
AnnaBridge	156:ff21514d8981	1243	#endif /* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
AnnaBridge	156:ff21514d8981	1244
AnnaBridge	156:ff21514d8981	1245	/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
AnnaBridge	156:ff21514d8981	1246	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	1247	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	1248	* using it.
AnnaBridge	156:ff21514d8981	1249	*/
AnnaBridge	156:ff21514d8981	1250	#if defined(STM32F030x8) \|\| defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6)\
AnnaBridge	156:ff21514d8981	1251	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
AnnaBridge	156:ff21514d8981	1252	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
AnnaBridge	156:ff21514d8981	1253	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
AnnaBridge	156:ff21514d8981	1254
AnnaBridge	156:ff21514d8981	1255	#define __HAL_RCC_TIM15_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1256	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	1257	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
AnnaBridge	156:ff21514d8981	1258	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1259	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
AnnaBridge	156:ff21514d8981	1260	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1261	} while(0)
AnnaBridge	156:ff21514d8981	1262
AnnaBridge	156:ff21514d8981	1263	#define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN))
AnnaBridge	156:ff21514d8981	1264
AnnaBridge	156:ff21514d8981	1265	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| STM32F070x6 \|\| */
AnnaBridge	156:ff21514d8981	1266	/* STM32F051x8 \|\| STM32F058xx \|\| */
AnnaBridge	156:ff21514d8981	1267	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
AnnaBridge	156:ff21514d8981	1268	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
AnnaBridge	156:ff21514d8981	1269
AnnaBridge	156:ff21514d8981	1270	#if defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
AnnaBridge	156:ff21514d8981	1271
AnnaBridge	156:ff21514d8981	1272	#define __HAL_RCC_USART6_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1273	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	1274	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
AnnaBridge	156:ff21514d8981	1275	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1276	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
AnnaBridge	156:ff21514d8981	1277	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1278	} while(0)
AnnaBridge	156:ff21514d8981	1279
AnnaBridge	156:ff21514d8981	1280	#define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
AnnaBridge	156:ff21514d8981	1281
AnnaBridge	156:ff21514d8981	1282	#endif /* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
AnnaBridge	156:ff21514d8981	1283
AnnaBridge	156:ff21514d8981	1284	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
AnnaBridge	156:ff21514d8981	1285
AnnaBridge	156:ff21514d8981	1286	#define __HAL_RCC_USART7_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1287	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	1288	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART7EN);\
AnnaBridge	156:ff21514d8981	1289	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1290	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART7EN);\
AnnaBridge	156:ff21514d8981	1291	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1292	} while(0)
AnnaBridge	156:ff21514d8981	1293	#define __HAL_RCC_USART8_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1294	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	1295	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART8EN);\
AnnaBridge	156:ff21514d8981	1296	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1297	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART8EN);\
AnnaBridge	156:ff21514d8981	1298	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1299	} while(0)
AnnaBridge	156:ff21514d8981	1300
AnnaBridge	156:ff21514d8981	1301	#define __HAL_RCC_USART7_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART7EN))
AnnaBridge	156:ff21514d8981	1302	#define __HAL_RCC_USART8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART8EN))
AnnaBridge	156:ff21514d8981	1303
AnnaBridge	156:ff21514d8981	1304	#endif /* STM32F091xC \|\| STM32F098xx */
AnnaBridge	156:ff21514d8981	1305
AnnaBridge	156:ff21514d8981	1306	/**
AnnaBridge	156:ff21514d8981	1307	* @}
AnnaBridge	156:ff21514d8981	1308	*/
AnnaBridge	156:ff21514d8981	1309
AnnaBridge	156:ff21514d8981	1310
AnnaBridge	156:ff21514d8981	1311	/** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset
AnnaBridge	156:ff21514d8981	1312	* @brief Forces or releases peripheral reset.
AnnaBridge	156:ff21514d8981	1313	* @{
AnnaBridge	156:ff21514d8981	1314	*/
AnnaBridge	156:ff21514d8981	1315
AnnaBridge	156:ff21514d8981	1316	/** @brief Force or release AHB peripheral reset.
AnnaBridge	156:ff21514d8981	1317	*/
AnnaBridge	156:ff21514d8981	1318	#if defined(GPIOD)
AnnaBridge	156:ff21514d8981	1319
AnnaBridge	156:ff21514d8981	1320	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIODRST))
AnnaBridge	156:ff21514d8981	1321
AnnaBridge	156:ff21514d8981	1322	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST))
AnnaBridge	156:ff21514d8981	1323
AnnaBridge	156:ff21514d8981	1324	#endif /* GPIOD */
AnnaBridge	156:ff21514d8981	1325
AnnaBridge	156:ff21514d8981	1326	#if defined(GPIOE)
AnnaBridge	156:ff21514d8981	1327
AnnaBridge	156:ff21514d8981	1328	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOERST))
AnnaBridge	156:ff21514d8981	1329
AnnaBridge	156:ff21514d8981	1330	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))
AnnaBridge	156:ff21514d8981	1331
AnnaBridge	156:ff21514d8981	1332	#endif /* GPIOE */
AnnaBridge	156:ff21514d8981	1333
AnnaBridge	156:ff21514d8981	1334	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
AnnaBridge	156:ff21514d8981	1335	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
AnnaBridge	156:ff21514d8981	1336	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
AnnaBridge	156:ff21514d8981	1337	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
AnnaBridge	156:ff21514d8981	1338
AnnaBridge	156:ff21514d8981	1339	#define __HAL_RCC_TSC_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_TSCRST))
AnnaBridge	156:ff21514d8981	1340
AnnaBridge	156:ff21514d8981	1341	#define __HAL_RCC_TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_TSCRST))
AnnaBridge	156:ff21514d8981	1342
AnnaBridge	156:ff21514d8981	1343	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
AnnaBridge	156:ff21514d8981	1344	/* STM32F051x8 \|\| STM32F058xx \|\| */
AnnaBridge	156:ff21514d8981	1345	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
AnnaBridge	156:ff21514d8981	1346	/* STM32F091xC \|\| STM32F098xx */
AnnaBridge	156:ff21514d8981	1347
AnnaBridge	156:ff21514d8981	1348	/** @brief Force or release APB1 peripheral reset.
AnnaBridge	156:ff21514d8981	1349	*/
AnnaBridge	156:ff21514d8981	1350	#if defined(STM32F030x8) \
AnnaBridge	156:ff21514d8981	1351	\|\| defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6)\
AnnaBridge	156:ff21514d8981	1352	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
AnnaBridge	156:ff21514d8981	1353	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
AnnaBridge	156:ff21514d8981	1354	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
AnnaBridge	156:ff21514d8981	1355
AnnaBridge	156:ff21514d8981	1356	#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART2RST))
AnnaBridge	156:ff21514d8981	1357	#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI2RST))
AnnaBridge	156:ff21514d8981	1358
AnnaBridge	156:ff21514d8981	1359	#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
AnnaBridge	156:ff21514d8981	1360	#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
AnnaBridge	156:ff21514d8981	1361
AnnaBridge	156:ff21514d8981	1362	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| STM32F070x6 \|\| */
AnnaBridge	156:ff21514d8981	1363	/* STM32F051x8 \|\| STM32F058xx \|\| */
AnnaBridge	156:ff21514d8981	1364	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
AnnaBridge	156:ff21514d8981	1365	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
AnnaBridge	156:ff21514d8981	1366
AnnaBridge	156:ff21514d8981	1367	#if defined(STM32F031x6) \|\| defined(STM32F038xx)\
AnnaBridge	156:ff21514d8981	1368	\|\| defined(STM32F042x6) \|\| defined(STM32F048xx)\
AnnaBridge	156:ff21514d8981	1369	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
AnnaBridge	156:ff21514d8981	1370	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
AnnaBridge	156:ff21514d8981	1371	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
AnnaBridge	156:ff21514d8981	1372
AnnaBridge	156:ff21514d8981	1373	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
AnnaBridge	156:ff21514d8981	1374
AnnaBridge	156:ff21514d8981	1375	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
AnnaBridge	156:ff21514d8981	1376
AnnaBridge	156:ff21514d8981	1377	#endif /* STM32F031x6 \|\| STM32F038xx \|\| */
AnnaBridge	156:ff21514d8981	1378	/* STM32F042x6 \|\| STM32F048xx \|\| */
AnnaBridge	156:ff21514d8981	1379	/* STM32F051x8 \|\| STM32F058xx \|\| */
AnnaBridge	156:ff21514d8981	1380	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
AnnaBridge	156:ff21514d8981	1381	/* STM32F091xC \|\| STM32F098xx */
AnnaBridge	156:ff21514d8981	1382
AnnaBridge	156:ff21514d8981	1383	#if defined(STM32F030x8) \
AnnaBridge	156:ff21514d8981	1384	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
AnnaBridge	156:ff21514d8981	1385	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
AnnaBridge	156:ff21514d8981	1386	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
AnnaBridge	156:ff21514d8981	1387
AnnaBridge	156:ff21514d8981	1388	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
AnnaBridge	156:ff21514d8981	1389	#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C2RST))
AnnaBridge	156:ff21514d8981	1390
AnnaBridge	156:ff21514d8981	1391	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
AnnaBridge	156:ff21514d8981	1392	#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
AnnaBridge	156:ff21514d8981	1393
AnnaBridge	156:ff21514d8981	1394	#endif /* STM32F030x8 \|\| */
AnnaBridge	156:ff21514d8981	1395	/* STM32F051x8 \|\| STM32F058xx \|\| */
AnnaBridge	156:ff21514d8981	1396	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
AnnaBridge	156:ff21514d8981	1397	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
AnnaBridge	156:ff21514d8981	1398
AnnaBridge	156:ff21514d8981	1399	#if defined(STM32F051x8) \|\| defined(STM32F058xx)\
AnnaBridge	156:ff21514d8981	1400	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
AnnaBridge	156:ff21514d8981	1401	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
AnnaBridge	156:ff21514d8981	1402
AnnaBridge	156:ff21514d8981	1403	#define __HAL_RCC_DAC1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
AnnaBridge	156:ff21514d8981	1404
AnnaBridge	156:ff21514d8981	1405	#define __HAL_RCC_DAC1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
AnnaBridge	156:ff21514d8981	1406
AnnaBridge	156:ff21514d8981	1407	#endif /* STM32F051x8 \|\| STM32F058xx \|\| */
AnnaBridge	156:ff21514d8981	1408	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
AnnaBridge	156:ff21514d8981	1409	/* STM32F091xC \|\| STM32F098xx */
AnnaBridge	156:ff21514d8981	1410
AnnaBridge	156:ff21514d8981	1411	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
AnnaBridge	156:ff21514d8981	1412	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
AnnaBridge	156:ff21514d8981	1413	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
AnnaBridge	156:ff21514d8981	1414	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
AnnaBridge	156:ff21514d8981	1415
AnnaBridge	156:ff21514d8981	1416	#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CECRST))
AnnaBridge	156:ff21514d8981	1417
AnnaBridge	156:ff21514d8981	1418	#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
AnnaBridge	156:ff21514d8981	1419
AnnaBridge	156:ff21514d8981	1420	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
AnnaBridge	156:ff21514d8981	1421	/* STM32F051x8 \|\| STM32F058xx \|\| */
AnnaBridge	156:ff21514d8981	1422	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
AnnaBridge	156:ff21514d8981	1423	/* STM32F091xC \|\| STM32F098xx */
AnnaBridge	156:ff21514d8981	1424
AnnaBridge	156:ff21514d8981	1425	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
AnnaBridge	156:ff21514d8981	1426	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
AnnaBridge	156:ff21514d8981	1427
AnnaBridge	156:ff21514d8981	1428	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
AnnaBridge	156:ff21514d8981	1429	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
AnnaBridge	156:ff21514d8981	1430	#define __HAL_RCC_USART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART4RST))
AnnaBridge	156:ff21514d8981	1431
AnnaBridge	156:ff21514d8981	1432	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
AnnaBridge	156:ff21514d8981	1433	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
AnnaBridge	156:ff21514d8981	1434	#define __HAL_RCC_USART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART4RST))
AnnaBridge	156:ff21514d8981	1435
AnnaBridge	156:ff21514d8981	1436	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
AnnaBridge	156:ff21514d8981	1437	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
AnnaBridge	156:ff21514d8981	1438
AnnaBridge	156:ff21514d8981	1439	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6)\
AnnaBridge	156:ff21514d8981	1440	\|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)
AnnaBridge	156:ff21514d8981	1441
AnnaBridge	156:ff21514d8981	1442	#define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USBRST))
AnnaBridge	156:ff21514d8981	1443
AnnaBridge	156:ff21514d8981	1444	#define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
AnnaBridge	156:ff21514d8981	1445
AnnaBridge	156:ff21514d8981	1446	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F070x6 \|\| */
AnnaBridge	156:ff21514d8981	1447	/* STM32F072xB \|\| STM32F078xx \|\| STM32F070xB */
AnnaBridge	156:ff21514d8981	1448
AnnaBridge	156:ff21514d8981	1449	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F072xB)\
AnnaBridge	156:ff21514d8981	1450	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
AnnaBridge	156:ff21514d8981	1451
AnnaBridge	156:ff21514d8981	1452	#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CANRST))
AnnaBridge	156:ff21514d8981	1453
AnnaBridge	156:ff21514d8981	1454	#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CANRST))
AnnaBridge	156:ff21514d8981	1455
AnnaBridge	156:ff21514d8981	1456	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F072xB \|\| */
AnnaBridge	156:ff21514d8981	1457	/* STM32F091xC \|\| STM32F098xx */
AnnaBridge	156:ff21514d8981	1458
AnnaBridge	156:ff21514d8981	1459	#if defined(CRS)
AnnaBridge	156:ff21514d8981	1460
AnnaBridge	156:ff21514d8981	1461	#define __HAL_RCC_CRS_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CRSRST))
AnnaBridge	156:ff21514d8981	1462
AnnaBridge	156:ff21514d8981	1463	#define __HAL_RCC_CRS_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CRSRST))
AnnaBridge	156:ff21514d8981	1464
AnnaBridge	156:ff21514d8981	1465	#endif /* CRS */
AnnaBridge	156:ff21514d8981	1466
AnnaBridge	156:ff21514d8981	1467	#if defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
AnnaBridge	156:ff21514d8981	1468
AnnaBridge	156:ff21514d8981	1469	#define __HAL_RCC_USART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART5RST))
AnnaBridge	156:ff21514d8981	1470
AnnaBridge	156:ff21514d8981	1471	#define __HAL_RCC_USART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART5RST))
AnnaBridge	156:ff21514d8981	1472
AnnaBridge	156:ff21514d8981	1473	#endif /* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
AnnaBridge	156:ff21514d8981	1474
AnnaBridge	156:ff21514d8981	1475
AnnaBridge	156:ff21514d8981	1476	/** @brief Force or release APB2 peripheral reset.
AnnaBridge	156:ff21514d8981	1477	*/
AnnaBridge	156:ff21514d8981	1478	#if defined(STM32F030x8) \|\| defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6)\
AnnaBridge	156:ff21514d8981	1479	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
AnnaBridge	156:ff21514d8981	1480	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
AnnaBridge	156:ff21514d8981	1481	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
AnnaBridge	156:ff21514d8981	1482
AnnaBridge	156:ff21514d8981	1483	#define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM15RST))
AnnaBridge	156:ff21514d8981	1484
AnnaBridge	156:ff21514d8981	1485	#define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST))
AnnaBridge	156:ff21514d8981	1486
AnnaBridge	156:ff21514d8981	1487	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| STM32F070x6 \|\| */
AnnaBridge	156:ff21514d8981	1488	/* STM32F051x8 \|\| STM32F058xx \|\| */
AnnaBridge	156:ff21514d8981	1489	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
AnnaBridge	156:ff21514d8981	1490	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
AnnaBridge	156:ff21514d8981	1491
AnnaBridge	156:ff21514d8981	1492	#if defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
AnnaBridge	156:ff21514d8981	1493
AnnaBridge	156:ff21514d8981	1494	#define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART6RST))
AnnaBridge	156:ff21514d8981	1495
AnnaBridge	156:ff21514d8981	1496	#define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
AnnaBridge	156:ff21514d8981	1497
AnnaBridge	156:ff21514d8981	1498	#endif /* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
AnnaBridge	156:ff21514d8981	1499
AnnaBridge	156:ff21514d8981	1500	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
AnnaBridge	156:ff21514d8981	1501
AnnaBridge	156:ff21514d8981	1502	#define __HAL_RCC_USART7_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART7RST))
AnnaBridge	156:ff21514d8981	1503	#define __HAL_RCC_USART8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART8RST))
AnnaBridge	156:ff21514d8981	1504
AnnaBridge	156:ff21514d8981	1505	#define __HAL_RCC_USART7_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART7RST))
AnnaBridge	156:ff21514d8981	1506	#define __HAL_RCC_USART8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART8RST))
AnnaBridge	156:ff21514d8981	1507
AnnaBridge	156:ff21514d8981	1508	#endif /* STM32F091xC \|\| STM32F098xx */
AnnaBridge	156:ff21514d8981	1509
AnnaBridge	156:ff21514d8981	1510	/**
AnnaBridge	156:ff21514d8981	1511	* @}
AnnaBridge	156:ff21514d8981	1512	*/
AnnaBridge	156:ff21514d8981	1513
AnnaBridge	156:ff21514d8981	1514	/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable_Status Peripheral Clock Enable Disable Status
AnnaBridge	156:ff21514d8981	1515	* @brief Get the enable or disable status of peripheral clock.
AnnaBridge	156:ff21514d8981	1516	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	1517	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	1518	* using it.
AnnaBridge	156:ff21514d8981	1519	* @{
AnnaBridge	156:ff21514d8981	1520	*/
AnnaBridge	156:ff21514d8981	1521	/** @brief AHB Peripheral Clock Enable Disable Status
AnnaBridge	156:ff21514d8981	1522	*/
AnnaBridge	156:ff21514d8981	1523	#if defined(GPIOD)
AnnaBridge	156:ff21514d8981	1524
AnnaBridge	156:ff21514d8981	1525	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) != RESET)
AnnaBridge	156:ff21514d8981	1526	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) == RESET)
AnnaBridge	156:ff21514d8981	1527
AnnaBridge	156:ff21514d8981	1528	#endif /* GPIOD */
AnnaBridge	156:ff21514d8981	1529
AnnaBridge	156:ff21514d8981	1530	#if defined(GPIOE)
AnnaBridge	156:ff21514d8981	1531
AnnaBridge	156:ff21514d8981	1532	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) != RESET)
AnnaBridge	156:ff21514d8981	1533	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) == RESET)
AnnaBridge	156:ff21514d8981	1534
AnnaBridge	156:ff21514d8981	1535	#endif /* GPIOE */
AnnaBridge	156:ff21514d8981	1536
AnnaBridge	156:ff21514d8981	1537	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
AnnaBridge	156:ff21514d8981	1538	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
AnnaBridge	156:ff21514d8981	1539	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
AnnaBridge	156:ff21514d8981	1540	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
AnnaBridge	156:ff21514d8981	1541
AnnaBridge	156:ff21514d8981	1542	#define __HAL_RCC_TSC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) != RESET)
AnnaBridge	156:ff21514d8981	1543	#define __HAL_RCC_TSC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) == RESET)
AnnaBridge	156:ff21514d8981	1544
AnnaBridge	156:ff21514d8981	1545	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
AnnaBridge	156:ff21514d8981	1546	/* STM32F051x8 \|\| STM32F058xx \|\| */
AnnaBridge	156:ff21514d8981	1547	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
AnnaBridge	156:ff21514d8981	1548	/* STM32F091xC \|\| STM32F098xx */
AnnaBridge	156:ff21514d8981	1549
AnnaBridge	156:ff21514d8981	1550	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
AnnaBridge	156:ff21514d8981	1551
AnnaBridge	156:ff21514d8981	1552	#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET)
AnnaBridge	156:ff21514d8981	1553	#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET)
AnnaBridge	156:ff21514d8981	1554
AnnaBridge	156:ff21514d8981	1555	#endif /* STM32F091xC \|\| STM32F098xx */
AnnaBridge	156:ff21514d8981	1556
AnnaBridge	156:ff21514d8981	1557	/** @brief APB1 Peripheral Clock Enable Disable Status
AnnaBridge	156:ff21514d8981	1558	*/
AnnaBridge	156:ff21514d8981	1559	#if defined(STM32F030x8)\
AnnaBridge	156:ff21514d8981	1560	\|\| defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6)\
AnnaBridge	156:ff21514d8981	1561	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
AnnaBridge	156:ff21514d8981	1562	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
AnnaBridge	156:ff21514d8981	1563	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
AnnaBridge	156:ff21514d8981	1564
AnnaBridge	156:ff21514d8981	1565	#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
AnnaBridge	156:ff21514d8981	1566	#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
AnnaBridge	156:ff21514d8981	1567
AnnaBridge	156:ff21514d8981	1568	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| */
AnnaBridge	156:ff21514d8981	1569	/* STM32F051x8 \|\| STM32F058xx \|\| STM32F070x6 \|\| */
AnnaBridge	156:ff21514d8981	1570	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
AnnaBridge	156:ff21514d8981	1571	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
AnnaBridge	156:ff21514d8981	1572
AnnaBridge	156:ff21514d8981	1573	#if defined(STM32F030x8)\
AnnaBridge	156:ff21514d8981	1574	\|\| defined(STM32F042x6) \|\| defined(STM32F048xx)\
AnnaBridge	156:ff21514d8981	1575	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
AnnaBridge	156:ff21514d8981	1576	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
AnnaBridge	156:ff21514d8981	1577	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
AnnaBridge	156:ff21514d8981	1578
AnnaBridge	156:ff21514d8981	1579	#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
AnnaBridge	156:ff21514d8981	1580	#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
AnnaBridge	156:ff21514d8981	1581
AnnaBridge	156:ff21514d8981	1582	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| */
AnnaBridge	156:ff21514d8981	1583	/* STM32F051x8 \|\| STM32F058xx \|\| */
AnnaBridge	156:ff21514d8981	1584	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
AnnaBridge	156:ff21514d8981	1585	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
AnnaBridge	156:ff21514d8981	1586
AnnaBridge	156:ff21514d8981	1587	#if defined(STM32F031x6) \|\| defined(STM32F038xx)\
AnnaBridge	156:ff21514d8981	1588	\|\| defined(STM32F042x6) \|\| defined(STM32F048xx)\
AnnaBridge	156:ff21514d8981	1589	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
AnnaBridge	156:ff21514d8981	1590	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
AnnaBridge	156:ff21514d8981	1591	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
AnnaBridge	156:ff21514d8981	1592
AnnaBridge	156:ff21514d8981	1593	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
AnnaBridge	156:ff21514d8981	1594	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
AnnaBridge	156:ff21514d8981	1595
AnnaBridge	156:ff21514d8981	1596	#endif /* STM32F031x6 \|\| STM32F038xx \|\| */
AnnaBridge	156:ff21514d8981	1597	/* STM32F042x6 \|\| STM32F048xx \|\| */
AnnaBridge	156:ff21514d8981	1598	/* STM32F051x8 \|\| STM32F058xx \|\| */
AnnaBridge	156:ff21514d8981	1599	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
AnnaBridge	156:ff21514d8981	1600	/* STM32F091xC \|\| STM32F098xx */
AnnaBridge	156:ff21514d8981	1601
AnnaBridge	156:ff21514d8981	1602	#if defined(STM32F030x8) \
AnnaBridge	156:ff21514d8981	1603	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
AnnaBridge	156:ff21514d8981	1604	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
AnnaBridge	156:ff21514d8981	1605	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
AnnaBridge	156:ff21514d8981	1606
AnnaBridge	156:ff21514d8981	1607	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
AnnaBridge	156:ff21514d8981	1608	#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
AnnaBridge	156:ff21514d8981	1609	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
AnnaBridge	156:ff21514d8981	1610	#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
AnnaBridge	156:ff21514d8981	1611
AnnaBridge	156:ff21514d8981	1612	#endif /* STM32F030x8 \|\| */
AnnaBridge	156:ff21514d8981	1613	/* STM32F051x8 \|\| STM32F058xx \|\| */
AnnaBridge	156:ff21514d8981	1614	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
AnnaBridge	156:ff21514d8981	1615	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
AnnaBridge	156:ff21514d8981	1616
AnnaBridge	156:ff21514d8981	1617	#if defined(STM32F051x8) \|\| defined(STM32F058xx)\
AnnaBridge	156:ff21514d8981	1618	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
AnnaBridge	156:ff21514d8981	1619	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
AnnaBridge	156:ff21514d8981	1620
AnnaBridge	156:ff21514d8981	1621	#define __HAL_RCC_DAC1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) != RESET)
AnnaBridge	156:ff21514d8981	1622	#define __HAL_RCC_DAC1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) == RESET)
AnnaBridge	156:ff21514d8981	1623
AnnaBridge	156:ff21514d8981	1624	#endif /* STM32F051x8 \|\| STM32F058xx \|\| */
AnnaBridge	156:ff21514d8981	1625	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
AnnaBridge	156:ff21514d8981	1626	/* STM32F091xC \|\| STM32F098xx */
AnnaBridge	156:ff21514d8981	1627
AnnaBridge	156:ff21514d8981	1628	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
AnnaBridge	156:ff21514d8981	1629	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
AnnaBridge	156:ff21514d8981	1630	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
AnnaBridge	156:ff21514d8981	1631	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
AnnaBridge	156:ff21514d8981	1632
AnnaBridge	156:ff21514d8981	1633	#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
AnnaBridge	156:ff21514d8981	1634	#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
AnnaBridge	156:ff21514d8981	1635
AnnaBridge	156:ff21514d8981	1636	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
AnnaBridge	156:ff21514d8981	1637	/* STM32F051x8 \|\| STM32F058xx \|\| */
AnnaBridge	156:ff21514d8981	1638	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
AnnaBridge	156:ff21514d8981	1639	/* STM32F091xC \|\| STM32F098xx */
AnnaBridge	156:ff21514d8981	1640
AnnaBridge	156:ff21514d8981	1641	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
AnnaBridge	156:ff21514d8981	1642	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
AnnaBridge	156:ff21514d8981	1643
AnnaBridge	156:ff21514d8981	1644	#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
AnnaBridge	156:ff21514d8981	1645	#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
AnnaBridge	156:ff21514d8981	1646	#define __HAL_RCC_USART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART4EN)) != RESET)
AnnaBridge	156:ff21514d8981	1647	#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
AnnaBridge	156:ff21514d8981	1648	#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
AnnaBridge	156:ff21514d8981	1649	#define __HAL_RCC_USART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART4EN)) == RESET)
AnnaBridge	156:ff21514d8981	1650
AnnaBridge	156:ff21514d8981	1651	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
AnnaBridge	156:ff21514d8981	1652	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
AnnaBridge	156:ff21514d8981	1653
AnnaBridge	156:ff21514d8981	1654	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6)\
AnnaBridge	156:ff21514d8981	1655	\|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)
AnnaBridge	156:ff21514d8981	1656
AnnaBridge	156:ff21514d8981	1657	#define __HAL_RCC_USB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET)
AnnaBridge	156:ff21514d8981	1658	#define __HAL_RCC_USB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET)
AnnaBridge	156:ff21514d8981	1659
AnnaBridge	156:ff21514d8981	1660	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F070x6 \|\| */
AnnaBridge	156:ff21514d8981	1661	/* STM32F072xB \|\| STM32F078xx \|\| STM32F070xB */
AnnaBridge	156:ff21514d8981	1662
AnnaBridge	156:ff21514d8981	1663	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F072xB)\
AnnaBridge	156:ff21514d8981	1664	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
AnnaBridge	156:ff21514d8981	1665
AnnaBridge	156:ff21514d8981	1666	#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
AnnaBridge	156:ff21514d8981	1667	#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
AnnaBridge	156:ff21514d8981	1668
AnnaBridge	156:ff21514d8981	1669	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F072xB \|\| */
AnnaBridge	156:ff21514d8981	1670	/* STM32F091xC \|\| STM32F098xx */
AnnaBridge	156:ff21514d8981	1671
AnnaBridge	156:ff21514d8981	1672	#if defined(CRS)
AnnaBridge	156:ff21514d8981	1673
AnnaBridge	156:ff21514d8981	1674	#define __HAL_RCC_CRS_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CRSEN)) != RESET)
AnnaBridge	156:ff21514d8981	1675	#define __HAL_RCC_CRS_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CRSEN)) == RESET)
AnnaBridge	156:ff21514d8981	1676
AnnaBridge	156:ff21514d8981	1677	#endif /* CRS */
AnnaBridge	156:ff21514d8981	1678
AnnaBridge	156:ff21514d8981	1679	#if defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
AnnaBridge	156:ff21514d8981	1680
AnnaBridge	156:ff21514d8981	1681	#define __HAL_RCC_USART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART5EN)) != RESET)
AnnaBridge	156:ff21514d8981	1682	#define __HAL_RCC_USART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART5EN)) == RESET)
AnnaBridge	156:ff21514d8981	1683
AnnaBridge	156:ff21514d8981	1684	#endif /* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
AnnaBridge	156:ff21514d8981	1685
AnnaBridge	156:ff21514d8981	1686	/** @brief APB1 Peripheral Clock Enable Disable Status
AnnaBridge	156:ff21514d8981	1687	*/
AnnaBridge	156:ff21514d8981	1688	#if defined(STM32F030x8) \|\| defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6)\
AnnaBridge	156:ff21514d8981	1689	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
AnnaBridge	156:ff21514d8981	1690	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
AnnaBridge	156:ff21514d8981	1691	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
AnnaBridge	156:ff21514d8981	1692
AnnaBridge	156:ff21514d8981	1693	#define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) != RESET)
AnnaBridge	156:ff21514d8981	1694	#define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) == RESET)
AnnaBridge	156:ff21514d8981	1695
AnnaBridge	156:ff21514d8981	1696	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| STM32F070x6 \|\| */
AnnaBridge	156:ff21514d8981	1697	/* STM32F051x8 \|\| STM32F058xx \|\| */
AnnaBridge	156:ff21514d8981	1698	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
AnnaBridge	156:ff21514d8981	1699	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
AnnaBridge	156:ff21514d8981	1700
AnnaBridge	156:ff21514d8981	1701	#if defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
AnnaBridge	156:ff21514d8981	1702
AnnaBridge	156:ff21514d8981	1703	#define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET)
AnnaBridge	156:ff21514d8981	1704	#define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET)
AnnaBridge	156:ff21514d8981	1705
AnnaBridge	156:ff21514d8981	1706	#endif /* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
AnnaBridge	156:ff21514d8981	1707
AnnaBridge	156:ff21514d8981	1708	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
AnnaBridge	156:ff21514d8981	1709
AnnaBridge	156:ff21514d8981	1710	#define __HAL_RCC_USART7_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART7EN)) != RESET)
AnnaBridge	156:ff21514d8981	1711	#define __HAL_RCC_USART8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART8EN)) != RESET)
AnnaBridge	156:ff21514d8981	1712	#define __HAL_RCC_USART7_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART7EN)) == RESET)
AnnaBridge	156:ff21514d8981	1713	#define __HAL_RCC_USART8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART8EN)) == RESET)
AnnaBridge	156:ff21514d8981	1714
AnnaBridge	156:ff21514d8981	1715	#endif /* STM32F091xC \|\| STM32F098xx */
AnnaBridge	156:ff21514d8981	1716	/**
AnnaBridge	156:ff21514d8981	1717	* @}
AnnaBridge	156:ff21514d8981	1718	*/
AnnaBridge	156:ff21514d8981	1719
AnnaBridge	156:ff21514d8981	1720
AnnaBridge	156:ff21514d8981	1721	/** @defgroup RCCEx_HSI48_Enable_Disable RCCEx HSI48 Enable Disable
AnnaBridge	156:ff21514d8981	1722	* @brief Macros to enable or disable the Internal 48Mhz High Speed oscillator (HSI48).
AnnaBridge	156:ff21514d8981	1723	* @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
AnnaBridge	156:ff21514d8981	1724	* @note HSI48 can not be stopped if it is used as system clock source. In this case,
AnnaBridge	156:ff21514d8981	1725	* you have to select another source of the system clock then stop the HSI14.
AnnaBridge	156:ff21514d8981	1726	* @note After enabling the HSI48 with __HAL_RCC_HSI48_ENABLE(), the application software
AnnaBridge	156:ff21514d8981	1727	* should wait on HSI48RDY flag to be set indicating that HSI48 clock is stable and can be
AnnaBridge	156:ff21514d8981	1728	* used as system clock source. This is not necessary if HAL_RCC_OscConfig() is used.
AnnaBridge	156:ff21514d8981	1729	* @note When the HSI48 is stopped, HSI48RDY flag goes low after 6 HSI48 oscillator
AnnaBridge	156:ff21514d8981	1730	* clock cycles.
AnnaBridge	156:ff21514d8981	1731	* @{
AnnaBridge	156:ff21514d8981	1732	*/
AnnaBridge	156:ff21514d8981	1733	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	156:ff21514d8981	1734
AnnaBridge	156:ff21514d8981	1735	#define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI48ON)
AnnaBridge	156:ff21514d8981	1736	#define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI48ON)
AnnaBridge	156:ff21514d8981	1737
AnnaBridge	156:ff21514d8981	1738	/** @brief Macro to get the Internal 48Mhz High Speed oscillator (HSI48) state.
AnnaBridge	156:ff21514d8981	1739	* @retval The clock source can be one of the following values:
AnnaBridge	156:ff21514d8981	1740	* @arg @ref RCC_HSI48_ON HSI48 enabled
AnnaBridge	156:ff21514d8981	1741	* @arg @ref RCC_HSI48_OFF HSI48 disabled
AnnaBridge	156:ff21514d8981	1742	*/
AnnaBridge	156:ff21514d8981	1743	#define __HAL_RCC_GET_HSI48_STATE() \
AnnaBridge	156:ff21514d8981	1744	(((uint32_t)(READ_BIT(RCC->CR2, RCC_CR2_HSI48ON)) != RESET) ? RCC_HSI48_ON : RCC_HSI48_OFF)
AnnaBridge	156:ff21514d8981	1745
AnnaBridge	156:ff21514d8981	1746	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	156:ff21514d8981	1747
AnnaBridge	156:ff21514d8981	1748	/**
AnnaBridge	156:ff21514d8981	1749	* @}
AnnaBridge	156:ff21514d8981	1750	*/
AnnaBridge	156:ff21514d8981	1751
AnnaBridge	156:ff21514d8981	1752	/** @defgroup RCCEx_Peripheral_Clock_Source_Config RCCEx Peripheral Clock Source Config
AnnaBridge	156:ff21514d8981	1753	* @{
AnnaBridge	156:ff21514d8981	1754	*/
AnnaBridge	156:ff21514d8981	1755	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
AnnaBridge	156:ff21514d8981	1756	\|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
AnnaBridge	156:ff21514d8981	1757	\|\| defined(STM32F070x6) \|\| defined(STM32F070xB)
AnnaBridge	156:ff21514d8981	1758
AnnaBridge	156:ff21514d8981	1759	/** @brief Macro to configure the USB clock (USBCLK).
AnnaBridge	156:ff21514d8981	1760	* @param __USBCLKSOURCE__ specifies the USB clock source.
AnnaBridge	156:ff21514d8981	1761	* This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	1762	@if STM32F070xB
AnnaBridge	156:ff21514d8981	1763	@elseif STM32F070x6
AnnaBridge	156:ff21514d8981	1764	@else
AnnaBridge	156:ff21514d8981	1765	* @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as USB clock
AnnaBridge	156:ff21514d8981	1766	@endif
AnnaBridge	156:ff21514d8981	1767	* @arg @ref RCC_USBCLKSOURCE_PLL PLL Clock selected as USB clock
AnnaBridge	156:ff21514d8981	1768	*/
AnnaBridge	156:ff21514d8981	1769	#define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) \
AnnaBridge	156:ff21514d8981	1770	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USBSW, (uint32_t)(__USBCLKSOURCE__))
AnnaBridge	156:ff21514d8981	1771
AnnaBridge	156:ff21514d8981	1772	/** @brief Macro to get the USB clock source.
AnnaBridge	156:ff21514d8981	1773	* @retval The clock source can be one of the following values:
AnnaBridge	156:ff21514d8981	1774	@if STM32F070xB
AnnaBridge	156:ff21514d8981	1775	@elseif STM32F070x6
AnnaBridge	156:ff21514d8981	1776	@else
AnnaBridge	156:ff21514d8981	1777	* @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as USB clock
AnnaBridge	156:ff21514d8981	1778	@endif
AnnaBridge	156:ff21514d8981	1779	* @arg @ref RCC_USBCLKSOURCE_PLL PLL Clock selected as USB clock
AnnaBridge	156:ff21514d8981	1780	*/
AnnaBridge	156:ff21514d8981	1781	#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USBSW)))
AnnaBridge	156:ff21514d8981	1782
AnnaBridge	156:ff21514d8981	1783	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
AnnaBridge	156:ff21514d8981	1784	/* STM32F072xB \|\| STM32F078xx \|\| */
AnnaBridge	156:ff21514d8981	1785	/* STM32F070x6 \|\| STM32F070xB */
AnnaBridge	156:ff21514d8981	1786
AnnaBridge	156:ff21514d8981	1787	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
AnnaBridge	156:ff21514d8981	1788	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
AnnaBridge	156:ff21514d8981	1789	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
AnnaBridge	156:ff21514d8981	1790	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
AnnaBridge	156:ff21514d8981	1791
AnnaBridge	156:ff21514d8981	1792	/** @brief Macro to configure the CEC clock.
AnnaBridge	156:ff21514d8981	1793	* @param __CECCLKSOURCE__ specifies the CEC clock source.
AnnaBridge	156:ff21514d8981	1794	* This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	1795	* @arg @ref RCC_CECCLKSOURCE_HSI HSI selected as CEC clock
AnnaBridge	156:ff21514d8981	1796	* @arg @ref RCC_CECCLKSOURCE_LSE LSE selected as CEC clock
AnnaBridge	156:ff21514d8981	1797	*/
AnnaBridge	156:ff21514d8981	1798	#define __HAL_RCC_CEC_CONFIG(__CECCLKSOURCE__) \
AnnaBridge	156:ff21514d8981	1799	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, (uint32_t)(__CECCLKSOURCE__))
AnnaBridge	156:ff21514d8981	1800
AnnaBridge	156:ff21514d8981	1801	/** @brief Macro to get the HDMI CEC clock source.
AnnaBridge	156:ff21514d8981	1802	* @retval The clock source can be one of the following values:
AnnaBridge	156:ff21514d8981	1803	* @arg @ref RCC_CECCLKSOURCE_HSI HSI selected as CEC clock
AnnaBridge	156:ff21514d8981	1804	* @arg @ref RCC_CECCLKSOURCE_LSE LSE selected as CEC clock
AnnaBridge	156:ff21514d8981	1805	*/
AnnaBridge	156:ff21514d8981	1806	#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_CECSW)))
AnnaBridge	156:ff21514d8981	1807
AnnaBridge	156:ff21514d8981	1808	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
AnnaBridge	156:ff21514d8981	1809	/* STM32F051x8 \|\| STM32F058xx \|\| */
AnnaBridge	156:ff21514d8981	1810	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
AnnaBridge	156:ff21514d8981	1811	/* STM32F091xC \|\| defined(STM32F098xx) */
AnnaBridge	156:ff21514d8981	1812
AnnaBridge	156:ff21514d8981	1813	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
AnnaBridge	156:ff21514d8981	1814	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
AnnaBridge	156:ff21514d8981	1815	/** @brief Macro to configure the USART2 clock (USART2CLK).
AnnaBridge	156:ff21514d8981	1816	* @param __USART2CLKSOURCE__ specifies the USART2 clock source.
AnnaBridge	156:ff21514d8981	1817	* This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	1818	* @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock
AnnaBridge	156:ff21514d8981	1819	* @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock
AnnaBridge	156:ff21514d8981	1820	* @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock
AnnaBridge	156:ff21514d8981	1821	* @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock
AnnaBridge	156:ff21514d8981	1822	*/
AnnaBridge	156:ff21514d8981	1823	#define __HAL_RCC_USART2_CONFIG(__USART2CLKSOURCE__) \
AnnaBridge	156:ff21514d8981	1824	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART2SW, (uint32_t)(__USART2CLKSOURCE__))
AnnaBridge	156:ff21514d8981	1825
AnnaBridge	156:ff21514d8981	1826	/** @brief Macro to get the USART2 clock source.
AnnaBridge	156:ff21514d8981	1827	* @retval The clock source can be one of the following values:
AnnaBridge	156:ff21514d8981	1828	* @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock
AnnaBridge	156:ff21514d8981	1829	* @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock
AnnaBridge	156:ff21514d8981	1830	* @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock
AnnaBridge	156:ff21514d8981	1831	* @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock
AnnaBridge	156:ff21514d8981	1832	*/
AnnaBridge	156:ff21514d8981	1833	#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART2SW)))
AnnaBridge	156:ff21514d8981	1834	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F091xC \|\| STM32F098xx*/
AnnaBridge	156:ff21514d8981	1835
AnnaBridge	156:ff21514d8981	1836	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
AnnaBridge	156:ff21514d8981	1837	/** @brief Macro to configure the USART3 clock (USART3CLK).
AnnaBridge	156:ff21514d8981	1838	* @param __USART3CLKSOURCE__ specifies the USART3 clock source.
AnnaBridge	156:ff21514d8981	1839	* This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	1840	* @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock
AnnaBridge	156:ff21514d8981	1841	* @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock
AnnaBridge	156:ff21514d8981	1842	* @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock
AnnaBridge	156:ff21514d8981	1843	* @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock
AnnaBridge	156:ff21514d8981	1844	*/
AnnaBridge	156:ff21514d8981	1845	#define __HAL_RCC_USART3_CONFIG(__USART3CLKSOURCE__) \
AnnaBridge	156:ff21514d8981	1846	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART3SW, (uint32_t)(__USART3CLKSOURCE__))
AnnaBridge	156:ff21514d8981	1847
AnnaBridge	156:ff21514d8981	1848	/** @brief Macro to get the USART3 clock source.
AnnaBridge	156:ff21514d8981	1849	* @retval The clock source can be one of the following values:
AnnaBridge	156:ff21514d8981	1850	* @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock
AnnaBridge	156:ff21514d8981	1851	* @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock
AnnaBridge	156:ff21514d8981	1852	* @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock
AnnaBridge	156:ff21514d8981	1853	* @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock
AnnaBridge	156:ff21514d8981	1854	*/
AnnaBridge	156:ff21514d8981	1855	#define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART3SW)))
AnnaBridge	156:ff21514d8981	1856
AnnaBridge	156:ff21514d8981	1857	#endif /* STM32F091xC \|\| STM32F098xx */
AnnaBridge	156:ff21514d8981	1858	/**
AnnaBridge	156:ff21514d8981	1859	* @}
AnnaBridge	156:ff21514d8981	1860	*/
AnnaBridge	156:ff21514d8981	1861
AnnaBridge	156:ff21514d8981	1862	/** @defgroup RCCEx_LSE_Configuration LSE Drive Configuration
AnnaBridge	156:ff21514d8981	1863	* @{
AnnaBridge	156:ff21514d8981	1864	*/
AnnaBridge	156:ff21514d8981	1865
AnnaBridge	156:ff21514d8981	1866	/**
AnnaBridge	156:ff21514d8981	1867	* @brief Macro to configure the External Low Speed oscillator (LSE) drive capability.
AnnaBridge	156:ff21514d8981	1868	* @param __RCC_LSEDRIVE__ specifies the new state of the LSE drive capability.
AnnaBridge	156:ff21514d8981	1869	* This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	1870	* @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability.
AnnaBridge	156:ff21514d8981	1871	* @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability.
AnnaBridge	156:ff21514d8981	1872	* @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability.
AnnaBridge	156:ff21514d8981	1873	* @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability.
AnnaBridge	156:ff21514d8981	1874	* @retval None
AnnaBridge	156:ff21514d8981	1875	*/
AnnaBridge	156:ff21514d8981	1876	#define __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDRIVE__) (MODIFY_REG(RCC->BDCR,\
AnnaBridge	156:ff21514d8981	1877	RCC_BDCR_LSEDRV, (uint32_t)(__RCC_LSEDRIVE__) ))
AnnaBridge	156:ff21514d8981	1878
AnnaBridge	156:ff21514d8981	1879	/**
AnnaBridge	156:ff21514d8981	1880	* @}
AnnaBridge	156:ff21514d8981	1881	*/
AnnaBridge	156:ff21514d8981	1882
AnnaBridge	156:ff21514d8981	1883	#if defined(CRS)
AnnaBridge	156:ff21514d8981	1884
AnnaBridge	156:ff21514d8981	1885	/** @defgroup RCCEx_IT_And_Flag RCCEx IT and Flag
AnnaBridge	156:ff21514d8981	1886	* @{
AnnaBridge	156:ff21514d8981	1887	*/
AnnaBridge	156:ff21514d8981	1888	/* Interrupt & Flag management */
AnnaBridge	156:ff21514d8981	1889
AnnaBridge	156:ff21514d8981	1890	/**
AnnaBridge	156:ff21514d8981	1891	* @brief Enable the specified CRS interrupts.
AnnaBridge	156:ff21514d8981	1892	* @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled.
AnnaBridge	156:ff21514d8981	1893	* This parameter can be any combination of the following values:
AnnaBridge	156:ff21514d8981	1894	* @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
AnnaBridge	156:ff21514d8981	1895	* @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
AnnaBridge	156:ff21514d8981	1896	* @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
AnnaBridge	156:ff21514d8981	1897	* @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
AnnaBridge	156:ff21514d8981	1898	* @retval None
AnnaBridge	156:ff21514d8981	1899	*/
AnnaBridge	156:ff21514d8981	1900	#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__))
AnnaBridge	156:ff21514d8981	1901
AnnaBridge	156:ff21514d8981	1902	/**
AnnaBridge	156:ff21514d8981	1903	* @brief Disable the specified CRS interrupts.
AnnaBridge	156:ff21514d8981	1904	* @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled.
AnnaBridge	156:ff21514d8981	1905	* This parameter can be any combination of the following values:
AnnaBridge	156:ff21514d8981	1906	* @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
AnnaBridge	156:ff21514d8981	1907	* @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
AnnaBridge	156:ff21514d8981	1908	* @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
AnnaBridge	156:ff21514d8981	1909	* @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
AnnaBridge	156:ff21514d8981	1910	* @retval None
AnnaBridge	156:ff21514d8981	1911	*/
AnnaBridge	156:ff21514d8981	1912	#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__))
AnnaBridge	156:ff21514d8981	1913
AnnaBridge	156:ff21514d8981	1914	/** @brief Check whether the CRS interrupt has occurred or not.
AnnaBridge	156:ff21514d8981	1915	* @param __INTERRUPT__ specifies the CRS interrupt source to check.
AnnaBridge	156:ff21514d8981	1916	* This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	1917	* @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
AnnaBridge	156:ff21514d8981	1918	* @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
AnnaBridge	156:ff21514d8981	1919	* @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
AnnaBridge	156:ff21514d8981	1920	* @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
AnnaBridge	156:ff21514d8981	1921	* @retval The new state of __INTERRUPT__ (SET or RESET).
AnnaBridge	156:ff21514d8981	1922	*/
AnnaBridge	156:ff21514d8981	1923	#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != RESET) ? SET : RESET)
AnnaBridge	156:ff21514d8981	1924
AnnaBridge	156:ff21514d8981	1925	/** @brief Clear the CRS interrupt pending bits
AnnaBridge	156:ff21514d8981	1926	* @param __INTERRUPT__ specifies the interrupt pending bit to clear.
AnnaBridge	156:ff21514d8981	1927	* This parameter can be any combination of the following values:
AnnaBridge	156:ff21514d8981	1928	* @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
AnnaBridge	156:ff21514d8981	1929	* @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
AnnaBridge	156:ff21514d8981	1930	* @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
AnnaBridge	156:ff21514d8981	1931	* @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
AnnaBridge	156:ff21514d8981	1932	* @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt
AnnaBridge	156:ff21514d8981	1933	* @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt
AnnaBridge	156:ff21514d8981	1934	* @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt
AnnaBridge	156:ff21514d8981	1935	*/
AnnaBridge	156:ff21514d8981	1936	#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \
AnnaBridge	156:ff21514d8981	1937	if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != RESET) \
AnnaBridge	156:ff21514d8981	1938	{ \
AnnaBridge	156:ff21514d8981	1939	WRITE_REG(CRS->ICR, CRS_ICR_ERRC \| ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \
AnnaBridge	156:ff21514d8981	1940	} \
AnnaBridge	156:ff21514d8981	1941	else \
AnnaBridge	156:ff21514d8981	1942	{ \
AnnaBridge	156:ff21514d8981	1943	WRITE_REG(CRS->ICR, (__INTERRUPT__)); \
AnnaBridge	156:ff21514d8981	1944	} \
AnnaBridge	156:ff21514d8981	1945	} while(0)
AnnaBridge	156:ff21514d8981	1946
AnnaBridge	156:ff21514d8981	1947	/**
AnnaBridge	156:ff21514d8981	1948	* @brief Check whether the specified CRS flag is set or not.
AnnaBridge	156:ff21514d8981	1949	* @param __FLAG__ specifies the flag to check.
AnnaBridge	156:ff21514d8981	1950	* This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	1951	* @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK
AnnaBridge	156:ff21514d8981	1952	* @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning
AnnaBridge	156:ff21514d8981	1953	* @arg @ref RCC_CRS_FLAG_ERR Error
AnnaBridge	156:ff21514d8981	1954	* @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC
AnnaBridge	156:ff21514d8981	1955	* @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow
AnnaBridge	156:ff21514d8981	1956	* @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error
AnnaBridge	156:ff21514d8981	1957	* @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed
AnnaBridge	156:ff21514d8981	1958	* @retval The new state of _FLAG_ (TRUE or FALSE).
AnnaBridge	156:ff21514d8981	1959	*/
AnnaBridge	156:ff21514d8981	1960	#define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__))
AnnaBridge	156:ff21514d8981	1961
AnnaBridge	156:ff21514d8981	1962	/**
AnnaBridge	156:ff21514d8981	1963	* @brief Clear the CRS specified FLAG.
AnnaBridge	156:ff21514d8981	1964	* @param __FLAG__ specifies the flag to clear.
AnnaBridge	156:ff21514d8981	1965	* This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	1966	* @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK
AnnaBridge	156:ff21514d8981	1967	* @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning
AnnaBridge	156:ff21514d8981	1968	* @arg @ref RCC_CRS_FLAG_ERR Error
AnnaBridge	156:ff21514d8981	1969	* @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC
AnnaBridge	156:ff21514d8981	1970	* @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow
AnnaBridge	156:ff21514d8981	1971	* @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error
AnnaBridge	156:ff21514d8981	1972	* @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed
AnnaBridge	156:ff21514d8981	1973	* @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR
AnnaBridge	156:ff21514d8981	1974	* @retval None
AnnaBridge	156:ff21514d8981	1975	*/
AnnaBridge	156:ff21514d8981	1976	#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \
AnnaBridge	156:ff21514d8981	1977	if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != RESET) \
AnnaBridge	156:ff21514d8981	1978	{ \
AnnaBridge	156:ff21514d8981	1979	WRITE_REG(CRS->ICR, CRS_ICR_ERRC \| ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \
AnnaBridge	156:ff21514d8981	1980	} \
AnnaBridge	156:ff21514d8981	1981	else \
AnnaBridge	156:ff21514d8981	1982	{ \
AnnaBridge	156:ff21514d8981	1983	WRITE_REG(CRS->ICR, (__FLAG__)); \
AnnaBridge	156:ff21514d8981	1984	} \
AnnaBridge	156:ff21514d8981	1985	} while(0)
AnnaBridge	156:ff21514d8981	1986
AnnaBridge	156:ff21514d8981	1987	/**
AnnaBridge	156:ff21514d8981	1988	* @}
AnnaBridge	156:ff21514d8981	1989	*/
AnnaBridge	156:ff21514d8981	1990
AnnaBridge	156:ff21514d8981	1991	/** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features
AnnaBridge	156:ff21514d8981	1992	* @{
AnnaBridge	156:ff21514d8981	1993	*/
AnnaBridge	156:ff21514d8981	1994	/**
AnnaBridge	156:ff21514d8981	1995	* @brief Enable the oscillator clock for frequency error counter.
AnnaBridge	156:ff21514d8981	1996	* @note when the CEN bit is set the CRS_CFGR register becomes write-protected.
AnnaBridge	156:ff21514d8981	1997	* @retval None
AnnaBridge	156:ff21514d8981	1998	*/
AnnaBridge	156:ff21514d8981	1999	#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN)
AnnaBridge	156:ff21514d8981	2000
AnnaBridge	156:ff21514d8981	2001	/**
AnnaBridge	156:ff21514d8981	2002	* @brief Disable the oscillator clock for frequency error counter.
AnnaBridge	156:ff21514d8981	2003	* @retval None
AnnaBridge	156:ff21514d8981	2004	*/
AnnaBridge	156:ff21514d8981	2005	#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN)
AnnaBridge	156:ff21514d8981	2006
AnnaBridge	156:ff21514d8981	2007	/**
AnnaBridge	156:ff21514d8981	2008	* @brief Enable the automatic hardware adjustement of TRIM bits.
AnnaBridge	156:ff21514d8981	2009	* @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
AnnaBridge	156:ff21514d8981	2010	* @retval None
AnnaBridge	156:ff21514d8981	2011	*/
AnnaBridge	156:ff21514d8981	2012	#define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
AnnaBridge	156:ff21514d8981	2013
AnnaBridge	156:ff21514d8981	2014	/**
AnnaBridge	156:ff21514d8981	2015	* @brief Disable the automatic hardware adjustement of TRIM bits.
AnnaBridge	156:ff21514d8981	2016	* @retval None
AnnaBridge	156:ff21514d8981	2017	*/
AnnaBridge	156:ff21514d8981	2018	#define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
AnnaBridge	156:ff21514d8981	2019
AnnaBridge	156:ff21514d8981	2020	/**
AnnaBridge	156:ff21514d8981	2021	* @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
AnnaBridge	156:ff21514d8981	2022	* @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency
AnnaBridge	156:ff21514d8981	2023	* of the synchronization source after prescaling. It is then decreased by one in order to
AnnaBridge	156:ff21514d8981	2024	* reach the expected synchronization on the zero value. The formula is the following:
AnnaBridge	156:ff21514d8981	2025	* RELOAD = (fTARGET / fSYNC) -1
AnnaBridge	156:ff21514d8981	2026	* @param __FTARGET__ Target frequency (value in Hz)
AnnaBridge	156:ff21514d8981	2027	* @param __FSYNC__ Synchronization signal frequency (value in Hz)
AnnaBridge	156:ff21514d8981	2028	* @retval None
AnnaBridge	156:ff21514d8981	2029	*/
AnnaBridge	156:ff21514d8981	2030	#define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
AnnaBridge	156:ff21514d8981	2031
AnnaBridge	156:ff21514d8981	2032	/**
AnnaBridge	156:ff21514d8981	2033	* @}
AnnaBridge	156:ff21514d8981	2034	*/
AnnaBridge	156:ff21514d8981	2035
AnnaBridge	156:ff21514d8981	2036	#endif /* CRS */
AnnaBridge	156:ff21514d8981	2037
AnnaBridge	156:ff21514d8981	2038	/**
AnnaBridge	156:ff21514d8981	2039	* @}
AnnaBridge	156:ff21514d8981	2040	*/
AnnaBridge	156:ff21514d8981	2041
AnnaBridge	156:ff21514d8981	2042	/* Exported functions --------------------------------------------------------*/
AnnaBridge	156:ff21514d8981	2043	/** @addtogroup RCCEx_Exported_Functions
AnnaBridge	156:ff21514d8981	2044	* @{
AnnaBridge	156:ff21514d8981	2045	*/
AnnaBridge	156:ff21514d8981	2046
AnnaBridge	156:ff21514d8981	2047	/** @addtogroup RCCEx_Exported_Functions_Group1
AnnaBridge	156:ff21514d8981	2048	* @{
AnnaBridge	156:ff21514d8981	2049	*/
AnnaBridge	156:ff21514d8981	2050
AnnaBridge	156:ff21514d8981	2051	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
AnnaBridge	156:ff21514d8981	2052	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
AnnaBridge	156:ff21514d8981	2053	uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
AnnaBridge	156:ff21514d8981	2054
AnnaBridge	156:ff21514d8981	2055	/**
AnnaBridge	156:ff21514d8981	2056	* @}
AnnaBridge	156:ff21514d8981	2057	*/
AnnaBridge	156:ff21514d8981	2058
AnnaBridge	156:ff21514d8981	2059	#if defined(CRS)
AnnaBridge	156:ff21514d8981	2060
AnnaBridge	156:ff21514d8981	2061	/** @addtogroup RCCEx_Exported_Functions_Group3
AnnaBridge	156:ff21514d8981	2062	* @{
AnnaBridge	156:ff21514d8981	2063	*/
AnnaBridge	156:ff21514d8981	2064
AnnaBridge	156:ff21514d8981	2065	void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
AnnaBridge	156:ff21514d8981	2066	void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
AnnaBridge	156:ff21514d8981	2067	void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
AnnaBridge	156:ff21514d8981	2068	uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
AnnaBridge	156:ff21514d8981	2069	void HAL_RCCEx_CRS_IRQHandler(void);
AnnaBridge	156:ff21514d8981	2070	void HAL_RCCEx_CRS_SyncOkCallback(void);
AnnaBridge	156:ff21514d8981	2071	void HAL_RCCEx_CRS_SyncWarnCallback(void);
AnnaBridge	156:ff21514d8981	2072	void HAL_RCCEx_CRS_ExpectedSyncCallback(void);
AnnaBridge	156:ff21514d8981	2073	void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error);
AnnaBridge	156:ff21514d8981	2074
AnnaBridge	156:ff21514d8981	2075	/**
AnnaBridge	156:ff21514d8981	2076	* @}
AnnaBridge	156:ff21514d8981	2077	*/
AnnaBridge	156:ff21514d8981	2078
AnnaBridge	156:ff21514d8981	2079	#endif /* CRS */
AnnaBridge	156:ff21514d8981	2080
AnnaBridge	156:ff21514d8981	2081	/**
AnnaBridge	156:ff21514d8981	2082	* @}
AnnaBridge	156:ff21514d8981	2083	*/
AnnaBridge	156:ff21514d8981	2084
AnnaBridge	156:ff21514d8981	2085	/**
AnnaBridge	156:ff21514d8981	2086	* @}
AnnaBridge	156:ff21514d8981	2087	*/
AnnaBridge	156:ff21514d8981	2088
AnnaBridge	156:ff21514d8981	2089	/**
AnnaBridge	156:ff21514d8981	2090	* @}
AnnaBridge	156:ff21514d8981	2091	*/
AnnaBridge	156:ff21514d8981	2092
AnnaBridge	156:ff21514d8981	2093	/**
AnnaBridge	156:ff21514d8981	2094	* @}
AnnaBridge	156:ff21514d8981	2095	*/
AnnaBridge	156:ff21514d8981	2096
AnnaBridge	156:ff21514d8981	2097	#ifdef __cplusplus
AnnaBridge	156:ff21514d8981	2098	}
AnnaBridge	156:ff21514d8981	2099	#endif
AnnaBridge	156:ff21514d8981	2100
AnnaBridge	156:ff21514d8981	2101	#endif /* __STM32F0xx_HAL_RCC_EX_H */
AnnaBridge	156:ff21514d8981	2102
AnnaBridge	156:ff21514d8981	2103	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/