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TARGET_NUCLEO_L152RE/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_tim.h@169:a7c7b631e539, 2018-06-22 (annotated)

Committer:
Anna Bridge
Date:
Fri Jun 22 15:38:59 2018 +0100
Revision:
169:a7c7b631e539
Parent:
165:d1b4690b3f8b 
mbed library. Release version 162

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 128:9bcdf88f62b0 1 /**
<> 128:9bcdf88f62b0 2 ******************************************************************************
<> 128:9bcdf88f62b0 3 * @file stm32l1xx_hal_tim.h
<> 128:9bcdf88f62b0 4 * @author MCD Application Team
<> 128:9bcdf88f62b0 5 * @brief Header file of TIM HAL module.
<> 128:9bcdf88f62b0 6 ******************************************************************************
<> 128:9bcdf88f62b0 7 * @attention
<> 128:9bcdf88f62b0 8 *
AnnaBridge 165:d1b4690b3f8b 9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 128:9bcdf88f62b0 10 *
<> 128:9bcdf88f62b0 11 * Redistribution and use in source and binary forms, with or without modification,
<> 128:9bcdf88f62b0 12 * are permitted provided that the following conditions are met:
<> 128:9bcdf88f62b0 13 * 1. Redistributions of source code must retain the above copyright notice,
<> 128:9bcdf88f62b0 14 * this list of conditions and the following disclaimer.
<> 128:9bcdf88f62b0 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 128:9bcdf88f62b0 16 * this list of conditions and the following disclaimer in the documentation
<> 128:9bcdf88f62b0 17 * and/or other materials provided with the distribution.
<> 128:9bcdf88f62b0 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 128:9bcdf88f62b0 19 * may be used to endorse or promote products derived from this software
<> 128:9bcdf88f62b0 20 * without specific prior written permission.
<> 128:9bcdf88f62b0 21 *
<> 128:9bcdf88f62b0 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 128:9bcdf88f62b0 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 128:9bcdf88f62b0 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 128:9bcdf88f62b0 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 128:9bcdf88f62b0 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 128:9bcdf88f62b0 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 128:9bcdf88f62b0 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 128:9bcdf88f62b0 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 128:9bcdf88f62b0 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 128:9bcdf88f62b0 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 128:9bcdf88f62b0 32 *
<> 128:9bcdf88f62b0 33 ******************************************************************************
<> 128:9bcdf88f62b0 34 */
<> 128:9bcdf88f62b0 35
<> 128:9bcdf88f62b0 36 /* Define to prevent recursive inclusion -------------------------------------*/
<> 128:9bcdf88f62b0 37 #ifndef __STM32L1xx_HAL_TIM_H
<> 128:9bcdf88f62b0 38 #define __STM32L1xx_HAL_TIM_H
<> 128:9bcdf88f62b0 39
<> 128:9bcdf88f62b0 40 #ifdef __cplusplus
<> 128:9bcdf88f62b0 41 extern "C" {
<> 128:9bcdf88f62b0 42 #endif
<> 128:9bcdf88f62b0 43
<> 128:9bcdf88f62b0 44 /* Includes ------------------------------------------------------------------*/
<> 128:9bcdf88f62b0 45 #include "stm32l1xx_hal_def.h"
<> 128:9bcdf88f62b0 46
<> 128:9bcdf88f62b0 47 /** @addtogroup STM32L1xx_HAL_Driver
<> 128:9bcdf88f62b0 48 * @{
<> 128:9bcdf88f62b0 49 */
<> 128:9bcdf88f62b0 50
<> 128:9bcdf88f62b0 51 /** @addtogroup TIM
<> 128:9bcdf88f62b0 52 * @{
<> 128:9bcdf88f62b0 53 */
<> 128:9bcdf88f62b0 54
<> 128:9bcdf88f62b0 55 /* Exported types ------------------------------------------------------------*/
<> 128:9bcdf88f62b0 56 /** @defgroup TIM_Exported_Types TIM Exported Types
<> 128:9bcdf88f62b0 57 * @{
<> 128:9bcdf88f62b0 58 */
<> 128:9bcdf88f62b0 59 /**
<> 128:9bcdf88f62b0 60 * @brief TIM Time base Configuration Structure definition
<> 128:9bcdf88f62b0 61 */
<> 128:9bcdf88f62b0 62 typedef struct
<> 128:9bcdf88f62b0 63 {
<> 128:9bcdf88f62b0 64 uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
<> 128:9bcdf88f62b0 65 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
<> 128:9bcdf88f62b0 66
<> 128:9bcdf88f62b0 67 uint32_t CounterMode; /*!< Specifies the counter mode.
<> 128:9bcdf88f62b0 68 This parameter can be a value of @ref TIM_Counter_Mode */
<> 128:9bcdf88f62b0 69
<> 128:9bcdf88f62b0 70 uint32_t Period; /*!< Specifies the period value to be loaded into the active
<> 128:9bcdf88f62b0 71 Auto-Reload Register at the next update event.
<> 128:9bcdf88f62b0 72 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
<> 128:9bcdf88f62b0 73
<> 128:9bcdf88f62b0 74 uint32_t ClockDivision; /*!< Specifies the clock division.
<> 128:9bcdf88f62b0 75 This parameter can be a value of @ref TIM_ClockDivision */
<> 128:9bcdf88f62b0 76
<> 128:9bcdf88f62b0 77 } TIM_Base_InitTypeDef;
<> 128:9bcdf88f62b0 78
<> 128:9bcdf88f62b0 79 /**
<> 128:9bcdf88f62b0 80 * @brief TIM Output Compare Configuration Structure definition
<> 128:9bcdf88f62b0 81 */
<> 128:9bcdf88f62b0 82 typedef struct
<> 128:9bcdf88f62b0 83 {
<> 128:9bcdf88f62b0 84 uint32_t OCMode; /*!< Specifies the TIM mode.
<> 128:9bcdf88f62b0 85 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
<> 128:9bcdf88f62b0 86
<> 128:9bcdf88f62b0 87 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
<> 128:9bcdf88f62b0 88 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
<> 128:9bcdf88f62b0 89
<> 128:9bcdf88f62b0 90 uint32_t OCPolarity; /*!< Specifies the output polarity.
<> 128:9bcdf88f62b0 91 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
<> 128:9bcdf88f62b0 92
<> 128:9bcdf88f62b0 93 uint32_t OCFastMode; /*!< Specifies the Fast mode state.
<> 128:9bcdf88f62b0 94 This parameter can be a value of @ref TIM_Output_Fast_State
<> 128:9bcdf88f62b0 95 @note This parameter is valid only in PWM1 and PWM2 mode. */
<> 128:9bcdf88f62b0 96
<> 128:9bcdf88f62b0 97 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
<> 128:9bcdf88f62b0 98 This parameter can be a value of @ref TIM_Output_Compare_Idle_State. */
<> 128:9bcdf88f62b0 99 } TIM_OC_InitTypeDef;
<> 128:9bcdf88f62b0 100
<> 128:9bcdf88f62b0 101 /**
<> 128:9bcdf88f62b0 102 * @brief TIM One Pulse Mode Configuration Structure definition
<> 128:9bcdf88f62b0 103 */
<> 128:9bcdf88f62b0 104 typedef struct
<> 128:9bcdf88f62b0 105 {
<> 128:9bcdf88f62b0 106 uint32_t OCMode; /*!< Specifies the TIM mode.
<> 128:9bcdf88f62b0 107 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
<> 128:9bcdf88f62b0 108
<> 128:9bcdf88f62b0 109 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
<> 128:9bcdf88f62b0 110 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
<> 128:9bcdf88f62b0 111
<> 128:9bcdf88f62b0 112 uint32_t OCPolarity; /*!< Specifies the output polarity.
<> 128:9bcdf88f62b0 113 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
<> 128:9bcdf88f62b0 114
<> 128:9bcdf88f62b0 115 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
<> 128:9bcdf88f62b0 116 This parameter can be a value of @ref TIM_Output_Compare_Idle_State. */
<> 128:9bcdf88f62b0 117
<> 128:9bcdf88f62b0 118 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
<> 128:9bcdf88f62b0 119 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
<> 128:9bcdf88f62b0 120
<> 128:9bcdf88f62b0 121 uint32_t ICSelection; /*!< Specifies the input.
<> 128:9bcdf88f62b0 122 This parameter can be a value of @ref TIM_Input_Capture_Selection */
<> 128:9bcdf88f62b0 123
<> 128:9bcdf88f62b0 124 uint32_t ICFilter; /*!< Specifies the input capture filter.
<> 128:9bcdf88f62b0 125 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
<> 128:9bcdf88f62b0 126 } TIM_OnePulse_InitTypeDef;
<> 128:9bcdf88f62b0 127
<> 128:9bcdf88f62b0 128
<> 128:9bcdf88f62b0 129 /**
<> 128:9bcdf88f62b0 130 * @brief TIM Input Capture Configuration Structure definition
<> 128:9bcdf88f62b0 131 */
<> 128:9bcdf88f62b0 132 typedef struct
<> 128:9bcdf88f62b0 133 {
<> 128:9bcdf88f62b0 134 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
<> 128:9bcdf88f62b0 135 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
<> 128:9bcdf88f62b0 136
<> 128:9bcdf88f62b0 137 uint32_t ICSelection; /*!< Specifies the input.
<> 128:9bcdf88f62b0 138 This parameter can be a value of @ref TIM_Input_Capture_Selection */
<> 128:9bcdf88f62b0 139
<> 128:9bcdf88f62b0 140 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
<> 128:9bcdf88f62b0 141 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
<> 128:9bcdf88f62b0 142
<> 128:9bcdf88f62b0 143 uint32_t ICFilter; /*!< Specifies the input capture filter.
<> 128:9bcdf88f62b0 144 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
<> 128:9bcdf88f62b0 145 } TIM_IC_InitTypeDef;
<> 128:9bcdf88f62b0 146
<> 128:9bcdf88f62b0 147 /**
<> 128:9bcdf88f62b0 148 * @brief TIM Encoder Configuration Structure definition
<> 128:9bcdf88f62b0 149 */
<> 128:9bcdf88f62b0 150 typedef struct
<> 128:9bcdf88f62b0 151 {
<> 128:9bcdf88f62b0 152 uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
<> 128:9bcdf88f62b0 153 This parameter can be a value of @ref TIM_Encoder_Mode */
<> 128:9bcdf88f62b0 154
<> 128:9bcdf88f62b0 155 uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
<> 128:9bcdf88f62b0 156 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
<> 128:9bcdf88f62b0 157
<> 128:9bcdf88f62b0 158 uint32_t IC1Selection; /*!< Specifies the input.
<> 128:9bcdf88f62b0 159 This parameter can be a value of @ref TIM_Input_Capture_Selection */
<> 128:9bcdf88f62b0 160
<> 128:9bcdf88f62b0 161 uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
<> 128:9bcdf88f62b0 162 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
<> 128:9bcdf88f62b0 163
<> 128:9bcdf88f62b0 164 uint32_t IC1Filter; /*!< Specifies the input capture filter.
<> 128:9bcdf88f62b0 165 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
<> 128:9bcdf88f62b0 166
<> 128:9bcdf88f62b0 167 uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
<> 128:9bcdf88f62b0 168 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
<> 128:9bcdf88f62b0 169
<> 128:9bcdf88f62b0 170 uint32_t IC2Selection; /*!< Specifies the input.
<> 128:9bcdf88f62b0 171 This parameter can be a value of @ref TIM_Input_Capture_Selection */
<> 128:9bcdf88f62b0 172
<> 128:9bcdf88f62b0 173 uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
<> 128:9bcdf88f62b0 174 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
<> 128:9bcdf88f62b0 175
<> 128:9bcdf88f62b0 176 uint32_t IC2Filter; /*!< Specifies the input capture filter.
<> 128:9bcdf88f62b0 177 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
<> 128:9bcdf88f62b0 178 } TIM_Encoder_InitTypeDef;
<> 128:9bcdf88f62b0 179
<> 128:9bcdf88f62b0 180
<> 128:9bcdf88f62b0 181 /**
<> 128:9bcdf88f62b0 182 * @brief TIM Clock Configuration Handle Structure definition
<> 128:9bcdf88f62b0 183 */
<> 128:9bcdf88f62b0 184 typedef struct
<> 128:9bcdf88f62b0 185 {
<> 128:9bcdf88f62b0 186 uint32_t ClockSource; /*!< TIM clock sources
<> 128:9bcdf88f62b0 187 This parameter can be a value of @ref TIM_Clock_Source */
<> 128:9bcdf88f62b0 188 uint32_t ClockPolarity; /*!< TIM clock polarity
<> 128:9bcdf88f62b0 189 This parameter can be a value of @ref TIM_Clock_Polarity */
<> 128:9bcdf88f62b0 190 uint32_t ClockPrescaler; /*!< TIM clock prescaler
<> 128:9bcdf88f62b0 191 This parameter can be a value of @ref TIM_Clock_Prescaler */
<> 128:9bcdf88f62b0 192 uint32_t ClockFilter; /*!< TIM clock filter
<> 128:9bcdf88f62b0 193 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
<> 128:9bcdf88f62b0 194 }TIM_ClockConfigTypeDef;
<> 128:9bcdf88f62b0 195
<> 128:9bcdf88f62b0 196 /**
<> 128:9bcdf88f62b0 197 * @brief TIM Clear Input Configuration Handle Structure definition
<> 128:9bcdf88f62b0 198 */
<> 128:9bcdf88f62b0 199 typedef struct
<> 128:9bcdf88f62b0 200 {
<> 128:9bcdf88f62b0 201 uint32_t ClearInputState; /*!< TIM clear Input state
<> 128:9bcdf88f62b0 202 This parameter can be ENABLE or DISABLE */
<> 128:9bcdf88f62b0 203 uint32_t ClearInputSource; /*!< TIM clear Input sources
<> 128:9bcdf88f62b0 204 This parameter can be a value of @ref TIM_ClearInput_Source */
<> 128:9bcdf88f62b0 205 uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
<> 128:9bcdf88f62b0 206 This parameter can be a value of @ref TIM_ClearInput_Polarity */
<> 128:9bcdf88f62b0 207 uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
<> 128:9bcdf88f62b0 208 This parameter can be a value of @ref TIM_ClearInput_Prescaler */
<> 128:9bcdf88f62b0 209 uint32_t ClearInputFilter; /*!< TIM Clear Input filter
<> 128:9bcdf88f62b0 210 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
<> 128:9bcdf88f62b0 211 }TIM_ClearInputConfigTypeDef;
<> 128:9bcdf88f62b0 212
<> 128:9bcdf88f62b0 213 /**
<> 128:9bcdf88f62b0 214 * @brief TIM Slave configuration Structure definition
<> 128:9bcdf88f62b0 215 */
<> 128:9bcdf88f62b0 216 typedef struct {
<> 128:9bcdf88f62b0 217 uint32_t SlaveMode; /*!< Slave mode selection
<> 128:9bcdf88f62b0 218 This parameter can be a value of @ref TIM_Slave_Mode */
<> 128:9bcdf88f62b0 219 uint32_t InputTrigger; /*!< Input Trigger source
<> 128:9bcdf88f62b0 220 This parameter can be a value of @ref TIM_Trigger_Selection */
<> 128:9bcdf88f62b0 221 uint32_t TriggerPolarity; /*!< Input Trigger polarity
<> 128:9bcdf88f62b0 222 This parameter can be a value of @ref TIM_Trigger_Polarity */
<> 128:9bcdf88f62b0 223 uint32_t TriggerPrescaler; /*!< Input trigger prescaler
<> 128:9bcdf88f62b0 224 This parameter can be a value of @ref TIM_Trigger_Prescaler */
<> 128:9bcdf88f62b0 225 uint32_t TriggerFilter; /*!< Input trigger filter
<> 128:9bcdf88f62b0 226 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
<> 128:9bcdf88f62b0 227
<> 128:9bcdf88f62b0 228 }TIM_SlaveConfigTypeDef;
<> 128:9bcdf88f62b0 229
<> 128:9bcdf88f62b0 230 /**
<> 128:9bcdf88f62b0 231 * @brief HAL State structures definition
<> 128:9bcdf88f62b0 232 */
<> 128:9bcdf88f62b0 233 typedef enum
<> 128:9bcdf88f62b0 234 {
<> 128:9bcdf88f62b0 235 HAL_TIM_STATE_RESET = 0x00, /*!< Peripheral not yet initialized or disabled */
<> 128:9bcdf88f62b0 236 HAL_TIM_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
<> 128:9bcdf88f62b0 237 HAL_TIM_STATE_BUSY = 0x02, /*!< An internal process is ongoing */
<> 128:9bcdf88f62b0 238 HAL_TIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */
<> 128:9bcdf88f62b0 239 HAL_TIM_STATE_ERROR = 0x04 /*!< Reception process is ongoing */
<> 128:9bcdf88f62b0 240 }HAL_TIM_StateTypeDef;
<> 128:9bcdf88f62b0 241
<> 128:9bcdf88f62b0 242 /**
<> 128:9bcdf88f62b0 243 * @brief HAL Active channel structures definition
<> 128:9bcdf88f62b0 244 */
<> 128:9bcdf88f62b0 245 typedef enum
<> 128:9bcdf88f62b0 246 {
<> 128:9bcdf88f62b0 247 HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /*!< The active channel is 1 */
<> 128:9bcdf88f62b0 248 HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /*!< The active channel is 2 */
<> 128:9bcdf88f62b0 249 HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /*!< The active channel is 3 */
<> 128:9bcdf88f62b0 250 HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /*!< The active channel is 4 */
<> 128:9bcdf88f62b0 251 HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /*!< All active channels cleared */
<> 128:9bcdf88f62b0 252 }HAL_TIM_ActiveChannel;
<> 128:9bcdf88f62b0 253
<> 128:9bcdf88f62b0 254 /**
<> 128:9bcdf88f62b0 255 * @brief TIM Time Base Handle Structure definition
<> 128:9bcdf88f62b0 256 */
<> 128:9bcdf88f62b0 257 typedef struct
<> 128:9bcdf88f62b0 258 {
<> 128:9bcdf88f62b0 259 TIM_TypeDef *Instance; /*!< Register base address */
<> 128:9bcdf88f62b0 260 TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
<> 128:9bcdf88f62b0 261 HAL_TIM_ActiveChannel Channel; /*!< Active channel */
<> 128:9bcdf88f62b0 262 DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
<> 128:9bcdf88f62b0 263 This array is accessed by a @ref TIM_DMA_Handle_index */
<> 128:9bcdf88f62b0 264 HAL_LockTypeDef Lock; /*!< Locking object */
<> 128:9bcdf88f62b0 265 __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
<> 128:9bcdf88f62b0 266 }TIM_HandleTypeDef;
<> 128:9bcdf88f62b0 267
<> 128:9bcdf88f62b0 268 /**
<> 128:9bcdf88f62b0 269 * @}
<> 128:9bcdf88f62b0 270 */
<> 128:9bcdf88f62b0 271
<> 128:9bcdf88f62b0 272 /* Exported constants --------------------------------------------------------*/
<> 128:9bcdf88f62b0 273 /** @defgroup TIM_Exported_Constants TIM Exported Constants
<> 128:9bcdf88f62b0 274 * @{
<> 128:9bcdf88f62b0 275 */
<> 128:9bcdf88f62b0 276
<> 128:9bcdf88f62b0 277 /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity
<> 128:9bcdf88f62b0 278 * @{
<> 128:9bcdf88f62b0 279 */
AnnaBridge 165:d1b4690b3f8b 280 #define TIM_INPUTCHANNELPOLARITY_RISING (0x00000000U) /*!< Polarity for TIx source */
<> 128:9bcdf88f62b0 281 #define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */
<> 128:9bcdf88f62b0 282 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */
<> 128:9bcdf88f62b0 283 /**
<> 128:9bcdf88f62b0 284 * @}
<> 128:9bcdf88f62b0 285 */
<> 128:9bcdf88f62b0 286
<> 128:9bcdf88f62b0 287 /** @defgroup TIM_ETR_Polarity TIM ETR Polarity
<> 128:9bcdf88f62b0 288 * @{
<> 128:9bcdf88f62b0 289 */
<> 128:9bcdf88f62b0 290 #define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */
AnnaBridge 165:d1b4690b3f8b 291 #define TIM_ETRPOLARITY_NONINVERTED (0x0000U) /*!< Polarity for ETR source */
<> 128:9bcdf88f62b0 292 /**
<> 128:9bcdf88f62b0 293 * @}
<> 128:9bcdf88f62b0 294 */
<> 128:9bcdf88f62b0 295
<> 128:9bcdf88f62b0 296 /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
<> 128:9bcdf88f62b0 297 * @{
<> 128:9bcdf88f62b0 298 */
AnnaBridge 165:d1b4690b3f8b 299 #define TIM_ETRPRESCALER_DIV1 (0x0000U) /*!< No prescaler is used */
<> 128:9bcdf88f62b0 300 #define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */
<> 128:9bcdf88f62b0 301 #define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */
<> 128:9bcdf88f62b0 302 #define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */
<> 128:9bcdf88f62b0 303 /**
<> 128:9bcdf88f62b0 304 * @}
<> 128:9bcdf88f62b0 305 */
<> 128:9bcdf88f62b0 306
<> 128:9bcdf88f62b0 307 /** @defgroup TIM_Counter_Mode TIM Counter Mode
<> 128:9bcdf88f62b0 308 * @{
<> 128:9bcdf88f62b0 309 */
AnnaBridge 165:d1b4690b3f8b 310 #define TIM_COUNTERMODE_UP (0x0000U)
<> 128:9bcdf88f62b0 311 #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
<> 128:9bcdf88f62b0 312 #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
<> 128:9bcdf88f62b0 313 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
<> 128:9bcdf88f62b0 314 #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
<> 128:9bcdf88f62b0 315 /**
<> 128:9bcdf88f62b0 316 * @}
<> 128:9bcdf88f62b0 317 */
<> 128:9bcdf88f62b0 318
<> 128:9bcdf88f62b0 319 /** @defgroup TIM_ClockDivision TIM ClockDivision
<> 128:9bcdf88f62b0 320 * @{
<> 128:9bcdf88f62b0 321 */
AnnaBridge 165:d1b4690b3f8b 322 #define TIM_CLOCKDIVISION_DIV1 (0x0000U)
<> 128:9bcdf88f62b0 323 #define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
<> 128:9bcdf88f62b0 324 #define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
<> 128:9bcdf88f62b0 325 /**
<> 128:9bcdf88f62b0 326 * @}
<> 128:9bcdf88f62b0 327 */
<> 128:9bcdf88f62b0 328
<> 128:9bcdf88f62b0 329 /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM modes
<> 128:9bcdf88f62b0 330 * @{
<> 128:9bcdf88f62b0 331 */
AnnaBridge 165:d1b4690b3f8b 332 #define TIM_OCMODE_TIMING (0x0000U)
<> 128:9bcdf88f62b0 333 #define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)
<> 128:9bcdf88f62b0 334 #define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)
<> 128:9bcdf88f62b0 335 #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1)
<> 128:9bcdf88f62b0 336 #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
<> 128:9bcdf88f62b0 337 #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)
<> 128:9bcdf88f62b0 338 #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
<> 128:9bcdf88f62b0 339 #define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)
<> 128:9bcdf88f62b0 340 /**
<> 128:9bcdf88f62b0 341 * @}
<> 128:9bcdf88f62b0 342 */
<> 128:9bcdf88f62b0 343
<> 128:9bcdf88f62b0 344 /** @defgroup TIM_Output_Fast_State TIM Output Fast State
<> 128:9bcdf88f62b0 345 * @{
<> 128:9bcdf88f62b0 346 */
AnnaBridge 165:d1b4690b3f8b 347 #define TIM_OCFAST_DISABLE (0x0000U)
<> 128:9bcdf88f62b0 348 #define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
<> 128:9bcdf88f62b0 349 /**
<> 128:9bcdf88f62b0 350 * @}
<> 128:9bcdf88f62b0 351 */
<> 128:9bcdf88f62b0 352
<> 128:9bcdf88f62b0 353 /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
<> 128:9bcdf88f62b0 354 * @{
<> 128:9bcdf88f62b0 355 */
AnnaBridge 165:d1b4690b3f8b 356 #define TIM_OCPOLARITY_HIGH (0x0000U)
<> 128:9bcdf88f62b0 357 #define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
<> 128:9bcdf88f62b0 358 /**
<> 128:9bcdf88f62b0 359 * @}
<> 128:9bcdf88f62b0 360 */
<> 128:9bcdf88f62b0 361
<> 128:9bcdf88f62b0 362 /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
<> 128:9bcdf88f62b0 363 * @{
<> 128:9bcdf88f62b0 364 */
<> 128:9bcdf88f62b0 365 #define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
AnnaBridge 165:d1b4690b3f8b 366 #define TIM_OCIDLESTATE_RESET (0x0000U)
<> 128:9bcdf88f62b0 367 /**
<> 128:9bcdf88f62b0 368 * @}
<> 128:9bcdf88f62b0 369 */
<> 128:9bcdf88f62b0 370
<> 128:9bcdf88f62b0 371 /** @defgroup TIM_Channel TIM Channel
<> 128:9bcdf88f62b0 372 * @{
<> 128:9bcdf88f62b0 373 */
AnnaBridge 165:d1b4690b3f8b 374 #define TIM_CHANNEL_1 (0x0000U)
AnnaBridge 165:d1b4690b3f8b 375 #define TIM_CHANNEL_2 (0x0004U)
AnnaBridge 165:d1b4690b3f8b 376 #define TIM_CHANNEL_3 (0x0008U)
AnnaBridge 165:d1b4690b3f8b 377 #define TIM_CHANNEL_4 (0x000CU)
AnnaBridge 165:d1b4690b3f8b 378 #define TIM_CHANNEL_ALL (0x0018U)
<> 128:9bcdf88f62b0 379 /**
<> 128:9bcdf88f62b0 380 * @}
<> 128:9bcdf88f62b0 381 */
<> 128:9bcdf88f62b0 382
<> 128:9bcdf88f62b0 383 /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
<> 128:9bcdf88f62b0 384 * @{
<> 128:9bcdf88f62b0 385 */
<> 128:9bcdf88f62b0 386 #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
<> 128:9bcdf88f62b0 387 #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
<> 128:9bcdf88f62b0 388 #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
<> 128:9bcdf88f62b0 389 /**
<> 128:9bcdf88f62b0 390 * @}
<> 128:9bcdf88f62b0 391 */
<> 128:9bcdf88f62b0 392
<> 128:9bcdf88f62b0 393 /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
<> 128:9bcdf88f62b0 394 * @{
<> 128:9bcdf88f62b0 395 */
<> 128:9bcdf88f62b0 396 #define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
<> 128:9bcdf88f62b0 397 connected to IC1, IC2, IC3 or IC4, respectively */
<> 128:9bcdf88f62b0 398 #define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
<> 128:9bcdf88f62b0 399 connected to IC2, IC1, IC4 or IC3, respectively */
<> 128:9bcdf88f62b0 400 #define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
<> 128:9bcdf88f62b0 401 /**
<> 128:9bcdf88f62b0 402 * @}
<> 128:9bcdf88f62b0 403 */
<> 128:9bcdf88f62b0 404
<> 128:9bcdf88f62b0 405 /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
<> 128:9bcdf88f62b0 406 * @{
<> 128:9bcdf88f62b0 407 */
AnnaBridge 165:d1b4690b3f8b 408 #define TIM_ICPSC_DIV1 (0x0000U) /*!< Capture performed each time an edge is detected on the capture input */
<> 128:9bcdf88f62b0 409 #define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */
<> 128:9bcdf88f62b0 410 #define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */
<> 128:9bcdf88f62b0 411 #define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */
<> 128:9bcdf88f62b0 412 /**
<> 128:9bcdf88f62b0 413 * @}
<> 128:9bcdf88f62b0 414 */
<> 128:9bcdf88f62b0 415
<> 128:9bcdf88f62b0 416 /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
<> 128:9bcdf88f62b0 417 * @{
<> 128:9bcdf88f62b0 418 */
<> 128:9bcdf88f62b0 419 #define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
AnnaBridge 165:d1b4690b3f8b 420 #define TIM_OPMODE_REPETITIVE (0x0000U)
<> 128:9bcdf88f62b0 421 /**
<> 128:9bcdf88f62b0 422 * @}
<> 128:9bcdf88f62b0 423 */
<> 128:9bcdf88f62b0 424
<> 128:9bcdf88f62b0 425 /** @defgroup TIM_Encoder_Mode TIM Encoder Mode
<> 128:9bcdf88f62b0 426 * @{
<> 128:9bcdf88f62b0 427 */
<> 128:9bcdf88f62b0 428 #define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
<> 128:9bcdf88f62b0 429 #define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
<> 128:9bcdf88f62b0 430 #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
<> 128:9bcdf88f62b0 431 /**
<> 128:9bcdf88f62b0 432 * @}
<> 128:9bcdf88f62b0 433 */
<> 128:9bcdf88f62b0 434
<> 128:9bcdf88f62b0 435 /** @defgroup TIM_Interrupt_definition TIM Interrupt Definition
<> 128:9bcdf88f62b0 436 * @{
<> 128:9bcdf88f62b0 437 */
<> 128:9bcdf88f62b0 438 #define TIM_IT_UPDATE (TIM_DIER_UIE)
<> 128:9bcdf88f62b0 439 #define TIM_IT_CC1 (TIM_DIER_CC1IE)
<> 128:9bcdf88f62b0 440 #define TIM_IT_CC2 (TIM_DIER_CC2IE)
<> 128:9bcdf88f62b0 441 #define TIM_IT_CC3 (TIM_DIER_CC3IE)
<> 128:9bcdf88f62b0 442 #define TIM_IT_CC4 (TIM_DIER_CC4IE)
<> 128:9bcdf88f62b0 443 #define TIM_IT_TRIGGER (TIM_DIER_TIE)
<> 128:9bcdf88f62b0 444 /**
<> 128:9bcdf88f62b0 445 * @}
<> 128:9bcdf88f62b0 446 */
<> 128:9bcdf88f62b0 447
<> 128:9bcdf88f62b0 448 /** @defgroup TIM_DMA_sources TIM DMA Sources
<> 128:9bcdf88f62b0 449 * @{
<> 128:9bcdf88f62b0 450 */
<> 128:9bcdf88f62b0 451 #define TIM_DMA_UPDATE (TIM_DIER_UDE)
<> 128:9bcdf88f62b0 452 #define TIM_DMA_CC1 (TIM_DIER_CC1DE)
<> 128:9bcdf88f62b0 453 #define TIM_DMA_CC2 (TIM_DIER_CC2DE)
<> 128:9bcdf88f62b0 454 #define TIM_DMA_CC3 (TIM_DIER_CC3DE)
<> 128:9bcdf88f62b0 455 #define TIM_DMA_CC4 (TIM_DIER_CC4DE)
<> 128:9bcdf88f62b0 456 #define TIM_DMA_TRIGGER (TIM_DIER_TDE)
<> 128:9bcdf88f62b0 457 /**
<> 128:9bcdf88f62b0 458 * @}
<> 128:9bcdf88f62b0 459 */
<> 128:9bcdf88f62b0 460
<> 128:9bcdf88f62b0 461 /** @defgroup TIM_Event_Source TIM Event Source
<> 128:9bcdf88f62b0 462 * @{
<> 128:9bcdf88f62b0 463 */
<> 128:9bcdf88f62b0 464 #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
<> 128:9bcdf88f62b0 465 #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
<> 128:9bcdf88f62b0 466 #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
<> 128:9bcdf88f62b0 467 #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
<> 128:9bcdf88f62b0 468 #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
<> 128:9bcdf88f62b0 469 #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
<> 128:9bcdf88f62b0 470 /**
<> 128:9bcdf88f62b0 471 * @}
<> 128:9bcdf88f62b0 472 */
<> 128:9bcdf88f62b0 473
<> 128:9bcdf88f62b0 474 /** @defgroup TIM_Flag_definition TIM Flag Definition
<> 128:9bcdf88f62b0 475 * @{
<> 128:9bcdf88f62b0 476 */
<> 128:9bcdf88f62b0 477 #define TIM_FLAG_UPDATE (TIM_SR_UIF)
<> 128:9bcdf88f62b0 478 #define TIM_FLAG_CC1 (TIM_SR_CC1IF)
<> 128:9bcdf88f62b0 479 #define TIM_FLAG_CC2 (TIM_SR_CC2IF)
<> 128:9bcdf88f62b0 480 #define TIM_FLAG_CC3 (TIM_SR_CC3IF)
<> 128:9bcdf88f62b0 481 #define TIM_FLAG_CC4 (TIM_SR_CC4IF)
<> 128:9bcdf88f62b0 482 #define TIM_FLAG_TRIGGER (TIM_SR_TIF)
<> 128:9bcdf88f62b0 483 #define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
<> 128:9bcdf88f62b0 484 #define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
<> 128:9bcdf88f62b0 485 #define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
<> 128:9bcdf88f62b0 486 #define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
<> 128:9bcdf88f62b0 487 /**
<> 128:9bcdf88f62b0 488 * @}
<> 128:9bcdf88f62b0 489 */
<> 128:9bcdf88f62b0 490
<> 128:9bcdf88f62b0 491 /** @defgroup TIM_Clock_Source TIM Clock Source
<> 128:9bcdf88f62b0 492 * @{
<> 128:9bcdf88f62b0 493 */
<> 128:9bcdf88f62b0 494 #define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
<> 128:9bcdf88f62b0 495 #define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
AnnaBridge 165:d1b4690b3f8b 496 #define TIM_CLOCKSOURCE_ITR0 (0x0000U)
<> 128:9bcdf88f62b0 497 #define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
<> 128:9bcdf88f62b0 498 #define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
<> 128:9bcdf88f62b0 499 #define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
<> 128:9bcdf88f62b0 500 #define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
<> 128:9bcdf88f62b0 501 #define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
<> 128:9bcdf88f62b0 502 #define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
<> 128:9bcdf88f62b0 503 #define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
<> 128:9bcdf88f62b0 504 /**
<> 128:9bcdf88f62b0 505 * @}
<> 128:9bcdf88f62b0 506 */
<> 128:9bcdf88f62b0 507
<> 128:9bcdf88f62b0 508 /** @defgroup TIM_Clock_Polarity TIM Clock Polarity
<> 128:9bcdf88f62b0 509 * @{
<> 128:9bcdf88f62b0 510 */
<> 128:9bcdf88f62b0 511 #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */
<> 128:9bcdf88f62b0 512 #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */
<> 128:9bcdf88f62b0 513 #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */
<> 128:9bcdf88f62b0 514 #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */
<> 128:9bcdf88f62b0 515 #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */
<> 128:9bcdf88f62b0 516 /**
<> 128:9bcdf88f62b0 517 * @}
<> 128:9bcdf88f62b0 518 */
<> 128:9bcdf88f62b0 519
<> 128:9bcdf88f62b0 520 /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
<> 128:9bcdf88f62b0 521 * @{
<> 128:9bcdf88f62b0 522 */
<> 128:9bcdf88f62b0 523 #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
<> 128:9bcdf88f62b0 524 #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
<> 128:9bcdf88f62b0 525 #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
<> 128:9bcdf88f62b0 526 #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
<> 128:9bcdf88f62b0 527 /**
<> 128:9bcdf88f62b0 528 * @}
<> 128:9bcdf88f62b0 529 */
<> 128:9bcdf88f62b0 530
<> 128:9bcdf88f62b0 531 /** @defgroup TIM_ClearInput_Source TIM ClearInput Source
<> 128:9bcdf88f62b0 532 * @{
<> 128:9bcdf88f62b0 533 */
AnnaBridge 165:d1b4690b3f8b 534 #define TIM_CLEARINPUTSOURCE_ETR (0x0001U)
AnnaBridge 165:d1b4690b3f8b 535 #define TIM_CLEARINPUTSOURCE_OCREFCLR (0x0002U)
AnnaBridge 165:d1b4690b3f8b 536 #define TIM_CLEARINPUTSOURCE_NONE (0x0000U)
<> 128:9bcdf88f62b0 537 /**
<> 128:9bcdf88f62b0 538 * @}
<> 128:9bcdf88f62b0 539 */
<> 128:9bcdf88f62b0 540
<> 128:9bcdf88f62b0 541 /** @defgroup TIM_ClearInput_Polarity TIM ClearInput Polarity
<> 128:9bcdf88f62b0 542 * @{
<> 128:9bcdf88f62b0 543 */
<> 128:9bcdf88f62b0 544 #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
<> 128:9bcdf88f62b0 545 #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
<> 128:9bcdf88f62b0 546 /**
<> 128:9bcdf88f62b0 547 * @}
<> 128:9bcdf88f62b0 548 */
<> 128:9bcdf88f62b0 549
<> 128:9bcdf88f62b0 550 /** @defgroup TIM_ClearInput_Prescaler TIM ClearInput Prescaler
<> 128:9bcdf88f62b0 551 * @{
<> 128:9bcdf88f62b0 552 */
<> 128:9bcdf88f62b0 553 #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
<> 128:9bcdf88f62b0 554 #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
<> 128:9bcdf88f62b0 555 #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
<> 128:9bcdf88f62b0 556 #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
<> 128:9bcdf88f62b0 557 /**
<> 128:9bcdf88f62b0 558 * @}
<> 128:9bcdf88f62b0 559 */
<> 128:9bcdf88f62b0 560
<> 128:9bcdf88f62b0 561 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR Off State Selection for Run mode state
<> 128:9bcdf88f62b0 562 * @{
<> 128:9bcdf88f62b0 563 */
<> 128:9bcdf88f62b0 564 #define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
AnnaBridge 165:d1b4690b3f8b 565 #define TIM_OSSR_DISABLE (0x0000U)
<> 128:9bcdf88f62b0 566 /**
<> 128:9bcdf88f62b0 567 * @}
<> 128:9bcdf88f62b0 568 */
<> 128:9bcdf88f62b0 569
<> 128:9bcdf88f62b0 570 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI Off State Selection for Idle mode state
<> 128:9bcdf88f62b0 571 * @{
<> 128:9bcdf88f62b0 572 */
<> 128:9bcdf88f62b0 573 #define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
AnnaBridge 165:d1b4690b3f8b 574 #define TIM_OSSI_DISABLE (0x0000U)
<> 128:9bcdf88f62b0 575 /**
<> 128:9bcdf88f62b0 576 * @}
<> 128:9bcdf88f62b0 577 */
<> 128:9bcdf88f62b0 578
<> 128:9bcdf88f62b0 579 /** @defgroup TIM_Lock_level TIM Lock level
<> 128:9bcdf88f62b0 580 * @{
<> 128:9bcdf88f62b0 581 */
AnnaBridge 165:d1b4690b3f8b 582 #define TIM_LOCKLEVEL_OFF (0x0000U)
AnnaBridge 165:d1b4690b3f8b 583 #define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
AnnaBridge 165:d1b4690b3f8b 584 #define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
AnnaBridge 165:d1b4690b3f8b 585 #define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
<> 128:9bcdf88f62b0 586 /**
<> 128:9bcdf88f62b0 587 * @}
<> 128:9bcdf88f62b0 588 */
<> 128:9bcdf88f62b0 589
<> 128:9bcdf88f62b0 590 /** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
<> 128:9bcdf88f62b0 591 * @{
<> 128:9bcdf88f62b0 592 */
<> 128:9bcdf88f62b0 593 #define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
AnnaBridge 165:d1b4690b3f8b 594 #define TIM_AUTOMATICOUTPUT_DISABLE (0x0000U)
<> 128:9bcdf88f62b0 595 /**
<> 128:9bcdf88f62b0 596 * @}
<> 128:9bcdf88f62b0 597 */
<> 128:9bcdf88f62b0 598
<> 128:9bcdf88f62b0 599 /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
<> 128:9bcdf88f62b0 600 * @{
<> 128:9bcdf88f62b0 601 */
AnnaBridge 165:d1b4690b3f8b 602 #define TIM_TRGO_RESET (0x0000U)
<> 128:9bcdf88f62b0 603 #define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
<> 128:9bcdf88f62b0 604 #define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
<> 128:9bcdf88f62b0 605 #define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
<> 128:9bcdf88f62b0 606 #define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
<> 128:9bcdf88f62b0 607 #define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
<> 128:9bcdf88f62b0 608 #define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
<> 128:9bcdf88f62b0 609 #define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
<> 128:9bcdf88f62b0 610 /**
<> 128:9bcdf88f62b0 611 * @}
<> 128:9bcdf88f62b0 612 */
<> 128:9bcdf88f62b0 613
<> 128:9bcdf88f62b0 614 /** @defgroup TIM_Slave_Mode TIM Slave Mode
<> 128:9bcdf88f62b0 615 * @{
<> 128:9bcdf88f62b0 616 */
AnnaBridge 165:d1b4690b3f8b 617 #define TIM_SLAVEMODE_DISABLE (0x0000U)
AnnaBridge 165:d1b4690b3f8b 618 #define TIM_SLAVEMODE_RESET (0x0004U)
AnnaBridge 165:d1b4690b3f8b 619 #define TIM_SLAVEMODE_GATED (0x0005U)
AnnaBridge 165:d1b4690b3f8b 620 #define TIM_SLAVEMODE_TRIGGER (0x0006U)
AnnaBridge 165:d1b4690b3f8b 621 #define TIM_SLAVEMODE_EXTERNAL1 (0x0007U)
<> 128:9bcdf88f62b0 622 /**
<> 128:9bcdf88f62b0 623 * @}
<> 128:9bcdf88f62b0 624 */
<> 128:9bcdf88f62b0 625
<> 128:9bcdf88f62b0 626 /** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode
<> 128:9bcdf88f62b0 627 * @{
<> 128:9bcdf88f62b0 628 */
AnnaBridge 165:d1b4690b3f8b 629 #define TIM_MASTERSLAVEMODE_ENABLE (0x0080U)
AnnaBridge 165:d1b4690b3f8b 630 #define TIM_MASTERSLAVEMODE_DISABLE (0x0000U)
<> 128:9bcdf88f62b0 631 /**
<> 128:9bcdf88f62b0 632 * @}
<> 128:9bcdf88f62b0 633 */
<> 128:9bcdf88f62b0 634
<> 128:9bcdf88f62b0 635 /** @defgroup TIM_Trigger_Selection TIM Trigger Selection
<> 128:9bcdf88f62b0 636 * @{
<> 128:9bcdf88f62b0 637 */
AnnaBridge 165:d1b4690b3f8b 638 #define TIM_TS_ITR0 (0x0000U)
AnnaBridge 165:d1b4690b3f8b 639 #define TIM_TS_ITR1 (0x0010U)
AnnaBridge 165:d1b4690b3f8b 640 #define TIM_TS_ITR2 (0x0020U)
AnnaBridge 165:d1b4690b3f8b 641 #define TIM_TS_ITR3 (0x0030U)
AnnaBridge 165:d1b4690b3f8b 642 #define TIM_TS_TI1F_ED (0x0040U)
AnnaBridge 165:d1b4690b3f8b 643 #define TIM_TS_TI1FP1 (0x0050U)
AnnaBridge 165:d1b4690b3f8b 644 #define TIM_TS_TI2FP2 (0x0060U)
AnnaBridge 165:d1b4690b3f8b 645 #define TIM_TS_ETRF (0x0070U)
AnnaBridge 165:d1b4690b3f8b 646 #define TIM_TS_NONE (0xFFFFU)
<> 128:9bcdf88f62b0 647 /**
<> 128:9bcdf88f62b0 648 * @}
<> 128:9bcdf88f62b0 649 */
<> 128:9bcdf88f62b0 650
<> 128:9bcdf88f62b0 651 /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
<> 128:9bcdf88f62b0 652 * @{
<> 128:9bcdf88f62b0 653 */
<> 128:9bcdf88f62b0 654 #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */
<> 128:9bcdf88f62b0 655 #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */
<> 128:9bcdf88f62b0 656 #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
<> 128:9bcdf88f62b0 657 #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
<> 128:9bcdf88f62b0 658 #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */
<> 128:9bcdf88f62b0 659 /**
<> 128:9bcdf88f62b0 660 * @}
<> 128:9bcdf88f62b0 661 */
<> 128:9bcdf88f62b0 662
<> 128:9bcdf88f62b0 663 /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
<> 128:9bcdf88f62b0 664 * @{
<> 128:9bcdf88f62b0 665 */
<> 128:9bcdf88f62b0 666 #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
<> 128:9bcdf88f62b0 667 #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
<> 128:9bcdf88f62b0 668 #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
<> 128:9bcdf88f62b0 669 #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
<> 128:9bcdf88f62b0 670 /**
<> 128:9bcdf88f62b0 671 * @}
<> 128:9bcdf88f62b0 672 */
<> 128:9bcdf88f62b0 673
<> 128:9bcdf88f62b0 674 /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
<> 128:9bcdf88f62b0 675 * @{
<> 128:9bcdf88f62b0 676 */
AnnaBridge 165:d1b4690b3f8b 677 #define TIM_TI1SELECTION_CH1 (0x0000U)
<> 128:9bcdf88f62b0 678 #define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
<> 128:9bcdf88f62b0 679 /**
<> 128:9bcdf88f62b0 680 * @}
<> 128:9bcdf88f62b0 681 */
<> 128:9bcdf88f62b0 682
<> 128:9bcdf88f62b0 683 /** @defgroup TIM_DMA_Base_address TIM DMA Base Address
<> 128:9bcdf88f62b0 684 * @{
<> 128:9bcdf88f62b0 685 */
AnnaBridge 165:d1b4690b3f8b 686 #define TIM_DMABASE_CR1 (0x00000000U)
AnnaBridge 165:d1b4690b3f8b 687 #define TIM_DMABASE_CR2 (0x00000001U)
AnnaBridge 165:d1b4690b3f8b 688 #define TIM_DMABASE_SMCR (0x00000002U)
AnnaBridge 165:d1b4690b3f8b 689 #define TIM_DMABASE_DIER (0x00000003U)
AnnaBridge 165:d1b4690b3f8b 690 #define TIM_DMABASE_SR (0x00000004U)
AnnaBridge 165:d1b4690b3f8b 691 #define TIM_DMABASE_EGR (0x00000005U)
AnnaBridge 165:d1b4690b3f8b 692 #define TIM_DMABASE_CCMR1 (0x00000006U)
AnnaBridge 165:d1b4690b3f8b 693 #define TIM_DMABASE_CCMR2 (0x00000007U)
AnnaBridge 165:d1b4690b3f8b 694 #define TIM_DMABASE_CCER (0x00000008U)
AnnaBridge 165:d1b4690b3f8b 695 #define TIM_DMABASE_CNT (0x00000009U)
AnnaBridge 165:d1b4690b3f8b 696 #define TIM_DMABASE_PSC (0x0000000AU)
AnnaBridge 165:d1b4690b3f8b 697 #define TIM_DMABASE_ARR (0x0000000BU)
AnnaBridge 165:d1b4690b3f8b 698 #define TIM_DMABASE_CCR1 (0x0000000DU)
AnnaBridge 165:d1b4690b3f8b 699 #define TIM_DMABASE_CCR2 (0x0000000EU)
AnnaBridge 165:d1b4690b3f8b 700 #define TIM_DMABASE_CCR3 (0x0000000FU)
AnnaBridge 165:d1b4690b3f8b 701 #define TIM_DMABASE_CCR4 (0x00000010U)
AnnaBridge 165:d1b4690b3f8b 702 #define TIM_DMABASE_DCR (0x00000012U)
AnnaBridge 165:d1b4690b3f8b 703 #define TIM_DMABASE_OR (0x00000013U)
<> 128:9bcdf88f62b0 704 /**
<> 128:9bcdf88f62b0 705 * @}
<> 128:9bcdf88f62b0 706 */
<> 128:9bcdf88f62b0 707
<> 128:9bcdf88f62b0 708 /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
<> 128:9bcdf88f62b0 709 * @{
<> 128:9bcdf88f62b0 710 */
<> 128:9bcdf88f62b0 711 #define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000)
<> 128:9bcdf88f62b0 712 #define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100)
<> 128:9bcdf88f62b0 713 #define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200)
<> 128:9bcdf88f62b0 714 #define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300)
<> 128:9bcdf88f62b0 715 #define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400)
<> 128:9bcdf88f62b0 716 #define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500)
<> 128:9bcdf88f62b0 717 #define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600)
<> 128:9bcdf88f62b0 718 #define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700)
<> 128:9bcdf88f62b0 719 #define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800)
<> 128:9bcdf88f62b0 720 #define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900)
<> 128:9bcdf88f62b0 721 #define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00)
<> 128:9bcdf88f62b0 722 #define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00)
<> 128:9bcdf88f62b0 723 #define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00)
<> 128:9bcdf88f62b0 724 #define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00)
<> 128:9bcdf88f62b0 725 #define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00)
<> 128:9bcdf88f62b0 726 #define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00)
<> 128:9bcdf88f62b0 727 #define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000)
<> 128:9bcdf88f62b0 728 #define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100)
<> 128:9bcdf88f62b0 729 /**
<> 128:9bcdf88f62b0 730 * @}
<> 128:9bcdf88f62b0 731 */
<> 128:9bcdf88f62b0 732
<> 128:9bcdf88f62b0 733 /** @defgroup TIM_DMA_Handle_index TIM DMA Handle Index
<> 128:9bcdf88f62b0 734 * @{
<> 128:9bcdf88f62b0 735 */
<> 128:9bcdf88f62b0 736 #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /*!< Index of the DMA handle used for Update DMA requests */
<> 128:9bcdf88f62b0 737 #define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
<> 128:9bcdf88f62b0 738 #define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
<> 128:9bcdf88f62b0 739 #define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
<> 128:9bcdf88f62b0 740 #define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
<> 128:9bcdf88f62b0 741 #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6) /*!< Index of the DMA handle used for Trigger DMA requests */
<> 128:9bcdf88f62b0 742 /**
<> 128:9bcdf88f62b0 743 * @}
<> 128:9bcdf88f62b0 744 */
<> 128:9bcdf88f62b0 745
<> 128:9bcdf88f62b0 746 /** @defgroup TIM_Channel_CC_State TIM Capture/Compare Channel State
<> 128:9bcdf88f62b0 747 * @{
<> 128:9bcdf88f62b0 748 */
AnnaBridge 165:d1b4690b3f8b 749 #define TIM_CCx_ENABLE (0x0001U)
AnnaBridge 165:d1b4690b3f8b 750 #define TIM_CCx_DISABLE (0x0000U)
<> 128:9bcdf88f62b0 751 /**
<> 128:9bcdf88f62b0 752 * @}
<> 128:9bcdf88f62b0 753 */
<> 128:9bcdf88f62b0 754
<> 128:9bcdf88f62b0 755 /**
<> 128:9bcdf88f62b0 756 * @}
<> 128:9bcdf88f62b0 757 */
<> 128:9bcdf88f62b0 758
<> 128:9bcdf88f62b0 759 /* Private Constants -----------------------------------------------------------*/
<> 128:9bcdf88f62b0 760 /** @defgroup TIM_Private_Constants TIM Private Constants
<> 128:9bcdf88f62b0 761 * @{
<> 128:9bcdf88f62b0 762 */
<> 128:9bcdf88f62b0 763
<> 128:9bcdf88f62b0 764 /* The counter of a timer instance is disabled only if all the CCx
<> 128:9bcdf88f62b0 765 channels have been disabled */
<> 128:9bcdf88f62b0 766 #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
<> 128:9bcdf88f62b0 767 /**
<> 128:9bcdf88f62b0 768 * @}
<> 128:9bcdf88f62b0 769 */
<> 128:9bcdf88f62b0 770
<> 128:9bcdf88f62b0 771 /* Private Macros -----------------------------------------------------------*/
<> 128:9bcdf88f62b0 772 /** @defgroup TIM_Private_Macros TIM Private Macros
<> 128:9bcdf88f62b0 773 * @{
<> 128:9bcdf88f62b0 774 */
<> 128:9bcdf88f62b0 775
<> 128:9bcdf88f62b0 776 #define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) || \
<> 128:9bcdf88f62b0 777 ((MODE) == TIM_COUNTERMODE_DOWN) || \
<> 128:9bcdf88f62b0 778 ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) || \
<> 128:9bcdf88f62b0 779 ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) || \
<> 128:9bcdf88f62b0 780 ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
<> 128:9bcdf88f62b0 781
<> 128:9bcdf88f62b0 782 #define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \
<> 128:9bcdf88f62b0 783 ((DIV) == TIM_CLOCKDIVISION_DIV2) || \
<> 128:9bcdf88f62b0 784 ((DIV) == TIM_CLOCKDIVISION_DIV4))
<> 128:9bcdf88f62b0 785
<> 128:9bcdf88f62b0 786 #define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \
<> 128:9bcdf88f62b0 787 ((MODE) == TIM_OCMODE_PWM2))
<> 128:9bcdf88f62b0 788
<> 128:9bcdf88f62b0 789 #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \
<> 128:9bcdf88f62b0 790 ((MODE) == TIM_OCMODE_ACTIVE) || \
<> 128:9bcdf88f62b0 791 ((MODE) == TIM_OCMODE_INACTIVE) || \
<> 128:9bcdf88f62b0 792 ((MODE) == TIM_OCMODE_TOGGLE) || \
<> 128:9bcdf88f62b0 793 ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \
<> 128:9bcdf88f62b0 794 ((MODE) == TIM_OCMODE_FORCED_INACTIVE))
<> 128:9bcdf88f62b0 795
<> 128:9bcdf88f62b0 796 #define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \
<> 128:9bcdf88f62b0 797 ((STATE) == TIM_OCFAST_ENABLE))
<> 128:9bcdf88f62b0 798
<> 128:9bcdf88f62b0 799 #define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \
<> 128:9bcdf88f62b0 800 ((POLARITY) == TIM_OCPOLARITY_LOW))
<> 128:9bcdf88f62b0 801
<> 128:9bcdf88f62b0 802 #define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \
<> 128:9bcdf88f62b0 803 ((STATE) == TIM_OCIDLESTATE_RESET))
<> 128:9bcdf88f62b0 804
<> 128:9bcdf88f62b0 805 #define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
<> 128:9bcdf88f62b0 806 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 128:9bcdf88f62b0 807 ((CHANNEL) == TIM_CHANNEL_3) || \
<> 128:9bcdf88f62b0 808 ((CHANNEL) == TIM_CHANNEL_4) || \
<> 128:9bcdf88f62b0 809 ((CHANNEL) == TIM_CHANNEL_ALL))
<> 128:9bcdf88f62b0 810
<> 128:9bcdf88f62b0 811 #define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
<> 128:9bcdf88f62b0 812 ((CHANNEL) == TIM_CHANNEL_2))
<> 128:9bcdf88f62b0 813
<> 128:9bcdf88f62b0 814 #define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) || \
<> 128:9bcdf88f62b0 815 ((POLARITY) == TIM_ICPOLARITY_FALLING) || \
<> 128:9bcdf88f62b0 816 ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
<> 128:9bcdf88f62b0 817
<> 128:9bcdf88f62b0 818 #define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \
<> 128:9bcdf88f62b0 819 ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \
<> 128:9bcdf88f62b0 820 ((SELECTION) == TIM_ICSELECTION_TRC))
<> 128:9bcdf88f62b0 821
<> 128:9bcdf88f62b0 822 #define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
<> 128:9bcdf88f62b0 823 ((PRESCALER) == TIM_ICPSC_DIV2) || \
<> 128:9bcdf88f62b0 824 ((PRESCALER) == TIM_ICPSC_DIV4) || \
<> 128:9bcdf88f62b0 825 ((PRESCALER) == TIM_ICPSC_DIV8))
<> 128:9bcdf88f62b0 826
<> 128:9bcdf88f62b0 827 #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \
<> 128:9bcdf88f62b0 828 ((MODE) == TIM_OPMODE_REPETITIVE))
<> 128:9bcdf88f62b0 829
<> 128:9bcdf88f62b0 830 #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \
<> 128:9bcdf88f62b0 831 ((MODE) == TIM_ENCODERMODE_TI2) || \
<> 128:9bcdf88f62b0 832 ((MODE) == TIM_ENCODERMODE_TI12))
<> 128:9bcdf88f62b0 833
<> 128:9bcdf88f62b0 834 #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FFU) == 0x00000000U) && ((SOURCE) != 0x00000000U))
<> 128:9bcdf88f62b0 835
<> 128:9bcdf88f62b0 836 #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00U) == 0x00000000U) && ((SOURCE) != 0x00000000U))
<> 128:9bcdf88f62b0 837
<> 128:9bcdf88f62b0 838 #define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \
<> 128:9bcdf88f62b0 839 ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \
<> 128:9bcdf88f62b0 840 ((CLOCK) == TIM_CLOCKSOURCE_ITR0) || \
<> 128:9bcdf88f62b0 841 ((CLOCK) == TIM_CLOCKSOURCE_ITR1) || \
<> 128:9bcdf88f62b0 842 ((CLOCK) == TIM_CLOCKSOURCE_ITR2) || \
<> 128:9bcdf88f62b0 843 ((CLOCK) == TIM_CLOCKSOURCE_ITR3) || \
<> 128:9bcdf88f62b0 844 ((CLOCK) == TIM_CLOCKSOURCE_TI1ED) || \
<> 128:9bcdf88f62b0 845 ((CLOCK) == TIM_CLOCKSOURCE_TI1) || \
<> 128:9bcdf88f62b0 846 ((CLOCK) == TIM_CLOCKSOURCE_TI2) || \
<> 128:9bcdf88f62b0 847 ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
<> 128:9bcdf88f62b0 848
<> 128:9bcdf88f62b0 849 #define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) || \
<> 128:9bcdf88f62b0 850 ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \
<> 128:9bcdf88f62b0 851 ((POLARITY) == TIM_CLOCKPOLARITY_RISING) || \
<> 128:9bcdf88f62b0 852 ((POLARITY) == TIM_CLOCKPOLARITY_FALLING) || \
<> 128:9bcdf88f62b0 853 ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
<> 128:9bcdf88f62b0 854
<> 128:9bcdf88f62b0 855 #define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \
<> 128:9bcdf88f62b0 856 ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \
<> 128:9bcdf88f62b0 857 ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \
<> 128:9bcdf88f62b0 858 ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
<> 128:9bcdf88f62b0 859
<> 128:9bcdf88f62b0 860 #define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF)
<> 128:9bcdf88f62b0 861
<> 128:9bcdf88f62b0 862 #define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_ETR) || \
<> 128:9bcdf88f62b0 863 ((SOURCE) == TIM_CLEARINPUTSOURCE_OCREFCLR) || \
<> 128:9bcdf88f62b0 864 ((SOURCE) == TIM_CLEARINPUTSOURCE_NONE))
<> 128:9bcdf88f62b0 865
<> 128:9bcdf88f62b0 866 #define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
<> 128:9bcdf88f62b0 867 ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
<> 128:9bcdf88f62b0 868
<> 128:9bcdf88f62b0 869 #define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \
<> 128:9bcdf88f62b0 870 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \
<> 128:9bcdf88f62b0 871 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \
<> 128:9bcdf88f62b0 872 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
<> 128:9bcdf88f62b0 873
<> 128:9bcdf88f62b0 874 #define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
<> 128:9bcdf88f62b0 875
<> 128:9bcdf88f62b0 876 #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \
<> 128:9bcdf88f62b0 877 ((STATE) == TIM_OSSR_DISABLE))
<> 128:9bcdf88f62b0 878
<> 128:9bcdf88f62b0 879 #define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \
<> 128:9bcdf88f62b0 880 ((STATE) == TIM_OSSI_DISABLE))
<> 128:9bcdf88f62b0 881
<> 128:9bcdf88f62b0 882 #define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \
<> 128:9bcdf88f62b0 883 ((LEVEL) == TIM_LOCKLEVEL_1) || \
<> 128:9bcdf88f62b0 884 ((LEVEL) == TIM_LOCKLEVEL_2) || \
<> 128:9bcdf88f62b0 885 ((LEVEL) == TIM_LOCKLEVEL_3))
<> 128:9bcdf88f62b0 886
<> 128:9bcdf88f62b0 887 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \
<> 128:9bcdf88f62b0 888 ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
<> 128:9bcdf88f62b0 889
<> 128:9bcdf88f62b0 890 #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \
<> 128:9bcdf88f62b0 891 ((SOURCE) == TIM_TRGO_ENABLE) || \
<> 128:9bcdf88f62b0 892 ((SOURCE) == TIM_TRGO_UPDATE) || \
<> 128:9bcdf88f62b0 893 ((SOURCE) == TIM_TRGO_OC1) || \
<> 128:9bcdf88f62b0 894 ((SOURCE) == TIM_TRGO_OC1REF) || \
<> 128:9bcdf88f62b0 895 ((SOURCE) == TIM_TRGO_OC2REF) || \
<> 128:9bcdf88f62b0 896 ((SOURCE) == TIM_TRGO_OC3REF) || \
<> 128:9bcdf88f62b0 897 ((SOURCE) == TIM_TRGO_OC4REF))
<> 128:9bcdf88f62b0 898
<> 128:9bcdf88f62b0 899 #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \
<> 128:9bcdf88f62b0 900 ((MODE) == TIM_SLAVEMODE_GATED) || \
<> 128:9bcdf88f62b0 901 ((MODE) == TIM_SLAVEMODE_RESET) || \
<> 128:9bcdf88f62b0 902 ((MODE) == TIM_SLAVEMODE_TRIGGER) || \
<> 128:9bcdf88f62b0 903 ((MODE) == TIM_SLAVEMODE_EXTERNAL1))
<> 128:9bcdf88f62b0 904
<> 128:9bcdf88f62b0 905 #define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \
<> 128:9bcdf88f62b0 906 ((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
<> 128:9bcdf88f62b0 907
<> 128:9bcdf88f62b0 908 #define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
<> 128:9bcdf88f62b0 909 ((SELECTION) == TIM_TS_ITR1) || \
<> 128:9bcdf88f62b0 910 ((SELECTION) == TIM_TS_ITR2) || \
<> 128:9bcdf88f62b0 911 ((SELECTION) == TIM_TS_ITR3) || \
<> 128:9bcdf88f62b0 912 ((SELECTION) == TIM_TS_TI1F_ED) || \
<> 128:9bcdf88f62b0 913 ((SELECTION) == TIM_TS_TI1FP1) || \
<> 128:9bcdf88f62b0 914 ((SELECTION) == TIM_TS_TI2FP2) || \
<> 128:9bcdf88f62b0 915 ((SELECTION) == TIM_TS_ETRF))
<> 128:9bcdf88f62b0 916
<> 128:9bcdf88f62b0 917 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
<> 128:9bcdf88f62b0 918 ((SELECTION) == TIM_TS_ITR1) || \
<> 128:9bcdf88f62b0 919 ((SELECTION) == TIM_TS_ITR2) || \
<> 128:9bcdf88f62b0 920 ((SELECTION) == TIM_TS_ITR3) || \
<> 128:9bcdf88f62b0 921 ((SELECTION) == TIM_TS_NONE))
<> 128:9bcdf88f62b0 922
<> 128:9bcdf88f62b0 923 #define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) || \
<> 128:9bcdf88f62b0 924 ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
<> 128:9bcdf88f62b0 925 ((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) || \
<> 128:9bcdf88f62b0 926 ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) || \
<> 128:9bcdf88f62b0 927 ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
<> 128:9bcdf88f62b0 928
<> 128:9bcdf88f62b0 929 #define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \
<> 128:9bcdf88f62b0 930 ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \
<> 128:9bcdf88f62b0 931 ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \
<> 128:9bcdf88f62b0 932 ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
<> 128:9bcdf88f62b0 933
<> 128:9bcdf88f62b0 934 #define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xF)
<> 128:9bcdf88f62b0 935
<> 128:9bcdf88f62b0 936 #define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \
<> 128:9bcdf88f62b0 937 ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
<> 128:9bcdf88f62b0 938
<> 128:9bcdf88f62b0 939 #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) || \
<> 128:9bcdf88f62b0 940 ((BASE) == TIM_DMABASE_CR2) || \
<> 128:9bcdf88f62b0 941 ((BASE) == TIM_DMABASE_SMCR) || \
<> 128:9bcdf88f62b0 942 ((BASE) == TIM_DMABASE_DIER) || \
<> 128:9bcdf88f62b0 943 ((BASE) == TIM_DMABASE_SR) || \
<> 128:9bcdf88f62b0 944 ((BASE) == TIM_DMABASE_EGR) || \
<> 128:9bcdf88f62b0 945 ((BASE) == TIM_DMABASE_CCMR1) || \
<> 128:9bcdf88f62b0 946 ((BASE) == TIM_DMABASE_CCMR2) || \
<> 128:9bcdf88f62b0 947 ((BASE) == TIM_DMABASE_CCER) || \
<> 128:9bcdf88f62b0 948 ((BASE) == TIM_DMABASE_CNT) || \
<> 128:9bcdf88f62b0 949 ((BASE) == TIM_DMABASE_PSC) || \
<> 128:9bcdf88f62b0 950 ((BASE) == TIM_DMABASE_ARR) || \
<> 128:9bcdf88f62b0 951 ((BASE) == TIM_DMABASE_CCR1) || \
<> 128:9bcdf88f62b0 952 ((BASE) == TIM_DMABASE_CCR2) || \
<> 128:9bcdf88f62b0 953 ((BASE) == TIM_DMABASE_CCR3) || \
<> 128:9bcdf88f62b0 954 ((BASE) == TIM_DMABASE_CCR4) || \
<> 128:9bcdf88f62b0 955 ((BASE) == TIM_DMABASE_DCR) || \
<> 128:9bcdf88f62b0 956 ((BASE) == TIM_DMABASE_OR))
<> 128:9bcdf88f62b0 957
<> 128:9bcdf88f62b0 958 #define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER) || \
<> 128:9bcdf88f62b0 959 ((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
<> 128:9bcdf88f62b0 960 ((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
<> 128:9bcdf88f62b0 961 ((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
<> 128:9bcdf88f62b0 962 ((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
<> 128:9bcdf88f62b0 963 ((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
<> 128:9bcdf88f62b0 964 ((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
<> 128:9bcdf88f62b0 965 ((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
<> 128:9bcdf88f62b0 966 ((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
<> 128:9bcdf88f62b0 967 ((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
<> 128:9bcdf88f62b0 968 ((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
<> 128:9bcdf88f62b0 969 ((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
<> 128:9bcdf88f62b0 970 ((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
<> 128:9bcdf88f62b0 971 ((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
<> 128:9bcdf88f62b0 972 ((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
<> 128:9bcdf88f62b0 973 ((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
<> 128:9bcdf88f62b0 974 ((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
<> 128:9bcdf88f62b0 975 ((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS))
<> 128:9bcdf88f62b0 976
<> 128:9bcdf88f62b0 977 #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
<> 128:9bcdf88f62b0 978
<> 128:9bcdf88f62b0 979 /** @brief Set TIM IC prescaler
<> 128:9bcdf88f62b0 980 * @param __HANDLE__: TIM handle
<> 128:9bcdf88f62b0 981 * @param __CHANNEL__: specifies TIM Channel
<> 128:9bcdf88f62b0 982 * @param __ICPSC__: specifies the prescaler value.
<> 128:9bcdf88f62b0 983 * @retval None
<> 128:9bcdf88f62b0 984 */
<> 128:9bcdf88f62b0 985 #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
<> 128:9bcdf88f62b0 986 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
<> 128:9bcdf88f62b0 987 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\
<> 128:9bcdf88f62b0 988 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
<> 128:9bcdf88f62b0 989 ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8)))
<> 128:9bcdf88f62b0 990
<> 128:9bcdf88f62b0 991 /** @brief Reset TIM IC prescaler
<> 128:9bcdf88f62b0 992 * @param __HANDLE__: TIM handle
<> 128:9bcdf88f62b0 993 * @param __CHANNEL__: specifies TIM Channel
<> 128:9bcdf88f62b0 994 * @retval None
<> 128:9bcdf88f62b0 995 */
<> 128:9bcdf88f62b0 996 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
<> 128:9bcdf88f62b0 997 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
<> 128:9bcdf88f62b0 998 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
<> 128:9bcdf88f62b0 999 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
<> 128:9bcdf88f62b0 1000 ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
<> 128:9bcdf88f62b0 1001
<> 128:9bcdf88f62b0 1002
<> 128:9bcdf88f62b0 1003 /** @brief Set TIM IC polarity
<> 128:9bcdf88f62b0 1004 * @param __HANDLE__: TIM handle
<> 128:9bcdf88f62b0 1005 * @param __CHANNEL__: specifies TIM Channel
<> 128:9bcdf88f62b0 1006 * @param __POLARITY__: specifies TIM Channel Polarity
<> 128:9bcdf88f62b0 1007 * @retval None
<> 128:9bcdf88f62b0 1008 */
<> 128:9bcdf88f62b0 1009 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
<> 128:9bcdf88f62b0 1010 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
<> 128:9bcdf88f62b0 1011 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4)) :\
<> 128:9bcdf88f62b0 1012 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8)) :\
<> 128:9bcdf88f62b0 1013 ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12) & TIM_CCER_CC4P)))
<> 128:9bcdf88f62b0 1014
<> 128:9bcdf88f62b0 1015 /** @brief Reset TIM IC polarity
<> 128:9bcdf88f62b0 1016 * @param __HANDLE__: TIM handle
<> 128:9bcdf88f62b0 1017 * @param __CHANNEL__: specifies TIM Channel
<> 128:9bcdf88f62b0 1018 * @retval None
<> 128:9bcdf88f62b0 1019 */
<> 128:9bcdf88f62b0 1020 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
<> 128:9bcdf88f62b0 1021 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
<> 128:9bcdf88f62b0 1022 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
<> 128:9bcdf88f62b0 1023 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
<> 128:9bcdf88f62b0 1024 ((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P))
<> 128:9bcdf88f62b0 1025
<> 128:9bcdf88f62b0 1026 /**
<> 128:9bcdf88f62b0 1027 * @}
<> 128:9bcdf88f62b0 1028 */
<> 128:9bcdf88f62b0 1029
<> 128:9bcdf88f62b0 1030 /* Private Functions --------------------------------------------------------*/
<> 128:9bcdf88f62b0 1031
<> 128:9bcdf88f62b0 1032 /* Exported macros -----------------------------------------------------------*/
<> 128:9bcdf88f62b0 1033 /** @defgroup TIM_Exported_Macros TIM Exported Macros
<> 128:9bcdf88f62b0 1034 * @{
<> 128:9bcdf88f62b0 1035 */
<> 128:9bcdf88f62b0 1036
<> 128:9bcdf88f62b0 1037 /** @brief Reset TIM handle state
<> 128:9bcdf88f62b0 1038 * @param __HANDLE__: TIM handle.
<> 128:9bcdf88f62b0 1039 * @retval None
<> 128:9bcdf88f62b0 1040 */
<> 128:9bcdf88f62b0 1041 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
<> 128:9bcdf88f62b0 1042
<> 128:9bcdf88f62b0 1043 /**
<> 128:9bcdf88f62b0 1044 * @brief Enable the TIM peripheral.
<> 128:9bcdf88f62b0 1045 * @param __HANDLE__: TIM handle
<> 128:9bcdf88f62b0 1046 * @retval None
<> 128:9bcdf88f62b0 1047 */
<> 128:9bcdf88f62b0 1048 #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
<> 128:9bcdf88f62b0 1049
<> 128:9bcdf88f62b0 1050 /**
<> 128:9bcdf88f62b0 1051 * @brief Disable the TIM peripheral.
<> 128:9bcdf88f62b0 1052 * @param __HANDLE__: TIM handle
<> 128:9bcdf88f62b0 1053 * @retval None
<> 128:9bcdf88f62b0 1054 */
<> 128:9bcdf88f62b0 1055 #define __HAL_TIM_DISABLE(__HANDLE__) \
<> 128:9bcdf88f62b0 1056 do { \
<> 128:9bcdf88f62b0 1057 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
<> 128:9bcdf88f62b0 1058 { \
<> 128:9bcdf88f62b0 1059 (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
<> 128:9bcdf88f62b0 1060 } \
<> 128:9bcdf88f62b0 1061 } while(0)
<> 128:9bcdf88f62b0 1062
<> 128:9bcdf88f62b0 1063 /**
<> 128:9bcdf88f62b0 1064 * @brief Enables the specified TIM interrupt.
<> 128:9bcdf88f62b0 1065 * @param __HANDLE__: specifies the TIM Handle.
<> 128:9bcdf88f62b0 1066 * @param __INTERRUPT__: specifies the TIM interrupt source to enable.
<> 128:9bcdf88f62b0 1067 * This parameter can be one of the following values:
<> 128:9bcdf88f62b0 1068 * @arg TIM_IT_UPDATE: Update interrupt
<> 128:9bcdf88f62b0 1069 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
<> 128:9bcdf88f62b0 1070 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
<> 128:9bcdf88f62b0 1071 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
<> 128:9bcdf88f62b0 1072 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
<> 128:9bcdf88f62b0 1073 * @arg TIM_IT_COM: Commutation interrupt
<> 128:9bcdf88f62b0 1074 * @arg TIM_IT_TRIGGER: Trigger interrupt
<> 128:9bcdf88f62b0 1075 * @retval None
<> 128:9bcdf88f62b0 1076 */
<> 128:9bcdf88f62b0 1077 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
<> 128:9bcdf88f62b0 1078
<> 128:9bcdf88f62b0 1079 /**
<> 128:9bcdf88f62b0 1080 * @brief Disables the specified TIM interrupt.
<> 128:9bcdf88f62b0 1081 * @param __HANDLE__: specifies the TIM Handle.
<> 128:9bcdf88f62b0 1082 * @param __INTERRUPT__: specifies the TIM interrupt source to disable.
<> 128:9bcdf88f62b0 1083 * This parameter can be one of the following values:
<> 128:9bcdf88f62b0 1084 * @arg TIM_IT_UPDATE: Update interrupt
<> 128:9bcdf88f62b0 1085 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
<> 128:9bcdf88f62b0 1086 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
<> 128:9bcdf88f62b0 1087 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
<> 128:9bcdf88f62b0 1088 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
<> 128:9bcdf88f62b0 1089 * @arg TIM_IT_COM: Commutation interrupt
<> 128:9bcdf88f62b0 1090 * @arg TIM_IT_TRIGGER: Trigger interrupt
<> 128:9bcdf88f62b0 1091 * @retval None
<> 128:9bcdf88f62b0 1092 */
<> 128:9bcdf88f62b0 1093 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
<> 128:9bcdf88f62b0 1094
<> 128:9bcdf88f62b0 1095 /**
<> 128:9bcdf88f62b0 1096 * @brief Enables the specified DMA request.
<> 128:9bcdf88f62b0 1097 * @param __HANDLE__: specifies the TIM Handle.
<> 128:9bcdf88f62b0 1098 * @param __DMA__: specifies the TIM DMA request to enable.
<> 128:9bcdf88f62b0 1099 * This parameter can be one of the following values:
<> 128:9bcdf88f62b0 1100 * @arg TIM_DMA_UPDATE: Update DMA request
<> 128:9bcdf88f62b0 1101 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
<> 128:9bcdf88f62b0 1102 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
<> 128:9bcdf88f62b0 1103 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
<> 128:9bcdf88f62b0 1104 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
<> 128:9bcdf88f62b0 1105 * @arg TIM_DMA_COM: Commutation DMA request
<> 128:9bcdf88f62b0 1106 * @arg TIM_DMA_TRIGGER: Trigger DMA request
<> 128:9bcdf88f62b0 1107 * @retval None
<> 128:9bcdf88f62b0 1108 */
<> 128:9bcdf88f62b0 1109 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
<> 128:9bcdf88f62b0 1110
<> 128:9bcdf88f62b0 1111 /**
<> 128:9bcdf88f62b0 1112 * @brief Disables the specified DMA request.
<> 128:9bcdf88f62b0 1113 * @param __HANDLE__: specifies the TIM Handle.
<> 128:9bcdf88f62b0 1114 * @param __DMA__: specifies the TIM DMA request to disable.
<> 128:9bcdf88f62b0 1115 * This parameter can be one of the following values:
<> 128:9bcdf88f62b0 1116 * @arg TIM_DMA_UPDATE: Update DMA request
<> 128:9bcdf88f62b0 1117 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
<> 128:9bcdf88f62b0 1118 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
<> 128:9bcdf88f62b0 1119 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
<> 128:9bcdf88f62b0 1120 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
<> 128:9bcdf88f62b0 1121 * @arg TIM_DMA_COM: Commutation DMA request
<> 128:9bcdf88f62b0 1122 * @arg TIM_DMA_TRIGGER: Trigger DMA request
<> 128:9bcdf88f62b0 1123 * @retval None
<> 128:9bcdf88f62b0 1124 */
<> 128:9bcdf88f62b0 1125 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
<> 128:9bcdf88f62b0 1126
<> 128:9bcdf88f62b0 1127 /**
<> 128:9bcdf88f62b0 1128 * @brief Checks whether the specified TIM interrupt flag is set or not.
<> 128:9bcdf88f62b0 1129 * @param __HANDLE__: specifies the TIM Handle.
<> 128:9bcdf88f62b0 1130 * @param __FLAG__: specifies the TIM interrupt flag to check.
<> 128:9bcdf88f62b0 1131 * This parameter can be one of the following values:
<> 128:9bcdf88f62b0 1132 * @arg TIM_FLAG_UPDATE: Update interrupt flag
<> 128:9bcdf88f62b0 1133 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
<> 128:9bcdf88f62b0 1134 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
<> 128:9bcdf88f62b0 1135 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
<> 128:9bcdf88f62b0 1136 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
<> 128:9bcdf88f62b0 1137 * @arg TIM_FLAG_COM: Commutation interrupt flag
<> 128:9bcdf88f62b0 1138 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
<> 128:9bcdf88f62b0 1139 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
<> 128:9bcdf88f62b0 1140 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
<> 128:9bcdf88f62b0 1141 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
<> 128:9bcdf88f62b0 1142 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
<> 128:9bcdf88f62b0 1143 * @retval The new state of __FLAG__ (TRUE or FALSE).
<> 128:9bcdf88f62b0 1144 */
<> 128:9bcdf88f62b0 1145 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
<> 128:9bcdf88f62b0 1146
<> 128:9bcdf88f62b0 1147 /**
<> 128:9bcdf88f62b0 1148 * @brief Clears the specified TIM interrupt flag.
<> 128:9bcdf88f62b0 1149 * @param __HANDLE__: specifies the TIM Handle.
<> 128:9bcdf88f62b0 1150 * @param __FLAG__: specifies the TIM interrupt flag to clear.
<> 128:9bcdf88f62b0 1151 * This parameter can be one of the following values:
<> 128:9bcdf88f62b0 1152 * @arg TIM_FLAG_UPDATE: Update interrupt flag
<> 128:9bcdf88f62b0 1153 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
<> 128:9bcdf88f62b0 1154 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
<> 128:9bcdf88f62b0 1155 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
<> 128:9bcdf88f62b0 1156 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
<> 128:9bcdf88f62b0 1157 * @arg TIM_FLAG_COM: Commutation interrupt flag
<> 128:9bcdf88f62b0 1158 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
<> 128:9bcdf88f62b0 1159 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
<> 128:9bcdf88f62b0 1160 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
<> 128:9bcdf88f62b0 1161 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
<> 128:9bcdf88f62b0 1162 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
<> 128:9bcdf88f62b0 1163 * @retval The new state of __FLAG__ (TRUE or FALSE).
<> 128:9bcdf88f62b0 1164 */
<> 128:9bcdf88f62b0 1165 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
<> 128:9bcdf88f62b0 1166
<> 128:9bcdf88f62b0 1167 /**
<> 128:9bcdf88f62b0 1168 * @brief Checks whether the specified TIM interrupt has occurred or not.
<> 128:9bcdf88f62b0 1169 * @param __HANDLE__: TIM handle
<> 128:9bcdf88f62b0 1170 * @param __INTERRUPT__: specifies the TIM interrupt source to check.
<> 128:9bcdf88f62b0 1171 * @retval The state of TIM_IT (SET or RESET).
<> 128:9bcdf88f62b0 1172 */
<> 128:9bcdf88f62b0 1173 #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
<> 128:9bcdf88f62b0 1174
<> 128:9bcdf88f62b0 1175 /**
<> 128:9bcdf88f62b0 1176 * @brief Clear the TIM interrupt pending bits
<> 128:9bcdf88f62b0 1177 * @param __HANDLE__: TIM handle
<> 128:9bcdf88f62b0 1178 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
<> 128:9bcdf88f62b0 1179 * @retval None
<> 128:9bcdf88f62b0 1180 */
<> 128:9bcdf88f62b0 1181 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
<> 128:9bcdf88f62b0 1182
<> 128:9bcdf88f62b0 1183 /**
<> 128:9bcdf88f62b0 1184 * @brief Indicates whether or not the TIM Counter is used as downcounter
<> 128:9bcdf88f62b0 1185 * @param __HANDLE__: TIM handle.
<> 128:9bcdf88f62b0 1186 * @retval False (Counter used as upcounter) or True (Counter used as downcounter)
<> 128:9bcdf88f62b0 1187 * @note This macro is particularly usefull to get the counting mode when the timer operates in Center-aligned mode or Encoder
<> 128:9bcdf88f62b0 1188 mode.
<> 128:9bcdf88f62b0 1189 */
<> 128:9bcdf88f62b0 1190 #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 & (TIM_CR1_DIR)) == (TIM_CR1_DIR))
<> 128:9bcdf88f62b0 1191
<> 128:9bcdf88f62b0 1192 /**
<> 128:9bcdf88f62b0 1193 * @brief Sets the TIM active prescaler register value on update event.
<> 128:9bcdf88f62b0 1194 * @param __HANDLE__: TIM handle.
<> 128:9bcdf88f62b0 1195 * @param __PRESC__: specifies the active prescaler register new value.
<> 128:9bcdf88f62b0 1196 * @retval None
<> 128:9bcdf88f62b0 1197 */
<> 128:9bcdf88f62b0 1198 #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
<> 128:9bcdf88f62b0 1199
<> 128:9bcdf88f62b0 1200 /**
<> 128:9bcdf88f62b0 1201 * @brief Sets the TIM Capture Compare Register value on runtime without
<> 128:9bcdf88f62b0 1202 * calling another time ConfigChannel function.
<> 128:9bcdf88f62b0 1203 * @param __HANDLE__: TIM handle.
<> 128:9bcdf88f62b0 1204 * @param __CHANNEL__ : TIM Channels to be configured.
<> 128:9bcdf88f62b0 1205 * This parameter can be one of the following values:
<> 128:9bcdf88f62b0 1206 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 128:9bcdf88f62b0 1207 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 128:9bcdf88f62b0 1208 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 128:9bcdf88f62b0 1209 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 128:9bcdf88f62b0 1210 * @param __COMPARE__: specifies the Capture Compare register new value.
<> 128:9bcdf88f62b0 1211 * @retval None
<> 128:9bcdf88f62b0 1212 */
<> 128:9bcdf88f62b0 1213 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
<> 128:9bcdf88f62b0 1214 (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__))
<> 128:9bcdf88f62b0 1215
<> 128:9bcdf88f62b0 1216 /**
<> 128:9bcdf88f62b0 1217 * @brief Gets the TIM Capture Compare Register value on runtime
<> 128:9bcdf88f62b0 1218 * @param __HANDLE__: TIM handle.
<> 128:9bcdf88f62b0 1219 * @param __CHANNEL__ : TIM Channel associated with the capture compare register
<> 128:9bcdf88f62b0 1220 * This parameter can be one of the following values:
<> 128:9bcdf88f62b0 1221 * @arg TIM_CHANNEL_1: get capture/compare 1 register value
<> 128:9bcdf88f62b0 1222 * @arg TIM_CHANNEL_2: get capture/compare 2 register value
<> 128:9bcdf88f62b0 1223 * @arg TIM_CHANNEL_3: get capture/compare 3 register value
<> 128:9bcdf88f62b0 1224 * @arg TIM_CHANNEL_4: get capture/compare 4 register value
<> 128:9bcdf88f62b0 1225 * @retval None
<> 128:9bcdf88f62b0 1226 */
<> 128:9bcdf88f62b0 1227 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
<> 128:9bcdf88f62b0 1228 (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)))
<> 128:9bcdf88f62b0 1229
<> 128:9bcdf88f62b0 1230 /**
<> 128:9bcdf88f62b0 1231 * @brief Sets the TIM Counter Register value on runtime.
<> 128:9bcdf88f62b0 1232 * @param __HANDLE__: TIM handle.
<> 128:9bcdf88f62b0 1233 * @param __COUNTER__: specifies the Counter register new value.
<> 128:9bcdf88f62b0 1234 * @retval None
<> 128:9bcdf88f62b0 1235 */
<> 128:9bcdf88f62b0 1236 #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
<> 128:9bcdf88f62b0 1237
<> 128:9bcdf88f62b0 1238 /**
<> 128:9bcdf88f62b0 1239 * @brief Gets the TIM Counter Register value on runtime.
<> 128:9bcdf88f62b0 1240 * @param __HANDLE__: TIM handle.
<> 128:9bcdf88f62b0 1241 * @retval None
<> 128:9bcdf88f62b0 1242 */
<> 128:9bcdf88f62b0 1243 #define __HAL_TIM_GET_COUNTER(__HANDLE__) \
<> 128:9bcdf88f62b0 1244 ((__HANDLE__)->Instance->CNT)
<> 128:9bcdf88f62b0 1245
<> 128:9bcdf88f62b0 1246 /**
<> 128:9bcdf88f62b0 1247 * @brief Sets the TIM Autoreload Register value on runtime without calling
<> 128:9bcdf88f62b0 1248 * another time any Init function.
<> 128:9bcdf88f62b0 1249 * @param __HANDLE__: TIM handle.
<> 128:9bcdf88f62b0 1250 * @param __AUTORELOAD__: specifies the Counter register new value.
<> 128:9bcdf88f62b0 1251 * @retval None
<> 128:9bcdf88f62b0 1252 */
<> 128:9bcdf88f62b0 1253 #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
<> 128:9bcdf88f62b0 1254 do{ \
<> 128:9bcdf88f62b0 1255 (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
<> 128:9bcdf88f62b0 1256 (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
<> 128:9bcdf88f62b0 1257 } while(0)
<> 128:9bcdf88f62b0 1258
<> 128:9bcdf88f62b0 1259 /**
<> 128:9bcdf88f62b0 1260 * @brief Gets the TIM Autoreload Register value on runtime
<> 128:9bcdf88f62b0 1261 * @param __HANDLE__: TIM handle.
<> 128:9bcdf88f62b0 1262 * @retval None
<> 128:9bcdf88f62b0 1263 */
<> 128:9bcdf88f62b0 1264 #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \
<> 128:9bcdf88f62b0 1265 ((__HANDLE__)->Instance->ARR)
<> 128:9bcdf88f62b0 1266
<> 128:9bcdf88f62b0 1267 /**
<> 128:9bcdf88f62b0 1268 * @brief Sets the TIM Clock Division value on runtime without calling
<> 128:9bcdf88f62b0 1269 * another time any Init function.
<> 128:9bcdf88f62b0 1270 * @param __HANDLE__: TIM handle.
<> 128:9bcdf88f62b0 1271 * @param __CKD__: specifies the clock division value.
<> 128:9bcdf88f62b0 1272 * This parameter can be one of the following value:
<> 128:9bcdf88f62b0 1273 * @arg TIM_CLOCKDIVISION_DIV1
<> 128:9bcdf88f62b0 1274 * @arg TIM_CLOCKDIVISION_DIV2
<> 128:9bcdf88f62b0 1275 * @arg TIM_CLOCKDIVISION_DIV4
<> 128:9bcdf88f62b0 1276 * @retval None
<> 128:9bcdf88f62b0 1277 */
<> 128:9bcdf88f62b0 1278 #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
<> 128:9bcdf88f62b0 1279 do{ \
<> 128:9bcdf88f62b0 1280 (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
<> 128:9bcdf88f62b0 1281 (__HANDLE__)->Instance->CR1 |= (__CKD__); \
<> 128:9bcdf88f62b0 1282 (__HANDLE__)->Init.ClockDivision = (__CKD__); \
<> 128:9bcdf88f62b0 1283 } while(0)
<> 128:9bcdf88f62b0 1284
<> 128:9bcdf88f62b0 1285 /**
<> 128:9bcdf88f62b0 1286 * @brief Gets the TIM Clock Division value on runtime
<> 128:9bcdf88f62b0 1287 * @param __HANDLE__: TIM handle.
<> 128:9bcdf88f62b0 1288 * @retval None
<> 128:9bcdf88f62b0 1289 */
<> 128:9bcdf88f62b0 1290 #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \
<> 128:9bcdf88f62b0 1291 ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
<> 128:9bcdf88f62b0 1292
<> 128:9bcdf88f62b0 1293 /**
<> 128:9bcdf88f62b0 1294 * @brief Sets the TIM Input Capture prescaler on runtime without calling
<> 128:9bcdf88f62b0 1295 * another time HAL_TIM_IC_ConfigChannel() function.
<> 128:9bcdf88f62b0 1296 * @param __HANDLE__: TIM handle.
<> 128:9bcdf88f62b0 1297 * @param __CHANNEL__ : TIM Channels to be configured.
<> 128:9bcdf88f62b0 1298 * This parameter can be one of the following values:
<> 128:9bcdf88f62b0 1299 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 128:9bcdf88f62b0 1300 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 128:9bcdf88f62b0 1301 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 128:9bcdf88f62b0 1302 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 128:9bcdf88f62b0 1303 * @param __ICPSC__: specifies the Input Capture4 prescaler new value.
<> 128:9bcdf88f62b0 1304 * This parameter can be one of the following values:
<> 128:9bcdf88f62b0 1305 * @arg TIM_ICPSC_DIV1: no prescaler
<> 128:9bcdf88f62b0 1306 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
<> 128:9bcdf88f62b0 1307 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
<> 128:9bcdf88f62b0 1308 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
<> 128:9bcdf88f62b0 1309 * @retval None
<> 128:9bcdf88f62b0 1310 */
<> 128:9bcdf88f62b0 1311 #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
<> 128:9bcdf88f62b0 1312 do{ \
<> 128:9bcdf88f62b0 1313 TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
<> 128:9bcdf88f62b0 1314 TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
<> 128:9bcdf88f62b0 1315 } while(0)
<> 128:9bcdf88f62b0 1316
<> 128:9bcdf88f62b0 1317 /**
<> 128:9bcdf88f62b0 1318 * @brief Gets the TIM Input Capture prescaler on runtime
<> 128:9bcdf88f62b0 1319 * @param __HANDLE__: TIM handle.
<> 128:9bcdf88f62b0 1320 * @param __CHANNEL__ : TIM Channels to be configured.
<> 128:9bcdf88f62b0 1321 * This parameter can be one of the following values:
<> 128:9bcdf88f62b0 1322 * @arg TIM_CHANNEL_1: get input capture 1 prescaler value
<> 128:9bcdf88f62b0 1323 * @arg TIM_CHANNEL_2: get input capture 2 prescaler value
<> 128:9bcdf88f62b0 1324 * @arg TIM_CHANNEL_3: get input capture 3 prescaler value
<> 128:9bcdf88f62b0 1325 * @arg TIM_CHANNEL_4: get input capture 4 prescaler value
<> 128:9bcdf88f62b0 1326 * @retval None
<> 128:9bcdf88f62b0 1327 */
<> 128:9bcdf88f62b0 1328 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
<> 128:9bcdf88f62b0 1329 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
<> 128:9bcdf88f62b0 1330 ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
<> 128:9bcdf88f62b0 1331 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
<> 128:9bcdf88f62b0 1332 (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)
<> 128:9bcdf88f62b0 1333
<> 128:9bcdf88f62b0 1334 /**
<> 128:9bcdf88f62b0 1335 * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register
<> 128:9bcdf88f62b0 1336 * @param __HANDLE__: TIM handle.
<> 128:9bcdf88f62b0 1337 * @note When the USR bit of the TIMx_CR1 register is set, only counter
<> 128:9bcdf88f62b0 1338 * overflow/underflow generates an update interrupt or DMA request (if
<> 128:9bcdf88f62b0 1339 * enabled)
<> 128:9bcdf88f62b0 1340 * @retval None
<> 128:9bcdf88f62b0 1341 */
<> 128:9bcdf88f62b0 1342 #define __HAL_TIM_URS_ENABLE(__HANDLE__) \
<> 128:9bcdf88f62b0 1343 ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS))
<> 128:9bcdf88f62b0 1344
<> 128:9bcdf88f62b0 1345 /**
<> 128:9bcdf88f62b0 1346 * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register
<> 128:9bcdf88f62b0 1347 * @param __HANDLE__: TIM handle.
<> 128:9bcdf88f62b0 1348 * @note When the USR bit of the TIMx_CR1 register is reset, any of the
<> 128:9bcdf88f62b0 1349 * following events generate an update interrupt or DMA request (if
<> 128:9bcdf88f62b0 1350 * enabled):
<> 128:9bcdf88f62b0 1351 * (+) Counter overflow/underflow
<> 128:9bcdf88f62b0 1352 * (+) Setting the UG bit
<> 128:9bcdf88f62b0 1353 * (+) Update generation through the slave mode controller
<> 128:9bcdf88f62b0 1354 * @retval None
<> 128:9bcdf88f62b0 1355 */
<> 128:9bcdf88f62b0 1356 #define __HAL_TIM_URS_DISABLE(__HANDLE__) \
<> 128:9bcdf88f62b0 1357 ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
<> 128:9bcdf88f62b0 1358
<> 128:9bcdf88f62b0 1359 /**
<> 128:9bcdf88f62b0 1360 * @brief Sets the TIM Capture x input polarity on runtime.
<> 128:9bcdf88f62b0 1361 * @param __HANDLE__: TIM handle.
<> 128:9bcdf88f62b0 1362 * @param __CHANNEL__: TIM Channels to be configured.
<> 128:9bcdf88f62b0 1363 * This parameter can be one of the following values:
<> 128:9bcdf88f62b0 1364 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 128:9bcdf88f62b0 1365 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 128:9bcdf88f62b0 1366 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 128:9bcdf88f62b0 1367 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 128:9bcdf88f62b0 1368 * @param __POLARITY__: Polarity for TIx source
<> 128:9bcdf88f62b0 1369 * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
<> 128:9bcdf88f62b0 1370 * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
<> 128:9bcdf88f62b0 1371 * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
<> 128:9bcdf88f62b0 1372 * @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4.
<> 128:9bcdf88f62b0 1373 * @retval None
<> 128:9bcdf88f62b0 1374 */
<> 128:9bcdf88f62b0 1375 #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
<> 128:9bcdf88f62b0 1376 do{ \
<> 128:9bcdf88f62b0 1377 TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
<> 128:9bcdf88f62b0 1378 TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
<> 128:9bcdf88f62b0 1379 }while(0)
<> 128:9bcdf88f62b0 1380
<> 128:9bcdf88f62b0 1381 /**
<> 128:9bcdf88f62b0 1382 * @}
<> 128:9bcdf88f62b0 1383 */
<> 128:9bcdf88f62b0 1384
<> 128:9bcdf88f62b0 1385 /* Include TIM HAL Extension module */
<> 128:9bcdf88f62b0 1386 #include "stm32l1xx_hal_tim_ex.h"
<> 128:9bcdf88f62b0 1387
<> 128:9bcdf88f62b0 1388 /* Exported functions --------------------------------------------------------*/
<> 128:9bcdf88f62b0 1389 /** @addtogroup TIM_Exported_Functions
<> 128:9bcdf88f62b0 1390 * @{
<> 128:9bcdf88f62b0 1391 */
<> 128:9bcdf88f62b0 1392
<> 128:9bcdf88f62b0 1393 /** @addtogroup TIM_Exported_Functions_Group1
<> 128:9bcdf88f62b0 1394 * @{
<> 128:9bcdf88f62b0 1395 */
<> 128:9bcdf88f62b0 1396 /* Time Base functions ********************************************************/
<> 128:9bcdf88f62b0 1397 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
<> 128:9bcdf88f62b0 1398 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
<> 128:9bcdf88f62b0 1399 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
<> 128:9bcdf88f62b0 1400 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
<> 128:9bcdf88f62b0 1401 /* Blocking mode: Polling */
<> 128:9bcdf88f62b0 1402 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
<> 128:9bcdf88f62b0 1403 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
<> 128:9bcdf88f62b0 1404 /* Non-Blocking mode: Interrupt */
<> 128:9bcdf88f62b0 1405 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
<> 128:9bcdf88f62b0 1406 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
<> 128:9bcdf88f62b0 1407 /* Non-Blocking mode: DMA */
<> 128:9bcdf88f62b0 1408 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
<> 128:9bcdf88f62b0 1409 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
<> 128:9bcdf88f62b0 1410 /**
<> 128:9bcdf88f62b0 1411 * @}
<> 128:9bcdf88f62b0 1412 */
<> 128:9bcdf88f62b0 1413
<> 128:9bcdf88f62b0 1414 /** @addtogroup TIM_Exported_Functions_Group2
<> 128:9bcdf88f62b0 1415 * @{
<> 128:9bcdf88f62b0 1416 */
<> 128:9bcdf88f62b0 1417 /* Timer Output Compare functions **********************************************/
<> 128:9bcdf88f62b0 1418 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
<> 128:9bcdf88f62b0 1419 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
<> 128:9bcdf88f62b0 1420 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
<> 128:9bcdf88f62b0 1421 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
<> 128:9bcdf88f62b0 1422 /* Blocking mode: Polling */
<> 128:9bcdf88f62b0 1423 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 128:9bcdf88f62b0 1424 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 128:9bcdf88f62b0 1425 /* Non-Blocking mode: Interrupt */
<> 128:9bcdf88f62b0 1426 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 128:9bcdf88f62b0 1427 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 128:9bcdf88f62b0 1428 /* Non-Blocking mode: DMA */
<> 128:9bcdf88f62b0 1429 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
<> 128:9bcdf88f62b0 1430 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 128:9bcdf88f62b0 1431
<> 128:9bcdf88f62b0 1432 /**
<> 128:9bcdf88f62b0 1433 * @}
<> 128:9bcdf88f62b0 1434 */
<> 128:9bcdf88f62b0 1435
<> 128:9bcdf88f62b0 1436 /** @addtogroup TIM_Exported_Functions_Group3
<> 128:9bcdf88f62b0 1437 * @{
<> 128:9bcdf88f62b0 1438 */
<> 128:9bcdf88f62b0 1439 /* Timer PWM functions *********************************************************/
<> 128:9bcdf88f62b0 1440 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
<> 128:9bcdf88f62b0 1441 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
<> 128:9bcdf88f62b0 1442 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
<> 128:9bcdf88f62b0 1443 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
<> 128:9bcdf88f62b0 1444 /* Blocking mode: Polling */
<> 128:9bcdf88f62b0 1445 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 128:9bcdf88f62b0 1446 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 128:9bcdf88f62b0 1447 /* Non-Blocking mode: Interrupt */
<> 128:9bcdf88f62b0 1448 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 128:9bcdf88f62b0 1449 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 128:9bcdf88f62b0 1450 /* Non-Blocking mode: DMA */
<> 128:9bcdf88f62b0 1451 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
<> 128:9bcdf88f62b0 1452 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 128:9bcdf88f62b0 1453 /**
<> 128:9bcdf88f62b0 1454 * @}
<> 128:9bcdf88f62b0 1455 */
<> 128:9bcdf88f62b0 1456
<> 128:9bcdf88f62b0 1457 /** @addtogroup TIM_Exported_Functions_Group4
<> 128:9bcdf88f62b0 1458 * @{
<> 128:9bcdf88f62b0 1459 */
<> 128:9bcdf88f62b0 1460 /* Timer Input Capture functions ***********************************************/
<> 128:9bcdf88f62b0 1461 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
<> 128:9bcdf88f62b0 1462 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
<> 128:9bcdf88f62b0 1463 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
<> 128:9bcdf88f62b0 1464 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
<> 128:9bcdf88f62b0 1465 /* Blocking mode: Polling */
<> 128:9bcdf88f62b0 1466 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 128:9bcdf88f62b0 1467 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 128:9bcdf88f62b0 1468 /* Non-Blocking mode: Interrupt */
<> 128:9bcdf88f62b0 1469 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 128:9bcdf88f62b0 1470 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 128:9bcdf88f62b0 1471 /* Non-Blocking mode: DMA */
<> 128:9bcdf88f62b0 1472 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
<> 128:9bcdf88f62b0 1473 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 128:9bcdf88f62b0 1474 /**
<> 128:9bcdf88f62b0 1475 * @}
<> 128:9bcdf88f62b0 1476 */
<> 128:9bcdf88f62b0 1477
<> 128:9bcdf88f62b0 1478 /** @addtogroup TIM_Exported_Functions_Group5
<> 128:9bcdf88f62b0 1479 * @{
<> 128:9bcdf88f62b0 1480 */
<> 128:9bcdf88f62b0 1481 /* Timer One Pulse functions ***************************************************/
<> 128:9bcdf88f62b0 1482 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
<> 128:9bcdf88f62b0 1483 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
<> 128:9bcdf88f62b0 1484 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
<> 128:9bcdf88f62b0 1485 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
<> 128:9bcdf88f62b0 1486 /* Blocking mode: Polling */
<> 128:9bcdf88f62b0 1487 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
<> 128:9bcdf88f62b0 1488 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
<> 128:9bcdf88f62b0 1489 /* Non-Blocking mode: Interrupt */
<> 128:9bcdf88f62b0 1490 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
<> 128:9bcdf88f62b0 1491 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
<> 128:9bcdf88f62b0 1492 /**
<> 128:9bcdf88f62b0 1493 * @}
<> 128:9bcdf88f62b0 1494 */
<> 128:9bcdf88f62b0 1495
<> 128:9bcdf88f62b0 1496 /** @addtogroup TIM_Exported_Functions_Group6
<> 128:9bcdf88f62b0 1497 * @{
<> 128:9bcdf88f62b0 1498 */
<> 128:9bcdf88f62b0 1499 /* Timer Encoder functions *****************************************************/
<> 128:9bcdf88f62b0 1500 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig);
<> 128:9bcdf88f62b0 1501 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
<> 128:9bcdf88f62b0 1502 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
<> 128:9bcdf88f62b0 1503 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
<> 128:9bcdf88f62b0 1504 /* Blocking mode: Polling */
<> 128:9bcdf88f62b0 1505 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 128:9bcdf88f62b0 1506 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 128:9bcdf88f62b0 1507 /* Non-Blocking mode: Interrupt */
<> 128:9bcdf88f62b0 1508 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 128:9bcdf88f62b0 1509 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 128:9bcdf88f62b0 1510 /* Non-Blocking mode: DMA */
<> 128:9bcdf88f62b0 1511 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
<> 128:9bcdf88f62b0 1512 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 128:9bcdf88f62b0 1513
<> 128:9bcdf88f62b0 1514 /**
<> 128:9bcdf88f62b0 1515 * @}
<> 128:9bcdf88f62b0 1516 */
<> 128:9bcdf88f62b0 1517
<> 128:9bcdf88f62b0 1518 /** @addtogroup TIM_Exported_Functions_Group7
<> 128:9bcdf88f62b0 1519 * @{
<> 128:9bcdf88f62b0 1520 */
<> 128:9bcdf88f62b0 1521 /* Interrupt Handler functions **********************************************/
<> 128:9bcdf88f62b0 1522 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
<> 128:9bcdf88f62b0 1523 /**
<> 128:9bcdf88f62b0 1524 * @}
<> 128:9bcdf88f62b0 1525 */
<> 128:9bcdf88f62b0 1526
<> 128:9bcdf88f62b0 1527 /** @addtogroup TIM_Exported_Functions_Group8
<> 128:9bcdf88f62b0 1528 * @{
<> 128:9bcdf88f62b0 1529 */
<> 128:9bcdf88f62b0 1530 /* Control functions *********************************************************/
<> 128:9bcdf88f62b0 1531 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
<> 128:9bcdf88f62b0 1532 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
<> 128:9bcdf88f62b0 1533 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel);
<> 128:9bcdf88f62b0 1534 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel);
<> 128:9bcdf88f62b0 1535 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel);
<> 128:9bcdf88f62b0 1536 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig);
<> 128:9bcdf88f62b0 1537 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
<> 128:9bcdf88f62b0 1538 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
<> 128:9bcdf88f62b0 1539 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
<> 128:9bcdf88f62b0 1540 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
<> 128:9bcdf88f62b0 1541 uint32_t *BurstBuffer, uint32_t BurstLength);
<> 128:9bcdf88f62b0 1542 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
<> 128:9bcdf88f62b0 1543 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
<> 128:9bcdf88f62b0 1544 uint32_t *BurstBuffer, uint32_t BurstLength);
<> 128:9bcdf88f62b0 1545 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
<> 128:9bcdf88f62b0 1546 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
<> 128:9bcdf88f62b0 1547 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
<> 128:9bcdf88f62b0 1548
<> 128:9bcdf88f62b0 1549 /**
<> 128:9bcdf88f62b0 1550 * @}
<> 128:9bcdf88f62b0 1551 */
<> 128:9bcdf88f62b0 1552
<> 128:9bcdf88f62b0 1553 /** @addtogroup TIM_Exported_Functions_Group9
<> 128:9bcdf88f62b0 1554 * @{
<> 128:9bcdf88f62b0 1555 */
<> 128:9bcdf88f62b0 1556 /* Callback in non blocking modes (Interrupt and DMA) *************************/
<> 128:9bcdf88f62b0 1557 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
<> 128:9bcdf88f62b0 1558 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
<> 128:9bcdf88f62b0 1559 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
<> 128:9bcdf88f62b0 1560 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
<> 128:9bcdf88f62b0 1561 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
<> 128:9bcdf88f62b0 1562 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
<> 128:9bcdf88f62b0 1563 /**
<> 128:9bcdf88f62b0 1564 * @}
<> 128:9bcdf88f62b0 1565 */
<> 128:9bcdf88f62b0 1566
<> 128:9bcdf88f62b0 1567 /** @addtogroup TIM_Exported_Functions_Group10
<> 128:9bcdf88f62b0 1568 * @{
<> 128:9bcdf88f62b0 1569 */
<> 128:9bcdf88f62b0 1570 /* Peripheral State functions **************************************************/
<> 128:9bcdf88f62b0 1571 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
<> 128:9bcdf88f62b0 1572 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
<> 128:9bcdf88f62b0 1573 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
<> 128:9bcdf88f62b0 1574 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
<> 128:9bcdf88f62b0 1575 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
<> 128:9bcdf88f62b0 1576 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
<> 128:9bcdf88f62b0 1577
<> 128:9bcdf88f62b0 1578 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
<> 128:9bcdf88f62b0 1579 void TIM_DMAError(DMA_HandleTypeDef *hdma);
<> 128:9bcdf88f62b0 1580 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
<> 128:9bcdf88f62b0 1581
<> 128:9bcdf88f62b0 1582 /**
<> 128:9bcdf88f62b0 1583 * @}
<> 128:9bcdf88f62b0 1584 */
<> 128:9bcdf88f62b0 1585
<> 128:9bcdf88f62b0 1586 /**
<> 128:9bcdf88f62b0 1587 * @}
<> 128:9bcdf88f62b0 1588 */
<> 128:9bcdf88f62b0 1589
<> 128:9bcdf88f62b0 1590 /**
<> 128:9bcdf88f62b0 1591 * @}
<> 128:9bcdf88f62b0 1592 */
<> 128:9bcdf88f62b0 1593
<> 128:9bcdf88f62b0 1594 /**
<> 128:9bcdf88f62b0 1595 * @}
<> 128:9bcdf88f62b0 1596 */
<> 128:9bcdf88f62b0 1597
<> 128:9bcdf88f62b0 1598 #ifdef __cplusplus
<> 128:9bcdf88f62b0 1599 }
<> 128:9bcdf88f62b0 1600 #endif
<> 128:9bcdf88f62b0 1601
<> 128:9bcdf88f62b0 1602 #endif /* __STM32L1xx_HAL_TIM_H */
<> 128:9bcdf88f62b0 1603
<> 128:9bcdf88f62b0 1604 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/