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TARGET_MAX32600MBED/TARGET_Maxim/TARGET_MAX32600/device/i2cm_regs.h@128:9bcdf88f62b0, 2016-10-27 (annotated)

Committer:
<>
Date:
Thu Oct 27 16:45:56 2016 +0100
Revision:
128:9bcdf88f62b0
Release 128 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



2966: Add kw24 support https://github.com/ARMmbed/mbed-os/pull/2966

3068: MultiTech mDot - clean up PeripheralPins.c and add new pin names https://github.com/ARMmbed/mbed-os/pull/3068

3089: Kinetis HAL: Remove clock initialization code from serial and ticker  https://github.com/ARMmbed/mbed-os/pull/3089

2943: [NRF5] NVIC_SetVector functionality https://github.com/ARMmbed/mbed-os/pull/2943

2938: InterruptIn changes in NCS36510 HAL. https://github.com/ARMmbed/mbed-os/pull/2938

3108: Fix sleep function for NRF52. https://github.com/ARMmbed/mbed-os/pull/3108

3076: STM32F1: Correct timer master value reading https://github.com/ARMmbed/mbed-os/pull/3076

3085: Add LOWPOWERTIMER capability for NUCLEO_F303ZE https://github.com/ARMmbed/mbed-os/pull/3085

3046: [BEETLE] Update BLE stack on Beetle board https://github.com/ARMmbed/mbed-os/pull/3046

3122: [Silicon Labs] Update of Silicon Labs HAL https://github.com/ARMmbed/mbed-os/pull/3122

3022: OnSemi RAM usage fix https://github.com/ARMmbed/mbed-os/pull/3022

3121: STM32F3: Correct UART4 and UART5 defines when using DEVICE_SERIAL_ASYNCH https://github.com/ARMmbed/mbed-os/pull/3121

3142: Targets- NUMAKER_PFM_NUC47216 remove mbed 2 https://github.com/ARMmbed/mbed-os/pull/3142

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 128:9bcdf88f62b0 1 /*******************************************************************************
<> 128:9bcdf88f62b0 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
<> 128:9bcdf88f62b0 3 *
<> 128:9bcdf88f62b0 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 128:9bcdf88f62b0 5 * copy of this software and associated documentation files (the "Software"),
<> 128:9bcdf88f62b0 6 * to deal in the Software without restriction, including without limitation
<> 128:9bcdf88f62b0 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 128:9bcdf88f62b0 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 128:9bcdf88f62b0 9 * Software is furnished to do so, subject to the following conditions:
<> 128:9bcdf88f62b0 10 *
<> 128:9bcdf88f62b0 11 * The above copyright notice and this permission notice shall be included
<> 128:9bcdf88f62b0 12 * in all copies or substantial portions of the Software.
<> 128:9bcdf88f62b0 13 *
<> 128:9bcdf88f62b0 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 128:9bcdf88f62b0 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 128:9bcdf88f62b0 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 128:9bcdf88f62b0 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 128:9bcdf88f62b0 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 128:9bcdf88f62b0 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 128:9bcdf88f62b0 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 128:9bcdf88f62b0 21 *
<> 128:9bcdf88f62b0 22 * Except as contained in this notice, the name of Maxim Integrated
<> 128:9bcdf88f62b0 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 128:9bcdf88f62b0 24 * Products, Inc. Branding Policy.
<> 128:9bcdf88f62b0 25 *
<> 128:9bcdf88f62b0 26 * The mere transfer of this software does not imply any licenses
<> 128:9bcdf88f62b0 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 128:9bcdf88f62b0 28 * trademarks, maskwork rights, or any other form of intellectual
<> 128:9bcdf88f62b0 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 128:9bcdf88f62b0 30 * ownership rights.
<> 128:9bcdf88f62b0 31 *******************************************************************************
<> 128:9bcdf88f62b0 32 */
<> 128:9bcdf88f62b0 33
<> 128:9bcdf88f62b0 34 #ifndef _MXC_I2CM_REGS_H_
<> 128:9bcdf88f62b0 35 #define _MXC_I2CM_REGS_H_
<> 128:9bcdf88f62b0 36
<> 128:9bcdf88f62b0 37 #ifdef __cplusplus
<> 128:9bcdf88f62b0 38 extern "C" {
<> 128:9bcdf88f62b0 39 #endif
<> 128:9bcdf88f62b0 40
<> 128:9bcdf88f62b0 41 #include <stdint.h>
<> 128:9bcdf88f62b0 42
<> 128:9bcdf88f62b0 43 /**
<> 128:9bcdf88f62b0 44 * @file i2cm_regs.h
<> 128:9bcdf88f62b0 45 * @addtogroup i2cm I2CM
<> 128:9bcdf88f62b0 46 * @{
<> 128:9bcdf88f62b0 47 */
<> 128:9bcdf88f62b0 48
<> 128:9bcdf88f62b0 49 /* Offset Register Description
<> 128:9bcdf88f62b0 50 ====== ================================================ */
<> 128:9bcdf88f62b0 51 typedef struct {
<> 128:9bcdf88f62b0 52 __IO uint32_t fs_clk_div; /* 0x0000 Full Speed SCL Clock Settings */
<> 128:9bcdf88f62b0 53 __IO uint32_t hs_clk_div; /* 0x0004 High Speed SCL Clock Settings */
<> 128:9bcdf88f62b0 54 __I uint32_t rsv0008; /* 0x0008 */
<> 128:9bcdf88f62b0 55 __IO uint32_t timeout; /* 0x000C [TO_CNTL] Timeout and Auto-Stop Settings */
<> 128:9bcdf88f62b0 56 __IO uint32_t ctrl; /* 0x0010 [EN_CNTL] I2C Master Control Register */
<> 128:9bcdf88f62b0 57 __IO uint32_t trans; /* 0x0014 [MSTR_CNTL] I2C Master Tx Start and Status Flags */
<> 128:9bcdf88f62b0 58 __IO uint32_t intfl; /* 0x0018 Interrupt Flags */
<> 128:9bcdf88f62b0 59 __IO uint32_t inten; /* 0x001C Interrupt Enable/Disable Controls */
<> 128:9bcdf88f62b0 60 __I uint32_t rsv0020[2]; /* 0x0020 */
<> 128:9bcdf88f62b0 61 __IO uint32_t bb; /* 0x0028 Bit-Bang Control Register */
<> 128:9bcdf88f62b0 62 } mxc_i2cm_regs_t;
<> 128:9bcdf88f62b0 63
<> 128:9bcdf88f62b0 64 /* Offset Register Description
<> 128:9bcdf88f62b0 65 ====== ================================================ */
<> 128:9bcdf88f62b0 66 typedef struct {
<> 128:9bcdf88f62b0 67 __IO uint32_t trans[512]; /* 0x0000 I2C Master Transaction FIFO */
<> 128:9bcdf88f62b0 68 __IO uint32_t rslts[512]; /* 0x0800 I2C Master Results FIFO */
<> 128:9bcdf88f62b0 69 } mxc_i2cm_fifo_regs_t;
<> 128:9bcdf88f62b0 70
<> 128:9bcdf88f62b0 71 /*
<> 128:9bcdf88f62b0 72 Register offsets for module I2CM.
<> 128:9bcdf88f62b0 73 */
<> 128:9bcdf88f62b0 74 #define MXC_R_I2CM_OFFS_FS_CLK_DIV ((uint32_t)0x00000000UL)
<> 128:9bcdf88f62b0 75 #define MXC_R_I2CM_OFFS_HS_CLK_DIV ((uint32_t)0x00000004UL)
<> 128:9bcdf88f62b0 76 #define MXC_R_I2CM_OFFS_TIMEOUT ((uint32_t)0x0000000CUL)
<> 128:9bcdf88f62b0 77 #define MXC_R_I2CM_OFFS_CTRL ((uint32_t)0x00000010UL)
<> 128:9bcdf88f62b0 78 #define MXC_R_I2CM_OFFS_TRANS ((uint32_t)0x00000014UL)
<> 128:9bcdf88f62b0 79 #define MXC_R_I2CM_OFFS_INTFL ((uint32_t)0x00000018UL)
<> 128:9bcdf88f62b0 80 #define MXC_R_I2CM_OFFS_INTEN ((uint32_t)0x0000001CUL)
<> 128:9bcdf88f62b0 81 #define MXC_R_I2CM_OFFS_BB ((uint32_t)0x00000028UL)
<> 128:9bcdf88f62b0 82 #define MXC_R_I2CM_OFFS_AHB_RETRY ((uint32_t)0x00000030UL)
<> 128:9bcdf88f62b0 83
<> 128:9bcdf88f62b0 84 #define MXC_R_I2CM_FIFO_OFFS_TRANS ((uint32_t)0x00000000UL)
<> 128:9bcdf88f62b0 85 #define MXC_R_I2CM_FIFO_OFFS_RSLTS ((uint32_t)0x00000800UL)
<> 128:9bcdf88f62b0 86
<> 128:9bcdf88f62b0 87 /*
<> 128:9bcdf88f62b0 88 Field positions and masks for module I2CM.
<> 128:9bcdf88f62b0 89 */
<> 128:9bcdf88f62b0 90 #define MXC_S_I2CM_TRANS_TAG_START 0x000
<> 128:9bcdf88f62b0 91 #define MXC_S_I2CM_TRANS_TAG_TXDATA_ACK 0x100
<> 128:9bcdf88f62b0 92 #define MXC_S_I2CM_TRANS_TAG_TXDATA_NACK 0x200
<> 128:9bcdf88f62b0 93 #define MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT 0x400
<> 128:9bcdf88f62b0 94 #define MXC_S_I2CM_TRANS_TAG_RXDATA_NACK 0x500
<> 128:9bcdf88f62b0 95 #define MXC_S_I2CM_TRANS_TAG_STOP 0x700
<> 128:9bcdf88f62b0 96 #define MXC_S_I2CM_RSTLS_TAG_DATA 0x100
<> 128:9bcdf88f62b0 97 #define MXC_S_I2CM_RSTLS_TAG_EMPTY 0x200
<> 128:9bcdf88f62b0 98
<> 128:9bcdf88f62b0 99 #define MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS 0
<> 128:9bcdf88f62b0 100 #define MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV ((uint32_t)(0x000000FFUL << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS))
<> 128:9bcdf88f62b0 101 #define MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS 8
<> 128:9bcdf88f62b0 102 #define MXC_F_I2CM_CLK_DIV_SCL_LO_CNT ((uint32_t)(0x00000FFFUL << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS))
<> 128:9bcdf88f62b0 103 #define MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS 20
<> 128:9bcdf88f62b0 104 #define MXC_F_I2CM_CLK_DIV_SCL_HI_CNT ((uint32_t)(0x00000FFFUL << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS))
<> 128:9bcdf88f62b0 105
<> 128:9bcdf88f62b0 106 #define MXC_F_I2CM_TIMEOUT_TX_TIMEOUT_POS 16
<> 128:9bcdf88f62b0 107 #define MXC_F_I2CM_TIMEOUT_TX_TIMEOUT ((uint32_t)(0x000000FFUL << MXC_F_I2CM_TIMEOUT_TX_TIMEOUT_POS))
<> 128:9bcdf88f62b0 108 #define MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN_POS 24
<> 128:9bcdf88f62b0 109 #define MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN ((uint32_t)(0x00000001UL << MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN_POS))
<> 128:9bcdf88f62b0 110
<> 128:9bcdf88f62b0 111 #define MXC_F_I2CM_CTRL_TX_FIFO_EN_POS 2
<> 128:9bcdf88f62b0 112 #define MXC_F_I2CM_CTRL_TX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_I2CM_CTRL_TX_FIFO_EN_POS))
<> 128:9bcdf88f62b0 113 #define MXC_F_I2CM_CTRL_RX_FIFO_EN_POS 3
<> 128:9bcdf88f62b0 114 #define MXC_F_I2CM_CTRL_RX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_I2CM_CTRL_RX_FIFO_EN_POS))
<> 128:9bcdf88f62b0 115 #define MXC_F_I2CM_CTRL_MSTR_RESET_EN_POS 7
<> 128:9bcdf88f62b0 116 #define MXC_F_I2CM_CTRL_MSTR_RESET_EN ((uint32_t)(0x00000001UL << MXC_F_I2CM_CTRL_MSTR_RESET_EN_POS))
<> 128:9bcdf88f62b0 117
<> 128:9bcdf88f62b0 118 #define MXC_F_I2CM_TRANS_TX_START_POS 0
<> 128:9bcdf88f62b0 119 #define MXC_F_I2CM_TRANS_TX_START ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_START_POS))
<> 128:9bcdf88f62b0 120 #define MXC_F_I2CM_TRANS_TX_IN_PROGRESS_POS 1
<> 128:9bcdf88f62b0 121 #define MXC_F_I2CM_TRANS_TX_IN_PROGRESS ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_IN_PROGRESS_POS))
<> 128:9bcdf88f62b0 122 #define MXC_F_I2CM_TRANS_TX_DONE_POS 2
<> 128:9bcdf88f62b0 123 #define MXC_F_I2CM_TRANS_TX_DONE ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_DONE_POS))
<> 128:9bcdf88f62b0 124 #define MXC_F_I2CM_TRANS_TX_NACKED_POS 3
<> 128:9bcdf88f62b0 125 #define MXC_F_I2CM_TRANS_TX_NACKED ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_NACKED_POS))
<> 128:9bcdf88f62b0 126 #define MXC_F_I2CM_TRANS_TX_LOST_ARBITR_POS 4
<> 128:9bcdf88f62b0 127 #define MXC_F_I2CM_TRANS_TX_LOST_ARBITR ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_LOST_ARBITR_POS))
<> 128:9bcdf88f62b0 128 #define MXC_F_I2CM_TRANS_TX_TIMEOUT_POS 5
<> 128:9bcdf88f62b0 129 #define MXC_F_I2CM_TRANS_TX_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_TIMEOUT_POS))
<> 128:9bcdf88f62b0 130
<> 128:9bcdf88f62b0 131 #define MXC_F_I2CM_INTFL_TX_DONE_POS 0
<> 128:9bcdf88f62b0 132 #define MXC_F_I2CM_INTFL_TX_DONE ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_DONE_POS))
<> 128:9bcdf88f62b0 133 #define MXC_F_I2CM_INTFL_TX_NACKED_POS 1
<> 128:9bcdf88f62b0 134 #define MXC_F_I2CM_INTFL_TX_NACKED ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_NACKED_POS))
<> 128:9bcdf88f62b0 135 #define MXC_F_I2CM_INTFL_TX_LOST_ARBITR_POS 2
<> 128:9bcdf88f62b0 136 #define MXC_F_I2CM_INTFL_TX_LOST_ARBITR ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_LOST_ARBITR_POS))
<> 128:9bcdf88f62b0 137 #define MXC_F_I2CM_INTFL_TX_TIMEOUT_POS 3
<> 128:9bcdf88f62b0 138 #define MXC_F_I2CM_INTFL_TX_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_TIMEOUT_POS))
<> 128:9bcdf88f62b0 139 #define MXC_F_I2CM_INTFL_TX_FIFO_EMPTY_POS 4
<> 128:9bcdf88f62b0 140 #define MXC_F_I2CM_INTFL_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_FIFO_EMPTY_POS))
<> 128:9bcdf88f62b0 141 #define MXC_F_I2CM_INTFL_TX_FIFO_3Q_EMPTY_POS 5
<> 128:9bcdf88f62b0 142 #define MXC_F_I2CM_INTFL_TX_FIFO_3Q_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_FIFO_3Q_EMPTY_POS))
<> 128:9bcdf88f62b0 143 #define MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY_POS 6
<> 128:9bcdf88f62b0 144 #define MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY_POS))
<> 128:9bcdf88f62b0 145 #define MXC_F_I2CM_INTFL_RX_FIFO_2Q_FULL_POS 7
<> 128:9bcdf88f62b0 146 #define MXC_F_I2CM_INTFL_RX_FIFO_2Q_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_2Q_FULL_POS))
<> 128:9bcdf88f62b0 147 #define MXC_F_I2CM_INTFL_RX_FIFO_3Q_FULL_POS 8
<> 128:9bcdf88f62b0 148 #define MXC_F_I2CM_INTFL_RX_FIFO_3Q_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_3Q_FULL_POS))
<> 128:9bcdf88f62b0 149 #define MXC_F_I2CM_INTFL_RX_FIFO_FULL_POS 9
<> 128:9bcdf88f62b0 150 #define MXC_F_I2CM_INTFL_RX_FIFO_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_FULL_POS))
<> 128:9bcdf88f62b0 151
<> 128:9bcdf88f62b0 152 #define MXC_F_I2CM_INTEN_TX_DONE_POS 0
<> 128:9bcdf88f62b0 153 #define MXC_F_I2CM_INTEN_TX_DONE ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_DONE_POS))
<> 128:9bcdf88f62b0 154 #define MXC_F_I2CM_INTEN_TX_NACKED_POS 1
<> 128:9bcdf88f62b0 155 #define MXC_F_I2CM_INTEN_TX_NACKED ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_NACKED_POS))
<> 128:9bcdf88f62b0 156 #define MXC_F_I2CM_INTEN_TX_LOST_ARBITR_POS 2
<> 128:9bcdf88f62b0 157 #define MXC_F_I2CM_INTEN_TX_LOST_ARBITR ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_LOST_ARBITR_POS))
<> 128:9bcdf88f62b0 158 #define MXC_F_I2CM_INTEN_TX_TIMEOUT_POS 3
<> 128:9bcdf88f62b0 159 #define MXC_F_I2CM_INTEN_TX_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_TIMEOUT_POS))
<> 128:9bcdf88f62b0 160 #define MXC_F_I2CM_INTEN_TX_FIFO_EMPTY_POS 4
<> 128:9bcdf88f62b0 161 #define MXC_F_I2CM_INTEN_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_FIFO_EMPTY_POS))
<> 128:9bcdf88f62b0 162 #define MXC_F_I2CM_INTEN_TX_FIFO_3Q_EMPTY_POS 5
<> 128:9bcdf88f62b0 163 #define MXC_F_I2CM_INTEN_TX_FIFO_3Q_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_FIFO_3Q_EMPTY_POS))
<> 128:9bcdf88f62b0 164 #define MXC_F_I2CM_INTEN_RX_FIFO_EMPTY_POS 6
<> 128:9bcdf88f62b0 165 #define MXC_F_I2CM_INTEN_RX_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_EMPTY_POS))
<> 128:9bcdf88f62b0 166 #define MXC_F_I2CM_INTEN_RX_FIFO_2Q_FULL_POS 7
<> 128:9bcdf88f62b0 167 #define MXC_F_I2CM_INTEN_RX_FIFO_2Q_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_2Q_FULL_POS))
<> 128:9bcdf88f62b0 168 #define MXC_F_I2CM_INTEN_RX_FIFO_3Q_FULL_POS 8
<> 128:9bcdf88f62b0 169 #define MXC_F_I2CM_INTEN_RX_FIFO_3Q_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_3Q_FULL_POS))
<> 128:9bcdf88f62b0 170 #define MXC_F_I2CM_INTEN_RX_FIFO_FULL_POS 9
<> 128:9bcdf88f62b0 171 #define MXC_F_I2CM_INTEN_RX_FIFO_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_FULL_POS))
<> 128:9bcdf88f62b0 172
<> 128:9bcdf88f62b0 173 #define MXC_F_I2CM_BB_BB_SCL_OUT_POS 0
<> 128:9bcdf88f62b0 174 #define MXC_F_I2CM_BB_BB_SCL_OUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SCL_OUT_POS))
<> 128:9bcdf88f62b0 175 #define MXC_F_I2CM_BB_BB_SDA_OUT_POS 1
<> 128:9bcdf88f62b0 176 #define MXC_F_I2CM_BB_BB_SDA_OUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SDA_OUT_POS))
<> 128:9bcdf88f62b0 177 #define MXC_F_I2CM_BB_BB_SCL_IN_VAL_POS 2
<> 128:9bcdf88f62b0 178 #define MXC_F_I2CM_BB_BB_SCL_IN_VAL ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SCL_IN_VAL_POS))
<> 128:9bcdf88f62b0 179 #define MXC_F_I2CM_BB_BB_SDA_IN_VAL_POS 3
<> 128:9bcdf88f62b0 180 #define MXC_F_I2CM_BB_BB_SDA_IN_VAL ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SDA_IN_VAL_POS))
<> 128:9bcdf88f62b0 181 #define MXC_F_I2CM_BB_RX_FIFO_CNT_POS 16
<> 128:9bcdf88f62b0 182 #define MXC_F_I2CM_BB_RX_FIFO_CNT ((uint32_t)(0x0000001FUL << MXC_F_I2CM_BB_RX_FIFO_CNT_POS))
<> 128:9bcdf88f62b0 183
<> 128:9bcdf88f62b0 184 #ifdef __cplusplus
<> 128:9bcdf88f62b0 185 }
<> 128:9bcdf88f62b0 186 #endif
<> 128:9bcdf88f62b0 187
<> 128:9bcdf88f62b0 188 /**
<> 128:9bcdf88f62b0 189 * @}
<> 128:9bcdf88f62b0 190 */
<> 128:9bcdf88f62b0 191
<> 128:9bcdf88f62b0 192 #endif