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TARGET_NUCLEO_F412ZG/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2c.h@132:9baf128c2fab, 2016-12-20 (annotated)

Committer:
<>
Date:
Tue Dec 20 15:36:52 2016 +0000
Revision:
132:9baf128c2fab
Child:
145:64910690c574
Release 132 of the mbed library



Ports for Upcoming Targets



3241: Add support for FRDM-KW41 https://github.com/ARMmbed/mbed-os/pull/3241

3291: Adding mbed enabled Maker board with NINA-B1 and EVA-M8Q https://github.com/ARMmbed/mbed-os/pull/3291



Fixes and Changes



3062: TARGET_STM :USB device FS  https://github.com/ARMmbed/mbed-os/pull/3062

3213: STM32: Refactor us_ticker.c + hal_tick.c files https://github.com/ARMmbed/mbed-os/pull/3213

3288: Dev spi asynch l0l1 https://github.com/ARMmbed/mbed-os/pull/3288

3289: Bug fix of initial value of interrupt edge in "gpio_irq_init" function. https://github.com/ARMmbed/mbed-os/pull/3289

3302: STM32F4 AnalogIn - Clear VBATE and TSVREFE bits before configuring ADC channels https://github.com/ARMmbed/mbed-os/pull/3302

3320: STM32 - Add ADC_VREF label https://github.com/ARMmbed/mbed-os/pull/3320

3321: no HSE available by default for NUCLEO_L432KC https://github.com/ARMmbed/mbed-os/pull/3321

3352: ublox eva nina - fix line endings https://github.com/ARMmbed/mbed-os/pull/3352

3322: DISCO_L053C8 doesn't support LSE https://github.com/ARMmbed/mbed-os/pull/3322

3345: STM32 - Remove TIM_IT_UPDATE flag in HAL_Suspend/ResumeTick functions https://github.com/ARMmbed/mbed-os/pull/3345

3309: [NUC472/M453] Fix CI failed tests https://github.com/ARMmbed/mbed-os/pull/3309

3157: [Silicon Labs] Adding support for EFR32MG1 wireless SoC https://github.com/ARMmbed/mbed-os/pull/3157

3301: I2C - correct return values for write functions (docs) - part 1 https://github.com/ARMmbed/mbed-os/pull/3301

3303: Fix #2956 #2939 #2957 #2959 #2960: Add HAL_DeInit function in gpio_irq destructor https://github.com/ARMmbed/mbed-os/pull/3303

3304: STM32L476: no HSE is present in NUCLEO and DISCO boards https://github.com/ARMmbed/mbed-os/pull/3304

3318: Register map changes for RevG https://github.com/ARMmbed/mbed-os/pull/3318

3317: NUCLEO_F429ZI has integrated LSE https://github.com/ARMmbed/mbed-os/pull/3317

3312: K64F: SPI Asynch API implementation https://github.com/ARMmbed/mbed-os/pull/3312

3324: Dev i2c common code https://github.com/ARMmbed/mbed-os/pull/3324

3369: Add CAN2 missing pins for connector CN12 https://github.com/ARMmbed/mbed-os/pull/3369

3377: STM32 NUCLEO-L152RE Update system core clock to 32MHz https://github.com/ARMmbed/mbed-os/pull/3377

3378: K66F: Enable LWIP feature https://github.com/ARMmbed/mbed-os/pull/3378

3382: [MAX32620] Fixing serial readable function. https://github.com/ARMmbed/mbed-os/pull/3382

3399: NUCLEO_F103RB - Add SERIAL_FC feature https://github.com/ARMmbed/mbed-os/pull/3399

3409: STM32L1 : map ST HAL assert into MBED assert https://github.com/ARMmbed/mbed-os/pull/3409

3416: Renames i2c_api.c for STM32F1 targets to fix IAR exporter https://github.com/ARMmbed/mbed-os/pull/3416

3348: Fix frequency function of CAN driver. https://github.com/ARMmbed/mbed-os/pull/3348

3366: NUCLEO_F412ZG - Add new platform https://github.com/ARMmbed/mbed-os/pull/3366

3379: STM32F0 : map ST HAL assert into MBED assert https://github.com/ARMmbed/mbed-os/pull/3379

3393: ISR register never re-evaluated in HAL_DMA_PollForTransfer for STM32F4 https://github.com/ARMmbed/mbed-os/pull/3393

3408: STM32F7 : map ST HAL assert into MBED assert https://github.com/ARMmbed/mbed-os/pull/3408

3411: STM32L0 : map ST HAL assert into MBED assert https://github.com/ARMmbed/mbed-os/pull/3411

3424: STM32F4 - FIX to add the update of hdma->State variable https://github.com/ARMmbed/mbed-os/pull/3424

3427: Fix stm i2c slave https://github.com/ARMmbed/mbed-os/pull/3427

3429: Fix stm i2c fix init https://github.com/ARMmbed/mbed-os/pull/3429

3434: [NUC472/M453] Fix stuck in lp_ticker_init and other updates https://github.com/ARMmbed/mbed-os/pull/3434

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 132:9baf128c2fab 1 /**
<> 132:9baf128c2fab 2 ******************************************************************************
<> 132:9baf128c2fab 3 * @file stm32f4xx_hal_i2c.h
<> 132:9baf128c2fab 4 * @author MCD Application Team
<> 132:9baf128c2fab 5 * @version V1.5.0
<> 132:9baf128c2fab 6 * @date 06-May-2016
<> 132:9baf128c2fab 7 * @brief Header file of I2C HAL module.
<> 132:9baf128c2fab 8 ******************************************************************************
<> 132:9baf128c2fab 9 * @attention
<> 132:9baf128c2fab 10 *
<> 132:9baf128c2fab 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 132:9baf128c2fab 12 *
<> 132:9baf128c2fab 13 * Redistribution and use in source and binary forms, with or without modification,
<> 132:9baf128c2fab 14 * are permitted provided that the following conditions are met:
<> 132:9baf128c2fab 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 132:9baf128c2fab 16 * this list of conditions and the following disclaimer.
<> 132:9baf128c2fab 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 132:9baf128c2fab 18 * this list of conditions and the following disclaimer in the documentation
<> 132:9baf128c2fab 19 * and/or other materials provided with the distribution.
<> 132:9baf128c2fab 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 132:9baf128c2fab 21 * may be used to endorse or promote products derived from this software
<> 132:9baf128c2fab 22 * without specific prior written permission.
<> 132:9baf128c2fab 23 *
<> 132:9baf128c2fab 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 132:9baf128c2fab 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 132:9baf128c2fab 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 132:9baf128c2fab 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 132:9baf128c2fab 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 132:9baf128c2fab 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 132:9baf128c2fab 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 132:9baf128c2fab 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 132:9baf128c2fab 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 132:9baf128c2fab 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 132:9baf128c2fab 34 *
<> 132:9baf128c2fab 35 ******************************************************************************
<> 132:9baf128c2fab 36 */
<> 132:9baf128c2fab 37
<> 132:9baf128c2fab 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 132:9baf128c2fab 39 #ifndef __STM32F4xx_HAL_I2C_H
<> 132:9baf128c2fab 40 #define __STM32F4xx_HAL_I2C_H
<> 132:9baf128c2fab 41
<> 132:9baf128c2fab 42 #ifdef __cplusplus
<> 132:9baf128c2fab 43 extern "C" {
<> 132:9baf128c2fab 44 #endif
<> 132:9baf128c2fab 45
<> 132:9baf128c2fab 46 /* Includes ------------------------------------------------------------------*/
<> 132:9baf128c2fab 47 #include "stm32f4xx_hal_def.h"
<> 132:9baf128c2fab 48
<> 132:9baf128c2fab 49 /** @addtogroup STM32F4xx_HAL_Driver
<> 132:9baf128c2fab 50 * @{
<> 132:9baf128c2fab 51 */
<> 132:9baf128c2fab 52
<> 132:9baf128c2fab 53 /** @addtogroup I2C
<> 132:9baf128c2fab 54 * @{
<> 132:9baf128c2fab 55 */
<> 132:9baf128c2fab 56
<> 132:9baf128c2fab 57 /* Exported types ------------------------------------------------------------*/
<> 132:9baf128c2fab 58 /** @defgroup I2C_Exported_Types I2C Exported Types
<> 132:9baf128c2fab 59 * @{
<> 132:9baf128c2fab 60 */
<> 132:9baf128c2fab 61
<> 132:9baf128c2fab 62 /**
<> 132:9baf128c2fab 63 * @brief I2C Configuration Structure definition
<> 132:9baf128c2fab 64 */
<> 132:9baf128c2fab 65 typedef struct
<> 132:9baf128c2fab 66 {
<> 132:9baf128c2fab 67 uint32_t ClockSpeed; /*!< Specifies the clock frequency.
<> 132:9baf128c2fab 68 This parameter must be set to a value lower than 400kHz */
<> 132:9baf128c2fab 69
<> 132:9baf128c2fab 70 uint32_t DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
<> 132:9baf128c2fab 71 This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
<> 132:9baf128c2fab 72
<> 132:9baf128c2fab 73 uint32_t OwnAddress1; /*!< Specifies the first device own address.
<> 132:9baf128c2fab 74 This parameter can be a 7-bit or 10-bit address. */
<> 132:9baf128c2fab 75
<> 132:9baf128c2fab 76 uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
<> 132:9baf128c2fab 77 This parameter can be a value of @ref I2C_addressing_mode */
<> 132:9baf128c2fab 78
<> 132:9baf128c2fab 79 uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
<> 132:9baf128c2fab 80 This parameter can be a value of @ref I2C_dual_addressing_mode */
<> 132:9baf128c2fab 81
<> 132:9baf128c2fab 82 uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
<> 132:9baf128c2fab 83 This parameter can be a 7-bit address. */
<> 132:9baf128c2fab 84
<> 132:9baf128c2fab 85 uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
<> 132:9baf128c2fab 86 This parameter can be a value of @ref I2C_general_call_addressing_mode */
<> 132:9baf128c2fab 87
<> 132:9baf128c2fab 88 uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
<> 132:9baf128c2fab 89 This parameter can be a value of @ref I2C_nostretch_mode */
<> 132:9baf128c2fab 90
<> 132:9baf128c2fab 91 }I2C_InitTypeDef;
<> 132:9baf128c2fab 92
<> 132:9baf128c2fab 93 /**
<> 132:9baf128c2fab 94 * @brief HAL State structure definition
<> 132:9baf128c2fab 95 * @note HAL I2C State value coding follow below described bitmap :
<> 132:9baf128c2fab 96 * b7-b6 Error information
<> 132:9baf128c2fab 97 * 00 : No Error
<> 132:9baf128c2fab 98 * 01 : Abort (Abort user request on going)
<> 132:9baf128c2fab 99 * 10 : Timeout
<> 132:9baf128c2fab 100 * 11 : Error
<> 132:9baf128c2fab 101 * b5 IP initilisation status
<> 132:9baf128c2fab 102 * 0 : Reset (IP not initialized)
<> 132:9baf128c2fab 103 * 1 : Init done (IP initialized and ready to use. HAL I2C Init function called)
<> 132:9baf128c2fab 104 * b4 (not used)
<> 132:9baf128c2fab 105 * x : Should be set to 0
<> 132:9baf128c2fab 106 * b3
<> 132:9baf128c2fab 107 * 0 : Ready or Busy (No Listen mode ongoing)
<> 132:9baf128c2fab 108 * 1 : Listen (IP in Address Listen Mode)
<> 132:9baf128c2fab 109 * b2 Intrinsic process state
<> 132:9baf128c2fab 110 * 0 : Ready
<> 132:9baf128c2fab 111 * 1 : Busy (IP busy with some configuration or internal operations)
<> 132:9baf128c2fab 112 * b1 Rx state
<> 132:9baf128c2fab 113 * 0 : Ready (no Rx operation ongoing)
<> 132:9baf128c2fab 114 * 1 : Busy (Rx operation ongoing)
<> 132:9baf128c2fab 115 * b0 Tx state
<> 132:9baf128c2fab 116 * 0 : Ready (no Tx operation ongoing)
<> 132:9baf128c2fab 117 * 1 : Busy (Tx operation ongoing)
<> 132:9baf128c2fab 118 */
<> 132:9baf128c2fab 119 typedef enum
<> 132:9baf128c2fab 120 {
<> 132:9baf128c2fab 121 HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */
<> 132:9baf128c2fab 122 HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */
<> 132:9baf128c2fab 123 HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */
<> 132:9baf128c2fab 124 HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */
<> 132:9baf128c2fab 125 HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
<> 132:9baf128c2fab 126 HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */
<> 132:9baf128c2fab 127 HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission
<> 132:9baf128c2fab 128 process is ongoing */
<> 132:9baf128c2fab 129 HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
<> 132:9baf128c2fab 130 process is ongoing */
<> 132:9baf128c2fab 131 HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */
<> 132:9baf128c2fab 132 HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */
<> 132:9baf128c2fab 133 HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */
<> 132:9baf128c2fab 134
<> 132:9baf128c2fab 135 }HAL_I2C_StateTypeDef;
<> 132:9baf128c2fab 136
<> 132:9baf128c2fab 137 /**
<> 132:9baf128c2fab 138 * @brief HAL Mode structure definition
<> 132:9baf128c2fab 139 * @note HAL I2C Mode value coding follow below described bitmap :
<> 132:9baf128c2fab 140 * b7 (not used)
<> 132:9baf128c2fab 141 * x : Should be set to 0
<> 132:9baf128c2fab 142 * b6
<> 132:9baf128c2fab 143 * 0 : None
<> 132:9baf128c2fab 144 * 1 : Memory (HAL I2C communication is in Memory Mode)
<> 132:9baf128c2fab 145 * b5
<> 132:9baf128c2fab 146 * 0 : None
<> 132:9baf128c2fab 147 * 1 : Slave (HAL I2C communication is in Slave Mode)
<> 132:9baf128c2fab 148 * b4
<> 132:9baf128c2fab 149 * 0 : None
<> 132:9baf128c2fab 150 * 1 : Master (HAL I2C communication is in Master Mode)
<> 132:9baf128c2fab 151 * b3-b2-b1-b0 (not used)
<> 132:9baf128c2fab 152 * xxxx : Should be set to 0000
<> 132:9baf128c2fab 153 */
<> 132:9baf128c2fab 154 typedef enum
<> 132:9baf128c2fab 155 {
<> 132:9baf128c2fab 156 HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */
<> 132:9baf128c2fab 157 HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */
<> 132:9baf128c2fab 158 HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */
<> 132:9baf128c2fab 159 HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */
<> 132:9baf128c2fab 160
<> 132:9baf128c2fab 161 }HAL_I2C_ModeTypeDef;
<> 132:9baf128c2fab 162
<> 132:9baf128c2fab 163 /**
<> 132:9baf128c2fab 164 * @brief I2C handle Structure definition
<> 132:9baf128c2fab 165 */
<> 132:9baf128c2fab 166 typedef struct
<> 132:9baf128c2fab 167 {
<> 132:9baf128c2fab 168 I2C_TypeDef *Instance; /*!< I2C registers base address */
<> 132:9baf128c2fab 169
<> 132:9baf128c2fab 170 I2C_InitTypeDef Init; /*!< I2C communication parameters */
<> 132:9baf128c2fab 171
<> 132:9baf128c2fab 172 uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */
<> 132:9baf128c2fab 173
<> 132:9baf128c2fab 174 uint16_t XferSize; /*!< I2C transfer size */
<> 132:9baf128c2fab 175
<> 132:9baf128c2fab 176 __IO uint16_t XferCount; /*!< I2C transfer counter */
<> 132:9baf128c2fab 177
<> 132:9baf128c2fab 178 __IO uint32_t XferOptions; /*!< I2C transfer options */
<> 132:9baf128c2fab 179
<> 132:9baf128c2fab 180 __IO uint32_t PreviousState; /*!< I2C communication Previous state and mode
<> 132:9baf128c2fab 181 context for internal usage */
<> 132:9baf128c2fab 182
<> 132:9baf128c2fab 183 DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */
<> 132:9baf128c2fab 184
<> 132:9baf128c2fab 185 DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
<> 132:9baf128c2fab 186
<> 132:9baf128c2fab 187 HAL_LockTypeDef Lock; /*!< I2C locking object */
<> 132:9baf128c2fab 188
<> 132:9baf128c2fab 189 __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
<> 132:9baf128c2fab 190
<> 132:9baf128c2fab 191 __IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */
<> 132:9baf128c2fab 192
<> 132:9baf128c2fab 193 __IO uint32_t ErrorCode; /*!< I2C Error code */
<> 132:9baf128c2fab 194
<> 132:9baf128c2fab 195 __IO uint32_t Devaddress; /*!< I2C Target device address */
<> 132:9baf128c2fab 196
<> 132:9baf128c2fab 197 __IO uint32_t Memaddress; /*!< I2C Target memory address */
<> 132:9baf128c2fab 198
<> 132:9baf128c2fab 199 __IO uint32_t MemaddSize; /*!< I2C Target memory address size */
<> 132:9baf128c2fab 200
<> 132:9baf128c2fab 201 __IO uint32_t EventCount; /*!< I2C Event counter */
<> 132:9baf128c2fab 202
<> 132:9baf128c2fab 203 }I2C_HandleTypeDef;
<> 132:9baf128c2fab 204
<> 132:9baf128c2fab 205 /**
<> 132:9baf128c2fab 206 * @}
<> 132:9baf128c2fab 207 */
<> 132:9baf128c2fab 208
<> 132:9baf128c2fab 209 /* Exported constants --------------------------------------------------------*/
<> 132:9baf128c2fab 210 /** @defgroup I2C_Exported_Constants I2C Exported Constants
<> 132:9baf128c2fab 211 * @{
<> 132:9baf128c2fab 212 */
<> 132:9baf128c2fab 213
<> 132:9baf128c2fab 214 /** @defgroup I2C_Error_Code I2C Error Code
<> 132:9baf128c2fab 215 * @brief I2C Error Code
<> 132:9baf128c2fab 216 * @{
<> 132:9baf128c2fab 217 */
<> 132:9baf128c2fab 218 #define HAL_I2C_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
<> 132:9baf128c2fab 219 #define HAL_I2C_ERROR_BERR ((uint32_t)0x00000001U) /*!< BERR error */
<> 132:9baf128c2fab 220 #define HAL_I2C_ERROR_ARLO ((uint32_t)0x00000002U) /*!< ARLO error */
<> 132:9baf128c2fab 221 #define HAL_I2C_ERROR_AF ((uint32_t)0x00000004U) /*!< AF error */
<> 132:9baf128c2fab 222 #define HAL_I2C_ERROR_OVR ((uint32_t)0x00000008U) /*!< OVR error */
<> 132:9baf128c2fab 223 #define HAL_I2C_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
<> 132:9baf128c2fab 224 #define HAL_I2C_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout Error */
<> 132:9baf128c2fab 225 /**
<> 132:9baf128c2fab 226 * @}
<> 132:9baf128c2fab 227 */
<> 132:9baf128c2fab 228
<> 132:9baf128c2fab 229 /** @defgroup I2C_duty_cycle_in_fast_mode I2C duty cycle in fast mode
<> 132:9baf128c2fab 230 * @{
<> 132:9baf128c2fab 231 */
<> 132:9baf128c2fab 232 #define I2C_DUTYCYCLE_2 ((uint32_t)0x00000000U)
<> 132:9baf128c2fab 233 #define I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY
<> 132:9baf128c2fab 234 /**
<> 132:9baf128c2fab 235 * @}
<> 132:9baf128c2fab 236 */
<> 132:9baf128c2fab 237
<> 132:9baf128c2fab 238 /** @defgroup I2C_addressing_mode I2C addressing mode
<> 132:9baf128c2fab 239 * @{
<> 132:9baf128c2fab 240 */
<> 132:9baf128c2fab 241 #define I2C_ADDRESSINGMODE_7BIT ((uint32_t)0x00004000U)
<> 132:9baf128c2fab 242 #define I2C_ADDRESSINGMODE_10BIT (I2C_OAR1_ADDMODE | ((uint32_t)0x00004000U))
<> 132:9baf128c2fab 243 /**
<> 132:9baf128c2fab 244 * @}
<> 132:9baf128c2fab 245 */
<> 132:9baf128c2fab 246
<> 132:9baf128c2fab 247 /** @defgroup I2C_dual_addressing_mode I2C dual addressing mode
<> 132:9baf128c2fab 248 * @{
<> 132:9baf128c2fab 249 */
<> 132:9baf128c2fab 250 #define I2C_DUALADDRESS_DISABLE ((uint32_t)0x00000000U)
<> 132:9baf128c2fab 251 #define I2C_DUALADDRESS_ENABLE I2C_OAR2_ENDUAL
<> 132:9baf128c2fab 252 /**
<> 132:9baf128c2fab 253 * @}
<> 132:9baf128c2fab 254 */
<> 132:9baf128c2fab 255
<> 132:9baf128c2fab 256 /** @defgroup I2C_general_call_addressing_mode I2C general call addressing mode
<> 132:9baf128c2fab 257 * @{
<> 132:9baf128c2fab 258 */
<> 132:9baf128c2fab 259 #define I2C_GENERALCALL_DISABLE ((uint32_t)0x00000000U)
<> 132:9baf128c2fab 260 #define I2C_GENERALCALL_ENABLE I2C_CR1_ENGC
<> 132:9baf128c2fab 261 /**
<> 132:9baf128c2fab 262 * @}
<> 132:9baf128c2fab 263 */
<> 132:9baf128c2fab 264
<> 132:9baf128c2fab 265 /** @defgroup I2C_nostretch_mode I2C nostretch mode
<> 132:9baf128c2fab 266 * @{
<> 132:9baf128c2fab 267 */
<> 132:9baf128c2fab 268 #define I2C_NOSTRETCH_DISABLE ((uint32_t)0x00000000U)
<> 132:9baf128c2fab 269 #define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
<> 132:9baf128c2fab 270 /**
<> 132:9baf128c2fab 271 * @}
<> 132:9baf128c2fab 272 */
<> 132:9baf128c2fab 273
<> 132:9baf128c2fab 274 /** @defgroup I2C_Memory_Address_Size I2C Memory Address Size
<> 132:9baf128c2fab 275 * @{
<> 132:9baf128c2fab 276 */
<> 132:9baf128c2fab 277 #define I2C_MEMADD_SIZE_8BIT ((uint32_t)0x00000001U)
<> 132:9baf128c2fab 278 #define I2C_MEMADD_SIZE_16BIT ((uint32_t)0x00000010U)
<> 132:9baf128c2fab 279 /**
<> 132:9baf128c2fab 280 * @}
<> 132:9baf128c2fab 281 */
<> 132:9baf128c2fab 282
<> 132:9baf128c2fab 283 /** @defgroup I2C_XferDirection_definition I2C XferDirection definition
<> 132:9baf128c2fab 284 * @{
<> 132:9baf128c2fab 285 */
<> 132:9baf128c2fab 286 #define I2C_DIRECTION_RECEIVE ((uint32_t)0x00000000U)
<> 132:9baf128c2fab 287 #define I2C_DIRECTION_TRANSMIT ((uint32_t)0x00000001U)
<> 132:9baf128c2fab 288 /**
<> 132:9baf128c2fab 289 * @}
<> 132:9baf128c2fab 290 */
<> 132:9baf128c2fab 291
<> 132:9baf128c2fab 292 /** @defgroup I2C_XferOptions_definition I2C XferOptions definition
<> 132:9baf128c2fab 293 * @{
<> 132:9baf128c2fab 294 */
<> 132:9baf128c2fab 295 #define I2C_FIRST_FRAME ((uint32_t)0x00000001U)
<> 132:9baf128c2fab 296 #define I2C_NEXT_FRAME ((uint32_t)0x00000002U)
<> 132:9baf128c2fab 297 #define I2C_FIRST_AND_LAST_FRAME ((uint32_t)0x00000004U)
<> 132:9baf128c2fab 298 #define I2C_LAST_FRAME ((uint32_t)0x00000008U)
<> 132:9baf128c2fab 299 /**
<> 132:9baf128c2fab 300 * @}
<> 132:9baf128c2fab 301 */
<> 132:9baf128c2fab 302
<> 132:9baf128c2fab 303 /** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
<> 132:9baf128c2fab 304 * @{
<> 132:9baf128c2fab 305 */
<> 132:9baf128c2fab 306 #define I2C_IT_BUF I2C_CR2_ITBUFEN
<> 132:9baf128c2fab 307 #define I2C_IT_EVT I2C_CR2_ITEVTEN
<> 132:9baf128c2fab 308 #define I2C_IT_ERR I2C_CR2_ITERREN
<> 132:9baf128c2fab 309 /**
<> 132:9baf128c2fab 310 * @}
<> 132:9baf128c2fab 311 */
<> 132:9baf128c2fab 312
<> 132:9baf128c2fab 313 /** @defgroup I2C_Flag_definition I2C Flag definition
<> 132:9baf128c2fab 314 * @{
<> 132:9baf128c2fab 315 */
<> 132:9baf128c2fab 316 #define I2C_FLAG_SMBALERT ((uint32_t)0x00018000U)
<> 132:9baf128c2fab 317 #define I2C_FLAG_TIMEOUT ((uint32_t)0x00014000U)
<> 132:9baf128c2fab 318 #define I2C_FLAG_PECERR ((uint32_t)0x00011000U)
<> 132:9baf128c2fab 319 #define I2C_FLAG_OVR ((uint32_t)0x00010800U)
<> 132:9baf128c2fab 320 #define I2C_FLAG_AF ((uint32_t)0x00010400U)
<> 132:9baf128c2fab 321 #define I2C_FLAG_ARLO ((uint32_t)0x00010200U)
<> 132:9baf128c2fab 322 #define I2C_FLAG_BERR ((uint32_t)0x00010100U)
<> 132:9baf128c2fab 323 #define I2C_FLAG_TXE ((uint32_t)0x00010080U)
<> 132:9baf128c2fab 324 #define I2C_FLAG_RXNE ((uint32_t)0x00010040U)
<> 132:9baf128c2fab 325 #define I2C_FLAG_STOPF ((uint32_t)0x00010010U)
<> 132:9baf128c2fab 326 #define I2C_FLAG_ADD10 ((uint32_t)0x00010008U)
<> 132:9baf128c2fab 327 #define I2C_FLAG_BTF ((uint32_t)0x00010004U)
<> 132:9baf128c2fab 328 #define I2C_FLAG_ADDR ((uint32_t)0x00010002U)
<> 132:9baf128c2fab 329 #define I2C_FLAG_SB ((uint32_t)0x00010001U)
<> 132:9baf128c2fab 330 #define I2C_FLAG_DUALF ((uint32_t)0x00100080U)
<> 132:9baf128c2fab 331 #define I2C_FLAG_SMBHOST ((uint32_t)0x00100040U)
<> 132:9baf128c2fab 332 #define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00100020U)
<> 132:9baf128c2fab 333 #define I2C_FLAG_GENCALL ((uint32_t)0x00100010U)
<> 132:9baf128c2fab 334 #define I2C_FLAG_TRA ((uint32_t)0x00100004U)
<> 132:9baf128c2fab 335 #define I2C_FLAG_BUSY ((uint32_t)0x00100002U)
<> 132:9baf128c2fab 336 #define I2C_FLAG_MSL ((uint32_t)0x00100001U)
<> 132:9baf128c2fab 337 /**
<> 132:9baf128c2fab 338 * @}
<> 132:9baf128c2fab 339 */
<> 132:9baf128c2fab 340
<> 132:9baf128c2fab 341 /**
<> 132:9baf128c2fab 342 * @}
<> 132:9baf128c2fab 343 */
<> 132:9baf128c2fab 344
<> 132:9baf128c2fab 345 /* Exported macro ------------------------------------------------------------*/
<> 132:9baf128c2fab 346 /** @defgroup I2C_Exported_Macros I2C Exported Macros
<> 132:9baf128c2fab 347 * @{
<> 132:9baf128c2fab 348 */
<> 132:9baf128c2fab 349
<> 132:9baf128c2fab 350 /** @brief Reset I2C handle state
<> 132:9baf128c2fab 351 * @param __HANDLE__: specifies the I2C Handle.
<> 132:9baf128c2fab 352 * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
<> 132:9baf128c2fab 353 * @retval None
<> 132:9baf128c2fab 354 */
<> 132:9baf128c2fab 355 #define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
<> 132:9baf128c2fab 356
<> 132:9baf128c2fab 357 /** @brief Enable or disable the specified I2C interrupts.
<> 132:9baf128c2fab 358 * @param __HANDLE__: specifies the I2C Handle.
<> 132:9baf128c2fab 359 * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
<> 132:9baf128c2fab 360 * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
<> 132:9baf128c2fab 361 * This parameter can be one of the following values:
<> 132:9baf128c2fab 362 * @arg I2C_IT_BUF: Buffer interrupt enable
<> 132:9baf128c2fab 363 * @arg I2C_IT_EVT: Event interrupt enable
<> 132:9baf128c2fab 364 * @arg I2C_IT_ERR: Error interrupt enable
<> 132:9baf128c2fab 365 * @retval None
<> 132:9baf128c2fab 366 */
<> 132:9baf128c2fab 367 #define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
<> 132:9baf128c2fab 368 #define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
<> 132:9baf128c2fab 369
<> 132:9baf128c2fab 370 /** @brief Checks if the specified I2C interrupt source is enabled or disabled.
<> 132:9baf128c2fab 371 * @param __HANDLE__: specifies the I2C Handle.
<> 132:9baf128c2fab 372 * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
<> 132:9baf128c2fab 373 * @param __INTERRUPT__: specifies the I2C interrupt source to check.
<> 132:9baf128c2fab 374 * This parameter can be one of the following values:
<> 132:9baf128c2fab 375 * @arg I2C_IT_BUF: Buffer interrupt enable
<> 132:9baf128c2fab 376 * @arg I2C_IT_EVT: Event interrupt enable
<> 132:9baf128c2fab 377 * @arg I2C_IT_ERR: Error interrupt enable
<> 132:9baf128c2fab 378 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
<> 132:9baf128c2fab 379 */
<> 132:9baf128c2fab 380 #define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
<> 132:9baf128c2fab 381
<> 132:9baf128c2fab 382 /** @brief Checks whether the specified I2C flag is set or not.
<> 132:9baf128c2fab 383 * @param __HANDLE__: specifies the I2C Handle.
<> 132:9baf128c2fab 384 * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
<> 132:9baf128c2fab 385 * @param __FLAG__: specifies the flag to check.
<> 132:9baf128c2fab 386 * This parameter can be one of the following values:
<> 132:9baf128c2fab 387 * @arg I2C_FLAG_SMBALERT: SMBus Alert flag
<> 132:9baf128c2fab 388 * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
<> 132:9baf128c2fab 389 * @arg I2C_FLAG_PECERR: PEC error in reception flag
<> 132:9baf128c2fab 390 * @arg I2C_FLAG_OVR: Overrun/Underrun flag
<> 132:9baf128c2fab 391 * @arg I2C_FLAG_AF: Acknowledge failure flag
<> 132:9baf128c2fab 392 * @arg I2C_FLAG_ARLO: Arbitration lost flag
<> 132:9baf128c2fab 393 * @arg I2C_FLAG_BERR: Bus error flag
<> 132:9baf128c2fab 394 * @arg I2C_FLAG_TXE: Data register empty flag
<> 132:9baf128c2fab 395 * @arg I2C_FLAG_RXNE: Data register not empty flag
<> 132:9baf128c2fab 396 * @arg I2C_FLAG_STOPF: Stop detection flag
<> 132:9baf128c2fab 397 * @arg I2C_FLAG_ADD10: 10-bit header sent flag
<> 132:9baf128c2fab 398 * @arg I2C_FLAG_BTF: Byte transfer finished flag
<> 132:9baf128c2fab 399 * @arg I2C_FLAG_ADDR: Address sent flag
<> 132:9baf128c2fab 400 * Address matched flag
<> 132:9baf128c2fab 401 * @arg I2C_FLAG_SB: Start bit flag
<> 132:9baf128c2fab 402 * @arg I2C_FLAG_DUALF: Dual flag
<> 132:9baf128c2fab 403 * @arg I2C_FLAG_SMBHOST: SMBus host header
<> 132:9baf128c2fab 404 * @arg I2C_FLAG_SMBDEFAULT: SMBus default header
<> 132:9baf128c2fab 405 * @arg I2C_FLAG_GENCALL: General call header flag
<> 132:9baf128c2fab 406 * @arg I2C_FLAG_TRA: Transmitter/Receiver flag
<> 132:9baf128c2fab 407 * @arg I2C_FLAG_BUSY: Bus busy flag
<> 132:9baf128c2fab 408 * @arg I2C_FLAG_MSL: Master/Slave flag
<> 132:9baf128c2fab 409 * @retval The new state of __FLAG__ (TRUE or FALSE).
<> 132:9baf128c2fab 410 */
<> 132:9baf128c2fab 411 #define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 16U)) == 0x01U)?((((__HANDLE__)->Instance->SR1) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)): \
<> 132:9baf128c2fab 412 ((((__HANDLE__)->Instance->SR2) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)))
<> 132:9baf128c2fab 413
<> 132:9baf128c2fab 414 /** @brief Clears the I2C pending flags which are cleared by writing 0 in a specific bit.
<> 132:9baf128c2fab 415 * @param __HANDLE__: specifies the I2C Handle.
<> 132:9baf128c2fab 416 * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
<> 132:9baf128c2fab 417 * @param __FLAG__: specifies the flag to clear.
<> 132:9baf128c2fab 418 * This parameter can be any combination of the following values:
<> 132:9baf128c2fab 419 * @arg I2C_FLAG_SMBALERT: SMBus Alert flag
<> 132:9baf128c2fab 420 * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
<> 132:9baf128c2fab 421 * @arg I2C_FLAG_PECERR: PEC error in reception flag
<> 132:9baf128c2fab 422 * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
<> 132:9baf128c2fab 423 * @arg I2C_FLAG_AF: Acknowledge failure flag
<> 132:9baf128c2fab 424 * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
<> 132:9baf128c2fab 425 * @arg I2C_FLAG_BERR: Bus error flag
<> 132:9baf128c2fab 426 * @retval None
<> 132:9baf128c2fab 427 */
<> 132:9baf128c2fab 428 #define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR1 = ~((__FLAG__) & I2C_FLAG_MASK))
<> 132:9baf128c2fab 429
<> 132:9baf128c2fab 430 /** @brief Clears the I2C ADDR pending flag.
<> 132:9baf128c2fab 431 * @param __HANDLE__: specifies the I2C Handle.
<> 132:9baf128c2fab 432 * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
<> 132:9baf128c2fab 433 * @retval None
<> 132:9baf128c2fab 434 */
<> 132:9baf128c2fab 435 #define __HAL_I2C_CLEAR_ADDRFLAG(__HANDLE__) \
<> 132:9baf128c2fab 436 do{ \
<> 132:9baf128c2fab 437 __IO uint32_t tmpreg = 0x00U; \
<> 132:9baf128c2fab 438 tmpreg = (__HANDLE__)->Instance->SR1; \
<> 132:9baf128c2fab 439 tmpreg = (__HANDLE__)->Instance->SR2; \
<> 132:9baf128c2fab 440 UNUSED(tmpreg); \
<> 132:9baf128c2fab 441 } while(0)
<> 132:9baf128c2fab 442
<> 132:9baf128c2fab 443 /** @brief Clears the I2C STOPF pending flag.
<> 132:9baf128c2fab 444 * @param __HANDLE__: specifies the I2C Handle.
<> 132:9baf128c2fab 445 * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
<> 132:9baf128c2fab 446 * @retval None
<> 132:9baf128c2fab 447 */
<> 132:9baf128c2fab 448 #define __HAL_I2C_CLEAR_STOPFLAG(__HANDLE__) \
<> 132:9baf128c2fab 449 do{ \
<> 132:9baf128c2fab 450 __IO uint32_t tmpreg = 0x00U; \
<> 132:9baf128c2fab 451 tmpreg = (__HANDLE__)->Instance->SR1; \
<> 132:9baf128c2fab 452 (__HANDLE__)->Instance->CR1 |= I2C_CR1_PE; \
<> 132:9baf128c2fab 453 UNUSED(tmpreg); \
<> 132:9baf128c2fab 454 } while(0)
<> 132:9baf128c2fab 455
<> 132:9baf128c2fab 456 /** @brief Enable the I2C peripheral.
<> 132:9baf128c2fab 457 * @param __HANDLE__: specifies the I2C Handle.
<> 132:9baf128c2fab 458 * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral.
<> 132:9baf128c2fab 459 * @retval None
<> 132:9baf128c2fab 460 */
<> 132:9baf128c2fab 461 #define __HAL_I2C_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= I2C_CR1_PE)
<> 132:9baf128c2fab 462
<> 132:9baf128c2fab 463 /** @brief Disable the I2C peripheral.
<> 132:9baf128c2fab 464 * @param __HANDLE__: specifies the I2C Handle.
<> 132:9baf128c2fab 465 * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral.
<> 132:9baf128c2fab 466 * @retval None
<> 132:9baf128c2fab 467 */
<> 132:9baf128c2fab 468 #define __HAL_I2C_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~I2C_CR1_PE)
<> 132:9baf128c2fab 469
<> 132:9baf128c2fab 470 /**
<> 132:9baf128c2fab 471 * @}
<> 132:9baf128c2fab 472 */
<> 132:9baf128c2fab 473
<> 132:9baf128c2fab 474 /* Include I2C HAL Extension module */
<> 132:9baf128c2fab 475 #include "stm32f4xx_hal_i2c_ex.h"
<> 132:9baf128c2fab 476
<> 132:9baf128c2fab 477 /* Exported functions --------------------------------------------------------*/
<> 132:9baf128c2fab 478 /** @addtogroup I2C_Exported_Functions
<> 132:9baf128c2fab 479 * @{
<> 132:9baf128c2fab 480 */
<> 132:9baf128c2fab 481
<> 132:9baf128c2fab 482 /** @addtogroup I2C_Exported_Functions_Group1
<> 132:9baf128c2fab 483 * @{
<> 132:9baf128c2fab 484 */
<> 132:9baf128c2fab 485 /* Initialization/de-initialization functions **********************************/
<> 132:9baf128c2fab 486 HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
<> 132:9baf128c2fab 487 HAL_StatusTypeDef HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c);
<> 132:9baf128c2fab 488 void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
<> 132:9baf128c2fab 489 void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
<> 132:9baf128c2fab 490 /**
<> 132:9baf128c2fab 491 * @}
<> 132:9baf128c2fab 492 */
<> 132:9baf128c2fab 493
<> 132:9baf128c2fab 494 /** @addtogroup I2C_Exported_Functions_Group2
<> 132:9baf128c2fab 495 * @{
<> 132:9baf128c2fab 496 */
<> 132:9baf128c2fab 497 /* I/O operation functions *****************************************************/
<> 132:9baf128c2fab 498 /******* Blocking mode: Polling */
<> 132:9baf128c2fab 499 HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
<> 132:9baf128c2fab 500 HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
<> 132:9baf128c2fab 501 HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
<> 132:9baf128c2fab 502 HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
<> 132:9baf128c2fab 503 HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
<> 132:9baf128c2fab 504 HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
<> 132:9baf128c2fab 505 HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
<> 132:9baf128c2fab 506
<> 132:9baf128c2fab 507 /******* Non-Blocking mode: Interrupt */
<> 132:9baf128c2fab 508 HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
<> 132:9baf128c2fab 509 HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
<> 132:9baf128c2fab 510 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
<> 132:9baf128c2fab 511 HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
<> 132:9baf128c2fab 512 HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
<> 132:9baf128c2fab 513 HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
<> 132:9baf128c2fab 514
<> 132:9baf128c2fab 515 HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
<> 132:9baf128c2fab 516 HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
<> 132:9baf128c2fab 517 HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
<> 132:9baf128c2fab 518 HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
<> 132:9baf128c2fab 519 HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
<> 132:9baf128c2fab 520 HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
<> 132:9baf128c2fab 521 HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
<> 132:9baf128c2fab 522
<> 132:9baf128c2fab 523 /******* Non-Blocking mode: DMA */
<> 132:9baf128c2fab 524 HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
<> 132:9baf128c2fab 525 HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
<> 132:9baf128c2fab 526 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
<> 132:9baf128c2fab 527 HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
<> 132:9baf128c2fab 528 HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
<> 132:9baf128c2fab 529 HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
<> 132:9baf128c2fab 530
<> 132:9baf128c2fab 531 /******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
<> 132:9baf128c2fab 532 void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
<> 132:9baf128c2fab 533 void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
<> 132:9baf128c2fab 534 void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
<> 132:9baf128c2fab 535 void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
<> 132:9baf128c2fab 536 void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
<> 132:9baf128c2fab 537 void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
<> 132:9baf128c2fab 538 void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
<> 132:9baf128c2fab 539 void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
<> 132:9baf128c2fab 540 void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
<> 132:9baf128c2fab 541 void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
<> 132:9baf128c2fab 542 void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
<> 132:9baf128c2fab 543 void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
<> 132:9baf128c2fab 544 /**
<> 132:9baf128c2fab 545 * @}
<> 132:9baf128c2fab 546 */
<> 132:9baf128c2fab 547
<> 132:9baf128c2fab 548 /** @addtogroup I2C_Exported_Functions_Group3
<> 132:9baf128c2fab 549 * @{
<> 132:9baf128c2fab 550 */
<> 132:9baf128c2fab 551 /* Peripheral State, Mode and Errors functions *********************************/
<> 132:9baf128c2fab 552 HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
<> 132:9baf128c2fab 553 HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
<> 132:9baf128c2fab 554 uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
<> 132:9baf128c2fab 555
<> 132:9baf128c2fab 556 /**
<> 132:9baf128c2fab 557 * @}
<> 132:9baf128c2fab 558 */
<> 132:9baf128c2fab 559
<> 132:9baf128c2fab 560 /**
<> 132:9baf128c2fab 561 * @}
<> 132:9baf128c2fab 562 */
<> 132:9baf128c2fab 563 /* Private types -------------------------------------------------------------*/
<> 132:9baf128c2fab 564 /* Private variables ---------------------------------------------------------*/
<> 132:9baf128c2fab 565 /* Private constants ---------------------------------------------------------*/
<> 132:9baf128c2fab 566 /** @defgroup I2C_Private_Constants I2C Private Constants
<> 132:9baf128c2fab 567 * @{
<> 132:9baf128c2fab 568 */
<> 132:9baf128c2fab 569 #define I2C_FLAG_MASK ((uint32_t)0x0000FFFFU)
<> 132:9baf128c2fab 570 /**
<> 132:9baf128c2fab 571 * @}
<> 132:9baf128c2fab 572 */
<> 132:9baf128c2fab 573
<> 132:9baf128c2fab 574 /* Private macros ------------------------------------------------------------*/
<> 132:9baf128c2fab 575 /** @defgroup I2C_Private_Macros I2C Private Macros
<> 132:9baf128c2fab 576 * @{
<> 132:9baf128c2fab 577 */
<> 132:9baf128c2fab 578
<> 132:9baf128c2fab 579 #define I2C_FREQRANGE(__PCLK__) ((__PCLK__)/1000000U)
<> 132:9baf128c2fab 580 #define I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (((__SPEED__) <= 100000U) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U))
<> 132:9baf128c2fab 581 #define I2C_SPEED_STANDARD(__PCLK__, __SPEED__) (((((__PCLK__)/((__SPEED__) << 1U)) & I2C_CCR_CCR) < 4U)? 4U:((__PCLK__) / ((__SPEED__) << 1U)))
<> 132:9baf128c2fab 582 #define I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? ((__PCLK__) / ((__SPEED__) * 3U)) : (((__PCLK__) / ((__SPEED__) * 25U)) | I2C_DUTYCYCLE_16_9))
<> 132:9baf128c2fab 583 #define I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__SPEED__) <= 100000U)? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) : \
<> 132:9baf128c2fab 584 ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0U)? 1U : \
<> 132:9baf128c2fab 585 ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS))
<> 132:9baf128c2fab 586
<> 132:9baf128c2fab 587 #define I2C_7BIT_ADD_WRITE(__ADDRESS__) ((uint8_t)((__ADDRESS__) & (~I2C_OAR1_ADD0)))
<> 132:9baf128c2fab 588 #define I2C_7BIT_ADD_READ(__ADDRESS__) ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0))
<> 132:9baf128c2fab 589
<> 132:9baf128c2fab 590 #define I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
<> 132:9baf128c2fab 591 #define I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300U))) >> 7U) | (uint16_t)(0x00F0U))))
<> 132:9baf128c2fab 592 #define I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300U))) >> 7U) | (uint16_t)(0x00F1U))))
<> 132:9baf128c2fab 593
<> 132:9baf128c2fab 594 #define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
<> 132:9baf128c2fab 595 #define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
<> 132:9baf128c2fab 596
<> 132:9baf128c2fab 597 /** @defgroup I2C_IS_RTC_Definitions I2C Private macros to check input parameters
<> 132:9baf128c2fab 598 * @{
<> 132:9baf128c2fab 599 */
<> 132:9baf128c2fab 600 #define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DUTYCYCLE_2) || \
<> 132:9baf128c2fab 601 ((CYCLE) == I2C_DUTYCYCLE_16_9))
<> 132:9baf128c2fab 602 #define IS_I2C_ADDRESSING_MODE(ADDRESS) (((ADDRESS) == I2C_ADDRESSINGMODE_7BIT) || \
<> 132:9baf128c2fab 603 ((ADDRESS) == I2C_ADDRESSINGMODE_10BIT))
<> 132:9baf128c2fab 604 #define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
<> 132:9baf128c2fab 605 ((ADDRESS) == I2C_DUALADDRESS_ENABLE))
<> 132:9baf128c2fab 606 #define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \
<> 132:9baf128c2fab 607 ((CALL) == I2C_GENERALCALL_ENABLE))
<> 132:9baf128c2fab 608 #define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
<> 132:9baf128c2fab 609 ((STRETCH) == I2C_NOSTRETCH_ENABLE))
<> 132:9baf128c2fab 610 #define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
<> 132:9baf128c2fab 611 ((SIZE) == I2C_MEMADD_SIZE_16BIT))
<> 132:9baf128c2fab 612 #define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0) && ((SPEED) <= 400000U))
<> 132:9baf128c2fab 613 #define IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & (uint32_t)(0xFFFFFC00U)) == 0U)
<> 132:9baf128c2fab 614 #define IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & (uint32_t)(0xFFFFFF01U)) == 0U)
<> 132:9baf128c2fab 615 #define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \
<> 132:9baf128c2fab 616 ((REQUEST) == I2C_NEXT_FRAME) || \
<> 132:9baf128c2fab 617 ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
<> 132:9baf128c2fab 618 ((REQUEST) == I2C_LAST_FRAME))
<> 132:9baf128c2fab 619 /**
<> 132:9baf128c2fab 620 * @}
<> 132:9baf128c2fab 621 */
<> 132:9baf128c2fab 622
<> 132:9baf128c2fab 623 /**
<> 132:9baf128c2fab 624 * @}
<> 132:9baf128c2fab 625 */
<> 132:9baf128c2fab 626
<> 132:9baf128c2fab 627 /* Private functions ---------------------------------------------------------*/
<> 132:9baf128c2fab 628 /** @defgroup I2C_Private_Functions I2C Private Functions
<> 132:9baf128c2fab 629 * @{
<> 132:9baf128c2fab 630 */
<> 132:9baf128c2fab 631
<> 132:9baf128c2fab 632 /**
<> 132:9baf128c2fab 633 * @}
<> 132:9baf128c2fab 634 */
<> 132:9baf128c2fab 635
<> 132:9baf128c2fab 636 /**
<> 132:9baf128c2fab 637 * @}
<> 132:9baf128c2fab 638 */
<> 132:9baf128c2fab 639
<> 132:9baf128c2fab 640 /**
<> 132:9baf128c2fab 641 * @}
<> 132:9baf128c2fab 642 */
<> 132:9baf128c2fab 643
<> 132:9baf128c2fab 644 #ifdef __cplusplus
<> 132:9baf128c2fab 645 }
<> 132:9baf128c2fab 646 #endif
<> 132:9baf128c2fab 647
<> 132:9baf128c2fab 648
<> 132:9baf128c2fab 649 #endif /* __STM32F4xx_HAL_I2C_H */
<> 132:9baf128c2fab 650
<> 132:9baf128c2fab 651 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/