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TARGET_RO359B/TOOLCHAIN_ARM_STD/RTE_Device.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
Parent:
TARGET_RO359B/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/RTE_Device.h@143:86740a56073b 
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 143:86740a56073b 1 /*
AnnaBridge 143:86740a56073b 2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
AnnaBridge 143:86740a56073b 3 * Copyright (c) 2016 - 2017 , NXP
AnnaBridge 143:86740a56073b 4 * All rights reserved.
AnnaBridge 143:86740a56073b 5 *
AnnaBridge 143:86740a56073b 6 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 143:86740a56073b 7 * are permitted provided that the following conditions are met:
AnnaBridge 143:86740a56073b 8 *
AnnaBridge 143:86740a56073b 9 * o Redistributions of source code must retain the above copyright notice, this list
AnnaBridge 143:86740a56073b 10 * of conditions and the following disclaimer.
AnnaBridge 143:86740a56073b 11 *
AnnaBridge 143:86740a56073b 12 * o Redistributions in binary form must reproduce the above copyright notice, this
AnnaBridge 143:86740a56073b 13 * list of conditions and the following disclaimer in the documentation and/or
AnnaBridge 143:86740a56073b 14 * other materials provided with the distribution.
AnnaBridge 143:86740a56073b 15 *
AnnaBridge 143:86740a56073b 16 * o Neither the name of copyright holder nor the names of its
AnnaBridge 143:86740a56073b 17 * contributors may be used to endorse or promote products derived from this
AnnaBridge 143:86740a56073b 18 * software without specific prior written permission.
AnnaBridge 143:86740a56073b 19 *
AnnaBridge 143:86740a56073b 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
AnnaBridge 143:86740a56073b 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
AnnaBridge 143:86740a56073b 22 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 143:86740a56073b 23 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
AnnaBridge 143:86740a56073b 24 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
AnnaBridge 143:86740a56073b 25 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
AnnaBridge 143:86740a56073b 26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
AnnaBridge 143:86740a56073b 27 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
AnnaBridge 143:86740a56073b 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
AnnaBridge 143:86740a56073b 29 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 143:86740a56073b 30 */
AnnaBridge 143:86740a56073b 31
AnnaBridge 143:86740a56073b 32 #ifndef __RTE_DEVICE_H
AnnaBridge 143:86740a56073b 33 #define __RTE_DEVICE_H
AnnaBridge 143:86740a56073b 34
AnnaBridge 143:86740a56073b 35 /* UART select, UART0-UART5 */
AnnaBridge 143:86740a56073b 36 #define RTE_USART0 0
AnnaBridge 143:86740a56073b 37 #define RTE_USART0_DMA_EN 0
AnnaBridge 143:86740a56073b 38 #define RTE_USART1 0
AnnaBridge 143:86740a56073b 39 #define RTE_USART1_DMA_EN 0
AnnaBridge 143:86740a56073b 40 #define RTE_USART2 0
AnnaBridge 143:86740a56073b 41 #define RTE_USART2_DMA_EN 0
AnnaBridge 143:86740a56073b 42 #define RTE_USART3 0
AnnaBridge 143:86740a56073b 43 #define RTE_USART3_DMA_EN 0
AnnaBridge 143:86740a56073b 44 #define RTE_USART4 0
AnnaBridge 143:86740a56073b 45 #define RTE_USART4_DMA_EN 0
AnnaBridge 143:86740a56073b 46 #define RTE_USART5 0
AnnaBridge 143:86740a56073b 47 #define RTE_USART5_DMA_EN 0
AnnaBridge 143:86740a56073b 48
AnnaBridge 143:86740a56073b 49 /* UART RX Buffer configuration. */
AnnaBridge 143:86740a56073b 50 #define USART_RX_BUFFER_LEN 64
AnnaBridge 143:86740a56073b 51 #define USART0_RX_BUFFER_ENABLE 0
AnnaBridge 143:86740a56073b 52 #define USART1_RX_BUFFER_ENABLE 0
AnnaBridge 143:86740a56073b 53 #define USART2_RX_BUFFER_ENABLE 0
AnnaBridge 143:86740a56073b 54 #define USART3_RX_BUFFER_ENABLE 0
AnnaBridge 143:86740a56073b 55 #define USART4_RX_BUFFER_ENABLE 0
AnnaBridge 143:86740a56073b 56 #define USART5_RX_BUFFER_ENABLE 0
AnnaBridge 143:86740a56073b 57
AnnaBridge 143:86740a56073b 58 #define RTE_USART0_DMA_TX_CH 0
AnnaBridge 143:86740a56073b 59 #define RTE_USART0_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0UART0Tx
AnnaBridge 143:86740a56073b 60 #define RTE_USART0_DMA_TX_DMAMUX_BASE DMAMUX0
AnnaBridge 143:86740a56073b 61 #define RTE_USART0_DMA_TX_DMA_BASE DMA0
AnnaBridge 143:86740a56073b 62 #define RTE_USART0_DMA_RX_CH 1
AnnaBridge 143:86740a56073b 63 #define RTE_USART0_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0UART0Rx
AnnaBridge 143:86740a56073b 64 #define RTE_USART0_DMA_RX_DMAMUX_BASE DMAMUX0
AnnaBridge 143:86740a56073b 65 #define RTE_USART0_DMA_RX_DMA_BASE DMA0
AnnaBridge 143:86740a56073b 66
AnnaBridge 143:86740a56073b 67 #define RTE_USART1_DMA_TX_CH 0
AnnaBridge 143:86740a56073b 68 #define RTE_USART1_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0UART1Tx
AnnaBridge 143:86740a56073b 69 #define RTE_USART1_DMA_TX_DMAMUX_BASE DMAMUX0
AnnaBridge 143:86740a56073b 70 #define RTE_USART1_DMA_TX_DMA_BASE DMA0
AnnaBridge 143:86740a56073b 71 #define RTE_USART1_DMA_RX_CH 1
AnnaBridge 143:86740a56073b 72 #define RTE_USART1_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0UART1Rx
AnnaBridge 143:86740a56073b 73 #define RTE_USART1_DMA_RX_DMAMUX_BASE DMAMUX0
AnnaBridge 143:86740a56073b 74 #define RTE_USART1_DMA_RX_DMA_BASE DMA0
AnnaBridge 143:86740a56073b 75
AnnaBridge 143:86740a56073b 76 #define RTE_USART2_DMA_TX_CH 0
AnnaBridge 143:86740a56073b 77 #define RTE_USART2_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0UART2Tx
AnnaBridge 143:86740a56073b 78 #define RTE_USART2_DMA_TX_DMAMUX_BASE DMAMUX0
AnnaBridge 143:86740a56073b 79 #define RTE_USART2_DMA_TX_DMA_BASE DMA0
AnnaBridge 143:86740a56073b 80 #define RTE_USART2_DMA_RX_CH 1
AnnaBridge 143:86740a56073b 81 #define RTE_USART2_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0UART2Rx
AnnaBridge 143:86740a56073b 82 #define RTE_USART2_DMA_RX_DMAMUX_BASE DMAMUX0
AnnaBridge 143:86740a56073b 83 #define RTE_USART2_DMA_RX_DMA_BASE DMA0
AnnaBridge 143:86740a56073b 84
AnnaBridge 143:86740a56073b 85 #define RTE_USART3_DMA_TX_CH 0
AnnaBridge 143:86740a56073b 86 #define RTE_USART3_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0UART3Tx
AnnaBridge 143:86740a56073b 87 #define RTE_USART3_DMA_TX_DMAMUX_BASE DMAMUX0
AnnaBridge 143:86740a56073b 88 #define RTE_USART3_DMA_TX_DMA_BASE DMA0
AnnaBridge 143:86740a56073b 89 #define RTE_USART3_DMA_RX_CH 1
AnnaBridge 143:86740a56073b 90 #define RTE_USART3_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0UART3Rx
AnnaBridge 143:86740a56073b 91 #define RTE_USART3_DMA_RX_DMAMUX_BASE DMAMUX0
AnnaBridge 143:86740a56073b 92 #define RTE_USART3_DMA_RX_DMA_BASE DMA0
AnnaBridge 143:86740a56073b 93
AnnaBridge 143:86740a56073b 94 #define RTE_USART4_DMA_TX_CH 0
AnnaBridge 143:86740a56073b 95 #define RTE_USART4_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0UART4
AnnaBridge 143:86740a56073b 96 #define RTE_USART4_DMA_TX_DMAMUX_BASE DMAMUX0
AnnaBridge 143:86740a56073b 97 #define RTE_USART4_DMA_TX_DMA_BASE DMA0
AnnaBridge 143:86740a56073b 98 #define RTE_USART4_DMA_RX_CH 1
AnnaBridge 143:86740a56073b 99 #define RTE_USART4_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0UART4
AnnaBridge 143:86740a56073b 100 #define RTE_USART4_DMA_RX_DMAMUX_BASE DMAMUX0
AnnaBridge 143:86740a56073b 101 #define RTE_USART4_DMA_RX_DMA_BASE DMA0
AnnaBridge 143:86740a56073b 102
AnnaBridge 143:86740a56073b 103 #define RTE_USART5_DMA_TX_CH 0
AnnaBridge 143:86740a56073b 104 #define RTE_USART5_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0UART5
AnnaBridge 143:86740a56073b 105 #define RTE_USART5_DMA_TX_DMAMUX_BASE DMAMUX0
AnnaBridge 143:86740a56073b 106 #define RTE_USART5_DMA_TX_DMA_BASE DMA0
AnnaBridge 143:86740a56073b 107 #define RTE_USART5_DMA_RX_CH 1
AnnaBridge 143:86740a56073b 108 #define RTE_USART5_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0UART5
AnnaBridge 143:86740a56073b 109 #define RTE_USART5_DMA_RX_DMAMUX_BASE DMAMUX0
AnnaBridge 143:86740a56073b 110 #define RTE_USART5_DMA_RX_DMA_BASE DMA0
AnnaBridge 143:86740a56073b 111
AnnaBridge 143:86740a56073b 112
AnnaBridge 143:86740a56073b 113 /* I2C select, I2C0 - I2C2. */
AnnaBridge 143:86740a56073b 114 #define RTE_I2C0 0
AnnaBridge 143:86740a56073b 115 #define RTE_I2C0_DMA_EN 0
AnnaBridge 143:86740a56073b 116 #define RTE_I2C1 0
AnnaBridge 143:86740a56073b 117 #define RTE_I2C1_DMA_EN 0
AnnaBridge 143:86740a56073b 118 #define RTE_I2C2 0
AnnaBridge 143:86740a56073b 119 #define RTE_I2C2_DMA_EN 0
AnnaBridge 143:86740a56073b 120
AnnaBridge 143:86740a56073b 121 /*I2C configuration*/
AnnaBridge 143:86740a56073b 122 #define RTE_I2C0_Master_DMA_BASE DMA0
AnnaBridge 143:86740a56073b 123 #define RTE_I2C0_Master_DMA_CH 0
AnnaBridge 143:86740a56073b 124 #define RTE_I2C0_Master_DMAMUX_BASE DMAMUX0
AnnaBridge 143:86740a56073b 125 #define RTE_I2C0_Master_PERI_SEL kDmaRequestMux0I2C0
AnnaBridge 143:86740a56073b 126
AnnaBridge 143:86740a56073b 127 #define RTE_I2C1_Master_DMA_BASE DMA0
AnnaBridge 143:86740a56073b 128 #define RTE_I2C1_Master_DMA_CH 1
AnnaBridge 143:86740a56073b 129 #define RTE_I2C1_Master_DMAMUX_BASE DMAMUX0
AnnaBridge 143:86740a56073b 130 #define RTE_I2C1_Master_PERI_SEL kDmaRequestMux0I2C1
AnnaBridge 143:86740a56073b 131
AnnaBridge 143:86740a56073b 132 #define RTE_I2C2_Master_DMA_BASE DMA0
AnnaBridge 143:86740a56073b 133 #define RTE_I2C2_Master_DMA_CH 2
AnnaBridge 143:86740a56073b 134 #define RTE_I2C2_Master_DMAMUX_BASE DMAMUX0
AnnaBridge 143:86740a56073b 135 #define RTE_I2C2_Master_PERI_SEL kDmaRequestMux0I2C2
AnnaBridge 143:86740a56073b 136
AnnaBridge 143:86740a56073b 137 /* SPI select, DSPI0 - DSPI2. */
AnnaBridge 143:86740a56073b 138 #define RTE_SPI0 0
AnnaBridge 143:86740a56073b 139 #define RTE_SPI0_DMA_EN 0
AnnaBridge 143:86740a56073b 140 #define RTE_SPI1 0
AnnaBridge 143:86740a56073b 141 #define RTE_SPI1_DMA_EN 0
AnnaBridge 143:86740a56073b 142 #define RTE_SPI2 0
AnnaBridge 143:86740a56073b 143 #define RTE_SPI2_DMA_EN 0
AnnaBridge 143:86740a56073b 144
AnnaBridge 143:86740a56073b 145 /* DSPI configuration. */
AnnaBridge 143:86740a56073b 146 #define RTE_SPI0_PCS_TO_SCK_DELAY 1000
AnnaBridge 143:86740a56073b 147 #define RTE_SPI0_SCK_TO_PSC_DELAY 1000
AnnaBridge 143:86740a56073b 148 #define RTE_SPI0_BETWEEN_TRANSFER_DELAY 1000
AnnaBridge 143:86740a56073b 149 #define RTE_SPI0_MASTER_PCS_PIN_SEL kDSPI_MasterPcs0
AnnaBridge 143:86740a56073b 150 #define RTE_SPI0_DMA_TX_CH 0
AnnaBridge 143:86740a56073b 151 #define RTE_SPI0_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0SPI0Tx
AnnaBridge 143:86740a56073b 152 #define RTE_SPI0_DMA_TX_DMAMUX_BASE DMAMUX0
AnnaBridge 143:86740a56073b 153 #define RTE_SPI0_DMA_TX_DMA_BASE DMA0
AnnaBridge 143:86740a56073b 154 #define RTE_SPI0_DMA_RX_CH 1
AnnaBridge 143:86740a56073b 155 #define RTE_SPI0_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0SPI0Rx
AnnaBridge 143:86740a56073b 156 #define RTE_SPI0_DMA_RX_DMAMUX_BASE DMAMUX0
AnnaBridge 143:86740a56073b 157 #define RTE_SPI0_DMA_RX_DMA_BASE DMA0
AnnaBridge 143:86740a56073b 158 #define RTE_SPI0_DMA_LINK_DMA_BASE DMA0
AnnaBridge 143:86740a56073b 159 #define RTE_SPI0_DMA_LINK_CH 2
AnnaBridge 143:86740a56073b 160
AnnaBridge 143:86740a56073b 161 #define RTE_SPI1_PCS_TO_SCK_DELAY 1000
AnnaBridge 143:86740a56073b 162 #define RTE_SPI1_SCK_TO_PSC_DELAY 1000
AnnaBridge 143:86740a56073b 163 #define RTE_SPI1_BETWEEN_TRANSFER_DELAY 1000
AnnaBridge 143:86740a56073b 164 #define RTE_SPI1_MASTER_PCS_PIN_SEL kDSPI_MasterPcs0
AnnaBridge 143:86740a56073b 165 #define RTE_SPI1_DMA_TX_CH 4
AnnaBridge 143:86740a56073b 166 #define RTE_SPI1_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0SPI1
AnnaBridge 143:86740a56073b 167 #define RTE_SPI1_DMA_TX_DMAMUX_BASE DMAMUX0
AnnaBridge 143:86740a56073b 168 #define RTE_SPI1_DMA_TX_DMA_BASE DMA0
AnnaBridge 143:86740a56073b 169 #define RTE_SPI1_DMA_RX_CH 3
AnnaBridge 143:86740a56073b 170 #define RTE_SPI1_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0SPI1
AnnaBridge 143:86740a56073b 171 #define RTE_SPI1_DMA_RX_DMAMUX_BASE DMAMUX0
AnnaBridge 143:86740a56073b 172 #define RTE_SPI1_DMA_RX_DMA_BASE DMA0
AnnaBridge 143:86740a56073b 173 #define RTE_SPI1_DMA_LINK_DMA_BASE DMA0
AnnaBridge 143:86740a56073b 174 #define RTE_SPI1_DMA_LINK_CH 2
AnnaBridge 143:86740a56073b 175
AnnaBridge 143:86740a56073b 176 #define RTE_SPI2_PCS_TO_SCK_DELAY 1000
AnnaBridge 143:86740a56073b 177 #define RTE_SPI2_SCK_TO_PSC_DELAY 1000
AnnaBridge 143:86740a56073b 178 #define RTE_SPI2_BETWEEN_TRANSFER_DELAY 1000
AnnaBridge 143:86740a56073b 179 #define RTE_SPI2_MASTER_PCS_PIN_SEL kDSPI_MasterPcs0
AnnaBridge 143:86740a56073b 180 #define RTE_SPI2_DMA_TX_CH 6
AnnaBridge 143:86740a56073b 181 #define RTE_SPI2_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0SPI2
AnnaBridge 143:86740a56073b 182 #define RTE_SPI2_DMA_TX_DMAMUX_BASE DMAMUX0
AnnaBridge 143:86740a56073b 183 #define RTE_SPI2_DMA_TX_DMA_BASE DMA0
AnnaBridge 143:86740a56073b 184 #define RTE_SPI2_DMA_RX_CH 7
AnnaBridge 143:86740a56073b 185 #define RTE_SPI2_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0SPI2
AnnaBridge 143:86740a56073b 186 #define RTE_SPI2_DMA_RX_DMAMUX_BASE DMAMUX0
AnnaBridge 143:86740a56073b 187 #define RTE_SPI2_DMA_RX_DMA_BASE DMA0
AnnaBridge 143:86740a56073b 188 #define RTE_SPI2_DMA_LINK_DMA_BASE DMA0
AnnaBridge 143:86740a56073b 189 #define RTE_SPI2_DMA_LINK_CH 8
AnnaBridge 143:86740a56073b 190
AnnaBridge 143:86740a56073b 191 #endif /* __RTE_DEVICE_H */