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Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

TARGET_K82F/core_ca9.h@129:0ab6a29f35bf, 2016-11-08 (annotated)

Committer:
<>
Date:
Tue Nov 08 17:28:34 2016 +0000
Revision:
129:0ab6a29f35bf
Release 129 of the mbed library



Ports for Upcoming Targets



3011: Add u-blox Sara-N target. https://github.com/ARMmbed/mbed-os/pull/3011

3099: MAX32625 https://github.com/ARMmbed/mbed-os/pull/3099

3151: Add support for FRDM-K82F https://github.com/ARMmbed/mbed-os/pull/3151

3177: New mcu k22512 fixing pr 3136 https://github.com/ARMmbed/mbed-os/pull/3177



Fixes and Changes



3008: NUCLEO_F072RB: Fix wrong timer channel number on pwm PB_5 pin https://github.com/ARMmbed/mbed-os/pull/3008

3013: STM32xx - Change how the ADC internal pins are checked before pinmap_ https://github.com/ARMmbed/mbed-os/pull/3013

3041: [nRF5] - added implementation of API of serial port flow control configuration. https://github.com/ARMmbed/mbed-os/pull/3041

3084: [nrf5] fix in Digital I/O : a gpioe pin was uninitialized badly https://github.com/ARMmbed/mbed-os/pull/3084

3009: TRNG enabled. TRNG APIs implemented. REV A/B/C/D flags removed. Warnings removed https://github.com/ARMmbed/mbed-os/pull/3009

3074: Target stm init gcc alignement https://github.com/ARMmbed/mbed-os/pull/3074

2988: Update of can_api.c fixing #2987 https://github.com/ARMmbed/mbed-os/pull/2988

3173: [Exporters] Add a device_name to microbit entry in targets.json https://github.com/ARMmbed/mbed-os/pull/3173

2969: [nRF52] - switch irq priorities of driver handlers to the lowest level https://github.com/ARMmbed/mbed-os/pull/2969

3184: #3183 Compiler warning in trng_api.c with K64F  https://github.com/ARMmbed/mbed-os/pull/3184

3104: [NuMaker] Support CAN and fix PWM CLK error https://github.com/ARMmbed/mbed-os/pull/3104

3186: MultiTech mDot - add back SPI3 pins https://github.com/ARMmbed/mbed-os/pull/3186

3075: nsapi - Add standardized return types for size and errors https://github.com/ARMmbed/mbed-os/pull/3075

3221: u-blox odin w2 drivers update https://github.com/ARMmbed/mbed-os/pull/3221

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 129:0ab6a29f35bf 1 /**************************************************************************//**
<> 129:0ab6a29f35bf 2 * @file core_ca9.h
<> 129:0ab6a29f35bf 3 * @brief CMSIS Cortex-A9 Core Peripheral Access Layer Header File
<> 129:0ab6a29f35bf 4 * @version
<> 129:0ab6a29f35bf 5 * @date 25 March 2013
<> 129:0ab6a29f35bf 6 *
<> 129:0ab6a29f35bf 7 * @note
<> 129:0ab6a29f35bf 8 *
<> 129:0ab6a29f35bf 9 ******************************************************************************/
<> 129:0ab6a29f35bf 10 /* Copyright (c) 2009 - 2012 ARM LIMITED
<> 129:0ab6a29f35bf 11
<> 129:0ab6a29f35bf 12 All rights reserved.
<> 129:0ab6a29f35bf 13 Redistribution and use in source and binary forms, with or without
<> 129:0ab6a29f35bf 14 modification, are permitted provided that the following conditions are met:
<> 129:0ab6a29f35bf 15 - Redistributions of source code must retain the above copyright
<> 129:0ab6a29f35bf 16 notice, this list of conditions and the following disclaimer.
<> 129:0ab6a29f35bf 17 - Redistributions in binary form must reproduce the above copyright
<> 129:0ab6a29f35bf 18 notice, this list of conditions and the following disclaimer in the
<> 129:0ab6a29f35bf 19 documentation and/or other materials provided with the distribution.
<> 129:0ab6a29f35bf 20 - Neither the name of ARM nor the names of its contributors may be used
<> 129:0ab6a29f35bf 21 to endorse or promote products derived from this software without
<> 129:0ab6a29f35bf 22 specific prior written permission.
<> 129:0ab6a29f35bf 23 *
<> 129:0ab6a29f35bf 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 129:0ab6a29f35bf 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 129:0ab6a29f35bf 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
<> 129:0ab6a29f35bf 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
<> 129:0ab6a29f35bf 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
<> 129:0ab6a29f35bf 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
<> 129:0ab6a29f35bf 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
<> 129:0ab6a29f35bf 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
<> 129:0ab6a29f35bf 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
<> 129:0ab6a29f35bf 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
<> 129:0ab6a29f35bf 34 POSSIBILITY OF SUCH DAMAGE.
<> 129:0ab6a29f35bf 35 ---------------------------------------------------------------------------*/
<> 129:0ab6a29f35bf 36
<> 129:0ab6a29f35bf 37
<> 129:0ab6a29f35bf 38 #if defined ( __ICCARM__ )
<> 129:0ab6a29f35bf 39 #pragma system_include /* treat file as system include file for MISRA check */
<> 129:0ab6a29f35bf 40 #endif
<> 129:0ab6a29f35bf 41
<> 129:0ab6a29f35bf 42 #ifdef __cplusplus
<> 129:0ab6a29f35bf 43 extern "C" {
<> 129:0ab6a29f35bf 44 #endif
<> 129:0ab6a29f35bf 45
<> 129:0ab6a29f35bf 46 #ifndef __CORE_CA9_H_GENERIC
<> 129:0ab6a29f35bf 47 #define __CORE_CA9_H_GENERIC
<> 129:0ab6a29f35bf 48
<> 129:0ab6a29f35bf 49
<> 129:0ab6a29f35bf 50 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
<> 129:0ab6a29f35bf 51 CMSIS violates the following MISRA-C:2004 rules:
<> 129:0ab6a29f35bf 52
<> 129:0ab6a29f35bf 53 \li Required Rule 8.5, object/function definition in header file.<br>
<> 129:0ab6a29f35bf 54 Function definitions in header files are used to allow 'inlining'.
<> 129:0ab6a29f35bf 55
<> 129:0ab6a29f35bf 56 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
<> 129:0ab6a29f35bf 57 Unions are used for effective representation of core registers.
<> 129:0ab6a29f35bf 58
<> 129:0ab6a29f35bf 59 \li Advisory Rule 19.7, Function-like macro defined.<br>
<> 129:0ab6a29f35bf 60 Function-like macros are used to allow more efficient code.
<> 129:0ab6a29f35bf 61 */
<> 129:0ab6a29f35bf 62
<> 129:0ab6a29f35bf 63
<> 129:0ab6a29f35bf 64 /*******************************************************************************
<> 129:0ab6a29f35bf 65 * CMSIS definitions
<> 129:0ab6a29f35bf 66 ******************************************************************************/
<> 129:0ab6a29f35bf 67 /** \ingroup Cortex_A9
<> 129:0ab6a29f35bf 68 @{
<> 129:0ab6a29f35bf 69 */
<> 129:0ab6a29f35bf 70
<> 129:0ab6a29f35bf 71 /* CMSIS CA9 definitions */
<> 129:0ab6a29f35bf 72 #define __CA9_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
<> 129:0ab6a29f35bf 73 #define __CA9_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */
<> 129:0ab6a29f35bf 74 #define __CA9_CMSIS_VERSION ((__CA9_CMSIS_VERSION_MAIN << 16) | \
<> 129:0ab6a29f35bf 75 __CA9_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
<> 129:0ab6a29f35bf 76
<> 129:0ab6a29f35bf 77 #define __CORTEX_A (0x09) /*!< Cortex-A Core */
<> 129:0ab6a29f35bf 78
<> 129:0ab6a29f35bf 79
<> 129:0ab6a29f35bf 80 #if defined ( __CC_ARM )
<> 129:0ab6a29f35bf 81 #define __ASM __asm /*!< asm keyword for ARM Compiler */
<> 129:0ab6a29f35bf 82 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
<> 129:0ab6a29f35bf 83 #define __STATIC_INLINE static __inline
<> 129:0ab6a29f35bf 84 #define __STATIC_ASM static __asm
<> 129:0ab6a29f35bf 85
<> 129:0ab6a29f35bf 86 #elif defined ( __ICCARM__ )
<> 129:0ab6a29f35bf 87 #define __ASM __asm /*!< asm keyword for IAR Compiler */
<> 129:0ab6a29f35bf 88 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
<> 129:0ab6a29f35bf 89 #define __STATIC_INLINE static inline
<> 129:0ab6a29f35bf 90 #define __STATIC_ASM static __asm
<> 129:0ab6a29f35bf 91
<> 129:0ab6a29f35bf 92 #include <stdint.h>
<> 129:0ab6a29f35bf 93 inline uint32_t __get_PSR(void) {
<> 129:0ab6a29f35bf 94 __ASM("mrs r0, cpsr");
<> 129:0ab6a29f35bf 95 }
<> 129:0ab6a29f35bf 96
<> 129:0ab6a29f35bf 97 #elif defined ( __TMS470__ )
<> 129:0ab6a29f35bf 98 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
<> 129:0ab6a29f35bf 99 #define __STATIC_INLINE static inline
<> 129:0ab6a29f35bf 100 #define __STATIC_ASM static __asm
<> 129:0ab6a29f35bf 101
<> 129:0ab6a29f35bf 102 #elif defined ( __GNUC__ )
<> 129:0ab6a29f35bf 103 #define __ASM __asm /*!< asm keyword for GNU Compiler */
<> 129:0ab6a29f35bf 104 #define __INLINE inline /*!< inline keyword for GNU Compiler */
<> 129:0ab6a29f35bf 105 #define __STATIC_INLINE static inline
<> 129:0ab6a29f35bf 106 #define __STATIC_ASM static __asm
<> 129:0ab6a29f35bf 107
<> 129:0ab6a29f35bf 108 #elif defined ( __TASKING__ )
<> 129:0ab6a29f35bf 109 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
<> 129:0ab6a29f35bf 110 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
<> 129:0ab6a29f35bf 111 #define __STATIC_INLINE static inline
<> 129:0ab6a29f35bf 112 #define __STATIC_ASM static __asm
<> 129:0ab6a29f35bf 113
<> 129:0ab6a29f35bf 114 #endif
<> 129:0ab6a29f35bf 115
<> 129:0ab6a29f35bf 116 /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
<> 129:0ab6a29f35bf 117 */
<> 129:0ab6a29f35bf 118 #if defined ( __CC_ARM )
<> 129:0ab6a29f35bf 119 #if defined __TARGET_FPU_VFP
<> 129:0ab6a29f35bf 120 #if (__FPU_PRESENT == 1)
<> 129:0ab6a29f35bf 121 #define __FPU_USED 1
<> 129:0ab6a29f35bf 122 #else
<> 129:0ab6a29f35bf 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 129:0ab6a29f35bf 124 #define __FPU_USED 0
<> 129:0ab6a29f35bf 125 #endif
<> 129:0ab6a29f35bf 126 #else
<> 129:0ab6a29f35bf 127 #define __FPU_USED 0
<> 129:0ab6a29f35bf 128 #endif
<> 129:0ab6a29f35bf 129
<> 129:0ab6a29f35bf 130 #elif defined ( __ICCARM__ )
<> 129:0ab6a29f35bf 131 #if defined __ARMVFP__
<> 129:0ab6a29f35bf 132 #if (__FPU_PRESENT == 1)
<> 129:0ab6a29f35bf 133 #define __FPU_USED 1
<> 129:0ab6a29f35bf 134 #else
<> 129:0ab6a29f35bf 135 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 129:0ab6a29f35bf 136 #define __FPU_USED 0
<> 129:0ab6a29f35bf 137 #endif
<> 129:0ab6a29f35bf 138 #else
<> 129:0ab6a29f35bf 139 #define __FPU_USED 0
<> 129:0ab6a29f35bf 140 #endif
<> 129:0ab6a29f35bf 141
<> 129:0ab6a29f35bf 142 #elif defined ( __TMS470__ )
<> 129:0ab6a29f35bf 143 #if defined __TI_VFP_SUPPORT__
<> 129:0ab6a29f35bf 144 #if (__FPU_PRESENT == 1)
<> 129:0ab6a29f35bf 145 #define __FPU_USED 1
<> 129:0ab6a29f35bf 146 #else
<> 129:0ab6a29f35bf 147 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 129:0ab6a29f35bf 148 #define __FPU_USED 0
<> 129:0ab6a29f35bf 149 #endif
<> 129:0ab6a29f35bf 150 #else
<> 129:0ab6a29f35bf 151 #define __FPU_USED 0
<> 129:0ab6a29f35bf 152 #endif
<> 129:0ab6a29f35bf 153
<> 129:0ab6a29f35bf 154 #elif defined ( __GNUC__ )
<> 129:0ab6a29f35bf 155 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
<> 129:0ab6a29f35bf 156 #if (__FPU_PRESENT == 1)
<> 129:0ab6a29f35bf 157 #define __FPU_USED 1
<> 129:0ab6a29f35bf 158 #else
<> 129:0ab6a29f35bf 159 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 129:0ab6a29f35bf 160 #define __FPU_USED 0
<> 129:0ab6a29f35bf 161 #endif
<> 129:0ab6a29f35bf 162 #else
<> 129:0ab6a29f35bf 163 #define __FPU_USED 0
<> 129:0ab6a29f35bf 164 #endif
<> 129:0ab6a29f35bf 165
<> 129:0ab6a29f35bf 166 #elif defined ( __TASKING__ )
<> 129:0ab6a29f35bf 167 #if defined __FPU_VFP__
<> 129:0ab6a29f35bf 168 #if (__FPU_PRESENT == 1)
<> 129:0ab6a29f35bf 169 #define __FPU_USED 1
<> 129:0ab6a29f35bf 170 #else
<> 129:0ab6a29f35bf 171 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
<> 129:0ab6a29f35bf 172 #define __FPU_USED 0
<> 129:0ab6a29f35bf 173 #endif
<> 129:0ab6a29f35bf 174 #else
<> 129:0ab6a29f35bf 175 #define __FPU_USED 0
<> 129:0ab6a29f35bf 176 #endif
<> 129:0ab6a29f35bf 177 #endif
<> 129:0ab6a29f35bf 178
<> 129:0ab6a29f35bf 179 #include <stdint.h> /*!< standard types definitions */
<> 129:0ab6a29f35bf 180 #include "core_caInstr.h" /*!< Core Instruction Access */
<> 129:0ab6a29f35bf 181 #include "core_caFunc.h" /*!< Core Function Access */
<> 129:0ab6a29f35bf 182 #include "core_cm4_simd.h" /*!< Compiler specific SIMD Intrinsics */
<> 129:0ab6a29f35bf 183
<> 129:0ab6a29f35bf 184 #endif /* __CORE_CA9_H_GENERIC */
<> 129:0ab6a29f35bf 185
<> 129:0ab6a29f35bf 186 #ifndef __CMSIS_GENERIC
<> 129:0ab6a29f35bf 187
<> 129:0ab6a29f35bf 188 #ifndef __CORE_CA9_H_DEPENDANT
<> 129:0ab6a29f35bf 189 #define __CORE_CA9_H_DEPENDANT
<> 129:0ab6a29f35bf 190
<> 129:0ab6a29f35bf 191 /* check device defines and use defaults */
<> 129:0ab6a29f35bf 192 #if defined __CHECK_DEVICE_DEFINES
<> 129:0ab6a29f35bf 193 #ifndef __CA9_REV
<> 129:0ab6a29f35bf 194 #define __CA9_REV 0x0000
<> 129:0ab6a29f35bf 195 #warning "__CA9_REV not defined in device header file; using default!"
<> 129:0ab6a29f35bf 196 #endif
<> 129:0ab6a29f35bf 197
<> 129:0ab6a29f35bf 198 #ifndef __FPU_PRESENT
<> 129:0ab6a29f35bf 199 #define __FPU_PRESENT 1
<> 129:0ab6a29f35bf 200 #warning "__FPU_PRESENT not defined in device header file; using default!"
<> 129:0ab6a29f35bf 201 #endif
<> 129:0ab6a29f35bf 202
<> 129:0ab6a29f35bf 203 #ifndef __Vendor_SysTickConfig
<> 129:0ab6a29f35bf 204 #define __Vendor_SysTickConfig 1
<> 129:0ab6a29f35bf 205 #endif
<> 129:0ab6a29f35bf 206
<> 129:0ab6a29f35bf 207 #if __Vendor_SysTickConfig == 0
<> 129:0ab6a29f35bf 208 #error "__Vendor_SysTickConfig set to 0, but vendor systick timer must be supplied for Cortex-A9"
<> 129:0ab6a29f35bf 209 #endif
<> 129:0ab6a29f35bf 210 #endif
<> 129:0ab6a29f35bf 211
<> 129:0ab6a29f35bf 212 /* IO definitions (access restrictions to peripheral registers) */
<> 129:0ab6a29f35bf 213 /**
<> 129:0ab6a29f35bf 214 \defgroup CMSIS_glob_defs CMSIS Global Defines
<> 129:0ab6a29f35bf 215
<> 129:0ab6a29f35bf 216 <strong>IO Type Qualifiers</strong> are used
<> 129:0ab6a29f35bf 217 \li to specify the access to peripheral variables.
<> 129:0ab6a29f35bf 218 \li for automatic generation of peripheral register debug information.
<> 129:0ab6a29f35bf 219 */
<> 129:0ab6a29f35bf 220 #ifdef __cplusplus
<> 129:0ab6a29f35bf 221 #define __I volatile /*!< Defines 'read only' permissions */
<> 129:0ab6a29f35bf 222 #else
<> 129:0ab6a29f35bf 223 #define __I volatile const /*!< Defines 'read only' permissions */
<> 129:0ab6a29f35bf 224 #endif
<> 129:0ab6a29f35bf 225 #define __O volatile /*!< Defines 'write only' permissions */
<> 129:0ab6a29f35bf 226 #define __IO volatile /*!< Defines 'read / write' permissions */
<> 129:0ab6a29f35bf 227
<> 129:0ab6a29f35bf 228 /*@} end of group Cortex_A9 */
<> 129:0ab6a29f35bf 229
<> 129:0ab6a29f35bf 230
<> 129:0ab6a29f35bf 231 /*******************************************************************************
<> 129:0ab6a29f35bf 232 * Register Abstraction
<> 129:0ab6a29f35bf 233 ******************************************************************************/
<> 129:0ab6a29f35bf 234 /** \defgroup CMSIS_core_register Defines and Type Definitions
<> 129:0ab6a29f35bf 235 \brief Type definitions and defines for Cortex-A processor based devices.
<> 129:0ab6a29f35bf 236 */
<> 129:0ab6a29f35bf 237
<> 129:0ab6a29f35bf 238 /** \ingroup CMSIS_core_register
<> 129:0ab6a29f35bf 239 \defgroup CMSIS_CORE Status and Control Registers
<> 129:0ab6a29f35bf 240 \brief Core Register type definitions.
<> 129:0ab6a29f35bf 241 @{
<> 129:0ab6a29f35bf 242 */
<> 129:0ab6a29f35bf 243
<> 129:0ab6a29f35bf 244 /** \brief Union type to access the Application Program Status Register (APSR).
<> 129:0ab6a29f35bf 245 */
<> 129:0ab6a29f35bf 246 typedef union
<> 129:0ab6a29f35bf 247 {
<> 129:0ab6a29f35bf 248 struct
<> 129:0ab6a29f35bf 249 {
<> 129:0ab6a29f35bf 250 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
<> 129:0ab6a29f35bf 251 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
<> 129:0ab6a29f35bf 252 uint32_t reserved1:7; /*!< bit: 20..23 Reserved */
<> 129:0ab6a29f35bf 253 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
<> 129:0ab6a29f35bf 254 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
<> 129:0ab6a29f35bf 255 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
<> 129:0ab6a29f35bf 256 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
<> 129:0ab6a29f35bf 257 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
<> 129:0ab6a29f35bf 258 } b; /*!< Structure used for bit access */
<> 129:0ab6a29f35bf 259 uint32_t w; /*!< Type used for word access */
<> 129:0ab6a29f35bf 260 } APSR_Type;
<> 129:0ab6a29f35bf 261
<> 129:0ab6a29f35bf 262
<> 129:0ab6a29f35bf 263 /*@} end of group CMSIS_CORE */
<> 129:0ab6a29f35bf 264
<> 129:0ab6a29f35bf 265 /*@} end of CMSIS_Core_FPUFunctions */
<> 129:0ab6a29f35bf 266
<> 129:0ab6a29f35bf 267
<> 129:0ab6a29f35bf 268 #endif /* __CORE_CA9_H_GENERIC */
<> 129:0ab6a29f35bf 269
<> 129:0ab6a29f35bf 270 #endif /* __CMSIS_GENERIC */
<> 129:0ab6a29f35bf 271
<> 129:0ab6a29f35bf 272 #ifdef __cplusplus
<> 129:0ab6a29f35bf 273 }
<> 129:0ab6a29f35bf 274
<> 129:0ab6a29f35bf 275
<> 129:0ab6a29f35bf 276 #endif