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TARGET_EFM32HG_STK3400/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/efm32hg308f64.h@138:093f2bd7b9eb, 2017-03-14 (annotated)

Committer:
<>
Date:
Tue Mar 14 16:20:51 2017 +0000
Revision:
138:093f2bd7b9eb
Parent:
128:9bcdf88f62b0
Child:
139:856d2700e60b
Release 138 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



3716: fix for issue #3715: correction in startup files for ARM and IAR, alignment of system_stm32f429xx.c files https://github.com/ARMmbed/mbed-os/pull/3716

3741: STM32 remove warning in hal_tick_32b.c file https://github.com/ARMmbed/mbed-os/pull/3741

3780: STM32L4 : Fix GPIO G port compatibility https://github.com/ARMmbed/mbed-os/pull/3780

3831: NCS36510: SPISLAVE enabled (Conflict resolved) https://github.com/ARMmbed/mbed-os/pull/3831

3836: Allow to redefine nRF's PSTORAGE_NUM_OF_PAGES outside of the mbed-os https://github.com/ARMmbed/mbed-os/pull/3836

3840: STM32: gpio SPEED - always set High Speed by default https://github.com/ARMmbed/mbed-os/pull/3840

3844: STM32 GPIO: Typo correction. Update comment (GPIO_IP_WITHOUT_BRR) https://github.com/ARMmbed/mbed-os/pull/3844

3850: STM32: change spi error to debug warning https://github.com/ARMmbed/mbed-os/pull/3850

3860: Define GPIO_IP_WITHOUT_BRR for xDot platform https://github.com/ARMmbed/mbed-os/pull/3860

3880: DISCO_F469NI: allow the use of CAN2 instance when CAN1 is not activated https://github.com/ARMmbed/mbed-os/pull/3880

3795: Fix pwm period calc https://github.com/ARMmbed/mbed-os/pull/3795

3828: STM32 CAN API: correct format and type https://github.com/ARMmbed/mbed-os/pull/3828

3842: TARGET_NRF: corrected spi_init() to properly handle re-initialization https://github.com/ARMmbed/mbed-os/pull/3842

3843: STM32L476xG: set APB2 clock to 80MHz (instead of 40MHz) https://github.com/ARMmbed/mbed-os/pull/3843

3879: NUCLEO_F446ZE: Add missing AnalogIn pins on PF_3, PF_5 and PF_10. https://github.com/ARMmbed/mbed-os/pull/3879

3902: Fix heap and stack size for NUCLEO_F746ZG https://github.com/ARMmbed/mbed-os/pull/3902

3829: can_write(): return error code when no tx mailboxes are available https://github.com/ARMmbed/mbed-os/pull/3829

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 128:9bcdf88f62b0 1 /**************************************************************************//**
<> 128:9bcdf88f62b0 2 * @file efm32hg308f64.h
<> 128:9bcdf88f62b0 3 * @brief CMSIS Cortex-M Peripheral Access Layer Header File
<> 128:9bcdf88f62b0 4 * for EFM32HG308F64
<> 128:9bcdf88f62b0 5 * @version 5.0.0
<> 128:9bcdf88f62b0 6 ******************************************************************************
<> 128:9bcdf88f62b0 7 * @section License
<> 128:9bcdf88f62b0 8 * <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
<> 128:9bcdf88f62b0 9 ******************************************************************************
<> 128:9bcdf88f62b0 10 *
<> 128:9bcdf88f62b0 11 * Permission is granted to anyone to use this software for any purpose,
<> 128:9bcdf88f62b0 12 * including commercial applications, and to alter it and redistribute it
<> 128:9bcdf88f62b0 13 * freely, subject to the following restrictions:
<> 128:9bcdf88f62b0 14 *
<> 128:9bcdf88f62b0 15 * 1. The origin of this software must not be misrepresented; you must not
<> 128:9bcdf88f62b0 16 * claim that you wrote the original software.@n
<> 128:9bcdf88f62b0 17 * 2. Altered source versions must be plainly marked as such, and must not be
<> 128:9bcdf88f62b0 18 * misrepresented as being the original software.@n
<> 128:9bcdf88f62b0 19 * 3. This notice may not be removed or altered from any source distribution.
<> 128:9bcdf88f62b0 20 *
<> 128:9bcdf88f62b0 21 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
<> 128:9bcdf88f62b0 22 * has no obligation to support this Software. Silicon Laboratories, Inc. is
<> 128:9bcdf88f62b0 23 * providing the Software "AS IS", with no express or implied warranties of any
<> 128:9bcdf88f62b0 24 * kind, including, but not limited to, any implied warranties of
<> 128:9bcdf88f62b0 25 * merchantability or fitness for any particular purpose or warranties against
<> 128:9bcdf88f62b0 26 * infringement of any proprietary rights of a third party.
<> 128:9bcdf88f62b0 27 *
<> 128:9bcdf88f62b0 28 * Silicon Laboratories, Inc. will not be liable for any consequential,
<> 128:9bcdf88f62b0 29 * incidental, or special damages, or any other relief, or for any claim by
<> 128:9bcdf88f62b0 30 * any third party, arising from your use of this Software.
<> 128:9bcdf88f62b0 31 *
<> 128:9bcdf88f62b0 32 *****************************************************************************/
<> 128:9bcdf88f62b0 33
<> 128:9bcdf88f62b0 34 #ifndef EFM32HG308F64_H
<> 128:9bcdf88f62b0 35 #define EFM32HG308F64_H
<> 128:9bcdf88f62b0 36
<> 128:9bcdf88f62b0 37 #ifdef __cplusplus
<> 128:9bcdf88f62b0 38 extern "C" {
<> 128:9bcdf88f62b0 39 #endif
<> 128:9bcdf88f62b0 40
<> 128:9bcdf88f62b0 41 /**************************************************************************//**
<> 128:9bcdf88f62b0 42 * @addtogroup Parts
<> 128:9bcdf88f62b0 43 * @{
<> 128:9bcdf88f62b0 44 *****************************************************************************/
<> 128:9bcdf88f62b0 45
<> 128:9bcdf88f62b0 46 /**************************************************************************//**
<> 128:9bcdf88f62b0 47 * @defgroup EFM32HG308F64 EFM32HG308F64
<> 128:9bcdf88f62b0 48 * @{
<> 128:9bcdf88f62b0 49 *****************************************************************************/
<> 128:9bcdf88f62b0 50
<> 128:9bcdf88f62b0 51 /** Interrupt Number Definition */
<> 128:9bcdf88f62b0 52 typedef enum IRQn
<> 128:9bcdf88f62b0 53 {
<> 128:9bcdf88f62b0 54 /****** Cortex-M0+ Processor Exceptions Numbers *****************************************/
<> 128:9bcdf88f62b0 55 NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M0+ Non Maskable Interrupt */
<> 128:9bcdf88f62b0 56 HardFault_IRQn = -13, /*!< -13 Cortex-M0+ Hard Fault Interrupt */
<> 128:9bcdf88f62b0 57 SVCall_IRQn = -5, /*!< -5 Cortex-M0+ SV Call Interrupt */
<> 128:9bcdf88f62b0 58 PendSV_IRQn = -2, /*!< -2 Cortex-M0+ Pend SV Interrupt */
<> 128:9bcdf88f62b0 59 SysTick_IRQn = -1, /*!< -1 Cortex-M0+ System Tick Interrupt */
<> 128:9bcdf88f62b0 60
<> 128:9bcdf88f62b0 61 /****** EFM32HG Peripheral Interrupt Numbers ********************************************/
<> 128:9bcdf88f62b0 62 DMA_IRQn = 0, /*!< 0 EFM32 DMA Interrupt */
<> 128:9bcdf88f62b0 63 GPIO_EVEN_IRQn = 1, /*!< 1 EFM32 GPIO_EVEN Interrupt */
<> 128:9bcdf88f62b0 64 TIMER0_IRQn = 2, /*!< 2 EFM32 TIMER0 Interrupt */
<> 128:9bcdf88f62b0 65 ACMP0_IRQn = 3, /*!< 3 EFM32 ACMP0 Interrupt */
<> 128:9bcdf88f62b0 66 I2C0_IRQn = 5, /*!< 5 EFM32 I2C0 Interrupt */
<> 128:9bcdf88f62b0 67 GPIO_ODD_IRQn = 6, /*!< 6 EFM32 GPIO_ODD Interrupt */
<> 128:9bcdf88f62b0 68 TIMER1_IRQn = 7, /*!< 7 EFM32 TIMER1 Interrupt */
<> 128:9bcdf88f62b0 69 USART1_RX_IRQn = 8, /*!< 8 EFM32 USART1_RX Interrupt */
<> 128:9bcdf88f62b0 70 USART1_TX_IRQn = 9, /*!< 9 EFM32 USART1_TX Interrupt */
<> 128:9bcdf88f62b0 71 LEUART0_IRQn = 10, /*!< 10 EFM32 LEUART0 Interrupt */
<> 128:9bcdf88f62b0 72 PCNT0_IRQn = 11, /*!< 11 EFM32 PCNT0 Interrupt */
<> 128:9bcdf88f62b0 73 RTC_IRQn = 12, /*!< 12 EFM32 RTC Interrupt */
<> 128:9bcdf88f62b0 74 CMU_IRQn = 13, /*!< 13 EFM32 CMU Interrupt */
<> 128:9bcdf88f62b0 75 VCMP_IRQn = 14, /*!< 14 EFM32 VCMP Interrupt */
<> 128:9bcdf88f62b0 76 MSC_IRQn = 15, /*!< 15 EFM32 MSC Interrupt */
<> 128:9bcdf88f62b0 77 USART0_RX_IRQn = 17, /*!< 17 EFM32 USART0_RX Interrupt */
<> 128:9bcdf88f62b0 78 USART0_TX_IRQn = 18, /*!< 18 EFM32 USART0_TX Interrupt */
<> 128:9bcdf88f62b0 79 USB_IRQn = 19, /*!< 19 EFM32 USB Interrupt */
<> 128:9bcdf88f62b0 80 TIMER2_IRQn = 20, /*!< 20 EFM32 TIMER2 Interrupt */
<> 128:9bcdf88f62b0 81 } IRQn_Type;
<> 128:9bcdf88f62b0 82
<> 128:9bcdf88f62b0 83 /**************************************************************************//**
<> 128:9bcdf88f62b0 84 * @defgroup EFM32HG308F64_Core EFM32HG308F64 Core
<> 128:9bcdf88f62b0 85 * @{
<> 128:9bcdf88f62b0 86 * @brief Processor and Core Peripheral Section
<> 128:9bcdf88f62b0 87 *****************************************************************************/
<> 128:9bcdf88f62b0 88 #define __MPU_PRESENT 0 /**< MPU not present */
<> 128:9bcdf88f62b0 89 #define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */
<> 128:9bcdf88f62b0 90 #define __NVIC_PRIO_BITS 2 /**< NVIC interrupt priority bits */
<> 128:9bcdf88f62b0 91 #define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
<> 128:9bcdf88f62b0 92
<> 128:9bcdf88f62b0 93 /** @} End of group EFM32HG308F64_Core */
<> 128:9bcdf88f62b0 94
<> 128:9bcdf88f62b0 95 /**************************************************************************//**
<> 128:9bcdf88f62b0 96 * @defgroup EFM32HG308F64_Part EFM32HG308F64 Part
<> 128:9bcdf88f62b0 97 * @{
<> 128:9bcdf88f62b0 98 ******************************************************************************/
<> 128:9bcdf88f62b0 99
<> 128:9bcdf88f62b0 100 /** Part family */
<> 128:9bcdf88f62b0 101 #define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */
<> 128:9bcdf88f62b0 102 #define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */
<> 128:9bcdf88f62b0 103 #define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */
<> 128:9bcdf88f62b0 104 #define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */
<> 128:9bcdf88f62b0 105 #define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */
<> 128:9bcdf88f62b0 106 #define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */
<> 128:9bcdf88f62b0 107
<> 128:9bcdf88f62b0 108 /* If part number is not defined as compiler option, define it */
<> 128:9bcdf88f62b0 109 #if !defined(EFM32HG308F64)
<> 128:9bcdf88f62b0 110 #define EFM32HG308F64 1 /**< Happy Gecko Part */
<> 128:9bcdf88f62b0 111 #endif
<> 128:9bcdf88f62b0 112
<> 128:9bcdf88f62b0 113 /** Configure part number */
<> 128:9bcdf88f62b0 114 #define PART_NUMBER "EFM32HG308F64" /**< Part Number */
<> 128:9bcdf88f62b0 115
<> 128:9bcdf88f62b0 116 /** Memory Base addresses and limits */
<> 128:9bcdf88f62b0 117 #define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
<> 128:9bcdf88f62b0 118 #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
<> 128:9bcdf88f62b0 119 #define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
<> 128:9bcdf88f62b0 120 #define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
<> 128:9bcdf88f62b0 121 #define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
<> 128:9bcdf88f62b0 122 #define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
<> 128:9bcdf88f62b0 123 #define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
<> 128:9bcdf88f62b0 124 #define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
<> 128:9bcdf88f62b0 125 #define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */
<> 128:9bcdf88f62b0 126 #define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */
<> 128:9bcdf88f62b0 127 #define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */
<> 128:9bcdf88f62b0 128 #define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */
<> 128:9bcdf88f62b0 129 #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
<> 128:9bcdf88f62b0 130 #define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
<> 128:9bcdf88f62b0 131 #define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
<> 128:9bcdf88f62b0 132 #define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
<> 128:9bcdf88f62b0 133 #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
<> 128:9bcdf88f62b0 134 #define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */
<> 128:9bcdf88f62b0 135 #define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */
<> 128:9bcdf88f62b0 136 #define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */
<> 128:9bcdf88f62b0 137 #define DEVICE_MEM_BASE ((uint32_t) 0xF0040000UL) /**< DEVICE base address */
<> 128:9bcdf88f62b0 138 #define DEVICE_MEM_SIZE ((uint32_t) 0x1000UL) /**< DEVICE available address space */
<> 128:9bcdf88f62b0 139 #define DEVICE_MEM_END ((uint32_t) 0xF0040FFFUL) /**< DEVICE end address */
<> 128:9bcdf88f62b0 140 #define DEVICE_MEM_BITS ((uint32_t) 0x12UL) /**< DEVICE used bits */
<> 128:9bcdf88f62b0 141 #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
<> 128:9bcdf88f62b0 142 #define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */
<> 128:9bcdf88f62b0 143 #define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */
<> 128:9bcdf88f62b0 144 #define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */
<> 128:9bcdf88f62b0 145
<> 128:9bcdf88f62b0 146 /** Flash and SRAM limits for EFM32HG308F64 */
<> 128:9bcdf88f62b0 147 #define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
<> 128:9bcdf88f62b0 148 #define FLASH_SIZE (0x00010000UL) /**< Available Flash Memory */
<> 128:9bcdf88f62b0 149 #define FLASH_PAGE_SIZE 1024 /**< Flash Memory page size */
<> 128:9bcdf88f62b0 150 #define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
<> 128:9bcdf88f62b0 151 #define SRAM_SIZE (0x00002000UL) /**< Available SRAM Memory */
<> 128:9bcdf88f62b0 152 #define __CM0PLUS_REV 0x001 /**< Cortex-M0+ Core revision r0p1 */
<> 128:9bcdf88f62b0 153 #define PRS_CHAN_COUNT 6 /**< Number of PRS channels */
<> 128:9bcdf88f62b0 154 #define DMA_CHAN_COUNT 6 /**< Number of DMA channels */
<> 128:9bcdf88f62b0 155 #define EXT_IRQ_COUNT 21 /**< Number of External (NVIC) interrupts */
<> 128:9bcdf88f62b0 156
<> 128:9bcdf88f62b0 157 /** AF channels connect the different on-chip peripherals with the af-mux */
<> 128:9bcdf88f62b0 158 #define AFCHAN_MAX 42
<> 128:9bcdf88f62b0 159 #define AFCHANLOC_MAX 7
<> 128:9bcdf88f62b0 160 /** Analog AF channels */
<> 128:9bcdf88f62b0 161 #define AFACHAN_MAX 27
<> 128:9bcdf88f62b0 162
<> 128:9bcdf88f62b0 163 /* Part number capabilities */
<> 128:9bcdf88f62b0 164
<> 128:9bcdf88f62b0 165 #define TIMER_PRESENT /**< TIMER is available in this part */
<> 128:9bcdf88f62b0 166 #define TIMER_COUNT 3 /**< 3 TIMERs available */
<> 128:9bcdf88f62b0 167 #define ACMP_PRESENT /**< ACMP is available in this part */
<> 128:9bcdf88f62b0 168 #define ACMP_COUNT 1 /**< 1 ACMPs available */
<> 128:9bcdf88f62b0 169 #define USART_PRESENT /**< USART is available in this part */
<> 128:9bcdf88f62b0 170 #define USART_COUNT 2 /**< 2 USARTs available */
<> 128:9bcdf88f62b0 171 #define LEUART_PRESENT /**< LEUART is available in this part */
<> 128:9bcdf88f62b0 172 #define LEUART_COUNT 1 /**< 1 LEUARTs available */
<> 128:9bcdf88f62b0 173 #define PCNT_PRESENT /**< PCNT is available in this part */
<> 128:9bcdf88f62b0 174 #define PCNT_COUNT 1 /**< 1 PCNTs available */
<> 128:9bcdf88f62b0 175 #define I2C_PRESENT /**< I2C is available in this part */
<> 128:9bcdf88f62b0 176 #define I2C_COUNT 1 /**< 1 I2Cs available */
<> 128:9bcdf88f62b0 177 #define DMA_PRESENT
<> 128:9bcdf88f62b0 178 #define DMA_COUNT 1
<> 128:9bcdf88f62b0 179 #define LE_PRESENT
<> 128:9bcdf88f62b0 180 #define LE_COUNT 1
<> 128:9bcdf88f62b0 181 #define USBC_PRESENT
<> 128:9bcdf88f62b0 182 #define USBC_COUNT 1
<> 128:9bcdf88f62b0 183 #define USBLE_PRESENT
<> 128:9bcdf88f62b0 184 #define USBLE_COUNT 1
<> 128:9bcdf88f62b0 185 #define USB_PRESENT
<> 128:9bcdf88f62b0 186 #define USB_COUNT 1
<> 128:9bcdf88f62b0 187 #define MSC_PRESENT
<> 128:9bcdf88f62b0 188 #define MSC_COUNT 1
<> 128:9bcdf88f62b0 189 #define EMU_PRESENT
<> 128:9bcdf88f62b0 190 #define EMU_COUNT 1
<> 128:9bcdf88f62b0 191 #define RMU_PRESENT
<> 128:9bcdf88f62b0 192 #define RMU_COUNT 1
<> 128:9bcdf88f62b0 193 #define CMU_PRESENT
<> 128:9bcdf88f62b0 194 #define CMU_COUNT 1
<> 128:9bcdf88f62b0 195 #define PRS_PRESENT
<> 128:9bcdf88f62b0 196 #define PRS_COUNT 1
<> 128:9bcdf88f62b0 197 #define GPIO_PRESENT
<> 128:9bcdf88f62b0 198 #define GPIO_COUNT 1
<> 128:9bcdf88f62b0 199 #define VCMP_PRESENT
<> 128:9bcdf88f62b0 200 #define VCMP_COUNT 1
<> 128:9bcdf88f62b0 201 #define RTC_PRESENT
<> 128:9bcdf88f62b0 202 #define RTC_COUNT 1
<> 128:9bcdf88f62b0 203 #define HFXTAL_PRESENT
<> 128:9bcdf88f62b0 204 #define HFXTAL_COUNT 1
<> 128:9bcdf88f62b0 205 #define LFXTAL_PRESENT
<> 128:9bcdf88f62b0 206 #define LFXTAL_COUNT 1
<> 128:9bcdf88f62b0 207 #define USHFRCO_PRESENT
<> 128:9bcdf88f62b0 208 #define USHFRCO_COUNT 1
<> 128:9bcdf88f62b0 209 #define WDOG_PRESENT
<> 128:9bcdf88f62b0 210 #define WDOG_COUNT 1
<> 128:9bcdf88f62b0 211 #define DBG_PRESENT
<> 128:9bcdf88f62b0 212 #define DBG_COUNT 1
<> 128:9bcdf88f62b0 213 #define MTB_PRESENT
<> 128:9bcdf88f62b0 214 #define MTB_COUNT 1
<> 128:9bcdf88f62b0 215 #define BOOTLOADER_PRESENT
<> 128:9bcdf88f62b0 216 #define BOOTLOADER_COUNT 1
<> 128:9bcdf88f62b0 217 #define ANALOG_PRESENT
<> 128:9bcdf88f62b0 218 #define ANALOG_COUNT 1
<> 128:9bcdf88f62b0 219
<> 128:9bcdf88f62b0 220 /** @} End of group EFM32HG308F64_Part */
<> 128:9bcdf88f62b0 221
<> 128:9bcdf88f62b0 222 #define ARM_MATH_CM0PLUS
<> 128:9bcdf88f62b0 223 #include "arm_math.h" /* To get __CLZ definitions etc. */
<> 128:9bcdf88f62b0 224 #include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */
<> 128:9bcdf88f62b0 225 #include "system_efm32hg.h" /* System Header */
<> 128:9bcdf88f62b0 226
<> 128:9bcdf88f62b0 227 /**************************************************************************//**
<> 128:9bcdf88f62b0 228 * @defgroup EFM32HG308F64_Peripheral_TypeDefs EFM32HG308F64 Peripheral TypeDefs
<> 128:9bcdf88f62b0 229 * @{
<> 128:9bcdf88f62b0 230 * @brief Device Specific Peripheral Register Structures
<> 128:9bcdf88f62b0 231 *****************************************************************************/
<> 128:9bcdf88f62b0 232
<> 128:9bcdf88f62b0 233 #include "efm32hg_dma_ch.h"
<> 128:9bcdf88f62b0 234
<> 128:9bcdf88f62b0 235 /**************************************************************************//**
<> 128:9bcdf88f62b0 236 * @defgroup EFM32HG308F64_DMA EFM32HG308F64 DMA
<> 128:9bcdf88f62b0 237 * @{
<> 128:9bcdf88f62b0 238 * @brief EFM32HG308F64_DMA Register Declaration
<> 128:9bcdf88f62b0 239 *****************************************************************************/
<> 128:9bcdf88f62b0 240 typedef struct
<> 128:9bcdf88f62b0 241 {
<> 128:9bcdf88f62b0 242 __IM uint32_t STATUS; /**< DMA Status Registers */
<> 128:9bcdf88f62b0 243 __OM uint32_t CONFIG; /**< DMA Configuration Register */
<> 128:9bcdf88f62b0 244 __IOM uint32_t CTRLBASE; /**< Channel Control Data Base Pointer Register */
<> 128:9bcdf88f62b0 245 __IM uint32_t ALTCTRLBASE; /**< Channel Alternate Control Data Base Pointer Register */
<> 128:9bcdf88f62b0 246 __IM uint32_t CHWAITSTATUS; /**< Channel Wait on Request Status Register */
<> 128:9bcdf88f62b0 247 __OM uint32_t CHSWREQ; /**< Channel Software Request Register */
<> 128:9bcdf88f62b0 248 __IOM uint32_t CHUSEBURSTS; /**< Channel Useburst Set Register */
<> 128:9bcdf88f62b0 249 __OM uint32_t CHUSEBURSTC; /**< Channel Useburst Clear Register */
<> 128:9bcdf88f62b0 250 __IOM uint32_t CHREQMASKS; /**< Channel Request Mask Set Register */
<> 128:9bcdf88f62b0 251 __OM uint32_t CHREQMASKC; /**< Channel Request Mask Clear Register */
<> 128:9bcdf88f62b0 252 __IOM uint32_t CHENS; /**< Channel Enable Set Register */
<> 128:9bcdf88f62b0 253 __OM uint32_t CHENC; /**< Channel Enable Clear Register */
<> 128:9bcdf88f62b0 254 __IOM uint32_t CHALTS; /**< Channel Alternate Set Register */
<> 128:9bcdf88f62b0 255 __OM uint32_t CHALTC; /**< Channel Alternate Clear Register */
<> 128:9bcdf88f62b0 256 __IOM uint32_t CHPRIS; /**< Channel Priority Set Register */
<> 128:9bcdf88f62b0 257 __OM uint32_t CHPRIC; /**< Channel Priority Clear Register */
<> 128:9bcdf88f62b0 258 uint32_t RESERVED0[3]; /**< Reserved for future use **/
<> 128:9bcdf88f62b0 259 __IOM uint32_t ERRORC; /**< Bus Error Clear Register */
<> 128:9bcdf88f62b0 260
<> 128:9bcdf88f62b0 261 uint32_t RESERVED1[880]; /**< Reserved for future use **/
<> 128:9bcdf88f62b0 262 __IM uint32_t CHREQSTATUS; /**< Channel Request Status */
<> 128:9bcdf88f62b0 263 uint32_t RESERVED2[1]; /**< Reserved for future use **/
<> 128:9bcdf88f62b0 264 __IM uint32_t CHSREQSTATUS; /**< Channel Single Request Status */
<> 128:9bcdf88f62b0 265
<> 128:9bcdf88f62b0 266 uint32_t RESERVED3[121]; /**< Reserved for future use **/
<> 128:9bcdf88f62b0 267 __IM uint32_t IF; /**< Interrupt Flag Register */
<> 128:9bcdf88f62b0 268 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
<> 128:9bcdf88f62b0 269 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
<> 128:9bcdf88f62b0 270 __IOM uint32_t IEN; /**< Interrupt Enable register */
<> 128:9bcdf88f62b0 271
<> 128:9bcdf88f62b0 272 uint32_t RESERVED4[60]; /**< Reserved registers */
<> 128:9bcdf88f62b0 273 DMA_CH_TypeDef CH[6]; /**< Channel registers */
<> 128:9bcdf88f62b0 274 } DMA_TypeDef; /** @} */
<> 128:9bcdf88f62b0 275
<> 128:9bcdf88f62b0 276 #include "efm32hg_usb_diep.h"
<> 128:9bcdf88f62b0 277 #include "efm32hg_usb_doep.h"
<> 128:9bcdf88f62b0 278 #include "efm32hg_usb.h"
<> 128:9bcdf88f62b0 279 #include "efm32hg_msc.h"
<> 128:9bcdf88f62b0 280 #include "efm32hg_emu.h"
<> 128:9bcdf88f62b0 281 #include "efm32hg_rmu.h"
<> 128:9bcdf88f62b0 282
<> 128:9bcdf88f62b0 283 /**************************************************************************//**
<> 128:9bcdf88f62b0 284 * @defgroup EFM32HG308F64_CMU EFM32HG308F64 CMU
<> 128:9bcdf88f62b0 285 * @{
<> 128:9bcdf88f62b0 286 * @brief EFM32HG308F64_CMU Register Declaration
<> 128:9bcdf88f62b0 287 *****************************************************************************/
<> 128:9bcdf88f62b0 288 typedef struct
<> 128:9bcdf88f62b0 289 {
<> 128:9bcdf88f62b0 290 __IOM uint32_t CTRL; /**< CMU Control Register */
<> 128:9bcdf88f62b0 291 __IOM uint32_t HFCORECLKDIV; /**< High Frequency Core Clock Division Register */
<> 128:9bcdf88f62b0 292 __IOM uint32_t HFPERCLKDIV; /**< High Frequency Peripheral Clock Division Register */
<> 128:9bcdf88f62b0 293 __IOM uint32_t HFRCOCTRL; /**< HFRCO Control Register */
<> 128:9bcdf88f62b0 294 __IOM uint32_t LFRCOCTRL; /**< LFRCO Control Register */
<> 128:9bcdf88f62b0 295 __IOM uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */
<> 128:9bcdf88f62b0 296 __IOM uint32_t CALCTRL; /**< Calibration Control Register */
<> 128:9bcdf88f62b0 297 __IOM uint32_t CALCNT; /**< Calibration Counter Register */
<> 128:9bcdf88f62b0 298 __IOM uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */
<> 128:9bcdf88f62b0 299 __IOM uint32_t CMD; /**< Command Register */
<> 128:9bcdf88f62b0 300 __IOM uint32_t LFCLKSEL; /**< Low Frequency Clock Select Register */
<> 128:9bcdf88f62b0 301 __IM uint32_t STATUS; /**< Status Register */
<> 128:9bcdf88f62b0 302 __IM uint32_t IF; /**< Interrupt Flag Register */
<> 128:9bcdf88f62b0 303 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
<> 128:9bcdf88f62b0 304 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
<> 128:9bcdf88f62b0 305 __IOM uint32_t IEN; /**< Interrupt Enable Register */
<> 128:9bcdf88f62b0 306 __IOM uint32_t HFCORECLKEN0; /**< High Frequency Core Clock Enable Register 0 */
<> 128:9bcdf88f62b0 307 __IOM uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */
<> 128:9bcdf88f62b0 308 uint32_t RESERVED0[2]; /**< Reserved for future use **/
<> 128:9bcdf88f62b0 309 __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
<> 128:9bcdf88f62b0 310 __IOM uint32_t FREEZE; /**< Freeze Register */
<> 128:9bcdf88f62b0 311 __IOM uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */
<> 128:9bcdf88f62b0 312 uint32_t RESERVED1[1]; /**< Reserved for future use **/
<> 128:9bcdf88f62b0 313 __IOM uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */
<> 128:9bcdf88f62b0 314 __IOM uint32_t LFCCLKEN0; /**< Low Frequency C Clock Enable Register 0 (Async Reg) */
<> 128:9bcdf88f62b0 315 __IOM uint32_t LFAPRESC0; /**< Low Frequency A Prescaler Register 0 (Async Reg) */
<> 128:9bcdf88f62b0 316 uint32_t RESERVED2[1]; /**< Reserved for future use **/
<> 128:9bcdf88f62b0 317 __IOM uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */
<> 128:9bcdf88f62b0 318 uint32_t RESERVED3[1]; /**< Reserved for future use **/
<> 128:9bcdf88f62b0 319 __IOM uint32_t PCNTCTRL; /**< PCNT Control Register */
<> 128:9bcdf88f62b0 320
<> 128:9bcdf88f62b0 321 uint32_t RESERVED4[1]; /**< Reserved for future use **/
<> 128:9bcdf88f62b0 322 __IOM uint32_t ROUTE; /**< I/O Routing Register */
<> 128:9bcdf88f62b0 323 __IOM uint32_t LOCK; /**< Configuration Lock Register */
<> 128:9bcdf88f62b0 324
<> 128:9bcdf88f62b0 325 uint32_t RESERVED5[18]; /**< Reserved for future use **/
<> 128:9bcdf88f62b0 326 __IOM uint32_t USBCRCTRL; /**< USB Clock Recovery Control */
<> 128:9bcdf88f62b0 327 __IOM uint32_t USHFRCOCTRL; /**< USHFRCO Control */
<> 128:9bcdf88f62b0 328 __IOM uint32_t USHFRCOTUNE; /**< USHFRCO Frequency Tune */
<> 128:9bcdf88f62b0 329 __IOM uint32_t USHFRCOCONF; /**< USHFRCO Configuration */
<> 128:9bcdf88f62b0 330 } CMU_TypeDef; /** @} */
<> 128:9bcdf88f62b0 331
<> 128:9bcdf88f62b0 332 #include "efm32hg_timer_cc.h"
<> 128:9bcdf88f62b0 333 #include "efm32hg_timer.h"
<> 128:9bcdf88f62b0 334 #include "efm32hg_acmp.h"
<> 128:9bcdf88f62b0 335 #include "efm32hg_usart.h"
<> 128:9bcdf88f62b0 336 #include "efm32hg_prs_ch.h"
<> 128:9bcdf88f62b0 337
<> 128:9bcdf88f62b0 338 /**************************************************************************//**
<> 128:9bcdf88f62b0 339 * @defgroup EFM32HG308F64_PRS EFM32HG308F64 PRS
<> 128:9bcdf88f62b0 340 * @{
<> 128:9bcdf88f62b0 341 * @brief EFM32HG308F64_PRS Register Declaration
<> 128:9bcdf88f62b0 342 *****************************************************************************/
<> 128:9bcdf88f62b0 343 typedef struct
<> 128:9bcdf88f62b0 344 {
<> 128:9bcdf88f62b0 345 __IOM uint32_t SWPULSE; /**< Software Pulse Register */
<> 128:9bcdf88f62b0 346 __IOM uint32_t SWLEVEL; /**< Software Level Register */
<> 128:9bcdf88f62b0 347 __IOM uint32_t ROUTE; /**< I/O Routing Register */
<> 128:9bcdf88f62b0 348
<> 128:9bcdf88f62b0 349 uint32_t RESERVED0[1]; /**< Reserved registers */
<> 128:9bcdf88f62b0 350 PRS_CH_TypeDef CH[6]; /**< Channel registers */
<> 128:9bcdf88f62b0 351
<> 128:9bcdf88f62b0 352 uint32_t RESERVED1[6]; /**< Reserved for future use **/
<> 128:9bcdf88f62b0 353 __IOM uint32_t TRACECTRL; /**< MTB Trace Control Register */
<> 128:9bcdf88f62b0 354 } PRS_TypeDef; /** @} */
<> 128:9bcdf88f62b0 355
<> 128:9bcdf88f62b0 356 #include "efm32hg_gpio_p.h"
<> 128:9bcdf88f62b0 357 #include "efm32hg_gpio.h"
<> 128:9bcdf88f62b0 358 #include "efm32hg_vcmp.h"
<> 128:9bcdf88f62b0 359 #include "efm32hg_leuart.h"
<> 128:9bcdf88f62b0 360 #include "efm32hg_pcnt.h"
<> 128:9bcdf88f62b0 361 #include "efm32hg_i2c.h"
<> 128:9bcdf88f62b0 362 #include "efm32hg_rtc.h"
<> 128:9bcdf88f62b0 363 #include "efm32hg_wdog.h"
<> 128:9bcdf88f62b0 364 #include "efm32hg_mtb.h"
<> 128:9bcdf88f62b0 365 #include "efm32hg_dma_descriptor.h"
<> 128:9bcdf88f62b0 366 #include "efm32hg_devinfo.h"
<> 128:9bcdf88f62b0 367 #include "efm32hg_romtable.h"
<> 128:9bcdf88f62b0 368 #include "efm32hg_calibrate.h"
<> 128:9bcdf88f62b0 369
<> 128:9bcdf88f62b0 370 /** @} End of group EFM32HG308F64_Peripheral_TypeDefs */
<> 128:9bcdf88f62b0 371
<> 128:9bcdf88f62b0 372 /**************************************************************************//**
<> 128:9bcdf88f62b0 373 * @defgroup EFM32HG308F64_Peripheral_Base EFM32HG308F64 Peripheral Memory Map
<> 128:9bcdf88f62b0 374 * @{
<> 128:9bcdf88f62b0 375 *****************************************************************************/
<> 128:9bcdf88f62b0 376
<> 128:9bcdf88f62b0 377 #define DMA_BASE (0x400C2000UL) /**< DMA base address */
<> 128:9bcdf88f62b0 378 #define USB_BASE (0x400C4000UL) /**< USB base address */
<> 128:9bcdf88f62b0 379 #define MSC_BASE (0x400C0000UL) /**< MSC base address */
<> 128:9bcdf88f62b0 380 #define EMU_BASE (0x400C6000UL) /**< EMU base address */
<> 128:9bcdf88f62b0 381 #define RMU_BASE (0x400CA000UL) /**< RMU base address */
<> 128:9bcdf88f62b0 382 #define CMU_BASE (0x400C8000UL) /**< CMU base address */
<> 128:9bcdf88f62b0 383 #define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */
<> 128:9bcdf88f62b0 384 #define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */
<> 128:9bcdf88f62b0 385 #define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */
<> 128:9bcdf88f62b0 386 #define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */
<> 128:9bcdf88f62b0 387 #define USART0_BASE (0x4000C000UL) /**< USART0 base address */
<> 128:9bcdf88f62b0 388 #define USART1_BASE (0x4000C400UL) /**< USART1 base address */
<> 128:9bcdf88f62b0 389 #define PRS_BASE (0x400CC000UL) /**< PRS base address */
<> 128:9bcdf88f62b0 390 #define GPIO_BASE (0x40006000UL) /**< GPIO base address */
<> 128:9bcdf88f62b0 391 #define VCMP_BASE (0x40000000UL) /**< VCMP base address */
<> 128:9bcdf88f62b0 392 #define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */
<> 128:9bcdf88f62b0 393 #define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */
<> 128:9bcdf88f62b0 394 #define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */
<> 128:9bcdf88f62b0 395 #define RTC_BASE (0x40080000UL) /**< RTC base address */
<> 128:9bcdf88f62b0 396 #define WDOG_BASE (0x40088000UL) /**< WDOG base address */
<> 128:9bcdf88f62b0 397 #define MTB_BASE (0xF0040000UL) /**< MTB base address */
<> 128:9bcdf88f62b0 398 #define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */
<> 128:9bcdf88f62b0 399 #define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
<> 128:9bcdf88f62b0 400 #define ROMTABLE_BASE (0xF00FFFD0UL) /**< ROMTABLE base address */
<> 128:9bcdf88f62b0 401 #define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
<> 128:9bcdf88f62b0 402 #define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
<> 128:9bcdf88f62b0 403
<> 128:9bcdf88f62b0 404 /** @} End of group EFM32HG308F64_Peripheral_Base */
<> 128:9bcdf88f62b0 405
<> 128:9bcdf88f62b0 406 /**************************************************************************//**
<> 128:9bcdf88f62b0 407 * @defgroup EFM32HG308F64_Peripheral_Declaration EFM32HG308F64 Peripheral Declarations
<> 128:9bcdf88f62b0 408 * @{
<> 128:9bcdf88f62b0 409 *****************************************************************************/
<> 128:9bcdf88f62b0 410
<> 128:9bcdf88f62b0 411 #define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
<> 128:9bcdf88f62b0 412 #define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */
<> 128:9bcdf88f62b0 413 #define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
<> 128:9bcdf88f62b0 414 #define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
<> 128:9bcdf88f62b0 415 #define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
<> 128:9bcdf88f62b0 416 #define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
<> 128:9bcdf88f62b0 417 #define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
<> 128:9bcdf88f62b0 418 #define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
<> 128:9bcdf88f62b0 419 #define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */
<> 128:9bcdf88f62b0 420 #define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
<> 128:9bcdf88f62b0 421 #define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
<> 128:9bcdf88f62b0 422 #define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
<> 128:9bcdf88f62b0 423 #define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
<> 128:9bcdf88f62b0 424 #define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
<> 128:9bcdf88f62b0 425 #define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
<> 128:9bcdf88f62b0 426 #define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
<> 128:9bcdf88f62b0 427 #define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
<> 128:9bcdf88f62b0 428 #define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
<> 128:9bcdf88f62b0 429 #define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
<> 128:9bcdf88f62b0 430 #define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
<> 128:9bcdf88f62b0 431 #define MTB ((MTB_TypeDef *) MTB_BASE) /**< MTB base pointer */
<> 128:9bcdf88f62b0 432 #define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
<> 128:9bcdf88f62b0 433 #define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
<> 128:9bcdf88f62b0 434 #define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
<> 128:9bcdf88f62b0 435
<> 128:9bcdf88f62b0 436 /** @} End of group EFM32HG308F64_Peripheral_Declaration */
<> 128:9bcdf88f62b0 437
<> 128:9bcdf88f62b0 438 /**************************************************************************//**
<> 128:9bcdf88f62b0 439 * @defgroup EFM32HG308F64_BitFields EFM32HG308F64 Bit Fields
<> 128:9bcdf88f62b0 440 * @{
<> 128:9bcdf88f62b0 441 *****************************************************************************/
<> 128:9bcdf88f62b0 442
<> 128:9bcdf88f62b0 443 /**************************************************************************//**
<> 128:9bcdf88f62b0 444 * @addtogroup EFM32HG308F64_PRS_Signals
<> 128:9bcdf88f62b0 445 * @{
<> 128:9bcdf88f62b0 446 * @brief PRS Signal names
<> 128:9bcdf88f62b0 447 *****************************************************************************/
<> 128:9bcdf88f62b0 448 #define PRS_VCMP_OUT ((1 << 16) + 0) /**< PRS Voltage comparator output */
<> 128:9bcdf88f62b0 449 #define PRS_ACMP0_OUT ((2 << 16) + 0) /**< PRS Analog comparator output */
<> 128:9bcdf88f62b0 450 #define PRS_USART0_IRTX ((16 << 16) + 0) /**< PRS USART 0 IRDA out */
<> 128:9bcdf88f62b0 451 #define PRS_USART0_TXC ((16 << 16) + 1) /**< PRS USART 0 TX complete */
<> 128:9bcdf88f62b0 452 #define PRS_USART0_RXDATAV ((16 << 16) + 2) /**< PRS USART 0 RX Data Valid */
<> 128:9bcdf88f62b0 453 #define PRS_USART1_IRTX ((17 << 16) + 0) /**< PRS USART 1 IRDA out */
<> 128:9bcdf88f62b0 454 #define PRS_USART1_TXC ((17 << 16) + 1) /**< PRS USART 1 TX complete */
<> 128:9bcdf88f62b0 455 #define PRS_USART1_RXDATAV ((17 << 16) + 2) /**< PRS USART 1 RX Data Valid */
<> 128:9bcdf88f62b0 456 #define PRS_TIMER0_UF ((28 << 16) + 0) /**< PRS Timer 0 Underflow */
<> 128:9bcdf88f62b0 457 #define PRS_TIMER0_OF ((28 << 16) + 1) /**< PRS Timer 0 Overflow */
<> 128:9bcdf88f62b0 458 #define PRS_TIMER0_CC0 ((28 << 16) + 2) /**< PRS Timer 0 Compare/Capture 0 */
<> 128:9bcdf88f62b0 459 #define PRS_TIMER0_CC1 ((28 << 16) + 3) /**< PRS Timer 0 Compare/Capture 1 */
<> 128:9bcdf88f62b0 460 #define PRS_TIMER0_CC2 ((28 << 16) + 4) /**< PRS Timer 0 Compare/Capture 2 */
<> 128:9bcdf88f62b0 461 #define PRS_TIMER1_UF ((29 << 16) + 0) /**< PRS Timer 1 Underflow */
<> 128:9bcdf88f62b0 462 #define PRS_TIMER1_OF ((29 << 16) + 1) /**< PRS Timer 1 Overflow */
<> 128:9bcdf88f62b0 463 #define PRS_TIMER1_CC0 ((29 << 16) + 2) /**< PRS Timer 1 Compare/Capture 0 */
<> 128:9bcdf88f62b0 464 #define PRS_TIMER1_CC1 ((29 << 16) + 3) /**< PRS Timer 1 Compare/Capture 1 */
<> 128:9bcdf88f62b0 465 #define PRS_TIMER1_CC2 ((29 << 16) + 4) /**< PRS Timer 1 Compare/Capture 2 */
<> 128:9bcdf88f62b0 466 #define PRS_TIMER2_UF ((30 << 16) + 0) /**< PRS Timer 2 Underflow */
<> 128:9bcdf88f62b0 467 #define PRS_TIMER2_OF ((30 << 16) + 1) /**< PRS Timer 2 Overflow */
<> 128:9bcdf88f62b0 468 #define PRS_TIMER2_CC0 ((30 << 16) + 2) /**< PRS Timer 2 Compare/Capture 0 */
<> 128:9bcdf88f62b0 469 #define PRS_TIMER2_CC1 ((30 << 16) + 3) /**< PRS Timer 2 Compare/Capture 1 */
<> 128:9bcdf88f62b0 470 #define PRS_TIMER2_CC2 ((30 << 16) + 4) /**< PRS Timer 2 Compare/Capture 2 */
<> 128:9bcdf88f62b0 471 #define PRS_USB_SOF ((36 << 16) + 0) /**< PRS USB Start of Frame */
<> 128:9bcdf88f62b0 472 #define PRS_USB_SOFSR ((36 << 16) + 1) /**< PRS USB Start of Frame Sent/Received */
<> 128:9bcdf88f62b0 473 #define PRS_RTC_OF ((40 << 16) + 0) /**< PRS RTC Overflow */
<> 128:9bcdf88f62b0 474 #define PRS_RTC_COMP0 ((40 << 16) + 1) /**< PRS RTC Compare 0 */
<> 128:9bcdf88f62b0 475 #define PRS_RTC_COMP1 ((40 << 16) + 2) /**< PRS RTC Compare 1 */
<> 128:9bcdf88f62b0 476 #define PRS_GPIO_PIN0 ((48 << 16) + 0) /**< PRS GPIO pin 0 */
<> 128:9bcdf88f62b0 477 #define PRS_GPIO_PIN1 ((48 << 16) + 1) /**< PRS GPIO pin 1 */
<> 128:9bcdf88f62b0 478 #define PRS_GPIO_PIN2 ((48 << 16) + 2) /**< PRS GPIO pin 2 */
<> 128:9bcdf88f62b0 479 #define PRS_GPIO_PIN3 ((48 << 16) + 3) /**< PRS GPIO pin 3 */
<> 128:9bcdf88f62b0 480 #define PRS_GPIO_PIN4 ((48 << 16) + 4) /**< PRS GPIO pin 4 */
<> 128:9bcdf88f62b0 481 #define PRS_GPIO_PIN5 ((48 << 16) + 5) /**< PRS GPIO pin 5 */
<> 128:9bcdf88f62b0 482 #define PRS_GPIO_PIN6 ((48 << 16) + 6) /**< PRS GPIO pin 6 */
<> 128:9bcdf88f62b0 483 #define PRS_GPIO_PIN7 ((48 << 16) + 7) /**< PRS GPIO pin 7 */
<> 128:9bcdf88f62b0 484 #define PRS_GPIO_PIN8 ((49 << 16) + 0) /**< PRS GPIO pin 8 */
<> 128:9bcdf88f62b0 485 #define PRS_GPIO_PIN9 ((49 << 16) + 1) /**< PRS GPIO pin 9 */
<> 128:9bcdf88f62b0 486 #define PRS_GPIO_PIN10 ((49 << 16) + 2) /**< PRS GPIO pin 10 */
<> 128:9bcdf88f62b0 487 #define PRS_GPIO_PIN11 ((49 << 16) + 3) /**< PRS GPIO pin 11 */
<> 128:9bcdf88f62b0 488 #define PRS_GPIO_PIN12 ((49 << 16) + 4) /**< PRS GPIO pin 12 */
<> 128:9bcdf88f62b0 489 #define PRS_GPIO_PIN13 ((49 << 16) + 5) /**< PRS GPIO pin 13 */
<> 128:9bcdf88f62b0 490 #define PRS_GPIO_PIN14 ((49 << 16) + 6) /**< PRS GPIO pin 14 */
<> 128:9bcdf88f62b0 491 #define PRS_GPIO_PIN15 ((49 << 16) + 7) /**< PRS GPIO pin 15 */
<> 128:9bcdf88f62b0 492 #define PRS_PCNT0_TCC ((54 << 16) + 0) /**< PRS Triggered compare match */
<> 128:9bcdf88f62b0 493
<> 128:9bcdf88f62b0 494 /** @} End of group EFM32HG308F64_PRS */
<> 128:9bcdf88f62b0 495
<> 128:9bcdf88f62b0 496 #include "efm32hg_dmareq.h"
<> 128:9bcdf88f62b0 497 #include "efm32hg_dmactrl.h"
<> 128:9bcdf88f62b0 498
<> 128:9bcdf88f62b0 499 /**************************************************************************//**
<> 128:9bcdf88f62b0 500 * @defgroup EFM32HG308F64_DMA_BitFields EFM32HG308F64_DMA Bit Fields
<> 128:9bcdf88f62b0 501 * @{
<> 128:9bcdf88f62b0 502 *****************************************************************************/
<> 128:9bcdf88f62b0 503
<> 128:9bcdf88f62b0 504 /* Bit fields for DMA STATUS */
<> 128:9bcdf88f62b0 505 #define _DMA_STATUS_RESETVALUE 0x10050000UL /**< Default value for DMA_STATUS */
<> 128:9bcdf88f62b0 506 #define _DMA_STATUS_MASK 0x001F00F1UL /**< Mask for DMA_STATUS */
<> 128:9bcdf88f62b0 507 #define DMA_STATUS_EN (0x1UL << 0) /**< DMA Enable Status */
<> 128:9bcdf88f62b0 508 #define _DMA_STATUS_EN_SHIFT 0 /**< Shift value for DMA_EN */
<> 128:9bcdf88f62b0 509 #define _DMA_STATUS_EN_MASK 0x1UL /**< Bit mask for DMA_EN */
<> 128:9bcdf88f62b0 510 #define _DMA_STATUS_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_STATUS */
<> 128:9bcdf88f62b0 511 #define DMA_STATUS_EN_DEFAULT (_DMA_STATUS_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_STATUS */
<> 128:9bcdf88f62b0 512 #define _DMA_STATUS_STATE_SHIFT 4 /**< Shift value for DMA_STATE */
<> 128:9bcdf88f62b0 513 #define _DMA_STATUS_STATE_MASK 0xF0UL /**< Bit mask for DMA_STATE */
<> 128:9bcdf88f62b0 514 #define _DMA_STATUS_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_STATUS */
<> 128:9bcdf88f62b0 515 #define _DMA_STATUS_STATE_IDLE 0x00000000UL /**< Mode IDLE for DMA_STATUS */
<> 128:9bcdf88f62b0 516 #define _DMA_STATUS_STATE_RDCHCTRLDATA 0x00000001UL /**< Mode RDCHCTRLDATA for DMA_STATUS */
<> 128:9bcdf88f62b0 517 #define _DMA_STATUS_STATE_RDSRCENDPTR 0x00000002UL /**< Mode RDSRCENDPTR for DMA_STATUS */
<> 128:9bcdf88f62b0 518 #define _DMA_STATUS_STATE_RDDSTENDPTR 0x00000003UL /**< Mode RDDSTENDPTR for DMA_STATUS */
<> 128:9bcdf88f62b0 519 #define _DMA_STATUS_STATE_RDSRCDATA 0x00000004UL /**< Mode RDSRCDATA for DMA_STATUS */
<> 128:9bcdf88f62b0 520 #define _DMA_STATUS_STATE_WRDSTDATA 0x00000005UL /**< Mode WRDSTDATA for DMA_STATUS */
<> 128:9bcdf88f62b0 521 #define _DMA_STATUS_STATE_WAITREQCLR 0x00000006UL /**< Mode WAITREQCLR for DMA_STATUS */
<> 128:9bcdf88f62b0 522 #define _DMA_STATUS_STATE_WRCHCTRLDATA 0x00000007UL /**< Mode WRCHCTRLDATA for DMA_STATUS */
<> 128:9bcdf88f62b0 523 #define _DMA_STATUS_STATE_STALLED 0x00000008UL /**< Mode STALLED for DMA_STATUS */
<> 128:9bcdf88f62b0 524 #define _DMA_STATUS_STATE_DONE 0x00000009UL /**< Mode DONE for DMA_STATUS */
<> 128:9bcdf88f62b0 525 #define _DMA_STATUS_STATE_PERSCATTRANS 0x0000000AUL /**< Mode PERSCATTRANS for DMA_STATUS */
<> 128:9bcdf88f62b0 526 #define DMA_STATUS_STATE_DEFAULT (_DMA_STATUS_STATE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_STATUS */
<> 128:9bcdf88f62b0 527 #define DMA_STATUS_STATE_IDLE (_DMA_STATUS_STATE_IDLE << 4) /**< Shifted mode IDLE for DMA_STATUS */
<> 128:9bcdf88f62b0 528 #define DMA_STATUS_STATE_RDCHCTRLDATA (_DMA_STATUS_STATE_RDCHCTRLDATA << 4) /**< Shifted mode RDCHCTRLDATA for DMA_STATUS */
<> 128:9bcdf88f62b0 529 #define DMA_STATUS_STATE_RDSRCENDPTR (_DMA_STATUS_STATE_RDSRCENDPTR << 4) /**< Shifted mode RDSRCENDPTR for DMA_STATUS */
<> 128:9bcdf88f62b0 530 #define DMA_STATUS_STATE_RDDSTENDPTR (_DMA_STATUS_STATE_RDDSTENDPTR << 4) /**< Shifted mode RDDSTENDPTR for DMA_STATUS */
<> 128:9bcdf88f62b0 531 #define DMA_STATUS_STATE_RDSRCDATA (_DMA_STATUS_STATE_RDSRCDATA << 4) /**< Shifted mode RDSRCDATA for DMA_STATUS */
<> 128:9bcdf88f62b0 532 #define DMA_STATUS_STATE_WRDSTDATA (_DMA_STATUS_STATE_WRDSTDATA << 4) /**< Shifted mode WRDSTDATA for DMA_STATUS */
<> 128:9bcdf88f62b0 533 #define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< Shifted mode WAITREQCLR for DMA_STATUS */
<> 128:9bcdf88f62b0 534 #define DMA_STATUS_STATE_WRCHCTRLDATA (_DMA_STATUS_STATE_WRCHCTRLDATA << 4) /**< Shifted mode WRCHCTRLDATA for DMA_STATUS */
<> 128:9bcdf88f62b0 535 #define DMA_STATUS_STATE_STALLED (_DMA_STATUS_STATE_STALLED << 4) /**< Shifted mode STALLED for DMA_STATUS */
<> 128:9bcdf88f62b0 536 #define DMA_STATUS_STATE_DONE (_DMA_STATUS_STATE_DONE << 4) /**< Shifted mode DONE for DMA_STATUS */
<> 128:9bcdf88f62b0 537 #define DMA_STATUS_STATE_PERSCATTRANS (_DMA_STATUS_STATE_PERSCATTRANS << 4) /**< Shifted mode PERSCATTRANS for DMA_STATUS */
<> 128:9bcdf88f62b0 538 #define _DMA_STATUS_CHNUM_SHIFT 16 /**< Shift value for DMA_CHNUM */
<> 128:9bcdf88f62b0 539 #define _DMA_STATUS_CHNUM_MASK 0x1F0000UL /**< Bit mask for DMA_CHNUM */
<> 128:9bcdf88f62b0 540 #define _DMA_STATUS_CHNUM_DEFAULT 0x00000005UL /**< Mode DEFAULT for DMA_STATUS */
<> 128:9bcdf88f62b0 541 #define DMA_STATUS_CHNUM_DEFAULT (_DMA_STATUS_CHNUM_DEFAULT << 16) /**< Shifted mode DEFAULT for DMA_STATUS */
<> 128:9bcdf88f62b0 542
<> 128:9bcdf88f62b0 543 /* Bit fields for DMA CONFIG */
<> 128:9bcdf88f62b0 544 #define _DMA_CONFIG_RESETVALUE 0x00000000UL /**< Default value for DMA_CONFIG */
<> 128:9bcdf88f62b0 545 #define _DMA_CONFIG_MASK 0x00000021UL /**< Mask for DMA_CONFIG */
<> 128:9bcdf88f62b0 546 #define DMA_CONFIG_EN (0x1UL << 0) /**< Enable DMA */
<> 128:9bcdf88f62b0 547 #define _DMA_CONFIG_EN_SHIFT 0 /**< Shift value for DMA_EN */
<> 128:9bcdf88f62b0 548 #define _DMA_CONFIG_EN_MASK 0x1UL /**< Bit mask for DMA_EN */
<> 128:9bcdf88f62b0 549 #define _DMA_CONFIG_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CONFIG */
<> 128:9bcdf88f62b0 550 #define DMA_CONFIG_EN_DEFAULT (_DMA_CONFIG_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CONFIG */
<> 128:9bcdf88f62b0 551 #define DMA_CONFIG_CHPROT (0x1UL << 5) /**< Channel Protection Control */
<> 128:9bcdf88f62b0 552 #define _DMA_CONFIG_CHPROT_SHIFT 5 /**< Shift value for DMA_CHPROT */
<> 128:9bcdf88f62b0 553 #define _DMA_CONFIG_CHPROT_MASK 0x20UL /**< Bit mask for DMA_CHPROT */
<> 128:9bcdf88f62b0 554 #define _DMA_CONFIG_CHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CONFIG */
<> 128:9bcdf88f62b0 555 #define DMA_CONFIG_CHPROT_DEFAULT (_DMA_CONFIG_CHPROT_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CONFIG */
<> 128:9bcdf88f62b0 556
<> 128:9bcdf88f62b0 557 /* Bit fields for DMA CTRLBASE */
<> 128:9bcdf88f62b0 558 #define _DMA_CTRLBASE_RESETVALUE 0x00000000UL /**< Default value for DMA_CTRLBASE */
<> 128:9bcdf88f62b0 559 #define _DMA_CTRLBASE_MASK 0xFFFFFFFFUL /**< Mask for DMA_CTRLBASE */
<> 128:9bcdf88f62b0 560 #define _DMA_CTRLBASE_CTRLBASE_SHIFT 0 /**< Shift value for DMA_CTRLBASE */
<> 128:9bcdf88f62b0 561 #define _DMA_CTRLBASE_CTRLBASE_MASK 0xFFFFFFFFUL /**< Bit mask for DMA_CTRLBASE */
<> 128:9bcdf88f62b0 562 #define _DMA_CTRLBASE_CTRLBASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CTRLBASE */
<> 128:9bcdf88f62b0 563 #define DMA_CTRLBASE_CTRLBASE_DEFAULT (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CTRLBASE */
<> 128:9bcdf88f62b0 564
<> 128:9bcdf88f62b0 565 /* Bit fields for DMA ALTCTRLBASE */
<> 128:9bcdf88f62b0 566 #define _DMA_ALTCTRLBASE_RESETVALUE 0x00000080UL /**< Default value for DMA_ALTCTRLBASE */
<> 128:9bcdf88f62b0 567 #define _DMA_ALTCTRLBASE_MASK 0xFFFFFFFFUL /**< Mask for DMA_ALTCTRLBASE */
<> 128:9bcdf88f62b0 568 #define _DMA_ALTCTRLBASE_ALTCTRLBASE_SHIFT 0 /**< Shift value for DMA_ALTCTRLBASE */
<> 128:9bcdf88f62b0 569 #define _DMA_ALTCTRLBASE_ALTCTRLBASE_MASK 0xFFFFFFFFUL /**< Bit mask for DMA_ALTCTRLBASE */
<> 128:9bcdf88f62b0 570 #define _DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT 0x00000080UL /**< Mode DEFAULT for DMA_ALTCTRLBASE */
<> 128:9bcdf88f62b0 571 #define DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT (_DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_ALTCTRLBASE */
<> 128:9bcdf88f62b0 572
<> 128:9bcdf88f62b0 573 /* Bit fields for DMA CHWAITSTATUS */
<> 128:9bcdf88f62b0 574 #define _DMA_CHWAITSTATUS_RESETVALUE 0x0000003FUL /**< Default value for DMA_CHWAITSTATUS */
<> 128:9bcdf88f62b0 575 #define _DMA_CHWAITSTATUS_MASK 0x0000003FUL /**< Mask for DMA_CHWAITSTATUS */
<> 128:9bcdf88f62b0 576 #define DMA_CHWAITSTATUS_CH0WAITSTATUS (0x1UL << 0) /**< Channel 0 Wait on Request Status */
<> 128:9bcdf88f62b0 577 #define _DMA_CHWAITSTATUS_CH0WAITSTATUS_SHIFT 0 /**< Shift value for DMA_CH0WAITSTATUS */
<> 128:9bcdf88f62b0 578 #define _DMA_CHWAITSTATUS_CH0WAITSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0WAITSTATUS */
<> 128:9bcdf88f62b0 579 #define _DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
<> 128:9bcdf88f62b0 580 #define DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
<> 128:9bcdf88f62b0 581 #define DMA_CHWAITSTATUS_CH1WAITSTATUS (0x1UL << 1) /**< Channel 1 Wait on Request Status */
<> 128:9bcdf88f62b0 582 #define _DMA_CHWAITSTATUS_CH1WAITSTATUS_SHIFT 1 /**< Shift value for DMA_CH1WAITSTATUS */
<> 128:9bcdf88f62b0 583 #define _DMA_CHWAITSTATUS_CH1WAITSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1WAITSTATUS */
<> 128:9bcdf88f62b0 584 #define _DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
<> 128:9bcdf88f62b0 585 #define DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
<> 128:9bcdf88f62b0 586 #define DMA_CHWAITSTATUS_CH2WAITSTATUS (0x1UL << 2) /**< Channel 2 Wait on Request Status */
<> 128:9bcdf88f62b0 587 #define _DMA_CHWAITSTATUS_CH2WAITSTATUS_SHIFT 2 /**< Shift value for DMA_CH2WAITSTATUS */
<> 128:9bcdf88f62b0 588 #define _DMA_CHWAITSTATUS_CH2WAITSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2WAITSTATUS */
<> 128:9bcdf88f62b0 589 #define _DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
<> 128:9bcdf88f62b0 590 #define DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
<> 128:9bcdf88f62b0 591 #define DMA_CHWAITSTATUS_CH3WAITSTATUS (0x1UL << 3) /**< Channel 3 Wait on Request Status */
<> 128:9bcdf88f62b0 592 #define _DMA_CHWAITSTATUS_CH3WAITSTATUS_SHIFT 3 /**< Shift value for DMA_CH3WAITSTATUS */
<> 128:9bcdf88f62b0 593 #define _DMA_CHWAITSTATUS_CH3WAITSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3WAITSTATUS */
<> 128:9bcdf88f62b0 594 #define _DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
<> 128:9bcdf88f62b0 595 #define DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
<> 128:9bcdf88f62b0 596 #define DMA_CHWAITSTATUS_CH4WAITSTATUS (0x1UL << 4) /**< Channel 4 Wait on Request Status */
<> 128:9bcdf88f62b0 597 #define _DMA_CHWAITSTATUS_CH4WAITSTATUS_SHIFT 4 /**< Shift value for DMA_CH4WAITSTATUS */
<> 128:9bcdf88f62b0 598 #define _DMA_CHWAITSTATUS_CH4WAITSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4WAITSTATUS */
<> 128:9bcdf88f62b0 599 #define _DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
<> 128:9bcdf88f62b0 600 #define DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
<> 128:9bcdf88f62b0 601 #define DMA_CHWAITSTATUS_CH5WAITSTATUS (0x1UL << 5) /**< Channel 5 Wait on Request Status */
<> 128:9bcdf88f62b0 602 #define _DMA_CHWAITSTATUS_CH5WAITSTATUS_SHIFT 5 /**< Shift value for DMA_CH5WAITSTATUS */
<> 128:9bcdf88f62b0 603 #define _DMA_CHWAITSTATUS_CH5WAITSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5WAITSTATUS */
<> 128:9bcdf88f62b0 604 #define _DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
<> 128:9bcdf88f62b0 605 #define DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
<> 128:9bcdf88f62b0 606
<> 128:9bcdf88f62b0 607 /* Bit fields for DMA CHSWREQ */
<> 128:9bcdf88f62b0 608 #define _DMA_CHSWREQ_RESETVALUE 0x00000000UL /**< Default value for DMA_CHSWREQ */
<> 128:9bcdf88f62b0 609 #define _DMA_CHSWREQ_MASK 0x0000003FUL /**< Mask for DMA_CHSWREQ */
<> 128:9bcdf88f62b0 610 #define DMA_CHSWREQ_CH0SWREQ (0x1UL << 0) /**< Channel 0 Software Request */
<> 128:9bcdf88f62b0 611 #define _DMA_CHSWREQ_CH0SWREQ_SHIFT 0 /**< Shift value for DMA_CH0SWREQ */
<> 128:9bcdf88f62b0 612 #define _DMA_CHSWREQ_CH0SWREQ_MASK 0x1UL /**< Bit mask for DMA_CH0SWREQ */
<> 128:9bcdf88f62b0 613 #define _DMA_CHSWREQ_CH0SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
<> 128:9bcdf88f62b0 614 #define DMA_CHSWREQ_CH0SWREQ_DEFAULT (_DMA_CHSWREQ_CH0SWREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
<> 128:9bcdf88f62b0 615 #define DMA_CHSWREQ_CH1SWREQ (0x1UL << 1) /**< Channel 1 Software Request */
<> 128:9bcdf88f62b0 616 #define _DMA_CHSWREQ_CH1SWREQ_SHIFT 1 /**< Shift value for DMA_CH1SWREQ */
<> 128:9bcdf88f62b0 617 #define _DMA_CHSWREQ_CH1SWREQ_MASK 0x2UL /**< Bit mask for DMA_CH1SWREQ */
<> 128:9bcdf88f62b0 618 #define _DMA_CHSWREQ_CH1SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
<> 128:9bcdf88f62b0 619 #define DMA_CHSWREQ_CH1SWREQ_DEFAULT (_DMA_CHSWREQ_CH1SWREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
<> 128:9bcdf88f62b0 620 #define DMA_CHSWREQ_CH2SWREQ (0x1UL << 2) /**< Channel 2 Software Request */
<> 128:9bcdf88f62b0 621 #define _DMA_CHSWREQ_CH2SWREQ_SHIFT 2 /**< Shift value for DMA_CH2SWREQ */
<> 128:9bcdf88f62b0 622 #define _DMA_CHSWREQ_CH2SWREQ_MASK 0x4UL /**< Bit mask for DMA_CH2SWREQ */
<> 128:9bcdf88f62b0 623 #define _DMA_CHSWREQ_CH2SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
<> 128:9bcdf88f62b0 624 #define DMA_CHSWREQ_CH2SWREQ_DEFAULT (_DMA_CHSWREQ_CH2SWREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
<> 128:9bcdf88f62b0 625 #define DMA_CHSWREQ_CH3SWREQ (0x1UL << 3) /**< Channel 3 Software Request */
<> 128:9bcdf88f62b0 626 #define _DMA_CHSWREQ_CH3SWREQ_SHIFT 3 /**< Shift value for DMA_CH3SWREQ */
<> 128:9bcdf88f62b0 627 #define _DMA_CHSWREQ_CH3SWREQ_MASK 0x8UL /**< Bit mask for DMA_CH3SWREQ */
<> 128:9bcdf88f62b0 628 #define _DMA_CHSWREQ_CH3SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
<> 128:9bcdf88f62b0 629 #define DMA_CHSWREQ_CH3SWREQ_DEFAULT (_DMA_CHSWREQ_CH3SWREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
<> 128:9bcdf88f62b0 630 #define DMA_CHSWREQ_CH4SWREQ (0x1UL << 4) /**< Channel 4 Software Request */
<> 128:9bcdf88f62b0 631 #define _DMA_CHSWREQ_CH4SWREQ_SHIFT 4 /**< Shift value for DMA_CH4SWREQ */
<> 128:9bcdf88f62b0 632 #define _DMA_CHSWREQ_CH4SWREQ_MASK 0x10UL /**< Bit mask for DMA_CH4SWREQ */
<> 128:9bcdf88f62b0 633 #define _DMA_CHSWREQ_CH4SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
<> 128:9bcdf88f62b0 634 #define DMA_CHSWREQ_CH4SWREQ_DEFAULT (_DMA_CHSWREQ_CH4SWREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
<> 128:9bcdf88f62b0 635 #define DMA_CHSWREQ_CH5SWREQ (0x1UL << 5) /**< Channel 5 Software Request */
<> 128:9bcdf88f62b0 636 #define _DMA_CHSWREQ_CH5SWREQ_SHIFT 5 /**< Shift value for DMA_CH5SWREQ */
<> 128:9bcdf88f62b0 637 #define _DMA_CHSWREQ_CH5SWREQ_MASK 0x20UL /**< Bit mask for DMA_CH5SWREQ */
<> 128:9bcdf88f62b0 638 #define _DMA_CHSWREQ_CH5SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
<> 128:9bcdf88f62b0 639 #define DMA_CHSWREQ_CH5SWREQ_DEFAULT (_DMA_CHSWREQ_CH5SWREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
<> 128:9bcdf88f62b0 640
<> 128:9bcdf88f62b0 641 /* Bit fields for DMA CHUSEBURSTS */
<> 128:9bcdf88f62b0 642 #define _DMA_CHUSEBURSTS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHUSEBURSTS */
<> 128:9bcdf88f62b0 643 #define _DMA_CHUSEBURSTS_MASK 0x0000003FUL /**< Mask for DMA_CHUSEBURSTS */
<> 128:9bcdf88f62b0 644 #define DMA_CHUSEBURSTS_CH0USEBURSTS (0x1UL << 0) /**< Channel 0 Useburst Set */
<> 128:9bcdf88f62b0 645 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_SHIFT 0 /**< Shift value for DMA_CH0USEBURSTS */
<> 128:9bcdf88f62b0 646 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_MASK 0x1UL /**< Bit mask for DMA_CH0USEBURSTS */
<> 128:9bcdf88f62b0 647 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
<> 128:9bcdf88f62b0 648 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST 0x00000000UL /**< Mode SINGLEANDBURST for DMA_CHUSEBURSTS */
<> 128:9bcdf88f62b0 649 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY 0x00000001UL /**< Mode BURSTONLY for DMA_CHUSEBURSTS */
<> 128:9bcdf88f62b0 650 #define DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
<> 128:9bcdf88f62b0 651 #define DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST (_DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST << 0) /**< Shifted mode SINGLEANDBURST for DMA_CHUSEBURSTS */
<> 128:9bcdf88f62b0 652 #define DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY (_DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY << 0) /**< Shifted mode BURSTONLY for DMA_CHUSEBURSTS */
<> 128:9bcdf88f62b0 653 #define DMA_CHUSEBURSTS_CH1USEBURSTS (0x1UL << 1) /**< Channel 1 Useburst Set */
<> 128:9bcdf88f62b0 654 #define _DMA_CHUSEBURSTS_CH1USEBURSTS_SHIFT 1 /**< Shift value for DMA_CH1USEBURSTS */
<> 128:9bcdf88f62b0 655 #define _DMA_CHUSEBURSTS_CH1USEBURSTS_MASK 0x2UL /**< Bit mask for DMA_CH1USEBURSTS */
<> 128:9bcdf88f62b0 656 #define _DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
<> 128:9bcdf88f62b0 657 #define DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
<> 128:9bcdf88f62b0 658 #define DMA_CHUSEBURSTS_CH2USEBURSTS (0x1UL << 2) /**< Channel 2 Useburst Set */
<> 128:9bcdf88f62b0 659 #define _DMA_CHUSEBURSTS_CH2USEBURSTS_SHIFT 2 /**< Shift value for DMA_CH2USEBURSTS */
<> 128:9bcdf88f62b0 660 #define _DMA_CHUSEBURSTS_CH2USEBURSTS_MASK 0x4UL /**< Bit mask for DMA_CH2USEBURSTS */
<> 128:9bcdf88f62b0 661 #define _DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
<> 128:9bcdf88f62b0 662 #define DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
<> 128:9bcdf88f62b0 663 #define DMA_CHUSEBURSTS_CH3USEBURSTS (0x1UL << 3) /**< Channel 3 Useburst Set */
<> 128:9bcdf88f62b0 664 #define _DMA_CHUSEBURSTS_CH3USEBURSTS_SHIFT 3 /**< Shift value for DMA_CH3USEBURSTS */
<> 128:9bcdf88f62b0 665 #define _DMA_CHUSEBURSTS_CH3USEBURSTS_MASK 0x8UL /**< Bit mask for DMA_CH3USEBURSTS */
<> 128:9bcdf88f62b0 666 #define _DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
<> 128:9bcdf88f62b0 667 #define DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
<> 128:9bcdf88f62b0 668 #define DMA_CHUSEBURSTS_CH4USEBURSTS (0x1UL << 4) /**< Channel 4 Useburst Set */
<> 128:9bcdf88f62b0 669 #define _DMA_CHUSEBURSTS_CH4USEBURSTS_SHIFT 4 /**< Shift value for DMA_CH4USEBURSTS */
<> 128:9bcdf88f62b0 670 #define _DMA_CHUSEBURSTS_CH4USEBURSTS_MASK 0x10UL /**< Bit mask for DMA_CH4USEBURSTS */
<> 128:9bcdf88f62b0 671 #define _DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
<> 128:9bcdf88f62b0 672 #define DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
<> 128:9bcdf88f62b0 673 #define DMA_CHUSEBURSTS_CH5USEBURSTS (0x1UL << 5) /**< Channel 5 Useburst Set */
<> 128:9bcdf88f62b0 674 #define _DMA_CHUSEBURSTS_CH5USEBURSTS_SHIFT 5 /**< Shift value for DMA_CH5USEBURSTS */
<> 128:9bcdf88f62b0 675 #define _DMA_CHUSEBURSTS_CH5USEBURSTS_MASK 0x20UL /**< Bit mask for DMA_CH5USEBURSTS */
<> 128:9bcdf88f62b0 676 #define _DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
<> 128:9bcdf88f62b0 677 #define DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
<> 128:9bcdf88f62b0 678
<> 128:9bcdf88f62b0 679 /* Bit fields for DMA CHUSEBURSTC */
<> 128:9bcdf88f62b0 680 #define _DMA_CHUSEBURSTC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHUSEBURSTC */
<> 128:9bcdf88f62b0 681 #define _DMA_CHUSEBURSTC_MASK 0x0000003FUL /**< Mask for DMA_CHUSEBURSTC */
<> 128:9bcdf88f62b0 682 #define DMA_CHUSEBURSTC_CH0USEBURSTC (0x1UL << 0) /**< Channel 0 Useburst Clear */
<> 128:9bcdf88f62b0 683 #define _DMA_CHUSEBURSTC_CH0USEBURSTC_SHIFT 0 /**< Shift value for DMA_CH0USEBURSTC */
<> 128:9bcdf88f62b0 684 #define _DMA_CHUSEBURSTC_CH0USEBURSTC_MASK 0x1UL /**< Bit mask for DMA_CH0USEBURSTC */
<> 128:9bcdf88f62b0 685 #define _DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
<> 128:9bcdf88f62b0 686 #define DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
<> 128:9bcdf88f62b0 687 #define DMA_CHUSEBURSTC_CH1USEBURSTC (0x1UL << 1) /**< Channel 1 Useburst Clear */
<> 128:9bcdf88f62b0 688 #define _DMA_CHUSEBURSTC_CH1USEBURSTC_SHIFT 1 /**< Shift value for DMA_CH1USEBURSTC */
<> 128:9bcdf88f62b0 689 #define _DMA_CHUSEBURSTC_CH1USEBURSTC_MASK 0x2UL /**< Bit mask for DMA_CH1USEBURSTC */
<> 128:9bcdf88f62b0 690 #define _DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
<> 128:9bcdf88f62b0 691 #define DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
<> 128:9bcdf88f62b0 692 #define DMA_CHUSEBURSTC_CH2USEBURSTC (0x1UL << 2) /**< Channel 2 Useburst Clear */
<> 128:9bcdf88f62b0 693 #define _DMA_CHUSEBURSTC_CH2USEBURSTC_SHIFT 2 /**< Shift value for DMA_CH2USEBURSTC */
<> 128:9bcdf88f62b0 694 #define _DMA_CHUSEBURSTC_CH2USEBURSTC_MASK 0x4UL /**< Bit mask for DMA_CH2USEBURSTC */
<> 128:9bcdf88f62b0 695 #define _DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
<> 128:9bcdf88f62b0 696 #define DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
<> 128:9bcdf88f62b0 697 #define DMA_CHUSEBURSTC_CH3USEBURSTC (0x1UL << 3) /**< Channel 3 Useburst Clear */
<> 128:9bcdf88f62b0 698 #define _DMA_CHUSEBURSTC_CH3USEBURSTC_SHIFT 3 /**< Shift value for DMA_CH3USEBURSTC */
<> 128:9bcdf88f62b0 699 #define _DMA_CHUSEBURSTC_CH3USEBURSTC_MASK 0x8UL /**< Bit mask for DMA_CH3USEBURSTC */
<> 128:9bcdf88f62b0 700 #define _DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
<> 128:9bcdf88f62b0 701 #define DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
<> 128:9bcdf88f62b0 702 #define DMA_CHUSEBURSTC_CH4USEBURSTC (0x1UL << 4) /**< Channel 4 Useburst Clear */
<> 128:9bcdf88f62b0 703 #define _DMA_CHUSEBURSTC_CH4USEBURSTC_SHIFT 4 /**< Shift value for DMA_CH4USEBURSTC */
<> 128:9bcdf88f62b0 704 #define _DMA_CHUSEBURSTC_CH4USEBURSTC_MASK 0x10UL /**< Bit mask for DMA_CH4USEBURSTC */
<> 128:9bcdf88f62b0 705 #define _DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
<> 128:9bcdf88f62b0 706 #define DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
<> 128:9bcdf88f62b0 707 #define DMA_CHUSEBURSTC_CH5USEBURSTC (0x1UL << 5) /**< Channel 5 Useburst Clear */
<> 128:9bcdf88f62b0 708 #define _DMA_CHUSEBURSTC_CH5USEBURSTC_SHIFT 5 /**< Shift value for DMA_CH5USEBURSTC */
<> 128:9bcdf88f62b0 709 #define _DMA_CHUSEBURSTC_CH5USEBURSTC_MASK 0x20UL /**< Bit mask for DMA_CH5USEBURSTC */
<> 128:9bcdf88f62b0 710 #define _DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
<> 128:9bcdf88f62b0 711 #define DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
<> 128:9bcdf88f62b0 712
<> 128:9bcdf88f62b0 713 /* Bit fields for DMA CHREQMASKS */
<> 128:9bcdf88f62b0 714 #define _DMA_CHREQMASKS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQMASKS */
<> 128:9bcdf88f62b0 715 #define _DMA_CHREQMASKS_MASK 0x0000003FUL /**< Mask for DMA_CHREQMASKS */
<> 128:9bcdf88f62b0 716 #define DMA_CHREQMASKS_CH0REQMASKS (0x1UL << 0) /**< Channel 0 Request Mask Set */
<> 128:9bcdf88f62b0 717 #define _DMA_CHREQMASKS_CH0REQMASKS_SHIFT 0 /**< Shift value for DMA_CH0REQMASKS */
<> 128:9bcdf88f62b0 718 #define _DMA_CHREQMASKS_CH0REQMASKS_MASK 0x1UL /**< Bit mask for DMA_CH0REQMASKS */
<> 128:9bcdf88f62b0 719 #define _DMA_CHREQMASKS_CH0REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
<> 128:9bcdf88f62b0 720 #define DMA_CHREQMASKS_CH0REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH0REQMASKS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
<> 128:9bcdf88f62b0 721 #define DMA_CHREQMASKS_CH1REQMASKS (0x1UL << 1) /**< Channel 1 Request Mask Set */
<> 128:9bcdf88f62b0 722 #define _DMA_CHREQMASKS_CH1REQMASKS_SHIFT 1 /**< Shift value for DMA_CH1REQMASKS */
<> 128:9bcdf88f62b0 723 #define _DMA_CHREQMASKS_CH1REQMASKS_MASK 0x2UL /**< Bit mask for DMA_CH1REQMASKS */
<> 128:9bcdf88f62b0 724 #define _DMA_CHREQMASKS_CH1REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
<> 128:9bcdf88f62b0 725 #define DMA_CHREQMASKS_CH1REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH1REQMASKS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
<> 128:9bcdf88f62b0 726 #define DMA_CHREQMASKS_CH2REQMASKS (0x1UL << 2) /**< Channel 2 Request Mask Set */
<> 128:9bcdf88f62b0 727 #define _DMA_CHREQMASKS_CH2REQMASKS_SHIFT 2 /**< Shift value for DMA_CH2REQMASKS */
<> 128:9bcdf88f62b0 728 #define _DMA_CHREQMASKS_CH2REQMASKS_MASK 0x4UL /**< Bit mask for DMA_CH2REQMASKS */
<> 128:9bcdf88f62b0 729 #define _DMA_CHREQMASKS_CH2REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
<> 128:9bcdf88f62b0 730 #define DMA_CHREQMASKS_CH2REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH2REQMASKS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
<> 128:9bcdf88f62b0 731 #define DMA_CHREQMASKS_CH3REQMASKS (0x1UL << 3) /**< Channel 3 Request Mask Set */
<> 128:9bcdf88f62b0 732 #define _DMA_CHREQMASKS_CH3REQMASKS_SHIFT 3 /**< Shift value for DMA_CH3REQMASKS */
<> 128:9bcdf88f62b0 733 #define _DMA_CHREQMASKS_CH3REQMASKS_MASK 0x8UL /**< Bit mask for DMA_CH3REQMASKS */
<> 128:9bcdf88f62b0 734 #define _DMA_CHREQMASKS_CH3REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
<> 128:9bcdf88f62b0 735 #define DMA_CHREQMASKS_CH3REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH3REQMASKS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
<> 128:9bcdf88f62b0 736 #define DMA_CHREQMASKS_CH4REQMASKS (0x1UL << 4) /**< Channel 4 Request Mask Set */
<> 128:9bcdf88f62b0 737 #define _DMA_CHREQMASKS_CH4REQMASKS_SHIFT 4 /**< Shift value for DMA_CH4REQMASKS */
<> 128:9bcdf88f62b0 738 #define _DMA_CHREQMASKS_CH4REQMASKS_MASK 0x10UL /**< Bit mask for DMA_CH4REQMASKS */
<> 128:9bcdf88f62b0 739 #define _DMA_CHREQMASKS_CH4REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
<> 128:9bcdf88f62b0 740 #define DMA_CHREQMASKS_CH4REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH4REQMASKS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
<> 128:9bcdf88f62b0 741 #define DMA_CHREQMASKS_CH5REQMASKS (0x1UL << 5) /**< Channel 5 Request Mask Set */
<> 128:9bcdf88f62b0 742 #define _DMA_CHREQMASKS_CH5REQMASKS_SHIFT 5 /**< Shift value for DMA_CH5REQMASKS */
<> 128:9bcdf88f62b0 743 #define _DMA_CHREQMASKS_CH5REQMASKS_MASK 0x20UL /**< Bit mask for DMA_CH5REQMASKS */
<> 128:9bcdf88f62b0 744 #define _DMA_CHREQMASKS_CH5REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
<> 128:9bcdf88f62b0 745 #define DMA_CHREQMASKS_CH5REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH5REQMASKS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
<> 128:9bcdf88f62b0 746
<> 128:9bcdf88f62b0 747 /* Bit fields for DMA CHREQMASKC */
<> 128:9bcdf88f62b0 748 #define _DMA_CHREQMASKC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQMASKC */
<> 128:9bcdf88f62b0 749 #define _DMA_CHREQMASKC_MASK 0x0000003FUL /**< Mask for DMA_CHREQMASKC */
<> 128:9bcdf88f62b0 750 #define DMA_CHREQMASKC_CH0REQMASKC (0x1UL << 0) /**< Channel 0 Request Mask Clear */
<> 128:9bcdf88f62b0 751 #define _DMA_CHREQMASKC_CH0REQMASKC_SHIFT 0 /**< Shift value for DMA_CH0REQMASKC */
<> 128:9bcdf88f62b0 752 #define _DMA_CHREQMASKC_CH0REQMASKC_MASK 0x1UL /**< Bit mask for DMA_CH0REQMASKC */
<> 128:9bcdf88f62b0 753 #define _DMA_CHREQMASKC_CH0REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
<> 128:9bcdf88f62b0 754 #define DMA_CHREQMASKC_CH0REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH0REQMASKC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
<> 128:9bcdf88f62b0 755 #define DMA_CHREQMASKC_CH1REQMASKC (0x1UL << 1) /**< Channel 1 Request Mask Clear */
<> 128:9bcdf88f62b0 756 #define _DMA_CHREQMASKC_CH1REQMASKC_SHIFT 1 /**< Shift value for DMA_CH1REQMASKC */
<> 128:9bcdf88f62b0 757 #define _DMA_CHREQMASKC_CH1REQMASKC_MASK 0x2UL /**< Bit mask for DMA_CH1REQMASKC */
<> 128:9bcdf88f62b0 758 #define _DMA_CHREQMASKC_CH1REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
<> 128:9bcdf88f62b0 759 #define DMA_CHREQMASKC_CH1REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH1REQMASKC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
<> 128:9bcdf88f62b0 760 #define DMA_CHREQMASKC_CH2REQMASKC (0x1UL << 2) /**< Channel 2 Request Mask Clear */
<> 128:9bcdf88f62b0 761 #define _DMA_CHREQMASKC_CH2REQMASKC_SHIFT 2 /**< Shift value for DMA_CH2REQMASKC */
<> 128:9bcdf88f62b0 762 #define _DMA_CHREQMASKC_CH2REQMASKC_MASK 0x4UL /**< Bit mask for DMA_CH2REQMASKC */
<> 128:9bcdf88f62b0 763 #define _DMA_CHREQMASKC_CH2REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
<> 128:9bcdf88f62b0 764 #define DMA_CHREQMASKC_CH2REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH2REQMASKC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
<> 128:9bcdf88f62b0 765 #define DMA_CHREQMASKC_CH3REQMASKC (0x1UL << 3) /**< Channel 3 Request Mask Clear */
<> 128:9bcdf88f62b0 766 #define _DMA_CHREQMASKC_CH3REQMASKC_SHIFT 3 /**< Shift value for DMA_CH3REQMASKC */
<> 128:9bcdf88f62b0 767 #define _DMA_CHREQMASKC_CH3REQMASKC_MASK 0x8UL /**< Bit mask for DMA_CH3REQMASKC */
<> 128:9bcdf88f62b0 768 #define _DMA_CHREQMASKC_CH3REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
<> 128:9bcdf88f62b0 769 #define DMA_CHREQMASKC_CH3REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH3REQMASKC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
<> 128:9bcdf88f62b0 770 #define DMA_CHREQMASKC_CH4REQMASKC (0x1UL << 4) /**< Channel 4 Request Mask Clear */
<> 128:9bcdf88f62b0 771 #define _DMA_CHREQMASKC_CH4REQMASKC_SHIFT 4 /**< Shift value for DMA_CH4REQMASKC */
<> 128:9bcdf88f62b0 772 #define _DMA_CHREQMASKC_CH4REQMASKC_MASK 0x10UL /**< Bit mask for DMA_CH4REQMASKC */
<> 128:9bcdf88f62b0 773 #define _DMA_CHREQMASKC_CH4REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
<> 128:9bcdf88f62b0 774 #define DMA_CHREQMASKC_CH4REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH4REQMASKC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
<> 128:9bcdf88f62b0 775 #define DMA_CHREQMASKC_CH5REQMASKC (0x1UL << 5) /**< Channel 5 Request Mask Clear */
<> 128:9bcdf88f62b0 776 #define _DMA_CHREQMASKC_CH5REQMASKC_SHIFT 5 /**< Shift value for DMA_CH5REQMASKC */
<> 128:9bcdf88f62b0 777 #define _DMA_CHREQMASKC_CH5REQMASKC_MASK 0x20UL /**< Bit mask for DMA_CH5REQMASKC */
<> 128:9bcdf88f62b0 778 #define _DMA_CHREQMASKC_CH5REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
<> 128:9bcdf88f62b0 779 #define DMA_CHREQMASKC_CH5REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH5REQMASKC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
<> 128:9bcdf88f62b0 780
<> 128:9bcdf88f62b0 781 /* Bit fields for DMA CHENS */
<> 128:9bcdf88f62b0 782 #define _DMA_CHENS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHENS */
<> 128:9bcdf88f62b0 783 #define _DMA_CHENS_MASK 0x0000003FUL /**< Mask for DMA_CHENS */
<> 128:9bcdf88f62b0 784 #define DMA_CHENS_CH0ENS (0x1UL << 0) /**< Channel 0 Enable Set */
<> 128:9bcdf88f62b0 785 #define _DMA_CHENS_CH0ENS_SHIFT 0 /**< Shift value for DMA_CH0ENS */
<> 128:9bcdf88f62b0 786 #define _DMA_CHENS_CH0ENS_MASK 0x1UL /**< Bit mask for DMA_CH0ENS */
<> 128:9bcdf88f62b0 787 #define _DMA_CHENS_CH0ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
<> 128:9bcdf88f62b0 788 #define DMA_CHENS_CH0ENS_DEFAULT (_DMA_CHENS_CH0ENS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHENS */
<> 128:9bcdf88f62b0 789 #define DMA_CHENS_CH1ENS (0x1UL << 1) /**< Channel 1 Enable Set */
<> 128:9bcdf88f62b0 790 #define _DMA_CHENS_CH1ENS_SHIFT 1 /**< Shift value for DMA_CH1ENS */
<> 128:9bcdf88f62b0 791 #define _DMA_CHENS_CH1ENS_MASK 0x2UL /**< Bit mask for DMA_CH1ENS */
<> 128:9bcdf88f62b0 792 #define _DMA_CHENS_CH1ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
<> 128:9bcdf88f62b0 793 #define DMA_CHENS_CH1ENS_DEFAULT (_DMA_CHENS_CH1ENS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHENS */
<> 128:9bcdf88f62b0 794 #define DMA_CHENS_CH2ENS (0x1UL << 2) /**< Channel 2 Enable Set */
<> 128:9bcdf88f62b0 795 #define _DMA_CHENS_CH2ENS_SHIFT 2 /**< Shift value for DMA_CH2ENS */
<> 128:9bcdf88f62b0 796 #define _DMA_CHENS_CH2ENS_MASK 0x4UL /**< Bit mask for DMA_CH2ENS */
<> 128:9bcdf88f62b0 797 #define _DMA_CHENS_CH2ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
<> 128:9bcdf88f62b0 798 #define DMA_CHENS_CH2ENS_DEFAULT (_DMA_CHENS_CH2ENS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHENS */
<> 128:9bcdf88f62b0 799 #define DMA_CHENS_CH3ENS (0x1UL << 3) /**< Channel 3 Enable Set */
<> 128:9bcdf88f62b0 800 #define _DMA_CHENS_CH3ENS_SHIFT 3 /**< Shift value for DMA_CH3ENS */
<> 128:9bcdf88f62b0 801 #define _DMA_CHENS_CH3ENS_MASK 0x8UL /**< Bit mask for DMA_CH3ENS */
<> 128:9bcdf88f62b0 802 #define _DMA_CHENS_CH3ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
<> 128:9bcdf88f62b0 803 #define DMA_CHENS_CH3ENS_DEFAULT (_DMA_CHENS_CH3ENS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHENS */
<> 128:9bcdf88f62b0 804 #define DMA_CHENS_CH4ENS (0x1UL << 4) /**< Channel 4 Enable Set */
<> 128:9bcdf88f62b0 805 #define _DMA_CHENS_CH4ENS_SHIFT 4 /**< Shift value for DMA_CH4ENS */
<> 128:9bcdf88f62b0 806 #define _DMA_CHENS_CH4ENS_MASK 0x10UL /**< Bit mask for DMA_CH4ENS */
<> 128:9bcdf88f62b0 807 #define _DMA_CHENS_CH4ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
<> 128:9bcdf88f62b0 808 #define DMA_CHENS_CH4ENS_DEFAULT (_DMA_CHENS_CH4ENS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHENS */
<> 128:9bcdf88f62b0 809 #define DMA_CHENS_CH5ENS (0x1UL << 5) /**< Channel 5 Enable Set */
<> 128:9bcdf88f62b0 810 #define _DMA_CHENS_CH5ENS_SHIFT 5 /**< Shift value for DMA_CH5ENS */
<> 128:9bcdf88f62b0 811 #define _DMA_CHENS_CH5ENS_MASK 0x20UL /**< Bit mask for DMA_CH5ENS */
<> 128:9bcdf88f62b0 812 #define _DMA_CHENS_CH5ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
<> 128:9bcdf88f62b0 813 #define DMA_CHENS_CH5ENS_DEFAULT (_DMA_CHENS_CH5ENS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHENS */
<> 128:9bcdf88f62b0 814
<> 128:9bcdf88f62b0 815 /* Bit fields for DMA CHENC */
<> 128:9bcdf88f62b0 816 #define _DMA_CHENC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHENC */
<> 128:9bcdf88f62b0 817 #define _DMA_CHENC_MASK 0x0000003FUL /**< Mask for DMA_CHENC */
<> 128:9bcdf88f62b0 818 #define DMA_CHENC_CH0ENC (0x1UL << 0) /**< Channel 0 Enable Clear */
<> 128:9bcdf88f62b0 819 #define _DMA_CHENC_CH0ENC_SHIFT 0 /**< Shift value for DMA_CH0ENC */
<> 128:9bcdf88f62b0 820 #define _DMA_CHENC_CH0ENC_MASK 0x1UL /**< Bit mask for DMA_CH0ENC */
<> 128:9bcdf88f62b0 821 #define _DMA_CHENC_CH0ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
<> 128:9bcdf88f62b0 822 #define DMA_CHENC_CH0ENC_DEFAULT (_DMA_CHENC_CH0ENC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHENC */
<> 128:9bcdf88f62b0 823 #define DMA_CHENC_CH1ENC (0x1UL << 1) /**< Channel 1 Enable Clear */
<> 128:9bcdf88f62b0 824 #define _DMA_CHENC_CH1ENC_SHIFT 1 /**< Shift value for DMA_CH1ENC */
<> 128:9bcdf88f62b0 825 #define _DMA_CHENC_CH1ENC_MASK 0x2UL /**< Bit mask for DMA_CH1ENC */
<> 128:9bcdf88f62b0 826 #define _DMA_CHENC_CH1ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
<> 128:9bcdf88f62b0 827 #define DMA_CHENC_CH1ENC_DEFAULT (_DMA_CHENC_CH1ENC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHENC */
<> 128:9bcdf88f62b0 828 #define DMA_CHENC_CH2ENC (0x1UL << 2) /**< Channel 2 Enable Clear */
<> 128:9bcdf88f62b0 829 #define _DMA_CHENC_CH2ENC_SHIFT 2 /**< Shift value for DMA_CH2ENC */
<> 128:9bcdf88f62b0 830 #define _DMA_CHENC_CH2ENC_MASK 0x4UL /**< Bit mask for DMA_CH2ENC */
<> 128:9bcdf88f62b0 831 #define _DMA_CHENC_CH2ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
<> 128:9bcdf88f62b0 832 #define DMA_CHENC_CH2ENC_DEFAULT (_DMA_CHENC_CH2ENC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHENC */
<> 128:9bcdf88f62b0 833 #define DMA_CHENC_CH3ENC (0x1UL << 3) /**< Channel 3 Enable Clear */
<> 128:9bcdf88f62b0 834 #define _DMA_CHENC_CH3ENC_SHIFT 3 /**< Shift value for DMA_CH3ENC */
<> 128:9bcdf88f62b0 835 #define _DMA_CHENC_CH3ENC_MASK 0x8UL /**< Bit mask for DMA_CH3ENC */
<> 128:9bcdf88f62b0 836 #define _DMA_CHENC_CH3ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
<> 128:9bcdf88f62b0 837 #define DMA_CHENC_CH3ENC_DEFAULT (_DMA_CHENC_CH3ENC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHENC */
<> 128:9bcdf88f62b0 838 #define DMA_CHENC_CH4ENC (0x1UL << 4) /**< Channel 4 Enable Clear */
<> 128:9bcdf88f62b0 839 #define _DMA_CHENC_CH4ENC_SHIFT 4 /**< Shift value for DMA_CH4ENC */
<> 128:9bcdf88f62b0 840 #define _DMA_CHENC_CH4ENC_MASK 0x10UL /**< Bit mask for DMA_CH4ENC */
<> 128:9bcdf88f62b0 841 #define _DMA_CHENC_CH4ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
<> 128:9bcdf88f62b0 842 #define DMA_CHENC_CH4ENC_DEFAULT (_DMA_CHENC_CH4ENC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHENC */
<> 128:9bcdf88f62b0 843 #define DMA_CHENC_CH5ENC (0x1UL << 5) /**< Channel 5 Enable Clear */
<> 128:9bcdf88f62b0 844 #define _DMA_CHENC_CH5ENC_SHIFT 5 /**< Shift value for DMA_CH5ENC */
<> 128:9bcdf88f62b0 845 #define _DMA_CHENC_CH5ENC_MASK 0x20UL /**< Bit mask for DMA_CH5ENC */
<> 128:9bcdf88f62b0 846 #define _DMA_CHENC_CH5ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
<> 128:9bcdf88f62b0 847 #define DMA_CHENC_CH5ENC_DEFAULT (_DMA_CHENC_CH5ENC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHENC */
<> 128:9bcdf88f62b0 848
<> 128:9bcdf88f62b0 849 /* Bit fields for DMA CHALTS */
<> 128:9bcdf88f62b0 850 #define _DMA_CHALTS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHALTS */
<> 128:9bcdf88f62b0 851 #define _DMA_CHALTS_MASK 0x0000003FUL /**< Mask for DMA_CHALTS */
<> 128:9bcdf88f62b0 852 #define DMA_CHALTS_CH0ALTS (0x1UL << 0) /**< Channel 0 Alternate Structure Set */
<> 128:9bcdf88f62b0 853 #define _DMA_CHALTS_CH0ALTS_SHIFT 0 /**< Shift value for DMA_CH0ALTS */
<> 128:9bcdf88f62b0 854 #define _DMA_CHALTS_CH0ALTS_MASK 0x1UL /**< Bit mask for DMA_CH0ALTS */
<> 128:9bcdf88f62b0 855 #define _DMA_CHALTS_CH0ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
<> 128:9bcdf88f62b0 856 #define DMA_CHALTS_CH0ALTS_DEFAULT (_DMA_CHALTS_CH0ALTS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHALTS */
<> 128:9bcdf88f62b0 857 #define DMA_CHALTS_CH1ALTS (0x1UL << 1) /**< Channel 1 Alternate Structure Set */
<> 128:9bcdf88f62b0 858 #define _DMA_CHALTS_CH1ALTS_SHIFT 1 /**< Shift value for DMA_CH1ALTS */
<> 128:9bcdf88f62b0 859 #define _DMA_CHALTS_CH1ALTS_MASK 0x2UL /**< Bit mask for DMA_CH1ALTS */
<> 128:9bcdf88f62b0 860 #define _DMA_CHALTS_CH1ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
<> 128:9bcdf88f62b0 861 #define DMA_CHALTS_CH1ALTS_DEFAULT (_DMA_CHALTS_CH1ALTS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHALTS */
<> 128:9bcdf88f62b0 862 #define DMA_CHALTS_CH2ALTS (0x1UL << 2) /**< Channel 2 Alternate Structure Set */
<> 128:9bcdf88f62b0 863 #define _DMA_CHALTS_CH2ALTS_SHIFT 2 /**< Shift value for DMA_CH2ALTS */
<> 128:9bcdf88f62b0 864 #define _DMA_CHALTS_CH2ALTS_MASK 0x4UL /**< Bit mask for DMA_CH2ALTS */
<> 128:9bcdf88f62b0 865 #define _DMA_CHALTS_CH2ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
<> 128:9bcdf88f62b0 866 #define DMA_CHALTS_CH2ALTS_DEFAULT (_DMA_CHALTS_CH2ALTS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHALTS */
<> 128:9bcdf88f62b0 867 #define DMA_CHALTS_CH3ALTS (0x1UL << 3) /**< Channel 3 Alternate Structure Set */
<> 128:9bcdf88f62b0 868 #define _DMA_CHALTS_CH3ALTS_SHIFT 3 /**< Shift value for DMA_CH3ALTS */
<> 128:9bcdf88f62b0 869 #define _DMA_CHALTS_CH3ALTS_MASK 0x8UL /**< Bit mask for DMA_CH3ALTS */
<> 128:9bcdf88f62b0 870 #define _DMA_CHALTS_CH3ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
<> 128:9bcdf88f62b0 871 #define DMA_CHALTS_CH3ALTS_DEFAULT (_DMA_CHALTS_CH3ALTS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHALTS */
<> 128:9bcdf88f62b0 872 #define DMA_CHALTS_CH4ALTS (0x1UL << 4) /**< Channel 4 Alternate Structure Set */
<> 128:9bcdf88f62b0 873 #define _DMA_CHALTS_CH4ALTS_SHIFT 4 /**< Shift value for DMA_CH4ALTS */
<> 128:9bcdf88f62b0 874 #define _DMA_CHALTS_CH4ALTS_MASK 0x10UL /**< Bit mask for DMA_CH4ALTS */
<> 128:9bcdf88f62b0 875 #define _DMA_CHALTS_CH4ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
<> 128:9bcdf88f62b0 876 #define DMA_CHALTS_CH4ALTS_DEFAULT (_DMA_CHALTS_CH4ALTS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHALTS */
<> 128:9bcdf88f62b0 877 #define DMA_CHALTS_CH5ALTS (0x1UL << 5) /**< Channel 5 Alternate Structure Set */
<> 128:9bcdf88f62b0 878 #define _DMA_CHALTS_CH5ALTS_SHIFT 5 /**< Shift value for DMA_CH5ALTS */
<> 128:9bcdf88f62b0 879 #define _DMA_CHALTS_CH5ALTS_MASK 0x20UL /**< Bit mask for DMA_CH5ALTS */
<> 128:9bcdf88f62b0 880 #define _DMA_CHALTS_CH5ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
<> 128:9bcdf88f62b0 881 #define DMA_CHALTS_CH5ALTS_DEFAULT (_DMA_CHALTS_CH5ALTS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHALTS */
<> 128:9bcdf88f62b0 882
<> 128:9bcdf88f62b0 883 /* Bit fields for DMA CHALTC */
<> 128:9bcdf88f62b0 884 #define _DMA_CHALTC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHALTC */
<> 128:9bcdf88f62b0 885 #define _DMA_CHALTC_MASK 0x0000003FUL /**< Mask for DMA_CHALTC */
<> 128:9bcdf88f62b0 886 #define DMA_CHALTC_CH0ALTC (0x1UL << 0) /**< Channel 0 Alternate Clear */
<> 128:9bcdf88f62b0 887 #define _DMA_CHALTC_CH0ALTC_SHIFT 0 /**< Shift value for DMA_CH0ALTC */
<> 128:9bcdf88f62b0 888 #define _DMA_CHALTC_CH0ALTC_MASK 0x1UL /**< Bit mask for DMA_CH0ALTC */
<> 128:9bcdf88f62b0 889 #define _DMA_CHALTC_CH0ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
<> 128:9bcdf88f62b0 890 #define DMA_CHALTC_CH0ALTC_DEFAULT (_DMA_CHALTC_CH0ALTC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHALTC */
<> 128:9bcdf88f62b0 891 #define DMA_CHALTC_CH1ALTC (0x1UL << 1) /**< Channel 1 Alternate Clear */
<> 128:9bcdf88f62b0 892 #define _DMA_CHALTC_CH1ALTC_SHIFT 1 /**< Shift value for DMA_CH1ALTC */
<> 128:9bcdf88f62b0 893 #define _DMA_CHALTC_CH1ALTC_MASK 0x2UL /**< Bit mask for DMA_CH1ALTC */
<> 128:9bcdf88f62b0 894 #define _DMA_CHALTC_CH1ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
<> 128:9bcdf88f62b0 895 #define DMA_CHALTC_CH1ALTC_DEFAULT (_DMA_CHALTC_CH1ALTC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHALTC */
<> 128:9bcdf88f62b0 896 #define DMA_CHALTC_CH2ALTC (0x1UL << 2) /**< Channel 2 Alternate Clear */
<> 128:9bcdf88f62b0 897 #define _DMA_CHALTC_CH2ALTC_SHIFT 2 /**< Shift value for DMA_CH2ALTC */
<> 128:9bcdf88f62b0 898 #define _DMA_CHALTC_CH2ALTC_MASK 0x4UL /**< Bit mask for DMA_CH2ALTC */
<> 128:9bcdf88f62b0 899 #define _DMA_CHALTC_CH2ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
<> 128:9bcdf88f62b0 900 #define DMA_CHALTC_CH2ALTC_DEFAULT (_DMA_CHALTC_CH2ALTC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHALTC */
<> 128:9bcdf88f62b0 901 #define DMA_CHALTC_CH3ALTC (0x1UL << 3) /**< Channel 3 Alternate Clear */
<> 128:9bcdf88f62b0 902 #define _DMA_CHALTC_CH3ALTC_SHIFT 3 /**< Shift value for DMA_CH3ALTC */
<> 128:9bcdf88f62b0 903 #define _DMA_CHALTC_CH3ALTC_MASK 0x8UL /**< Bit mask for DMA_CH3ALTC */
<> 128:9bcdf88f62b0 904 #define _DMA_CHALTC_CH3ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
<> 128:9bcdf88f62b0 905 #define DMA_CHALTC_CH3ALTC_DEFAULT (_DMA_CHALTC_CH3ALTC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHALTC */
<> 128:9bcdf88f62b0 906 #define DMA_CHALTC_CH4ALTC (0x1UL << 4) /**< Channel 4 Alternate Clear */
<> 128:9bcdf88f62b0 907 #define _DMA_CHALTC_CH4ALTC_SHIFT 4 /**< Shift value for DMA_CH4ALTC */
<> 128:9bcdf88f62b0 908 #define _DMA_CHALTC_CH4ALTC_MASK 0x10UL /**< Bit mask for DMA_CH4ALTC */
<> 128:9bcdf88f62b0 909 #define _DMA_CHALTC_CH4ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
<> 128:9bcdf88f62b0 910 #define DMA_CHALTC_CH4ALTC_DEFAULT (_DMA_CHALTC_CH4ALTC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHALTC */
<> 128:9bcdf88f62b0 911 #define DMA_CHALTC_CH5ALTC (0x1UL << 5) /**< Channel 5 Alternate Clear */
<> 128:9bcdf88f62b0 912 #define _DMA_CHALTC_CH5ALTC_SHIFT 5 /**< Shift value for DMA_CH5ALTC */
<> 128:9bcdf88f62b0 913 #define _DMA_CHALTC_CH5ALTC_MASK 0x20UL /**< Bit mask for DMA_CH5ALTC */
<> 128:9bcdf88f62b0 914 #define _DMA_CHALTC_CH5ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
<> 128:9bcdf88f62b0 915 #define DMA_CHALTC_CH5ALTC_DEFAULT (_DMA_CHALTC_CH5ALTC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHALTC */
<> 128:9bcdf88f62b0 916
<> 128:9bcdf88f62b0 917 /* Bit fields for DMA CHPRIS */
<> 128:9bcdf88f62b0 918 #define _DMA_CHPRIS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHPRIS */
<> 128:9bcdf88f62b0 919 #define _DMA_CHPRIS_MASK 0x0000003FUL /**< Mask for DMA_CHPRIS */
<> 128:9bcdf88f62b0 920 #define DMA_CHPRIS_CH0PRIS (0x1UL << 0) /**< Channel 0 High Priority Set */
<> 128:9bcdf88f62b0 921 #define _DMA_CHPRIS_CH0PRIS_SHIFT 0 /**< Shift value for DMA_CH0PRIS */
<> 128:9bcdf88f62b0 922 #define _DMA_CHPRIS_CH0PRIS_MASK 0x1UL /**< Bit mask for DMA_CH0PRIS */
<> 128:9bcdf88f62b0 923 #define _DMA_CHPRIS_CH0PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
<> 128:9bcdf88f62b0 924 #define DMA_CHPRIS_CH0PRIS_DEFAULT (_DMA_CHPRIS_CH0PRIS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHPRIS */
<> 128:9bcdf88f62b0 925 #define DMA_CHPRIS_CH1PRIS (0x1UL << 1) /**< Channel 1 High Priority Set */
<> 128:9bcdf88f62b0 926 #define _DMA_CHPRIS_CH1PRIS_SHIFT 1 /**< Shift value for DMA_CH1PRIS */
<> 128:9bcdf88f62b0 927 #define _DMA_CHPRIS_CH1PRIS_MASK 0x2UL /**< Bit mask for DMA_CH1PRIS */
<> 128:9bcdf88f62b0 928 #define _DMA_CHPRIS_CH1PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
<> 128:9bcdf88f62b0 929 #define DMA_CHPRIS_CH1PRIS_DEFAULT (_DMA_CHPRIS_CH1PRIS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHPRIS */
<> 128:9bcdf88f62b0 930 #define DMA_CHPRIS_CH2PRIS (0x1UL << 2) /**< Channel 2 High Priority Set */
<> 128:9bcdf88f62b0 931 #define _DMA_CHPRIS_CH2PRIS_SHIFT 2 /**< Shift value for DMA_CH2PRIS */
<> 128:9bcdf88f62b0 932 #define _DMA_CHPRIS_CH2PRIS_MASK 0x4UL /**< Bit mask for DMA_CH2PRIS */
<> 128:9bcdf88f62b0 933 #define _DMA_CHPRIS_CH2PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
<> 128:9bcdf88f62b0 934 #define DMA_CHPRIS_CH2PRIS_DEFAULT (_DMA_CHPRIS_CH2PRIS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHPRIS */
<> 128:9bcdf88f62b0 935 #define DMA_CHPRIS_CH3PRIS (0x1UL << 3) /**< Channel 3 High Priority Set */
<> 128:9bcdf88f62b0 936 #define _DMA_CHPRIS_CH3PRIS_SHIFT 3 /**< Shift value for DMA_CH3PRIS */
<> 128:9bcdf88f62b0 937 #define _DMA_CHPRIS_CH3PRIS_MASK 0x8UL /**< Bit mask for DMA_CH3PRIS */
<> 128:9bcdf88f62b0 938 #define _DMA_CHPRIS_CH3PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
<> 128:9bcdf88f62b0 939 #define DMA_CHPRIS_CH3PRIS_DEFAULT (_DMA_CHPRIS_CH3PRIS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHPRIS */
<> 128:9bcdf88f62b0 940 #define DMA_CHPRIS_CH4PRIS (0x1UL << 4) /**< Channel 4 High Priority Set */
<> 128:9bcdf88f62b0 941 #define _DMA_CHPRIS_CH4PRIS_SHIFT 4 /**< Shift value for DMA_CH4PRIS */
<> 128:9bcdf88f62b0 942 #define _DMA_CHPRIS_CH4PRIS_MASK 0x10UL /**< Bit mask for DMA_CH4PRIS */
<> 128:9bcdf88f62b0 943 #define _DMA_CHPRIS_CH4PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
<> 128:9bcdf88f62b0 944 #define DMA_CHPRIS_CH4PRIS_DEFAULT (_DMA_CHPRIS_CH4PRIS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHPRIS */
<> 128:9bcdf88f62b0 945 #define DMA_CHPRIS_CH5PRIS (0x1UL << 5) /**< Channel 5 High Priority Set */
<> 128:9bcdf88f62b0 946 #define _DMA_CHPRIS_CH5PRIS_SHIFT 5 /**< Shift value for DMA_CH5PRIS */
<> 128:9bcdf88f62b0 947 #define _DMA_CHPRIS_CH5PRIS_MASK 0x20UL /**< Bit mask for DMA_CH5PRIS */
<> 128:9bcdf88f62b0 948 #define _DMA_CHPRIS_CH5PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
<> 128:9bcdf88f62b0 949 #define DMA_CHPRIS_CH5PRIS_DEFAULT (_DMA_CHPRIS_CH5PRIS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHPRIS */
<> 128:9bcdf88f62b0 950
<> 128:9bcdf88f62b0 951 /* Bit fields for DMA CHPRIC */
<> 128:9bcdf88f62b0 952 #define _DMA_CHPRIC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHPRIC */
<> 128:9bcdf88f62b0 953 #define _DMA_CHPRIC_MASK 0x0000003FUL /**< Mask for DMA_CHPRIC */
<> 128:9bcdf88f62b0 954 #define DMA_CHPRIC_CH0PRIC (0x1UL << 0) /**< Channel 0 High Priority Clear */
<> 128:9bcdf88f62b0 955 #define _DMA_CHPRIC_CH0PRIC_SHIFT 0 /**< Shift value for DMA_CH0PRIC */
<> 128:9bcdf88f62b0 956 #define _DMA_CHPRIC_CH0PRIC_MASK 0x1UL /**< Bit mask for DMA_CH0PRIC */
<> 128:9bcdf88f62b0 957 #define _DMA_CHPRIC_CH0PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
<> 128:9bcdf88f62b0 958 #define DMA_CHPRIC_CH0PRIC_DEFAULT (_DMA_CHPRIC_CH0PRIC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHPRIC */
<> 128:9bcdf88f62b0 959 #define DMA_CHPRIC_CH1PRIC (0x1UL << 1) /**< Channel 1 High Priority Clear */
<> 128:9bcdf88f62b0 960 #define _DMA_CHPRIC_CH1PRIC_SHIFT 1 /**< Shift value for DMA_CH1PRIC */
<> 128:9bcdf88f62b0 961 #define _DMA_CHPRIC_CH1PRIC_MASK 0x2UL /**< Bit mask for DMA_CH1PRIC */
<> 128:9bcdf88f62b0 962 #define _DMA_CHPRIC_CH1PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
<> 128:9bcdf88f62b0 963 #define DMA_CHPRIC_CH1PRIC_DEFAULT (_DMA_CHPRIC_CH1PRIC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHPRIC */
<> 128:9bcdf88f62b0 964 #define DMA_CHPRIC_CH2PRIC (0x1UL << 2) /**< Channel 2 High Priority Clear */
<> 128:9bcdf88f62b0 965 #define _DMA_CHPRIC_CH2PRIC_SHIFT 2 /**< Shift value for DMA_CH2PRIC */
<> 128:9bcdf88f62b0 966 #define _DMA_CHPRIC_CH2PRIC_MASK 0x4UL /**< Bit mask for DMA_CH2PRIC */
<> 128:9bcdf88f62b0 967 #define _DMA_CHPRIC_CH2PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
<> 128:9bcdf88f62b0 968 #define DMA_CHPRIC_CH2PRIC_DEFAULT (_DMA_CHPRIC_CH2PRIC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHPRIC */
<> 128:9bcdf88f62b0 969 #define DMA_CHPRIC_CH3PRIC (0x1UL << 3) /**< Channel 3 High Priority Clear */
<> 128:9bcdf88f62b0 970 #define _DMA_CHPRIC_CH3PRIC_SHIFT 3 /**< Shift value for DMA_CH3PRIC */
<> 128:9bcdf88f62b0 971 #define _DMA_CHPRIC_CH3PRIC_MASK 0x8UL /**< Bit mask for DMA_CH3PRIC */
<> 128:9bcdf88f62b0 972 #define _DMA_CHPRIC_CH3PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
<> 128:9bcdf88f62b0 973 #define DMA_CHPRIC_CH3PRIC_DEFAULT (_DMA_CHPRIC_CH3PRIC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHPRIC */
<> 128:9bcdf88f62b0 974 #define DMA_CHPRIC_CH4PRIC (0x1UL << 4) /**< Channel 4 High Priority Clear */
<> 128:9bcdf88f62b0 975 #define _DMA_CHPRIC_CH4PRIC_SHIFT 4 /**< Shift value for DMA_CH4PRIC */
<> 128:9bcdf88f62b0 976 #define _DMA_CHPRIC_CH4PRIC_MASK 0x10UL /**< Bit mask for DMA_CH4PRIC */
<> 128:9bcdf88f62b0 977 #define _DMA_CHPRIC_CH4PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
<> 128:9bcdf88f62b0 978 #define DMA_CHPRIC_CH4PRIC_DEFAULT (_DMA_CHPRIC_CH4PRIC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHPRIC */
<> 128:9bcdf88f62b0 979 #define DMA_CHPRIC_CH5PRIC (0x1UL << 5) /**< Channel 5 High Priority Clear */
<> 128:9bcdf88f62b0 980 #define _DMA_CHPRIC_CH5PRIC_SHIFT 5 /**< Shift value for DMA_CH5PRIC */
<> 128:9bcdf88f62b0 981 #define _DMA_CHPRIC_CH5PRIC_MASK 0x20UL /**< Bit mask for DMA_CH5PRIC */
<> 128:9bcdf88f62b0 982 #define _DMA_CHPRIC_CH5PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
<> 128:9bcdf88f62b0 983 #define DMA_CHPRIC_CH5PRIC_DEFAULT (_DMA_CHPRIC_CH5PRIC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHPRIC */
<> 128:9bcdf88f62b0 984
<> 128:9bcdf88f62b0 985 /* Bit fields for DMA ERRORC */
<> 128:9bcdf88f62b0 986 #define _DMA_ERRORC_RESETVALUE 0x00000000UL /**< Default value for DMA_ERRORC */
<> 128:9bcdf88f62b0 987 #define _DMA_ERRORC_MASK 0x00000001UL /**< Mask for DMA_ERRORC */
<> 128:9bcdf88f62b0 988 #define DMA_ERRORC_ERRORC (0x1UL << 0) /**< Bus Error Clear */
<> 128:9bcdf88f62b0 989 #define _DMA_ERRORC_ERRORC_SHIFT 0 /**< Shift value for DMA_ERRORC */
<> 128:9bcdf88f62b0 990 #define _DMA_ERRORC_ERRORC_MASK 0x1UL /**< Bit mask for DMA_ERRORC */
<> 128:9bcdf88f62b0 991 #define _DMA_ERRORC_ERRORC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_ERRORC */
<> 128:9bcdf88f62b0 992 #define DMA_ERRORC_ERRORC_DEFAULT (_DMA_ERRORC_ERRORC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_ERRORC */
<> 128:9bcdf88f62b0 993
<> 128:9bcdf88f62b0 994 /* Bit fields for DMA CHREQSTATUS */
<> 128:9bcdf88f62b0 995 #define _DMA_CHREQSTATUS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQSTATUS */
<> 128:9bcdf88f62b0 996 #define _DMA_CHREQSTATUS_MASK 0x0000003FUL /**< Mask for DMA_CHREQSTATUS */
<> 128:9bcdf88f62b0 997 #define DMA_CHREQSTATUS_CH0REQSTATUS (0x1UL << 0) /**< Channel 0 Request Status */
<> 128:9bcdf88f62b0 998 #define _DMA_CHREQSTATUS_CH0REQSTATUS_SHIFT 0 /**< Shift value for DMA_CH0REQSTATUS */
<> 128:9bcdf88f62b0 999 #define _DMA_CHREQSTATUS_CH0REQSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0REQSTATUS */
<> 128:9bcdf88f62b0 1000 #define _DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
<> 128:9bcdf88f62b0 1001 #define DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
<> 128:9bcdf88f62b0 1002 #define DMA_CHREQSTATUS_CH1REQSTATUS (0x1UL << 1) /**< Channel 1 Request Status */
<> 128:9bcdf88f62b0 1003 #define _DMA_CHREQSTATUS_CH1REQSTATUS_SHIFT 1 /**< Shift value for DMA_CH1REQSTATUS */
<> 128:9bcdf88f62b0 1004 #define _DMA_CHREQSTATUS_CH1REQSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1REQSTATUS */
<> 128:9bcdf88f62b0 1005 #define _DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
<> 128:9bcdf88f62b0 1006 #define DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
<> 128:9bcdf88f62b0 1007 #define DMA_CHREQSTATUS_CH2REQSTATUS (0x1UL << 2) /**< Channel 2 Request Status */
<> 128:9bcdf88f62b0 1008 #define _DMA_CHREQSTATUS_CH2REQSTATUS_SHIFT 2 /**< Shift value for DMA_CH2REQSTATUS */
<> 128:9bcdf88f62b0 1009 #define _DMA_CHREQSTATUS_CH2REQSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2REQSTATUS */
<> 128:9bcdf88f62b0 1010 #define _DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
<> 128:9bcdf88f62b0 1011 #define DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
<> 128:9bcdf88f62b0 1012 #define DMA_CHREQSTATUS_CH3REQSTATUS (0x1UL << 3) /**< Channel 3 Request Status */
<> 128:9bcdf88f62b0 1013 #define _DMA_CHREQSTATUS_CH3REQSTATUS_SHIFT 3 /**< Shift value for DMA_CH3REQSTATUS */
<> 128:9bcdf88f62b0 1014 #define _DMA_CHREQSTATUS_CH3REQSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3REQSTATUS */
<> 128:9bcdf88f62b0 1015 #define _DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
<> 128:9bcdf88f62b0 1016 #define DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
<> 128:9bcdf88f62b0 1017 #define DMA_CHREQSTATUS_CH4REQSTATUS (0x1UL << 4) /**< Channel 4 Request Status */
<> 128:9bcdf88f62b0 1018 #define _DMA_CHREQSTATUS_CH4REQSTATUS_SHIFT 4 /**< Shift value for DMA_CH4REQSTATUS */
<> 128:9bcdf88f62b0 1019 #define _DMA_CHREQSTATUS_CH4REQSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4REQSTATUS */
<> 128:9bcdf88f62b0 1020 #define _DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
<> 128:9bcdf88f62b0 1021 #define DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
<> 128:9bcdf88f62b0 1022 #define DMA_CHREQSTATUS_CH5REQSTATUS (0x1UL << 5) /**< Channel 5 Request Status */
<> 128:9bcdf88f62b0 1023 #define _DMA_CHREQSTATUS_CH5REQSTATUS_SHIFT 5 /**< Shift value for DMA_CH5REQSTATUS */
<> 128:9bcdf88f62b0 1024 #define _DMA_CHREQSTATUS_CH5REQSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5REQSTATUS */
<> 128:9bcdf88f62b0 1025 #define _DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
<> 128:9bcdf88f62b0 1026 #define DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
<> 128:9bcdf88f62b0 1027
<> 128:9bcdf88f62b0 1028 /* Bit fields for DMA CHSREQSTATUS */
<> 128:9bcdf88f62b0 1029 #define _DMA_CHSREQSTATUS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHSREQSTATUS */
<> 128:9bcdf88f62b0 1030 #define _DMA_CHSREQSTATUS_MASK 0x0000003FUL /**< Mask for DMA_CHSREQSTATUS */
<> 128:9bcdf88f62b0 1031 #define DMA_CHSREQSTATUS_CH0SREQSTATUS (0x1UL << 0) /**< Channel 0 Single Request Status */
<> 128:9bcdf88f62b0 1032 #define _DMA_CHSREQSTATUS_CH0SREQSTATUS_SHIFT 0 /**< Shift value for DMA_CH0SREQSTATUS */
<> 128:9bcdf88f62b0 1033 #define _DMA_CHSREQSTATUS_CH0SREQSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0SREQSTATUS */
<> 128:9bcdf88f62b0 1034 #define _DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
<> 128:9bcdf88f62b0 1035 #define DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
<> 128:9bcdf88f62b0 1036 #define DMA_CHSREQSTATUS_CH1SREQSTATUS (0x1UL << 1) /**< Channel 1 Single Request Status */
<> 128:9bcdf88f62b0 1037 #define _DMA_CHSREQSTATUS_CH1SREQSTATUS_SHIFT 1 /**< Shift value for DMA_CH1SREQSTATUS */
<> 128:9bcdf88f62b0 1038 #define _DMA_CHSREQSTATUS_CH1SREQSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1SREQSTATUS */
<> 128:9bcdf88f62b0 1039 #define _DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
<> 128:9bcdf88f62b0 1040 #define DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
<> 128:9bcdf88f62b0 1041 #define DMA_CHSREQSTATUS_CH2SREQSTATUS (0x1UL << 2) /**< Channel 2 Single Request Status */
<> 128:9bcdf88f62b0 1042 #define _DMA_CHSREQSTATUS_CH2SREQSTATUS_SHIFT 2 /**< Shift value for DMA_CH2SREQSTATUS */
<> 128:9bcdf88f62b0 1043 #define _DMA_CHSREQSTATUS_CH2SREQSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2SREQSTATUS */
<> 128:9bcdf88f62b0 1044 #define _DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
<> 128:9bcdf88f62b0 1045 #define DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
<> 128:9bcdf88f62b0 1046 #define DMA_CHSREQSTATUS_CH3SREQSTATUS (0x1UL << 3) /**< Channel 3 Single Request Status */
<> 128:9bcdf88f62b0 1047 #define _DMA_CHSREQSTATUS_CH3SREQSTATUS_SHIFT 3 /**< Shift value for DMA_CH3SREQSTATUS */
<> 128:9bcdf88f62b0 1048 #define _DMA_CHSREQSTATUS_CH3SREQSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3SREQSTATUS */
<> 128:9bcdf88f62b0 1049 #define _DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
<> 128:9bcdf88f62b0 1050 #define DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
<> 128:9bcdf88f62b0 1051 #define DMA_CHSREQSTATUS_CH4SREQSTATUS (0x1UL << 4) /**< Channel 4 Single Request Status */
<> 128:9bcdf88f62b0 1052 #define _DMA_CHSREQSTATUS_CH4SREQSTATUS_SHIFT 4 /**< Shift value for DMA_CH4SREQSTATUS */
<> 128:9bcdf88f62b0 1053 #define _DMA_CHSREQSTATUS_CH4SREQSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4SREQSTATUS */
<> 128:9bcdf88f62b0 1054 #define _DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
<> 128:9bcdf88f62b0 1055 #define DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
<> 128:9bcdf88f62b0 1056 #define DMA_CHSREQSTATUS_CH5SREQSTATUS (0x1UL << 5) /**< Channel 5 Single Request Status */
<> 128:9bcdf88f62b0 1057 #define _DMA_CHSREQSTATUS_CH5SREQSTATUS_SHIFT 5 /**< Shift value for DMA_CH5SREQSTATUS */
<> 128:9bcdf88f62b0 1058 #define _DMA_CHSREQSTATUS_CH5SREQSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5SREQSTATUS */
<> 128:9bcdf88f62b0 1059 #define _DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
<> 128:9bcdf88f62b0 1060 #define DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
<> 128:9bcdf88f62b0 1061
<> 128:9bcdf88f62b0 1062 /* Bit fields for DMA IF */
<> 128:9bcdf88f62b0 1063 #define _DMA_IF_RESETVALUE 0x00000000UL /**< Default value for DMA_IF */
<> 128:9bcdf88f62b0 1064 #define _DMA_IF_MASK 0x8000003FUL /**< Mask for DMA_IF */
<> 128:9bcdf88f62b0 1065 #define DMA_IF_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag */
<> 128:9bcdf88f62b0 1066 #define _DMA_IF_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */
<> 128:9bcdf88f62b0 1067 #define _DMA_IF_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */
<> 128:9bcdf88f62b0 1068 #define _DMA_IF_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
<> 128:9bcdf88f62b0 1069 #define DMA_IF_CH0DONE_DEFAULT (_DMA_IF_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IF */
<> 128:9bcdf88f62b0 1070 #define DMA_IF_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag */
<> 128:9bcdf88f62b0 1071 #define _DMA_IF_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */
<> 128:9bcdf88f62b0 1072 #define _DMA_IF_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */
<> 128:9bcdf88f62b0 1073 #define _DMA_IF_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
<> 128:9bcdf88f62b0 1074 #define DMA_IF_CH1DONE_DEFAULT (_DMA_IF_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IF */
<> 128:9bcdf88f62b0 1075 #define DMA_IF_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag */
<> 128:9bcdf88f62b0 1076 #define _DMA_IF_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */
<> 128:9bcdf88f62b0 1077 #define _DMA_IF_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */
<> 128:9bcdf88f62b0 1078 #define _DMA_IF_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
<> 128:9bcdf88f62b0 1079 #define DMA_IF_CH2DONE_DEFAULT (_DMA_IF_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IF */
<> 128:9bcdf88f62b0 1080 #define DMA_IF_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag */
<> 128:9bcdf88f62b0 1081 #define _DMA_IF_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */
<> 128:9bcdf88f62b0 1082 #define _DMA_IF_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */
<> 128:9bcdf88f62b0 1083 #define _DMA_IF_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
<> 128:9bcdf88f62b0 1084 #define DMA_IF_CH3DONE_DEFAULT (_DMA_IF_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IF */
<> 128:9bcdf88f62b0 1085 #define DMA_IF_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag */
<> 128:9bcdf88f62b0 1086 #define _DMA_IF_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */
<> 128:9bcdf88f62b0 1087 #define _DMA_IF_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */
<> 128:9bcdf88f62b0 1088 #define _DMA_IF_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
<> 128:9bcdf88f62b0 1089 #define DMA_IF_CH4DONE_DEFAULT (_DMA_IF_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IF */
<> 128:9bcdf88f62b0 1090 #define DMA_IF_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag */
<> 128:9bcdf88f62b0 1091 #define _DMA_IF_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */
<> 128:9bcdf88f62b0 1092 #define _DMA_IF_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */
<> 128:9bcdf88f62b0 1093 #define _DMA_IF_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
<> 128:9bcdf88f62b0 1094 #define DMA_IF_CH5DONE_DEFAULT (_DMA_IF_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IF */
<> 128:9bcdf88f62b0 1095 #define DMA_IF_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag */
<> 128:9bcdf88f62b0 1096 #define _DMA_IF_ERR_SHIFT 31 /**< Shift value for DMA_ERR */
<> 128:9bcdf88f62b0 1097 #define _DMA_IF_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */
<> 128:9bcdf88f62b0 1098 #define _DMA_IF_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
<> 128:9bcdf88f62b0 1099 #define DMA_IF_ERR_DEFAULT (_DMA_IF_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IF */
<> 128:9bcdf88f62b0 1100
<> 128:9bcdf88f62b0 1101 /* Bit fields for DMA IFS */
<> 128:9bcdf88f62b0 1102 #define _DMA_IFS_RESETVALUE 0x00000000UL /**< Default value for DMA_IFS */
<> 128:9bcdf88f62b0 1103 #define _DMA_IFS_MASK 0x8000003FUL /**< Mask for DMA_IFS */
<> 128:9bcdf88f62b0 1104 #define DMA_IFS_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag Set */
<> 128:9bcdf88f62b0 1105 #define _DMA_IFS_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */
<> 128:9bcdf88f62b0 1106 #define _DMA_IFS_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */
<> 128:9bcdf88f62b0 1107 #define _DMA_IFS_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
<> 128:9bcdf88f62b0 1108 #define DMA_IFS_CH0DONE_DEFAULT (_DMA_IFS_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IFS */
<> 128:9bcdf88f62b0 1109 #define DMA_IFS_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag Set */
<> 128:9bcdf88f62b0 1110 #define _DMA_IFS_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */
<> 128:9bcdf88f62b0 1111 #define _DMA_IFS_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */
<> 128:9bcdf88f62b0 1112 #define _DMA_IFS_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
<> 128:9bcdf88f62b0 1113 #define DMA_IFS_CH1DONE_DEFAULT (_DMA_IFS_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IFS */
<> 128:9bcdf88f62b0 1114 #define DMA_IFS_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag Set */
<> 128:9bcdf88f62b0 1115 #define _DMA_IFS_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */
<> 128:9bcdf88f62b0 1116 #define _DMA_IFS_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */
<> 128:9bcdf88f62b0 1117 #define _DMA_IFS_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
<> 128:9bcdf88f62b0 1118 #define DMA_IFS_CH2DONE_DEFAULT (_DMA_IFS_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IFS */
<> 128:9bcdf88f62b0 1119 #define DMA_IFS_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag Set */
<> 128:9bcdf88f62b0 1120 #define _DMA_IFS_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */
<> 128:9bcdf88f62b0 1121 #define _DMA_IFS_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */
<> 128:9bcdf88f62b0 1122 #define _DMA_IFS_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
<> 128:9bcdf88f62b0 1123 #define DMA_IFS_CH3DONE_DEFAULT (_DMA_IFS_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IFS */
<> 128:9bcdf88f62b0 1124 #define DMA_IFS_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag Set */
<> 128:9bcdf88f62b0 1125 #define _DMA_IFS_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */
<> 128:9bcdf88f62b0 1126 #define _DMA_IFS_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */
<> 128:9bcdf88f62b0 1127 #define _DMA_IFS_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
<> 128:9bcdf88f62b0 1128 #define DMA_IFS_CH4DONE_DEFAULT (_DMA_IFS_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IFS */
<> 128:9bcdf88f62b0 1129 #define DMA_IFS_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag Set */
<> 128:9bcdf88f62b0 1130 #define _DMA_IFS_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */
<> 128:9bcdf88f62b0 1131 #define _DMA_IFS_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */
<> 128:9bcdf88f62b0 1132 #define _DMA_IFS_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
<> 128:9bcdf88f62b0 1133 #define DMA_IFS_CH5DONE_DEFAULT (_DMA_IFS_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IFS */
<> 128:9bcdf88f62b0 1134 #define DMA_IFS_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Set */
<> 128:9bcdf88f62b0 1135 #define _DMA_IFS_ERR_SHIFT 31 /**< Shift value for DMA_ERR */
<> 128:9bcdf88f62b0 1136 #define _DMA_IFS_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */
<> 128:9bcdf88f62b0 1137 #define _DMA_IFS_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
<> 128:9bcdf88f62b0 1138 #define DMA_IFS_ERR_DEFAULT (_DMA_IFS_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IFS */
<> 128:9bcdf88f62b0 1139
<> 128:9bcdf88f62b0 1140 /* Bit fields for DMA IFC */
<> 128:9bcdf88f62b0 1141 #define _DMA_IFC_RESETVALUE 0x00000000UL /**< Default value for DMA_IFC */
<> 128:9bcdf88f62b0 1142 #define _DMA_IFC_MASK 0x8000003FUL /**< Mask for DMA_IFC */
<> 128:9bcdf88f62b0 1143 #define DMA_IFC_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag Clear */
<> 128:9bcdf88f62b0 1144 #define _DMA_IFC_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */
<> 128:9bcdf88f62b0 1145 #define _DMA_IFC_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */
<> 128:9bcdf88f62b0 1146 #define _DMA_IFC_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
<> 128:9bcdf88f62b0 1147 #define DMA_IFC_CH0DONE_DEFAULT (_DMA_IFC_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IFC */
<> 128:9bcdf88f62b0 1148 #define DMA_IFC_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag Clear */
<> 128:9bcdf88f62b0 1149 #define _DMA_IFC_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */
<> 128:9bcdf88f62b0 1150 #define _DMA_IFC_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */
<> 128:9bcdf88f62b0 1151 #define _DMA_IFC_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
<> 128:9bcdf88f62b0 1152 #define DMA_IFC_CH1DONE_DEFAULT (_DMA_IFC_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IFC */
<> 128:9bcdf88f62b0 1153 #define DMA_IFC_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag Clear */
<> 128:9bcdf88f62b0 1154 #define _DMA_IFC_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */
<> 128:9bcdf88f62b0 1155 #define _DMA_IFC_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */
<> 128:9bcdf88f62b0 1156 #define _DMA_IFC_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
<> 128:9bcdf88f62b0 1157 #define DMA_IFC_CH2DONE_DEFAULT (_DMA_IFC_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IFC */
<> 128:9bcdf88f62b0 1158 #define DMA_IFC_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag Clear */
<> 128:9bcdf88f62b0 1159 #define _DMA_IFC_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */
<> 128:9bcdf88f62b0 1160 #define _DMA_IFC_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */
<> 128:9bcdf88f62b0 1161 #define _DMA_IFC_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
<> 128:9bcdf88f62b0 1162 #define DMA_IFC_CH3DONE_DEFAULT (_DMA_IFC_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IFC */
<> 128:9bcdf88f62b0 1163 #define DMA_IFC_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag Clear */
<> 128:9bcdf88f62b0 1164 #define _DMA_IFC_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */
<> 128:9bcdf88f62b0 1165 #define _DMA_IFC_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */
<> 128:9bcdf88f62b0 1166 #define _DMA_IFC_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
<> 128:9bcdf88f62b0 1167 #define DMA_IFC_CH4DONE_DEFAULT (_DMA_IFC_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IFC */
<> 128:9bcdf88f62b0 1168 #define DMA_IFC_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag Clear */
<> 128:9bcdf88f62b0 1169 #define _DMA_IFC_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */
<> 128:9bcdf88f62b0 1170 #define _DMA_IFC_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */
<> 128:9bcdf88f62b0 1171 #define _DMA_IFC_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
<> 128:9bcdf88f62b0 1172 #define DMA_IFC_CH5DONE_DEFAULT (_DMA_IFC_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IFC */
<> 128:9bcdf88f62b0 1173 #define DMA_IFC_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Clear */
<> 128:9bcdf88f62b0 1174 #define _DMA_IFC_ERR_SHIFT 31 /**< Shift value for DMA_ERR */
<> 128:9bcdf88f62b0 1175 #define _DMA_IFC_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */
<> 128:9bcdf88f62b0 1176 #define _DMA_IFC_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
<> 128:9bcdf88f62b0 1177 #define DMA_IFC_ERR_DEFAULT (_DMA_IFC_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IFC */
<> 128:9bcdf88f62b0 1178
<> 128:9bcdf88f62b0 1179 /* Bit fields for DMA IEN */
<> 128:9bcdf88f62b0 1180 #define _DMA_IEN_RESETVALUE 0x00000000UL /**< Default value for DMA_IEN */
<> 128:9bcdf88f62b0 1181 #define _DMA_IEN_MASK 0x8000003FUL /**< Mask for DMA_IEN */
<> 128:9bcdf88f62b0 1182 #define DMA_IEN_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Enable */
<> 128:9bcdf88f62b0 1183 #define _DMA_IEN_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */
<> 128:9bcdf88f62b0 1184 #define _DMA_IEN_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */
<> 128:9bcdf88f62b0 1185 #define _DMA_IEN_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
<> 128:9bcdf88f62b0 1186 #define DMA_IEN_CH0DONE_DEFAULT (_DMA_IEN_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IEN */
<> 128:9bcdf88f62b0 1187 #define DMA_IEN_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Enable */
<> 128:9bcdf88f62b0 1188 #define _DMA_IEN_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */
<> 128:9bcdf88f62b0 1189 #define _DMA_IEN_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */
<> 128:9bcdf88f62b0 1190 #define _DMA_IEN_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
<> 128:9bcdf88f62b0 1191 #define DMA_IEN_CH1DONE_DEFAULT (_DMA_IEN_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IEN */
<> 128:9bcdf88f62b0 1192 #define DMA_IEN_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Enable */
<> 128:9bcdf88f62b0 1193 #define _DMA_IEN_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */
<> 128:9bcdf88f62b0 1194 #define _DMA_IEN_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */
<> 128:9bcdf88f62b0 1195 #define _DMA_IEN_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
<> 128:9bcdf88f62b0 1196 #define DMA_IEN_CH2DONE_DEFAULT (_DMA_IEN_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IEN */
<> 128:9bcdf88f62b0 1197 #define DMA_IEN_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Enable */
<> 128:9bcdf88f62b0 1198 #define _DMA_IEN_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */
<> 128:9bcdf88f62b0 1199 #define _DMA_IEN_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */
<> 128:9bcdf88f62b0 1200 #define _DMA_IEN_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
<> 128:9bcdf88f62b0 1201 #define DMA_IEN_CH3DONE_DEFAULT (_DMA_IEN_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IEN */
<> 128:9bcdf88f62b0 1202 #define DMA_IEN_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Enable */
<> 128:9bcdf88f62b0 1203 #define _DMA_IEN_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */
<> 128:9bcdf88f62b0 1204 #define _DMA_IEN_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */
<> 128:9bcdf88f62b0 1205 #define _DMA_IEN_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
<> 128:9bcdf88f62b0 1206 #define DMA_IEN_CH4DONE_DEFAULT (_DMA_IEN_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IEN */
<> 128:9bcdf88f62b0 1207 #define DMA_IEN_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Enable */
<> 128:9bcdf88f62b0 1208 #define _DMA_IEN_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */
<> 128:9bcdf88f62b0 1209 #define _DMA_IEN_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */
<> 128:9bcdf88f62b0 1210 #define _DMA_IEN_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
<> 128:9bcdf88f62b0 1211 #define DMA_IEN_CH5DONE_DEFAULT (_DMA_IEN_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IEN */
<> 128:9bcdf88f62b0 1212 #define DMA_IEN_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Enable */
<> 128:9bcdf88f62b0 1213 #define _DMA_IEN_ERR_SHIFT 31 /**< Shift value for DMA_ERR */
<> 128:9bcdf88f62b0 1214 #define _DMA_IEN_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */
<> 128:9bcdf88f62b0 1215 #define _DMA_IEN_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
<> 128:9bcdf88f62b0 1216 #define DMA_IEN_ERR_DEFAULT (_DMA_IEN_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IEN */
<> 128:9bcdf88f62b0 1217
<> 128:9bcdf88f62b0 1218 /* Bit fields for DMA CH_CTRL */
<> 128:9bcdf88f62b0 1219 #define _DMA_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1220 #define _DMA_CH_CTRL_MASK 0x003F000FUL /**< Mask for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1221 #define _DMA_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for DMA_SIGSEL */
<> 128:9bcdf88f62b0 1222 #define _DMA_CH_CTRL_SIGSEL_MASK 0xFUL /**< Bit mask for DMA_SIGSEL */
<> 128:9bcdf88f62b0 1223 #define _DMA_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000000UL /**< Mode USART0RXDATAV for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1224 #define _DMA_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000000UL /**< Mode USART1RXDATAV for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1225 #define _DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV 0x00000000UL /**< Mode LEUART0RXDATAV for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1226 #define _DMA_CH_CTRL_SIGSEL_I2C0RXDATAV 0x00000000UL /**< Mode I2C0RXDATAV for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1227 #define _DMA_CH_CTRL_SIGSEL_TIMER0UFOF 0x00000000UL /**< Mode TIMER0UFOF for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1228 #define _DMA_CH_CTRL_SIGSEL_TIMER1UFOF 0x00000000UL /**< Mode TIMER1UFOF for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1229 #define _DMA_CH_CTRL_SIGSEL_TIMER2UFOF 0x00000000UL /**< Mode TIMER2UFOF for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1230 #define _DMA_CH_CTRL_SIGSEL_MSCWDATA 0x00000000UL /**< Mode MSCWDATA for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1231 #define _DMA_CH_CTRL_SIGSEL_USART0TXBL 0x00000001UL /**< Mode USART0TXBL for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1232 #define _DMA_CH_CTRL_SIGSEL_USART1TXBL 0x00000001UL /**< Mode USART1TXBL for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1233 #define _DMA_CH_CTRL_SIGSEL_LEUART0TXBL 0x00000001UL /**< Mode LEUART0TXBL for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1234 #define _DMA_CH_CTRL_SIGSEL_I2C0TXBL 0x00000001UL /**< Mode I2C0TXBL for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1235 #define _DMA_CH_CTRL_SIGSEL_TIMER0CC0 0x00000001UL /**< Mode TIMER0CC0 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1236 #define _DMA_CH_CTRL_SIGSEL_TIMER1CC0 0x00000001UL /**< Mode TIMER1CC0 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1237 #define _DMA_CH_CTRL_SIGSEL_TIMER2CC0 0x00000001UL /**< Mode TIMER2CC0 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1238 #define _DMA_CH_CTRL_SIGSEL_USART0TXEMPTY 0x00000002UL /**< Mode USART0TXEMPTY for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1239 #define _DMA_CH_CTRL_SIGSEL_USART1TXEMPTY 0x00000002UL /**< Mode USART1TXEMPTY for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1240 #define _DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY 0x00000002UL /**< Mode LEUART0TXEMPTY for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1241 #define _DMA_CH_CTRL_SIGSEL_TIMER0CC1 0x00000002UL /**< Mode TIMER0CC1 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1242 #define _DMA_CH_CTRL_SIGSEL_TIMER1CC1 0x00000002UL /**< Mode TIMER1CC1 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1243 #define _DMA_CH_CTRL_SIGSEL_TIMER2CC1 0x00000002UL /**< Mode TIMER2CC1 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1244 #define _DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT 0x00000003UL /**< Mode USART1RXDATAVRIGHT for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1245 #define _DMA_CH_CTRL_SIGSEL_TIMER0CC2 0x00000003UL /**< Mode TIMER0CC2 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1246 #define _DMA_CH_CTRL_SIGSEL_TIMER1CC2 0x00000003UL /**< Mode TIMER1CC2 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1247 #define _DMA_CH_CTRL_SIGSEL_TIMER2CC2 0x00000003UL /**< Mode TIMER2CC2 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1248 #define _DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT 0x00000004UL /**< Mode USART1TXBLRIGHT for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1249 #define DMA_CH_CTRL_SIGSEL_USART0RXDATAV (_DMA_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1250 #define DMA_CH_CTRL_SIGSEL_USART1RXDATAV (_DMA_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1251 #define DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV (_DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV << 0) /**< Shifted mode LEUART0RXDATAV for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1252 #define DMA_CH_CTRL_SIGSEL_I2C0RXDATAV (_DMA_CH_CTRL_SIGSEL_I2C0RXDATAV << 0) /**< Shifted mode I2C0RXDATAV for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1253 #define DMA_CH_CTRL_SIGSEL_TIMER0UFOF (_DMA_CH_CTRL_SIGSEL_TIMER0UFOF << 0) /**< Shifted mode TIMER0UFOF for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1254 #define DMA_CH_CTRL_SIGSEL_TIMER1UFOF (_DMA_CH_CTRL_SIGSEL_TIMER1UFOF << 0) /**< Shifted mode TIMER1UFOF for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1255 #define DMA_CH_CTRL_SIGSEL_TIMER2UFOF (_DMA_CH_CTRL_SIGSEL_TIMER2UFOF << 0) /**< Shifted mode TIMER2UFOF for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1256 #define DMA_CH_CTRL_SIGSEL_MSCWDATA (_DMA_CH_CTRL_SIGSEL_MSCWDATA << 0) /**< Shifted mode MSCWDATA for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1257 #define DMA_CH_CTRL_SIGSEL_USART0TXBL (_DMA_CH_CTRL_SIGSEL_USART0TXBL << 0) /**< Shifted mode USART0TXBL for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1258 #define DMA_CH_CTRL_SIGSEL_USART1TXBL (_DMA_CH_CTRL_SIGSEL_USART1TXBL << 0) /**< Shifted mode USART1TXBL for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1259 #define DMA_CH_CTRL_SIGSEL_LEUART0TXBL (_DMA_CH_CTRL_SIGSEL_LEUART0TXBL << 0) /**< Shifted mode LEUART0TXBL for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1260 #define DMA_CH_CTRL_SIGSEL_I2C0TXBL (_DMA_CH_CTRL_SIGSEL_I2C0TXBL << 0) /**< Shifted mode I2C0TXBL for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1261 #define DMA_CH_CTRL_SIGSEL_TIMER0CC0 (_DMA_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1262 #define DMA_CH_CTRL_SIGSEL_TIMER1CC0 (_DMA_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1263 #define DMA_CH_CTRL_SIGSEL_TIMER2CC0 (_DMA_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1264 #define DMA_CH_CTRL_SIGSEL_USART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART0TXEMPTY << 0) /**< Shifted mode USART0TXEMPTY for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1265 #define DMA_CH_CTRL_SIGSEL_USART1TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART1TXEMPTY << 0) /**< Shifted mode USART1TXEMPTY for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1266 #define DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY << 0) /**< Shifted mode LEUART0TXEMPTY for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1267 #define DMA_CH_CTRL_SIGSEL_TIMER0CC1 (_DMA_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1268 #define DMA_CH_CTRL_SIGSEL_TIMER1CC1 (_DMA_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1269 #define DMA_CH_CTRL_SIGSEL_TIMER2CC1 (_DMA_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1270 #define DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT (_DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT << 0) /**< Shifted mode USART1RXDATAVRIGHT for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1271 #define DMA_CH_CTRL_SIGSEL_TIMER0CC2 (_DMA_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1272 #define DMA_CH_CTRL_SIGSEL_TIMER1CC2 (_DMA_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1273 #define DMA_CH_CTRL_SIGSEL_TIMER2CC2 (_DMA_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1274 #define DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT (_DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT << 0) /**< Shifted mode USART1TXBLRIGHT for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1275 #define _DMA_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for DMA_SOURCESEL */
<> 128:9bcdf88f62b0 1276 #define _DMA_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for DMA_SOURCESEL */
<> 128:9bcdf88f62b0 1277 #define _DMA_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1278 #define _DMA_CH_CTRL_SOURCESEL_USART0 0x0000000CUL /**< Mode USART0 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1279 #define _DMA_CH_CTRL_SOURCESEL_USART1 0x0000000DUL /**< Mode USART1 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1280 #define _DMA_CH_CTRL_SOURCESEL_LEUART0 0x00000010UL /**< Mode LEUART0 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1281 #define _DMA_CH_CTRL_SOURCESEL_I2C0 0x00000014UL /**< Mode I2C0 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1282 #define _DMA_CH_CTRL_SOURCESEL_TIMER0 0x00000018UL /**< Mode TIMER0 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1283 #define _DMA_CH_CTRL_SOURCESEL_TIMER1 0x00000019UL /**< Mode TIMER1 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1284 #define _DMA_CH_CTRL_SOURCESEL_TIMER2 0x0000001AUL /**< Mode TIMER2 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1285 #define _DMA_CH_CTRL_SOURCESEL_MSC 0x00000030UL /**< Mode MSC for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1286 #define DMA_CH_CTRL_SOURCESEL_NONE (_DMA_CH_CTRL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1287 #define DMA_CH_CTRL_SOURCESEL_USART0 (_DMA_CH_CTRL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1288 #define DMA_CH_CTRL_SOURCESEL_USART1 (_DMA_CH_CTRL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1289 #define DMA_CH_CTRL_SOURCESEL_LEUART0 (_DMA_CH_CTRL_SOURCESEL_LEUART0 << 16) /**< Shifted mode LEUART0 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1290 #define DMA_CH_CTRL_SOURCESEL_I2C0 (_DMA_CH_CTRL_SOURCESEL_I2C0 << 16) /**< Shifted mode I2C0 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1291 #define DMA_CH_CTRL_SOURCESEL_TIMER0 (_DMA_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1292 #define DMA_CH_CTRL_SOURCESEL_TIMER1 (_DMA_CH_CTRL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1293 #define DMA_CH_CTRL_SOURCESEL_TIMER2 (_DMA_CH_CTRL_SOURCESEL_TIMER2 << 16) /**< Shifted mode TIMER2 for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1294 #define DMA_CH_CTRL_SOURCESEL_MSC (_DMA_CH_CTRL_SOURCESEL_MSC << 16) /**< Shifted mode MSC for DMA_CH_CTRL */
<> 128:9bcdf88f62b0 1295
<> 128:9bcdf88f62b0 1296 /** @} End of group EFM32HG308F64_DMA */
<> 128:9bcdf88f62b0 1297
<> 128:9bcdf88f62b0 1298
<> 128:9bcdf88f62b0 1299
<> 128:9bcdf88f62b0 1300 /**************************************************************************//**
<> 128:9bcdf88f62b0 1301 * @defgroup EFM32HG308F64_CMU_BitFields EFM32HG308F64_CMU Bit Fields
<> 128:9bcdf88f62b0 1302 * @{
<> 128:9bcdf88f62b0 1303 *****************************************************************************/
<> 128:9bcdf88f62b0 1304
<> 128:9bcdf88f62b0 1305 /* Bit fields for CMU CTRL */
<> 128:9bcdf88f62b0 1306 #define _CMU_CTRL_RESETVALUE 0x000C262CUL /**< Default value for CMU_CTRL */
<> 128:9bcdf88f62b0 1307 #define _CMU_CTRL_MASK 0x07FFFEEFUL /**< Mask for CMU_CTRL */
<> 128:9bcdf88f62b0 1308 #define _CMU_CTRL_HFXOMODE_SHIFT 0 /**< Shift value for CMU_HFXOMODE */
<> 128:9bcdf88f62b0 1309 #define _CMU_CTRL_HFXOMODE_MASK 0x3UL /**< Bit mask for CMU_HFXOMODE */
<> 128:9bcdf88f62b0 1310 #define _CMU_CTRL_HFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
<> 128:9bcdf88f62b0 1311 #define _CMU_CTRL_HFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */
<> 128:9bcdf88f62b0 1312 #define _CMU_CTRL_HFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */
<> 128:9bcdf88f62b0 1313 #define _CMU_CTRL_HFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */
<> 128:9bcdf88f62b0 1314 #define CMU_CTRL_HFXOMODE_DEFAULT (_CMU_CTRL_HFXOMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */
<> 128:9bcdf88f62b0 1315 #define CMU_CTRL_HFXOMODE_XTAL (_CMU_CTRL_HFXOMODE_XTAL << 0) /**< Shifted mode XTAL for CMU_CTRL */
<> 128:9bcdf88f62b0 1316 #define CMU_CTRL_HFXOMODE_BUFEXTCLK (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0) /**< Shifted mode BUFEXTCLK for CMU_CTRL */
<> 128:9bcdf88f62b0 1317 #define CMU_CTRL_HFXOMODE_DIGEXTCLK (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_CTRL */
<> 128:9bcdf88f62b0 1318 #define _CMU_CTRL_HFXOBOOST_SHIFT 2 /**< Shift value for CMU_HFXOBOOST */
<> 128:9bcdf88f62b0 1319 #define _CMU_CTRL_HFXOBOOST_MASK 0xCUL /**< Bit mask for CMU_HFXOBOOST */
<> 128:9bcdf88f62b0 1320 #define _CMU_CTRL_HFXOBOOST_50PCENT 0x00000000UL /**< Mode 50PCENT for CMU_CTRL */
<> 128:9bcdf88f62b0 1321 #define _CMU_CTRL_HFXOBOOST_70PCENT 0x00000001UL /**< Mode 70PCENT for CMU_CTRL */
<> 128:9bcdf88f62b0 1322 #define _CMU_CTRL_HFXOBOOST_80PCENT 0x00000002UL /**< Mode 80PCENT for CMU_CTRL */
<> 128:9bcdf88f62b0 1323 #define _CMU_CTRL_HFXOBOOST_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */
<> 128:9bcdf88f62b0 1324 #define _CMU_CTRL_HFXOBOOST_100PCENT 0x00000003UL /**< Mode 100PCENT for CMU_CTRL */
<> 128:9bcdf88f62b0 1325 #define CMU_CTRL_HFXOBOOST_50PCENT (_CMU_CTRL_HFXOBOOST_50PCENT << 2) /**< Shifted mode 50PCENT for CMU_CTRL */
<> 128:9bcdf88f62b0 1326 #define CMU_CTRL_HFXOBOOST_70PCENT (_CMU_CTRL_HFXOBOOST_70PCENT << 2) /**< Shifted mode 70PCENT for CMU_CTRL */
<> 128:9bcdf88f62b0 1327 #define CMU_CTRL_HFXOBOOST_80PCENT (_CMU_CTRL_HFXOBOOST_80PCENT << 2) /**< Shifted mode 80PCENT for CMU_CTRL */
<> 128:9bcdf88f62b0 1328 #define CMU_CTRL_HFXOBOOST_DEFAULT (_CMU_CTRL_HFXOBOOST_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CTRL */
<> 128:9bcdf88f62b0 1329 #define CMU_CTRL_HFXOBOOST_100PCENT (_CMU_CTRL_HFXOBOOST_100PCENT << 2) /**< Shifted mode 100PCENT for CMU_CTRL */
<> 128:9bcdf88f62b0 1330 #define _CMU_CTRL_HFXOBUFCUR_SHIFT 5 /**< Shift value for CMU_HFXOBUFCUR */
<> 128:9bcdf88f62b0 1331 #define _CMU_CTRL_HFXOBUFCUR_MASK 0x60UL /**< Bit mask for CMU_HFXOBUFCUR */
<> 128:9bcdf88f62b0 1332 #define _CMU_CTRL_HFXOBUFCUR_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */
<> 128:9bcdf88f62b0 1333 #define CMU_CTRL_HFXOBUFCUR_DEFAULT (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */
<> 128:9bcdf88f62b0 1334 #define CMU_CTRL_HFXOGLITCHDETEN (0x1UL << 7) /**< HFXO Glitch Detector Enable */
<> 128:9bcdf88f62b0 1335 #define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT 7 /**< Shift value for CMU_HFXOGLITCHDETEN */
<> 128:9bcdf88f62b0 1336 #define _CMU_CTRL_HFXOGLITCHDETEN_MASK 0x80UL /**< Bit mask for CMU_HFXOGLITCHDETEN */
<> 128:9bcdf88f62b0 1337 #define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
<> 128:9bcdf88f62b0 1338 #define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CTRL */
<> 128:9bcdf88f62b0 1339 #define _CMU_CTRL_HFXOTIMEOUT_SHIFT 9 /**< Shift value for CMU_HFXOTIMEOUT */
<> 128:9bcdf88f62b0 1340 #define _CMU_CTRL_HFXOTIMEOUT_MASK 0x600UL /**< Bit mask for CMU_HFXOTIMEOUT */
<> 128:9bcdf88f62b0 1341 #define _CMU_CTRL_HFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */
<> 128:9bcdf88f62b0 1342 #define _CMU_CTRL_HFXOTIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_CTRL */
<> 128:9bcdf88f62b0 1343 #define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_CTRL */
<> 128:9bcdf88f62b0 1344 #define _CMU_CTRL_HFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */
<> 128:9bcdf88f62b0 1345 #define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES 0x00000003UL /**< Mode 16KCYCLES for CMU_CTRL */
<> 128:9bcdf88f62b0 1346 #define CMU_CTRL_HFXOTIMEOUT_8CYCLES (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9) /**< Shifted mode 8CYCLES for CMU_CTRL */
<> 128:9bcdf88f62b0 1347 #define CMU_CTRL_HFXOTIMEOUT_256CYCLES (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9) /**< Shifted mode 256CYCLES for CMU_CTRL */
<> 128:9bcdf88f62b0 1348 #define CMU_CTRL_HFXOTIMEOUT_1KCYCLES (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9) /**< Shifted mode 1KCYCLES for CMU_CTRL */
<> 128:9bcdf88f62b0 1349 #define CMU_CTRL_HFXOTIMEOUT_DEFAULT (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CTRL */
<> 128:9bcdf88f62b0 1350 #define CMU_CTRL_HFXOTIMEOUT_16KCYCLES (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9) /**< Shifted mode 16KCYCLES for CMU_CTRL */
<> 128:9bcdf88f62b0 1351 #define _CMU_CTRL_LFXOMODE_SHIFT 11 /**< Shift value for CMU_LFXOMODE */
<> 128:9bcdf88f62b0 1352 #define _CMU_CTRL_LFXOMODE_MASK 0x1800UL /**< Bit mask for CMU_LFXOMODE */
<> 128:9bcdf88f62b0 1353 #define _CMU_CTRL_LFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
<> 128:9bcdf88f62b0 1354 #define _CMU_CTRL_LFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */
<> 128:9bcdf88f62b0 1355 #define _CMU_CTRL_LFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */
<> 128:9bcdf88f62b0 1356 #define _CMU_CTRL_LFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */
<> 128:9bcdf88f62b0 1357 #define CMU_CTRL_LFXOMODE_DEFAULT (_CMU_CTRL_LFXOMODE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CTRL */
<> 128:9bcdf88f62b0 1358 #define CMU_CTRL_LFXOMODE_XTAL (_CMU_CTRL_LFXOMODE_XTAL << 11) /**< Shifted mode XTAL for CMU_CTRL */
<> 128:9bcdf88f62b0 1359 #define CMU_CTRL_LFXOMODE_BUFEXTCLK (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11) /**< Shifted mode BUFEXTCLK for CMU_CTRL */
<> 128:9bcdf88f62b0 1360 #define CMU_CTRL_LFXOMODE_DIGEXTCLK (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11) /**< Shifted mode DIGEXTCLK for CMU_CTRL */
<> 128:9bcdf88f62b0 1361 #define CMU_CTRL_LFXOBOOST (0x1UL << 13) /**< LFXO Start-up Boost Current */
<> 128:9bcdf88f62b0 1362 #define _CMU_CTRL_LFXOBOOST_SHIFT 13 /**< Shift value for CMU_LFXOBOOST */
<> 128:9bcdf88f62b0 1363 #define _CMU_CTRL_LFXOBOOST_MASK 0x2000UL /**< Bit mask for CMU_LFXOBOOST */
<> 128:9bcdf88f62b0 1364 #define _CMU_CTRL_LFXOBOOST_70PCENT 0x00000000UL /**< Mode 70PCENT for CMU_CTRL */
<> 128:9bcdf88f62b0 1365 #define _CMU_CTRL_LFXOBOOST_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */
<> 128:9bcdf88f62b0 1366 #define _CMU_CTRL_LFXOBOOST_100PCENT 0x00000001UL /**< Mode 100PCENT for CMU_CTRL */
<> 128:9bcdf88f62b0 1367 #define CMU_CTRL_LFXOBOOST_70PCENT (_CMU_CTRL_LFXOBOOST_70PCENT << 13) /**< Shifted mode 70PCENT for CMU_CTRL */
<> 128:9bcdf88f62b0 1368 #define CMU_CTRL_LFXOBOOST_DEFAULT (_CMU_CTRL_LFXOBOOST_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CTRL */
<> 128:9bcdf88f62b0 1369 #define CMU_CTRL_LFXOBOOST_100PCENT (_CMU_CTRL_LFXOBOOST_100PCENT << 13) /**< Shifted mode 100PCENT for CMU_CTRL */
<> 128:9bcdf88f62b0 1370 #define _CMU_CTRL_HFCLKDIV_SHIFT 14 /**< Shift value for CMU_HFCLKDIV */
<> 128:9bcdf88f62b0 1371 #define _CMU_CTRL_HFCLKDIV_MASK 0x1C000UL /**< Bit mask for CMU_HFCLKDIV */
<> 128:9bcdf88f62b0 1372 #define _CMU_CTRL_HFCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
<> 128:9bcdf88f62b0 1373 #define CMU_CTRL_HFCLKDIV_DEFAULT (_CMU_CTRL_HFCLKDIV_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CTRL */
<> 128:9bcdf88f62b0 1374 #define CMU_CTRL_LFXOBUFCUR (0x1UL << 17) /**< LFXO Boost Buffer Current */
<> 128:9bcdf88f62b0 1375 #define _CMU_CTRL_LFXOBUFCUR_SHIFT 17 /**< Shift value for CMU_LFXOBUFCUR */
<> 128:9bcdf88f62b0 1376 #define _CMU_CTRL_LFXOBUFCUR_MASK 0x20000UL /**< Bit mask for CMU_LFXOBUFCUR */
<> 128:9bcdf88f62b0 1377 #define _CMU_CTRL_LFXOBUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
<> 128:9bcdf88f62b0 1378 #define CMU_CTRL_LFXOBUFCUR_DEFAULT (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CTRL */
<> 128:9bcdf88f62b0 1379 #define _CMU_CTRL_LFXOTIMEOUT_SHIFT 18 /**< Shift value for CMU_LFXOTIMEOUT */
<> 128:9bcdf88f62b0 1380 #define _CMU_CTRL_LFXOTIMEOUT_MASK 0xC0000UL /**< Bit mask for CMU_LFXOTIMEOUT */
<> 128:9bcdf88f62b0 1381 #define _CMU_CTRL_LFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */
<> 128:9bcdf88f62b0 1382 #define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES 0x00000001UL /**< Mode 1KCYCLES for CMU_CTRL */
<> 128:9bcdf88f62b0 1383 #define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES 0x00000002UL /**< Mode 16KCYCLES for CMU_CTRL */
<> 128:9bcdf88f62b0 1384 #define _CMU_CTRL_LFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */
<> 128:9bcdf88f62b0 1385 #define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES 0x00000003UL /**< Mode 32KCYCLES for CMU_CTRL */
<> 128:9bcdf88f62b0 1386 #define CMU_CTRL_LFXOTIMEOUT_8CYCLES (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18) /**< Shifted mode 8CYCLES for CMU_CTRL */
<> 128:9bcdf88f62b0 1387 #define CMU_CTRL_LFXOTIMEOUT_1KCYCLES (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18) /**< Shifted mode 1KCYCLES for CMU_CTRL */
<> 128:9bcdf88f62b0 1388 #define CMU_CTRL_LFXOTIMEOUT_16KCYCLES (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18) /**< Shifted mode 16KCYCLES for CMU_CTRL */
<> 128:9bcdf88f62b0 1389 #define CMU_CTRL_LFXOTIMEOUT_DEFAULT (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CTRL */
<> 128:9bcdf88f62b0 1390 #define CMU_CTRL_LFXOTIMEOUT_32KCYCLES (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18) /**< Shifted mode 32KCYCLES for CMU_CTRL */
<> 128:9bcdf88f62b0 1391 #define _CMU_CTRL_CLKOUTSEL0_SHIFT 20 /**< Shift value for CMU_CLKOUTSEL0 */
<> 128:9bcdf88f62b0 1392 #define _CMU_CTRL_CLKOUTSEL0_MASK 0x700000UL /**< Bit mask for CMU_CLKOUTSEL0 */
<> 128:9bcdf88f62b0 1393 #define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
<> 128:9bcdf88f62b0 1394 #define _CMU_CTRL_CLKOUTSEL0_HFRCO 0x00000000UL /**< Mode HFRCO for CMU_CTRL */
<> 128:9bcdf88f62b0 1395 #define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000001UL /**< Mode HFXO for CMU_CTRL */
<> 128:9bcdf88f62b0 1396 #define _CMU_CTRL_CLKOUTSEL0_HFCLK2 0x00000002UL /**< Mode HFCLK2 for CMU_CTRL */
<> 128:9bcdf88f62b0 1397 #define _CMU_CTRL_CLKOUTSEL0_HFCLK4 0x00000003UL /**< Mode HFCLK4 for CMU_CTRL */
<> 128:9bcdf88f62b0 1398 #define _CMU_CTRL_CLKOUTSEL0_HFCLK8 0x00000004UL /**< Mode HFCLK8 for CMU_CTRL */
<> 128:9bcdf88f62b0 1399 #define _CMU_CTRL_CLKOUTSEL0_HFCLK16 0x00000005UL /**< Mode HFCLK16 for CMU_CTRL */
<> 128:9bcdf88f62b0 1400 #define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000006UL /**< Mode ULFRCO for CMU_CTRL */
<> 128:9bcdf88f62b0 1401 #define _CMU_CTRL_CLKOUTSEL0_AUXHFRCO 0x00000007UL /**< Mode AUXHFRCO for CMU_CTRL */
<> 128:9bcdf88f62b0 1402 #define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */
<> 128:9bcdf88f62b0 1403 #define CMU_CTRL_CLKOUTSEL0_HFRCO (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20) /**< Shifted mode HFRCO for CMU_CTRL */
<> 128:9bcdf88f62b0 1404 #define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 20) /**< Shifted mode HFXO for CMU_CTRL */
<> 128:9bcdf88f62b0 1405 #define CMU_CTRL_CLKOUTSEL0_HFCLK2 (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20) /**< Shifted mode HFCLK2 for CMU_CTRL */
<> 128:9bcdf88f62b0 1406 #define CMU_CTRL_CLKOUTSEL0_HFCLK4 (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20) /**< Shifted mode HFCLK4 for CMU_CTRL */
<> 128:9bcdf88f62b0 1407 #define CMU_CTRL_CLKOUTSEL0_HFCLK8 (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20) /**< Shifted mode HFCLK8 for CMU_CTRL */
<> 128:9bcdf88f62b0 1408 #define CMU_CTRL_CLKOUTSEL0_HFCLK16 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20) /**< Shifted mode HFCLK16 for CMU_CTRL */
<> 128:9bcdf88f62b0 1409 #define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_CTRL */
<> 128:9bcdf88f62b0 1410 #define CMU_CTRL_CLKOUTSEL0_AUXHFRCO (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_CTRL */
<> 128:9bcdf88f62b0 1411 #define _CMU_CTRL_CLKOUTSEL1_SHIFT 23 /**< Shift value for CMU_CLKOUTSEL1 */
<> 128:9bcdf88f62b0 1412 #define _CMU_CTRL_CLKOUTSEL1_MASK 0x7800000UL /**< Bit mask for CMU_CLKOUTSEL1 */
<> 128:9bcdf88f62b0 1413 #define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
<> 128:9bcdf88f62b0 1414 #define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000000UL /**< Mode LFRCO for CMU_CTRL */
<> 128:9bcdf88f62b0 1415 #define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000001UL /**< Mode LFXO for CMU_CTRL */
<> 128:9bcdf88f62b0 1416 #define _CMU_CTRL_CLKOUTSEL1_HFCLK 0x00000002UL /**< Mode HFCLK for CMU_CTRL */
<> 128:9bcdf88f62b0 1417 #define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x00000003UL /**< Mode LFXOQ for CMU_CTRL */
<> 128:9bcdf88f62b0 1418 #define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x00000004UL /**< Mode HFXOQ for CMU_CTRL */
<> 128:9bcdf88f62b0 1419 #define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x00000005UL /**< Mode LFRCOQ for CMU_CTRL */
<> 128:9bcdf88f62b0 1420 #define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x00000006UL /**< Mode HFRCOQ for CMU_CTRL */
<> 128:9bcdf88f62b0 1421 #define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x00000007UL /**< Mode AUXHFRCOQ for CMU_CTRL */
<> 128:9bcdf88f62b0 1422 #define _CMU_CTRL_CLKOUTSEL1_USHFRCO 0x00000008UL /**< Mode USHFRCO for CMU_CTRL */
<> 128:9bcdf88f62b0 1423 #define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CTRL */
<> 128:9bcdf88f62b0 1424 #define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23) /**< Shifted mode LFRCO for CMU_CTRL */
<> 128:9bcdf88f62b0 1425 #define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 23) /**< Shifted mode LFXO for CMU_CTRL */
<> 128:9bcdf88f62b0 1426 #define CMU_CTRL_CLKOUTSEL1_HFCLK (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23) /**< Shifted mode HFCLK for CMU_CTRL */
<> 128:9bcdf88f62b0 1427 #define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23) /**< Shifted mode LFXOQ for CMU_CTRL */
<> 128:9bcdf88f62b0 1428 #define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23) /**< Shifted mode HFXOQ for CMU_CTRL */
<> 128:9bcdf88f62b0 1429 #define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23) /**< Shifted mode LFRCOQ for CMU_CTRL */
<> 128:9bcdf88f62b0 1430 #define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23) /**< Shifted mode HFRCOQ for CMU_CTRL */
<> 128:9bcdf88f62b0 1431 #define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */
<> 128:9bcdf88f62b0 1432 #define CMU_CTRL_CLKOUTSEL1_USHFRCO (_CMU_CTRL_CLKOUTSEL1_USHFRCO << 23) /**< Shifted mode USHFRCO for CMU_CTRL */
<> 128:9bcdf88f62b0 1433
<> 128:9bcdf88f62b0 1434 /* Bit fields for CMU HFCORECLKDIV */
<> 128:9bcdf88f62b0 1435 #define _CMU_HFCORECLKDIV_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKDIV */
<> 128:9bcdf88f62b0 1436 #define _CMU_HFCORECLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFCORECLKDIV */
<> 128:9bcdf88f62b0 1437 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT 0 /**< Shift value for CMU_HFCORECLKDIV */
<> 128:9bcdf88f62b0 1438 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFCORECLKDIV */
<> 128:9bcdf88f62b0 1439 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */
<> 128:9bcdf88f62b0 1440 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFCORECLKDIV */
<> 128:9bcdf88f62b0 1441 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFCORECLKDIV */
<> 128:9bcdf88f62b0 1442 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFCORECLKDIV */
<> 128:9bcdf88f62b0 1443 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFCORECLKDIV */
<> 128:9bcdf88f62b0 1444 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFCORECLKDIV */
<> 128:9bcdf88f62b0 1445 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFCORECLKDIV */
<> 128:9bcdf88f62b0 1446 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFCORECLKDIV */
<> 128:9bcdf88f62b0 1447 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFCORECLKDIV */
<> 128:9bcdf88f62b0 1448 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFCORECLKDIV */
<> 128:9bcdf88f62b0 1449 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFCORECLKDIV */
<> 128:9bcdf88f62b0 1450 #define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */
<> 128:9bcdf88f62b0 1451 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFCORECLKDIV */
<> 128:9bcdf88f62b0 1452 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFCORECLKDIV */
<> 128:9bcdf88f62b0 1453 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFCORECLKDIV */
<> 128:9bcdf88f62b0 1454 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFCORECLKDIV */
<> 128:9bcdf88f62b0 1455 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFCORECLKDIV */
<> 128:9bcdf88f62b0 1456 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFCORECLKDIV */
<> 128:9bcdf88f62b0 1457 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFCORECLKDIV */
<> 128:9bcdf88f62b0 1458 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFCORECLKDIV */
<> 128:9bcdf88f62b0 1459 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFCORECLKDIV */
<> 128:9bcdf88f62b0 1460 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFCORECLKDIV */
<> 128:9bcdf88f62b0 1461 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV (0x1UL << 8) /**< Additional Division Factor For HFCORECLKLE */
<> 128:9bcdf88f62b0 1462 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT 8 /**< Shift value for CMU_HFCORECLKLEDIV */
<> 128:9bcdf88f62b0 1463 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK 0x100UL /**< Bit mask for CMU_HFCORECLKLEDIV */
<> 128:9bcdf88f62b0 1464 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */
<> 128:9bcdf88f62b0 1465 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFCORECLKDIV */
<> 128:9bcdf88f62b0 1466 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFCORECLKDIV */
<> 128:9bcdf88f62b0 1467 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */
<> 128:9bcdf88f62b0 1468 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 << 8) /**< Shifted mode DIV2 for CMU_HFCORECLKDIV */
<> 128:9bcdf88f62b0 1469 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 << 8) /**< Shifted mode DIV4 for CMU_HFCORECLKDIV */
<> 128:9bcdf88f62b0 1470
<> 128:9bcdf88f62b0 1471 /* Bit fields for CMU HFPERCLKDIV */
<> 128:9bcdf88f62b0 1472 #define _CMU_HFPERCLKDIV_RESETVALUE 0x00000100UL /**< Default value for CMU_HFPERCLKDIV */
<> 128:9bcdf88f62b0 1473 #define _CMU_HFPERCLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFPERCLKDIV */
<> 128:9bcdf88f62b0 1474 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT 0 /**< Shift value for CMU_HFPERCLKDIV */
<> 128:9bcdf88f62b0 1475 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFPERCLKDIV */
<> 128:9bcdf88f62b0 1476 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */
<> 128:9bcdf88f62b0 1477 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFPERCLKDIV */
<> 128:9bcdf88f62b0 1478 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFPERCLKDIV */
<> 128:9bcdf88f62b0 1479 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFPERCLKDIV */
<> 128:9bcdf88f62b0 1480 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFPERCLKDIV */
<> 128:9bcdf88f62b0 1481 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFPERCLKDIV */
<> 128:9bcdf88f62b0 1482 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFPERCLKDIV */
<> 128:9bcdf88f62b0 1483 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFPERCLKDIV */
<> 128:9bcdf88f62b0 1484 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFPERCLKDIV */
<> 128:9bcdf88f62b0 1485 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFPERCLKDIV */
<> 128:9bcdf88f62b0 1486 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFPERCLKDIV */
<> 128:9bcdf88f62b0 1487 #define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */
<> 128:9bcdf88f62b0 1488 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFPERCLKDIV */
<> 128:9bcdf88f62b0 1489 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFPERCLKDIV */
<> 128:9bcdf88f62b0 1490 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFPERCLKDIV */
<> 128:9bcdf88f62b0 1491 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFPERCLKDIV */
<> 128:9bcdf88f62b0 1492 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFPERCLKDIV */
<> 128:9bcdf88f62b0 1493 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFPERCLKDIV */
<> 128:9bcdf88f62b0 1494 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFPERCLKDIV */
<> 128:9bcdf88f62b0 1495 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFPERCLKDIV */
<> 128:9bcdf88f62b0 1496 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFPERCLKDIV */
<> 128:9bcdf88f62b0 1497 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFPERCLKDIV */
<> 128:9bcdf88f62b0 1498 #define CMU_HFPERCLKDIV_HFPERCLKEN (0x1UL << 8) /**< HFPERCLK Enable */
<> 128:9bcdf88f62b0 1499 #define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT 8 /**< Shift value for CMU_HFPERCLKEN */
<> 128:9bcdf88f62b0 1500 #define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK 0x100UL /**< Bit mask for CMU_HFPERCLKEN */
<> 128:9bcdf88f62b0 1501 #define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */
<> 128:9bcdf88f62b0 1502 #define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */
<> 128:9bcdf88f62b0 1503
<> 128:9bcdf88f62b0 1504 /* Bit fields for CMU HFRCOCTRL */
<> 128:9bcdf88f62b0 1505 #define _CMU_HFRCOCTRL_RESETVALUE 0x00000380UL /**< Default value for CMU_HFRCOCTRL */
<> 128:9bcdf88f62b0 1506 #define _CMU_HFRCOCTRL_MASK 0x0001F7FFUL /**< Mask for CMU_HFRCOCTRL */
<> 128:9bcdf88f62b0 1507 #define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */
<> 128:9bcdf88f62b0 1508 #define _CMU_HFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */
<> 128:9bcdf88f62b0 1509 #define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_HFRCOCTRL */
<> 128:9bcdf88f62b0 1510 #define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
<> 128:9bcdf88f62b0 1511 #define _CMU_HFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */
<> 128:9bcdf88f62b0 1512 #define _CMU_HFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */
<> 128:9bcdf88f62b0 1513 #define _CMU_HFRCOCTRL_BAND_1MHZ 0x00000000UL /**< Mode 1MHZ for CMU_HFRCOCTRL */
<> 128:9bcdf88f62b0 1514 #define _CMU_HFRCOCTRL_BAND_7MHZ 0x00000001UL /**< Mode 7MHZ for CMU_HFRCOCTRL */
<> 128:9bcdf88f62b0 1515 #define _CMU_HFRCOCTRL_BAND_11MHZ 0x00000002UL /**< Mode 11MHZ for CMU_HFRCOCTRL */
<> 128:9bcdf88f62b0 1516 #define _CMU_HFRCOCTRL_BAND_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_HFRCOCTRL */
<> 128:9bcdf88f62b0 1517 #define _CMU_HFRCOCTRL_BAND_14MHZ 0x00000003UL /**< Mode 14MHZ for CMU_HFRCOCTRL */
<> 128:9bcdf88f62b0 1518 #define _CMU_HFRCOCTRL_BAND_21MHZ 0x00000004UL /**< Mode 21MHZ for CMU_HFRCOCTRL */
<> 128:9bcdf88f62b0 1519 #define CMU_HFRCOCTRL_BAND_1MHZ (_CMU_HFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_HFRCOCTRL */
<> 128:9bcdf88f62b0 1520 #define CMU_HFRCOCTRL_BAND_7MHZ (_CMU_HFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_HFRCOCTRL */
<> 128:9bcdf88f62b0 1521 #define CMU_HFRCOCTRL_BAND_11MHZ (_CMU_HFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_HFRCOCTRL */
<> 128:9bcdf88f62b0 1522 #define CMU_HFRCOCTRL_BAND_DEFAULT (_CMU_HFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
<> 128:9bcdf88f62b0 1523 #define CMU_HFRCOCTRL_BAND_14MHZ (_CMU_HFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_HFRCOCTRL */
<> 128:9bcdf88f62b0 1524 #define CMU_HFRCOCTRL_BAND_21MHZ (_CMU_HFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_HFRCOCTRL */
<> 128:9bcdf88f62b0 1525 #define _CMU_HFRCOCTRL_SUDELAY_SHIFT 12 /**< Shift value for CMU_SUDELAY */
<> 128:9bcdf88f62b0 1526 #define _CMU_HFRCOCTRL_SUDELAY_MASK 0x1F000UL /**< Bit mask for CMU_SUDELAY */
<> 128:9bcdf88f62b0 1527 #define _CMU_HFRCOCTRL_SUDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */
<> 128:9bcdf88f62b0 1528 #define CMU_HFRCOCTRL_SUDELAY_DEFAULT (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
<> 128:9bcdf88f62b0 1529
<> 128:9bcdf88f62b0 1530 /* Bit fields for CMU LFRCOCTRL */
<> 128:9bcdf88f62b0 1531 #define _CMU_LFRCOCTRL_RESETVALUE 0x00000040UL /**< Default value for CMU_LFRCOCTRL */
<> 128:9bcdf88f62b0 1532 #define _CMU_LFRCOCTRL_MASK 0x0000007FUL /**< Mask for CMU_LFRCOCTRL */
<> 128:9bcdf88f62b0 1533 #define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */
<> 128:9bcdf88f62b0 1534 #define _CMU_LFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */
<> 128:9bcdf88f62b0 1535 #define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000040UL /**< Mode DEFAULT for CMU_LFRCOCTRL */
<> 128:9bcdf88f62b0 1536 #define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */
<> 128:9bcdf88f62b0 1537
<> 128:9bcdf88f62b0 1538 /* Bit fields for CMU AUXHFRCOCTRL */
<> 128:9bcdf88f62b0 1539 #define _CMU_AUXHFRCOCTRL_RESETVALUE 0x00000080UL /**< Default value for CMU_AUXHFRCOCTRL */
<> 128:9bcdf88f62b0 1540 #define _CMU_AUXHFRCOCTRL_MASK 0x000007FFUL /**< Mask for CMU_AUXHFRCOCTRL */
<> 128:9bcdf88f62b0 1541 #define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */
<> 128:9bcdf88f62b0 1542 #define _CMU_AUXHFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */
<> 128:9bcdf88f62b0 1543 #define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */
<> 128:9bcdf88f62b0 1544 #define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */
<> 128:9bcdf88f62b0 1545 #define _CMU_AUXHFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */
<> 128:9bcdf88f62b0 1546 #define _CMU_AUXHFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */
<> 128:9bcdf88f62b0 1547 #define _CMU_AUXHFRCOCTRL_BAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */
<> 128:9bcdf88f62b0 1548 #define _CMU_AUXHFRCOCTRL_BAND_14MHZ 0x00000000UL /**< Mode 14MHZ for CMU_AUXHFRCOCTRL */
<> 128:9bcdf88f62b0 1549 #define _CMU_AUXHFRCOCTRL_BAND_11MHZ 0x00000001UL /**< Mode 11MHZ for CMU_AUXHFRCOCTRL */
<> 128:9bcdf88f62b0 1550 #define _CMU_AUXHFRCOCTRL_BAND_7MHZ 0x00000002UL /**< Mode 7MHZ for CMU_AUXHFRCOCTRL */
<> 128:9bcdf88f62b0 1551 #define _CMU_AUXHFRCOCTRL_BAND_1MHZ 0x00000003UL /**< Mode 1MHZ for CMU_AUXHFRCOCTRL */
<> 128:9bcdf88f62b0 1552 #define _CMU_AUXHFRCOCTRL_BAND_21MHZ 0x00000007UL /**< Mode 21MHZ for CMU_AUXHFRCOCTRL */
<> 128:9bcdf88f62b0 1553 #define CMU_AUXHFRCOCTRL_BAND_DEFAULT (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */
<> 128:9bcdf88f62b0 1554 #define CMU_AUXHFRCOCTRL_BAND_14MHZ (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_AUXHFRCOCTRL */
<> 128:9bcdf88f62b0 1555 #define CMU_AUXHFRCOCTRL_BAND_11MHZ (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_AUXHFRCOCTRL */
<> 128:9bcdf88f62b0 1556 #define CMU_AUXHFRCOCTRL_BAND_7MHZ (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_AUXHFRCOCTRL */
<> 128:9bcdf88f62b0 1557 #define CMU_AUXHFRCOCTRL_BAND_1MHZ (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_AUXHFRCOCTRL */
<> 128:9bcdf88f62b0 1558 #define CMU_AUXHFRCOCTRL_BAND_21MHZ (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_AUXHFRCOCTRL */
<> 128:9bcdf88f62b0 1559
<> 128:9bcdf88f62b0 1560 /* Bit fields for CMU CALCTRL */
<> 128:9bcdf88f62b0 1561 #define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */
<> 128:9bcdf88f62b0 1562 #define _CMU_CALCTRL_MASK 0x0000007FUL /**< Mask for CMU_CALCTRL */
<> 128:9bcdf88f62b0 1563 #define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */
<> 128:9bcdf88f62b0 1564 #define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */
<> 128:9bcdf88f62b0 1565 #define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */
<> 128:9bcdf88f62b0 1566 #define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */
<> 128:9bcdf88f62b0 1567 #define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */
<> 128:9bcdf88f62b0 1568 #define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */
<> 128:9bcdf88f62b0 1569 #define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */
<> 128:9bcdf88f62b0 1570 #define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */
<> 128:9bcdf88f62b0 1571 #define _CMU_CALCTRL_UPSEL_USHFRCO 0x00000005UL /**< Mode USHFRCO for CMU_CALCTRL */
<> 128:9bcdf88f62b0 1572 #define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */
<> 128:9bcdf88f62b0 1573 #define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */
<> 128:9bcdf88f62b0 1574 #define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */
<> 128:9bcdf88f62b0 1575 #define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */
<> 128:9bcdf88f62b0 1576 #define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */
<> 128:9bcdf88f62b0 1577 #define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */
<> 128:9bcdf88f62b0 1578 #define CMU_CALCTRL_UPSEL_USHFRCO (_CMU_CALCTRL_UPSEL_USHFRCO << 0) /**< Shifted mode USHFRCO for CMU_CALCTRL */
<> 128:9bcdf88f62b0 1579 #define _CMU_CALCTRL_DOWNSEL_SHIFT 3 /**< Shift value for CMU_DOWNSEL */
<> 128:9bcdf88f62b0 1580 #define _CMU_CALCTRL_DOWNSEL_MASK 0x38UL /**< Bit mask for CMU_DOWNSEL */
<> 128:9bcdf88f62b0 1581 #define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */
<> 128:9bcdf88f62b0 1582 #define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */
<> 128:9bcdf88f62b0 1583 #define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */
<> 128:9bcdf88f62b0 1584 #define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */
<> 128:9bcdf88f62b0 1585 #define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */
<> 128:9bcdf88f62b0 1586 #define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */
<> 128:9bcdf88f62b0 1587 #define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */
<> 128:9bcdf88f62b0 1588 #define _CMU_CALCTRL_DOWNSEL_USHFRCO 0x00000006UL /**< Mode USHFRCO for CMU_CALCTRL */
<> 128:9bcdf88f62b0 1589 #define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CALCTRL */
<> 128:9bcdf88f62b0 1590 #define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 3) /**< Shifted mode HFCLK for CMU_CALCTRL */
<> 128:9bcdf88f62b0 1591 #define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_CALCTRL */
<> 128:9bcdf88f62b0 1592 #define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_CALCTRL */
<> 128:9bcdf88f62b0 1593 #define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 3) /**< Shifted mode HFRCO for CMU_CALCTRL */
<> 128:9bcdf88f62b0 1594 #define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 3) /**< Shifted mode LFRCO for CMU_CALCTRL */
<> 128:9bcdf88f62b0 1595 #define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */
<> 128:9bcdf88f62b0 1596 #define CMU_CALCTRL_DOWNSEL_USHFRCO (_CMU_CALCTRL_DOWNSEL_USHFRCO << 3) /**< Shifted mode USHFRCO for CMU_CALCTRL */
<> 128:9bcdf88f62b0 1597 #define CMU_CALCTRL_CONT (0x1UL << 6) /**< Continuous Calibration */
<> 128:9bcdf88f62b0 1598 #define _CMU_CALCTRL_CONT_SHIFT 6 /**< Shift value for CMU_CONT */
<> 128:9bcdf88f62b0 1599 #define _CMU_CALCTRL_CONT_MASK 0x40UL /**< Bit mask for CMU_CONT */
<> 128:9bcdf88f62b0 1600 #define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */
<> 128:9bcdf88f62b0 1601 #define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CALCTRL */
<> 128:9bcdf88f62b0 1602
<> 128:9bcdf88f62b0 1603 /* Bit fields for CMU CALCNT */
<> 128:9bcdf88f62b0 1604 #define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */
<> 128:9bcdf88f62b0 1605 #define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */
<> 128:9bcdf88f62b0 1606 #define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */
<> 128:9bcdf88f62b0 1607 #define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */
<> 128:9bcdf88f62b0 1608 #define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */
<> 128:9bcdf88f62b0 1609 #define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */
<> 128:9bcdf88f62b0 1610
<> 128:9bcdf88f62b0 1611 /* Bit fields for CMU OSCENCMD */
<> 128:9bcdf88f62b0 1612 #define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */
<> 128:9bcdf88f62b0 1613 #define _CMU_OSCENCMD_MASK 0x00000FFFUL /**< Mask for CMU_OSCENCMD */
<> 128:9bcdf88f62b0 1614 #define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */
<> 128:9bcdf88f62b0 1615 #define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */
<> 128:9bcdf88f62b0 1616 #define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */
<> 128:9bcdf88f62b0 1617 #define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
<> 128:9bcdf88f62b0 1618 #define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
<> 128:9bcdf88f62b0 1619 #define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */
<> 128:9bcdf88f62b0 1620 #define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */
<> 128:9bcdf88f62b0 1621 #define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */
<> 128:9bcdf88f62b0 1622 #define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
<> 128:9bcdf88f62b0 1623 #define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
<> 128:9bcdf88f62b0 1624 #define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */
<> 128:9bcdf88f62b0 1625 #define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */
<> 128:9bcdf88f62b0 1626 #define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */
<> 128:9bcdf88f62b0 1627 #define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
<> 128:9bcdf88f62b0 1628 #define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
<> 128:9bcdf88f62b0 1629 #define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */
<> 128:9bcdf88f62b0 1630 #define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */
<> 128:9bcdf88f62b0 1631 #define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */
<> 128:9bcdf88f62b0 1632 #define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
<> 128:9bcdf88f62b0 1633 #define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
<> 128:9bcdf88f62b0 1634 #define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */
<> 128:9bcdf88f62b0 1635 #define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */
<> 128:9bcdf88f62b0 1636 #define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */
<> 128:9bcdf88f62b0 1637 #define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
<> 128:9bcdf88f62b0 1638 #define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
<> 128:9bcdf88f62b0 1639 #define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */
<> 128:9bcdf88f62b0 1640 #define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */
<> 128:9bcdf88f62b0 1641 #define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */
<> 128:9bcdf88f62b0 1642 #define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
<> 128:9bcdf88f62b0 1643 #define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
<> 128:9bcdf88f62b0 1644 #define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */
<> 128:9bcdf88f62b0 1645 #define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */
<> 128:9bcdf88f62b0 1646 #define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */
<> 128:9bcdf88f62b0 1647 #define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
<> 128:9bcdf88f62b0 1648 #define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
<> 128:9bcdf88f62b0 1649 #define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */
<> 128:9bcdf88f62b0 1650 #define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */
<> 128:9bcdf88f62b0 1651 #define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */
<> 128:9bcdf88f62b0 1652 #define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
<> 128:9bcdf88f62b0 1653 #define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
<> 128:9bcdf88f62b0 1654 #define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */
<> 128:9bcdf88f62b0 1655 #define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */
<> 128:9bcdf88f62b0 1656 #define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */
<> 128:9bcdf88f62b0 1657 #define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
<> 128:9bcdf88f62b0 1658 #define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
<> 128:9bcdf88f62b0 1659 #define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */
<> 128:9bcdf88f62b0 1660 #define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */
<> 128:9bcdf88f62b0 1661 #define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */
<> 128:9bcdf88f62b0 1662 #define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
<> 128:9bcdf88f62b0 1663 #define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
<> 128:9bcdf88f62b0 1664 #define CMU_OSCENCMD_USHFRCOEN (0x1UL << 10) /**< USHFRCO Enable */
<> 128:9bcdf88f62b0 1665 #define _CMU_OSCENCMD_USHFRCOEN_SHIFT 10 /**< Shift value for CMU_USHFRCOEN */
<> 128:9bcdf88f62b0 1666 #define _CMU_OSCENCMD_USHFRCOEN_MASK 0x400UL /**< Bit mask for CMU_USHFRCOEN */
<> 128:9bcdf88f62b0 1667 #define _CMU_OSCENCMD_USHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
<> 128:9bcdf88f62b0 1668 #define CMU_OSCENCMD_USHFRCOEN_DEFAULT (_CMU_OSCENCMD_USHFRCOEN_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
<> 128:9bcdf88f62b0 1669 #define CMU_OSCENCMD_USHFRCODIS (0x1UL << 11) /**< USHFRCO Disable */
<> 128:9bcdf88f62b0 1670 #define _CMU_OSCENCMD_USHFRCODIS_SHIFT 11 /**< Shift value for CMU_USHFRCODIS */
<> 128:9bcdf88f62b0 1671 #define _CMU_OSCENCMD_USHFRCODIS_MASK 0x800UL /**< Bit mask for CMU_USHFRCODIS */
<> 128:9bcdf88f62b0 1672 #define _CMU_OSCENCMD_USHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
<> 128:9bcdf88f62b0 1673 #define CMU_OSCENCMD_USHFRCODIS_DEFAULT (_CMU_OSCENCMD_USHFRCODIS_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
<> 128:9bcdf88f62b0 1674
<> 128:9bcdf88f62b0 1675 /* Bit fields for CMU CMD */
<> 128:9bcdf88f62b0 1676 #define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */
<> 128:9bcdf88f62b0 1677 #define _CMU_CMD_MASK 0x000000FFUL /**< Mask for CMU_CMD */
<> 128:9bcdf88f62b0 1678 #define _CMU_CMD_HFCLKSEL_SHIFT 0 /**< Shift value for CMU_HFCLKSEL */
<> 128:9bcdf88f62b0 1679 #define _CMU_CMD_HFCLKSEL_MASK 0x7UL /**< Bit mask for CMU_HFCLKSEL */
<> 128:9bcdf88f62b0 1680 #define _CMU_CMD_HFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */
<> 128:9bcdf88f62b0 1681 #define _CMU_CMD_HFCLKSEL_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_CMD */
<> 128:9bcdf88f62b0 1682 #define _CMU_CMD_HFCLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_CMD */
<> 128:9bcdf88f62b0 1683 #define _CMU_CMD_HFCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */
<> 128:9bcdf88f62b0 1684 #define _CMU_CMD_HFCLKSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_CMD */
<> 128:9bcdf88f62b0 1685 #define _CMU_CMD_HFCLKSEL_USHFRCODIV2 0x00000005UL /**< Mode USHFRCODIV2 for CMU_CMD */
<> 128:9bcdf88f62b0 1686 #define CMU_CMD_HFCLKSEL_DEFAULT (_CMU_CMD_HFCLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */
<> 128:9bcdf88f62b0 1687 #define CMU_CMD_HFCLKSEL_HFRCO (_CMU_CMD_HFCLKSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CMD */
<> 128:9bcdf88f62b0 1688 #define CMU_CMD_HFCLKSEL_HFXO (_CMU_CMD_HFCLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CMD */
<> 128:9bcdf88f62b0 1689 #define CMU_CMD_HFCLKSEL_LFRCO (_CMU_CMD_HFCLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CMD */
<> 128:9bcdf88f62b0 1690 #define CMU_CMD_HFCLKSEL_LFXO (_CMU_CMD_HFCLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CMD */
<> 128:9bcdf88f62b0 1691 #define CMU_CMD_HFCLKSEL_USHFRCODIV2 (_CMU_CMD_HFCLKSEL_USHFRCODIV2 << 0) /**< Shifted mode USHFRCODIV2 for CMU_CMD */
<> 128:9bcdf88f62b0 1692 #define CMU_CMD_CALSTART (0x1UL << 3) /**< Calibration Start */
<> 128:9bcdf88f62b0 1693 #define _CMU_CMD_CALSTART_SHIFT 3 /**< Shift value for CMU_CALSTART */
<> 128:9bcdf88f62b0 1694 #define _CMU_CMD_CALSTART_MASK 0x8UL /**< Bit mask for CMU_CALSTART */
<> 128:9bcdf88f62b0 1695 #define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */
<> 128:9bcdf88f62b0 1696 #define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CMD */
<> 128:9bcdf88f62b0 1697 #define CMU_CMD_CALSTOP (0x1UL << 4) /**< Calibration Stop */
<> 128:9bcdf88f62b0 1698 #define _CMU_CMD_CALSTOP_SHIFT 4 /**< Shift value for CMU_CALSTOP */
<> 128:9bcdf88f62b0 1699 #define _CMU_CMD_CALSTOP_MASK 0x10UL /**< Bit mask for CMU_CALSTOP */
<> 128:9bcdf88f62b0 1700 #define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */
<> 128:9bcdf88f62b0 1701 #define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */
<> 128:9bcdf88f62b0 1702 #define _CMU_CMD_USBCCLKSEL_SHIFT 5 /**< Shift value for CMU_USBCCLKSEL */
<> 128:9bcdf88f62b0 1703 #define _CMU_CMD_USBCCLKSEL_MASK 0xE0UL /**< Bit mask for CMU_USBCCLKSEL */
<> 128:9bcdf88f62b0 1704 #define _CMU_CMD_USBCCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */
<> 128:9bcdf88f62b0 1705 #define _CMU_CMD_USBCCLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CMD */
<> 128:9bcdf88f62b0 1706 #define _CMU_CMD_USBCCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */
<> 128:9bcdf88f62b0 1707 #define _CMU_CMD_USBCCLKSEL_USHFRCO 0x00000004UL /**< Mode USHFRCO for CMU_CMD */
<> 128:9bcdf88f62b0 1708 #define CMU_CMD_USBCCLKSEL_DEFAULT (_CMU_CMD_USBCCLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CMD */
<> 128:9bcdf88f62b0 1709 #define CMU_CMD_USBCCLKSEL_LFXO (_CMU_CMD_USBCCLKSEL_LFXO << 5) /**< Shifted mode LFXO for CMU_CMD */
<> 128:9bcdf88f62b0 1710 #define CMU_CMD_USBCCLKSEL_LFRCO (_CMU_CMD_USBCCLKSEL_LFRCO << 5) /**< Shifted mode LFRCO for CMU_CMD */
<> 128:9bcdf88f62b0 1711 #define CMU_CMD_USBCCLKSEL_USHFRCO (_CMU_CMD_USBCCLKSEL_USHFRCO << 5) /**< Shifted mode USHFRCO for CMU_CMD */
<> 128:9bcdf88f62b0 1712
<> 128:9bcdf88f62b0 1713 /* Bit fields for CMU LFCLKSEL */
<> 128:9bcdf88f62b0 1714 #define _CMU_LFCLKSEL_RESETVALUE 0x00000015UL /**< Default value for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 1715 #define _CMU_LFCLKSEL_MASK 0x0011003FUL /**< Mask for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 1716 #define _CMU_LFCLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */
<> 128:9bcdf88f62b0 1717 #define _CMU_LFCLKSEL_LFA_MASK 0x3UL /**< Bit mask for CMU_LFA */
<> 128:9bcdf88f62b0 1718 #define _CMU_LFCLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 1719 #define _CMU_LFCLKSEL_LFA_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 1720 #define _CMU_LFCLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 1721 #define _CMU_LFCLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 1722 #define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 1723 #define CMU_LFCLKSEL_LFA_DISABLED (_CMU_LFCLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 1724 #define CMU_LFCLKSEL_LFA_DEFAULT (_CMU_LFCLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 1725 #define CMU_LFCLKSEL_LFA_LFRCO (_CMU_LFCLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 1726 #define CMU_LFCLKSEL_LFA_LFXO (_CMU_LFCLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 1727 #define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 1728 #define _CMU_LFCLKSEL_LFB_SHIFT 2 /**< Shift value for CMU_LFB */
<> 128:9bcdf88f62b0 1729 #define _CMU_LFCLKSEL_LFB_MASK 0xCUL /**< Bit mask for CMU_LFB */
<> 128:9bcdf88f62b0 1730 #define _CMU_LFCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 1731 #define _CMU_LFCLKSEL_LFB_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 1732 #define _CMU_LFCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 1733 #define _CMU_LFCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 1734 #define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 1735 #define CMU_LFCLKSEL_LFB_DISABLED (_CMU_LFCLKSEL_LFB_DISABLED << 2) /**< Shifted mode DISABLED for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 1736 #define CMU_LFCLKSEL_LFB_DEFAULT (_CMU_LFCLKSEL_LFB_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 1737 #define CMU_LFCLKSEL_LFB_LFRCO (_CMU_LFCLKSEL_LFB_LFRCO << 2) /**< Shifted mode LFRCO for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 1738 #define CMU_LFCLKSEL_LFB_LFXO (_CMU_LFCLKSEL_LFB_LFXO << 2) /**< Shifted mode LFXO for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 1739 #define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 1740 #define _CMU_LFCLKSEL_LFC_SHIFT 4 /**< Shift value for CMU_LFC */
<> 128:9bcdf88f62b0 1741 #define _CMU_LFCLKSEL_LFC_MASK 0x30UL /**< Bit mask for CMU_LFC */
<> 128:9bcdf88f62b0 1742 #define _CMU_LFCLKSEL_LFC_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 1743 #define _CMU_LFCLKSEL_LFC_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 1744 #define _CMU_LFCLKSEL_LFC_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 1745 #define _CMU_LFCLKSEL_LFC_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 1746 #define CMU_LFCLKSEL_LFC_DISABLED (_CMU_LFCLKSEL_LFC_DISABLED << 4) /**< Shifted mode DISABLED for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 1747 #define CMU_LFCLKSEL_LFC_DEFAULT (_CMU_LFCLKSEL_LFC_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 1748 #define CMU_LFCLKSEL_LFC_LFRCO (_CMU_LFCLKSEL_LFC_LFRCO << 4) /**< Shifted mode LFRCO for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 1749 #define CMU_LFCLKSEL_LFC_LFXO (_CMU_LFCLKSEL_LFC_LFXO << 4) /**< Shifted mode LFXO for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 1750 #define CMU_LFCLKSEL_LFAE (0x1UL << 16) /**< Clock Select for LFA Extended */
<> 128:9bcdf88f62b0 1751 #define _CMU_LFCLKSEL_LFAE_SHIFT 16 /**< Shift value for CMU_LFAE */
<> 128:9bcdf88f62b0 1752 #define _CMU_LFCLKSEL_LFAE_MASK 0x10000UL /**< Bit mask for CMU_LFAE */
<> 128:9bcdf88f62b0 1753 #define _CMU_LFCLKSEL_LFAE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 1754 #define _CMU_LFCLKSEL_LFAE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 1755 #define _CMU_LFCLKSEL_LFAE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 1756 #define CMU_LFCLKSEL_LFAE_DEFAULT (_CMU_LFCLKSEL_LFAE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 1757 #define CMU_LFCLKSEL_LFAE_DISABLED (_CMU_LFCLKSEL_LFAE_DISABLED << 16) /**< Shifted mode DISABLED for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 1758 #define CMU_LFCLKSEL_LFAE_ULFRCO (_CMU_LFCLKSEL_LFAE_ULFRCO << 16) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 1759 #define CMU_LFCLKSEL_LFBE (0x1UL << 20) /**< Clock Select for LFB Extended */
<> 128:9bcdf88f62b0 1760 #define _CMU_LFCLKSEL_LFBE_SHIFT 20 /**< Shift value for CMU_LFBE */
<> 128:9bcdf88f62b0 1761 #define _CMU_LFCLKSEL_LFBE_MASK 0x100000UL /**< Bit mask for CMU_LFBE */
<> 128:9bcdf88f62b0 1762 #define _CMU_LFCLKSEL_LFBE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 1763 #define _CMU_LFCLKSEL_LFBE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 1764 #define _CMU_LFCLKSEL_LFBE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 1765 #define CMU_LFCLKSEL_LFBE_DEFAULT (_CMU_LFCLKSEL_LFBE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 1766 #define CMU_LFCLKSEL_LFBE_DISABLED (_CMU_LFCLKSEL_LFBE_DISABLED << 20) /**< Shifted mode DISABLED for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 1767 #define CMU_LFCLKSEL_LFBE_ULFRCO (_CMU_LFCLKSEL_LFBE_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */
<> 128:9bcdf88f62b0 1768
<> 128:9bcdf88f62b0 1769 /* Bit fields for CMU STATUS */
<> 128:9bcdf88f62b0 1770 #define _CMU_STATUS_RESETVALUE 0x00000403UL /**< Default value for CMU_STATUS */
<> 128:9bcdf88f62b0 1771 #define _CMU_STATUS_MASK 0x04F77FFFUL /**< Mask for CMU_STATUS */
<> 128:9bcdf88f62b0 1772 #define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */
<> 128:9bcdf88f62b0 1773 #define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */
<> 128:9bcdf88f62b0 1774 #define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */
<> 128:9bcdf88f62b0 1775 #define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 1776 #define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 1777 #define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */
<> 128:9bcdf88f62b0 1778 #define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */
<> 128:9bcdf88f62b0 1779 #define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */
<> 128:9bcdf88f62b0 1780 #define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 1781 #define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 1782 #define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */
<> 128:9bcdf88f62b0 1783 #define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */
<> 128:9bcdf88f62b0 1784 #define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */
<> 128:9bcdf88f62b0 1785 #define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 1786 #define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 1787 #define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */
<> 128:9bcdf88f62b0 1788 #define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */
<> 128:9bcdf88f62b0 1789 #define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */
<> 128:9bcdf88f62b0 1790 #define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 1791 #define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 1792 #define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */
<> 128:9bcdf88f62b0 1793 #define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */
<> 128:9bcdf88f62b0 1794 #define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */
<> 128:9bcdf88f62b0 1795 #define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 1796 #define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 1797 #define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */
<> 128:9bcdf88f62b0 1798 #define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */
<> 128:9bcdf88f62b0 1799 #define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */
<> 128:9bcdf88f62b0 1800 #define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 1801 #define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 1802 #define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */
<> 128:9bcdf88f62b0 1803 #define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */
<> 128:9bcdf88f62b0 1804 #define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */
<> 128:9bcdf88f62b0 1805 #define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 1806 #define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 1807 #define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */
<> 128:9bcdf88f62b0 1808 #define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */
<> 128:9bcdf88f62b0 1809 #define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */
<> 128:9bcdf88f62b0 1810 #define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 1811 #define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 1812 #define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */
<> 128:9bcdf88f62b0 1813 #define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */
<> 128:9bcdf88f62b0 1814 #define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */
<> 128:9bcdf88f62b0 1815 #define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 1816 #define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 1817 #define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */
<> 128:9bcdf88f62b0 1818 #define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */
<> 128:9bcdf88f62b0 1819 #define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */
<> 128:9bcdf88f62b0 1820 #define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 1821 #define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 1822 #define CMU_STATUS_HFRCOSEL (0x1UL << 10) /**< HFRCO Selected */
<> 128:9bcdf88f62b0 1823 #define _CMU_STATUS_HFRCOSEL_SHIFT 10 /**< Shift value for CMU_HFRCOSEL */
<> 128:9bcdf88f62b0 1824 #define _CMU_STATUS_HFRCOSEL_MASK 0x400UL /**< Bit mask for CMU_HFRCOSEL */
<> 128:9bcdf88f62b0 1825 #define _CMU_STATUS_HFRCOSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 1826 #define CMU_STATUS_HFRCOSEL_DEFAULT (_CMU_STATUS_HFRCOSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 1827 #define CMU_STATUS_HFXOSEL (0x1UL << 11) /**< HFXO Selected */
<> 128:9bcdf88f62b0 1828 #define _CMU_STATUS_HFXOSEL_SHIFT 11 /**< Shift value for CMU_HFXOSEL */
<> 128:9bcdf88f62b0 1829 #define _CMU_STATUS_HFXOSEL_MASK 0x800UL /**< Bit mask for CMU_HFXOSEL */
<> 128:9bcdf88f62b0 1830 #define _CMU_STATUS_HFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 1831 #define CMU_STATUS_HFXOSEL_DEFAULT (_CMU_STATUS_HFXOSEL_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 1832 #define CMU_STATUS_LFRCOSEL (0x1UL << 12) /**< LFRCO Selected */
<> 128:9bcdf88f62b0 1833 #define _CMU_STATUS_LFRCOSEL_SHIFT 12 /**< Shift value for CMU_LFRCOSEL */
<> 128:9bcdf88f62b0 1834 #define _CMU_STATUS_LFRCOSEL_MASK 0x1000UL /**< Bit mask for CMU_LFRCOSEL */
<> 128:9bcdf88f62b0 1835 #define _CMU_STATUS_LFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 1836 #define CMU_STATUS_LFRCOSEL_DEFAULT (_CMU_STATUS_LFRCOSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 1837 #define CMU_STATUS_LFXOSEL (0x1UL << 13) /**< LFXO Selected */
<> 128:9bcdf88f62b0 1838 #define _CMU_STATUS_LFXOSEL_SHIFT 13 /**< Shift value for CMU_LFXOSEL */
<> 128:9bcdf88f62b0 1839 #define _CMU_STATUS_LFXOSEL_MASK 0x2000UL /**< Bit mask for CMU_LFXOSEL */
<> 128:9bcdf88f62b0 1840 #define _CMU_STATUS_LFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 1841 #define CMU_STATUS_LFXOSEL_DEFAULT (_CMU_STATUS_LFXOSEL_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 1842 #define CMU_STATUS_CALBSY (0x1UL << 14) /**< Calibration Busy */
<> 128:9bcdf88f62b0 1843 #define _CMU_STATUS_CALBSY_SHIFT 14 /**< Shift value for CMU_CALBSY */
<> 128:9bcdf88f62b0 1844 #define _CMU_STATUS_CALBSY_MASK 0x4000UL /**< Bit mask for CMU_CALBSY */
<> 128:9bcdf88f62b0 1845 #define _CMU_STATUS_CALBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 1846 #define CMU_STATUS_CALBSY_DEFAULT (_CMU_STATUS_CALBSY_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 1847 #define CMU_STATUS_USBCLFXOSEL (0x1UL << 16) /**< USBC LFXO Selected */
<> 128:9bcdf88f62b0 1848 #define _CMU_STATUS_USBCLFXOSEL_SHIFT 16 /**< Shift value for CMU_USBCLFXOSEL */
<> 128:9bcdf88f62b0 1849 #define _CMU_STATUS_USBCLFXOSEL_MASK 0x10000UL /**< Bit mask for CMU_USBCLFXOSEL */
<> 128:9bcdf88f62b0 1850 #define _CMU_STATUS_USBCLFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 1851 #define CMU_STATUS_USBCLFXOSEL_DEFAULT (_CMU_STATUS_USBCLFXOSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 1852 #define CMU_STATUS_USBCLFRCOSEL (0x1UL << 17) /**< USBC LFRCO Selected */
<> 128:9bcdf88f62b0 1853 #define _CMU_STATUS_USBCLFRCOSEL_SHIFT 17 /**< Shift value for CMU_USBCLFRCOSEL */
<> 128:9bcdf88f62b0 1854 #define _CMU_STATUS_USBCLFRCOSEL_MASK 0x20000UL /**< Bit mask for CMU_USBCLFRCOSEL */
<> 128:9bcdf88f62b0 1855 #define _CMU_STATUS_USBCLFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 1856 #define CMU_STATUS_USBCLFRCOSEL_DEFAULT (_CMU_STATUS_USBCLFRCOSEL_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 1857 #define CMU_STATUS_USBCUSHFRCOSEL (0x1UL << 18) /**< USBC USHFRCO Selected */
<> 128:9bcdf88f62b0 1858 #define _CMU_STATUS_USBCUSHFRCOSEL_SHIFT 18 /**< Shift value for CMU_USBCUSHFRCOSEL */
<> 128:9bcdf88f62b0 1859 #define _CMU_STATUS_USBCUSHFRCOSEL_MASK 0x40000UL /**< Bit mask for CMU_USBCUSHFRCOSEL */
<> 128:9bcdf88f62b0 1860 #define _CMU_STATUS_USBCUSHFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 1861 #define CMU_STATUS_USBCUSHFRCOSEL_DEFAULT (_CMU_STATUS_USBCUSHFRCOSEL_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 1862 #define CMU_STATUS_USBCHFCLKSYNC (0x1UL << 20) /**< USBC is synchronous to HFCLK */
<> 128:9bcdf88f62b0 1863 #define _CMU_STATUS_USBCHFCLKSYNC_SHIFT 20 /**< Shift value for CMU_USBCHFCLKSYNC */
<> 128:9bcdf88f62b0 1864 #define _CMU_STATUS_USBCHFCLKSYNC_MASK 0x100000UL /**< Bit mask for CMU_USBCHFCLKSYNC */
<> 128:9bcdf88f62b0 1865 #define _CMU_STATUS_USBCHFCLKSYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 1866 #define CMU_STATUS_USBCHFCLKSYNC_DEFAULT (_CMU_STATUS_USBCHFCLKSYNC_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 1867 #define CMU_STATUS_USHFRCOENS (0x1UL << 21) /**< USHFRCO Enable Status */
<> 128:9bcdf88f62b0 1868 #define _CMU_STATUS_USHFRCOENS_SHIFT 21 /**< Shift value for CMU_USHFRCOENS */
<> 128:9bcdf88f62b0 1869 #define _CMU_STATUS_USHFRCOENS_MASK 0x200000UL /**< Bit mask for CMU_USHFRCOENS */
<> 128:9bcdf88f62b0 1870 #define _CMU_STATUS_USHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 1871 #define CMU_STATUS_USHFRCOENS_DEFAULT (_CMU_STATUS_USHFRCOENS_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 1872 #define CMU_STATUS_USHFRCORDY (0x1UL << 22) /**< USHFRCO Ready */
<> 128:9bcdf88f62b0 1873 #define _CMU_STATUS_USHFRCORDY_SHIFT 22 /**< Shift value for CMU_USHFRCORDY */
<> 128:9bcdf88f62b0 1874 #define _CMU_STATUS_USHFRCORDY_MASK 0x400000UL /**< Bit mask for CMU_USHFRCORDY */
<> 128:9bcdf88f62b0 1875 #define _CMU_STATUS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 1876 #define CMU_STATUS_USHFRCORDY_DEFAULT (_CMU_STATUS_USHFRCORDY_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 1877 #define CMU_STATUS_USHFRCOSUSPEND (0x1UL << 23) /**< USHFRCO is suspended */
<> 128:9bcdf88f62b0 1878 #define _CMU_STATUS_USHFRCOSUSPEND_SHIFT 23 /**< Shift value for CMU_USHFRCOSUSPEND */
<> 128:9bcdf88f62b0 1879 #define _CMU_STATUS_USHFRCOSUSPEND_MASK 0x800000UL /**< Bit mask for CMU_USHFRCOSUSPEND */
<> 128:9bcdf88f62b0 1880 #define _CMU_STATUS_USHFRCOSUSPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 1881 #define CMU_STATUS_USHFRCOSUSPEND_DEFAULT (_CMU_STATUS_USHFRCOSUSPEND_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 1882 #define CMU_STATUS_USHFRCODIV2SEL (0x1UL << 26) /**< USHFRCODIV2 Selected */
<> 128:9bcdf88f62b0 1883 #define _CMU_STATUS_USHFRCODIV2SEL_SHIFT 26 /**< Shift value for CMU_USHFRCODIV2SEL */
<> 128:9bcdf88f62b0 1884 #define _CMU_STATUS_USHFRCODIV2SEL_MASK 0x4000000UL /**< Bit mask for CMU_USHFRCODIV2SEL */
<> 128:9bcdf88f62b0 1885 #define _CMU_STATUS_USHFRCODIV2SEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 1886 #define CMU_STATUS_USHFRCODIV2SEL_DEFAULT (_CMU_STATUS_USHFRCODIV2SEL_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_STATUS */
<> 128:9bcdf88f62b0 1887
<> 128:9bcdf88f62b0 1888 /* Bit fields for CMU IF */
<> 128:9bcdf88f62b0 1889 #define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */
<> 128:9bcdf88f62b0 1890 #define _CMU_IF_MASK 0x0000037FUL /**< Mask for CMU_IF */
<> 128:9bcdf88f62b0 1891 #define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */
<> 128:9bcdf88f62b0 1892 #define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */
<> 128:9bcdf88f62b0 1893 #define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */
<> 128:9bcdf88f62b0 1894 #define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */
<> 128:9bcdf88f62b0 1895 #define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */
<> 128:9bcdf88f62b0 1896 #define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */
<> 128:9bcdf88f62b0 1897 #define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */
<> 128:9bcdf88f62b0 1898 #define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */
<> 128:9bcdf88f62b0 1899 #define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
<> 128:9bcdf88f62b0 1900 #define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */
<> 128:9bcdf88f62b0 1901 #define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */
<> 128:9bcdf88f62b0 1902 #define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */
<> 128:9bcdf88f62b0 1903 #define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */
<> 128:9bcdf88f62b0 1904 #define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
<> 128:9bcdf88f62b0 1905 #define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */
<> 128:9bcdf88f62b0 1906 #define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */
<> 128:9bcdf88f62b0 1907 #define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */
<> 128:9bcdf88f62b0 1908 #define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */
<> 128:9bcdf88f62b0 1909 #define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
<> 128:9bcdf88f62b0 1910 #define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */
<> 128:9bcdf88f62b0 1911 #define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */
<> 128:9bcdf88f62b0 1912 #define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */
<> 128:9bcdf88f62b0 1913 #define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */
<> 128:9bcdf88f62b0 1914 #define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
<> 128:9bcdf88f62b0 1915 #define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */
<> 128:9bcdf88f62b0 1916 #define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */
<> 128:9bcdf88f62b0 1917 #define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */
<> 128:9bcdf88f62b0 1918 #define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */
<> 128:9bcdf88f62b0 1919 #define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
<> 128:9bcdf88f62b0 1920 #define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */
<> 128:9bcdf88f62b0 1921 #define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */
<> 128:9bcdf88f62b0 1922 #define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */
<> 128:9bcdf88f62b0 1923 #define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */
<> 128:9bcdf88f62b0 1924 #define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
<> 128:9bcdf88f62b0 1925 #define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */
<> 128:9bcdf88f62b0 1926 #define CMU_IF_USHFRCORDY (0x1UL << 8) /**< USHFRCO Ready Interrupt Flag */
<> 128:9bcdf88f62b0 1927 #define _CMU_IF_USHFRCORDY_SHIFT 8 /**< Shift value for CMU_USHFRCORDY */
<> 128:9bcdf88f62b0 1928 #define _CMU_IF_USHFRCORDY_MASK 0x100UL /**< Bit mask for CMU_USHFRCORDY */
<> 128:9bcdf88f62b0 1929 #define _CMU_IF_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
<> 128:9bcdf88f62b0 1930 #define CMU_IF_USHFRCORDY_DEFAULT (_CMU_IF_USHFRCORDY_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IF */
<> 128:9bcdf88f62b0 1931 #define CMU_IF_USBCHFOSCSEL (0x1UL << 9) /**< USBC HF-oscillator Selected Interrupt Flag */
<> 128:9bcdf88f62b0 1932 #define _CMU_IF_USBCHFOSCSEL_SHIFT 9 /**< Shift value for CMU_USBCHFOSCSEL */
<> 128:9bcdf88f62b0 1933 #define _CMU_IF_USBCHFOSCSEL_MASK 0x200UL /**< Bit mask for CMU_USBCHFOSCSEL */
<> 128:9bcdf88f62b0 1934 #define _CMU_IF_USBCHFOSCSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
<> 128:9bcdf88f62b0 1935 #define CMU_IF_USBCHFOSCSEL_DEFAULT (_CMU_IF_USBCHFOSCSEL_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IF */
<> 128:9bcdf88f62b0 1936
<> 128:9bcdf88f62b0 1937 /* Bit fields for CMU IFS */
<> 128:9bcdf88f62b0 1938 #define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */
<> 128:9bcdf88f62b0 1939 #define _CMU_IFS_MASK 0x0000037FUL /**< Mask for CMU_IFS */
<> 128:9bcdf88f62b0 1940 #define CMU_IFS_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Set */
<> 128:9bcdf88f62b0 1941 #define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */
<> 128:9bcdf88f62b0 1942 #define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */
<> 128:9bcdf88f62b0 1943 #define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
<> 128:9bcdf88f62b0 1944 #define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */
<> 128:9bcdf88f62b0 1945 #define CMU_IFS_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Set */
<> 128:9bcdf88f62b0 1946 #define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */
<> 128:9bcdf88f62b0 1947 #define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */
<> 128:9bcdf88f62b0 1948 #define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
<> 128:9bcdf88f62b0 1949 #define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */
<> 128:9bcdf88f62b0 1950 #define CMU_IFS_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Set */
<> 128:9bcdf88f62b0 1951 #define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */
<> 128:9bcdf88f62b0 1952 #define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */
<> 128:9bcdf88f62b0 1953 #define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
<> 128:9bcdf88f62b0 1954 #define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */
<> 128:9bcdf88f62b0 1955 #define CMU_IFS_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Set */
<> 128:9bcdf88f62b0 1956 #define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */
<> 128:9bcdf88f62b0 1957 #define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */
<> 128:9bcdf88f62b0 1958 #define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
<> 128:9bcdf88f62b0 1959 #define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */
<> 128:9bcdf88f62b0 1960 #define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Set */
<> 128:9bcdf88f62b0 1961 #define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */
<> 128:9bcdf88f62b0 1962 #define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */
<> 128:9bcdf88f62b0 1963 #define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
<> 128:9bcdf88f62b0 1964 #define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */
<> 128:9bcdf88f62b0 1965 #define CMU_IFS_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Set */
<> 128:9bcdf88f62b0 1966 #define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */
<> 128:9bcdf88f62b0 1967 #define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */
<> 128:9bcdf88f62b0 1968 #define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
<> 128:9bcdf88f62b0 1969 #define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */
<> 128:9bcdf88f62b0 1970 #define CMU_IFS_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Set */
<> 128:9bcdf88f62b0 1971 #define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */
<> 128:9bcdf88f62b0 1972 #define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */
<> 128:9bcdf88f62b0 1973 #define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
<> 128:9bcdf88f62b0 1974 #define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */
<> 128:9bcdf88f62b0 1975 #define CMU_IFS_USHFRCORDY (0x1UL << 8) /**< USHFRCO Ready Interrupt Flag Set */
<> 128:9bcdf88f62b0 1976 #define _CMU_IFS_USHFRCORDY_SHIFT 8 /**< Shift value for CMU_USHFRCORDY */
<> 128:9bcdf88f62b0 1977 #define _CMU_IFS_USHFRCORDY_MASK 0x100UL /**< Bit mask for CMU_USHFRCORDY */
<> 128:9bcdf88f62b0 1978 #define _CMU_IFS_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
<> 128:9bcdf88f62b0 1979 #define CMU_IFS_USHFRCORDY_DEFAULT (_CMU_IFS_USHFRCORDY_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFS */
<> 128:9bcdf88f62b0 1980 #define CMU_IFS_USBCHFOSCSEL (0x1UL << 9) /**< USBC HF-oscillator Selected Interrupt Flag Set */
<> 128:9bcdf88f62b0 1981 #define _CMU_IFS_USBCHFOSCSEL_SHIFT 9 /**< Shift value for CMU_USBCHFOSCSEL */
<> 128:9bcdf88f62b0 1982 #define _CMU_IFS_USBCHFOSCSEL_MASK 0x200UL /**< Bit mask for CMU_USBCHFOSCSEL */
<> 128:9bcdf88f62b0 1983 #define _CMU_IFS_USBCHFOSCSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
<> 128:9bcdf88f62b0 1984 #define CMU_IFS_USBCHFOSCSEL_DEFAULT (_CMU_IFS_USBCHFOSCSEL_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFS */
<> 128:9bcdf88f62b0 1985
<> 128:9bcdf88f62b0 1986 /* Bit fields for CMU IFC */
<> 128:9bcdf88f62b0 1987 #define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */
<> 128:9bcdf88f62b0 1988 #define _CMU_IFC_MASK 0x0000037FUL /**< Mask for CMU_IFC */
<> 128:9bcdf88f62b0 1989 #define CMU_IFC_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Clear */
<> 128:9bcdf88f62b0 1990 #define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */
<> 128:9bcdf88f62b0 1991 #define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */
<> 128:9bcdf88f62b0 1992 #define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
<> 128:9bcdf88f62b0 1993 #define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */
<> 128:9bcdf88f62b0 1994 #define CMU_IFC_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Clear */
<> 128:9bcdf88f62b0 1995 #define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */
<> 128:9bcdf88f62b0 1996 #define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */
<> 128:9bcdf88f62b0 1997 #define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
<> 128:9bcdf88f62b0 1998 #define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */
<> 128:9bcdf88f62b0 1999 #define CMU_IFC_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Clear */
<> 128:9bcdf88f62b0 2000 #define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */
<> 128:9bcdf88f62b0 2001 #define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */
<> 128:9bcdf88f62b0 2002 #define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
<> 128:9bcdf88f62b0 2003 #define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */
<> 128:9bcdf88f62b0 2004 #define CMU_IFC_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Clear */
<> 128:9bcdf88f62b0 2005 #define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */
<> 128:9bcdf88f62b0 2006 #define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */
<> 128:9bcdf88f62b0 2007 #define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
<> 128:9bcdf88f62b0 2008 #define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */
<> 128:9bcdf88f62b0 2009 #define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Clear */
<> 128:9bcdf88f62b0 2010 #define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */
<> 128:9bcdf88f62b0 2011 #define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */
<> 128:9bcdf88f62b0 2012 #define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
<> 128:9bcdf88f62b0 2013 #define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */
<> 128:9bcdf88f62b0 2014 #define CMU_IFC_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Clear */
<> 128:9bcdf88f62b0 2015 #define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */
<> 128:9bcdf88f62b0 2016 #define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */
<> 128:9bcdf88f62b0 2017 #define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
<> 128:9bcdf88f62b0 2018 #define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */
<> 128:9bcdf88f62b0 2019 #define CMU_IFC_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Clear */
<> 128:9bcdf88f62b0 2020 #define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */
<> 128:9bcdf88f62b0 2021 #define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */
<> 128:9bcdf88f62b0 2022 #define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
<> 128:9bcdf88f62b0 2023 #define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */
<> 128:9bcdf88f62b0 2024 #define CMU_IFC_USHFRCORDY (0x1UL << 8) /**< USHFRCO Ready Interrupt Flag Clear */
<> 128:9bcdf88f62b0 2025 #define _CMU_IFC_USHFRCORDY_SHIFT 8 /**< Shift value for CMU_USHFRCORDY */
<> 128:9bcdf88f62b0 2026 #define _CMU_IFC_USHFRCORDY_MASK 0x100UL /**< Bit mask for CMU_USHFRCORDY */
<> 128:9bcdf88f62b0 2027 #define _CMU_IFC_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
<> 128:9bcdf88f62b0 2028 #define CMU_IFC_USHFRCORDY_DEFAULT (_CMU_IFC_USHFRCORDY_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IFC */
<> 128:9bcdf88f62b0 2029 #define CMU_IFC_USBCHFOSCSEL (0x1UL << 9) /**< USBC HF-oscillator Selected Interrupt Flag Clear */
<> 128:9bcdf88f62b0 2030 #define _CMU_IFC_USBCHFOSCSEL_SHIFT 9 /**< Shift value for CMU_USBCHFOSCSEL */
<> 128:9bcdf88f62b0 2031 #define _CMU_IFC_USBCHFOSCSEL_MASK 0x200UL /**< Bit mask for CMU_USBCHFOSCSEL */
<> 128:9bcdf88f62b0 2032 #define _CMU_IFC_USBCHFOSCSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
<> 128:9bcdf88f62b0 2033 #define CMU_IFC_USBCHFOSCSEL_DEFAULT (_CMU_IFC_USBCHFOSCSEL_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IFC */
<> 128:9bcdf88f62b0 2034
<> 128:9bcdf88f62b0 2035 /* Bit fields for CMU IEN */
<> 128:9bcdf88f62b0 2036 #define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */
<> 128:9bcdf88f62b0 2037 #define _CMU_IEN_MASK 0x0000037FUL /**< Mask for CMU_IEN */
<> 128:9bcdf88f62b0 2038 #define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Enable */
<> 128:9bcdf88f62b0 2039 #define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */
<> 128:9bcdf88f62b0 2040 #define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */
<> 128:9bcdf88f62b0 2041 #define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
<> 128:9bcdf88f62b0 2042 #define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */
<> 128:9bcdf88f62b0 2043 #define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Enable */
<> 128:9bcdf88f62b0 2044 #define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */
<> 128:9bcdf88f62b0 2045 #define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */
<> 128:9bcdf88f62b0 2046 #define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
<> 128:9bcdf88f62b0 2047 #define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */
<> 128:9bcdf88f62b0 2048 #define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Enable */
<> 128:9bcdf88f62b0 2049 #define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */
<> 128:9bcdf88f62b0 2050 #define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */
<> 128:9bcdf88f62b0 2051 #define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
<> 128:9bcdf88f62b0 2052 #define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */
<> 128:9bcdf88f62b0 2053 #define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Enable */
<> 128:9bcdf88f62b0 2054 #define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */
<> 128:9bcdf88f62b0 2055 #define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */
<> 128:9bcdf88f62b0 2056 #define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
<> 128:9bcdf88f62b0 2057 #define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */
<> 128:9bcdf88f62b0 2058 #define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Enable */
<> 128:9bcdf88f62b0 2059 #define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */
<> 128:9bcdf88f62b0 2060 #define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */
<> 128:9bcdf88f62b0 2061 #define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
<> 128:9bcdf88f62b0 2062 #define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */
<> 128:9bcdf88f62b0 2063 #define CMU_IEN_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Enable */
<> 128:9bcdf88f62b0 2064 #define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */
<> 128:9bcdf88f62b0 2065 #define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */
<> 128:9bcdf88f62b0 2066 #define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
<> 128:9bcdf88f62b0 2067 #define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */
<> 128:9bcdf88f62b0 2068 #define CMU_IEN_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Enable */
<> 128:9bcdf88f62b0 2069 #define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */
<> 128:9bcdf88f62b0 2070 #define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */
<> 128:9bcdf88f62b0 2071 #define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
<> 128:9bcdf88f62b0 2072 #define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */
<> 128:9bcdf88f62b0 2073 #define CMU_IEN_USHFRCORDY (0x1UL << 8) /**< USHFRCO Ready Interrupt Enable */
<> 128:9bcdf88f62b0 2074 #define _CMU_IEN_USHFRCORDY_SHIFT 8 /**< Shift value for CMU_USHFRCORDY */
<> 128:9bcdf88f62b0 2075 #define _CMU_IEN_USHFRCORDY_MASK 0x100UL /**< Bit mask for CMU_USHFRCORDY */
<> 128:9bcdf88f62b0 2076 #define _CMU_IEN_USHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
<> 128:9bcdf88f62b0 2077 #define CMU_IEN_USHFRCORDY_DEFAULT (_CMU_IEN_USHFRCORDY_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_IEN */
<> 128:9bcdf88f62b0 2078 #define CMU_IEN_USBCHFOSCSEL (0x1UL << 9) /**< USBC HF-oscillator Selected Interrupt Flag Clear */
<> 128:9bcdf88f62b0 2079 #define _CMU_IEN_USBCHFOSCSEL_SHIFT 9 /**< Shift value for CMU_USBCHFOSCSEL */
<> 128:9bcdf88f62b0 2080 #define _CMU_IEN_USBCHFOSCSEL_MASK 0x200UL /**< Bit mask for CMU_USBCHFOSCSEL */
<> 128:9bcdf88f62b0 2081 #define _CMU_IEN_USBCHFOSCSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
<> 128:9bcdf88f62b0 2082 #define CMU_IEN_USBCHFOSCSEL_DEFAULT (_CMU_IEN_USBCHFOSCSEL_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_IEN */
<> 128:9bcdf88f62b0 2083
<> 128:9bcdf88f62b0 2084 /* Bit fields for CMU HFCORECLKEN0 */
<> 128:9bcdf88f62b0 2085 #define _CMU_HFCORECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKEN0 */
<> 128:9bcdf88f62b0 2086 #define _CMU_HFCORECLKEN0_MASK 0x0000001EUL /**< Mask for CMU_HFCORECLKEN0 */
<> 128:9bcdf88f62b0 2087 #define CMU_HFCORECLKEN0_DMA (0x1UL << 1) /**< Direct Memory Access Controller Clock Enable */
<> 128:9bcdf88f62b0 2088 #define _CMU_HFCORECLKEN0_DMA_SHIFT 1 /**< Shift value for CMU_DMA */
<> 128:9bcdf88f62b0 2089 #define _CMU_HFCORECLKEN0_DMA_MASK 0x2UL /**< Bit mask for CMU_DMA */
<> 128:9bcdf88f62b0 2090 #define _CMU_HFCORECLKEN0_DMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */
<> 128:9bcdf88f62b0 2091 #define CMU_HFCORECLKEN0_DMA_DEFAULT (_CMU_HFCORECLKEN0_DMA_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */
<> 128:9bcdf88f62b0 2092 #define CMU_HFCORECLKEN0_LE (0x1UL << 2) /**< Low Energy Peripheral Interface Clock Enable */
<> 128:9bcdf88f62b0 2093 #define _CMU_HFCORECLKEN0_LE_SHIFT 2 /**< Shift value for CMU_LE */
<> 128:9bcdf88f62b0 2094 #define _CMU_HFCORECLKEN0_LE_MASK 0x4UL /**< Bit mask for CMU_LE */
<> 128:9bcdf88f62b0 2095 #define _CMU_HFCORECLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */
<> 128:9bcdf88f62b0 2096 #define CMU_HFCORECLKEN0_LE_DEFAULT (_CMU_HFCORECLKEN0_LE_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */
<> 128:9bcdf88f62b0 2097 #define CMU_HFCORECLKEN0_USBC (0x1UL << 3) /**< Universal Serial Bus Interface Core Clock Enable */
<> 128:9bcdf88f62b0 2098 #define _CMU_HFCORECLKEN0_USBC_SHIFT 3 /**< Shift value for CMU_USBC */
<> 128:9bcdf88f62b0 2099 #define _CMU_HFCORECLKEN0_USBC_MASK 0x8UL /**< Bit mask for CMU_USBC */
<> 128:9bcdf88f62b0 2100 #define _CMU_HFCORECLKEN0_USBC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */
<> 128:9bcdf88f62b0 2101 #define CMU_HFCORECLKEN0_USBC_DEFAULT (_CMU_HFCORECLKEN0_USBC_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */
<> 128:9bcdf88f62b0 2102 #define CMU_HFCORECLKEN0_USB (0x1UL << 4) /**< Universal Serial Bus Interface Clock Enable */
<> 128:9bcdf88f62b0 2103 #define _CMU_HFCORECLKEN0_USB_SHIFT 4 /**< Shift value for CMU_USB */
<> 128:9bcdf88f62b0 2104 #define _CMU_HFCORECLKEN0_USB_MASK 0x10UL /**< Bit mask for CMU_USB */
<> 128:9bcdf88f62b0 2105 #define _CMU_HFCORECLKEN0_USB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */
<> 128:9bcdf88f62b0 2106 #define CMU_HFCORECLKEN0_USB_DEFAULT (_CMU_HFCORECLKEN0_USB_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */
<> 128:9bcdf88f62b0 2107
<> 128:9bcdf88f62b0 2108 /* Bit fields for CMU HFPERCLKEN0 */
<> 128:9bcdf88f62b0 2109 #define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */
<> 128:9bcdf88f62b0 2110 #define _CMU_HFPERCLKEN0_MASK 0x00000B7FUL /**< Mask for CMU_HFPERCLKEN0 */
<> 128:9bcdf88f62b0 2111 #define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 0) /**< Timer 0 Clock Enable */
<> 128:9bcdf88f62b0 2112 #define _CMU_HFPERCLKEN0_TIMER0_SHIFT 0 /**< Shift value for CMU_TIMER0 */
<> 128:9bcdf88f62b0 2113 #define _CMU_HFPERCLKEN0_TIMER0_MASK 0x1UL /**< Bit mask for CMU_TIMER0 */
<> 128:9bcdf88f62b0 2114 #define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 128:9bcdf88f62b0 2115 #define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 128:9bcdf88f62b0 2116 #define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 1) /**< Timer 1 Clock Enable */
<> 128:9bcdf88f62b0 2117 #define _CMU_HFPERCLKEN0_TIMER1_SHIFT 1 /**< Shift value for CMU_TIMER1 */
<> 128:9bcdf88f62b0 2118 #define _CMU_HFPERCLKEN0_TIMER1_MASK 0x2UL /**< Bit mask for CMU_TIMER1 */
<> 128:9bcdf88f62b0 2119 #define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 128:9bcdf88f62b0 2120 #define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 128:9bcdf88f62b0 2121 #define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 2) /**< Timer 2 Clock Enable */
<> 128:9bcdf88f62b0 2122 #define _CMU_HFPERCLKEN0_TIMER2_SHIFT 2 /**< Shift value for CMU_TIMER2 */
<> 128:9bcdf88f62b0 2123 #define _CMU_HFPERCLKEN0_TIMER2_MASK 0x4UL /**< Bit mask for CMU_TIMER2 */
<> 128:9bcdf88f62b0 2124 #define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 128:9bcdf88f62b0 2125 #define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 128:9bcdf88f62b0 2126 #define CMU_HFPERCLKEN0_USART0 (0x1UL << 3) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */
<> 128:9bcdf88f62b0 2127 #define _CMU_HFPERCLKEN0_USART0_SHIFT 3 /**< Shift value for CMU_USART0 */
<> 128:9bcdf88f62b0 2128 #define _CMU_HFPERCLKEN0_USART0_MASK 0x8UL /**< Bit mask for CMU_USART0 */
<> 128:9bcdf88f62b0 2129 #define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 128:9bcdf88f62b0 2130 #define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 128:9bcdf88f62b0 2131 #define CMU_HFPERCLKEN0_USART1 (0x1UL << 4) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */
<> 128:9bcdf88f62b0 2132 #define _CMU_HFPERCLKEN0_USART1_SHIFT 4 /**< Shift value for CMU_USART1 */
<> 128:9bcdf88f62b0 2133 #define _CMU_HFPERCLKEN0_USART1_MASK 0x10UL /**< Bit mask for CMU_USART1 */
<> 128:9bcdf88f62b0 2134 #define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 128:9bcdf88f62b0 2135 #define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 128:9bcdf88f62b0 2136 #define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 5) /**< Analog Comparator 0 Clock Enable */
<> 128:9bcdf88f62b0 2137 #define _CMU_HFPERCLKEN0_ACMP0_SHIFT 5 /**< Shift value for CMU_ACMP0 */
<> 128:9bcdf88f62b0 2138 #define _CMU_HFPERCLKEN0_ACMP0_MASK 0x20UL /**< Bit mask for CMU_ACMP0 */
<> 128:9bcdf88f62b0 2139 #define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 128:9bcdf88f62b0 2140 #define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 128:9bcdf88f62b0 2141 #define CMU_HFPERCLKEN0_PRS (0x1UL << 6) /**< Peripheral Reflex System Clock Enable */
<> 128:9bcdf88f62b0 2142 #define _CMU_HFPERCLKEN0_PRS_SHIFT 6 /**< Shift value for CMU_PRS */
<> 128:9bcdf88f62b0 2143 #define _CMU_HFPERCLKEN0_PRS_MASK 0x40UL /**< Bit mask for CMU_PRS */
<> 128:9bcdf88f62b0 2144 #define _CMU_HFPERCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 128:9bcdf88f62b0 2145 #define CMU_HFPERCLKEN0_PRS_DEFAULT (_CMU_HFPERCLKEN0_PRS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 128:9bcdf88f62b0 2146 #define CMU_HFPERCLKEN0_GPIO (0x1UL << 8) /**< General purpose Input/Output Clock Enable */
<> 128:9bcdf88f62b0 2147 #define _CMU_HFPERCLKEN0_GPIO_SHIFT 8 /**< Shift value for CMU_GPIO */
<> 128:9bcdf88f62b0 2148 #define _CMU_HFPERCLKEN0_GPIO_MASK 0x100UL /**< Bit mask for CMU_GPIO */
<> 128:9bcdf88f62b0 2149 #define _CMU_HFPERCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 128:9bcdf88f62b0 2150 #define CMU_HFPERCLKEN0_GPIO_DEFAULT (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 128:9bcdf88f62b0 2151 #define CMU_HFPERCLKEN0_VCMP (0x1UL << 9) /**< Voltage Comparator Clock Enable */
<> 128:9bcdf88f62b0 2152 #define _CMU_HFPERCLKEN0_VCMP_SHIFT 9 /**< Shift value for CMU_VCMP */
<> 128:9bcdf88f62b0 2153 #define _CMU_HFPERCLKEN0_VCMP_MASK 0x200UL /**< Bit mask for CMU_VCMP */
<> 128:9bcdf88f62b0 2154 #define _CMU_HFPERCLKEN0_VCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 128:9bcdf88f62b0 2155 #define CMU_HFPERCLKEN0_VCMP_DEFAULT (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 128:9bcdf88f62b0 2156 #define CMU_HFPERCLKEN0_I2C0 (0x1UL << 11) /**< I2C 0 Clock Enable */
<> 128:9bcdf88f62b0 2157 #define _CMU_HFPERCLKEN0_I2C0_SHIFT 11 /**< Shift value for CMU_I2C0 */
<> 128:9bcdf88f62b0 2158 #define _CMU_HFPERCLKEN0_I2C0_MASK 0x800UL /**< Bit mask for CMU_I2C0 */
<> 128:9bcdf88f62b0 2159 #define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
<> 128:9bcdf88f62b0 2160 #define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
<> 128:9bcdf88f62b0 2161
<> 128:9bcdf88f62b0 2162 /* Bit fields for CMU SYNCBUSY */
<> 128:9bcdf88f62b0 2163 #define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */
<> 128:9bcdf88f62b0 2164 #define _CMU_SYNCBUSY_MASK 0x00000155UL /**< Mask for CMU_SYNCBUSY */
<> 128:9bcdf88f62b0 2165 #define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency A Clock Enable 0 Busy */
<> 128:9bcdf88f62b0 2166 #define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */
<> 128:9bcdf88f62b0 2167 #define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */
<> 128:9bcdf88f62b0 2168 #define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
<> 128:9bcdf88f62b0 2169 #define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
<> 128:9bcdf88f62b0 2170 #define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency A Prescaler 0 Busy */
<> 128:9bcdf88f62b0 2171 #define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 2172 #define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 2173 #define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
<> 128:9bcdf88f62b0 2174 #define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
<> 128:9bcdf88f62b0 2175 #define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */
<> 128:9bcdf88f62b0 2176 #define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */
<> 128:9bcdf88f62b0 2177 #define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */
<> 128:9bcdf88f62b0 2178 #define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
<> 128:9bcdf88f62b0 2179 #define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
<> 128:9bcdf88f62b0 2180 #define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */
<> 128:9bcdf88f62b0 2181 #define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */
<> 128:9bcdf88f62b0 2182 #define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */
<> 128:9bcdf88f62b0 2183 #define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
<> 128:9bcdf88f62b0 2184 #define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
<> 128:9bcdf88f62b0 2185 #define CMU_SYNCBUSY_LFCCLKEN0 (0x1UL << 8) /**< Low Frequency C Clock Enable 0 Busy */
<> 128:9bcdf88f62b0 2186 #define _CMU_SYNCBUSY_LFCCLKEN0_SHIFT 8 /**< Shift value for CMU_LFCCLKEN0 */
<> 128:9bcdf88f62b0 2187 #define _CMU_SYNCBUSY_LFCCLKEN0_MASK 0x100UL /**< Bit mask for CMU_LFCCLKEN0 */
<> 128:9bcdf88f62b0 2188 #define _CMU_SYNCBUSY_LFCCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
<> 128:9bcdf88f62b0 2189 #define CMU_SYNCBUSY_LFCCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFCCLKEN0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
<> 128:9bcdf88f62b0 2190
<> 128:9bcdf88f62b0 2191 /* Bit fields for CMU FREEZE */
<> 128:9bcdf88f62b0 2192 #define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */
<> 128:9bcdf88f62b0 2193 #define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */
<> 128:9bcdf88f62b0 2194 #define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */
<> 128:9bcdf88f62b0 2195 #define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */
<> 128:9bcdf88f62b0 2196 #define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */
<> 128:9bcdf88f62b0 2197 #define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */
<> 128:9bcdf88f62b0 2198 #define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */
<> 128:9bcdf88f62b0 2199 #define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */
<> 128:9bcdf88f62b0 2200 #define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */
<> 128:9bcdf88f62b0 2201 #define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */
<> 128:9bcdf88f62b0 2202 #define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */
<> 128:9bcdf88f62b0 2203
<> 128:9bcdf88f62b0 2204 /* Bit fields for CMU LFACLKEN0 */
<> 128:9bcdf88f62b0 2205 #define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */
<> 128:9bcdf88f62b0 2206 #define _CMU_LFACLKEN0_MASK 0x00000001UL /**< Mask for CMU_LFACLKEN0 */
<> 128:9bcdf88f62b0 2207 #define CMU_LFACLKEN0_RTC (0x1UL << 0) /**< Real-Time Counter Clock Enable */
<> 128:9bcdf88f62b0 2208 #define _CMU_LFACLKEN0_RTC_SHIFT 0 /**< Shift value for CMU_RTC */
<> 128:9bcdf88f62b0 2209 #define _CMU_LFACLKEN0_RTC_MASK 0x1UL /**< Bit mask for CMU_RTC */
<> 128:9bcdf88f62b0 2210 #define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */
<> 128:9bcdf88f62b0 2211 #define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */
<> 128:9bcdf88f62b0 2212
<> 128:9bcdf88f62b0 2213 /* Bit fields for CMU LFBCLKEN0 */
<> 128:9bcdf88f62b0 2214 #define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */
<> 128:9bcdf88f62b0 2215 #define _CMU_LFBCLKEN0_MASK 0x00000001UL /**< Mask for CMU_LFBCLKEN0 */
<> 128:9bcdf88f62b0 2216 #define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */
<> 128:9bcdf88f62b0 2217 #define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */
<> 128:9bcdf88f62b0 2218 #define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */
<> 128:9bcdf88f62b0 2219 #define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */
<> 128:9bcdf88f62b0 2220 #define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */
<> 128:9bcdf88f62b0 2221
<> 128:9bcdf88f62b0 2222 /* Bit fields for CMU LFCCLKEN0 */
<> 128:9bcdf88f62b0 2223 #define _CMU_LFCCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFCCLKEN0 */
<> 128:9bcdf88f62b0 2224 #define _CMU_LFCCLKEN0_MASK 0x00000001UL /**< Mask for CMU_LFCCLKEN0 */
<> 128:9bcdf88f62b0 2225 #define CMU_LFCCLKEN0_USBLE (0x1UL << 0) /**< Universal Serial Bus Low Energy Clock Clock Enable */
<> 128:9bcdf88f62b0 2226 #define _CMU_LFCCLKEN0_USBLE_SHIFT 0 /**< Shift value for CMU_USBLE */
<> 128:9bcdf88f62b0 2227 #define _CMU_LFCCLKEN0_USBLE_MASK 0x1UL /**< Bit mask for CMU_USBLE */
<> 128:9bcdf88f62b0 2228 #define _CMU_LFCCLKEN0_USBLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCCLKEN0 */
<> 128:9bcdf88f62b0 2229 #define CMU_LFCCLKEN0_USBLE_DEFAULT (_CMU_LFCCLKEN0_USBLE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCCLKEN0 */
<> 128:9bcdf88f62b0 2230
<> 128:9bcdf88f62b0 2231 /* Bit fields for CMU LFAPRESC0 */
<> 128:9bcdf88f62b0 2232 #define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 2233 #define _CMU_LFAPRESC0_MASK 0x0000000FUL /**< Mask for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 2234 #define _CMU_LFAPRESC0_RTC_SHIFT 0 /**< Shift value for CMU_RTC */
<> 128:9bcdf88f62b0 2235 #define _CMU_LFAPRESC0_RTC_MASK 0xFUL /**< Bit mask for CMU_RTC */
<> 128:9bcdf88f62b0 2236 #define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 2237 #define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 2238 #define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 2239 #define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 2240 #define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 2241 #define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 2242 #define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 2243 #define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 2244 #define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 2245 #define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 2246 #define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 2247 #define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 2248 #define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 2249 #define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 2250 #define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 2251 #define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 2252 #define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 2253 #define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 2254 #define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 2255 #define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 2256 #define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 0) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 2257 #define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 0) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 2258 #define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 0) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 2259 #define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 0) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 2260 #define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 0) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 2261 #define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 0) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 2262 #define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 0) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 2263 #define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 0) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 2264 #define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 0) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 2265 #define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 0) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 2266 #define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 0) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 2267 #define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 0) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */
<> 128:9bcdf88f62b0 2268
<> 128:9bcdf88f62b0 2269 /* Bit fields for CMU LFBPRESC0 */
<> 128:9bcdf88f62b0 2270 #define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */
<> 128:9bcdf88f62b0 2271 #define _CMU_LFBPRESC0_MASK 0x00000003UL /**< Mask for CMU_LFBPRESC0 */
<> 128:9bcdf88f62b0 2272 #define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */
<> 128:9bcdf88f62b0 2273 #define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */
<> 128:9bcdf88f62b0 2274 #define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */
<> 128:9bcdf88f62b0 2275 #define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */
<> 128:9bcdf88f62b0 2276 #define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */
<> 128:9bcdf88f62b0 2277 #define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */
<> 128:9bcdf88f62b0 2278 #define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */
<> 128:9bcdf88f62b0 2279 #define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */
<> 128:9bcdf88f62b0 2280 #define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */
<> 128:9bcdf88f62b0 2281 #define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */
<> 128:9bcdf88f62b0 2282
<> 128:9bcdf88f62b0 2283 /* Bit fields for CMU PCNTCTRL */
<> 128:9bcdf88f62b0 2284 #define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */
<> 128:9bcdf88f62b0 2285 #define _CMU_PCNTCTRL_MASK 0x00000003UL /**< Mask for CMU_PCNTCTRL */
<> 128:9bcdf88f62b0 2286 #define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */
<> 128:9bcdf88f62b0 2287 #define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */
<> 128:9bcdf88f62b0 2288 #define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */
<> 128:9bcdf88f62b0 2289 #define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */
<> 128:9bcdf88f62b0 2290 #define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
<> 128:9bcdf88f62b0 2291 #define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */
<> 128:9bcdf88f62b0 2292 #define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */
<> 128:9bcdf88f62b0 2293 #define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */
<> 128:9bcdf88f62b0 2294 #define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */
<> 128:9bcdf88f62b0 2295 #define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */
<> 128:9bcdf88f62b0 2296 #define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */
<> 128:9bcdf88f62b0 2297 #define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
<> 128:9bcdf88f62b0 2298 #define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */
<> 128:9bcdf88f62b0 2299 #define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */
<> 128:9bcdf88f62b0 2300
<> 128:9bcdf88f62b0 2301 /* Bit fields for CMU ROUTE */
<> 128:9bcdf88f62b0 2302 #define _CMU_ROUTE_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTE */
<> 128:9bcdf88f62b0 2303 #define _CMU_ROUTE_MASK 0x0000001FUL /**< Mask for CMU_ROUTE */
<> 128:9bcdf88f62b0 2304 #define CMU_ROUTE_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */
<> 128:9bcdf88f62b0 2305 #define _CMU_ROUTE_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */
<> 128:9bcdf88f62b0 2306 #define _CMU_ROUTE_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */
<> 128:9bcdf88f62b0 2307 #define _CMU_ROUTE_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */
<> 128:9bcdf88f62b0 2308 #define CMU_ROUTE_CLKOUT0PEN_DEFAULT (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTE */
<> 128:9bcdf88f62b0 2309 #define CMU_ROUTE_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */
<> 128:9bcdf88f62b0 2310 #define _CMU_ROUTE_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */
<> 128:9bcdf88f62b0 2311 #define _CMU_ROUTE_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */
<> 128:9bcdf88f62b0 2312 #define _CMU_ROUTE_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */
<> 128:9bcdf88f62b0 2313 #define CMU_ROUTE_CLKOUT1PEN_DEFAULT (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTE */
<> 128:9bcdf88f62b0 2314 #define _CMU_ROUTE_LOCATION_SHIFT 2 /**< Shift value for CMU_LOCATION */
<> 128:9bcdf88f62b0 2315 #define _CMU_ROUTE_LOCATION_MASK 0x1CUL /**< Bit mask for CMU_LOCATION */
<> 128:9bcdf88f62b0 2316 #define _CMU_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTE */
<> 128:9bcdf88f62b0 2317 #define _CMU_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */
<> 128:9bcdf88f62b0 2318 #define _CMU_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTE */
<> 128:9bcdf88f62b0 2319 #define _CMU_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTE */
<> 128:9bcdf88f62b0 2320 #define _CMU_ROUTE_LOCATION_LOC3 0x00000003UL /**< Mode LOC3 for CMU_ROUTE */
<> 128:9bcdf88f62b0 2321 #define CMU_ROUTE_LOCATION_LOC0 (_CMU_ROUTE_LOCATION_LOC0 << 2) /**< Shifted mode LOC0 for CMU_ROUTE */
<> 128:9bcdf88f62b0 2322 #define CMU_ROUTE_LOCATION_DEFAULT (_CMU_ROUTE_LOCATION_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTE */
<> 128:9bcdf88f62b0 2323 #define CMU_ROUTE_LOCATION_LOC1 (_CMU_ROUTE_LOCATION_LOC1 << 2) /**< Shifted mode LOC1 for CMU_ROUTE */
<> 128:9bcdf88f62b0 2324 #define CMU_ROUTE_LOCATION_LOC2 (_CMU_ROUTE_LOCATION_LOC2 << 2) /**< Shifted mode LOC2 for CMU_ROUTE */
<> 128:9bcdf88f62b0 2325 #define CMU_ROUTE_LOCATION_LOC3 (_CMU_ROUTE_LOCATION_LOC3 << 2) /**< Shifted mode LOC3 for CMU_ROUTE */
<> 128:9bcdf88f62b0 2326
<> 128:9bcdf88f62b0 2327 /* Bit fields for CMU LOCK */
<> 128:9bcdf88f62b0 2328 #define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */
<> 128:9bcdf88f62b0 2329 #define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */
<> 128:9bcdf88f62b0 2330 #define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */
<> 128:9bcdf88f62b0 2331 #define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */
<> 128:9bcdf88f62b0 2332 #define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */
<> 128:9bcdf88f62b0 2333 #define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */
<> 128:9bcdf88f62b0 2334 #define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */
<> 128:9bcdf88f62b0 2335 #define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */
<> 128:9bcdf88f62b0 2336 #define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */
<> 128:9bcdf88f62b0 2337 #define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */
<> 128:9bcdf88f62b0 2338 #define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */
<> 128:9bcdf88f62b0 2339 #define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */
<> 128:9bcdf88f62b0 2340 #define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */
<> 128:9bcdf88f62b0 2341 #define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */
<> 128:9bcdf88f62b0 2342
<> 128:9bcdf88f62b0 2343 /* Bit fields for CMU USBCRCTRL */
<> 128:9bcdf88f62b0 2344 #define _CMU_USBCRCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_USBCRCTRL */
<> 128:9bcdf88f62b0 2345 #define _CMU_USBCRCTRL_MASK 0x00000003UL /**< Mask for CMU_USBCRCTRL */
<> 128:9bcdf88f62b0 2346 #define CMU_USBCRCTRL_EN (0x1UL << 0) /**< Clock Recovery Enable */
<> 128:9bcdf88f62b0 2347 #define _CMU_USBCRCTRL_EN_SHIFT 0 /**< Shift value for CMU_EN */
<> 128:9bcdf88f62b0 2348 #define _CMU_USBCRCTRL_EN_MASK 0x1UL /**< Bit mask for CMU_EN */
<> 128:9bcdf88f62b0 2349 #define _CMU_USBCRCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USBCRCTRL */
<> 128:9bcdf88f62b0 2350 #define CMU_USBCRCTRL_EN_DEFAULT (_CMU_USBCRCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_USBCRCTRL */
<> 128:9bcdf88f62b0 2351 #define CMU_USBCRCTRL_LSMODE (0x1UL << 1) /**< Low Speed Clock Recovery Mode */
<> 128:9bcdf88f62b0 2352 #define _CMU_USBCRCTRL_LSMODE_SHIFT 1 /**< Shift value for CMU_LSMODE */
<> 128:9bcdf88f62b0 2353 #define _CMU_USBCRCTRL_LSMODE_MASK 0x2UL /**< Bit mask for CMU_LSMODE */
<> 128:9bcdf88f62b0 2354 #define _CMU_USBCRCTRL_LSMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USBCRCTRL */
<> 128:9bcdf88f62b0 2355 #define CMU_USBCRCTRL_LSMODE_DEFAULT (_CMU_USBCRCTRL_LSMODE_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_USBCRCTRL */
<> 128:9bcdf88f62b0 2356
<> 128:9bcdf88f62b0 2357 /* Bit fields for CMU USHFRCOCTRL */
<> 128:9bcdf88f62b0 2358 #define _CMU_USHFRCOCTRL_RESETVALUE 0x000FF040UL /**< Default value for CMU_USHFRCOCTRL */
<> 128:9bcdf88f62b0 2359 #define _CMU_USHFRCOCTRL_MASK 0x000FF37FUL /**< Mask for CMU_USHFRCOCTRL */
<> 128:9bcdf88f62b0 2360 #define _CMU_USHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */
<> 128:9bcdf88f62b0 2361 #define _CMU_USHFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */
<> 128:9bcdf88f62b0 2362 #define _CMU_USHFRCOCTRL_TUNING_DEFAULT 0x00000040UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */
<> 128:9bcdf88f62b0 2363 #define CMU_USHFRCOCTRL_TUNING_DEFAULT (_CMU_USHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */
<> 128:9bcdf88f62b0 2364 #define CMU_USHFRCOCTRL_DITHEN (0x1UL << 8) /**< USHFRCO dither enable */
<> 128:9bcdf88f62b0 2365 #define _CMU_USHFRCOCTRL_DITHEN_SHIFT 8 /**< Shift value for CMU_DITHEN */
<> 128:9bcdf88f62b0 2366 #define _CMU_USHFRCOCTRL_DITHEN_MASK 0x100UL /**< Bit mask for CMU_DITHEN */
<> 128:9bcdf88f62b0 2367 #define _CMU_USHFRCOCTRL_DITHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */
<> 128:9bcdf88f62b0 2368 #define CMU_USHFRCOCTRL_DITHEN_DEFAULT (_CMU_USHFRCOCTRL_DITHEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */
<> 128:9bcdf88f62b0 2369 #define CMU_USHFRCOCTRL_SUSPEND (0x1UL << 9) /**< USHFRCO suspend */
<> 128:9bcdf88f62b0 2370 #define _CMU_USHFRCOCTRL_SUSPEND_SHIFT 9 /**< Shift value for CMU_SUSPEND */
<> 128:9bcdf88f62b0 2371 #define _CMU_USHFRCOCTRL_SUSPEND_MASK 0x200UL /**< Bit mask for CMU_SUSPEND */
<> 128:9bcdf88f62b0 2372 #define _CMU_USHFRCOCTRL_SUSPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCTRL */
<> 128:9bcdf88f62b0 2373 #define CMU_USHFRCOCTRL_SUSPEND_DEFAULT (_CMU_USHFRCOCTRL_SUSPEND_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */
<> 128:9bcdf88f62b0 2374 #define _CMU_USHFRCOCTRL_TIMEOUT_SHIFT 12 /**< Shift value for CMU_TIMEOUT */
<> 128:9bcdf88f62b0 2375 #define _CMU_USHFRCOCTRL_TIMEOUT_MASK 0xFF000UL /**< Bit mask for CMU_TIMEOUT */
<> 128:9bcdf88f62b0 2376 #define _CMU_USHFRCOCTRL_TIMEOUT_DEFAULT 0x000000FFUL /**< Mode DEFAULT for CMU_USHFRCOCTRL */
<> 128:9bcdf88f62b0 2377 #define CMU_USHFRCOCTRL_TIMEOUT_DEFAULT (_CMU_USHFRCOCTRL_TIMEOUT_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_USHFRCOCTRL */
<> 128:9bcdf88f62b0 2378
<> 128:9bcdf88f62b0 2379 /* Bit fields for CMU USHFRCOTUNE */
<> 128:9bcdf88f62b0 2380 #define _CMU_USHFRCOTUNE_RESETVALUE 0x00000020UL /**< Default value for CMU_USHFRCOTUNE */
<> 128:9bcdf88f62b0 2381 #define _CMU_USHFRCOTUNE_MASK 0x0000003FUL /**< Mask for CMU_USHFRCOTUNE */
<> 128:9bcdf88f62b0 2382 #define _CMU_USHFRCOTUNE_FINETUNING_SHIFT 0 /**< Shift value for CMU_FINETUNING */
<> 128:9bcdf88f62b0 2383 #define _CMU_USHFRCOTUNE_FINETUNING_MASK 0x3FUL /**< Bit mask for CMU_FINETUNING */
<> 128:9bcdf88f62b0 2384 #define _CMU_USHFRCOTUNE_FINETUNING_DEFAULT 0x00000020UL /**< Mode DEFAULT for CMU_USHFRCOTUNE */
<> 128:9bcdf88f62b0 2385 #define CMU_USHFRCOTUNE_FINETUNING_DEFAULT (_CMU_USHFRCOTUNE_FINETUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_USHFRCOTUNE */
<> 128:9bcdf88f62b0 2386
<> 128:9bcdf88f62b0 2387 /* Bit fields for CMU USHFRCOCONF */
<> 128:9bcdf88f62b0 2388 #define _CMU_USHFRCOCONF_RESETVALUE 0x00000001UL /**< Default value for CMU_USHFRCOCONF */
<> 128:9bcdf88f62b0 2389 #define _CMU_USHFRCOCONF_MASK 0x00000017UL /**< Mask for CMU_USHFRCOCONF */
<> 128:9bcdf88f62b0 2390 #define _CMU_USHFRCOCONF_BAND_SHIFT 0 /**< Shift value for CMU_BAND */
<> 128:9bcdf88f62b0 2391 #define _CMU_USHFRCOCONF_BAND_MASK 0x7UL /**< Bit mask for CMU_BAND */
<> 128:9bcdf88f62b0 2392 #define _CMU_USHFRCOCONF_BAND_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_USHFRCOCONF */
<> 128:9bcdf88f62b0 2393 #define _CMU_USHFRCOCONF_BAND_48MHZ 0x00000001UL /**< Mode 48MHZ for CMU_USHFRCOCONF */
<> 128:9bcdf88f62b0 2394 #define _CMU_USHFRCOCONF_BAND_24MHZ 0x00000003UL /**< Mode 24MHZ for CMU_USHFRCOCONF */
<> 128:9bcdf88f62b0 2395 #define CMU_USHFRCOCONF_BAND_DEFAULT (_CMU_USHFRCOCONF_BAND_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_USHFRCOCONF */
<> 128:9bcdf88f62b0 2396 #define CMU_USHFRCOCONF_BAND_48MHZ (_CMU_USHFRCOCONF_BAND_48MHZ << 0) /**< Shifted mode 48MHZ for CMU_USHFRCOCONF */
<> 128:9bcdf88f62b0 2397 #define CMU_USHFRCOCONF_BAND_24MHZ (_CMU_USHFRCOCONF_BAND_24MHZ << 0) /**< Shifted mode 24MHZ for CMU_USHFRCOCONF */
<> 128:9bcdf88f62b0 2398 #define CMU_USHFRCOCONF_USHFRCODIV2DIS (0x1UL << 4) /**< USHFRCO divider for HFCLK disable */
<> 128:9bcdf88f62b0 2399 #define _CMU_USHFRCOCONF_USHFRCODIV2DIS_SHIFT 4 /**< Shift value for CMU_USHFRCODIV2DIS */
<> 128:9bcdf88f62b0 2400 #define _CMU_USHFRCOCONF_USHFRCODIV2DIS_MASK 0x10UL /**< Bit mask for CMU_USHFRCODIV2DIS */
<> 128:9bcdf88f62b0 2401 #define _CMU_USHFRCOCONF_USHFRCODIV2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_USHFRCOCONF */
<> 128:9bcdf88f62b0 2402 #define CMU_USHFRCOCONF_USHFRCODIV2DIS_DEFAULT (_CMU_USHFRCOCONF_USHFRCODIV2DIS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_USHFRCOCONF */
<> 128:9bcdf88f62b0 2403
<> 128:9bcdf88f62b0 2404 /** @} End of group EFM32HG308F64_CMU */
<> 128:9bcdf88f62b0 2405
<> 128:9bcdf88f62b0 2406 /**************************************************************************//**
<> 128:9bcdf88f62b0 2407 * @defgroup EFM32HG308F64_PRS_BitFields EFM32HG308F64_PRS Bit Fields
<> 128:9bcdf88f62b0 2408 * @{
<> 128:9bcdf88f62b0 2409 *****************************************************************************/
<> 128:9bcdf88f62b0 2410
<> 128:9bcdf88f62b0 2411 /* Bit fields for PRS SWPULSE */
<> 128:9bcdf88f62b0 2412 #define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */
<> 128:9bcdf88f62b0 2413 #define _PRS_SWPULSE_MASK 0x0000003FUL /**< Mask for PRS_SWPULSE */
<> 128:9bcdf88f62b0 2414 #define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */
<> 128:9bcdf88f62b0 2415 #define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */
<> 128:9bcdf88f62b0 2416 #define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */
<> 128:9bcdf88f62b0 2417 #define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
<> 128:9bcdf88f62b0 2418 #define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */
<> 128:9bcdf88f62b0 2419 #define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */
<> 128:9bcdf88f62b0 2420 #define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */
<> 128:9bcdf88f62b0 2421 #define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */
<> 128:9bcdf88f62b0 2422 #define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
<> 128:9bcdf88f62b0 2423 #define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */
<> 128:9bcdf88f62b0 2424 #define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */
<> 128:9bcdf88f62b0 2425 #define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */
<> 128:9bcdf88f62b0 2426 #define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */
<> 128:9bcdf88f62b0 2427 #define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
<> 128:9bcdf88f62b0 2428 #define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */
<> 128:9bcdf88f62b0 2429 #define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */
<> 128:9bcdf88f62b0 2430 #define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */
<> 128:9bcdf88f62b0 2431 #define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */
<> 128:9bcdf88f62b0 2432 #define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
<> 128:9bcdf88f62b0 2433 #define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */
<> 128:9bcdf88f62b0 2434 #define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */
<> 128:9bcdf88f62b0 2435 #define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */
<> 128:9bcdf88f62b0 2436 #define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */
<> 128:9bcdf88f62b0 2437 #define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
<> 128:9bcdf88f62b0 2438 #define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */
<> 128:9bcdf88f62b0 2439 #define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */
<> 128:9bcdf88f62b0 2440 #define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */
<> 128:9bcdf88f62b0 2441 #define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */
<> 128:9bcdf88f62b0 2442 #define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
<> 128:9bcdf88f62b0 2443 #define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */
<> 128:9bcdf88f62b0 2444
<> 128:9bcdf88f62b0 2445 /* Bit fields for PRS SWLEVEL */
<> 128:9bcdf88f62b0 2446 #define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */
<> 128:9bcdf88f62b0 2447 #define _PRS_SWLEVEL_MASK 0x0000003FUL /**< Mask for PRS_SWLEVEL */
<> 128:9bcdf88f62b0 2448 #define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */
<> 128:9bcdf88f62b0 2449 #define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */
<> 128:9bcdf88f62b0 2450 #define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */
<> 128:9bcdf88f62b0 2451 #define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
<> 128:9bcdf88f62b0 2452 #define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
<> 128:9bcdf88f62b0 2453 #define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */
<> 128:9bcdf88f62b0 2454 #define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */
<> 128:9bcdf88f62b0 2455 #define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */
<> 128:9bcdf88f62b0 2456 #define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
<> 128:9bcdf88f62b0 2457 #define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
<> 128:9bcdf88f62b0 2458 #define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */
<> 128:9bcdf88f62b0 2459 #define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */
<> 128:9bcdf88f62b0 2460 #define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */
<> 128:9bcdf88f62b0 2461 #define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
<> 128:9bcdf88f62b0 2462 #define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
<> 128:9bcdf88f62b0 2463 #define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */
<> 128:9bcdf88f62b0 2464 #define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */
<> 128:9bcdf88f62b0 2465 #define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */
<> 128:9bcdf88f62b0 2466 #define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
<> 128:9bcdf88f62b0 2467 #define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
<> 128:9bcdf88f62b0 2468 #define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */
<> 128:9bcdf88f62b0 2469 #define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */
<> 128:9bcdf88f62b0 2470 #define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */
<> 128:9bcdf88f62b0 2471 #define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
<> 128:9bcdf88f62b0 2472 #define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
<> 128:9bcdf88f62b0 2473 #define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */
<> 128:9bcdf88f62b0 2474 #define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */
<> 128:9bcdf88f62b0 2475 #define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */
<> 128:9bcdf88f62b0 2476 #define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
<> 128:9bcdf88f62b0 2477 #define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
<> 128:9bcdf88f62b0 2478
<> 128:9bcdf88f62b0 2479 /* Bit fields for PRS ROUTE */
<> 128:9bcdf88f62b0 2480 #define _PRS_ROUTE_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTE */
<> 128:9bcdf88f62b0 2481 #define _PRS_ROUTE_MASK 0x0000070FUL /**< Mask for PRS_ROUTE */
<> 128:9bcdf88f62b0 2482 #define PRS_ROUTE_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */
<> 128:9bcdf88f62b0 2483 #define _PRS_ROUTE_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */
<> 128:9bcdf88f62b0 2484 #define _PRS_ROUTE_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */
<> 128:9bcdf88f62b0 2485 #define _PRS_ROUTE_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */
<> 128:9bcdf88f62b0 2486 #define PRS_ROUTE_CH0PEN_DEFAULT (_PRS_ROUTE_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTE */
<> 128:9bcdf88f62b0 2487 #define PRS_ROUTE_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */
<> 128:9bcdf88f62b0 2488 #define _PRS_ROUTE_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */
<> 128:9bcdf88f62b0 2489 #define _PRS_ROUTE_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */
<> 128:9bcdf88f62b0 2490 #define _PRS_ROUTE_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */
<> 128:9bcdf88f62b0 2491 #define PRS_ROUTE_CH1PEN_DEFAULT (_PRS_ROUTE_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTE */
<> 128:9bcdf88f62b0 2492 #define PRS_ROUTE_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */
<> 128:9bcdf88f62b0 2493 #define _PRS_ROUTE_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */
<> 128:9bcdf88f62b0 2494 #define _PRS_ROUTE_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */
<> 128:9bcdf88f62b0 2495 #define _PRS_ROUTE_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */
<> 128:9bcdf88f62b0 2496 #define PRS_ROUTE_CH2PEN_DEFAULT (_PRS_ROUTE_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTE */
<> 128:9bcdf88f62b0 2497 #define PRS_ROUTE_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */
<> 128:9bcdf88f62b0 2498 #define _PRS_ROUTE_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */
<> 128:9bcdf88f62b0 2499 #define _PRS_ROUTE_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */
<> 128:9bcdf88f62b0 2500 #define _PRS_ROUTE_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */
<> 128:9bcdf88f62b0 2501 #define PRS_ROUTE_CH3PEN_DEFAULT (_PRS_ROUTE_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTE */
<> 128:9bcdf88f62b0 2502 #define _PRS_ROUTE_LOCATION_SHIFT 8 /**< Shift value for PRS_LOCATION */
<> 128:9bcdf88f62b0 2503 #define _PRS_ROUTE_LOCATION_MASK 0x700UL /**< Bit mask for PRS_LOCATION */
<> 128:9bcdf88f62b0 2504 #define _PRS_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTE */
<> 128:9bcdf88f62b0 2505 #define _PRS_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */
<> 128:9bcdf88f62b0 2506 #define _PRS_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTE */
<> 128:9bcdf88f62b0 2507 #define _PRS_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTE */
<> 128:9bcdf88f62b0 2508 #define _PRS_ROUTE_LOCATION_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTE */
<> 128:9bcdf88f62b0 2509 #define PRS_ROUTE_LOCATION_LOC0 (_PRS_ROUTE_LOCATION_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTE */
<> 128:9bcdf88f62b0 2510 #define PRS_ROUTE_LOCATION_DEFAULT (_PRS_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTE */
<> 128:9bcdf88f62b0 2511 #define PRS_ROUTE_LOCATION_LOC1 (_PRS_ROUTE_LOCATION_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTE */
<> 128:9bcdf88f62b0 2512 #define PRS_ROUTE_LOCATION_LOC2 (_PRS_ROUTE_LOCATION_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTE */
<> 128:9bcdf88f62b0 2513 #define PRS_ROUTE_LOCATION_LOC3 (_PRS_ROUTE_LOCATION_LOC3 << 8) /**< Shifted mode LOC3 for PRS_ROUTE */
<> 128:9bcdf88f62b0 2514
<> 128:9bcdf88f62b0 2515 /* Bit fields for PRS CH_CTRL */
<> 128:9bcdf88f62b0 2516 #define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2517 #define _PRS_CH_CTRL_MASK 0x133F0007UL /**< Mask for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2518 #define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */
<> 128:9bcdf88f62b0 2519 #define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */
<> 128:9bcdf88f62b0 2520 #define _PRS_CH_CTRL_SIGSEL_VCMPOUT 0x00000000UL /**< Mode VCMPOUT for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2521 #define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2522 #define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2523 #define _PRS_CH_CTRL_SIGSEL_USART1IRTX 0x00000000UL /**< Mode USART1IRTX for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2524 #define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2525 #define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2526 #define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2527 #define _PRS_CH_CTRL_SIGSEL_USBSOF 0x00000000UL /**< Mode USBSOF for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2528 #define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2529 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2530 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2531 #define _PRS_CH_CTRL_SIGSEL_PCNT0TCC 0x00000000UL /**< Mode PCNT0TCC for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2532 #define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2533 #define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2534 #define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2535 #define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2536 #define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2537 #define _PRS_CH_CTRL_SIGSEL_USBSOFSR 0x00000001UL /**< Mode USBSOFSR for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2538 #define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2539 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2540 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2541 #define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2542 #define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2543 #define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2544 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2545 #define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2546 #define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2547 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2548 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2549 #define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2550 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2551 #define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2552 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2553 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2554 #define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2555 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2556 #define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2557 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2558 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2559 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2560 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2561 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2562 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2563 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2564 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2565 #define PRS_CH_CTRL_SIGSEL_VCMPOUT (_PRS_CH_CTRL_SIGSEL_VCMPOUT << 0) /**< Shifted mode VCMPOUT for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2566 #define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2567 #define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2568 #define PRS_CH_CTRL_SIGSEL_USART1IRTX (_PRS_CH_CTRL_SIGSEL_USART1IRTX << 0) /**< Shifted mode USART1IRTX for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2569 #define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2570 #define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2571 #define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2572 #define PRS_CH_CTRL_SIGSEL_USBSOF (_PRS_CH_CTRL_SIGSEL_USBSOF << 0) /**< Shifted mode USBSOF for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2573 #define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2574 #define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2575 #define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2576 #define PRS_CH_CTRL_SIGSEL_PCNT0TCC (_PRS_CH_CTRL_SIGSEL_PCNT0TCC << 0) /**< Shifted mode PCNT0TCC for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2577 #define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2578 #define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2579 #define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2580 #define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2581 #define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2582 #define PRS_CH_CTRL_SIGSEL_USBSOFSR (_PRS_CH_CTRL_SIGSEL_USBSOFSR << 0) /**< Shifted mode USBSOFSR for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2583 #define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2584 #define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2585 #define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2586 #define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2587 #define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2588 #define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2589 #define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2590 #define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2591 #define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2592 #define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2593 #define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2594 #define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2595 #define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2596 #define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2597 #define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2598 #define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2599 #define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2600 #define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2601 #define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2602 #define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2603 #define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2604 #define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2605 #define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2606 #define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2607 #define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2608 #define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2609 #define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2610 #define _PRS_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for PRS_SOURCESEL */
<> 128:9bcdf88f62b0 2611 #define _PRS_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for PRS_SOURCESEL */
<> 128:9bcdf88f62b0 2612 #define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2613 #define _PRS_CH_CTRL_SOURCESEL_VCMP 0x00000001UL /**< Mode VCMP for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2614 #define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000002UL /**< Mode ACMP0 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2615 #define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000010UL /**< Mode USART0 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2616 #define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000011UL /**< Mode USART1 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2617 #define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL /**< Mode TIMER0 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2618 #define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000001DUL /**< Mode TIMER1 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2619 #define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000001EUL /**< Mode TIMER2 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2620 #define _PRS_CH_CTRL_SOURCESEL_USB 0x00000024UL /**< Mode USB for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2621 #define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000028UL /**< Mode RTC for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2622 #define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000030UL /**< Mode GPIOL for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2623 #define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x00000031UL /**< Mode GPIOH for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2624 #define _PRS_CH_CTRL_SOURCESEL_PCNT0 0x00000036UL /**< Mode PCNT0 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2625 #define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2626 #define PRS_CH_CTRL_SOURCESEL_VCMP (_PRS_CH_CTRL_SOURCESEL_VCMP << 16) /**< Shifted mode VCMP for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2627 #define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 16) /**< Shifted mode ACMP0 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2628 #define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2629 #define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2630 #define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2631 #define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2632 #define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 16) /**< Shifted mode TIMER2 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2633 #define PRS_CH_CTRL_SOURCESEL_USB (_PRS_CH_CTRL_SOURCESEL_USB << 16) /**< Shifted mode USB for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2634 #define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 16) /**< Shifted mode RTC for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2635 #define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 16) /**< Shifted mode GPIOL for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2636 #define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 16) /**< Shifted mode GPIOH for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2637 #define PRS_CH_CTRL_SOURCESEL_PCNT0 (_PRS_CH_CTRL_SOURCESEL_PCNT0 << 16) /**< Shifted mode PCNT0 for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2638 #define _PRS_CH_CTRL_EDSEL_SHIFT 24 /**< Shift value for PRS_EDSEL */
<> 128:9bcdf88f62b0 2639 #define _PRS_CH_CTRL_EDSEL_MASK 0x3000000UL /**< Bit mask for PRS_EDSEL */
<> 128:9bcdf88f62b0 2640 #define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2641 #define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2642 #define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2643 #define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2644 #define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2645 #define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2646 #define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 24) /**< Shifted mode OFF for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2647 #define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 24) /**< Shifted mode POSEDGE for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2648 #define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 24) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2649 #define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 24) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2650 #define PRS_CH_CTRL_ASYNC (0x1UL << 28) /**< Asynchronous reflex */
<> 128:9bcdf88f62b0 2651 #define _PRS_CH_CTRL_ASYNC_SHIFT 28 /**< Shift value for PRS_ASYNC */
<> 128:9bcdf88f62b0 2652 #define _PRS_CH_CTRL_ASYNC_MASK 0x10000000UL /**< Bit mask for PRS_ASYNC */
<> 128:9bcdf88f62b0 2653 #define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2654 #define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */
<> 128:9bcdf88f62b0 2655
<> 128:9bcdf88f62b0 2656 /* Bit fields for PRS TRACECTRL */
<> 128:9bcdf88f62b0 2657 #define _PRS_TRACECTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_TRACECTRL */
<> 128:9bcdf88f62b0 2658 #define _PRS_TRACECTRL_MASK 0x00000F0FUL /**< Mask for PRS_TRACECTRL */
<> 128:9bcdf88f62b0 2659 #define PRS_TRACECTRL_TSTARTEN (0x1UL << 0) /**< PRS TSTART Enable */
<> 128:9bcdf88f62b0 2660 #define _PRS_TRACECTRL_TSTARTEN_SHIFT 0 /**< Shift value for PRS_TSTARTEN */
<> 128:9bcdf88f62b0 2661 #define _PRS_TRACECTRL_TSTARTEN_MASK 0x1UL /**< Bit mask for PRS_TSTARTEN */
<> 128:9bcdf88f62b0 2662 #define _PRS_TRACECTRL_TSTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_TRACECTRL */
<> 128:9bcdf88f62b0 2663 #define PRS_TRACECTRL_TSTARTEN_DEFAULT (_PRS_TRACECTRL_TSTARTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_TRACECTRL */
<> 128:9bcdf88f62b0 2664 #define _PRS_TRACECTRL_TSTART_SHIFT 1 /**< Shift value for PRS_TSTART */
<> 128:9bcdf88f62b0 2665 #define _PRS_TRACECTRL_TSTART_MASK 0xEUL /**< Bit mask for PRS_TSTART */
<> 128:9bcdf88f62b0 2666 #define _PRS_TRACECTRL_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_TRACECTRL */
<> 128:9bcdf88f62b0 2667 #define _PRS_TRACECTRL_TSTART_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_TRACECTRL */
<> 128:9bcdf88f62b0 2668 #define _PRS_TRACECTRL_TSTART_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_TRACECTRL */
<> 128:9bcdf88f62b0 2669 #define _PRS_TRACECTRL_TSTART_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_TRACECTRL */
<> 128:9bcdf88f62b0 2670 #define _PRS_TRACECTRL_TSTART_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_TRACECTRL */
<> 128:9bcdf88f62b0 2671 #define _PRS_TRACECTRL_TSTART_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_TRACECTRL */
<> 128:9bcdf88f62b0 2672 #define _PRS_TRACECTRL_TSTART_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_TRACECTRL */
<> 128:9bcdf88f62b0 2673 #define PRS_TRACECTRL_TSTART_DEFAULT (_PRS_TRACECTRL_TSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_TRACECTRL */
<> 128:9bcdf88f62b0 2674 #define PRS_TRACECTRL_TSTART_PRSCH0 (_PRS_TRACECTRL_TSTART_PRSCH0 << 1) /**< Shifted mode PRSCH0 for PRS_TRACECTRL */
<> 128:9bcdf88f62b0 2675 #define PRS_TRACECTRL_TSTART_PRSCH1 (_PRS_TRACECTRL_TSTART_PRSCH1 << 1) /**< Shifted mode PRSCH1 for PRS_TRACECTRL */
<> 128:9bcdf88f62b0 2676 #define PRS_TRACECTRL_TSTART_PRSCH2 (_PRS_TRACECTRL_TSTART_PRSCH2 << 1) /**< Shifted mode PRSCH2 for PRS_TRACECTRL */
<> 128:9bcdf88f62b0 2677 #define PRS_TRACECTRL_TSTART_PRSCH3 (_PRS_TRACECTRL_TSTART_PRSCH3 << 1) /**< Shifted mode PRSCH3 for PRS_TRACECTRL */
<> 128:9bcdf88f62b0 2678 #define PRS_TRACECTRL_TSTART_PRSCH4 (_PRS_TRACECTRL_TSTART_PRSCH4 << 1) /**< Shifted mode PRSCH4 for PRS_TRACECTRL */
<> 128:9bcdf88f62b0 2679 #define PRS_TRACECTRL_TSTART_PRSCH5 (_PRS_TRACECTRL_TSTART_PRSCH5 << 1) /**< Shifted mode PRSCH5 for PRS_TRACECTRL */
<> 128:9bcdf88f62b0 2680 #define PRS_TRACECTRL_TSTOPEN (0x1UL << 8) /**< PRS TSTOP Enable */
<> 128:9bcdf88f62b0 2681 #define _PRS_TRACECTRL_TSTOPEN_SHIFT 8 /**< Shift value for PRS_TSTOPEN */
<> 128:9bcdf88f62b0 2682 #define _PRS_TRACECTRL_TSTOPEN_MASK 0x100UL /**< Bit mask for PRS_TSTOPEN */
<> 128:9bcdf88f62b0 2683 #define _PRS_TRACECTRL_TSTOPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_TRACECTRL */
<> 128:9bcdf88f62b0 2684 #define PRS_TRACECTRL_TSTOPEN_DEFAULT (_PRS_TRACECTRL_TSTOPEN_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_TRACECTRL */
<> 128:9bcdf88f62b0 2685 #define _PRS_TRACECTRL_TSTOP_SHIFT 9 /**< Shift value for PRS_TSTOP */
<> 128:9bcdf88f62b0 2686 #define _PRS_TRACECTRL_TSTOP_MASK 0xE00UL /**< Bit mask for PRS_TSTOP */
<> 128:9bcdf88f62b0 2687 #define _PRS_TRACECTRL_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_TRACECTRL */
<> 128:9bcdf88f62b0 2688 #define _PRS_TRACECTRL_TSTOP_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_TRACECTRL */
<> 128:9bcdf88f62b0 2689 #define _PRS_TRACECTRL_TSTOP_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_TRACECTRL */
<> 128:9bcdf88f62b0 2690 #define _PRS_TRACECTRL_TSTOP_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_TRACECTRL */
<> 128:9bcdf88f62b0 2691 #define _PRS_TRACECTRL_TSTOP_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_TRACECTRL */
<> 128:9bcdf88f62b0 2692 #define _PRS_TRACECTRL_TSTOP_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_TRACECTRL */
<> 128:9bcdf88f62b0 2693 #define _PRS_TRACECTRL_TSTOP_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_TRACECTRL */
<> 128:9bcdf88f62b0 2694 #define PRS_TRACECTRL_TSTOP_DEFAULT (_PRS_TRACECTRL_TSTOP_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_TRACECTRL */
<> 128:9bcdf88f62b0 2695 #define PRS_TRACECTRL_TSTOP_PRSCH0 (_PRS_TRACECTRL_TSTOP_PRSCH0 << 9) /**< Shifted mode PRSCH0 for PRS_TRACECTRL */
<> 128:9bcdf88f62b0 2696 #define PRS_TRACECTRL_TSTOP_PRSCH1 (_PRS_TRACECTRL_TSTOP_PRSCH1 << 9) /**< Shifted mode PRSCH1 for PRS_TRACECTRL */
<> 128:9bcdf88f62b0 2697 #define PRS_TRACECTRL_TSTOP_PRSCH2 (_PRS_TRACECTRL_TSTOP_PRSCH2 << 9) /**< Shifted mode PRSCH2 for PRS_TRACECTRL */
<> 128:9bcdf88f62b0 2698 #define PRS_TRACECTRL_TSTOP_PRSCH3 (_PRS_TRACECTRL_TSTOP_PRSCH3 << 9) /**< Shifted mode PRSCH3 for PRS_TRACECTRL */
<> 128:9bcdf88f62b0 2699 #define PRS_TRACECTRL_TSTOP_PRSCH4 (_PRS_TRACECTRL_TSTOP_PRSCH4 << 9) /**< Shifted mode PRSCH4 for PRS_TRACECTRL */
<> 128:9bcdf88f62b0 2700 #define PRS_TRACECTRL_TSTOP_PRSCH5 (_PRS_TRACECTRL_TSTOP_PRSCH5 << 9) /**< Shifted mode PRSCH5 for PRS_TRACECTRL */
<> 128:9bcdf88f62b0 2701
<> 128:9bcdf88f62b0 2702 /** @} End of group EFM32HG308F64_PRS */
<> 128:9bcdf88f62b0 2703
<> 128:9bcdf88f62b0 2704
<> 128:9bcdf88f62b0 2705
<> 128:9bcdf88f62b0 2706 /**************************************************************************//**
<> 128:9bcdf88f62b0 2707 * @defgroup EFM32HG308F64_UNLOCK EFM32HG308F64 Unlock Codes
<> 128:9bcdf88f62b0 2708 * @{
<> 128:9bcdf88f62b0 2709 *****************************************************************************/
<> 128:9bcdf88f62b0 2710 #define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
<> 128:9bcdf88f62b0 2711 #define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
<> 128:9bcdf88f62b0 2712 #define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
<> 128:9bcdf88f62b0 2713 #define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
<> 128:9bcdf88f62b0 2714 #define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
<> 128:9bcdf88f62b0 2715
<> 128:9bcdf88f62b0 2716 /** @} End of group EFM32HG308F64_UNLOCK */
<> 128:9bcdf88f62b0 2717
<> 128:9bcdf88f62b0 2718 /** @} End of group EFM32HG308F64_BitFields */
<> 128:9bcdf88f62b0 2719
<> 128:9bcdf88f62b0 2720 /**************************************************************************//**
<> 128:9bcdf88f62b0 2721 * @defgroup EFM32HG308F64_Alternate_Function EFM32HG308F64 Alternate Function
<> 128:9bcdf88f62b0 2722 * @{
<> 128:9bcdf88f62b0 2723 *****************************************************************************/
<> 128:9bcdf88f62b0 2724
<> 128:9bcdf88f62b0 2725 #include "efm32hg_af_ports.h"
<> 128:9bcdf88f62b0 2726 #include "efm32hg_af_pins.h"
<> 128:9bcdf88f62b0 2727
<> 128:9bcdf88f62b0 2728 /** @} End of group EFM32HG308F64_Alternate_Function */
<> 128:9bcdf88f62b0 2729
<> 128:9bcdf88f62b0 2730 /**************************************************************************//**
<> 128:9bcdf88f62b0 2731 * @brief Set the value of a bit field within a register.
<> 128:9bcdf88f62b0 2732 *
<> 128:9bcdf88f62b0 2733 * @param REG
<> 128:9bcdf88f62b0 2734 * The register to update
<> 128:9bcdf88f62b0 2735 * @param MASK
<> 128:9bcdf88f62b0 2736 * The mask for the bit field to update
<> 128:9bcdf88f62b0 2737 * @param VALUE
<> 128:9bcdf88f62b0 2738 * The value to write to the bit field
<> 128:9bcdf88f62b0 2739 * @param OFFSET
<> 128:9bcdf88f62b0 2740 * The number of bits that the field is offset within the register.
<> 128:9bcdf88f62b0 2741 * 0 (zero) means LSB.
<> 128:9bcdf88f62b0 2742 *****************************************************************************/
<> 128:9bcdf88f62b0 2743 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
<> 128:9bcdf88f62b0 2744 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
<> 128:9bcdf88f62b0 2745
<> 128:9bcdf88f62b0 2746 /** @} End of group EFM32HG308F64 */
<> 128:9bcdf88f62b0 2747
<> 128:9bcdf88f62b0 2748 /** @} End of group Parts */
<> 128:9bcdf88f62b0 2749
<> 128:9bcdf88f62b0 2750 #ifdef __cplusplus
<> 128:9bcdf88f62b0 2751 }
<> 128:9bcdf88f62b0 2752 #endif
<> 128:9bcdf88f62b0 2753 #endif /* EFM32HG308F64_H */