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Dependents: hello SerialTestv11 SerialTestv12 Sierpinski ... more
Diff: TARGET_B96B_F446VE/stm32f4xx_hal_usart.h
- Revision:
- 122:f9eeca106725
- Parent:
- 112:6f327212ef96
--- a/TARGET_B96B_F446VE/stm32f4xx_hal_usart.h Wed May 25 16:44:06 2016 +0100
+++ b/TARGET_B96B_F446VE/stm32f4xx_hal_usart.h Thu Jul 07 14:34:11 2016 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_usart.h
* @author MCD Application Team
- * @version V1.4.1
- * @date 09-October-2015
+ * @version V1.5.0
+ * @date 06-May-2016
* @brief Header file of USART HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -101,14 +101,14 @@
*/
typedef enum
{
- HAL_USART_STATE_RESET = 0x00, /*!< Peripheral is not yet Initialized */
- HAL_USART_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
- HAL_USART_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
- HAL_USART_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
- HAL_USART_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
- HAL_USART_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission Reception process is ongoing */
- HAL_USART_STATE_TIMEOUT = 0x03, /*!< Timeout state */
- HAL_USART_STATE_ERROR = 0x04 /*!< Error */
+ HAL_USART_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */
+ HAL_USART_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
+ HAL_USART_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
+ HAL_USART_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */
+ HAL_USART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
+ HAL_USART_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission Reception process is ongoing */
+ HAL_USART_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
+ HAL_USART_STATE_ERROR = 0x04U /*!< Error */
}HAL_USART_StateTypeDef;
/**
@@ -156,12 +156,12 @@
* @brief USART Error Code
* @{
*/
-#define HAL_USART_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
-#define HAL_USART_ERROR_PE ((uint32_t)0x00000001) /*!< Parity error */
-#define HAL_USART_ERROR_NE ((uint32_t)0x00000002) /*!< Noise error */
-#define HAL_USART_ERROR_FE ((uint32_t)0x00000004) /*!< Frame error */
-#define HAL_USART_ERROR_ORE ((uint32_t)0x00000008) /*!< Overrun error */
-#define HAL_USART_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */
+#define HAL_USART_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
+#define HAL_USART_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */
+#define HAL_USART_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */
+#define HAL_USART_ERROR_FE ((uint32_t)0x00000004U) /*!< Frame error */
+#define HAL_USART_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */
+#define HAL_USART_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
/**
* @}
*/
@@ -169,7 +169,7 @@
/** @defgroup USART_Word_Length USART Word Length
* @{
*/
-#define USART_WORDLENGTH_8B ((uint32_t)0x00000000)
+#define USART_WORDLENGTH_8B ((uint32_t)0x00000000U)
#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
/**
* @}
@@ -178,7 +178,7 @@
/** @defgroup USART_Stop_Bits USART Number of Stop Bits
* @{
*/
-#define USART_STOPBITS_1 ((uint32_t)0x00000000)
+#define USART_STOPBITS_1 ((uint32_t)0x00000000U)
#define USART_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0)
#define USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
#define USART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
@@ -189,7 +189,7 @@
/** @defgroup USART_Parity USART Parity
* @{
*/
-#define USART_PARITY_NONE ((uint32_t)0x00000000)
+#define USART_PARITY_NONE ((uint32_t)0x00000000U)
#define USART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
/**
@@ -209,7 +209,7 @@
/** @defgroup USART_Clock USART Clock
* @{
*/
-#define USART_CLOCK_DISABLE ((uint32_t)0x00000000)
+#define USART_CLOCK_DISABLE ((uint32_t)0x00000000U)
#define USART_CLOCK_ENABLE ((uint32_t)USART_CR2_CLKEN)
/**
* @}
@@ -218,7 +218,7 @@
/** @defgroup USART_Clock_Polarity USART Clock Polarity
* @{
*/
-#define USART_POLARITY_LOW ((uint32_t)0x00000000)
+#define USART_POLARITY_LOW ((uint32_t)0x00000000U)
#define USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)
/**
* @}
@@ -227,7 +227,7 @@
/** @defgroup USART_Clock_Phase USART Clock Phase
* @{
*/
-#define USART_PHASE_1EDGE ((uint32_t)0x00000000)
+#define USART_PHASE_1EDGE ((uint32_t)0x00000000U)
#define USART_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)
/**
* @}
@@ -236,7 +236,7 @@
/** @defgroup USART_Last_Bit USART Last Bit
* @{
*/
-#define USART_LASTBIT_DISABLE ((uint32_t)0x00000000)
+#define USART_LASTBIT_DISABLE ((uint32_t)0x00000000U)
#define USART_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)
/**
* @}
@@ -246,7 +246,7 @@
* @{
*/
#define USART_NACK_ENABLE ((uint32_t)USART_CR3_NACK)
-#define USART_NACK_DISABLE ((uint32_t)0x00000000)
+#define USART_NACK_DISABLE ((uint32_t)0x00000000U)
/**
* @}
*/
@@ -256,14 +256,14 @@
* - 0xXXXX : Flag mask in the SR register
* @{
*/
-#define USART_FLAG_TXE ((uint32_t)0x00000080)
-#define USART_FLAG_TC ((uint32_t)0x00000040)
-#define USART_FLAG_RXNE ((uint32_t)0x00000020)
-#define USART_FLAG_IDLE ((uint32_t)0x00000010)
-#define USART_FLAG_ORE ((uint32_t)0x00000008)
-#define USART_FLAG_NE ((uint32_t)0x00000004)
-#define USART_FLAG_FE ((uint32_t)0x00000002)
-#define USART_FLAG_PE ((uint32_t)0x00000001)
+#define USART_FLAG_TXE ((uint32_t)0x00000080U)
+#define USART_FLAG_TC ((uint32_t)0x00000040U)
+#define USART_FLAG_RXNE ((uint32_t)0x00000020U)
+#define USART_FLAG_IDLE ((uint32_t)0x00000010U)
+#define USART_FLAG_ORE ((uint32_t)0x00000008U)
+#define USART_FLAG_NE ((uint32_t)0x00000004U)
+#define USART_FLAG_FE ((uint32_t)0x00000002U)
+#define USART_FLAG_PE ((uint32_t)0x00000001U)
/**
* @}
*/
@@ -278,16 +278,16 @@
*
* @{
*/
-#define USART_IT_PE ((uint32_t)(USART_CR1_REG_INDEX << 28 | USART_CR1_PEIE))
-#define USART_IT_TXE ((uint32_t)(USART_CR1_REG_INDEX << 28 | USART_CR1_TXEIE))
-#define USART_IT_TC ((uint32_t)(USART_CR1_REG_INDEX << 28 | USART_CR1_TCIE))
-#define USART_IT_RXNE ((uint32_t)(USART_CR1_REG_INDEX << 28 | USART_CR1_RXNEIE))
-#define USART_IT_IDLE ((uint32_t)(USART_CR1_REG_INDEX << 28 | USART_CR1_IDLEIE))
+#define USART_IT_PE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
+#define USART_IT_TXE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
+#define USART_IT_TC ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
+#define USART_IT_RXNE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
+#define USART_IT_IDLE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
-#define USART_IT_LBD ((uint32_t)(USART_CR2_REG_INDEX << 28 | USART_CR2_LBDIE))
+#define USART_IT_LBD ((uint32_t)(USART_CR2_REG_INDEX << 28U | USART_CR2_LBDIE))
-#define USART_IT_CTS ((uint32_t)(USART_CR3_REG_INDEX << 28 | USART_CR3_CTSIE))
-#define USART_IT_ERR ((uint32_t)(USART_CR3_REG_INDEX << 28 | USART_CR3_EIE))
+#define USART_IT_CTS ((uint32_t)(USART_CR3_REG_INDEX << 28U | USART_CR3_CTSIE))
+#define USART_IT_ERR ((uint32_t)(USART_CR3_REG_INDEX << 28U | USART_CR3_EIE))
/**
* @}
*/
@@ -353,7 +353,7 @@
*/
#define __HAL_USART_CLEAR_PEFLAG(__HANDLE__) \
do{ \
- __IO uint32_t tmpreg; \
+ __IO uint32_t tmpreg = 0x00U; \
tmpreg = (__HANDLE__)->Instance->SR; \
tmpreg = (__HANDLE__)->Instance->DR; \
UNUSED(tmpreg); \
@@ -401,11 +401,11 @@
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
-#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & USART_IT_MASK)): \
- (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & USART_IT_MASK)): \
+#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & USART_IT_MASK)): \
+ (((__INTERRUPT__) >> 28U) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & USART_IT_MASK)): \
((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & USART_IT_MASK)))
-#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
- (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
+#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
+ (((__INTERRUPT__) >> 28U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & USART_IT_MASK)))
/** @brief Checks whether the specified USART interrupt has occurred or not.
@@ -421,7 +421,7 @@
* @arg USART_IT_PE: Parity Error interrupt
* @retval The new state of __IT__ (TRUE or FALSE).
*/
-#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == 1)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28) == 2)? \
+#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == 1U)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == 2U)? \
(__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & USART_IT_MASK))
/** @brief Macro to enable the USART's one bit sample method
@@ -486,6 +486,7 @@
HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart);
HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart);
HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart);
+
void HAL_USART_IRQHandler(USART_HandleTypeDef *husart);
void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart);
void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart);
@@ -522,10 +523,9 @@
#define USART_IT_MASK ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \
USART_CR1_IDLEIE | USART_CR2_LBDIE | USART_CR3_CTSIE | USART_CR3_EIE )
-
-#define USART_CR1_REG_INDEX 1
-#define USART_CR2_REG_INDEX 2
-#define USART_CR3_REG_INDEX 3
+#define USART_CR1_REG_INDEX 1U
+#define USART_CR2_REG_INDEX 2U
+#define USART_CR3_REG_INDEX 3U
/**
* @}
*/
@@ -551,13 +551,13 @@
#define IS_USART_PARITY(PARITY) (((PARITY) == USART_PARITY_NONE) || \
((PARITY) == USART_PARITY_EVEN) || \
((PARITY) == USART_PARITY_ODD))
-#define IS_USART_MODE(MODE) ((((MODE) & (uint32_t)0xFFF3) == 0x00) && ((MODE) != (uint32_t)0x00))
-#define IS_USART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 10500001)
+#define IS_USART_MODE(MODE) ((((MODE) & (uint32_t)0xFFF3) == 0x00U) && ((MODE) != (uint32_t)0x00U))
+#define IS_USART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 10500001U)
-#define USART_DIV(_PCLK_, _BAUD_) (((_PCLK_)*25)/(2*(_BAUD_)))
-#define USART_DIVMANT(_PCLK_, _BAUD_) (USART_DIV((_PCLK_), (_BAUD_))/100)
-#define USART_DIVFRAQ(_PCLK_, _BAUD_) (((USART_DIV((_PCLK_), (_BAUD_)) - (USART_DIVMANT((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100)
-#define USART_BRR(_PCLK_, _BAUD_) ((USART_DIVMANT((_PCLK_), (_BAUD_)) << 4)|(USART_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0F))
+#define USART_DIV(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(2U*(_BAUD_)))
+#define USART_DIVMANT(_PCLK_, _BAUD_) (USART_DIV((_PCLK_), (_BAUD_))/100U)
+#define USART_DIVFRAQ(_PCLK_, _BAUD_) (((USART_DIV((_PCLK_), (_BAUD_)) - (USART_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)
+#define USART_BRR(_PCLK_, _BAUD_) ((USART_DIVMANT((_PCLK_), (_BAUD_)) << 4U)|(USART_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0FU))
/**
* @}
*/
