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Dependents: hello SerialTestv11 SerialTestv12 Sierpinski ... more
Diff: TARGET_NUCLEO_F411RE/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_qspi.h
- Revision:
- 145:64910690c574
- Parent:
- 128:9bcdf88f62b0
--- a/TARGET_NUCLEO_F411RE/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_qspi.h Thu Jun 08 14:53:05 2017 +0100
+++ b/TARGET_NUCLEO_F411RE/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_qspi.h Wed Jun 21 17:31:38 2017 +0100
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_hal_qspi.h
* @author MCD Application Team
- * @version V1.5.0
- * @date 06-May-2016
+ * @version V1.7.1
+ * @date 14-April-2017
* @brief Header file of QSPI HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -44,7 +44,7 @@
#endif
#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
- defined(STM32F412Rx)
+ defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
@@ -121,11 +121,11 @@
QUADSPI_TypeDef *Instance; /* QSPI registers base address */
QSPI_InitTypeDef Init; /* QSPI communication parameters */
uint8_t *pTxBuffPtr; /* Pointer to QSPI Tx transfer Buffer */
- __IO uint16_t TxXferSize; /* QSPI Tx Transfer size */
- __IO uint16_t TxXferCount; /* QSPI Tx Transfer Counter */
+ __IO uint32_t TxXferSize; /* QSPI Tx Transfer size */
+ __IO uint32_t TxXferCount; /* QSPI Tx Transfer Counter */
uint8_t *pRxBuffPtr; /* Pointer to QSPI Rx transfer Buffer */
- __IO uint16_t RxXferSize; /* QSPI Rx Transfer size */
- __IO uint16_t RxXferCount; /* QSPI Rx Transfer Counter */
+ __IO uint32_t RxXferSize; /* QSPI Rx Transfer size */
+ __IO uint32_t RxXferCount; /* QSPI Rx Transfer Counter */
DMA_HandleTypeDef *hdma; /* QSPI Rx/Tx DMA Handle parameters */
__IO HAL_LockTypeDef Lock; /* Locking object */
__IO HAL_QSPI_StateTypeDef State; /* QSPI communication state */
@@ -210,11 +210,11 @@
/** @defgroup QSPI_ErrorCode QSPI Error Code
* @{
*/
-#define HAL_QSPI_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
-#define HAL_QSPI_ERROR_TIMEOUT ((uint32_t)0x00000001U) /*!< Timeout error */
-#define HAL_QSPI_ERROR_TRANSFER ((uint32_t)0x00000002U) /*!< Transfer error */
-#define HAL_QSPI_ERROR_DMA ((uint32_t)0x00000004U) /*!< DMA transfer error */
-#define HAL_QSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008U) /*!< Invalid parameters error */
+#define HAL_QSPI_ERROR_NONE 0x00000000U /*!< No error */
+#define HAL_QSPI_ERROR_TIMEOUT 0x00000001U /*!< Timeout error */
+#define HAL_QSPI_ERROR_TRANSFER 0x00000002U /*!< Transfer error */
+#define HAL_QSPI_ERROR_DMA 0x00000004U /*!< DMA transfer error */
+#define HAL_QSPI_ERROR_INVALID_PARAM 0x00000008U /*!< Invalid parameters error */
/**
* @}
*/
@@ -222,7 +222,7 @@
/** @defgroup QSPI_SampleShifting QSPI Sample Shifting
* @{
*/
-#define QSPI_SAMPLE_SHIFTING_NONE ((uint32_t)0x00000000U) /*!<No clock cycle shift to sample data*/
+#define QSPI_SAMPLE_SHIFTING_NONE 0x00000000U /*!<No clock cycle shift to sample data*/
#define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/
/**
* @}
@@ -231,7 +231,7 @@
/** @defgroup QSPI_ChipSelectHighTime QSPI Chip Select High Time
* @{
*/
-#define QSPI_CS_HIGH_TIME_1_CYCLE ((uint32_t)0x00000000U) /*!<nCS stay high for at least 1 clock cycle between commands*/
+#define QSPI_CS_HIGH_TIME_1_CYCLE 0x00000000U /*!<nCS stay high for at least 1 clock cycle between commands*/
#define QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 2 clock cycles between commands*/
#define QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 3 clock cycles between commands*/
#define QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/
@@ -246,7 +246,7 @@
/** @defgroup QSPI_ClockMode QSPI Clock Mode
* @{
*/
-#define QSPI_CLOCK_MODE_0 ((uint32_t)0x00000000U) /*!<Clk stays low while nCS is released*/
+#define QSPI_CLOCK_MODE_0 0x00000000U /*!<Clk stays low while nCS is released*/
#define QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/
/**
* @}
@@ -255,7 +255,7 @@
/** @defgroup QSPI_Flash_Select QSPI Flash Select
* @{
*/
-#define QSPI_FLASH_ID_1 ((uint32_t)0x00000000U)
+#define QSPI_FLASH_ID_1 0x00000000U
#define QSPI_FLASH_ID_2 ((uint32_t)QUADSPI_CR_FSEL)
/**
* @}
@@ -265,7 +265,7 @@
* @{
*/
#define QSPI_DUALFLASH_ENABLE ((uint32_t)QUADSPI_CR_DFM)
-#define QSPI_DUALFLASH_DISABLE ((uint32_t)0x00000000U)
+#define QSPI_DUALFLASH_DISABLE 0x00000000U
/**
* @}
*/
@@ -273,7 +273,7 @@
/** @defgroup QSPI_AddressSize QSPI Address Size
* @{
*/
-#define QSPI_ADDRESS_8_BITS ((uint32_t)0x00000000U) /*!<8-bit address*/
+#define QSPI_ADDRESS_8_BITS 0x00000000U /*!<8-bit address*/
#define QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/
#define QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/
#define QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE) /*!<32-bit address*/
@@ -284,7 +284,7 @@
/** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size
* @{
*/
-#define QSPI_ALTERNATE_BYTES_8_BITS ((uint32_t)0x00000000U) /*!<8-bit alternate bytes*/
+#define QSPI_ALTERNATE_BYTES_8_BITS 0x00000000U /*!<8-bit alternate bytes*/
#define QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/
#define QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/
#define QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE) /*!<32-bit alternate bytes*/
@@ -295,7 +295,7 @@
/** @defgroup QSPI_InstructionMode QSPI Instruction Mode
* @{
*/
-#define QSPI_INSTRUCTION_NONE ((uint32_t)0x00000000U) /*!<No instruction*/
+#define QSPI_INSTRUCTION_NONE 0x00000000U /*!<No instruction*/
#define QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/
#define QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/
#define QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE) /*!<Instruction on four lines*/
@@ -306,7 +306,7 @@
/** @defgroup QSPI_AddressMode QSPI Address Mode
* @{
*/
-#define QSPI_ADDRESS_NONE ((uint32_t)0x00000000U) /*!<No address*/
+#define QSPI_ADDRESS_NONE 0x00000000U /*!<No address*/
#define QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/
#define QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/
#define QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE) /*!<Address on four lines*/
@@ -317,7 +317,7 @@
/** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode
* @{
*/
-#define QSPI_ALTERNATE_BYTES_NONE ((uint32_t)0x00000000U) /*!<No alternate bytes*/
+#define QSPI_ALTERNATE_BYTES_NONE 0x00000000U /*!<No alternate bytes*/
#define QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/
#define QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/
#define QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE) /*!<Alternate bytes on four lines*/
@@ -328,7 +328,7 @@
/** @defgroup QSPI_DataMode QSPI Data Mode
* @{
*/
-#define QSPI_DATA_NONE ((uint32_t)0x00000000U) /*!<No data*/
+#define QSPI_DATA_NONE 0x00000000U /*!<No data*/
#define QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/
#define QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/
#define QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE) /*!<Data on four lines*/
@@ -339,7 +339,7 @@
/** @defgroup QSPI_DdrMode QSPI Ddr Mode
* @{
*/
-#define QSPI_DDR_MODE_DISABLE ((uint32_t)0x00000000U) /*!<Double data rate mode disabled*/
+#define QSPI_DDR_MODE_DISABLE 0x00000000U /*!<Double data rate mode disabled*/
#define QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/
/**
* @}
@@ -348,7 +348,7 @@
/** @defgroup QSPI_DdrHoldHalfCycle QSPI Ddr HoldHalfCycle
* @{
*/
-#define QSPI_DDR_HHC_ANALOG_DELAY ((uint32_t)0x00000000U) /*!<Delay the data output using analog delay in DDR mode*/
+#define QSPI_DDR_HHC_ANALOG_DELAY 0x00000000U /*!<Delay the data output using analog delay in DDR mode*/
#define QSPI_DDR_HHC_HALF_CLK_DELAY ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by 1/2 clock cycle in DDR mode*/
/**
* @}
@@ -357,7 +357,7 @@
/** @defgroup QSPI_SIOOMode QSPI SIOO Mode
* @{
*/
-#define QSPI_SIOO_INST_EVERY_CMD ((uint32_t)0x00000000U) /*!<Send instruction on every transaction*/
+#define QSPI_SIOO_INST_EVERY_CMD 0x00000000U /*!<Send instruction on every transaction*/
#define QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/
/**
* @}
@@ -366,7 +366,7 @@
/** @defgroup QSPI_MatchMode QSPI Match Mode
* @{
*/
-#define QSPI_MATCH_MODE_AND ((uint32_t)0x00000000U) /*!<AND match mode between unmasked bits*/
+#define QSPI_MATCH_MODE_AND 0x00000000U /*!<AND match mode between unmasked bits*/
#define QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/
/**
* @}
@@ -375,7 +375,7 @@
/** @defgroup QSPI_AutomaticStop QSPI Automatic Stop
* @{
*/
-#define QSPI_AUTOMATIC_STOP_DISABLE ((uint32_t)0x00000000U) /*!<AutoPolling stops only with abort or QSPI disabling*/
+#define QSPI_AUTOMATIC_STOP_DISABLE 0x00000000U /*!<AutoPolling stops only with abort or QSPI disabling*/
#define QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/
/**
* @}
@@ -384,7 +384,7 @@
/** @defgroup QSPI_TimeOutActivation QSPI TimeOut Activation
* @{
*/
-#define QSPI_TIMEOUT_COUNTER_DISABLE ((uint32_t)0x00000000U) /*!<Timeout counter disabled, nCS remains active*/
+#define QSPI_TIMEOUT_COUNTER_DISABLE 0x00000000U /*!<Timeout counter disabled, nCS remains active*/
#define QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/
/**
* @}
@@ -418,7 +418,7 @@
/** @defgroup QSPI_Timeout_definition QSPI Timeout definition
* @{
*/
-#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000U)/* 5 s */
+#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE 5000U /* 5 s */
/**
* @}
*/
@@ -748,7 +748,7 @@
((FLAG) == QSPI_FLAG_TC) || \
((FLAG) == QSPI_FLAG_TE))
-#define IS_QSPI_IT(IT) ((((IT) & (uint32_t)0xFFE0FFFFU) == 0x00000000U) && ((IT) != 0x00000000U))
+#define IS_QSPI_IT(IT) ((((IT) & 0xFFE0FFFFU) == 0x00000000U) && ((IT) != 0x00000000U))
/**
* @}
*/
@@ -773,7 +773,8 @@
/**
* @}
*/
-#endif /* STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx */
+#endif /* STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx ||
+ STM32F413xx || STM32F423xx */
#ifdef __cplusplus
}
