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TARGET_NUCLEO_L432KC/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc.h@156:ff21514d8981, 2017-11-08 (annotated)

Committer:: AnnaBridge
Date:: Wed Nov 08 17:18:06 2017 +0000
Revision:: 156:ff21514d8981
Child:: 161:aa5281ff4a02

Reverting back to release 154 of the mbed library

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	156:ff21514d8981	1	/**
AnnaBridge	156:ff21514d8981	2	******************************************************************************
AnnaBridge	156:ff21514d8981	3	* @file stm32l4xx_hal_rcc.h
AnnaBridge	156:ff21514d8981	4	* @author MCD Application Team
AnnaBridge	156:ff21514d8981	5	* @version V1.7.1
AnnaBridge	156:ff21514d8981	6	* @date 21-April-2017
AnnaBridge	156:ff21514d8981	7	* @brief Header file of RCC HAL module.
AnnaBridge	156:ff21514d8981	8	******************************************************************************
AnnaBridge	156:ff21514d8981	9	* @attention
AnnaBridge	156:ff21514d8981	10	*
AnnaBridge	156:ff21514d8981	11	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge	156:ff21514d8981	12	*
AnnaBridge	156:ff21514d8981	13	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	156:ff21514d8981	14	* are permitted provided that the following conditions are met:
AnnaBridge	156:ff21514d8981	15	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	156:ff21514d8981	16	* this list of conditions and the following disclaimer.
AnnaBridge	156:ff21514d8981	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	156:ff21514d8981	18	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	156:ff21514d8981	19	* and/or other materials provided with the distribution.
AnnaBridge	156:ff21514d8981	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	156:ff21514d8981	21	* may be used to endorse or promote products derived from this software
AnnaBridge	156:ff21514d8981	22	* without specific prior written permission.
AnnaBridge	156:ff21514d8981	23	*
AnnaBridge	156:ff21514d8981	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	156:ff21514d8981	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	156:ff21514d8981	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	156:ff21514d8981	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	156:ff21514d8981	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	156:ff21514d8981	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	156:ff21514d8981	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	156:ff21514d8981	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	156:ff21514d8981	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	156:ff21514d8981	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	156:ff21514d8981	34	*
AnnaBridge	156:ff21514d8981	35	******************************************************************************
AnnaBridge	156:ff21514d8981	36	*/
AnnaBridge	156:ff21514d8981	37
AnnaBridge	156:ff21514d8981	38	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	156:ff21514d8981	39	#ifndef __STM32L4xx_HAL_RCC_H
AnnaBridge	156:ff21514d8981	40	#define __STM32L4xx_HAL_RCC_H
AnnaBridge	156:ff21514d8981	41
AnnaBridge	156:ff21514d8981	42	#ifdef __cplusplus
AnnaBridge	156:ff21514d8981	43	extern "C" {
AnnaBridge	156:ff21514d8981	44	#endif
AnnaBridge	156:ff21514d8981	45
AnnaBridge	156:ff21514d8981	46	/* Includes ------------------------------------------------------------------*/
AnnaBridge	156:ff21514d8981	47	#include "stm32l4xx_hal_def.h"
AnnaBridge	156:ff21514d8981	48
AnnaBridge	156:ff21514d8981	49	/** @addtogroup STM32L4xx_HAL_Driver
AnnaBridge	156:ff21514d8981	50	* @{
AnnaBridge	156:ff21514d8981	51	*/
AnnaBridge	156:ff21514d8981	52
AnnaBridge	156:ff21514d8981	53	/** @addtogroup RCC
AnnaBridge	156:ff21514d8981	54	* @{
AnnaBridge	156:ff21514d8981	55	*/
AnnaBridge	156:ff21514d8981	56
AnnaBridge	156:ff21514d8981	57	/* Exported types ------------------------------------------------------------*/
AnnaBridge	156:ff21514d8981	58	/** @defgroup RCC_Exported_Types RCC Exported Types
AnnaBridge	156:ff21514d8981	59	* @{
AnnaBridge	156:ff21514d8981	60	*/
AnnaBridge	156:ff21514d8981	61
AnnaBridge	156:ff21514d8981	62	/**
AnnaBridge	156:ff21514d8981	63	* @brief RCC PLL configuration structure definition
AnnaBridge	156:ff21514d8981	64	*/
AnnaBridge	156:ff21514d8981	65	typedef struct
AnnaBridge	156:ff21514d8981	66	{
AnnaBridge	156:ff21514d8981	67	uint32_t PLLState; /*!< The new state of the PLL.
AnnaBridge	156:ff21514d8981	68	This parameter can be a value of @ref RCC_PLL_Config */
AnnaBridge	156:ff21514d8981	69
AnnaBridge	156:ff21514d8981	70	uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
AnnaBridge	156:ff21514d8981	71	This parameter must be a value of @ref RCC_PLL_Clock_Source */
AnnaBridge	156:ff21514d8981	72
AnnaBridge	156:ff21514d8981	73	uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
AnnaBridge	156:ff21514d8981	74	This parameter must be a number between Min_Data = 1 and Max_Data = 8 */
AnnaBridge	156:ff21514d8981	75
AnnaBridge	156:ff21514d8981	76	uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
AnnaBridge	156:ff21514d8981	77	This parameter must be a number between Min_Data = 8 and Max_Data = 86 */
AnnaBridge	156:ff21514d8981	78
AnnaBridge	156:ff21514d8981	79	uint32_t PLLP; /*!< PLLP: Division factor for SAI clock.
AnnaBridge	156:ff21514d8981	80	This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
AnnaBridge	156:ff21514d8981	81
AnnaBridge	156:ff21514d8981	82	uint32_t PLLQ; /*!< PLLQ: Division factor for SDMMC1, RNG and USB clocks.
AnnaBridge	156:ff21514d8981	83	This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */
AnnaBridge	156:ff21514d8981	84
AnnaBridge	156:ff21514d8981	85	uint32_t PLLR; /*!< PLLR: Division for the main system clock.
AnnaBridge	156:ff21514d8981	86	User have to set the PLLR parameter correctly to not exceed max frequency 80MHZ.
AnnaBridge	156:ff21514d8981	87	This parameter must be a value of @ref RCC_PLLR_Clock_Divider */
AnnaBridge	156:ff21514d8981	88
AnnaBridge	156:ff21514d8981	89	}RCC_PLLInitTypeDef;
AnnaBridge	156:ff21514d8981	90
AnnaBridge	156:ff21514d8981	91	/**
AnnaBridge	156:ff21514d8981	92	* @brief RCC Internal/External Oscillator (HSE, HSI, MSI, LSE and LSI) configuration structure definition
AnnaBridge	156:ff21514d8981	93	*/
AnnaBridge	156:ff21514d8981	94	typedef struct
AnnaBridge	156:ff21514d8981	95	{
AnnaBridge	156:ff21514d8981	96	uint32_t OscillatorType; /*!< The oscillators to be configured.
AnnaBridge	156:ff21514d8981	97	This parameter can be a value of @ref RCC_Oscillator_Type */
AnnaBridge	156:ff21514d8981	98
AnnaBridge	156:ff21514d8981	99	uint32_t HSEState; /*!< The new state of the HSE.
AnnaBridge	156:ff21514d8981	100	This parameter can be a value of @ref RCC_HSE_Config */
AnnaBridge	156:ff21514d8981	101
AnnaBridge	156:ff21514d8981	102	uint32_t LSEState; /*!< The new state of the LSE.
AnnaBridge	156:ff21514d8981	103	This parameter can be a value of @ref RCC_LSE_Config */
AnnaBridge	156:ff21514d8981	104
AnnaBridge	156:ff21514d8981	105	uint32_t HSIState; /*!< The new state of the HSI.
AnnaBridge	156:ff21514d8981	106	This parameter can be a value of @ref RCC_HSI_Config */
AnnaBridge	156:ff21514d8981	107
AnnaBridge	156:ff21514d8981	108	uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
AnnaBridge	156:ff21514d8981	109	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F on STM32L43x/STM32L44x/STM32L47x/STM32L48x devices.
AnnaBridge	156:ff21514d8981	110	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F on the other devices */
AnnaBridge	156:ff21514d8981	111
AnnaBridge	156:ff21514d8981	112	uint32_t LSIState; /*!< The new state of the LSI.
AnnaBridge	156:ff21514d8981	113	This parameter can be a value of @ref RCC_LSI_Config */
AnnaBridge	156:ff21514d8981	114
AnnaBridge	156:ff21514d8981	115	uint32_t MSIState; /*!< The new state of the MSI.
AnnaBridge	156:ff21514d8981	116	This parameter can be a value of @ref RCC_MSI_Config */
AnnaBridge	156:ff21514d8981	117
AnnaBridge	156:ff21514d8981	118	uint32_t MSICalibrationValue; /*!< The calibration trimming value (default is RCC_MSICALIBRATION_DEFAULT).
AnnaBridge	156:ff21514d8981	119	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
AnnaBridge	156:ff21514d8981	120
AnnaBridge	156:ff21514d8981	121	uint32_t MSIClockRange; /*!< The MSI frequency range.
AnnaBridge	156:ff21514d8981	122	This parameter can be a value of @ref RCC_MSI_Clock_Range */
AnnaBridge	156:ff21514d8981	123
AnnaBridge	156:ff21514d8981	124	uint32_t HSI48State; /*!< The new state of the HSI48 (only applicable to STM32L43x/STM32L44x/STM32L45x/STM32L46x/STM32L49x/STM32L4Ax devices).
AnnaBridge	156:ff21514d8981	125	This parameter can be a value of @ref RCC_HSI48_Config */
AnnaBridge	156:ff21514d8981	126
AnnaBridge	156:ff21514d8981	127	RCC_PLLInitTypeDef PLL; /!< Main PLL structure parameters /
AnnaBridge	156:ff21514d8981	128
AnnaBridge	156:ff21514d8981	129	}RCC_OscInitTypeDef;
AnnaBridge	156:ff21514d8981	130
AnnaBridge	156:ff21514d8981	131	/**
AnnaBridge	156:ff21514d8981	132	* @brief RCC System, AHB and APB busses clock configuration structure definition
AnnaBridge	156:ff21514d8981	133	*/
AnnaBridge	156:ff21514d8981	134	typedef struct
AnnaBridge	156:ff21514d8981	135	{
AnnaBridge	156:ff21514d8981	136	uint32_t ClockType; /*!< The clock to be configured.
AnnaBridge	156:ff21514d8981	137	This parameter can be a value of @ref RCC_System_Clock_Type */
AnnaBridge	156:ff21514d8981	138
AnnaBridge	156:ff21514d8981	139	uint32_t SYSCLKSource; /*!< The clock source used as system clock (SYSCLK).
AnnaBridge	156:ff21514d8981	140	This parameter can be a value of @ref RCC_System_Clock_Source */
AnnaBridge	156:ff21514d8981	141
AnnaBridge	156:ff21514d8981	142	uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
AnnaBridge	156:ff21514d8981	143	This parameter can be a value of @ref RCC_AHB_Clock_Source */
AnnaBridge	156:ff21514d8981	144
AnnaBridge	156:ff21514d8981	145	uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
AnnaBridge	156:ff21514d8981	146	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
AnnaBridge	156:ff21514d8981	147
AnnaBridge	156:ff21514d8981	148	uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
AnnaBridge	156:ff21514d8981	149	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
AnnaBridge	156:ff21514d8981	150
AnnaBridge	156:ff21514d8981	151	}RCC_ClkInitTypeDef;
AnnaBridge	156:ff21514d8981	152
AnnaBridge	156:ff21514d8981	153	/**
AnnaBridge	156:ff21514d8981	154	* @}
AnnaBridge	156:ff21514d8981	155	*/
AnnaBridge	156:ff21514d8981	156
AnnaBridge	156:ff21514d8981	157	/* Exported constants --------------------------------------------------------*/
AnnaBridge	156:ff21514d8981	158	/** @defgroup RCC_Exported_Constants RCC Exported Constants
AnnaBridge	156:ff21514d8981	159	* @{
AnnaBridge	156:ff21514d8981	160	*/
AnnaBridge	156:ff21514d8981	161
AnnaBridge	156:ff21514d8981	162	/** @defgroup RCC_Timeout_Value Timeout Values
AnnaBridge	156:ff21514d8981	163	* @{
AnnaBridge	156:ff21514d8981	164	*/
AnnaBridge	156:ff21514d8981	165	#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */
AnnaBridge	156:ff21514d8981	166	#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
AnnaBridge	156:ff21514d8981	167	/**
AnnaBridge	156:ff21514d8981	168	* @}
AnnaBridge	156:ff21514d8981	169	*/
AnnaBridge	156:ff21514d8981	170
AnnaBridge	156:ff21514d8981	171	/** @defgroup RCC_Oscillator_Type Oscillator Type
AnnaBridge	156:ff21514d8981	172	* @{
AnnaBridge	156:ff21514d8981	173	*/
AnnaBridge	156:ff21514d8981	174	#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000U) /!< Oscillator configuration unchanged /
AnnaBridge	156:ff21514d8981	175	#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001U) /!< HSE to configure /
AnnaBridge	156:ff21514d8981	176	#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002U) /!< HSI to configure /
AnnaBridge	156:ff21514d8981	177	#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004U) /!< LSE to configure /
AnnaBridge	156:ff21514d8981	178	#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008U) /!< LSI to configure /
AnnaBridge	156:ff21514d8981	179	#define RCC_OSCILLATORTYPE_MSI ((uint32_t)0x00000010U) /!< MSI to configure /
AnnaBridge	156:ff21514d8981	180	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	156:ff21514d8981	181	#define RCC_OSCILLATORTYPE_HSI48 ((uint32_t)0x00000020U) /!< HSI48 to configure /
AnnaBridge	156:ff21514d8981	182	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	156:ff21514d8981	183	/**
AnnaBridge	156:ff21514d8981	184	* @}
AnnaBridge	156:ff21514d8981	185	*/
AnnaBridge	156:ff21514d8981	186
AnnaBridge	156:ff21514d8981	187	/** @defgroup RCC_HSE_Config HSE Config
AnnaBridge	156:ff21514d8981	188	* @{
AnnaBridge	156:ff21514d8981	189	*/
AnnaBridge	156:ff21514d8981	190	#define RCC_HSE_OFF ((uint32_t)0x00000000U) /!< HSE clock deactivation /
AnnaBridge	156:ff21514d8981	191	#define RCC_HSE_ON RCC_CR_HSEON /!< HSE clock activation /
AnnaBridge	156:ff21514d8981	192	#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP \| RCC_CR_HSEON)) /!< External clock source for HSE clock /
AnnaBridge	156:ff21514d8981	193	/**
AnnaBridge	156:ff21514d8981	194	* @}
AnnaBridge	156:ff21514d8981	195	*/
AnnaBridge	156:ff21514d8981	196
AnnaBridge	156:ff21514d8981	197	/** @defgroup RCC_LSE_Config LSE Config
AnnaBridge	156:ff21514d8981	198	* @{
AnnaBridge	156:ff21514d8981	199	*/
AnnaBridge	156:ff21514d8981	200	#define RCC_LSE_OFF ((uint32_t)0x00000000U) /!< LSE clock deactivation /
AnnaBridge	156:ff21514d8981	201	#define RCC_LSE_ON RCC_BDCR_LSEON /!< LSE clock activation /
AnnaBridge	156:ff21514d8981	202	#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP \| RCC_BDCR_LSEON)) /!< External clock source for LSE clock /
AnnaBridge	156:ff21514d8981	203	/**
AnnaBridge	156:ff21514d8981	204	* @}
AnnaBridge	156:ff21514d8981	205	*/
AnnaBridge	156:ff21514d8981	206
AnnaBridge	156:ff21514d8981	207	/** @defgroup RCC_HSI_Config HSI Config
AnnaBridge	156:ff21514d8981	208	* @{
AnnaBridge	156:ff21514d8981	209	*/
AnnaBridge	156:ff21514d8981	210	#define RCC_HSI_OFF ((uint32_t)0x00000000U) /!< HSI clock deactivation /
AnnaBridge	156:ff21514d8981	211	#define RCC_HSI_ON RCC_CR_HSION /!< HSI clock activation /
AnnaBridge	156:ff21514d8981	212
AnnaBridge	156:ff21514d8981	213	#if defined(STM32L431xx) \|\| defined(STM32L432xx) \|\| defined(STM32L433xx) \|\| defined(STM32L442xx) \|\| defined(STM32L443xx) \|\| \
AnnaBridge	156:ff21514d8981	214	defined(STM32L471xx) \|\| defined(STM32L475xx) \|\| defined(STM32L476xx) \|\| defined(STM32L485xx) \|\| defined(STM32L486xx)
AnnaBridge	156:ff21514d8981	215	#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10U) /* Default HSI calibration trimming value */
AnnaBridge	156:ff21514d8981	216	#else
AnnaBridge	156:ff21514d8981	217	#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x40U) /* Default HSI calibration trimming value */
AnnaBridge	156:ff21514d8981	218	#endif /* STM32L431xx \|\| STM32L432xx \|\| STM32L433xx \|\| STM32L442xx \|\| STM32L443xx \|\| */
AnnaBridge	156:ff21514d8981	219	/* STM32L471xx \|\| STM32L475xx \|\| STM32L476xx \|\| STM32L485xx \|\| STM32L486xx */
AnnaBridge	156:ff21514d8981	220	/**
AnnaBridge	156:ff21514d8981	221	* @}
AnnaBridge	156:ff21514d8981	222	*/
AnnaBridge	156:ff21514d8981	223
AnnaBridge	156:ff21514d8981	224	/** @defgroup RCC_LSI_Config LSI Config
AnnaBridge	156:ff21514d8981	225	* @{
AnnaBridge	156:ff21514d8981	226	*/
AnnaBridge	156:ff21514d8981	227	#define RCC_LSI_OFF ((uint32_t)0x00000000U) /!< LSI clock deactivation /
AnnaBridge	156:ff21514d8981	228	#define RCC_LSI_ON RCC_CSR_LSION /!< LSI clock activation /
AnnaBridge	156:ff21514d8981	229	/**
AnnaBridge	156:ff21514d8981	230	* @}
AnnaBridge	156:ff21514d8981	231	*/
AnnaBridge	156:ff21514d8981	232
AnnaBridge	156:ff21514d8981	233	/** @defgroup RCC_MSI_Config MSI Config
AnnaBridge	156:ff21514d8981	234	* @{
AnnaBridge	156:ff21514d8981	235	*/
AnnaBridge	156:ff21514d8981	236	#define RCC_MSI_OFF ((uint32_t)0x00000000U) /!< MSI clock deactivation /
AnnaBridge	156:ff21514d8981	237	#define RCC_MSI_ON RCC_CR_MSION /!< MSI clock activation /
AnnaBridge	156:ff21514d8981	238
AnnaBridge	156:ff21514d8981	239	#define RCC_MSICALIBRATION_DEFAULT ((uint32_t)0) /!< Default MSI calibration trimming value /
AnnaBridge	156:ff21514d8981	240	/**
AnnaBridge	156:ff21514d8981	241	* @}
AnnaBridge	156:ff21514d8981	242	*/
AnnaBridge	156:ff21514d8981	243
AnnaBridge	156:ff21514d8981	244	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	156:ff21514d8981	245	/** @defgroup RCC_HSI48_Config HSI48 Config
AnnaBridge	156:ff21514d8981	246	* @{
AnnaBridge	156:ff21514d8981	247	*/
AnnaBridge	156:ff21514d8981	248	#define RCC_HSI48_OFF ((uint32_t)0x00000000U) /!< HSI48 clock deactivation /
AnnaBridge	156:ff21514d8981	249	#define RCC_HSI48_ON RCC_CRRCR_HSI48ON /!< HSI48 clock activation /
AnnaBridge	156:ff21514d8981	250	/**
AnnaBridge	156:ff21514d8981	251	* @}
AnnaBridge	156:ff21514d8981	252	*/
AnnaBridge	156:ff21514d8981	253	#else
AnnaBridge	156:ff21514d8981	254	/** @defgroup RCC_HSI48_Config HSI48 Config
AnnaBridge	156:ff21514d8981	255	* @{
AnnaBridge	156:ff21514d8981	256	*/
AnnaBridge	156:ff21514d8981	257	#define RCC_HSI48_OFF ((uint32_t)0x00000000U) /!< HSI48 clock deactivation /
AnnaBridge	156:ff21514d8981	258	/**
AnnaBridge	156:ff21514d8981	259	* @}
AnnaBridge	156:ff21514d8981	260	*/
AnnaBridge	156:ff21514d8981	261	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	156:ff21514d8981	262
AnnaBridge	156:ff21514d8981	263	/** @defgroup RCC_PLL_Config PLL Config
AnnaBridge	156:ff21514d8981	264	* @{
AnnaBridge	156:ff21514d8981	265	*/
AnnaBridge	156:ff21514d8981	266	#define RCC_PLL_NONE ((uint32_t)0x00000000U) /!< PLL configuration unchanged /
AnnaBridge	156:ff21514d8981	267	#define RCC_PLL_OFF ((uint32_t)0x00000001U) /!< PLL deactivation /
AnnaBridge	156:ff21514d8981	268	#define RCC_PLL_ON ((uint32_t)0x00000002U) /!< PLL activation /
AnnaBridge	156:ff21514d8981	269	/**
AnnaBridge	156:ff21514d8981	270	* @}
AnnaBridge	156:ff21514d8981	271	*/
AnnaBridge	156:ff21514d8981	272
AnnaBridge	156:ff21514d8981	273	/** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
AnnaBridge	156:ff21514d8981	274	* @{
AnnaBridge	156:ff21514d8981	275	*/
AnnaBridge	156:ff21514d8981	276	#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
AnnaBridge	156:ff21514d8981	277	#define RCC_PLLP_DIV2 ((uint32_t)0x00000002U) /!< PLLP division factor = 2 /
AnnaBridge	156:ff21514d8981	278	#define RCC_PLLP_DIV3 ((uint32_t)0x00000003U) /!< PLLP division factor = 3 /
AnnaBridge	156:ff21514d8981	279	#define RCC_PLLP_DIV4 ((uint32_t)0x00000004U) /!< PLLP division factor = 4 /
AnnaBridge	156:ff21514d8981	280	#define RCC_PLLP_DIV5 ((uint32_t)0x00000005U) /!< PLLP division factor = 5 /
AnnaBridge	156:ff21514d8981	281	#define RCC_PLLP_DIV6 ((uint32_t)0x00000006U) /!< PLLP division factor = 6 /
AnnaBridge	156:ff21514d8981	282	#define RCC_PLLP_DIV7 ((uint32_t)0x00000007U) /!< PLLP division factor = 7 /
AnnaBridge	156:ff21514d8981	283	#define RCC_PLLP_DIV8 ((uint32_t)0x00000008U) /!< PLLP division factor = 8 /
AnnaBridge	156:ff21514d8981	284	#define RCC_PLLP_DIV9 ((uint32_t)0x00000009U) /!< PLLP division factor = 9 /
AnnaBridge	156:ff21514d8981	285	#define RCC_PLLP_DIV10 ((uint32_t)0x0000000AU) /!< PLLP division factor = 10 /
AnnaBridge	156:ff21514d8981	286	#define RCC_PLLP_DIV11 ((uint32_t)0x0000000BU) /!< PLLP division factor = 11 /
AnnaBridge	156:ff21514d8981	287	#define RCC_PLLP_DIV12 ((uint32_t)0x0000000CU) /!< PLLP division factor = 12 /
AnnaBridge	156:ff21514d8981	288	#define RCC_PLLP_DIV13 ((uint32_t)0x0000000DU) /!< PLLP division factor = 13 /
AnnaBridge	156:ff21514d8981	289	#define RCC_PLLP_DIV14 ((uint32_t)0x0000000EU) /!< PLLP division factor = 14 /
AnnaBridge	156:ff21514d8981	290	#define RCC_PLLP_DIV15 ((uint32_t)0x0000000FU) /!< PLLP division factor = 15 /
AnnaBridge	156:ff21514d8981	291	#define RCC_PLLP_DIV16 ((uint32_t)0x00000010U) /!< PLLP division factor = 16 /
AnnaBridge	156:ff21514d8981	292	#define RCC_PLLP_DIV17 ((uint32_t)0x00000011U) /!< PLLP division factor = 17 /
AnnaBridge	156:ff21514d8981	293	#define RCC_PLLP_DIV18 ((uint32_t)0x00000012U) /!< PLLP division factor = 18 /
AnnaBridge	156:ff21514d8981	294	#define RCC_PLLP_DIV19 ((uint32_t)0x00000013U) /!< PLLP division factor = 19 /
AnnaBridge	156:ff21514d8981	295	#define RCC_PLLP_DIV20 ((uint32_t)0x00000014U) /!< PLLP division factor = 20 /
AnnaBridge	156:ff21514d8981	296	#define RCC_PLLP_DIV21 ((uint32_t)0x00000015U) /!< PLLP division factor = 21 /
AnnaBridge	156:ff21514d8981	297	#define RCC_PLLP_DIV22 ((uint32_t)0x00000016U) /!< PLLP division factor = 22 /
AnnaBridge	156:ff21514d8981	298	#define RCC_PLLP_DIV23 ((uint32_t)0x00000017U) /!< PLLP division factor = 23 /
AnnaBridge	156:ff21514d8981	299	#define RCC_PLLP_DIV24 ((uint32_t)0x00000018U) /!< PLLP division factor = 24 /
AnnaBridge	156:ff21514d8981	300	#define RCC_PLLP_DIV25 ((uint32_t)0x00000019U) /!< PLLP division factor = 25 /
AnnaBridge	156:ff21514d8981	301	#define RCC_PLLP_DIV26 ((uint32_t)0x0000001AU) /!< PLLP division factor = 26 /
AnnaBridge	156:ff21514d8981	302	#define RCC_PLLP_DIV27 ((uint32_t)0x0000001BU) /!< PLLP division factor = 27 /
AnnaBridge	156:ff21514d8981	303	#define RCC_PLLP_DIV28 ((uint32_t)0x0000001CU) /!< PLLP division factor = 28 /
AnnaBridge	156:ff21514d8981	304	#define RCC_PLLP_DIV29 ((uint32_t)0x0000001DU) /!< PLLP division factor = 29 /
AnnaBridge	156:ff21514d8981	305	#define RCC_PLLP_DIV30 ((uint32_t)0x0000001EU) /!< PLLP division factor = 30 /
AnnaBridge	156:ff21514d8981	306	#define RCC_PLLP_DIV31 ((uint32_t)0x0000001FU) /!< PLLP division factor = 31 /
AnnaBridge	156:ff21514d8981	307	#else
AnnaBridge	156:ff21514d8981	308	#define RCC_PLLP_DIV7 ((uint32_t)0x00000007U) /!< PLLP division factor = 7 /
AnnaBridge	156:ff21514d8981	309	#define RCC_PLLP_DIV17 ((uint32_t)0x00000011U) /!< PLLP division factor = 17 /
AnnaBridge	156:ff21514d8981	310	#endif /* RCC_PLLP_DIV_2_31_SUPPORT */
AnnaBridge	156:ff21514d8981	311	/**
AnnaBridge	156:ff21514d8981	312	* @}
AnnaBridge	156:ff21514d8981	313	*/
AnnaBridge	156:ff21514d8981	314
AnnaBridge	156:ff21514d8981	315	/** @defgroup RCC_PLLQ_Clock_Divider PLLQ Clock Divider
AnnaBridge	156:ff21514d8981	316	* @{
AnnaBridge	156:ff21514d8981	317	*/
AnnaBridge	156:ff21514d8981	318	#define RCC_PLLQ_DIV2 ((uint32_t)0x00000002U) /!< PLLQ division factor = 2 /
AnnaBridge	156:ff21514d8981	319	#define RCC_PLLQ_DIV4 ((uint32_t)0x00000004U) /!< PLLQ division factor = 4 /
AnnaBridge	156:ff21514d8981	320	#define RCC_PLLQ_DIV6 ((uint32_t)0x00000006U) /!< PLLQ division factor = 6 /
AnnaBridge	156:ff21514d8981	321	#define RCC_PLLQ_DIV8 ((uint32_t)0x00000008U) /!< PLLQ division factor = 8 /
AnnaBridge	156:ff21514d8981	322	/**
AnnaBridge	156:ff21514d8981	323	* @}
AnnaBridge	156:ff21514d8981	324	*/
AnnaBridge	156:ff21514d8981	325
AnnaBridge	156:ff21514d8981	326	/** @defgroup RCC_PLLR_Clock_Divider PLLR Clock Divider
AnnaBridge	156:ff21514d8981	327	* @{
AnnaBridge	156:ff21514d8981	328	*/
AnnaBridge	156:ff21514d8981	329	#define RCC_PLLR_DIV2 ((uint32_t)0x00000002U) /!< PLLR division factor = 2 /
AnnaBridge	156:ff21514d8981	330	#define RCC_PLLR_DIV4 ((uint32_t)0x00000004U) /!< PLLR division factor = 4 /
AnnaBridge	156:ff21514d8981	331	#define RCC_PLLR_DIV6 ((uint32_t)0x00000006U) /!< PLLR division factor = 6 /
AnnaBridge	156:ff21514d8981	332	#define RCC_PLLR_DIV8 ((uint32_t)0x00000008U) /!< PLLR division factor = 8 /
AnnaBridge	156:ff21514d8981	333	/**
AnnaBridge	156:ff21514d8981	334	* @}
AnnaBridge	156:ff21514d8981	335	*/
AnnaBridge	156:ff21514d8981	336
AnnaBridge	156:ff21514d8981	337	/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
AnnaBridge	156:ff21514d8981	338	* @{
AnnaBridge	156:ff21514d8981	339	*/
AnnaBridge	156:ff21514d8981	340	#define RCC_PLLSOURCE_NONE ((uint32_t)0x00000000U) /!< No clock selected as PLL entry clock source /
AnnaBridge	156:ff21514d8981	341	#define RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_MSI /!< MSI clock selected as PLL entry clock source /
AnnaBridge	156:ff21514d8981	342	#define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /!< HSI clock selected as PLL entry clock source /
AnnaBridge	156:ff21514d8981	343	#define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /!< HSE clock selected as PLL entry clock source /
AnnaBridge	156:ff21514d8981	344	/**
AnnaBridge	156:ff21514d8981	345	* @}
AnnaBridge	156:ff21514d8981	346	*/
AnnaBridge	156:ff21514d8981	347
AnnaBridge	156:ff21514d8981	348	/** @defgroup RCC_PLL_Clock_Output PLL Clock Output
AnnaBridge	156:ff21514d8981	349	* @{
AnnaBridge	156:ff21514d8981	350	*/
AnnaBridge	156:ff21514d8981	351	#if defined(RCC_PLLSAI2_SUPPORT)
AnnaBridge	156:ff21514d8981	352	#define RCC_PLL_SAI3CLK RCC_PLLCFGR_PLLPEN /!< PLLSAI3CLK selection from main PLL (for devices with PLLSAI2) /
AnnaBridge	156:ff21514d8981	353	#else
AnnaBridge	156:ff21514d8981	354	#define RCC_PLL_SAI2CLK RCC_PLLCFGR_PLLPEN /!< PLLSAI2CLK selection from main PLL (for devices without PLLSAI2) /
AnnaBridge	156:ff21514d8981	355	#endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge	156:ff21514d8981	356	#define RCC_PLL_48M1CLK RCC_PLLCFGR_PLLQEN /!< PLL48M1CLK selection from main PLL /
AnnaBridge	156:ff21514d8981	357	#define RCC_PLL_SYSCLK RCC_PLLCFGR_PLLREN /!< PLLCLK selection from main PLL /
AnnaBridge	156:ff21514d8981	358	/**
AnnaBridge	156:ff21514d8981	359	* @}
AnnaBridge	156:ff21514d8981	360	*/
AnnaBridge	156:ff21514d8981	361
AnnaBridge	156:ff21514d8981	362	/** @defgroup RCC_PLLSAI1_Clock_Output PLLSAI1 Clock Output
AnnaBridge	156:ff21514d8981	363	* @{
AnnaBridge	156:ff21514d8981	364	*/
AnnaBridge	156:ff21514d8981	365	#define RCC_PLLSAI1_SAI1CLK RCC_PLLSAI1CFGR_PLLSAI1PEN /!< PLLSAI1CLK selection from PLLSAI1 /
AnnaBridge	156:ff21514d8981	366	#define RCC_PLLSAI1_48M2CLK RCC_PLLSAI1CFGR_PLLSAI1QEN /!< PLL48M2CLK selection from PLLSAI1 /
AnnaBridge	156:ff21514d8981	367	#define RCC_PLLSAI1_ADC1CLK RCC_PLLSAI1CFGR_PLLSAI1REN /!< PLLADC1CLK selection from PLLSAI1 /
AnnaBridge	156:ff21514d8981	368	/**
AnnaBridge	156:ff21514d8981	369	* @}
AnnaBridge	156:ff21514d8981	370	*/
AnnaBridge	156:ff21514d8981	371
AnnaBridge	156:ff21514d8981	372	#if defined(RCC_PLLSAI2_SUPPORT)
AnnaBridge	156:ff21514d8981	373
AnnaBridge	156:ff21514d8981	374	/** @defgroup RCC_PLLSAI2_Clock_Output PLLSAI2 Clock Output
AnnaBridge	156:ff21514d8981	375	* @{
AnnaBridge	156:ff21514d8981	376	*/
AnnaBridge	156:ff21514d8981	377	#define RCC_PLLSAI2_SAI2CLK RCC_PLLSAI2CFGR_PLLSAI2PEN /!< PLLSAI2CLK selection from PLLSAI2 /
AnnaBridge	156:ff21514d8981	378	#define RCC_PLLSAI2_ADC2CLK RCC_PLLSAI2CFGR_PLLSAI2REN /!< PLLADC2CLK selection from PLLSAI2 /
AnnaBridge	156:ff21514d8981	379	/**
AnnaBridge	156:ff21514d8981	380	* @}
AnnaBridge	156:ff21514d8981	381	*/
AnnaBridge	156:ff21514d8981	382
AnnaBridge	156:ff21514d8981	383	#endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge	156:ff21514d8981	384
AnnaBridge	156:ff21514d8981	385	/** @defgroup RCC_MSI_Clock_Range MSI Clock Range
AnnaBridge	156:ff21514d8981	386	* @{
AnnaBridge	156:ff21514d8981	387	*/
AnnaBridge	156:ff21514d8981	388	#define RCC_MSIRANGE_0 RCC_CR_MSIRANGE_0 /!< MSI = 100 KHz /
AnnaBridge	156:ff21514d8981	389	#define RCC_MSIRANGE_1 RCC_CR_MSIRANGE_1 /!< MSI = 200 KHz /
AnnaBridge	156:ff21514d8981	390	#define RCC_MSIRANGE_2 RCC_CR_MSIRANGE_2 /!< MSI = 400 KHz /
AnnaBridge	156:ff21514d8981	391	#define RCC_MSIRANGE_3 RCC_CR_MSIRANGE_3 /!< MSI = 800 KHz /
AnnaBridge	156:ff21514d8981	392	#define RCC_MSIRANGE_4 RCC_CR_MSIRANGE_4 /!< MSI = 1 MHz /
AnnaBridge	156:ff21514d8981	393	#define RCC_MSIRANGE_5 RCC_CR_MSIRANGE_5 /!< MSI = 2 MHz /
AnnaBridge	156:ff21514d8981	394	#define RCC_MSIRANGE_6 RCC_CR_MSIRANGE_6 /!< MSI = 4 MHz /
AnnaBridge	156:ff21514d8981	395	#define RCC_MSIRANGE_7 RCC_CR_MSIRANGE_7 /!< MSI = 8 MHz /
AnnaBridge	156:ff21514d8981	396	#define RCC_MSIRANGE_8 RCC_CR_MSIRANGE_8 /!< MSI = 16 MHz /
AnnaBridge	156:ff21514d8981	397	#define RCC_MSIRANGE_9 RCC_CR_MSIRANGE_9 /!< MSI = 24 MHz /
AnnaBridge	156:ff21514d8981	398	#define RCC_MSIRANGE_10 RCC_CR_MSIRANGE_10 /!< MSI = 32 MHz /
AnnaBridge	156:ff21514d8981	399	#define RCC_MSIRANGE_11 RCC_CR_MSIRANGE_11 /!< MSI = 48 MHz /
AnnaBridge	156:ff21514d8981	400	/**
AnnaBridge	156:ff21514d8981	401	* @}
AnnaBridge	156:ff21514d8981	402	*/
AnnaBridge	156:ff21514d8981	403
AnnaBridge	156:ff21514d8981	404	/** @defgroup RCC_System_Clock_Type System Clock Type
AnnaBridge	156:ff21514d8981	405	* @{
AnnaBridge	156:ff21514d8981	406	*/
AnnaBridge	156:ff21514d8981	407	#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001U) /!< SYSCLK to configure /
AnnaBridge	156:ff21514d8981	408	#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002U) /!< HCLK to configure /
AnnaBridge	156:ff21514d8981	409	#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004U) /!< PCLK1 to configure /
AnnaBridge	156:ff21514d8981	410	#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008U) /!< PCLK2 to configure /
AnnaBridge	156:ff21514d8981	411	/**
AnnaBridge	156:ff21514d8981	412	* @}
AnnaBridge	156:ff21514d8981	413	*/
AnnaBridge	156:ff21514d8981	414
AnnaBridge	156:ff21514d8981	415	/** @defgroup RCC_System_Clock_Source System Clock Source
AnnaBridge	156:ff21514d8981	416	* @{
AnnaBridge	156:ff21514d8981	417	*/
AnnaBridge	156:ff21514d8981	418	#define RCC_SYSCLKSOURCE_MSI RCC_CFGR_SW_MSI /!< MSI selection as system clock /
AnnaBridge	156:ff21514d8981	419	#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /!< HSI selection as system clock /
AnnaBridge	156:ff21514d8981	420	#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /!< HSE selection as system clock /
AnnaBridge	156:ff21514d8981	421	#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /!< PLL selection as system clock /
AnnaBridge	156:ff21514d8981	422	/**
AnnaBridge	156:ff21514d8981	423	* @}
AnnaBridge	156:ff21514d8981	424	*/
AnnaBridge	156:ff21514d8981	425
AnnaBridge	156:ff21514d8981	426	/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
AnnaBridge	156:ff21514d8981	427	* @{
AnnaBridge	156:ff21514d8981	428	*/
AnnaBridge	156:ff21514d8981	429	#define RCC_SYSCLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI /!< MSI used as system clock /
AnnaBridge	156:ff21514d8981	430	#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /!< HSI used as system clock /
AnnaBridge	156:ff21514d8981	431	#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /!< HSE used as system clock /
AnnaBridge	156:ff21514d8981	432	#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /!< PLL used as system clock /
AnnaBridge	156:ff21514d8981	433	/**
AnnaBridge	156:ff21514d8981	434	* @}
AnnaBridge	156:ff21514d8981	435	*/
AnnaBridge	156:ff21514d8981	436
AnnaBridge	156:ff21514d8981	437	/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
AnnaBridge	156:ff21514d8981	438	* @{
AnnaBridge	156:ff21514d8981	439	*/
AnnaBridge	156:ff21514d8981	440	#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /!< SYSCLK not divided /
AnnaBridge	156:ff21514d8981	441	#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /!< SYSCLK divided by 2 /
AnnaBridge	156:ff21514d8981	442	#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /!< SYSCLK divided by 4 /
AnnaBridge	156:ff21514d8981	443	#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /!< SYSCLK divided by 8 /
AnnaBridge	156:ff21514d8981	444	#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /!< SYSCLK divided by 16 /
AnnaBridge	156:ff21514d8981	445	#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /!< SYSCLK divided by 64 /
AnnaBridge	156:ff21514d8981	446	#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /!< SYSCLK divided by 128 /
AnnaBridge	156:ff21514d8981	447	#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /!< SYSCLK divided by 256 /
AnnaBridge	156:ff21514d8981	448	#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /!< SYSCLK divided by 512 /
AnnaBridge	156:ff21514d8981	449	/**
AnnaBridge	156:ff21514d8981	450	* @}
AnnaBridge	156:ff21514d8981	451	*/
AnnaBridge	156:ff21514d8981	452
AnnaBridge	156:ff21514d8981	453	/** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source
AnnaBridge	156:ff21514d8981	454	* @{
AnnaBridge	156:ff21514d8981	455	*/
AnnaBridge	156:ff21514d8981	456	#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /!< HCLK not divided /
AnnaBridge	156:ff21514d8981	457	#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /!< HCLK divided by 2 /
AnnaBridge	156:ff21514d8981	458	#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /!< HCLK divided by 4 /
AnnaBridge	156:ff21514d8981	459	#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /!< HCLK divided by 8 /
AnnaBridge	156:ff21514d8981	460	#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /!< HCLK divided by 16 /
AnnaBridge	156:ff21514d8981	461	/**
AnnaBridge	156:ff21514d8981	462	* @}
AnnaBridge	156:ff21514d8981	463	*/
AnnaBridge	156:ff21514d8981	464
AnnaBridge	156:ff21514d8981	465	/** @defgroup RCC_RTC_Clock_Source RTC Clock Source
AnnaBridge	156:ff21514d8981	466	* @{
AnnaBridge	156:ff21514d8981	467	*/
AnnaBridge	156:ff21514d8981	468	#define RCC_RTCCLKSOURCE_NO_CLK ((uint32_t)0x00000000U) /!< No clock used as RTC clock /
AnnaBridge	156:ff21514d8981	469	#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /!< LSE oscillator clock used as RTC clock /
AnnaBridge	156:ff21514d8981	470	#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /!< LSI oscillator clock used as RTC clock /
AnnaBridge	156:ff21514d8981	471	#define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /!< HSE oscillator clock divided by 32 used as RTC clock /
AnnaBridge	156:ff21514d8981	472	/**
AnnaBridge	156:ff21514d8981	473	* @}
AnnaBridge	156:ff21514d8981	474	*/
AnnaBridge	156:ff21514d8981	475
AnnaBridge	156:ff21514d8981	476	/** @defgroup RCC_MCO_Index MCO Index
AnnaBridge	156:ff21514d8981	477	* @{
AnnaBridge	156:ff21514d8981	478	*/
AnnaBridge	156:ff21514d8981	479	#define RCC_MCO1 ((uint32_t)0x00000000U)
AnnaBridge	156:ff21514d8981	480	#define RCC_MCO RCC_MCO1 /!< MCO1 to be compliant with other families with 2 MCOs/
AnnaBridge	156:ff21514d8981	481	/**
AnnaBridge	156:ff21514d8981	482	* @}
AnnaBridge	156:ff21514d8981	483	*/
AnnaBridge	156:ff21514d8981	484
AnnaBridge	156:ff21514d8981	485	/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
AnnaBridge	156:ff21514d8981	486	* @{
AnnaBridge	156:ff21514d8981	487	*/
AnnaBridge	156:ff21514d8981	488	#define RCC_MCO1SOURCE_NOCLOCK ((uint32_t)0x00000000U) /!< MCO1 output disabled, no clock on MCO1 /
AnnaBridge	156:ff21514d8981	489	#define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /!< SYSCLK selection as MCO1 source /
AnnaBridge	156:ff21514d8981	490	#define RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_1 /!< MSI selection as MCO1 source /
AnnaBridge	156:ff21514d8981	491	#define RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0\| RCC_CFGR_MCOSEL_1) /!< HSI selection as MCO1 source /
AnnaBridge	156:ff21514d8981	492	#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /!< HSE selection as MCO1 source /
AnnaBridge	156:ff21514d8981	493	#define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0\|RCC_CFGR_MCOSEL_2) /!< PLLCLK selection as MCO1 source /
AnnaBridge	156:ff21514d8981	494	#define RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1\|RCC_CFGR_MCOSEL_2) /!< LSI selection as MCO1 source /
AnnaBridge	156:ff21514d8981	495	#define RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0\|RCC_CFGR_MCOSEL_1\|RCC_CFGR_MCOSEL_2) /!< LSE selection as MCO1 source /
AnnaBridge	156:ff21514d8981	496	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	156:ff21514d8981	497	#define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_3 /!< HSI48 selection as MCO1 source (STM32L43x/STM32L44x devices) /
AnnaBridge	156:ff21514d8981	498	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	156:ff21514d8981	499	/**
AnnaBridge	156:ff21514d8981	500	* @}
AnnaBridge	156:ff21514d8981	501	*/
AnnaBridge	156:ff21514d8981	502
AnnaBridge	156:ff21514d8981	503	/** @defgroup RCC_MCOx_Clock_Prescaler MCO1 Clock Prescaler
AnnaBridge	156:ff21514d8981	504	* @{
AnnaBridge	156:ff21514d8981	505	*/
AnnaBridge	156:ff21514d8981	506	#define RCC_MCODIV_1 RCC_CFGR_MCOPRE_DIV1 /!< MCO not divided /
AnnaBridge	156:ff21514d8981	507	#define RCC_MCODIV_2 RCC_CFGR_MCOPRE_DIV2 /!< MCO divided by 2 /
AnnaBridge	156:ff21514d8981	508	#define RCC_MCODIV_4 RCC_CFGR_MCOPRE_DIV4 /!< MCO divided by 4 /
AnnaBridge	156:ff21514d8981	509	#define RCC_MCODIV_8 RCC_CFGR_MCOPRE_DIV8 /!< MCO divided by 8 /
AnnaBridge	156:ff21514d8981	510	#define RCC_MCODIV_16 RCC_CFGR_MCOPRE_DIV16 /!< MCO divided by 16 /
AnnaBridge	156:ff21514d8981	511	/**
AnnaBridge	156:ff21514d8981	512	* @}
AnnaBridge	156:ff21514d8981	513	*/
AnnaBridge	156:ff21514d8981	514
AnnaBridge	156:ff21514d8981	515	/** @defgroup RCC_Interrupt Interrupts
AnnaBridge	156:ff21514d8981	516	* @{
AnnaBridge	156:ff21514d8981	517	*/
AnnaBridge	156:ff21514d8981	518	#define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF /!< LSI Ready Interrupt flag /
AnnaBridge	156:ff21514d8981	519	#define RCC_IT_LSERDY RCC_CIFR_LSERDYF /!< LSE Ready Interrupt flag /
AnnaBridge	156:ff21514d8981	520	#define RCC_IT_MSIRDY RCC_CIFR_MSIRDYF /!< MSI Ready Interrupt flag /
AnnaBridge	156:ff21514d8981	521	#define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF /!< HSI16 Ready Interrupt flag /
AnnaBridge	156:ff21514d8981	522	#define RCC_IT_HSERDY RCC_CIFR_HSERDYF /!< HSE Ready Interrupt flag /
AnnaBridge	156:ff21514d8981	523	#define RCC_IT_PLLRDY RCC_CIFR_PLLRDYF /!< PLL Ready Interrupt flag /
AnnaBridge	156:ff21514d8981	524	#define RCC_IT_PLLSAI1RDY RCC_CIFR_PLLSAI1RDYF /!< PLLSAI1 Ready Interrupt flag /
AnnaBridge	156:ff21514d8981	525	#if defined(RCC_PLLSAI2_SUPPORT)
AnnaBridge	156:ff21514d8981	526	#define RCC_IT_PLLSAI2RDY RCC_CIFR_PLLSAI2RDYF /!< PLLSAI2 Ready Interrupt flag /
AnnaBridge	156:ff21514d8981	527	#endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge	156:ff21514d8981	528	#define RCC_IT_CSS RCC_CIFR_CSSF /!< Clock Security System Interrupt flag /
AnnaBridge	156:ff21514d8981	529	#define RCC_IT_LSECSS RCC_CIFR_LSECSSF /!< LSE Clock Security System Interrupt flag /
AnnaBridge	156:ff21514d8981	530	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	156:ff21514d8981	531	#define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF /!< HSI48 Ready Interrupt flag /
AnnaBridge	156:ff21514d8981	532	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	156:ff21514d8981	533	/**
AnnaBridge	156:ff21514d8981	534	* @}
AnnaBridge	156:ff21514d8981	535	*/
AnnaBridge	156:ff21514d8981	536
AnnaBridge	156:ff21514d8981	537	/** @defgroup RCC_Flag Flags
AnnaBridge	156:ff21514d8981	538	* Elements values convention: XXXYYYYYb
AnnaBridge	156:ff21514d8981	539	* - YYYYY : Flag position in the register
AnnaBridge	156:ff21514d8981	540	* - XXX : Register index
AnnaBridge	156:ff21514d8981	541	* - 001: CR register
AnnaBridge	156:ff21514d8981	542	* - 010: BDCR register
AnnaBridge	156:ff21514d8981	543	* - 011: CSR register
AnnaBridge	156:ff21514d8981	544	* - 100: CRRCR register
AnnaBridge	156:ff21514d8981	545	* @{
AnnaBridge	156:ff21514d8981	546	*/
AnnaBridge	156:ff21514d8981	547	/* Flags in the CR register */
AnnaBridge	156:ff21514d8981	548	#define RCC_FLAG_MSIRDY ((uint32_t)((CR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CR_MSIRDY))) /!< MSI Ready flag /
AnnaBridge	156:ff21514d8981	549	#define RCC_FLAG_HSIRDY ((uint32_t)((CR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CR_HSIRDY))) /!< HSI Ready flag /
AnnaBridge	156:ff21514d8981	550	#define RCC_FLAG_HSERDY ((uint32_t)((CR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CR_HSERDY))) /!< HSE Ready flag /
AnnaBridge	156:ff21514d8981	551	#define RCC_FLAG_PLLRDY ((uint32_t)((CR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CR_PLLRDY))) /!< PLL Ready flag /
AnnaBridge	156:ff21514d8981	552	#define RCC_FLAG_PLLSAI1RDY ((uint32_t)((CR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CR_PLLSAI1RDY))) /!< PLLSAI1 Ready flag /
AnnaBridge	156:ff21514d8981	553	#if defined(RCC_PLLSAI2_SUPPORT)
AnnaBridge	156:ff21514d8981	554	#define RCC_FLAG_PLLSAI2RDY ((uint32_t)((CR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CR_PLLSAI2RDY))) /!< PLLSAI2 Ready flag /
AnnaBridge	156:ff21514d8981	555	#endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge	156:ff21514d8981	556
AnnaBridge	156:ff21514d8981	557	/* Flags in the BDCR register */
AnnaBridge	156:ff21514d8981	558	#define RCC_FLAG_LSERDY ((uint32_t)((BDCR_REG_INDEX << 5U) \| POSITION_VAL(RCC_BDCR_LSERDY))) /!< LSE Ready flag /
AnnaBridge	156:ff21514d8981	559	#define RCC_FLAG_LSECSSD ((uint32_t)((BDCR_REG_INDEX << 5U) \| POSITION_VAL(RCC_BDCR_LSECSSD))) /!< LSE Clock Security System Interrupt flag /
AnnaBridge	156:ff21514d8981	560
AnnaBridge	156:ff21514d8981	561	/* Flags in the CSR register */
AnnaBridge	156:ff21514d8981	562	#define RCC_FLAG_LSIRDY ((uint32_t)((CSR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CSR_LSIRDY))) /!< LSI Ready flag /
AnnaBridge	156:ff21514d8981	563	#define RCC_FLAG_RMVF ((uint32_t)((CSR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CSR_RMVF))) /!< Remove reset flag /
AnnaBridge	156:ff21514d8981	564	#define RCC_FLAG_FWRST ((uint32_t)((CSR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CSR_FWRSTF))) /!< Firewall reset flag /
AnnaBridge	156:ff21514d8981	565	#define RCC_FLAG_OBLRST ((uint32_t)((CSR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CSR_OBLRSTF))) /!< Option Byte Loader reset flag /
AnnaBridge	156:ff21514d8981	566	#define RCC_FLAG_PINRST ((uint32_t)((CSR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CSR_PINRSTF))) /!< PIN reset flag /
AnnaBridge	156:ff21514d8981	567	#define RCC_FLAG_BORRST ((uint32_t)((CSR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CSR_BORRSTF))) /!< BOR reset flag /
AnnaBridge	156:ff21514d8981	568	#define RCC_FLAG_SFTRST ((uint32_t)((CSR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CSR_SFTRSTF))) /!< Software Reset flag /
AnnaBridge	156:ff21514d8981	569	#define RCC_FLAG_IWDGRST ((uint32_t)((CSR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CSR_IWDGRSTF))) /!< Independent Watchdog reset flag /
AnnaBridge	156:ff21514d8981	570	#define RCC_FLAG_WWDGRST ((uint32_t)((CSR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CSR_WWDGRSTF))) /!< Window watchdog reset flag /
AnnaBridge	156:ff21514d8981	571	#define RCC_FLAG_LPWRRST ((uint32_t)((CSR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CSR_LPWRRSTF))) /!< Low-Power reset flag /
AnnaBridge	156:ff21514d8981	572
AnnaBridge	156:ff21514d8981	573	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	156:ff21514d8981	574	/* Flags in the CRRCR register */
AnnaBridge	156:ff21514d8981	575	#define RCC_FLAG_HSI48RDY ((uint32_t)((CRRCR_REG_INDEX << 5U) \| POSITION_VAL(RCC_CRRCR_HSI48RDY))) /!< HSI48 Ready flag /
AnnaBridge	156:ff21514d8981	576	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	156:ff21514d8981	577	/**
AnnaBridge	156:ff21514d8981	578	* @}
AnnaBridge	156:ff21514d8981	579	*/
AnnaBridge	156:ff21514d8981	580
AnnaBridge	156:ff21514d8981	581	/** @defgroup RCC_LSEDrive_Config LSE Drive Config
AnnaBridge	156:ff21514d8981	582	* @{
AnnaBridge	156:ff21514d8981	583	*/
AnnaBridge	156:ff21514d8981	584	#define RCC_LSEDRIVE_LOW ((uint32_t)0x00000000U) /!< LSE low drive capability /
AnnaBridge	156:ff21514d8981	585	#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /!< LSE medium low drive capability /
AnnaBridge	156:ff21514d8981	586	#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /!< LSE medium high drive capability /
AnnaBridge	156:ff21514d8981	587	#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /!< LSE high drive capability /
AnnaBridge	156:ff21514d8981	588	/**
AnnaBridge	156:ff21514d8981	589	* @}
AnnaBridge	156:ff21514d8981	590	*/
AnnaBridge	156:ff21514d8981	591
AnnaBridge	156:ff21514d8981	592	/** @defgroup RCC_Stop_WakeUpClock Wake-Up from STOP Clock
AnnaBridge	156:ff21514d8981	593	* @{
AnnaBridge	156:ff21514d8981	594	*/
AnnaBridge	156:ff21514d8981	595	#define RCC_STOP_WAKEUPCLOCK_MSI ((uint32_t)0x00000000U) /!< MSI selection after wake-up from STOP /
AnnaBridge	156:ff21514d8981	596	#define RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK /!< HSI selection after wake-up from STOP /
AnnaBridge	156:ff21514d8981	597	/**
AnnaBridge	156:ff21514d8981	598	* @}
AnnaBridge	156:ff21514d8981	599	*/
AnnaBridge	156:ff21514d8981	600
AnnaBridge	156:ff21514d8981	601	/**
AnnaBridge	156:ff21514d8981	602	* @}
AnnaBridge	156:ff21514d8981	603	*/
AnnaBridge	156:ff21514d8981	604
AnnaBridge	156:ff21514d8981	605	/* Exported macros -----------------------------------------------------------*/
AnnaBridge	156:ff21514d8981	606
AnnaBridge	156:ff21514d8981	607	/** @defgroup RCC_Exported_Macros RCC Exported Macros
AnnaBridge	156:ff21514d8981	608	* @{
AnnaBridge	156:ff21514d8981	609	*/
AnnaBridge	156:ff21514d8981	610
AnnaBridge	156:ff21514d8981	611	/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
AnnaBridge	156:ff21514d8981	612	* @brief Enable or disable the AHB1 peripheral clock.
AnnaBridge	156:ff21514d8981	613	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	614	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	615	* using it.
AnnaBridge	156:ff21514d8981	616	* @{
AnnaBridge	156:ff21514d8981	617	*/
AnnaBridge	156:ff21514d8981	618
AnnaBridge	156:ff21514d8981	619	#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	620	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	621	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
AnnaBridge	156:ff21514d8981	622	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	623	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
AnnaBridge	156:ff21514d8981	624	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	625	} while(0)
AnnaBridge	156:ff21514d8981	626
AnnaBridge	156:ff21514d8981	627	#define __HAL_RCC_DMA2_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	628	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	629	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
AnnaBridge	156:ff21514d8981	630	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	631	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
AnnaBridge	156:ff21514d8981	632	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	633	} while(0)
AnnaBridge	156:ff21514d8981	634
AnnaBridge	156:ff21514d8981	635	#define __HAL_RCC_FLASH_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	636	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	637	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
AnnaBridge	156:ff21514d8981	638	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	639	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
AnnaBridge	156:ff21514d8981	640	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	641	} while(0)
AnnaBridge	156:ff21514d8981	642
AnnaBridge	156:ff21514d8981	643	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	644	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	645	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
AnnaBridge	156:ff21514d8981	646	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	647	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
AnnaBridge	156:ff21514d8981	648	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	649	} while(0)
AnnaBridge	156:ff21514d8981	650
AnnaBridge	156:ff21514d8981	651	#define __HAL_RCC_TSC_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	652	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	653	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \
AnnaBridge	156:ff21514d8981	654	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	655	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \
AnnaBridge	156:ff21514d8981	656	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	657	} while(0)
AnnaBridge	156:ff21514d8981	658
AnnaBridge	156:ff21514d8981	659	#if defined(DMA2D)
AnnaBridge	156:ff21514d8981	660	#define __HAL_RCC_DMA2D_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	661	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	662	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN); \
AnnaBridge	156:ff21514d8981	663	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	664	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN); \
AnnaBridge	156:ff21514d8981	665	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	666	} while(0)
AnnaBridge	156:ff21514d8981	667	#endif /* DMA2D */
AnnaBridge	156:ff21514d8981	668
AnnaBridge	156:ff21514d8981	669
AnnaBridge	156:ff21514d8981	670	#define __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN)
AnnaBridge	156:ff21514d8981	671
AnnaBridge	156:ff21514d8981	672	#define __HAL_RCC_DMA2_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN)
AnnaBridge	156:ff21514d8981	673
AnnaBridge	156:ff21514d8981	674	#define __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN)
AnnaBridge	156:ff21514d8981	675
AnnaBridge	156:ff21514d8981	676	#define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN)
AnnaBridge	156:ff21514d8981	677
AnnaBridge	156:ff21514d8981	678	#define __HAL_RCC_TSC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN)
AnnaBridge	156:ff21514d8981	679
AnnaBridge	156:ff21514d8981	680	#if defined(DMA2D)
AnnaBridge	156:ff21514d8981	681	#define __HAL_RCC_DMA2D_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN)
AnnaBridge	156:ff21514d8981	682	#endif /* DMA2D */
AnnaBridge	156:ff21514d8981	683
AnnaBridge	156:ff21514d8981	684	/**
AnnaBridge	156:ff21514d8981	685	* @}
AnnaBridge	156:ff21514d8981	686	*/
AnnaBridge	156:ff21514d8981	687
AnnaBridge	156:ff21514d8981	688	/** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
AnnaBridge	156:ff21514d8981	689	* @brief Enable or disable the AHB2 peripheral clock.
AnnaBridge	156:ff21514d8981	690	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	691	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	692	* using it.
AnnaBridge	156:ff21514d8981	693	* @{
AnnaBridge	156:ff21514d8981	694	*/
AnnaBridge	156:ff21514d8981	695
AnnaBridge	156:ff21514d8981	696	#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	697	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	698	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
AnnaBridge	156:ff21514d8981	699	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	700	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
AnnaBridge	156:ff21514d8981	701	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	702	} while(0)
AnnaBridge	156:ff21514d8981	703
AnnaBridge	156:ff21514d8981	704	#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	705	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	706	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
AnnaBridge	156:ff21514d8981	707	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	708	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
AnnaBridge	156:ff21514d8981	709	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	710	} while(0)
AnnaBridge	156:ff21514d8981	711
AnnaBridge	156:ff21514d8981	712	#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	713	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	714	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \
AnnaBridge	156:ff21514d8981	715	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	716	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \
AnnaBridge	156:ff21514d8981	717	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	718	} while(0)
AnnaBridge	156:ff21514d8981	719
AnnaBridge	156:ff21514d8981	720	#if defined(GPIOD)
AnnaBridge	156:ff21514d8981	721	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	722	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	723	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \
AnnaBridge	156:ff21514d8981	724	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	725	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \
AnnaBridge	156:ff21514d8981	726	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	727	} while(0)
AnnaBridge	156:ff21514d8981	728	#endif /* GPIOD */
AnnaBridge	156:ff21514d8981	729
AnnaBridge	156:ff21514d8981	730	#if defined(GPIOE)
AnnaBridge	156:ff21514d8981	731	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	732	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	733	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \
AnnaBridge	156:ff21514d8981	734	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	735	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \
AnnaBridge	156:ff21514d8981	736	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	737	} while(0)
AnnaBridge	156:ff21514d8981	738	#endif /* GPIOE */
AnnaBridge	156:ff21514d8981	739
AnnaBridge	156:ff21514d8981	740	#if defined(GPIOF)
AnnaBridge	156:ff21514d8981	741	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	742	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	743	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \
AnnaBridge	156:ff21514d8981	744	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	745	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \
AnnaBridge	156:ff21514d8981	746	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	747	} while(0)
AnnaBridge	156:ff21514d8981	748	#endif /* GPIOF */
AnnaBridge	156:ff21514d8981	749
AnnaBridge	156:ff21514d8981	750	#if defined(GPIOG)
AnnaBridge	156:ff21514d8981	751	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	752	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	753	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \
AnnaBridge	156:ff21514d8981	754	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	755	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \
AnnaBridge	156:ff21514d8981	756	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	757	} while(0)
AnnaBridge	156:ff21514d8981	758	#endif /* GPIOG */
AnnaBridge	156:ff21514d8981	759
AnnaBridge	156:ff21514d8981	760	#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	761	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	762	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \
AnnaBridge	156:ff21514d8981	763	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	764	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \
AnnaBridge	156:ff21514d8981	765	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	766	} while(0)
AnnaBridge	156:ff21514d8981	767
AnnaBridge	156:ff21514d8981	768	#if defined(GPIOI)
AnnaBridge	156:ff21514d8981	769	#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	770	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	771	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN); \
AnnaBridge	156:ff21514d8981	772	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	773	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN); \
AnnaBridge	156:ff21514d8981	774	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	775	} while(0)
AnnaBridge	156:ff21514d8981	776	#endif /* GPIOI */
AnnaBridge	156:ff21514d8981	777
AnnaBridge	156:ff21514d8981	778	#if defined(USB_OTG_FS)
AnnaBridge	156:ff21514d8981	779	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	780	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	781	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); \
AnnaBridge	156:ff21514d8981	782	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	783	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); \
AnnaBridge	156:ff21514d8981	784	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	785	} while(0)
AnnaBridge	156:ff21514d8981	786	#endif /* USB_OTG_FS */
AnnaBridge	156:ff21514d8981	787
AnnaBridge	156:ff21514d8981	788	#define __HAL_RCC_ADC_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	789	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	790	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \
AnnaBridge	156:ff21514d8981	791	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	792	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \
AnnaBridge	156:ff21514d8981	793	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	794	} while(0)
AnnaBridge	156:ff21514d8981	795
AnnaBridge	156:ff21514d8981	796	#if defined(DCMI)
AnnaBridge	156:ff21514d8981	797	#define __HAL_RCC_DCMI_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	798	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	799	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN); \
AnnaBridge	156:ff21514d8981	800	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	801	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN); \
AnnaBridge	156:ff21514d8981	802	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	803	} while(0)
AnnaBridge	156:ff21514d8981	804	#endif /* DCMI */
AnnaBridge	156:ff21514d8981	805
AnnaBridge	156:ff21514d8981	806	#if defined(AES)
AnnaBridge	156:ff21514d8981	807	#define __HAL_RCC_AES_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	808	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	809	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \
AnnaBridge	156:ff21514d8981	810	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	811	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \
AnnaBridge	156:ff21514d8981	812	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	813	} while(0)
AnnaBridge	156:ff21514d8981	814	#endif /* AES */
AnnaBridge	156:ff21514d8981	815
AnnaBridge	156:ff21514d8981	816	#if defined(HASH)
AnnaBridge	156:ff21514d8981	817	#define __HAL_RCC_HASH_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	818	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	819	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \
AnnaBridge	156:ff21514d8981	820	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	821	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \
AnnaBridge	156:ff21514d8981	822	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	823	} while(0)
AnnaBridge	156:ff21514d8981	824	#endif /* HASH */
AnnaBridge	156:ff21514d8981	825
AnnaBridge	156:ff21514d8981	826	#define __HAL_RCC_RNG_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	827	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	828	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \
AnnaBridge	156:ff21514d8981	829	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	830	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \
AnnaBridge	156:ff21514d8981	831	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	832	} while(0)
AnnaBridge	156:ff21514d8981	833
AnnaBridge	156:ff21514d8981	834
AnnaBridge	156:ff21514d8981	835	#define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN)
AnnaBridge	156:ff21514d8981	836
AnnaBridge	156:ff21514d8981	837	#define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN)
AnnaBridge	156:ff21514d8981	838
AnnaBridge	156:ff21514d8981	839	#define __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN)
AnnaBridge	156:ff21514d8981	840
AnnaBridge	156:ff21514d8981	841	#if defined(GPIOD)
AnnaBridge	156:ff21514d8981	842	#define __HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN)
AnnaBridge	156:ff21514d8981	843	#endif /* GPIOD */
AnnaBridge	156:ff21514d8981	844
AnnaBridge	156:ff21514d8981	845	#if defined(GPIOE)
AnnaBridge	156:ff21514d8981	846	#define __HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN)
AnnaBridge	156:ff21514d8981	847	#endif /* GPIOE */
AnnaBridge	156:ff21514d8981	848
AnnaBridge	156:ff21514d8981	849	#if defined(GPIOF)
AnnaBridge	156:ff21514d8981	850	#define __HAL_RCC_GPIOF_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN)
AnnaBridge	156:ff21514d8981	851	#endif /* GPIOF */
AnnaBridge	156:ff21514d8981	852
AnnaBridge	156:ff21514d8981	853	#if defined(GPIOG)
AnnaBridge	156:ff21514d8981	854	#define __HAL_RCC_GPIOG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN)
AnnaBridge	156:ff21514d8981	855	#endif /* GPIOG */
AnnaBridge	156:ff21514d8981	856
AnnaBridge	156:ff21514d8981	857	#define __HAL_RCC_GPIOH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN)
AnnaBridge	156:ff21514d8981	858
AnnaBridge	156:ff21514d8981	859	#if defined(GPIOI)
AnnaBridge	156:ff21514d8981	860	#define __HAL_RCC_GPIOI_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN)
AnnaBridge	156:ff21514d8981	861	#endif /* GPIOI */
AnnaBridge	156:ff21514d8981	862
AnnaBridge	156:ff21514d8981	863	#if defined(USB_OTG_FS)
AnnaBridge	156:ff21514d8981	864	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);
AnnaBridge	156:ff21514d8981	865	#endif /* USB_OTG_FS */
AnnaBridge	156:ff21514d8981	866
AnnaBridge	156:ff21514d8981	867	#define __HAL_RCC_ADC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN)
AnnaBridge	156:ff21514d8981	868
AnnaBridge	156:ff21514d8981	869	#if defined(DCMI)
AnnaBridge	156:ff21514d8981	870	#define __HAL_RCC_DCMI_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN)
AnnaBridge	156:ff21514d8981	871	#endif /* DCMI */
AnnaBridge	156:ff21514d8981	872
AnnaBridge	156:ff21514d8981	873	#if defined(AES)
AnnaBridge	156:ff21514d8981	874	#define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);
AnnaBridge	156:ff21514d8981	875	#endif /* AES */
AnnaBridge	156:ff21514d8981	876
AnnaBridge	156:ff21514d8981	877	#if defined(HASH)
AnnaBridge	156:ff21514d8981	878	#define __HAL_RCC_HASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN)
AnnaBridge	156:ff21514d8981	879	#endif /* HASH */
AnnaBridge	156:ff21514d8981	880
AnnaBridge	156:ff21514d8981	881	#define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN)
AnnaBridge	156:ff21514d8981	882
AnnaBridge	156:ff21514d8981	883	/**
AnnaBridge	156:ff21514d8981	884	* @}
AnnaBridge	156:ff21514d8981	885	*/
AnnaBridge	156:ff21514d8981	886
AnnaBridge	156:ff21514d8981	887	/** @defgroup RCC_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
AnnaBridge	156:ff21514d8981	888	* @brief Enable or disable the AHB3 peripheral clock.
AnnaBridge	156:ff21514d8981	889	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	890	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	891	* using it.
AnnaBridge	156:ff21514d8981	892	* @{
AnnaBridge	156:ff21514d8981	893	*/
AnnaBridge	156:ff21514d8981	894
AnnaBridge	156:ff21514d8981	895	#if defined(FMC_BANK1)
AnnaBridge	156:ff21514d8981	896	#define __HAL_RCC_FMC_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	897	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	898	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \
AnnaBridge	156:ff21514d8981	899	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	900	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \
AnnaBridge	156:ff21514d8981	901	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	902	} while(0)
AnnaBridge	156:ff21514d8981	903	#endif /* FMC_BANK1 */
AnnaBridge	156:ff21514d8981	904
AnnaBridge	156:ff21514d8981	905	#if defined(QUADSPI)
AnnaBridge	156:ff21514d8981	906	#define __HAL_RCC_QSPI_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	907	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	908	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \
AnnaBridge	156:ff21514d8981	909	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	910	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \
AnnaBridge	156:ff21514d8981	911	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	912	} while(0)
AnnaBridge	156:ff21514d8981	913	#endif /* QUADSPI */
AnnaBridge	156:ff21514d8981	914
AnnaBridge	156:ff21514d8981	915	#if defined(FMC_BANK1)
AnnaBridge	156:ff21514d8981	916	#define __HAL_RCC_FMC_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN)
AnnaBridge	156:ff21514d8981	917	#endif /* FMC_BANK1 */
AnnaBridge	156:ff21514d8981	918
AnnaBridge	156:ff21514d8981	919	#if defined(QUADSPI)
AnnaBridge	156:ff21514d8981	920	#define __HAL_RCC_QSPI_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN)
AnnaBridge	156:ff21514d8981	921	#endif /* QUADSPI */
AnnaBridge	156:ff21514d8981	922
AnnaBridge	156:ff21514d8981	923	/**
AnnaBridge	156:ff21514d8981	924	* @}
AnnaBridge	156:ff21514d8981	925	*/
AnnaBridge	156:ff21514d8981	926
AnnaBridge	156:ff21514d8981	927	/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
AnnaBridge	156:ff21514d8981	928	* @brief Enable or disable the APB1 peripheral clock.
AnnaBridge	156:ff21514d8981	929	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	930	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	931	* using it.
AnnaBridge	156:ff21514d8981	932	* @{
AnnaBridge	156:ff21514d8981	933	*/
AnnaBridge	156:ff21514d8981	934
AnnaBridge	156:ff21514d8981	935	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	936	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	937	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \
AnnaBridge	156:ff21514d8981	938	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	939	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \
AnnaBridge	156:ff21514d8981	940	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	941	} while(0)
AnnaBridge	156:ff21514d8981	942
AnnaBridge	156:ff21514d8981	943	#if defined(TIM3)
AnnaBridge	156:ff21514d8981	944	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	945	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	946	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \
AnnaBridge	156:ff21514d8981	947	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	948	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \
AnnaBridge	156:ff21514d8981	949	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	950	} while(0)
AnnaBridge	156:ff21514d8981	951	#endif /* TIM3 */
AnnaBridge	156:ff21514d8981	952
AnnaBridge	156:ff21514d8981	953	#if defined(TIM4)
AnnaBridge	156:ff21514d8981	954	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	955	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	956	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \
AnnaBridge	156:ff21514d8981	957	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	958	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \
AnnaBridge	156:ff21514d8981	959	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	960	} while(0)
AnnaBridge	156:ff21514d8981	961	#endif /* TIM4 */
AnnaBridge	156:ff21514d8981	962
AnnaBridge	156:ff21514d8981	963	#if defined(TIM5)
AnnaBridge	156:ff21514d8981	964	#define __HAL_RCC_TIM5_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	965	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	966	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \
AnnaBridge	156:ff21514d8981	967	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	968	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \
AnnaBridge	156:ff21514d8981	969	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	970	} while(0)
AnnaBridge	156:ff21514d8981	971	#endif /* TIM5 */
AnnaBridge	156:ff21514d8981	972
AnnaBridge	156:ff21514d8981	973	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	974	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	975	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \
AnnaBridge	156:ff21514d8981	976	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	977	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \
AnnaBridge	156:ff21514d8981	978	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	979	} while(0)
AnnaBridge	156:ff21514d8981	980
AnnaBridge	156:ff21514d8981	981	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	982	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	983	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \
AnnaBridge	156:ff21514d8981	984	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	985	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \
AnnaBridge	156:ff21514d8981	986	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	987	} while(0)
AnnaBridge	156:ff21514d8981	988
AnnaBridge	156:ff21514d8981	989	#if defined(LCD)
AnnaBridge	156:ff21514d8981	990	#define __HAL_RCC_LCD_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	991	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	992	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); \
AnnaBridge	156:ff21514d8981	993	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	994	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); \
AnnaBridge	156:ff21514d8981	995	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	996	} while(0)
AnnaBridge	156:ff21514d8981	997	#endif /* LCD */
AnnaBridge	156:ff21514d8981	998
AnnaBridge	156:ff21514d8981	999	#if defined(RCC_APB1ENR1_RTCAPBEN)
AnnaBridge	156:ff21514d8981	1000	#define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1001	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	1002	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \
AnnaBridge	156:ff21514d8981	1003	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1004	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \
AnnaBridge	156:ff21514d8981	1005	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1006	} while(0)
AnnaBridge	156:ff21514d8981	1007	#endif /* RCC_APB1ENR1_RTCAPBEN */
AnnaBridge	156:ff21514d8981	1008
AnnaBridge	156:ff21514d8981	1009	#define __HAL_RCC_WWDG_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1010	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	1011	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \
AnnaBridge	156:ff21514d8981	1012	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1013	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \
AnnaBridge	156:ff21514d8981	1014	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1015	} while(0)
AnnaBridge	156:ff21514d8981	1016
AnnaBridge	156:ff21514d8981	1017	#if defined(SPI2)
AnnaBridge	156:ff21514d8981	1018	#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1019	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	1020	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \
AnnaBridge	156:ff21514d8981	1021	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1022	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \
AnnaBridge	156:ff21514d8981	1023	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1024	} while(0)
AnnaBridge	156:ff21514d8981	1025	#endif /* SPI2 */
AnnaBridge	156:ff21514d8981	1026
AnnaBridge	156:ff21514d8981	1027	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1028	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	1029	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \
AnnaBridge	156:ff21514d8981	1030	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1031	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \
AnnaBridge	156:ff21514d8981	1032	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1033	} while(0)
AnnaBridge	156:ff21514d8981	1034
AnnaBridge	156:ff21514d8981	1035	#define __HAL_RCC_USART2_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1036	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	1037	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \
AnnaBridge	156:ff21514d8981	1038	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1039	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \
AnnaBridge	156:ff21514d8981	1040	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1041	} while(0)
AnnaBridge	156:ff21514d8981	1042
AnnaBridge	156:ff21514d8981	1043	#if defined(USART3)
AnnaBridge	156:ff21514d8981	1044	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1045	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	1046	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \
AnnaBridge	156:ff21514d8981	1047	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1048	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \
AnnaBridge	156:ff21514d8981	1049	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1050	} while(0)
AnnaBridge	156:ff21514d8981	1051	#endif /* USART3 */
AnnaBridge	156:ff21514d8981	1052
AnnaBridge	156:ff21514d8981	1053	#if defined(UART4)
AnnaBridge	156:ff21514d8981	1054	#define __HAL_RCC_UART4_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1055	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	1056	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \
AnnaBridge	156:ff21514d8981	1057	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1058	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \
AnnaBridge	156:ff21514d8981	1059	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1060	} while(0)
AnnaBridge	156:ff21514d8981	1061	#endif /* UART4 */
AnnaBridge	156:ff21514d8981	1062
AnnaBridge	156:ff21514d8981	1063	#if defined(UART5)
AnnaBridge	156:ff21514d8981	1064	#define __HAL_RCC_UART5_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1065	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	1066	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \
AnnaBridge	156:ff21514d8981	1067	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1068	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \
AnnaBridge	156:ff21514d8981	1069	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1070	} while(0)
AnnaBridge	156:ff21514d8981	1071	#endif /* UART5 */
AnnaBridge	156:ff21514d8981	1072
AnnaBridge	156:ff21514d8981	1073	#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1074	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	1075	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \
AnnaBridge	156:ff21514d8981	1076	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1077	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \
AnnaBridge	156:ff21514d8981	1078	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1079	} while(0)
AnnaBridge	156:ff21514d8981	1080
AnnaBridge	156:ff21514d8981	1081	#if defined(I2C2)
AnnaBridge	156:ff21514d8981	1082	#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1083	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	1084	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \
AnnaBridge	156:ff21514d8981	1085	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1086	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \
AnnaBridge	156:ff21514d8981	1087	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1088	} while(0)
AnnaBridge	156:ff21514d8981	1089	#endif /* I2C2 */
AnnaBridge	156:ff21514d8981	1090
AnnaBridge	156:ff21514d8981	1091	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1092	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	1093	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \
AnnaBridge	156:ff21514d8981	1094	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1095	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \
AnnaBridge	156:ff21514d8981	1096	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1097	} while(0)
AnnaBridge	156:ff21514d8981	1098
AnnaBridge	156:ff21514d8981	1099	#if defined(I2C4)
AnnaBridge	156:ff21514d8981	1100	#define __HAL_RCC_I2C4_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1101	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	1102	SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \
AnnaBridge	156:ff21514d8981	1103	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1104	tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \
AnnaBridge	156:ff21514d8981	1105	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1106	} while(0)
AnnaBridge	156:ff21514d8981	1107	#endif /* I2C4 */
AnnaBridge	156:ff21514d8981	1108
AnnaBridge	156:ff21514d8981	1109	#if defined(CRS)
AnnaBridge	156:ff21514d8981	1110	#define __HAL_RCC_CRS_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1111	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	1112	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \
AnnaBridge	156:ff21514d8981	1113	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1114	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \
AnnaBridge	156:ff21514d8981	1115	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1116	} while(0)
AnnaBridge	156:ff21514d8981	1117	#endif /* CRS */
AnnaBridge	156:ff21514d8981	1118
AnnaBridge	156:ff21514d8981	1119	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1120	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	1121	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN); \
AnnaBridge	156:ff21514d8981	1122	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1123	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN); \
AnnaBridge	156:ff21514d8981	1124	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1125	} while(0)
AnnaBridge	156:ff21514d8981	1126
AnnaBridge	156:ff21514d8981	1127	#if defined(CAN2)
AnnaBridge	156:ff21514d8981	1128	#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1129	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	1130	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN); \
AnnaBridge	156:ff21514d8981	1131	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1132	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN); \
AnnaBridge	156:ff21514d8981	1133	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1134	} while(0)
AnnaBridge	156:ff21514d8981	1135	#endif /* CAN2 */
AnnaBridge	156:ff21514d8981	1136
AnnaBridge	156:ff21514d8981	1137	#if defined(USB)
AnnaBridge	156:ff21514d8981	1138	#define __HAL_RCC_USB_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1139	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	1140	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN); \
AnnaBridge	156:ff21514d8981	1141	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1142	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN); \
AnnaBridge	156:ff21514d8981	1143	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1144	} while(0)
AnnaBridge	156:ff21514d8981	1145	#endif /* USB */
AnnaBridge	156:ff21514d8981	1146
AnnaBridge	156:ff21514d8981	1147	#define __HAL_RCC_PWR_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1148	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	1149	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \
AnnaBridge	156:ff21514d8981	1150	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1151	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \
AnnaBridge	156:ff21514d8981	1152	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1153	} while(0)
AnnaBridge	156:ff21514d8981	1154
AnnaBridge	156:ff21514d8981	1155	#define __HAL_RCC_DAC1_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1156	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	1157	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \
AnnaBridge	156:ff21514d8981	1158	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1159	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \
AnnaBridge	156:ff21514d8981	1160	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1161	} while(0)
AnnaBridge	156:ff21514d8981	1162
AnnaBridge	156:ff21514d8981	1163	#define __HAL_RCC_OPAMP_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1164	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	1165	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \
AnnaBridge	156:ff21514d8981	1166	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1167	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \
AnnaBridge	156:ff21514d8981	1168	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1169	} while(0)
AnnaBridge	156:ff21514d8981	1170
AnnaBridge	156:ff21514d8981	1171	#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1172	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	1173	SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \
AnnaBridge	156:ff21514d8981	1174	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1175	tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \
AnnaBridge	156:ff21514d8981	1176	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1177	} while(0)
AnnaBridge	156:ff21514d8981	1178
AnnaBridge	156:ff21514d8981	1179	#define __HAL_RCC_LPUART1_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1180	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	1181	SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \
AnnaBridge	156:ff21514d8981	1182	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1183	tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \
AnnaBridge	156:ff21514d8981	1184	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1185	} while(0)
AnnaBridge	156:ff21514d8981	1186
AnnaBridge	156:ff21514d8981	1187	#if defined(SWPMI1)
AnnaBridge	156:ff21514d8981	1188	#define __HAL_RCC_SWPMI1_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1189	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	1190	SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN); \
AnnaBridge	156:ff21514d8981	1191	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1192	tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN); \
AnnaBridge	156:ff21514d8981	1193	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1194	} while(0)
AnnaBridge	156:ff21514d8981	1195	#endif /* SWPMI1 */
AnnaBridge	156:ff21514d8981	1196
AnnaBridge	156:ff21514d8981	1197	#define __HAL_RCC_LPTIM2_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1198	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	1199	SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \
AnnaBridge	156:ff21514d8981	1200	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1201	tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \
AnnaBridge	156:ff21514d8981	1202	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1203	} while(0)
AnnaBridge	156:ff21514d8981	1204
AnnaBridge	156:ff21514d8981	1205
AnnaBridge	156:ff21514d8981	1206	#define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN)
AnnaBridge	156:ff21514d8981	1207
AnnaBridge	156:ff21514d8981	1208	#if defined(TIM3)
AnnaBridge	156:ff21514d8981	1209	#define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN)
AnnaBridge	156:ff21514d8981	1210	#endif /* TIM3 */
AnnaBridge	156:ff21514d8981	1211
AnnaBridge	156:ff21514d8981	1212	#if defined(TIM4)
AnnaBridge	156:ff21514d8981	1213	#define __HAL_RCC_TIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN)
AnnaBridge	156:ff21514d8981	1214	#endif /* TIM4 */
AnnaBridge	156:ff21514d8981	1215
AnnaBridge	156:ff21514d8981	1216	#if defined(TIM5)
AnnaBridge	156:ff21514d8981	1217	#define __HAL_RCC_TIM5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN)
AnnaBridge	156:ff21514d8981	1218	#endif /* TIM5 */
AnnaBridge	156:ff21514d8981	1219
AnnaBridge	156:ff21514d8981	1220	#define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN)
AnnaBridge	156:ff21514d8981	1221
AnnaBridge	156:ff21514d8981	1222	#define __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN)
AnnaBridge	156:ff21514d8981	1223
AnnaBridge	156:ff21514d8981	1224	#if defined(LCD)
AnnaBridge	156:ff21514d8981	1225	#define __HAL_RCC_LCD_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN);
AnnaBridge	156:ff21514d8981	1226	#endif /* LCD */
AnnaBridge	156:ff21514d8981	1227
AnnaBridge	156:ff21514d8981	1228	#if defined(RCC_APB1ENR1_RTCAPBEN)
AnnaBridge	156:ff21514d8981	1229	#define __HAL_RCC_RTCAPB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN);
AnnaBridge	156:ff21514d8981	1230	#endif /* RCC_APB1ENR1_RTCAPBEN */
AnnaBridge	156:ff21514d8981	1231
AnnaBridge	156:ff21514d8981	1232	#if defined(SPI2)
AnnaBridge	156:ff21514d8981	1233	#define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN)
AnnaBridge	156:ff21514d8981	1234	#endif /* SPI2 */
AnnaBridge	156:ff21514d8981	1235
AnnaBridge	156:ff21514d8981	1236	#define __HAL_RCC_SPI3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN)
AnnaBridge	156:ff21514d8981	1237
AnnaBridge	156:ff21514d8981	1238	#define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN)
AnnaBridge	156:ff21514d8981	1239
AnnaBridge	156:ff21514d8981	1240	#if defined(USART3)
AnnaBridge	156:ff21514d8981	1241	#define __HAL_RCC_USART3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN)
AnnaBridge	156:ff21514d8981	1242	#endif /* USART3 */
AnnaBridge	156:ff21514d8981	1243
AnnaBridge	156:ff21514d8981	1244	#if defined(UART4)
AnnaBridge	156:ff21514d8981	1245	#define __HAL_RCC_UART4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN)
AnnaBridge	156:ff21514d8981	1246	#endif /* UART4 */
AnnaBridge	156:ff21514d8981	1247
AnnaBridge	156:ff21514d8981	1248	#if defined(UART5)
AnnaBridge	156:ff21514d8981	1249	#define __HAL_RCC_UART5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN)
AnnaBridge	156:ff21514d8981	1250	#endif /* UART5 */
AnnaBridge	156:ff21514d8981	1251
AnnaBridge	156:ff21514d8981	1252	#define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN)
AnnaBridge	156:ff21514d8981	1253
AnnaBridge	156:ff21514d8981	1254	#if defined(I2C2)
AnnaBridge	156:ff21514d8981	1255	#define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN)
AnnaBridge	156:ff21514d8981	1256	#endif /* I2C2 */
AnnaBridge	156:ff21514d8981	1257
AnnaBridge	156:ff21514d8981	1258	#define __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN)
AnnaBridge	156:ff21514d8981	1259
AnnaBridge	156:ff21514d8981	1260	#if defined(I2C4)
AnnaBridge	156:ff21514d8981	1261	#define __HAL_RCC_I2C4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN)
AnnaBridge	156:ff21514d8981	1262	#endif /* I2C4 */
AnnaBridge	156:ff21514d8981	1263
AnnaBridge	156:ff21514d8981	1264	#if defined(CRS)
AnnaBridge	156:ff21514d8981	1265	#define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN);
AnnaBridge	156:ff21514d8981	1266	#endif /* CRS */
AnnaBridge	156:ff21514d8981	1267
AnnaBridge	156:ff21514d8981	1268	#define __HAL_RCC_CAN1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN)
AnnaBridge	156:ff21514d8981	1269
AnnaBridge	156:ff21514d8981	1270	#if defined(CAN2)
AnnaBridge	156:ff21514d8981	1271	#define __HAL_RCC_CAN2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN)
AnnaBridge	156:ff21514d8981	1272	#endif /* CAN2 */
AnnaBridge	156:ff21514d8981	1273
AnnaBridge	156:ff21514d8981	1274	#if defined(USB)
AnnaBridge	156:ff21514d8981	1275	#define __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN);
AnnaBridge	156:ff21514d8981	1276	#endif /* USB */
AnnaBridge	156:ff21514d8981	1277
AnnaBridge	156:ff21514d8981	1278	#define __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN)
AnnaBridge	156:ff21514d8981	1279
AnnaBridge	156:ff21514d8981	1280	#define __HAL_RCC_DAC1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN)
AnnaBridge	156:ff21514d8981	1281
AnnaBridge	156:ff21514d8981	1282	#define __HAL_RCC_OPAMP_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN)
AnnaBridge	156:ff21514d8981	1283
AnnaBridge	156:ff21514d8981	1284	#define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN)
AnnaBridge	156:ff21514d8981	1285
AnnaBridge	156:ff21514d8981	1286	#define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN)
AnnaBridge	156:ff21514d8981	1287
AnnaBridge	156:ff21514d8981	1288	#if defined(SWPMI1)
AnnaBridge	156:ff21514d8981	1289	#define __HAL_RCC_SWPMI1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN)
AnnaBridge	156:ff21514d8981	1290	#endif /* SWPMI1 */
AnnaBridge	156:ff21514d8981	1291
AnnaBridge	156:ff21514d8981	1292	#define __HAL_RCC_LPTIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN)
AnnaBridge	156:ff21514d8981	1293
AnnaBridge	156:ff21514d8981	1294	/**
AnnaBridge	156:ff21514d8981	1295	* @}
AnnaBridge	156:ff21514d8981	1296	*/
AnnaBridge	156:ff21514d8981	1297
AnnaBridge	156:ff21514d8981	1298	/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
AnnaBridge	156:ff21514d8981	1299	* @brief Enable or disable the APB2 peripheral clock.
AnnaBridge	156:ff21514d8981	1300	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	1301	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	1302	* using it.
AnnaBridge	156:ff21514d8981	1303	* @{
AnnaBridge	156:ff21514d8981	1304	*/
AnnaBridge	156:ff21514d8981	1305
AnnaBridge	156:ff21514d8981	1306	#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1307	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	1308	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \
AnnaBridge	156:ff21514d8981	1309	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1310	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \
AnnaBridge	156:ff21514d8981	1311	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1312	} while(0)
AnnaBridge	156:ff21514d8981	1313
AnnaBridge	156:ff21514d8981	1314	#define __HAL_RCC_FIREWALL_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1315	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	1316	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN); \
AnnaBridge	156:ff21514d8981	1317	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1318	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN); \
AnnaBridge	156:ff21514d8981	1319	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1320	} while(0)
AnnaBridge	156:ff21514d8981	1321
AnnaBridge	156:ff21514d8981	1322	#if defined(SDMMC1)
AnnaBridge	156:ff21514d8981	1323	#define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1324	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	1325	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN); \
AnnaBridge	156:ff21514d8981	1326	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1327	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN); \
AnnaBridge	156:ff21514d8981	1328	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1329	} while(0)
AnnaBridge	156:ff21514d8981	1330	#endif /* SDMMC1 */
AnnaBridge	156:ff21514d8981	1331
AnnaBridge	156:ff21514d8981	1332	#define __HAL_RCC_TIM1_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1333	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	1334	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
AnnaBridge	156:ff21514d8981	1335	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1336	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
AnnaBridge	156:ff21514d8981	1337	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1338	} while(0)
AnnaBridge	156:ff21514d8981	1339
AnnaBridge	156:ff21514d8981	1340	#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1341	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	1342	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
AnnaBridge	156:ff21514d8981	1343	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1344	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
AnnaBridge	156:ff21514d8981	1345	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1346	} while(0)
AnnaBridge	156:ff21514d8981	1347
AnnaBridge	156:ff21514d8981	1348	#if defined(TIM8)
AnnaBridge	156:ff21514d8981	1349	#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1350	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	1351	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \
AnnaBridge	156:ff21514d8981	1352	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1353	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \
AnnaBridge	156:ff21514d8981	1354	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1355	} while(0)
AnnaBridge	156:ff21514d8981	1356	#endif /* TIM8 */
AnnaBridge	156:ff21514d8981	1357
AnnaBridge	156:ff21514d8981	1358	#define __HAL_RCC_USART1_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1359	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	1360	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
AnnaBridge	156:ff21514d8981	1361	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1362	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
AnnaBridge	156:ff21514d8981	1363	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1364	} while(0)
AnnaBridge	156:ff21514d8981	1365
AnnaBridge	156:ff21514d8981	1366
AnnaBridge	156:ff21514d8981	1367	#define __HAL_RCC_TIM15_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1368	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	1369	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \
AnnaBridge	156:ff21514d8981	1370	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1371	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \
AnnaBridge	156:ff21514d8981	1372	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1373	} while(0)
AnnaBridge	156:ff21514d8981	1374
AnnaBridge	156:ff21514d8981	1375	#define __HAL_RCC_TIM16_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1376	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	1377	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \
AnnaBridge	156:ff21514d8981	1378	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1379	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \
AnnaBridge	156:ff21514d8981	1380	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1381	} while(0)
AnnaBridge	156:ff21514d8981	1382
AnnaBridge	156:ff21514d8981	1383	#if defined(TIM17)
AnnaBridge	156:ff21514d8981	1384	#define __HAL_RCC_TIM17_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1385	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	1386	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \
AnnaBridge	156:ff21514d8981	1387	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1388	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \
AnnaBridge	156:ff21514d8981	1389	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1390	} while(0)
AnnaBridge	156:ff21514d8981	1391	#endif /* TIM17 */
AnnaBridge	156:ff21514d8981	1392
AnnaBridge	156:ff21514d8981	1393	#define __HAL_RCC_SAI1_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1394	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	1395	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \
AnnaBridge	156:ff21514d8981	1396	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1397	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \
AnnaBridge	156:ff21514d8981	1398	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1399	} while(0)
AnnaBridge	156:ff21514d8981	1400
AnnaBridge	156:ff21514d8981	1401	#if defined(SAI2)
AnnaBridge	156:ff21514d8981	1402	#define __HAL_RCC_SAI2_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1403	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	1404	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \
AnnaBridge	156:ff21514d8981	1405	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1406	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \
AnnaBridge	156:ff21514d8981	1407	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1408	} while(0)
AnnaBridge	156:ff21514d8981	1409	#endif /* SAI2 */
AnnaBridge	156:ff21514d8981	1410
AnnaBridge	156:ff21514d8981	1411	#if defined(DFSDM1_Filter0)
AnnaBridge	156:ff21514d8981	1412	#define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \
AnnaBridge	156:ff21514d8981	1413	__IO uint32_t tmpreg; \
AnnaBridge	156:ff21514d8981	1414	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN); \
AnnaBridge	156:ff21514d8981	1415	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	156:ff21514d8981	1416	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN); \
AnnaBridge	156:ff21514d8981	1417	UNUSED(tmpreg); \
AnnaBridge	156:ff21514d8981	1418	} while(0)
AnnaBridge	156:ff21514d8981	1419	#endif /* DFSDM1_Filter0 */
AnnaBridge	156:ff21514d8981	1420
AnnaBridge	156:ff21514d8981	1421
AnnaBridge	156:ff21514d8981	1422	#define __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN)
AnnaBridge	156:ff21514d8981	1423
AnnaBridge	156:ff21514d8981	1424	#if defined(SDMMC1)
AnnaBridge	156:ff21514d8981	1425	#define __HAL_RCC_SDMMC1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN)
AnnaBridge	156:ff21514d8981	1426	#endif /* SDMMC1 */
AnnaBridge	156:ff21514d8981	1427
AnnaBridge	156:ff21514d8981	1428	#define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN)
AnnaBridge	156:ff21514d8981	1429
AnnaBridge	156:ff21514d8981	1430	#define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN)
AnnaBridge	156:ff21514d8981	1431
AnnaBridge	156:ff21514d8981	1432	#if defined(TIM8)
AnnaBridge	156:ff21514d8981	1433	#define __HAL_RCC_TIM8_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN)
AnnaBridge	156:ff21514d8981	1434	#endif /* TIM8 */
AnnaBridge	156:ff21514d8981	1435
AnnaBridge	156:ff21514d8981	1436	#define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN)
AnnaBridge	156:ff21514d8981	1437
AnnaBridge	156:ff21514d8981	1438	#define __HAL_RCC_TIM15_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN)
AnnaBridge	156:ff21514d8981	1439
AnnaBridge	156:ff21514d8981	1440	#define __HAL_RCC_TIM16_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN)
AnnaBridge	156:ff21514d8981	1441
AnnaBridge	156:ff21514d8981	1442	#if defined(TIM17)
AnnaBridge	156:ff21514d8981	1443	#define __HAL_RCC_TIM17_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN)
AnnaBridge	156:ff21514d8981	1444	#endif /* TIM17 */
AnnaBridge	156:ff21514d8981	1445
AnnaBridge	156:ff21514d8981	1446	#define __HAL_RCC_SAI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN)
AnnaBridge	156:ff21514d8981	1447
AnnaBridge	156:ff21514d8981	1448	#if defined(SAI2)
AnnaBridge	156:ff21514d8981	1449	#define __HAL_RCC_SAI2_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN)
AnnaBridge	156:ff21514d8981	1450	#endif /* SAI2 */
AnnaBridge	156:ff21514d8981	1451
AnnaBridge	156:ff21514d8981	1452	#if defined(DFSDM1_Filter0)
AnnaBridge	156:ff21514d8981	1453	#define __HAL_RCC_DFSDM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN)
AnnaBridge	156:ff21514d8981	1454	#endif /* DFSDM1_Filter0 */
AnnaBridge	156:ff21514d8981	1455
AnnaBridge	156:ff21514d8981	1456	/**
AnnaBridge	156:ff21514d8981	1457	* @}
AnnaBridge	156:ff21514d8981	1458	*/
AnnaBridge	156:ff21514d8981	1459
AnnaBridge	156:ff21514d8981	1460	/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enabled or Disabled Status
AnnaBridge	156:ff21514d8981	1461	* @brief Check whether the AHB1 peripheral clock is enabled or not.
AnnaBridge	156:ff21514d8981	1462	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	1463	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	1464	* using it.
AnnaBridge	156:ff21514d8981	1465	* @{
AnnaBridge	156:ff21514d8981	1466	*/
AnnaBridge	156:ff21514d8981	1467
AnnaBridge	156:ff21514d8981	1468	#define __HAL_RCC_DMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) != RESET)
AnnaBridge	156:ff21514d8981	1469
AnnaBridge	156:ff21514d8981	1470	#define __HAL_RCC_DMA2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) != RESET)
AnnaBridge	156:ff21514d8981	1471
AnnaBridge	156:ff21514d8981	1472	#define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != RESET)
AnnaBridge	156:ff21514d8981	1473
AnnaBridge	156:ff21514d8981	1474	#define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != RESET)
AnnaBridge	156:ff21514d8981	1475
AnnaBridge	156:ff21514d8981	1476	#define __HAL_RCC_TSC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) != RESET)
AnnaBridge	156:ff21514d8981	1477
AnnaBridge	156:ff21514d8981	1478	#if defined(DMA2D)
AnnaBridge	156:ff21514d8981	1479	#define __HAL_RCC_DMA2D_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) != RESET)
AnnaBridge	156:ff21514d8981	1480	#endif /* DMA2D */
AnnaBridge	156:ff21514d8981	1481
AnnaBridge	156:ff21514d8981	1482
AnnaBridge	156:ff21514d8981	1483	#define __HAL_RCC_DMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) == RESET)
AnnaBridge	156:ff21514d8981	1484
AnnaBridge	156:ff21514d8981	1485	#define __HAL_RCC_DMA2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) == RESET)
AnnaBridge	156:ff21514d8981	1486
AnnaBridge	156:ff21514d8981	1487	#define __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) == RESET)
AnnaBridge	156:ff21514d8981	1488
AnnaBridge	156:ff21514d8981	1489	#define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == RESET)
AnnaBridge	156:ff21514d8981	1490
AnnaBridge	156:ff21514d8981	1491	#define __HAL_RCC_TSC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) == RESET)
AnnaBridge	156:ff21514d8981	1492
AnnaBridge	156:ff21514d8981	1493	#if defined(DMA2D)
AnnaBridge	156:ff21514d8981	1494	#define __HAL_RCC_DMA2D_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) == RESET)
AnnaBridge	156:ff21514d8981	1495	#endif /* DMA2D */
AnnaBridge	156:ff21514d8981	1496
AnnaBridge	156:ff21514d8981	1497	/**
AnnaBridge	156:ff21514d8981	1498	* @}
AnnaBridge	156:ff21514d8981	1499	*/
AnnaBridge	156:ff21514d8981	1500
AnnaBridge	156:ff21514d8981	1501	/** @defgroup RCC_AHB2_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enabled or Disabled Status
AnnaBridge	156:ff21514d8981	1502	* @brief Check whether the AHB2 peripheral clock is enabled or not.
AnnaBridge	156:ff21514d8981	1503	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	1504	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	1505	* using it.
AnnaBridge	156:ff21514d8981	1506	* @{
AnnaBridge	156:ff21514d8981	1507	*/
AnnaBridge	156:ff21514d8981	1508
AnnaBridge	156:ff21514d8981	1509	#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) != RESET)
AnnaBridge	156:ff21514d8981	1510
AnnaBridge	156:ff21514d8981	1511	#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != RESET)
AnnaBridge	156:ff21514d8981	1512
AnnaBridge	156:ff21514d8981	1513	#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != RESET)
AnnaBridge	156:ff21514d8981	1514
AnnaBridge	156:ff21514d8981	1515	#if defined(GPIOD)
AnnaBridge	156:ff21514d8981	1516	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) != RESET)
AnnaBridge	156:ff21514d8981	1517	#endif /* GPIOD */
AnnaBridge	156:ff21514d8981	1518
AnnaBridge	156:ff21514d8981	1519	#if defined(GPIOE)
AnnaBridge	156:ff21514d8981	1520	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) != RESET)
AnnaBridge	156:ff21514d8981	1521	#endif /* GPIOE */
AnnaBridge	156:ff21514d8981	1522
AnnaBridge	156:ff21514d8981	1523	#if defined(GPIOF)
AnnaBridge	156:ff21514d8981	1524	#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) != RESET)
AnnaBridge	156:ff21514d8981	1525	#endif /* GPIOF */
AnnaBridge	156:ff21514d8981	1526
AnnaBridge	156:ff21514d8981	1527	#if defined(GPIOG)
AnnaBridge	156:ff21514d8981	1528	#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) != RESET)
AnnaBridge	156:ff21514d8981	1529	#endif /* GPIOG */
AnnaBridge	156:ff21514d8981	1530
AnnaBridge	156:ff21514d8981	1531	#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) != RESET)
AnnaBridge	156:ff21514d8981	1532
AnnaBridge	156:ff21514d8981	1533	#if defined(GPIOI)
AnnaBridge	156:ff21514d8981	1534	#define __HAL_RCC_GPIOI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN) != RESET)
AnnaBridge	156:ff21514d8981	1535	#endif /* GPIOI */
AnnaBridge	156:ff21514d8981	1536
AnnaBridge	156:ff21514d8981	1537	#if defined(USB_OTG_FS)
AnnaBridge	156:ff21514d8981	1538	#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) != RESET)
AnnaBridge	156:ff21514d8981	1539	#endif /* USB_OTG_FS */
AnnaBridge	156:ff21514d8981	1540
AnnaBridge	156:ff21514d8981	1541	#define __HAL_RCC_ADC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) != RESET)
AnnaBridge	156:ff21514d8981	1542
AnnaBridge	156:ff21514d8981	1543	#if defined(DCMI)
AnnaBridge	156:ff21514d8981	1544	#define __HAL_RCC_DCMI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN) != RESET)
AnnaBridge	156:ff21514d8981	1545	#endif /* DCMI */
AnnaBridge	156:ff21514d8981	1546
AnnaBridge	156:ff21514d8981	1547	#if defined(AES)
AnnaBridge	156:ff21514d8981	1548	#define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) != RESET)
AnnaBridge	156:ff21514d8981	1549	#endif /* AES */
AnnaBridge	156:ff21514d8981	1550
AnnaBridge	156:ff21514d8981	1551	#if defined(HASH)
AnnaBridge	156:ff21514d8981	1552	#define __HAL_RCC_HASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) != RESET)
AnnaBridge	156:ff21514d8981	1553	#endif /* HASH */
AnnaBridge	156:ff21514d8981	1554
AnnaBridge	156:ff21514d8981	1555	#define __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) != RESET)
AnnaBridge	156:ff21514d8981	1556
AnnaBridge	156:ff21514d8981	1557
AnnaBridge	156:ff21514d8981	1558	#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) == RESET)
AnnaBridge	156:ff21514d8981	1559
AnnaBridge	156:ff21514d8981	1560	#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) == RESET)
AnnaBridge	156:ff21514d8981	1561
AnnaBridge	156:ff21514d8981	1562	#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) == RESET)
AnnaBridge	156:ff21514d8981	1563
AnnaBridge	156:ff21514d8981	1564	#if defined(GPIOD)
AnnaBridge	156:ff21514d8981	1565	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) == RESET)
AnnaBridge	156:ff21514d8981	1566	#endif /* GPIOD */
AnnaBridge	156:ff21514d8981	1567
AnnaBridge	156:ff21514d8981	1568	#if defined(GPIOE)
AnnaBridge	156:ff21514d8981	1569	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) == RESET)
AnnaBridge	156:ff21514d8981	1570	#endif /* GPIOE */
AnnaBridge	156:ff21514d8981	1571
AnnaBridge	156:ff21514d8981	1572	#if defined(GPIOF)
AnnaBridge	156:ff21514d8981	1573	#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) == RESET)
AnnaBridge	156:ff21514d8981	1574	#endif /* GPIOF */
AnnaBridge	156:ff21514d8981	1575
AnnaBridge	156:ff21514d8981	1576	#if defined(GPIOG)
AnnaBridge	156:ff21514d8981	1577	#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) == RESET)
AnnaBridge	156:ff21514d8981	1578	#endif /* GPIOG */
AnnaBridge	156:ff21514d8981	1579
AnnaBridge	156:ff21514d8981	1580	#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) == RESET)
AnnaBridge	156:ff21514d8981	1581
AnnaBridge	156:ff21514d8981	1582	#if defined(GPIOI)
AnnaBridge	156:ff21514d8981	1583	#define __HAL_RCC_GPIOI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOIEN) == RESET)
AnnaBridge	156:ff21514d8981	1584	#endif /* GPIOI */
AnnaBridge	156:ff21514d8981	1585
AnnaBridge	156:ff21514d8981	1586	#if defined(USB_OTG_FS)
AnnaBridge	156:ff21514d8981	1587	#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) == RESET)
AnnaBridge	156:ff21514d8981	1588	#endif /* USB_OTG_FS */
AnnaBridge	156:ff21514d8981	1589
AnnaBridge	156:ff21514d8981	1590	#define __HAL_RCC_ADC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) == RESET)
AnnaBridge	156:ff21514d8981	1591
AnnaBridge	156:ff21514d8981	1592	#if defined(DCMI)
AnnaBridge	156:ff21514d8981	1593	#define __HAL_RCC_DCMI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN) == RESET)
AnnaBridge	156:ff21514d8981	1594	#endif /* DCMI */
AnnaBridge	156:ff21514d8981	1595
AnnaBridge	156:ff21514d8981	1596	#if defined(AES)
AnnaBridge	156:ff21514d8981	1597	#define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) == RESET)
AnnaBridge	156:ff21514d8981	1598	#endif /* AES */
AnnaBridge	156:ff21514d8981	1599
AnnaBridge	156:ff21514d8981	1600	#if defined(HASH)
AnnaBridge	156:ff21514d8981	1601	#define __HAL_RCC_HASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) == RESET)
AnnaBridge	156:ff21514d8981	1602	#endif /* HASH */
AnnaBridge	156:ff21514d8981	1603
AnnaBridge	156:ff21514d8981	1604	#define __HAL_RCC_RNG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) == RESET)
AnnaBridge	156:ff21514d8981	1605
AnnaBridge	156:ff21514d8981	1606	/**
AnnaBridge	156:ff21514d8981	1607	* @}
AnnaBridge	156:ff21514d8981	1608	*/
AnnaBridge	156:ff21514d8981	1609
AnnaBridge	156:ff21514d8981	1610	/** @defgroup RCC_AHB3_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enabled or Disabled Status
AnnaBridge	156:ff21514d8981	1611	* @brief Check whether the AHB3 peripheral clock is enabled or not.
AnnaBridge	156:ff21514d8981	1612	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	1613	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	1614	* using it.
AnnaBridge	156:ff21514d8981	1615	* @{
AnnaBridge	156:ff21514d8981	1616	*/
AnnaBridge	156:ff21514d8981	1617
AnnaBridge	156:ff21514d8981	1618	#if defined(FMC_BANK1)
AnnaBridge	156:ff21514d8981	1619	#define __HAL_RCC_FMC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) != RESET)
AnnaBridge	156:ff21514d8981	1620	#endif /* FMC_BANK1 */
AnnaBridge	156:ff21514d8981	1621
AnnaBridge	156:ff21514d8981	1622	#if defined(QUADSPI)
AnnaBridge	156:ff21514d8981	1623	#define __HAL_RCC_QSPI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) != RESET)
AnnaBridge	156:ff21514d8981	1624	#endif /* QUADSPI */
AnnaBridge	156:ff21514d8981	1625
AnnaBridge	156:ff21514d8981	1626	#if defined(FMC_BANK1)
AnnaBridge	156:ff21514d8981	1627	#define __HAL_RCC_FMC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == RESET)
AnnaBridge	156:ff21514d8981	1628	#endif /* FMC_BANK1 */
AnnaBridge	156:ff21514d8981	1629
AnnaBridge	156:ff21514d8981	1630	#if defined(QUADSPI)
AnnaBridge	156:ff21514d8981	1631	#define __HAL_RCC_QSPI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) == RESET)
AnnaBridge	156:ff21514d8981	1632	#endif /* QUADSPI */
AnnaBridge	156:ff21514d8981	1633
AnnaBridge	156:ff21514d8981	1634	/**
AnnaBridge	156:ff21514d8981	1635	* @}
AnnaBridge	156:ff21514d8981	1636	*/
AnnaBridge	156:ff21514d8981	1637
AnnaBridge	156:ff21514d8981	1638	/** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status
AnnaBridge	156:ff21514d8981	1639	* @brief Check whether the APB1 peripheral clock is enabled or not.
AnnaBridge	156:ff21514d8981	1640	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	1641	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	1642	* using it.
AnnaBridge	156:ff21514d8981	1643	* @{
AnnaBridge	156:ff21514d8981	1644	*/
AnnaBridge	156:ff21514d8981	1645
AnnaBridge	156:ff21514d8981	1646	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) != RESET)
AnnaBridge	156:ff21514d8981	1647
AnnaBridge	156:ff21514d8981	1648	#if defined(TIM3)
AnnaBridge	156:ff21514d8981	1649	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) != RESET)
AnnaBridge	156:ff21514d8981	1650	#endif /* TIM3 */
AnnaBridge	156:ff21514d8981	1651
AnnaBridge	156:ff21514d8981	1652	#if defined(TIM4)
AnnaBridge	156:ff21514d8981	1653	#define __HAL_RCC_TIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) != RESET)
AnnaBridge	156:ff21514d8981	1654	#endif /* TIM4 */
AnnaBridge	156:ff21514d8981	1655
AnnaBridge	156:ff21514d8981	1656	#if defined(TIM5)
AnnaBridge	156:ff21514d8981	1657	#define __HAL_RCC_TIM5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) != RESET)
AnnaBridge	156:ff21514d8981	1658	#endif /* TIM5 */
AnnaBridge	156:ff21514d8981	1659
AnnaBridge	156:ff21514d8981	1660	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) != RESET)
AnnaBridge	156:ff21514d8981	1661
AnnaBridge	156:ff21514d8981	1662	#define __HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) != RESET)
AnnaBridge	156:ff21514d8981	1663
AnnaBridge	156:ff21514d8981	1664	#if defined(LCD)
AnnaBridge	156:ff21514d8981	1665	#define __HAL_RCC_LCD_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) != RESET)
AnnaBridge	156:ff21514d8981	1666	#endif /* LCD */
AnnaBridge	156:ff21514d8981	1667
AnnaBridge	156:ff21514d8981	1668	#if defined(RCC_APB1ENR1_RTCAPBEN)
AnnaBridge	156:ff21514d8981	1669	#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) != RESET)
AnnaBridge	156:ff21514d8981	1670	#endif /* RCC_APB1ENR1_RTCAPBEN */
AnnaBridge	156:ff21514d8981	1671
AnnaBridge	156:ff21514d8981	1672	#define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) != RESET)
AnnaBridge	156:ff21514d8981	1673
AnnaBridge	156:ff21514d8981	1674	#if defined(SPI2)
AnnaBridge	156:ff21514d8981	1675	#define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) != RESET)
AnnaBridge	156:ff21514d8981	1676	#endif /* SPI2 */
AnnaBridge	156:ff21514d8981	1677
AnnaBridge	156:ff21514d8981	1678	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) != RESET)
AnnaBridge	156:ff21514d8981	1679
AnnaBridge	156:ff21514d8981	1680	#define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != RESET)
AnnaBridge	156:ff21514d8981	1681
AnnaBridge	156:ff21514d8981	1682	#if defined(USART3)
AnnaBridge	156:ff21514d8981	1683	#define __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) != RESET)
AnnaBridge	156:ff21514d8981	1684	#endif /* USART3 */
AnnaBridge	156:ff21514d8981	1685
AnnaBridge	156:ff21514d8981	1686	#if defined(UART4)
AnnaBridge	156:ff21514d8981	1687	#define __HAL_RCC_UART4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) != RESET)
AnnaBridge	156:ff21514d8981	1688	#endif /* UART4 */
AnnaBridge	156:ff21514d8981	1689
AnnaBridge	156:ff21514d8981	1690	#if defined(UART5)
AnnaBridge	156:ff21514d8981	1691	#define __HAL_RCC_UART5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) != RESET)
AnnaBridge	156:ff21514d8981	1692	#endif /* UART5 */
AnnaBridge	156:ff21514d8981	1693
AnnaBridge	156:ff21514d8981	1694	#define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) != RESET)
AnnaBridge	156:ff21514d8981	1695
AnnaBridge	156:ff21514d8981	1696	#if defined(I2C2)
AnnaBridge	156:ff21514d8981	1697	#define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) != RESET)
AnnaBridge	156:ff21514d8981	1698	#endif /* I2C2 */
AnnaBridge	156:ff21514d8981	1699
AnnaBridge	156:ff21514d8981	1700	#define __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) != RESET)
AnnaBridge	156:ff21514d8981	1701
AnnaBridge	156:ff21514d8981	1702	#if defined(I2C4)
AnnaBridge	156:ff21514d8981	1703	#define __HAL_RCC_I2C4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) != RESET)
AnnaBridge	156:ff21514d8981	1704	#endif /* I2C4 */
AnnaBridge	156:ff21514d8981	1705
AnnaBridge	156:ff21514d8981	1706	#if defined(CRS)
AnnaBridge	156:ff21514d8981	1707	#define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) != RESET)
AnnaBridge	156:ff21514d8981	1708	#endif /* CRS */
AnnaBridge	156:ff21514d8981	1709
AnnaBridge	156:ff21514d8981	1710	#define __HAL_RCC_CAN1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) != RESET)
AnnaBridge	156:ff21514d8981	1711
AnnaBridge	156:ff21514d8981	1712	#if defined(CAN2)
AnnaBridge	156:ff21514d8981	1713	#define __HAL_RCC_CAN2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN) != RESET)
AnnaBridge	156:ff21514d8981	1714	#endif /* CAN2 */
AnnaBridge	156:ff21514d8981	1715
AnnaBridge	156:ff21514d8981	1716	#if defined(USB)
AnnaBridge	156:ff21514d8981	1717	#define __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN) != RESET)
AnnaBridge	156:ff21514d8981	1718	#endif /* USB */
AnnaBridge	156:ff21514d8981	1719
AnnaBridge	156:ff21514d8981	1720	#define __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) != RESET)
AnnaBridge	156:ff21514d8981	1721
AnnaBridge	156:ff21514d8981	1722	#define __HAL_RCC_DAC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) != RESET)
AnnaBridge	156:ff21514d8981	1723
AnnaBridge	156:ff21514d8981	1724	#define __HAL_RCC_OPAMP_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) != RESET)
AnnaBridge	156:ff21514d8981	1725
AnnaBridge	156:ff21514d8981	1726	#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) != RESET)
AnnaBridge	156:ff21514d8981	1727
AnnaBridge	156:ff21514d8981	1728	#define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) != RESET)
AnnaBridge	156:ff21514d8981	1729
AnnaBridge	156:ff21514d8981	1730	#if defined(SWPMI1)
AnnaBridge	156:ff21514d8981	1731	#define __HAL_RCC_SWPMI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) != RESET)
AnnaBridge	156:ff21514d8981	1732	#endif /* SWPMI1 */
AnnaBridge	156:ff21514d8981	1733
AnnaBridge	156:ff21514d8981	1734	#define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) != RESET)
AnnaBridge	156:ff21514d8981	1735
AnnaBridge	156:ff21514d8981	1736
AnnaBridge	156:ff21514d8981	1737	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) == RESET)
AnnaBridge	156:ff21514d8981	1738
AnnaBridge	156:ff21514d8981	1739	#if defined(TIM3)
AnnaBridge	156:ff21514d8981	1740	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) == RESET)
AnnaBridge	156:ff21514d8981	1741	#endif /* TIM3 */
AnnaBridge	156:ff21514d8981	1742
AnnaBridge	156:ff21514d8981	1743	#if defined(TIM4)
AnnaBridge	156:ff21514d8981	1744	#define __HAL_RCC_TIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) == RESET)
AnnaBridge	156:ff21514d8981	1745	#endif /* TIM4 */
AnnaBridge	156:ff21514d8981	1746
AnnaBridge	156:ff21514d8981	1747	#if defined(TIM5)
AnnaBridge	156:ff21514d8981	1748	#define __HAL_RCC_TIM5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) == RESET)
AnnaBridge	156:ff21514d8981	1749	#endif /* TIM5 */
AnnaBridge	156:ff21514d8981	1750
AnnaBridge	156:ff21514d8981	1751	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) == RESET)
AnnaBridge	156:ff21514d8981	1752
AnnaBridge	156:ff21514d8981	1753	#define __HAL_RCC_TIM7_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) == RESET)
AnnaBridge	156:ff21514d8981	1754
AnnaBridge	156:ff21514d8981	1755	#if defined(LCD)
AnnaBridge	156:ff21514d8981	1756	#define __HAL_RCC_LCD_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) == RESET)
AnnaBridge	156:ff21514d8981	1757	#endif /* LCD */
AnnaBridge	156:ff21514d8981	1758
AnnaBridge	156:ff21514d8981	1759	#if defined(RCC_APB1ENR1_RTCAPBEN)
AnnaBridge	156:ff21514d8981	1760	#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) == RESET)
AnnaBridge	156:ff21514d8981	1761	#endif /* RCC_APB1ENR1_RTCAPBEN */
AnnaBridge	156:ff21514d8981	1762
AnnaBridge	156:ff21514d8981	1763	#define __HAL_RCC_WWDG_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) == RESET)
AnnaBridge	156:ff21514d8981	1764
AnnaBridge	156:ff21514d8981	1765	#if defined(SPI2)
AnnaBridge	156:ff21514d8981	1766	#define __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) == RESET)
AnnaBridge	156:ff21514d8981	1767	#endif /* SPI2 */
AnnaBridge	156:ff21514d8981	1768
AnnaBridge	156:ff21514d8981	1769	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) == RESET)
AnnaBridge	156:ff21514d8981	1770
AnnaBridge	156:ff21514d8981	1771	#define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) == RESET)
AnnaBridge	156:ff21514d8981	1772
AnnaBridge	156:ff21514d8981	1773	#if defined(USART3)
AnnaBridge	156:ff21514d8981	1774	#define __HAL_RCC_USART3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) == RESET)
AnnaBridge	156:ff21514d8981	1775	#endif /* USART3 */
AnnaBridge	156:ff21514d8981	1776
AnnaBridge	156:ff21514d8981	1777	#if defined(UART4)
AnnaBridge	156:ff21514d8981	1778	#define __HAL_RCC_UART4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) == RESET)
AnnaBridge	156:ff21514d8981	1779	#endif /* UART4 */
AnnaBridge	156:ff21514d8981	1780
AnnaBridge	156:ff21514d8981	1781	#if defined(UART5)
AnnaBridge	156:ff21514d8981	1782	#define __HAL_RCC_UART5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) == RESET)
AnnaBridge	156:ff21514d8981	1783	#endif /* UART5 */
AnnaBridge	156:ff21514d8981	1784
AnnaBridge	156:ff21514d8981	1785	#define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) == RESET)
AnnaBridge	156:ff21514d8981	1786
AnnaBridge	156:ff21514d8981	1787	#if defined(I2C2)
AnnaBridge	156:ff21514d8981	1788	#define __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) == RESET)
AnnaBridge	156:ff21514d8981	1789	#endif /* I2C2 */
AnnaBridge	156:ff21514d8981	1790
AnnaBridge	156:ff21514d8981	1791	#define __HAL_RCC_I2C3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) == RESET)
AnnaBridge	156:ff21514d8981	1792
AnnaBridge	156:ff21514d8981	1793	#if defined(I2C4)
AnnaBridge	156:ff21514d8981	1794	#define __HAL_RCC_I2C4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) == RESET)
AnnaBridge	156:ff21514d8981	1795	#endif /* I2C4 */
AnnaBridge	156:ff21514d8981	1796
AnnaBridge	156:ff21514d8981	1797	#if defined(CRS)
AnnaBridge	156:ff21514d8981	1798	#define __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) == RESET)
AnnaBridge	156:ff21514d8981	1799	#endif /* CRS */
AnnaBridge	156:ff21514d8981	1800
AnnaBridge	156:ff21514d8981	1801	#define __HAL_RCC_CAN1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) == RESET)
AnnaBridge	156:ff21514d8981	1802
AnnaBridge	156:ff21514d8981	1803	#if defined(CAN2)
AnnaBridge	156:ff21514d8981	1804	#define __HAL_RCC_CAN2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN2EN) == RESET)
AnnaBridge	156:ff21514d8981	1805	#endif /* CAN2 */
AnnaBridge	156:ff21514d8981	1806
AnnaBridge	156:ff21514d8981	1807	#if defined(USB)
AnnaBridge	156:ff21514d8981	1808	#define __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN) == RESET)
AnnaBridge	156:ff21514d8981	1809	#endif /* USB */
AnnaBridge	156:ff21514d8981	1810
AnnaBridge	156:ff21514d8981	1811	#define __HAL_RCC_PWR_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) == RESET)
AnnaBridge	156:ff21514d8981	1812
AnnaBridge	156:ff21514d8981	1813	#define __HAL_RCC_DAC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) == RESET)
AnnaBridge	156:ff21514d8981	1814
AnnaBridge	156:ff21514d8981	1815	#define __HAL_RCC_OPAMP_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) == RESET)
AnnaBridge	156:ff21514d8981	1816
AnnaBridge	156:ff21514d8981	1817	#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) == RESET)
AnnaBridge	156:ff21514d8981	1818
AnnaBridge	156:ff21514d8981	1819	#define __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) == RESET)
AnnaBridge	156:ff21514d8981	1820
AnnaBridge	156:ff21514d8981	1821	#if defined(SWPMI1)
AnnaBridge	156:ff21514d8981	1822	#define __HAL_RCC_SWPMI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) == RESET)
AnnaBridge	156:ff21514d8981	1823	#endif /* SWPMI1 */
AnnaBridge	156:ff21514d8981	1824
AnnaBridge	156:ff21514d8981	1825	#define __HAL_RCC_LPTIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) == RESET)
AnnaBridge	156:ff21514d8981	1826
AnnaBridge	156:ff21514d8981	1827	/**
AnnaBridge	156:ff21514d8981	1828	* @}
AnnaBridge	156:ff21514d8981	1829	*/
AnnaBridge	156:ff21514d8981	1830
AnnaBridge	156:ff21514d8981	1831	/** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status
AnnaBridge	156:ff21514d8981	1832	* @brief Check whether the APB2 peripheral clock is enabled or not.
AnnaBridge	156:ff21514d8981	1833	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	156:ff21514d8981	1834	* is disabled and the application software has to enable this clock before
AnnaBridge	156:ff21514d8981	1835	* using it.
AnnaBridge	156:ff21514d8981	1836	* @{
AnnaBridge	156:ff21514d8981	1837	*/
AnnaBridge	156:ff21514d8981	1838
AnnaBridge	156:ff21514d8981	1839	#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) != RESET)
AnnaBridge	156:ff21514d8981	1840
AnnaBridge	156:ff21514d8981	1841	#define __HAL_RCC_FIREWALL_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN) != RESET)
AnnaBridge	156:ff21514d8981	1842
AnnaBridge	156:ff21514d8981	1843	#if defined(SDMMC1)
AnnaBridge	156:ff21514d8981	1844	#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) != RESET)
AnnaBridge	156:ff21514d8981	1845	#endif /* SDMMC1 */
AnnaBridge	156:ff21514d8981	1846
AnnaBridge	156:ff21514d8981	1847	#define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != RESET)
AnnaBridge	156:ff21514d8981	1848
AnnaBridge	156:ff21514d8981	1849	#define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != RESET)
AnnaBridge	156:ff21514d8981	1850
AnnaBridge	156:ff21514d8981	1851	#if defined(TIM8)
AnnaBridge	156:ff21514d8981	1852	#define __HAL_RCC_TIM8_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) != RESET)
AnnaBridge	156:ff21514d8981	1853	#endif /* TIM8 */
AnnaBridge	156:ff21514d8981	1854
AnnaBridge	156:ff21514d8981	1855	#define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != RESET)
AnnaBridge	156:ff21514d8981	1856
AnnaBridge	156:ff21514d8981	1857	#define __HAL_RCC_TIM15_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) != RESET)
AnnaBridge	156:ff21514d8981	1858
AnnaBridge	156:ff21514d8981	1859	#define __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != RESET)
AnnaBridge	156:ff21514d8981	1860
AnnaBridge	156:ff21514d8981	1861	#if defined(TIM17)
AnnaBridge	156:ff21514d8981	1862	#define __HAL_RCC_TIM17_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != RESET)
AnnaBridge	156:ff21514d8981	1863	#endif /* TIM17 */
AnnaBridge	156:ff21514d8981	1864
AnnaBridge	156:ff21514d8981	1865	#define __HAL_RCC_SAI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != RESET)
AnnaBridge	156:ff21514d8981	1866
AnnaBridge	156:ff21514d8981	1867	#if defined(SAI2)
AnnaBridge	156:ff21514d8981	1868	#define __HAL_RCC_SAI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) != RESET)
AnnaBridge	156:ff21514d8981	1869	#endif /* SAI2 */
AnnaBridge	156:ff21514d8981	1870
AnnaBridge	156:ff21514d8981	1871	#if defined(DFSDM1_Filter0)
AnnaBridge	156:ff21514d8981	1872	#define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) != RESET)
AnnaBridge	156:ff21514d8981	1873	#endif /* DFSDM1_Filter0 */
AnnaBridge	156:ff21514d8981	1874
AnnaBridge	156:ff21514d8981	1875
AnnaBridge	156:ff21514d8981	1876	#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) == RESET)
AnnaBridge	156:ff21514d8981	1877
AnnaBridge	156:ff21514d8981	1878	#if defined(SDMMC1)
AnnaBridge	156:ff21514d8981	1879	#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) == RESET)
AnnaBridge	156:ff21514d8981	1880	#endif /* SDMMC1 */
AnnaBridge	156:ff21514d8981	1881
AnnaBridge	156:ff21514d8981	1882	#define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == RESET)
AnnaBridge	156:ff21514d8981	1883
AnnaBridge	156:ff21514d8981	1884	#define __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) == RESET)
AnnaBridge	156:ff21514d8981	1885
AnnaBridge	156:ff21514d8981	1886	#if defined(TIM8)
AnnaBridge	156:ff21514d8981	1887	#define __HAL_RCC_TIM8_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) == RESET)
AnnaBridge	156:ff21514d8981	1888	#endif /* TIM8 */
AnnaBridge	156:ff21514d8981	1889
AnnaBridge	156:ff21514d8981	1890	#define __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) == RESET)
AnnaBridge	156:ff21514d8981	1891
AnnaBridge	156:ff21514d8981	1892	#define __HAL_RCC_TIM15_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) == RESET)
AnnaBridge	156:ff21514d8981	1893
AnnaBridge	156:ff21514d8981	1894	#define __HAL_RCC_TIM16_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) == RESET)
AnnaBridge	156:ff21514d8981	1895
AnnaBridge	156:ff21514d8981	1896	#if defined(TIM17)
AnnaBridge	156:ff21514d8981	1897	#define __HAL_RCC_TIM17_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) == RESET)
AnnaBridge	156:ff21514d8981	1898	#endif /* TIM17 */
AnnaBridge	156:ff21514d8981	1899
AnnaBridge	156:ff21514d8981	1900	#define __HAL_RCC_SAI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) == RESET)
AnnaBridge	156:ff21514d8981	1901
AnnaBridge	156:ff21514d8981	1902	#if defined(SAI2)
AnnaBridge	156:ff21514d8981	1903	#define __HAL_RCC_SAI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) == RESET)
AnnaBridge	156:ff21514d8981	1904	#endif /* SAI2 */
AnnaBridge	156:ff21514d8981	1905
AnnaBridge	156:ff21514d8981	1906	#if defined(DFSDM1_Filter0)
AnnaBridge	156:ff21514d8981	1907	#define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) == RESET)
AnnaBridge	156:ff21514d8981	1908	#endif /* DFSDM1_Filter0 */
AnnaBridge	156:ff21514d8981	1909
AnnaBridge	156:ff21514d8981	1910	/**
AnnaBridge	156:ff21514d8981	1911	* @}
AnnaBridge	156:ff21514d8981	1912	*/
AnnaBridge	156:ff21514d8981	1913
AnnaBridge	156:ff21514d8981	1914	/** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Peripheral Force Release Reset
AnnaBridge	156:ff21514d8981	1915	* @brief Force or release AHB1 peripheral reset.
AnnaBridge	156:ff21514d8981	1916	* @{
AnnaBridge	156:ff21514d8981	1917	*/
AnnaBridge	156:ff21514d8981	1918	#define __HAL_RCC_AHB1_FORCE_RESET() WRITE_REG(RCC->AHB1RSTR, 0xFFFFFFFFU)
AnnaBridge	156:ff21514d8981	1919
AnnaBridge	156:ff21514d8981	1920	#define __HAL_RCC_DMA1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST)
AnnaBridge	156:ff21514d8981	1921
AnnaBridge	156:ff21514d8981	1922	#define __HAL_RCC_DMA2_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST)
AnnaBridge	156:ff21514d8981	1923
AnnaBridge	156:ff21514d8981	1924	#define __HAL_RCC_FLASH_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST)
AnnaBridge	156:ff21514d8981	1925
AnnaBridge	156:ff21514d8981	1926	#define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)
AnnaBridge	156:ff21514d8981	1927
AnnaBridge	156:ff21514d8981	1928	#define __HAL_RCC_TSC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST)
AnnaBridge	156:ff21514d8981	1929
AnnaBridge	156:ff21514d8981	1930	#if defined(DMA2D)
AnnaBridge	156:ff21514d8981	1931	#define __HAL_RCC_DMA2D_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2DRST)
AnnaBridge	156:ff21514d8981	1932	#endif /* DMA2D */
AnnaBridge	156:ff21514d8981	1933
AnnaBridge	156:ff21514d8981	1934
AnnaBridge	156:ff21514d8981	1935	#define __HAL_RCC_AHB1_RELEASE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x00000000U)
AnnaBridge	156:ff21514d8981	1936
AnnaBridge	156:ff21514d8981	1937	#define __HAL_RCC_DMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST)
AnnaBridge	156:ff21514d8981	1938
AnnaBridge	156:ff21514d8981	1939	#define __HAL_RCC_DMA2_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST)
AnnaBridge	156:ff21514d8981	1940
AnnaBridge	156:ff21514d8981	1941	#define __HAL_RCC_FLASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST)
AnnaBridge	156:ff21514d8981	1942
AnnaBridge	156:ff21514d8981	1943	#define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)
AnnaBridge	156:ff21514d8981	1944
AnnaBridge	156:ff21514d8981	1945	#define __HAL_RCC_TSC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST)
AnnaBridge	156:ff21514d8981	1946
AnnaBridge	156:ff21514d8981	1947	#if defined(DMA2D)
AnnaBridge	156:ff21514d8981	1948	#define __HAL_RCC_DMA2D_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2DRST)
AnnaBridge	156:ff21514d8981	1949	#endif /* DMA2D */
AnnaBridge	156:ff21514d8981	1950
AnnaBridge	156:ff21514d8981	1951	/**
AnnaBridge	156:ff21514d8981	1952	* @}
AnnaBridge	156:ff21514d8981	1953	*/
AnnaBridge	156:ff21514d8981	1954
AnnaBridge	156:ff21514d8981	1955	/** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Peripheral Force Release Reset
AnnaBridge	156:ff21514d8981	1956	* @brief Force or release AHB2 peripheral reset.
AnnaBridge	156:ff21514d8981	1957	* @{
AnnaBridge	156:ff21514d8981	1958	*/
AnnaBridge	156:ff21514d8981	1959	#define __HAL_RCC_AHB2_FORCE_RESET() WRITE_REG(RCC->AHB2RSTR, 0xFFFFFFFFU)
AnnaBridge	156:ff21514d8981	1960
AnnaBridge	156:ff21514d8981	1961	#define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)
AnnaBridge	156:ff21514d8981	1962
AnnaBridge	156:ff21514d8981	1963	#define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST)
AnnaBridge	156:ff21514d8981	1964
AnnaBridge	156:ff21514d8981	1965	#define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST)
AnnaBridge	156:ff21514d8981	1966
AnnaBridge	156:ff21514d8981	1967	#if defined(GPIOD)
AnnaBridge	156:ff21514d8981	1968	#define __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST)
AnnaBridge	156:ff21514d8981	1969	#endif /* GPIOD */
AnnaBridge	156:ff21514d8981	1970
AnnaBridge	156:ff21514d8981	1971	#if defined(GPIOE)
AnnaBridge	156:ff21514d8981	1972	#define __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST)
AnnaBridge	156:ff21514d8981	1973	#endif /* GPIOE */
AnnaBridge	156:ff21514d8981	1974
AnnaBridge	156:ff21514d8981	1975	#if defined(GPIOF)
AnnaBridge	156:ff21514d8981	1976	#define __HAL_RCC_GPIOF_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST)
AnnaBridge	156:ff21514d8981	1977	#endif /* GPIOF */
AnnaBridge	156:ff21514d8981	1978
AnnaBridge	156:ff21514d8981	1979	#if defined(GPIOG)
AnnaBridge	156:ff21514d8981	1980	#define __HAL_RCC_GPIOG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST)
AnnaBridge	156:ff21514d8981	1981	#endif /* GPIOG */
AnnaBridge	156:ff21514d8981	1982
AnnaBridge	156:ff21514d8981	1983	#define __HAL_RCC_GPIOH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST)
AnnaBridge	156:ff21514d8981	1984
AnnaBridge	156:ff21514d8981	1985	#if defined(GPIOI)
AnnaBridge	156:ff21514d8981	1986	#define __HAL_RCC_GPIOI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOIRST)
AnnaBridge	156:ff21514d8981	1987	#endif /* GPIOI */
AnnaBridge	156:ff21514d8981	1988
AnnaBridge	156:ff21514d8981	1989	#if defined(USB_OTG_FS)
AnnaBridge	156:ff21514d8981	1990	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST)
AnnaBridge	156:ff21514d8981	1991	#endif /* USB_OTG_FS */
AnnaBridge	156:ff21514d8981	1992
AnnaBridge	156:ff21514d8981	1993	#define __HAL_RCC_ADC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST)
AnnaBridge	156:ff21514d8981	1994
AnnaBridge	156:ff21514d8981	1995	#if defined(DCMI)
AnnaBridge	156:ff21514d8981	1996	#define __HAL_RCC_DCMI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DCMIRST)
AnnaBridge	156:ff21514d8981	1997	#endif /* DCMI */
AnnaBridge	156:ff21514d8981	1998
AnnaBridge	156:ff21514d8981	1999	#if defined(AES)
AnnaBridge	156:ff21514d8981	2000	#define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST)
AnnaBridge	156:ff21514d8981	2001	#endif /* AES */
AnnaBridge	156:ff21514d8981	2002
AnnaBridge	156:ff21514d8981	2003	#if defined(HASH)
AnnaBridge	156:ff21514d8981	2004	#define __HAL_RCC_HASH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HASHRST)
AnnaBridge	156:ff21514d8981	2005	#endif /* HASH */
AnnaBridge	156:ff21514d8981	2006
AnnaBridge	156:ff21514d8981	2007	#define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST)
AnnaBridge	156:ff21514d8981	2008
AnnaBridge	156:ff21514d8981	2009
AnnaBridge	156:ff21514d8981	2010	#define __HAL_RCC_AHB2_RELEASE_RESET() WRITE_REG(RCC->AHB2RSTR, 0x00000000U)
AnnaBridge	156:ff21514d8981	2011
AnnaBridge	156:ff21514d8981	2012	#define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)
AnnaBridge	156:ff21514d8981	2013
AnnaBridge	156:ff21514d8981	2014	#define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST)
AnnaBridge	156:ff21514d8981	2015
AnnaBridge	156:ff21514d8981	2016	#define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST)
AnnaBridge	156:ff21514d8981	2017
AnnaBridge	156:ff21514d8981	2018	#if defined(GPIOD)
AnnaBridge	156:ff21514d8981	2019	#define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST)
AnnaBridge	156:ff21514d8981	2020	#endif /* GPIOD */
AnnaBridge	156:ff21514d8981	2021
AnnaBridge	156:ff21514d8981	2022	#if defined(GPIOE)
AnnaBridge	156:ff21514d8981	2023	#define __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST)
AnnaBridge	156:ff21514d8981	2024	#endif /* GPIOE */
AnnaBridge	156:ff21514d8981	2025
AnnaBridge	156:ff21514d8981	2026	#if defined(GPIOF)
AnnaBridge	156:ff21514d8981	2027	#define __HAL_RCC_GPIOF_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST)
AnnaBridge	156:ff21514d8981	2028	#endif /* GPIOF */
AnnaBridge	156:ff21514d8981	2029
AnnaBridge	156:ff21514d8981	2030	#if defined(GPIOG)
AnnaBridge	156:ff21514d8981	2031	#define __HAL_RCC_GPIOG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST)
AnnaBridge	156:ff21514d8981	2032	#endif /* GPIOG */
AnnaBridge	156:ff21514d8981	2033
AnnaBridge	156:ff21514d8981	2034	#define __HAL_RCC_GPIOH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST)
AnnaBridge	156:ff21514d8981	2035
AnnaBridge	156:ff21514d8981	2036	#if defined(GPIOI)
AnnaBridge	156:ff21514d8981	2037	#define __HAL_RCC_GPIOI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOIRST)
AnnaBridge	156:ff21514d8981	2038	#endif /* GPIOI */
AnnaBridge	156:ff21514d8981	2039
AnnaBridge	156:ff21514d8981	2040	#if defined(USB_OTG_FS)
AnnaBridge	156:ff21514d8981	2041	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST)
AnnaBridge	156:ff21514d8981	2042	#endif /* USB_OTG_FS */
AnnaBridge	156:ff21514d8981	2043
AnnaBridge	156:ff21514d8981	2044	#define __HAL_RCC_ADC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST)
AnnaBridge	156:ff21514d8981	2045
AnnaBridge	156:ff21514d8981	2046	#if defined(DCMI)
AnnaBridge	156:ff21514d8981	2047	#define __HAL_RCC_DCMI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DCMIRST)
AnnaBridge	156:ff21514d8981	2048	#endif /* DCMI */
AnnaBridge	156:ff21514d8981	2049
AnnaBridge	156:ff21514d8981	2050	#if defined(AES)
AnnaBridge	156:ff21514d8981	2051	#define __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST)
AnnaBridge	156:ff21514d8981	2052	#endif /* AES */
AnnaBridge	156:ff21514d8981	2053
AnnaBridge	156:ff21514d8981	2054	#if defined(HASH)
AnnaBridge	156:ff21514d8981	2055	#define __HAL_RCC_HASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HASHRST)
AnnaBridge	156:ff21514d8981	2056	#endif /* HASH */
AnnaBridge	156:ff21514d8981	2057
AnnaBridge	156:ff21514d8981	2058	#define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST)
AnnaBridge	156:ff21514d8981	2059
AnnaBridge	156:ff21514d8981	2060	/**
AnnaBridge	156:ff21514d8981	2061	* @}
AnnaBridge	156:ff21514d8981	2062	*/
AnnaBridge	156:ff21514d8981	2063
AnnaBridge	156:ff21514d8981	2064	/** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Peripheral Force Release Reset
AnnaBridge	156:ff21514d8981	2065	* @brief Force or release AHB3 peripheral reset.
AnnaBridge	156:ff21514d8981	2066	* @{
AnnaBridge	156:ff21514d8981	2067	*/
AnnaBridge	156:ff21514d8981	2068	#define __HAL_RCC_AHB3_FORCE_RESET() WRITE_REG(RCC->AHB3RSTR, 0xFFFFFFFFU)
AnnaBridge	156:ff21514d8981	2069
AnnaBridge	156:ff21514d8981	2070	#if defined(FMC_BANK1)
AnnaBridge	156:ff21514d8981	2071	#define __HAL_RCC_FMC_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST)
AnnaBridge	156:ff21514d8981	2072	#endif /* FMC_BANK1 */
AnnaBridge	156:ff21514d8981	2073
AnnaBridge	156:ff21514d8981	2074	#if defined(QUADSPI)
AnnaBridge	156:ff21514d8981	2075	#define __HAL_RCC_QSPI_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST)
AnnaBridge	156:ff21514d8981	2076	#endif /* QUADSPI */
AnnaBridge	156:ff21514d8981	2077
AnnaBridge	156:ff21514d8981	2078	#define __HAL_RCC_AHB3_RELEASE_RESET() WRITE_REG(RCC->AHB3RSTR, 0x00000000U)
AnnaBridge	156:ff21514d8981	2079
AnnaBridge	156:ff21514d8981	2080	#if defined(FMC_BANK1)
AnnaBridge	156:ff21514d8981	2081	#define __HAL_RCC_FMC_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST)
AnnaBridge	156:ff21514d8981	2082	#endif /* FMC_BANK1 */
AnnaBridge	156:ff21514d8981	2083
AnnaBridge	156:ff21514d8981	2084	#if defined(QUADSPI)
AnnaBridge	156:ff21514d8981	2085	#define __HAL_RCC_QSPI_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST)
AnnaBridge	156:ff21514d8981	2086	#endif /* QUADSPI */
AnnaBridge	156:ff21514d8981	2087
AnnaBridge	156:ff21514d8981	2088	/**
AnnaBridge	156:ff21514d8981	2089	* @}
AnnaBridge	156:ff21514d8981	2090	*/
AnnaBridge	156:ff21514d8981	2091
AnnaBridge	156:ff21514d8981	2092	/** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset
AnnaBridge	156:ff21514d8981	2093	* @brief Force or release APB1 peripheral reset.
AnnaBridge	156:ff21514d8981	2094	* @{
AnnaBridge	156:ff21514d8981	2095	*/
AnnaBridge	156:ff21514d8981	2096	#define __HAL_RCC_APB1_FORCE_RESET() WRITE_REG(RCC->APB1RSTR1, 0xFFFFFFFFU)
AnnaBridge	156:ff21514d8981	2097
AnnaBridge	156:ff21514d8981	2098	#define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
AnnaBridge	156:ff21514d8981	2099
AnnaBridge	156:ff21514d8981	2100	#if defined(TIM3)
AnnaBridge	156:ff21514d8981	2101	#define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)
AnnaBridge	156:ff21514d8981	2102	#endif /* TIM3 */
AnnaBridge	156:ff21514d8981	2103
AnnaBridge	156:ff21514d8981	2104	#if defined(TIM4)
AnnaBridge	156:ff21514d8981	2105	#define __HAL_RCC_TIM4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)
AnnaBridge	156:ff21514d8981	2106	#endif /* TIM4 */
AnnaBridge	156:ff21514d8981	2107
AnnaBridge	156:ff21514d8981	2108	#if defined(TIM5)
AnnaBridge	156:ff21514d8981	2109	#define __HAL_RCC_TIM5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)
AnnaBridge	156:ff21514d8981	2110	#endif /* TIM5 */
AnnaBridge	156:ff21514d8981	2111
AnnaBridge	156:ff21514d8981	2112	#define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)
AnnaBridge	156:ff21514d8981	2113
AnnaBridge	156:ff21514d8981	2114	#define __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)
AnnaBridge	156:ff21514d8981	2115
AnnaBridge	156:ff21514d8981	2116	#if defined(LCD)
AnnaBridge	156:ff21514d8981	2117	#define __HAL_RCC_LCD_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LCDRST)
AnnaBridge	156:ff21514d8981	2118	#endif /* LCD */
AnnaBridge	156:ff21514d8981	2119
AnnaBridge	156:ff21514d8981	2120	#if defined(SPI2)
AnnaBridge	156:ff21514d8981	2121	#define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)
AnnaBridge	156:ff21514d8981	2122	#endif /* SPI2 */
AnnaBridge	156:ff21514d8981	2123
AnnaBridge	156:ff21514d8981	2124	#define __HAL_RCC_SPI3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)
AnnaBridge	156:ff21514d8981	2125
AnnaBridge	156:ff21514d8981	2126	#define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)
AnnaBridge	156:ff21514d8981	2127
AnnaBridge	156:ff21514d8981	2128	#if defined(USART3)
AnnaBridge	156:ff21514d8981	2129	#define __HAL_RCC_USART3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)
AnnaBridge	156:ff21514d8981	2130	#endif /* USART3 */
AnnaBridge	156:ff21514d8981	2131
AnnaBridge	156:ff21514d8981	2132	#if defined(UART4)
AnnaBridge	156:ff21514d8981	2133	#define __HAL_RCC_UART4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)
AnnaBridge	156:ff21514d8981	2134	#endif /* UART4 */
AnnaBridge	156:ff21514d8981	2135
AnnaBridge	156:ff21514d8981	2136	#if defined(UART5)
AnnaBridge	156:ff21514d8981	2137	#define __HAL_RCC_UART5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST)
AnnaBridge	156:ff21514d8981	2138	#endif /* UART5 */
AnnaBridge	156:ff21514d8981	2139
AnnaBridge	156:ff21514d8981	2140	#define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)
AnnaBridge	156:ff21514d8981	2141
AnnaBridge	156:ff21514d8981	2142	#if defined(I2C2)
AnnaBridge	156:ff21514d8981	2143	#define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)
AnnaBridge	156:ff21514d8981	2144	#endif /* I2C2 */
AnnaBridge	156:ff21514d8981	2145
AnnaBridge	156:ff21514d8981	2146	#define __HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST)
AnnaBridge	156:ff21514d8981	2147
AnnaBridge	156:ff21514d8981	2148	#if defined(I2C4)
AnnaBridge	156:ff21514d8981	2149	#define __HAL_RCC_I2C4_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST)
AnnaBridge	156:ff21514d8981	2150	#endif /* I2C4 */
AnnaBridge	156:ff21514d8981	2151
AnnaBridge	156:ff21514d8981	2152	#if defined(CRS)
AnnaBridge	156:ff21514d8981	2153	#define __HAL_RCC_CRS_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST)
AnnaBridge	156:ff21514d8981	2154	#endif /* CRS */
AnnaBridge	156:ff21514d8981	2155
AnnaBridge	156:ff21514d8981	2156	#define __HAL_RCC_CAN1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN1RST)
AnnaBridge	156:ff21514d8981	2157
AnnaBridge	156:ff21514d8981	2158	#if defined(CAN2)
AnnaBridge	156:ff21514d8981	2159	#define __HAL_RCC_CAN2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN2RST)
AnnaBridge	156:ff21514d8981	2160	#endif /* CAN2 */
AnnaBridge	156:ff21514d8981	2161
AnnaBridge	156:ff21514d8981	2162	#if defined(USB)
AnnaBridge	156:ff21514d8981	2163	#define __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBFSRST)
AnnaBridge	156:ff21514d8981	2164	#endif /* USB */
AnnaBridge	156:ff21514d8981	2165
AnnaBridge	156:ff21514d8981	2166	#define __HAL_RCC_PWR_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST)
AnnaBridge	156:ff21514d8981	2167
AnnaBridge	156:ff21514d8981	2168	#define __HAL_RCC_DAC1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST)
AnnaBridge	156:ff21514d8981	2169
AnnaBridge	156:ff21514d8981	2170	#define __HAL_RCC_OPAMP_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST)
AnnaBridge	156:ff21514d8981	2171
AnnaBridge	156:ff21514d8981	2172	#define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST)
AnnaBridge	156:ff21514d8981	2173
AnnaBridge	156:ff21514d8981	2174	#define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST)
AnnaBridge	156:ff21514d8981	2175
AnnaBridge	156:ff21514d8981	2176	#if defined(SWPMI1)
AnnaBridge	156:ff21514d8981	2177	#define __HAL_RCC_SWPMI1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_SWPMI1RST)
AnnaBridge	156:ff21514d8981	2178	#endif /* SWPMI1 */
AnnaBridge	156:ff21514d8981	2179
AnnaBridge	156:ff21514d8981	2180	#define __HAL_RCC_LPTIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST)
AnnaBridge	156:ff21514d8981	2181
AnnaBridge	156:ff21514d8981	2182
AnnaBridge	156:ff21514d8981	2183	#define __HAL_RCC_APB1_RELEASE_RESET() WRITE_REG(RCC->APB1RSTR1, 0x00000000U)
AnnaBridge	156:ff21514d8981	2184
AnnaBridge	156:ff21514d8981	2185	#define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
AnnaBridge	156:ff21514d8981	2186
AnnaBridge	156:ff21514d8981	2187	#if defined(TIM3)
AnnaBridge	156:ff21514d8981	2188	#define __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)
AnnaBridge	156:ff21514d8981	2189	#endif /* TIM3 */
AnnaBridge	156:ff21514d8981	2190
AnnaBridge	156:ff21514d8981	2191	#if defined(TIM4)
AnnaBridge	156:ff21514d8981	2192	#define __HAL_RCC_TIM4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)
AnnaBridge	156:ff21514d8981	2193	#endif /* TIM4 */
AnnaBridge	156:ff21514d8981	2194
AnnaBridge	156:ff21514d8981	2195	#if defined(TIM5)
AnnaBridge	156:ff21514d8981	2196	#define __HAL_RCC_TIM5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)
AnnaBridge	156:ff21514d8981	2197	#endif /* TIM5 */
AnnaBridge	156:ff21514d8981	2198
AnnaBridge	156:ff21514d8981	2199	#define __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)
AnnaBridge	156:ff21514d8981	2200
AnnaBridge	156:ff21514d8981	2201	#define __HAL_RCC_TIM7_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)
AnnaBridge	156:ff21514d8981	2202
AnnaBridge	156:ff21514d8981	2203	#if defined(LCD)
AnnaBridge	156:ff21514d8981	2204	#define __HAL_RCC_LCD_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LCDRST)
AnnaBridge	156:ff21514d8981	2205	#endif /* LCD */
AnnaBridge	156:ff21514d8981	2206
AnnaBridge	156:ff21514d8981	2207	#if defined(SPI2)
AnnaBridge	156:ff21514d8981	2208	#define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)
AnnaBridge	156:ff21514d8981	2209	#endif /* SPI2 */
AnnaBridge	156:ff21514d8981	2210
AnnaBridge	156:ff21514d8981	2211	#define __HAL_RCC_SPI3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)
AnnaBridge	156:ff21514d8981	2212
AnnaBridge	156:ff21514d8981	2213	#define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)
AnnaBridge	156:ff21514d8981	2214
AnnaBridge	156:ff21514d8981	2215	#if defined(USART3)
AnnaBridge	156:ff21514d8981	2216	#define __HAL_RCC_USART3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)
AnnaBridge	156:ff21514d8981	2217	#endif /* USART3 */
AnnaBridge	156:ff21514d8981	2218
AnnaBridge	156:ff21514d8981	2219	#if defined(UART4)
AnnaBridge	156:ff21514d8981	2220	#define __HAL_RCC_UART4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)
AnnaBridge	156:ff21514d8981	2221	#endif /* UART4 */
AnnaBridge	156:ff21514d8981	2222
AnnaBridge	156:ff21514d8981	2223	#if defined(UART5)
AnnaBridge	156:ff21514d8981	2224	#define __HAL_RCC_UART5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST)
AnnaBridge	156:ff21514d8981	2225	#endif /* UART5 */
AnnaBridge	156:ff21514d8981	2226
AnnaBridge	156:ff21514d8981	2227	#define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)
AnnaBridge	156:ff21514d8981	2228
AnnaBridge	156:ff21514d8981	2229	#if defined(I2C2)
AnnaBridge	156:ff21514d8981	2230	#define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)
AnnaBridge	156:ff21514d8981	2231	#endif /* I2C2 */
AnnaBridge	156:ff21514d8981	2232
AnnaBridge	156:ff21514d8981	2233	#define __HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST)
AnnaBridge	156:ff21514d8981	2234
AnnaBridge	156:ff21514d8981	2235	#if defined(I2C4)
AnnaBridge	156:ff21514d8981	2236	#define __HAL_RCC_I2C4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST)
AnnaBridge	156:ff21514d8981	2237	#endif /* I2C4 */
AnnaBridge	156:ff21514d8981	2238
AnnaBridge	156:ff21514d8981	2239	#if defined(CRS)
AnnaBridge	156:ff21514d8981	2240	#define __HAL_RCC_CRS_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST)
AnnaBridge	156:ff21514d8981	2241	#endif /* CRS */
AnnaBridge	156:ff21514d8981	2242
AnnaBridge	156:ff21514d8981	2243	#define __HAL_RCC_CAN1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN1RST)
AnnaBridge	156:ff21514d8981	2244
AnnaBridge	156:ff21514d8981	2245	#if defined(CAN2)
AnnaBridge	156:ff21514d8981	2246	#define __HAL_RCC_CAN2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN2RST)
AnnaBridge	156:ff21514d8981	2247	#endif /* CAN2 */
AnnaBridge	156:ff21514d8981	2248
AnnaBridge	156:ff21514d8981	2249	#if defined(USB)
AnnaBridge	156:ff21514d8981	2250	#define __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBFSRST)
AnnaBridge	156:ff21514d8981	2251	#endif /* USB */
AnnaBridge	156:ff21514d8981	2252
AnnaBridge	156:ff21514d8981	2253	#define __HAL_RCC_PWR_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST)
AnnaBridge	156:ff21514d8981	2254
AnnaBridge	156:ff21514d8981	2255	#define __HAL_RCC_DAC1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST)
AnnaBridge	156:ff21514d8981	2256
AnnaBridge	156:ff21514d8981	2257	#define __HAL_RCC_OPAMP_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST)
AnnaBridge	156:ff21514d8981	2258
AnnaBridge	156:ff21514d8981	2259	#define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST)
AnnaBridge	156:ff21514d8981	2260
AnnaBridge	156:ff21514d8981	2261	#define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST)
AnnaBridge	156:ff21514d8981	2262
AnnaBridge	156:ff21514d8981	2263	#if defined(SWPMI1)
AnnaBridge	156:ff21514d8981	2264	#define __HAL_RCC_SWPMI1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_SWPMI1RST)
AnnaBridge	156:ff21514d8981	2265	#endif /* SWPMI1 */
AnnaBridge	156:ff21514d8981	2266
AnnaBridge	156:ff21514d8981	2267	#define __HAL_RCC_LPTIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST)
AnnaBridge	156:ff21514d8981	2268
AnnaBridge	156:ff21514d8981	2269	/**
AnnaBridge	156:ff21514d8981	2270	* @}
AnnaBridge	156:ff21514d8981	2271	*/
AnnaBridge	156:ff21514d8981	2272
AnnaBridge	156:ff21514d8981	2273	/** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset
AnnaBridge	156:ff21514d8981	2274	* @brief Force or release APB2 peripheral reset.
AnnaBridge	156:ff21514d8981	2275	* @{
AnnaBridge	156:ff21514d8981	2276	*/
AnnaBridge	156:ff21514d8981	2277	#define __HAL_RCC_APB2_FORCE_RESET() WRITE_REG(RCC->APB2RSTR, 0xFFFFFFFFU)
AnnaBridge	156:ff21514d8981	2278
AnnaBridge	156:ff21514d8981	2279	#define __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST)
AnnaBridge	156:ff21514d8981	2280
AnnaBridge	156:ff21514d8981	2281	#if defined(SDMMC1)
AnnaBridge	156:ff21514d8981	2282	#define __HAL_RCC_SDMMC1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SDMMC1RST)
AnnaBridge	156:ff21514d8981	2283	#endif /* SDMMC1 */
AnnaBridge	156:ff21514d8981	2284
AnnaBridge	156:ff21514d8981	2285	#define __HAL_RCC_TIM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)
AnnaBridge	156:ff21514d8981	2286
AnnaBridge	156:ff21514d8981	2287	#define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)
AnnaBridge	156:ff21514d8981	2288
AnnaBridge	156:ff21514d8981	2289	#if defined(TIM8)
AnnaBridge	156:ff21514d8981	2290	#define __HAL_RCC_TIM8_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)
AnnaBridge	156:ff21514d8981	2291	#endif /* TIM8 */
AnnaBridge	156:ff21514d8981	2292
AnnaBridge	156:ff21514d8981	2293	#define __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)
AnnaBridge	156:ff21514d8981	2294
AnnaBridge	156:ff21514d8981	2295	#define __HAL_RCC_TIM15_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)
AnnaBridge	156:ff21514d8981	2296
AnnaBridge	156:ff21514d8981	2297	#define __HAL_RCC_TIM16_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)
AnnaBridge	156:ff21514d8981	2298
AnnaBridge	156:ff21514d8981	2299	#if defined(TIM17)
AnnaBridge	156:ff21514d8981	2300	#define __HAL_RCC_TIM17_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)
AnnaBridge	156:ff21514d8981	2301	#endif /* TIM17 */
AnnaBridge	156:ff21514d8981	2302
AnnaBridge	156:ff21514d8981	2303	#define __HAL_RCC_SAI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)
AnnaBridge	156:ff21514d8981	2304
AnnaBridge	156:ff21514d8981	2305	#if defined(SAI2)
AnnaBridge	156:ff21514d8981	2306	#define __HAL_RCC_SAI2_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST)
AnnaBridge	156:ff21514d8981	2307	#endif /* SAI2 */
AnnaBridge	156:ff21514d8981	2308
AnnaBridge	156:ff21514d8981	2309	#if defined(DFSDM1_Filter0)
AnnaBridge	156:ff21514d8981	2310	#define __HAL_RCC_DFSDM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDM1RST)
AnnaBridge	156:ff21514d8981	2311	#endif /* DFSDM1_Filter0 */
AnnaBridge	156:ff21514d8981	2312
AnnaBridge	156:ff21514d8981	2313
AnnaBridge	156:ff21514d8981	2314	#define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00000000U)
AnnaBridge	156:ff21514d8981	2315
AnnaBridge	156:ff21514d8981	2316	#define __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST)
AnnaBridge	156:ff21514d8981	2317
AnnaBridge	156:ff21514d8981	2318	#if defined(SDMMC1)
AnnaBridge	156:ff21514d8981	2319	#define __HAL_RCC_SDMMC1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SDMMC1RST)
AnnaBridge	156:ff21514d8981	2320	#endif /* SDMMC1 */
AnnaBridge	156:ff21514d8981	2321
AnnaBridge	156:ff21514d8981	2322	#define __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)
AnnaBridge	156:ff21514d8981	2323
AnnaBridge	156:ff21514d8981	2324	#define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)
AnnaBridge	156:ff21514d8981	2325
AnnaBridge	156:ff21514d8981	2326	#if defined(TIM8)
AnnaBridge	156:ff21514d8981	2327	#define __HAL_RCC_TIM8_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)
AnnaBridge	156:ff21514d8981	2328	#endif /* TIM8 */
AnnaBridge	156:ff21514d8981	2329
AnnaBridge	156:ff21514d8981	2330	#define __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)
AnnaBridge	156:ff21514d8981	2331
AnnaBridge	156:ff21514d8981	2332	#define __HAL_RCC_TIM15_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)
AnnaBridge	156:ff21514d8981	2333
AnnaBridge	156:ff21514d8981	2334	#define __HAL_RCC_TIM16_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)
AnnaBridge	156:ff21514d8981	2335
AnnaBridge	156:ff21514d8981	2336	#if defined(TIM17)
AnnaBridge	156:ff21514d8981	2337	#define __HAL_RCC_TIM17_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)
AnnaBridge	156:ff21514d8981	2338	#endif /* TIM17 */
AnnaBridge	156:ff21514d8981	2339
AnnaBridge	156:ff21514d8981	2340	#define __HAL_RCC_SAI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)
AnnaBridge	156:ff21514d8981	2341
AnnaBridge	156:ff21514d8981	2342	#if defined(SAI2)
AnnaBridge	156:ff21514d8981	2343	#define __HAL_RCC_SAI2_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST)
AnnaBridge	156:ff21514d8981	2344	#endif /* SAI2 */
AnnaBridge	156:ff21514d8981	2345
AnnaBridge	156:ff21514d8981	2346	#if defined(DFSDM1_Filter0)
AnnaBridge	156:ff21514d8981	2347	#define __HAL_RCC_DFSDM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDM1RST)
AnnaBridge	156:ff21514d8981	2348	#endif /* DFSDM1_Filter0 */
AnnaBridge	156:ff21514d8981	2349
AnnaBridge	156:ff21514d8981	2350	/**
AnnaBridge	156:ff21514d8981	2351	* @}
AnnaBridge	156:ff21514d8981	2352	*/
AnnaBridge	156:ff21514d8981	2353
AnnaBridge	156:ff21514d8981	2354	/** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable AHB1 Peripheral Clock Sleep Enable Disable
AnnaBridge	156:ff21514d8981	2355	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	156:ff21514d8981	2356	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	156:ff21514d8981	2357	* power consumption.
AnnaBridge	156:ff21514d8981	2358	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	156:ff21514d8981	2359	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	156:ff21514d8981	2360	* @{
AnnaBridge	156:ff21514d8981	2361	*/
AnnaBridge	156:ff21514d8981	2362
AnnaBridge	156:ff21514d8981	2363	#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN)
AnnaBridge	156:ff21514d8981	2364
AnnaBridge	156:ff21514d8981	2365	#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN)
AnnaBridge	156:ff21514d8981	2366
AnnaBridge	156:ff21514d8981	2367	#define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN)
AnnaBridge	156:ff21514d8981	2368
AnnaBridge	156:ff21514d8981	2369	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)
AnnaBridge	156:ff21514d8981	2370
AnnaBridge	156:ff21514d8981	2371	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)
AnnaBridge	156:ff21514d8981	2372
AnnaBridge	156:ff21514d8981	2373	#define __HAL_RCC_TSC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN)
AnnaBridge	156:ff21514d8981	2374
AnnaBridge	156:ff21514d8981	2375	#if defined(DMA2D)
AnnaBridge	156:ff21514d8981	2376	#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN)
AnnaBridge	156:ff21514d8981	2377	#endif /* DMA2D */
AnnaBridge	156:ff21514d8981	2378
AnnaBridge	156:ff21514d8981	2379
AnnaBridge	156:ff21514d8981	2380	#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN)
AnnaBridge	156:ff21514d8981	2381
AnnaBridge	156:ff21514d8981	2382	#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN)
AnnaBridge	156:ff21514d8981	2383
AnnaBridge	156:ff21514d8981	2384	#define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN)
AnnaBridge	156:ff21514d8981	2385
AnnaBridge	156:ff21514d8981	2386	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)
AnnaBridge	156:ff21514d8981	2387
AnnaBridge	156:ff21514d8981	2388	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)
AnnaBridge	156:ff21514d8981	2389
AnnaBridge	156:ff21514d8981	2390	#define __HAL_RCC_TSC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN)
AnnaBridge	156:ff21514d8981	2391
AnnaBridge	156:ff21514d8981	2392	#if defined(DMA2D)
AnnaBridge	156:ff21514d8981	2393	#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN)
AnnaBridge	156:ff21514d8981	2394	#endif /* DMA2D */
AnnaBridge	156:ff21514d8981	2395
AnnaBridge	156:ff21514d8981	2396	/**
AnnaBridge	156:ff21514d8981	2397	* @}
AnnaBridge	156:ff21514d8981	2398	*/
AnnaBridge	156:ff21514d8981	2399
AnnaBridge	156:ff21514d8981	2400	/** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep Enable Disable
AnnaBridge	156:ff21514d8981	2401	* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	156:ff21514d8981	2402	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	156:ff21514d8981	2403	* power consumption.
AnnaBridge	156:ff21514d8981	2404	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	156:ff21514d8981	2405	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	156:ff21514d8981	2406	* @{
AnnaBridge	156:ff21514d8981	2407	*/
AnnaBridge	156:ff21514d8981	2408
AnnaBridge	156:ff21514d8981	2409	#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN)
AnnaBridge	156:ff21514d8981	2410
AnnaBridge	156:ff21514d8981	2411	#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN)
AnnaBridge	156:ff21514d8981	2412
AnnaBridge	156:ff21514d8981	2413	#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN)
AnnaBridge	156:ff21514d8981	2414
AnnaBridge	156:ff21514d8981	2415	#if defined(GPIOD)
AnnaBridge	156:ff21514d8981	2416	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN)
AnnaBridge	156:ff21514d8981	2417	#endif /* GPIOD */
AnnaBridge	156:ff21514d8981	2418
AnnaBridge	156:ff21514d8981	2419	#if defined(GPIOE)
AnnaBridge	156:ff21514d8981	2420	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN)
AnnaBridge	156:ff21514d8981	2421	#endif /* GPIOE */
AnnaBridge	156:ff21514d8981	2422
AnnaBridge	156:ff21514d8981	2423	#if defined(GPIOF)
AnnaBridge	156:ff21514d8981	2424	#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN)
AnnaBridge	156:ff21514d8981	2425	#endif /* GPIOF */
AnnaBridge	156:ff21514d8981	2426
AnnaBridge	156:ff21514d8981	2427	#if defined(GPIOG)
AnnaBridge	156:ff21514d8981	2428	#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN)
AnnaBridge	156:ff21514d8981	2429	#endif /* GPIOG */
AnnaBridge	156:ff21514d8981	2430
AnnaBridge	156:ff21514d8981	2431	#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN)
AnnaBridge	156:ff21514d8981	2432
AnnaBridge	156:ff21514d8981	2433	#if defined(GPIOI)
AnnaBridge	156:ff21514d8981	2434	#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN)
AnnaBridge	156:ff21514d8981	2435	#endif /* GPIOI */
AnnaBridge	156:ff21514d8981	2436
AnnaBridge	156:ff21514d8981	2437	#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN)
AnnaBridge	156:ff21514d8981	2438
AnnaBridge	156:ff21514d8981	2439	#if defined(USB_OTG_FS)
AnnaBridge	156:ff21514d8981	2440	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN)
AnnaBridge	156:ff21514d8981	2441	#endif /* USB_OTG_FS */
AnnaBridge	156:ff21514d8981	2442
AnnaBridge	156:ff21514d8981	2443	#define __HAL_RCC_ADC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN)
AnnaBridge	156:ff21514d8981	2444
AnnaBridge	156:ff21514d8981	2445	#if defined(DCMI)
AnnaBridge	156:ff21514d8981	2446	#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN)
AnnaBridge	156:ff21514d8981	2447	#endif /* DCMI */
AnnaBridge	156:ff21514d8981	2448
AnnaBridge	156:ff21514d8981	2449	#if defined(AES)
AnnaBridge	156:ff21514d8981	2450	#define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN)
AnnaBridge	156:ff21514d8981	2451	#endif /* AES */
AnnaBridge	156:ff21514d8981	2452
AnnaBridge	156:ff21514d8981	2453	#if defined(HASH)
AnnaBridge	156:ff21514d8981	2454	#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN)
AnnaBridge	156:ff21514d8981	2455	#endif /* HASH */
AnnaBridge	156:ff21514d8981	2456
AnnaBridge	156:ff21514d8981	2457	#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN)
AnnaBridge	156:ff21514d8981	2458
AnnaBridge	156:ff21514d8981	2459
AnnaBridge	156:ff21514d8981	2460	#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN)
AnnaBridge	156:ff21514d8981	2461
AnnaBridge	156:ff21514d8981	2462	#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN)
AnnaBridge	156:ff21514d8981	2463
AnnaBridge	156:ff21514d8981	2464	#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN)
AnnaBridge	156:ff21514d8981	2465
AnnaBridge	156:ff21514d8981	2466	#if defined(GPIOD)
AnnaBridge	156:ff21514d8981	2467	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN)
AnnaBridge	156:ff21514d8981	2468	#endif /* GPIOD */
AnnaBridge	156:ff21514d8981	2469
AnnaBridge	156:ff21514d8981	2470	#if defined(GPIOE)
AnnaBridge	156:ff21514d8981	2471	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN)
AnnaBridge	156:ff21514d8981	2472	#endif /* GPIOE */
AnnaBridge	156:ff21514d8981	2473
AnnaBridge	156:ff21514d8981	2474	#if defined(GPIOF)
AnnaBridge	156:ff21514d8981	2475	#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN)
AnnaBridge	156:ff21514d8981	2476	#endif /* GPIOF */
AnnaBridge	156:ff21514d8981	2477
AnnaBridge	156:ff21514d8981	2478	#if defined(GPIOG)
AnnaBridge	156:ff21514d8981	2479	#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN)
AnnaBridge	156:ff21514d8981	2480	#endif /* GPIOG */
AnnaBridge	156:ff21514d8981	2481
AnnaBridge	156:ff21514d8981	2482	#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN)
AnnaBridge	156:ff21514d8981	2483
AnnaBridge	156:ff21514d8981	2484	#if defined(GPIOI)
AnnaBridge	156:ff21514d8981	2485	#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN)
AnnaBridge	156:ff21514d8981	2486	#endif /* GPIOI */
AnnaBridge	156:ff21514d8981	2487
AnnaBridge	156:ff21514d8981	2488	#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN)
AnnaBridge	156:ff21514d8981	2489
AnnaBridge	156:ff21514d8981	2490	#if defined(USB_OTG_FS)
AnnaBridge	156:ff21514d8981	2491	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN)
AnnaBridge	156:ff21514d8981	2492	#endif /* USB_OTG_FS */
AnnaBridge	156:ff21514d8981	2493
AnnaBridge	156:ff21514d8981	2494	#define __HAL_RCC_ADC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN)
AnnaBridge	156:ff21514d8981	2495
AnnaBridge	156:ff21514d8981	2496	#if defined(DCMI)
AnnaBridge	156:ff21514d8981	2497	#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN)
AnnaBridge	156:ff21514d8981	2498	#endif /* DCMI */
AnnaBridge	156:ff21514d8981	2499
AnnaBridge	156:ff21514d8981	2500	#if defined(AES)
AnnaBridge	156:ff21514d8981	2501	#define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN)
AnnaBridge	156:ff21514d8981	2502	#endif /* AES */
AnnaBridge	156:ff21514d8981	2503
AnnaBridge	156:ff21514d8981	2504	#if defined(HASH)
AnnaBridge	156:ff21514d8981	2505	#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN)
AnnaBridge	156:ff21514d8981	2506	#endif /* HASH */
AnnaBridge	156:ff21514d8981	2507
AnnaBridge	156:ff21514d8981	2508	#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN)
AnnaBridge	156:ff21514d8981	2509
AnnaBridge	156:ff21514d8981	2510	/**
AnnaBridge	156:ff21514d8981	2511	* @}
AnnaBridge	156:ff21514d8981	2512	*/
AnnaBridge	156:ff21514d8981	2513
AnnaBridge	156:ff21514d8981	2514	/** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable AHB3 Peripheral Clock Sleep Enable Disable
AnnaBridge	156:ff21514d8981	2515	* @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	156:ff21514d8981	2516	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	156:ff21514d8981	2517	* power consumption.
AnnaBridge	156:ff21514d8981	2518	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	156:ff21514d8981	2519	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	156:ff21514d8981	2520	* @{
AnnaBridge	156:ff21514d8981	2521	*/
AnnaBridge	156:ff21514d8981	2522
AnnaBridge	156:ff21514d8981	2523	#if defined(QUADSPI)
AnnaBridge	156:ff21514d8981	2524	#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN)
AnnaBridge	156:ff21514d8981	2525	#endif /* QUADSPI */
AnnaBridge	156:ff21514d8981	2526
AnnaBridge	156:ff21514d8981	2527	#if defined(FMC_BANK1)
AnnaBridge	156:ff21514d8981	2528	#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN)
AnnaBridge	156:ff21514d8981	2529	#endif /* FMC_BANK1 */
AnnaBridge	156:ff21514d8981	2530
AnnaBridge	156:ff21514d8981	2531	#if defined(QUADSPI)
AnnaBridge	156:ff21514d8981	2532	#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN)
AnnaBridge	156:ff21514d8981	2533	#endif /* QUADSPI */
AnnaBridge	156:ff21514d8981	2534
AnnaBridge	156:ff21514d8981	2535	#if defined(FMC_BANK1)
AnnaBridge	156:ff21514d8981	2536	#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN)
AnnaBridge	156:ff21514d8981	2537	#endif /* FMC_BANK1 */
AnnaBridge	156:ff21514d8981	2538
AnnaBridge	156:ff21514d8981	2539	/**
AnnaBridge	156:ff21514d8981	2540	* @}
AnnaBridge	156:ff21514d8981	2541	*/
AnnaBridge	156:ff21514d8981	2542
AnnaBridge	156:ff21514d8981	2543	/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable
AnnaBridge	156:ff21514d8981	2544	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	156:ff21514d8981	2545	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	156:ff21514d8981	2546	* power consumption.
AnnaBridge	156:ff21514d8981	2547	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	156:ff21514d8981	2548	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	156:ff21514d8981	2549	* @{
AnnaBridge	156:ff21514d8981	2550	*/
AnnaBridge	156:ff21514d8981	2551
AnnaBridge	156:ff21514d8981	2552	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN)
AnnaBridge	156:ff21514d8981	2553
AnnaBridge	156:ff21514d8981	2554	#if defined(TIM3)
AnnaBridge	156:ff21514d8981	2555	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN)
AnnaBridge	156:ff21514d8981	2556	#endif /* TIM3 */
AnnaBridge	156:ff21514d8981	2557
AnnaBridge	156:ff21514d8981	2558	#if defined(TIM4)
AnnaBridge	156:ff21514d8981	2559	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)
AnnaBridge	156:ff21514d8981	2560	#endif /* TIM4 */
AnnaBridge	156:ff21514d8981	2561
AnnaBridge	156:ff21514d8981	2562	#if defined(TIM5)
AnnaBridge	156:ff21514d8981	2563	#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN)
AnnaBridge	156:ff21514d8981	2564	#endif /* TIM5 */
AnnaBridge	156:ff21514d8981	2565
AnnaBridge	156:ff21514d8981	2566	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN)
AnnaBridge	156:ff21514d8981	2567
AnnaBridge	156:ff21514d8981	2568	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN)
AnnaBridge	156:ff21514d8981	2569
AnnaBridge	156:ff21514d8981	2570	#if defined(LCD)
AnnaBridge	156:ff21514d8981	2571	#define __HAL_RCC_LCD_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN)
AnnaBridge	156:ff21514d8981	2572	#endif /* LCD */
AnnaBridge	156:ff21514d8981	2573
AnnaBridge	156:ff21514d8981	2574	#if defined(RCC_APB1SMENR1_RTCAPBSMEN)
AnnaBridge	156:ff21514d8981	2575	#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN)
AnnaBridge	156:ff21514d8981	2576	#endif /* RCC_APB1SMENR1_RTCAPBSMEN */
AnnaBridge	156:ff21514d8981	2577
AnnaBridge	156:ff21514d8981	2578	#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)
AnnaBridge	156:ff21514d8981	2579
AnnaBridge	156:ff21514d8981	2580	#if defined(SPI2)
AnnaBridge	156:ff21514d8981	2581	#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)
AnnaBridge	156:ff21514d8981	2582	#endif /* SPI2 */
AnnaBridge	156:ff21514d8981	2583
AnnaBridge	156:ff21514d8981	2584	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN)
AnnaBridge	156:ff21514d8981	2585
AnnaBridge	156:ff21514d8981	2586	#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)
AnnaBridge	156:ff21514d8981	2587
AnnaBridge	156:ff21514d8981	2588	#if defined(USART3)
AnnaBridge	156:ff21514d8981	2589	#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)
AnnaBridge	156:ff21514d8981	2590	#endif /* USART3 */
AnnaBridge	156:ff21514d8981	2591
AnnaBridge	156:ff21514d8981	2592	#if defined(UART4)
AnnaBridge	156:ff21514d8981	2593	#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN)
AnnaBridge	156:ff21514d8981	2594	#endif /* UART4 */
AnnaBridge	156:ff21514d8981	2595
AnnaBridge	156:ff21514d8981	2596	#if defined(UART5)
AnnaBridge	156:ff21514d8981	2597	#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN)
AnnaBridge	156:ff21514d8981	2598	#endif /* UART5 */
AnnaBridge	156:ff21514d8981	2599
AnnaBridge	156:ff21514d8981	2600	#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN)
AnnaBridge	156:ff21514d8981	2601
AnnaBridge	156:ff21514d8981	2602	#if defined(I2C2)
AnnaBridge	156:ff21514d8981	2603	#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN)
AnnaBridge	156:ff21514d8981	2604	#endif /* I2C2 */
AnnaBridge	156:ff21514d8981	2605
AnnaBridge	156:ff21514d8981	2606	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN)
AnnaBridge	156:ff21514d8981	2607
AnnaBridge	156:ff21514d8981	2608	#if defined(I2C4)
AnnaBridge	156:ff21514d8981	2609	#define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN)
AnnaBridge	156:ff21514d8981	2610	#endif /* I2C4 */
AnnaBridge	156:ff21514d8981	2611
AnnaBridge	156:ff21514d8981	2612	#if defined(CRS)
AnnaBridge	156:ff21514d8981	2613	#define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN)
AnnaBridge	156:ff21514d8981	2614	#endif /* CRS */
AnnaBridge	156:ff21514d8981	2615
AnnaBridge	156:ff21514d8981	2616	#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN)
AnnaBridge	156:ff21514d8981	2617
AnnaBridge	156:ff21514d8981	2618	#if defined(CAN2)
AnnaBridge	156:ff21514d8981	2619	#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN)
AnnaBridge	156:ff21514d8981	2620	#endif /* CAN2 */
AnnaBridge	156:ff21514d8981	2621
AnnaBridge	156:ff21514d8981	2622	#if defined(USB)
AnnaBridge	156:ff21514d8981	2623	#define __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN)
AnnaBridge	156:ff21514d8981	2624	#endif /* USB */
AnnaBridge	156:ff21514d8981	2625
AnnaBridge	156:ff21514d8981	2626	#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN)
AnnaBridge	156:ff21514d8981	2627
AnnaBridge	156:ff21514d8981	2628	#define __HAL_RCC_DAC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN)
AnnaBridge	156:ff21514d8981	2629
AnnaBridge	156:ff21514d8981	2630	#define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN)
AnnaBridge	156:ff21514d8981	2631
AnnaBridge	156:ff21514d8981	2632	#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN)
AnnaBridge	156:ff21514d8981	2633
AnnaBridge	156:ff21514d8981	2634	#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN)
AnnaBridge	156:ff21514d8981	2635
AnnaBridge	156:ff21514d8981	2636	#if defined(SWPMI1)
AnnaBridge	156:ff21514d8981	2637	#define __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN)
AnnaBridge	156:ff21514d8981	2638	#endif /* SWPMI1 */
AnnaBridge	156:ff21514d8981	2639
AnnaBridge	156:ff21514d8981	2640	#define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN)
AnnaBridge	156:ff21514d8981	2641
AnnaBridge	156:ff21514d8981	2642
AnnaBridge	156:ff21514d8981	2643	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN)
AnnaBridge	156:ff21514d8981	2644
AnnaBridge	156:ff21514d8981	2645	#if defined(TIM3)
AnnaBridge	156:ff21514d8981	2646	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN)
AnnaBridge	156:ff21514d8981	2647	#endif /* TIM3 */
AnnaBridge	156:ff21514d8981	2648
AnnaBridge	156:ff21514d8981	2649	#if defined(TIM4)
AnnaBridge	156:ff21514d8981	2650	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)
AnnaBridge	156:ff21514d8981	2651	#endif /* TIM4 */
AnnaBridge	156:ff21514d8981	2652
AnnaBridge	156:ff21514d8981	2653	#if defined(TIM5)
AnnaBridge	156:ff21514d8981	2654	#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN)
AnnaBridge	156:ff21514d8981	2655	#endif /* TIM5 */
AnnaBridge	156:ff21514d8981	2656
AnnaBridge	156:ff21514d8981	2657	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN)
AnnaBridge	156:ff21514d8981	2658
AnnaBridge	156:ff21514d8981	2659	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN)
AnnaBridge	156:ff21514d8981	2660
AnnaBridge	156:ff21514d8981	2661	#if defined(LCD)
AnnaBridge	156:ff21514d8981	2662	#define __HAL_RCC_LCD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN)
AnnaBridge	156:ff21514d8981	2663	#endif /* LCD */
AnnaBridge	156:ff21514d8981	2664
AnnaBridge	156:ff21514d8981	2665	#if defined(RCC_APB1SMENR1_RTCAPBSMEN)
AnnaBridge	156:ff21514d8981	2666	#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN)
AnnaBridge	156:ff21514d8981	2667	#endif /* RCC_APB1SMENR1_RTCAPBSMEN */
AnnaBridge	156:ff21514d8981	2668
AnnaBridge	156:ff21514d8981	2669	#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)
AnnaBridge	156:ff21514d8981	2670
AnnaBridge	156:ff21514d8981	2671	#if defined(SPI2)
AnnaBridge	156:ff21514d8981	2672	#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)
AnnaBridge	156:ff21514d8981	2673	#endif /* SPI2 */
AnnaBridge	156:ff21514d8981	2674
AnnaBridge	156:ff21514d8981	2675	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN)
AnnaBridge	156:ff21514d8981	2676
AnnaBridge	156:ff21514d8981	2677	#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)
AnnaBridge	156:ff21514d8981	2678
AnnaBridge	156:ff21514d8981	2679	#if defined(USART3)
AnnaBridge	156:ff21514d8981	2680	#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)
AnnaBridge	156:ff21514d8981	2681	#endif /* USART3 */
AnnaBridge	156:ff21514d8981	2682
AnnaBridge	156:ff21514d8981	2683	#if defined(UART4)
AnnaBridge	156:ff21514d8981	2684	#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN)
AnnaBridge	156:ff21514d8981	2685	#endif /* UART4 */
AnnaBridge	156:ff21514d8981	2686
AnnaBridge	156:ff21514d8981	2687	#if defined(UART5)
AnnaBridge	156:ff21514d8981	2688	#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN)
AnnaBridge	156:ff21514d8981	2689	#endif /* UART5 */
AnnaBridge	156:ff21514d8981	2690
AnnaBridge	156:ff21514d8981	2691	#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN)
AnnaBridge	156:ff21514d8981	2692
AnnaBridge	156:ff21514d8981	2693	#if defined(I2C2)
AnnaBridge	156:ff21514d8981	2694	#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN)
AnnaBridge	156:ff21514d8981	2695	#endif /* I2C2 */
AnnaBridge	156:ff21514d8981	2696
AnnaBridge	156:ff21514d8981	2697	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN)
AnnaBridge	156:ff21514d8981	2698
AnnaBridge	156:ff21514d8981	2699	#if defined(I2C4)
AnnaBridge	156:ff21514d8981	2700	#define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN)
AnnaBridge	156:ff21514d8981	2701	#endif /* I2C4 */
AnnaBridge	156:ff21514d8981	2702
AnnaBridge	156:ff21514d8981	2703	#if defined(CRS)
AnnaBridge	156:ff21514d8981	2704	#define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN)
AnnaBridge	156:ff21514d8981	2705	#endif /* CRS */
AnnaBridge	156:ff21514d8981	2706
AnnaBridge	156:ff21514d8981	2707	#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN)
AnnaBridge	156:ff21514d8981	2708
AnnaBridge	156:ff21514d8981	2709	#if defined(CAN2)
AnnaBridge	156:ff21514d8981	2710	#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN)
AnnaBridge	156:ff21514d8981	2711	#endif /* CAN2 */
AnnaBridge	156:ff21514d8981	2712
AnnaBridge	156:ff21514d8981	2713	#if defined(USB)
AnnaBridge	156:ff21514d8981	2714	#define __HAL_RCC_USB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN)
AnnaBridge	156:ff21514d8981	2715	#endif /* USB */
AnnaBridge	156:ff21514d8981	2716
AnnaBridge	156:ff21514d8981	2717	#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN)
AnnaBridge	156:ff21514d8981	2718
AnnaBridge	156:ff21514d8981	2719	#define __HAL_RCC_DAC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN)
AnnaBridge	156:ff21514d8981	2720
AnnaBridge	156:ff21514d8981	2721	#define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN)
AnnaBridge	156:ff21514d8981	2722
AnnaBridge	156:ff21514d8981	2723	#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN)
AnnaBridge	156:ff21514d8981	2724
AnnaBridge	156:ff21514d8981	2725	#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN)
AnnaBridge	156:ff21514d8981	2726
AnnaBridge	156:ff21514d8981	2727	#if defined(SWPMI1)
AnnaBridge	156:ff21514d8981	2728	#define __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN)
AnnaBridge	156:ff21514d8981	2729	#endif /* SWPMI1 */
AnnaBridge	156:ff21514d8981	2730
AnnaBridge	156:ff21514d8981	2731	#define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN)
AnnaBridge	156:ff21514d8981	2732
AnnaBridge	156:ff21514d8981	2733	/**
AnnaBridge	156:ff21514d8981	2734	* @}
AnnaBridge	156:ff21514d8981	2735	*/
AnnaBridge	156:ff21514d8981	2736
AnnaBridge	156:ff21514d8981	2737	/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable
AnnaBridge	156:ff21514d8981	2738	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	156:ff21514d8981	2739	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	156:ff21514d8981	2740	* power consumption.
AnnaBridge	156:ff21514d8981	2741	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	156:ff21514d8981	2742	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	156:ff21514d8981	2743	* @{
AnnaBridge	156:ff21514d8981	2744	*/
AnnaBridge	156:ff21514d8981	2745
AnnaBridge	156:ff21514d8981	2746	#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN)
AnnaBridge	156:ff21514d8981	2747
AnnaBridge	156:ff21514d8981	2748	#if defined(SDMMC1)
AnnaBridge	156:ff21514d8981	2749	#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN)
AnnaBridge	156:ff21514d8981	2750	#endif /* SDMMC1 */
AnnaBridge	156:ff21514d8981	2751
AnnaBridge	156:ff21514d8981	2752	#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN)
AnnaBridge	156:ff21514d8981	2753
AnnaBridge	156:ff21514d8981	2754	#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN)
AnnaBridge	156:ff21514d8981	2755
AnnaBridge	156:ff21514d8981	2756	#if defined(TIM8)
AnnaBridge	156:ff21514d8981	2757	#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN)
AnnaBridge	156:ff21514d8981	2758	#endif /* TIM8 */
AnnaBridge	156:ff21514d8981	2759
AnnaBridge	156:ff21514d8981	2760	#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN)
AnnaBridge	156:ff21514d8981	2761
AnnaBridge	156:ff21514d8981	2762	#define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN)
AnnaBridge	156:ff21514d8981	2763
AnnaBridge	156:ff21514d8981	2764	#define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN)
AnnaBridge	156:ff21514d8981	2765
AnnaBridge	156:ff21514d8981	2766	#if defined(TIM17)
AnnaBridge	156:ff21514d8981	2767	#define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN)
AnnaBridge	156:ff21514d8981	2768	#endif /* TIM17 */
AnnaBridge	156:ff21514d8981	2769
AnnaBridge	156:ff21514d8981	2770	#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)
AnnaBridge	156:ff21514d8981	2771
AnnaBridge	156:ff21514d8981	2772	#if defined(SAI2)
AnnaBridge	156:ff21514d8981	2773	#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN)
AnnaBridge	156:ff21514d8981	2774	#endif /* SAI2 */
AnnaBridge	156:ff21514d8981	2775
AnnaBridge	156:ff21514d8981	2776	#if defined(DFSDM1_Filter0)
AnnaBridge	156:ff21514d8981	2777	#define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN)
AnnaBridge	156:ff21514d8981	2778	#endif /* DFSDM1_Filter0 */
AnnaBridge	156:ff21514d8981	2779
AnnaBridge	156:ff21514d8981	2780
AnnaBridge	156:ff21514d8981	2781	#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN)
AnnaBridge	156:ff21514d8981	2782
AnnaBridge	156:ff21514d8981	2783	#if defined(SDMMC1)
AnnaBridge	156:ff21514d8981	2784	#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN)
AnnaBridge	156:ff21514d8981	2785	#endif /* SDMMC1 */
AnnaBridge	156:ff21514d8981	2786
AnnaBridge	156:ff21514d8981	2787	#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN)
AnnaBridge	156:ff21514d8981	2788
AnnaBridge	156:ff21514d8981	2789	#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN)
AnnaBridge	156:ff21514d8981	2790
AnnaBridge	156:ff21514d8981	2791	#if defined(TIM8)
AnnaBridge	156:ff21514d8981	2792	#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN)
AnnaBridge	156:ff21514d8981	2793	#endif /* TIM8 */
AnnaBridge	156:ff21514d8981	2794
AnnaBridge	156:ff21514d8981	2795	#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN)
AnnaBridge	156:ff21514d8981	2796
AnnaBridge	156:ff21514d8981	2797	#define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN)
AnnaBridge	156:ff21514d8981	2798
AnnaBridge	156:ff21514d8981	2799	#define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN)
AnnaBridge	156:ff21514d8981	2800
AnnaBridge	156:ff21514d8981	2801	#if defined(TIM17)
AnnaBridge	156:ff21514d8981	2802	#define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN)
AnnaBridge	156:ff21514d8981	2803	#endif /* TIM17 */
AnnaBridge	156:ff21514d8981	2804
AnnaBridge	156:ff21514d8981	2805	#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)
AnnaBridge	156:ff21514d8981	2806
AnnaBridge	156:ff21514d8981	2807	#if defined(SAI2)
AnnaBridge	156:ff21514d8981	2808	#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN)
AnnaBridge	156:ff21514d8981	2809	#endif /* SAI2 */
AnnaBridge	156:ff21514d8981	2810
AnnaBridge	156:ff21514d8981	2811	#if defined(DFSDM1_Filter0)
AnnaBridge	156:ff21514d8981	2812	#define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN)
AnnaBridge	156:ff21514d8981	2813	#endif /* DFSDM1_Filter0 */
AnnaBridge	156:ff21514d8981	2814
AnnaBridge	156:ff21514d8981	2815	/**
AnnaBridge	156:ff21514d8981	2816	* @}
AnnaBridge	156:ff21514d8981	2817	*/
AnnaBridge	156:ff21514d8981	2818
AnnaBridge	156:ff21514d8981	2819	/** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enabled or Disabled Status
AnnaBridge	156:ff21514d8981	2820	* @brief Check whether the AHB1 peripheral clock during Low Power (Sleep) mode is enabled or not.
AnnaBridge	156:ff21514d8981	2821	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	156:ff21514d8981	2822	* power consumption.
AnnaBridge	156:ff21514d8981	2823	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	156:ff21514d8981	2824	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	156:ff21514d8981	2825	* @{
AnnaBridge	156:ff21514d8981	2826	*/
AnnaBridge	156:ff21514d8981	2827
AnnaBridge	156:ff21514d8981	2828	#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) != RESET)
AnnaBridge	156:ff21514d8981	2829
AnnaBridge	156:ff21514d8981	2830	#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) != RESET)
AnnaBridge	156:ff21514d8981	2831
AnnaBridge	156:ff21514d8981	2832	#define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) != RESET)
AnnaBridge	156:ff21514d8981	2833
AnnaBridge	156:ff21514d8981	2834	#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) != RESET)
AnnaBridge	156:ff21514d8981	2835
AnnaBridge	156:ff21514d8981	2836	#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) != RESET)
AnnaBridge	156:ff21514d8981	2837
AnnaBridge	156:ff21514d8981	2838	#define __HAL_RCC_TSC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) != RESET)
AnnaBridge	156:ff21514d8981	2839
AnnaBridge	156:ff21514d8981	2840	#if defined(DMA2D)
AnnaBridge	156:ff21514d8981	2841	#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) != RESET)
AnnaBridge	156:ff21514d8981	2842	#endif /* DMA2D */
AnnaBridge	156:ff21514d8981	2843
AnnaBridge	156:ff21514d8981	2844
AnnaBridge	156:ff21514d8981	2845	#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) == RESET)
AnnaBridge	156:ff21514d8981	2846
AnnaBridge	156:ff21514d8981	2847	#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) == RESET)
AnnaBridge	156:ff21514d8981	2848
AnnaBridge	156:ff21514d8981	2849	#define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) == RESET)
AnnaBridge	156:ff21514d8981	2850
AnnaBridge	156:ff21514d8981	2851	#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) == RESET)
AnnaBridge	156:ff21514d8981	2852
AnnaBridge	156:ff21514d8981	2853	#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) == RESET)
AnnaBridge	156:ff21514d8981	2854
AnnaBridge	156:ff21514d8981	2855	#define __HAL_RCC_TSC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) == RESET)
AnnaBridge	156:ff21514d8981	2856
AnnaBridge	156:ff21514d8981	2857	#if defined(DMA2D)
AnnaBridge	156:ff21514d8981	2858	#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) == RESET)
AnnaBridge	156:ff21514d8981	2859	#endif /* DMA2D */
AnnaBridge	156:ff21514d8981	2860
AnnaBridge	156:ff21514d8981	2861	/**
AnnaBridge	156:ff21514d8981	2862	* @}
AnnaBridge	156:ff21514d8981	2863	*/
AnnaBridge	156:ff21514d8981	2864
AnnaBridge	156:ff21514d8981	2865	/** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable_Status AHB2 Peripheral Clock Sleep Enabled or Disabled Status
AnnaBridge	156:ff21514d8981	2866	* @brief Check whether the AHB2 peripheral clock during Low Power (Sleep) mode is enabled or not.
AnnaBridge	156:ff21514d8981	2867	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	156:ff21514d8981	2868	* power consumption.
AnnaBridge	156:ff21514d8981	2869	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	156:ff21514d8981	2870	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	156:ff21514d8981	2871	* @{
AnnaBridge	156:ff21514d8981	2872	*/
AnnaBridge	156:ff21514d8981	2873
AnnaBridge	156:ff21514d8981	2874	#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) != RESET)
AnnaBridge	156:ff21514d8981	2875
AnnaBridge	156:ff21514d8981	2876	#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) != RESET)
AnnaBridge	156:ff21514d8981	2877
AnnaBridge	156:ff21514d8981	2878	#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) != RESET)
AnnaBridge	156:ff21514d8981	2879
AnnaBridge	156:ff21514d8981	2880	#if defined(GPIOD)
AnnaBridge	156:ff21514d8981	2881	#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) != RESET)
AnnaBridge	156:ff21514d8981	2882	#endif /* GPIOD */
AnnaBridge	156:ff21514d8981	2883
AnnaBridge	156:ff21514d8981	2884	#if defined(GPIOE)
AnnaBridge	156:ff21514d8981	2885	#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) != RESET)
AnnaBridge	156:ff21514d8981	2886	#endif /* GPIOE */
AnnaBridge	156:ff21514d8981	2887
AnnaBridge	156:ff21514d8981	2888	#if defined(GPIOF)
AnnaBridge	156:ff21514d8981	2889	#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) != RESET)
AnnaBridge	156:ff21514d8981	2890	#endif /* GPIOF */
AnnaBridge	156:ff21514d8981	2891
AnnaBridge	156:ff21514d8981	2892	#if defined(GPIOG)
AnnaBridge	156:ff21514d8981	2893	#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) != RESET)
AnnaBridge	156:ff21514d8981	2894	#endif /* GPIOG */
AnnaBridge	156:ff21514d8981	2895
AnnaBridge	156:ff21514d8981	2896	#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) != RESET)
AnnaBridge	156:ff21514d8981	2897
AnnaBridge	156:ff21514d8981	2898	#if defined(GPIOI)
AnnaBridge	156:ff21514d8981	2899	#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN) != RESET)
AnnaBridge	156:ff21514d8981	2900	#endif /* GPIOI */
AnnaBridge	156:ff21514d8981	2901
AnnaBridge	156:ff21514d8981	2902	#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) != RESET)
AnnaBridge	156:ff21514d8981	2903
AnnaBridge	156:ff21514d8981	2904	#if defined(USB_OTG_FS)
AnnaBridge	156:ff21514d8981	2905	#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) != RESET)
AnnaBridge	156:ff21514d8981	2906	#endif /* USB_OTG_FS */
AnnaBridge	156:ff21514d8981	2907
AnnaBridge	156:ff21514d8981	2908	#define __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) != RESET)
AnnaBridge	156:ff21514d8981	2909
AnnaBridge	156:ff21514d8981	2910	#if defined(DCMI)
AnnaBridge	156:ff21514d8981	2911	#define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN) != RESET)
AnnaBridge	156:ff21514d8981	2912	#endif /* DCMI */
AnnaBridge	156:ff21514d8981	2913
AnnaBridge	156:ff21514d8981	2914	#if defined(AES)
AnnaBridge	156:ff21514d8981	2915	#define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) != RESET)
AnnaBridge	156:ff21514d8981	2916	#endif /* AES */
AnnaBridge	156:ff21514d8981	2917
AnnaBridge	156:ff21514d8981	2918	#if defined(HASH)
AnnaBridge	156:ff21514d8981	2919	#define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) != RESET)
AnnaBridge	156:ff21514d8981	2920	#endif /* HASH */
AnnaBridge	156:ff21514d8981	2921
AnnaBridge	156:ff21514d8981	2922	#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) != RESET)
AnnaBridge	156:ff21514d8981	2923
AnnaBridge	156:ff21514d8981	2924
AnnaBridge	156:ff21514d8981	2925	#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) == RESET)
AnnaBridge	156:ff21514d8981	2926
AnnaBridge	156:ff21514d8981	2927	#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) == RESET)
AnnaBridge	156:ff21514d8981	2928
AnnaBridge	156:ff21514d8981	2929	#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) == RESET)
AnnaBridge	156:ff21514d8981	2930
AnnaBridge	156:ff21514d8981	2931	#if defined(GPIOD)
AnnaBridge	156:ff21514d8981	2932	#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) == RESET)
AnnaBridge	156:ff21514d8981	2933	#endif /* GPIOD */
AnnaBridge	156:ff21514d8981	2934
AnnaBridge	156:ff21514d8981	2935	#if defined(GPIOE)
AnnaBridge	156:ff21514d8981	2936	#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) == RESET)
AnnaBridge	156:ff21514d8981	2937	#endif /* GPIOE */
AnnaBridge	156:ff21514d8981	2938
AnnaBridge	156:ff21514d8981	2939	#if defined(GPIOF)
AnnaBridge	156:ff21514d8981	2940	#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) == RESET)
AnnaBridge	156:ff21514d8981	2941	#endif /* GPIOF */
AnnaBridge	156:ff21514d8981	2942
AnnaBridge	156:ff21514d8981	2943	#if defined(GPIOG)
AnnaBridge	156:ff21514d8981	2944	#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) == RESET)
AnnaBridge	156:ff21514d8981	2945	#endif /* GPIOG */
AnnaBridge	156:ff21514d8981	2946
AnnaBridge	156:ff21514d8981	2947	#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) == RESET)
AnnaBridge	156:ff21514d8981	2948
AnnaBridge	156:ff21514d8981	2949	#if defined(GPIOI)
AnnaBridge	156:ff21514d8981	2950	#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOISMEN) == RESET)
AnnaBridge	156:ff21514d8981	2951	#endif /* GPIOI */
AnnaBridge	156:ff21514d8981	2952
AnnaBridge	156:ff21514d8981	2953	#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) == RESET)
AnnaBridge	156:ff21514d8981	2954
AnnaBridge	156:ff21514d8981	2955	#if defined(USB_OTG_FS)
AnnaBridge	156:ff21514d8981	2956	#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) == RESET)
AnnaBridge	156:ff21514d8981	2957	#endif /* USB_OTG_FS */
AnnaBridge	156:ff21514d8981	2958
AnnaBridge	156:ff21514d8981	2959	#define __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) == RESET)
AnnaBridge	156:ff21514d8981	2960
AnnaBridge	156:ff21514d8981	2961	#if defined(DCMI)
AnnaBridge	156:ff21514d8981	2962	#define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DCMISMEN) == RESET)
AnnaBridge	156:ff21514d8981	2963	#endif /* DCMI */
AnnaBridge	156:ff21514d8981	2964
AnnaBridge	156:ff21514d8981	2965	#if defined(AES)
AnnaBridge	156:ff21514d8981	2966	#define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) == RESET)
AnnaBridge	156:ff21514d8981	2967	#endif /* AES */
AnnaBridge	156:ff21514d8981	2968
AnnaBridge	156:ff21514d8981	2969	#if defined(HASH)
AnnaBridge	156:ff21514d8981	2970	#define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) == RESET)
AnnaBridge	156:ff21514d8981	2971	#endif /* HASH */
AnnaBridge	156:ff21514d8981	2972
AnnaBridge	156:ff21514d8981	2973	#define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) == RESET)
AnnaBridge	156:ff21514d8981	2974
AnnaBridge	156:ff21514d8981	2975	/**
AnnaBridge	156:ff21514d8981	2976	* @}
AnnaBridge	156:ff21514d8981	2977	*/
AnnaBridge	156:ff21514d8981	2978
AnnaBridge	156:ff21514d8981	2979	/** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable_Status AHB3 Peripheral Clock Sleep Enabled or Disabled Status
AnnaBridge	156:ff21514d8981	2980	* @brief Check whether the AHB3 peripheral clock during Low Power (Sleep) mode is enabled or not.
AnnaBridge	156:ff21514d8981	2981	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	156:ff21514d8981	2982	* power consumption.
AnnaBridge	156:ff21514d8981	2983	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	156:ff21514d8981	2984	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	156:ff21514d8981	2985	* @{
AnnaBridge	156:ff21514d8981	2986	*/
AnnaBridge	156:ff21514d8981	2987
AnnaBridge	156:ff21514d8981	2988	#if defined(QUADSPI)
AnnaBridge	156:ff21514d8981	2989	#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) != RESET)
AnnaBridge	156:ff21514d8981	2990	#endif /* QUADSPI */
AnnaBridge	156:ff21514d8981	2991
AnnaBridge	156:ff21514d8981	2992	#if defined(FMC_BANK1)
AnnaBridge	156:ff21514d8981	2993	#define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) != RESET)
AnnaBridge	156:ff21514d8981	2994	#endif /* FMC_BANK1 */
AnnaBridge	156:ff21514d8981	2995
AnnaBridge	156:ff21514d8981	2996	#if defined(QUADSPI)
AnnaBridge	156:ff21514d8981	2997	#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) == RESET)
AnnaBridge	156:ff21514d8981	2998	#endif /* QUADSPI */
AnnaBridge	156:ff21514d8981	2999
AnnaBridge	156:ff21514d8981	3000	#if defined(FMC_BANK1)
AnnaBridge	156:ff21514d8981	3001	#define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) == RESET)
AnnaBridge	156:ff21514d8981	3002	#endif /* FMC_BANK1 */
AnnaBridge	156:ff21514d8981	3003
AnnaBridge	156:ff21514d8981	3004	/**
AnnaBridge	156:ff21514d8981	3005	* @}
AnnaBridge	156:ff21514d8981	3006	*/
AnnaBridge	156:ff21514d8981	3007
AnnaBridge	156:ff21514d8981	3008	/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enabled or Disabled Status
AnnaBridge	156:ff21514d8981	3009	* @brief Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not.
AnnaBridge	156:ff21514d8981	3010	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	156:ff21514d8981	3011	* power consumption.
AnnaBridge	156:ff21514d8981	3012	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	156:ff21514d8981	3013	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	156:ff21514d8981	3014	* @{
AnnaBridge	156:ff21514d8981	3015	*/
AnnaBridge	156:ff21514d8981	3016
AnnaBridge	156:ff21514d8981	3017	#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) != RESET)
AnnaBridge	156:ff21514d8981	3018
AnnaBridge	156:ff21514d8981	3019	#if defined(TIM3)
AnnaBridge	156:ff21514d8981	3020	#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) != RESET)
AnnaBridge	156:ff21514d8981	3021	#endif /* TIM3 */
AnnaBridge	156:ff21514d8981	3022
AnnaBridge	156:ff21514d8981	3023	#if defined(TIM4)
AnnaBridge	156:ff21514d8981	3024	#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) != RESET)
AnnaBridge	156:ff21514d8981	3025	#endif /* TIM4 */
AnnaBridge	156:ff21514d8981	3026
AnnaBridge	156:ff21514d8981	3027	#if defined(TIM5)
AnnaBridge	156:ff21514d8981	3028	#define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) != RESET)
AnnaBridge	156:ff21514d8981	3029	#endif /* TIM5 */
AnnaBridge	156:ff21514d8981	3030
AnnaBridge	156:ff21514d8981	3031	#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) != RESET)
AnnaBridge	156:ff21514d8981	3032
AnnaBridge	156:ff21514d8981	3033	#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) != RESET)
AnnaBridge	156:ff21514d8981	3034
AnnaBridge	156:ff21514d8981	3035	#if defined(LCD)
AnnaBridge	156:ff21514d8981	3036	#define __HAL_RCC_LCD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) != RESET)
AnnaBridge	156:ff21514d8981	3037	#endif /* LCD */
AnnaBridge	156:ff21514d8981	3038
AnnaBridge	156:ff21514d8981	3039	#if defined(RCC_APB1SMENR1_RTCAPBSMEN)
AnnaBridge	156:ff21514d8981	3040	#define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) != RESET)
AnnaBridge	156:ff21514d8981	3041	#endif /* RCC_APB1SMENR1_RTCAPBSMEN */
AnnaBridge	156:ff21514d8981	3042
AnnaBridge	156:ff21514d8981	3043	#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) != RESET)
AnnaBridge	156:ff21514d8981	3044
AnnaBridge	156:ff21514d8981	3045	#if defined(SPI2)
AnnaBridge	156:ff21514d8981	3046	#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) != RESET)
AnnaBridge	156:ff21514d8981	3047	#endif /* SPI2 */
AnnaBridge	156:ff21514d8981	3048
AnnaBridge	156:ff21514d8981	3049	#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) != RESET)
AnnaBridge	156:ff21514d8981	3050
AnnaBridge	156:ff21514d8981	3051	#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) != RESET)
AnnaBridge	156:ff21514d8981	3052
AnnaBridge	156:ff21514d8981	3053	#if defined(USART3)
AnnaBridge	156:ff21514d8981	3054	#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) != RESET)
AnnaBridge	156:ff21514d8981	3055	#endif /* USART3 */
AnnaBridge	156:ff21514d8981	3056
AnnaBridge	156:ff21514d8981	3057	#if defined(UART4)
AnnaBridge	156:ff21514d8981	3058	#define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) != RESET)
AnnaBridge	156:ff21514d8981	3059	#endif /* UART4 */
AnnaBridge	156:ff21514d8981	3060
AnnaBridge	156:ff21514d8981	3061	#if defined(UART5)
AnnaBridge	156:ff21514d8981	3062	#define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) != RESET)
AnnaBridge	156:ff21514d8981	3063	#endif /* UART5 */
AnnaBridge	156:ff21514d8981	3064
AnnaBridge	156:ff21514d8981	3065	#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) != RESET)
AnnaBridge	156:ff21514d8981	3066
AnnaBridge	156:ff21514d8981	3067	#if defined(I2C2)
AnnaBridge	156:ff21514d8981	3068	#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) != RESET)
AnnaBridge	156:ff21514d8981	3069	#endif /* I2C2 */
AnnaBridge	156:ff21514d8981	3070
AnnaBridge	156:ff21514d8981	3071	#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) != RESET)
AnnaBridge	156:ff21514d8981	3072
AnnaBridge	156:ff21514d8981	3073	#if defined(I2C4)
AnnaBridge	156:ff21514d8981	3074	#define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) != RESET)
AnnaBridge	156:ff21514d8981	3075	#endif /* I2C4 */
AnnaBridge	156:ff21514d8981	3076
AnnaBridge	156:ff21514d8981	3077	#if defined(CRS)
AnnaBridge	156:ff21514d8981	3078	#define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) != RESET)
AnnaBridge	156:ff21514d8981	3079	#endif /* CRS */
AnnaBridge	156:ff21514d8981	3080
AnnaBridge	156:ff21514d8981	3081	#define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) != RESET)
AnnaBridge	156:ff21514d8981	3082
AnnaBridge	156:ff21514d8981	3083	#if defined(CAN2)
AnnaBridge	156:ff21514d8981	3084	#define __HAL_RCC_CAN2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN) != RESET)
AnnaBridge	156:ff21514d8981	3085	#endif /* CAN2 */
AnnaBridge	156:ff21514d8981	3086
AnnaBridge	156:ff21514d8981	3087	#if defined(USB)
AnnaBridge	156:ff21514d8981	3088	#define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) != RESET)
AnnaBridge	156:ff21514d8981	3089	#endif /* USB */
AnnaBridge	156:ff21514d8981	3090
AnnaBridge	156:ff21514d8981	3091	#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) != RESET)
AnnaBridge	156:ff21514d8981	3092
AnnaBridge	156:ff21514d8981	3093	#define __HAL_RCC_DAC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) != RESET)
AnnaBridge	156:ff21514d8981	3094
AnnaBridge	156:ff21514d8981	3095	#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) != RESET)
AnnaBridge	156:ff21514d8981	3096
AnnaBridge	156:ff21514d8981	3097	#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) != RESET)
AnnaBridge	156:ff21514d8981	3098
AnnaBridge	156:ff21514d8981	3099	#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) != RESET)
AnnaBridge	156:ff21514d8981	3100
AnnaBridge	156:ff21514d8981	3101	#if defined(SWPMI1)
AnnaBridge	156:ff21514d8981	3102	#define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) != RESET)
AnnaBridge	156:ff21514d8981	3103	#endif /* SWPMI1 */
AnnaBridge	156:ff21514d8981	3104
AnnaBridge	156:ff21514d8981	3105	#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) != RESET)
AnnaBridge	156:ff21514d8981	3106
AnnaBridge	156:ff21514d8981	3107
AnnaBridge	156:ff21514d8981	3108	#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) == RESET)
AnnaBridge	156:ff21514d8981	3109
AnnaBridge	156:ff21514d8981	3110	#if defined(TIM3)
AnnaBridge	156:ff21514d8981	3111	#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) == RESET)
AnnaBridge	156:ff21514d8981	3112	#endif /* TIM3 */
AnnaBridge	156:ff21514d8981	3113
AnnaBridge	156:ff21514d8981	3114	#if defined(TIM4)
AnnaBridge	156:ff21514d8981	3115	#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) == RESET)
AnnaBridge	156:ff21514d8981	3116	#endif /* TIM4 */
AnnaBridge	156:ff21514d8981	3117
AnnaBridge	156:ff21514d8981	3118	#if defined(TIM5)
AnnaBridge	156:ff21514d8981	3119	#define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) == RESET)
AnnaBridge	156:ff21514d8981	3120	#endif /* TIM5 */
AnnaBridge	156:ff21514d8981	3121
AnnaBridge	156:ff21514d8981	3122	#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) == RESET)
AnnaBridge	156:ff21514d8981	3123
AnnaBridge	156:ff21514d8981	3124	#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) == RESET)
AnnaBridge	156:ff21514d8981	3125
AnnaBridge	156:ff21514d8981	3126	#if defined(LCD)
AnnaBridge	156:ff21514d8981	3127	#define __HAL_RCC_LCD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) == RESET)
AnnaBridge	156:ff21514d8981	3128	#endif /* LCD */
AnnaBridge	156:ff21514d8981	3129
AnnaBridge	156:ff21514d8981	3130	#if defined(RCC_APB1SMENR1_RTCAPBSMEN)
AnnaBridge	156:ff21514d8981	3131	#define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) == RESET)
AnnaBridge	156:ff21514d8981	3132	#endif /* RCC_APB1SMENR1_RTCAPBSMEN */
AnnaBridge	156:ff21514d8981	3133
AnnaBridge	156:ff21514d8981	3134	#define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) == RESET)
AnnaBridge	156:ff21514d8981	3135
AnnaBridge	156:ff21514d8981	3136	#if defined(SPI2)
AnnaBridge	156:ff21514d8981	3137	#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) == RESET)
AnnaBridge	156:ff21514d8981	3138	#endif /* SPI2 */
AnnaBridge	156:ff21514d8981	3139
AnnaBridge	156:ff21514d8981	3140	#define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) == RESET)
AnnaBridge	156:ff21514d8981	3141
AnnaBridge	156:ff21514d8981	3142	#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) == RESET)
AnnaBridge	156:ff21514d8981	3143
AnnaBridge	156:ff21514d8981	3144	#if defined(USART3)
AnnaBridge	156:ff21514d8981	3145	#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) == RESET)
AnnaBridge	156:ff21514d8981	3146	#endif /* USART3 */
AnnaBridge	156:ff21514d8981	3147
AnnaBridge	156:ff21514d8981	3148	#if defined(UART4)
AnnaBridge	156:ff21514d8981	3149	#define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) == RESET)
AnnaBridge	156:ff21514d8981	3150	#endif /* UART4 */
AnnaBridge	156:ff21514d8981	3151
AnnaBridge	156:ff21514d8981	3152	#if defined(UART5)
AnnaBridge	156:ff21514d8981	3153	#define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) == RESET)
AnnaBridge	156:ff21514d8981	3154	#endif /* UART5 */
AnnaBridge	156:ff21514d8981	3155
AnnaBridge	156:ff21514d8981	3156	#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) == RESET)
AnnaBridge	156:ff21514d8981	3157
AnnaBridge	156:ff21514d8981	3158	#if defined(I2C2)
AnnaBridge	156:ff21514d8981	3159	#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) == RESET)
AnnaBridge	156:ff21514d8981	3160	#endif /* I2C2 */
AnnaBridge	156:ff21514d8981	3161
AnnaBridge	156:ff21514d8981	3162	#define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) == RESET)
AnnaBridge	156:ff21514d8981	3163
AnnaBridge	156:ff21514d8981	3164	#if defined(I2C4)
AnnaBridge	156:ff21514d8981	3165	#define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) == RESET)
AnnaBridge	156:ff21514d8981	3166	#endif /* I2C4 */
AnnaBridge	156:ff21514d8981	3167
AnnaBridge	156:ff21514d8981	3168	#if defined(CRS)
AnnaBridge	156:ff21514d8981	3169	#define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) == RESET)
AnnaBridge	156:ff21514d8981	3170	#endif /* CRS */
AnnaBridge	156:ff21514d8981	3171
AnnaBridge	156:ff21514d8981	3172	#define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) == RESET)
AnnaBridge	156:ff21514d8981	3173
AnnaBridge	156:ff21514d8981	3174	#if defined(CAN2)
AnnaBridge	156:ff21514d8981	3175	#define __HAL_RCC_CAN2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN2SMEN) == RESET)
AnnaBridge	156:ff21514d8981	3176	#endif /* CAN2 */
AnnaBridge	156:ff21514d8981	3177
AnnaBridge	156:ff21514d8981	3178	#if defined(USB)
AnnaBridge	156:ff21514d8981	3179	#define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) == RESET)
AnnaBridge	156:ff21514d8981	3180	#endif /* USB */
AnnaBridge	156:ff21514d8981	3181
AnnaBridge	156:ff21514d8981	3182	#define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) == RESET)
AnnaBridge	156:ff21514d8981	3183
AnnaBridge	156:ff21514d8981	3184	#define __HAL_RCC_DAC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) == RESET)
AnnaBridge	156:ff21514d8981	3185
AnnaBridge	156:ff21514d8981	3186	#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) == RESET)
AnnaBridge	156:ff21514d8981	3187
AnnaBridge	156:ff21514d8981	3188	#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) == RESET)
AnnaBridge	156:ff21514d8981	3189
AnnaBridge	156:ff21514d8981	3190	#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) == RESET)
AnnaBridge	156:ff21514d8981	3191
AnnaBridge	156:ff21514d8981	3192	#if defined(SWPMI1)
AnnaBridge	156:ff21514d8981	3193	#define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) == RESET)
AnnaBridge	156:ff21514d8981	3194	#endif /* SWPMI1 */
AnnaBridge	156:ff21514d8981	3195
AnnaBridge	156:ff21514d8981	3196	#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) == RESET)
AnnaBridge	156:ff21514d8981	3197
AnnaBridge	156:ff21514d8981	3198	/**
AnnaBridge	156:ff21514d8981	3199	* @}
AnnaBridge	156:ff21514d8981	3200	*/
AnnaBridge	156:ff21514d8981	3201
AnnaBridge	156:ff21514d8981	3202	/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enabled or Disabled Status
AnnaBridge	156:ff21514d8981	3203	* @brief Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not.
AnnaBridge	156:ff21514d8981	3204	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	156:ff21514d8981	3205	* power consumption.
AnnaBridge	156:ff21514d8981	3206	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	156:ff21514d8981	3207	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	156:ff21514d8981	3208	* @{
AnnaBridge	156:ff21514d8981	3209	*/
AnnaBridge	156:ff21514d8981	3210
AnnaBridge	156:ff21514d8981	3211	#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) != RESET)
AnnaBridge	156:ff21514d8981	3212
AnnaBridge	156:ff21514d8981	3213	#if defined(SDMMC1)
AnnaBridge	156:ff21514d8981	3214	#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) != RESET)
AnnaBridge	156:ff21514d8981	3215	#endif /* SDMMC1 */
AnnaBridge	156:ff21514d8981	3216
AnnaBridge	156:ff21514d8981	3217	#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) != RESET)
AnnaBridge	156:ff21514d8981	3218
AnnaBridge	156:ff21514d8981	3219	#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != RESET)
AnnaBridge	156:ff21514d8981	3220
AnnaBridge	156:ff21514d8981	3221	#if defined(TIM8)
AnnaBridge	156:ff21514d8981	3222	#define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) != RESET)
AnnaBridge	156:ff21514d8981	3223	#endif /* TIM8 */
AnnaBridge	156:ff21514d8981	3224
AnnaBridge	156:ff21514d8981	3225	#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != RESET)
AnnaBridge	156:ff21514d8981	3226
AnnaBridge	156:ff21514d8981	3227	#define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) != RESET)
AnnaBridge	156:ff21514d8981	3228
AnnaBridge	156:ff21514d8981	3229	#define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) != RESET)
AnnaBridge	156:ff21514d8981	3230
AnnaBridge	156:ff21514d8981	3231	#if defined(TIM17)
AnnaBridge	156:ff21514d8981	3232	#define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) != RESET)
AnnaBridge	156:ff21514d8981	3233	#endif /* TIM17 */
AnnaBridge	156:ff21514d8981	3234
AnnaBridge	156:ff21514d8981	3235	#define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) != RESET)
AnnaBridge	156:ff21514d8981	3236
AnnaBridge	156:ff21514d8981	3237	#if defined(SAI2)
AnnaBridge	156:ff21514d8981	3238	#define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) != RESET)
AnnaBridge	156:ff21514d8981	3239	#endif /* SAI2 */
AnnaBridge	156:ff21514d8981	3240
AnnaBridge	156:ff21514d8981	3241	#if defined(DFSDM1_Filter0)
AnnaBridge	156:ff21514d8981	3242	#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) != RESET)
AnnaBridge	156:ff21514d8981	3243	#endif /* DFSDM1_Filter0 */
AnnaBridge	156:ff21514d8981	3244
AnnaBridge	156:ff21514d8981	3245
AnnaBridge	156:ff21514d8981	3246	#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) == RESET)
AnnaBridge	156:ff21514d8981	3247
AnnaBridge	156:ff21514d8981	3248	#if defined(SDMMC1)
AnnaBridge	156:ff21514d8981	3249	#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) == RESET)
AnnaBridge	156:ff21514d8981	3250	#endif /* SDMMC1 */
AnnaBridge	156:ff21514d8981	3251
AnnaBridge	156:ff21514d8981	3252	#define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) == RESET)
AnnaBridge	156:ff21514d8981	3253
AnnaBridge	156:ff21514d8981	3254	#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) == RESET)
AnnaBridge	156:ff21514d8981	3255
AnnaBridge	156:ff21514d8981	3256	#if defined(TIM8)
AnnaBridge	156:ff21514d8981	3257	#define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) == RESET)
AnnaBridge	156:ff21514d8981	3258	#endif /* TIM8 */
AnnaBridge	156:ff21514d8981	3259
AnnaBridge	156:ff21514d8981	3260	#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) == RESET)
AnnaBridge	156:ff21514d8981	3261
AnnaBridge	156:ff21514d8981	3262	#define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) == RESET)
AnnaBridge	156:ff21514d8981	3263
AnnaBridge	156:ff21514d8981	3264	#define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) == RESET)
AnnaBridge	156:ff21514d8981	3265
AnnaBridge	156:ff21514d8981	3266	#if defined(TIM17)
AnnaBridge	156:ff21514d8981	3267	#define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) == RESET)
AnnaBridge	156:ff21514d8981	3268	#endif /* TIM17 */
AnnaBridge	156:ff21514d8981	3269
AnnaBridge	156:ff21514d8981	3270	#define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) == RESET)
AnnaBridge	156:ff21514d8981	3271
AnnaBridge	156:ff21514d8981	3272	#if defined(SAI2)
AnnaBridge	156:ff21514d8981	3273	#define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) == RESET)
AnnaBridge	156:ff21514d8981	3274	#endif /* SAI2 */
AnnaBridge	156:ff21514d8981	3275
AnnaBridge	156:ff21514d8981	3276	#if defined(DFSDM1_Filter0)
AnnaBridge	156:ff21514d8981	3277	#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) == RESET)
AnnaBridge	156:ff21514d8981	3278	#endif /* DFSDM1_Filter0 */
AnnaBridge	156:ff21514d8981	3279
AnnaBridge	156:ff21514d8981	3280	/**
AnnaBridge	156:ff21514d8981	3281	* @}
AnnaBridge	156:ff21514d8981	3282	*/
AnnaBridge	156:ff21514d8981	3283
AnnaBridge	156:ff21514d8981	3284	/** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset
AnnaBridge	156:ff21514d8981	3285	* @{
AnnaBridge	156:ff21514d8981	3286	*/
AnnaBridge	156:ff21514d8981	3287
AnnaBridge	156:ff21514d8981	3288	/** @brief Macros to force or release the Backup domain reset.
AnnaBridge	156:ff21514d8981	3289	* @note This function resets the RTC peripheral (including the backup registers)
AnnaBridge	156:ff21514d8981	3290	* and the RTC clock source selection in RCC_CSR register.
AnnaBridge	156:ff21514d8981	3291	* @note The BKPSRAM is not affected by this reset.
AnnaBridge	156:ff21514d8981	3292	* @retval None
AnnaBridge	156:ff21514d8981	3293	*/
AnnaBridge	156:ff21514d8981	3294	#define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)
AnnaBridge	156:ff21514d8981	3295
AnnaBridge	156:ff21514d8981	3296	#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)
AnnaBridge	156:ff21514d8981	3297
AnnaBridge	156:ff21514d8981	3298	/**
AnnaBridge	156:ff21514d8981	3299	* @}
AnnaBridge	156:ff21514d8981	3300	*/
AnnaBridge	156:ff21514d8981	3301
AnnaBridge	156:ff21514d8981	3302	/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
AnnaBridge	156:ff21514d8981	3303	* @{
AnnaBridge	156:ff21514d8981	3304	*/
AnnaBridge	156:ff21514d8981	3305
AnnaBridge	156:ff21514d8981	3306	/** @brief Macros to enable or disable the RTC clock.
AnnaBridge	156:ff21514d8981	3307	* @note As the RTC is in the Backup domain and write access is denied to
AnnaBridge	156:ff21514d8981	3308	* this domain after reset, you have to enable write access using
AnnaBridge	156:ff21514d8981	3309	* HAL_PWR_EnableBkUpAccess() function before to configure the RTC
AnnaBridge	156:ff21514d8981	3310	* (to be done once after reset).
AnnaBridge	156:ff21514d8981	3311	* @note These macros must be used after the RTC clock source was selected.
AnnaBridge	156:ff21514d8981	3312	* @retval None
AnnaBridge	156:ff21514d8981	3313	*/
AnnaBridge	156:ff21514d8981	3314	#define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
AnnaBridge	156:ff21514d8981	3315
AnnaBridge	156:ff21514d8981	3316	#define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
AnnaBridge	156:ff21514d8981	3317
AnnaBridge	156:ff21514d8981	3318	/**
AnnaBridge	156:ff21514d8981	3319	* @}
AnnaBridge	156:ff21514d8981	3320	*/
AnnaBridge	156:ff21514d8981	3321
AnnaBridge	156:ff21514d8981	3322	/** @brief Macros to enable or disable the Internal High Speed 16MHz oscillator (HSI).
AnnaBridge	156:ff21514d8981	3323	* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
AnnaBridge	156:ff21514d8981	3324	* It is used (enabled by hardware) as system clock source after startup
AnnaBridge	156:ff21514d8981	3325	* from Reset, wakeup from STOP and STANDBY mode, or in case of failure
AnnaBridge	156:ff21514d8981	3326	* of the HSE used directly or indirectly as system clock (if the Clock
AnnaBridge	156:ff21514d8981	3327	* Security System CSS is enabled).
AnnaBridge	156:ff21514d8981	3328	* @note HSI can not be stopped if it is used as system clock source. In this case,
AnnaBridge	156:ff21514d8981	3329	* you have to select another source of the system clock then stop the HSI.
AnnaBridge	156:ff21514d8981	3330	* @note After enabling the HSI, the application software should wait on HSIRDY
AnnaBridge	156:ff21514d8981	3331	* flag to be set indicating that HSI clock is stable and can be used as
AnnaBridge	156:ff21514d8981	3332	* system clock source.
AnnaBridge	156:ff21514d8981	3333	* This parameter can be: ENABLE or DISABLE.
AnnaBridge	156:ff21514d8981	3334	* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
AnnaBridge	156:ff21514d8981	3335	* clock cycles.
AnnaBridge	156:ff21514d8981	3336	* @retval None
AnnaBridge	156:ff21514d8981	3337	*/
AnnaBridge	156:ff21514d8981	3338	#define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
AnnaBridge	156:ff21514d8981	3339
AnnaBridge	156:ff21514d8981	3340	#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
AnnaBridge	156:ff21514d8981	3341
AnnaBridge	156:ff21514d8981	3342	/** @brief Macro to adjust the Internal High Speed 16MHz oscillator (HSI) calibration value.
AnnaBridge	156:ff21514d8981	3343	* @note The calibration is used to compensate for the variations in voltage
AnnaBridge	156:ff21514d8981	3344	* and temperature that influence the frequency of the internal HSI RC.
AnnaBridge	156:ff21514d8981	3345	* @param __HSICALIBRATIONVALUE__: specifies the calibration trimming value
AnnaBridge	156:ff21514d8981	3346	* (default is RCC_HSICALIBRATION_DEFAULT).
AnnaBridge	156:ff21514d8981	3347	* This parameter must be a number between 0 and 0x1F (STM32L43x/STM32L44x/STM32L47x/STM32L48x) or 0x7F (for other devices).
AnnaBridge	156:ff21514d8981	3348	* @retval None
AnnaBridge	156:ff21514d8981	3349	*/
AnnaBridge	156:ff21514d8981	3350	#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \
AnnaBridge	156:ff21514d8981	3351	MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << POSITION_VAL(RCC_ICSCR_HSITRIM))
AnnaBridge	156:ff21514d8981	3352
AnnaBridge	156:ff21514d8981	3353	/**
AnnaBridge	156:ff21514d8981	3354	* @brief Macros to enable or disable the wakeup the Internal High Speed oscillator (HSI)
AnnaBridge	156:ff21514d8981	3355	* in parallel to the Internal Multi Speed oscillator (MSI) used at system wakeup.
AnnaBridge	156:ff21514d8981	3356	* @note The enable of this function has not effect on the HSION bit.
AnnaBridge	156:ff21514d8981	3357	* This parameter can be: ENABLE or DISABLE.
AnnaBridge	156:ff21514d8981	3358	* @retval None
AnnaBridge	156:ff21514d8981	3359	*/
AnnaBridge	156:ff21514d8981	3360	#define __HAL_RCC_HSIAUTOMATIC_START_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIASFS)
AnnaBridge	156:ff21514d8981	3361
AnnaBridge	156:ff21514d8981	3362	#define __HAL_RCC_HSIAUTOMATIC_START_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIASFS)
AnnaBridge	156:ff21514d8981	3363
AnnaBridge	156:ff21514d8981	3364	/**
AnnaBridge	156:ff21514d8981	3365	* @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI)
AnnaBridge	156:ff21514d8981	3366	* in STOP mode to be quickly available as kernel clock for USARTs and I2Cs.
AnnaBridge	156:ff21514d8981	3367	* @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication
AnnaBridge	156:ff21514d8981	3368	* speed because of the HSI startup time.
AnnaBridge	156:ff21514d8981	3369	* @note The enable of this function has not effect on the HSION bit.
AnnaBridge	156:ff21514d8981	3370	* This parameter can be: ENABLE or DISABLE.
AnnaBridge	156:ff21514d8981	3371	* @retval None
AnnaBridge	156:ff21514d8981	3372	*/
AnnaBridge	156:ff21514d8981	3373	#define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON)
AnnaBridge	156:ff21514d8981	3374
AnnaBridge	156:ff21514d8981	3375	#define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)
AnnaBridge	156:ff21514d8981	3376
AnnaBridge	156:ff21514d8981	3377	/**
AnnaBridge	156:ff21514d8981	3378	* @brief Macros to enable or disable the Internal Multi Speed oscillator (MSI).
AnnaBridge	156:ff21514d8981	3379	* @note The MSI is stopped by hardware when entering STOP and STANDBY modes.
AnnaBridge	156:ff21514d8981	3380	* It is used (enabled by hardware) as system clock source after
AnnaBridge	156:ff21514d8981	3381	* startup from Reset, wakeup from STOP and STANDBY mode, or in case
AnnaBridge	156:ff21514d8981	3382	* of failure of the HSE used directly or indirectly as system clock
AnnaBridge	156:ff21514d8981	3383	* (if the Clock Security System CSS is enabled).
AnnaBridge	156:ff21514d8981	3384	* @note MSI can not be stopped if it is used as system clock source.
AnnaBridge	156:ff21514d8981	3385	* In this case, you have to select another source of the system
AnnaBridge	156:ff21514d8981	3386	* clock then stop the MSI.
AnnaBridge	156:ff21514d8981	3387	* @note After enabling the MSI, the application software should wait on
AnnaBridge	156:ff21514d8981	3388	* MSIRDY flag to be set indicating that MSI clock is stable and can
AnnaBridge	156:ff21514d8981	3389	* be used as system clock source.
AnnaBridge	156:ff21514d8981	3390	* @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator
AnnaBridge	156:ff21514d8981	3391	* clock cycles.
AnnaBridge	156:ff21514d8981	3392	* @retval None
AnnaBridge	156:ff21514d8981	3393	*/
AnnaBridge	156:ff21514d8981	3394	#define __HAL_RCC_MSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_MSION)
AnnaBridge	156:ff21514d8981	3395
AnnaBridge	156:ff21514d8981	3396	#define __HAL_RCC_MSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSION)
AnnaBridge	156:ff21514d8981	3397
AnnaBridge	156:ff21514d8981	3398	/** @brief Macro Adjusts the Internal Multi Speed oscillator (MSI) calibration value.
AnnaBridge	156:ff21514d8981	3399	* @note The calibration is used to compensate for the variations in voltage
AnnaBridge	156:ff21514d8981	3400	* and temperature that influence the frequency of the internal MSI RC.
AnnaBridge	156:ff21514d8981	3401	* Refer to the Application Note AN3300 for more details on how to
AnnaBridge	156:ff21514d8981	3402	* calibrate the MSI.
AnnaBridge	156:ff21514d8981	3403	* @param __MSICALIBRATIONVALUE__: specifies the calibration trimming value
AnnaBridge	156:ff21514d8981	3404	* (default is RCC_MSICALIBRATION_DEFAULT).
AnnaBridge	156:ff21514d8981	3405	* This parameter must be a number between 0 and 255.
AnnaBridge	156:ff21514d8981	3406	* @retval None
AnnaBridge	156:ff21514d8981	3407	*/
AnnaBridge	156:ff21514d8981	3408	#define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICALIBRATIONVALUE__) \
AnnaBridge	156:ff21514d8981	3409	MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (uint32_t)(__MSICALIBRATIONVALUE__) << 8)
AnnaBridge	156:ff21514d8981	3410
AnnaBridge	156:ff21514d8981	3411	/**
AnnaBridge	156:ff21514d8981	3412	* @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range in run mode
AnnaBridge	156:ff21514d8981	3413	* @note After restart from Reset , the MSI clock is around 4 MHz.
AnnaBridge	156:ff21514d8981	3414	* After stop the startup clock can be MSI (at any of its possible
AnnaBridge	156:ff21514d8981	3415	* frequencies, the one that was used before entering stop mode) or HSI.
AnnaBridge	156:ff21514d8981	3416	* After Standby its frequency can be selected between 4 possible values
AnnaBridge	156:ff21514d8981	3417	* (1, 2, 4 or 8 MHz).
AnnaBridge	156:ff21514d8981	3418	* @note MSIRANGE can be modified when MSI is OFF (MSION=0) or when MSI is ready
AnnaBridge	156:ff21514d8981	3419	* (MSIRDY=1).
AnnaBridge	156:ff21514d8981	3420	* @note The MSI clock range after reset can be modified on the fly.
AnnaBridge	156:ff21514d8981	3421	* @param __MSIRANGEVALUE__: specifies the MSI clock range.
AnnaBridge	156:ff21514d8981	3422	* This parameter must be one of the following values:
AnnaBridge	156:ff21514d8981	3423	* @arg @ref RCC_MSIRANGE_0 MSI clock is around 100 KHz
AnnaBridge	156:ff21514d8981	3424	* @arg @ref RCC_MSIRANGE_1 MSI clock is around 200 KHz
AnnaBridge	156:ff21514d8981	3425	* @arg @ref RCC_MSIRANGE_2 MSI clock is around 400 KHz
AnnaBridge	156:ff21514d8981	3426	* @arg @ref RCC_MSIRANGE_3 MSI clock is around 800 KHz
AnnaBridge	156:ff21514d8981	3427	* @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz
AnnaBridge	156:ff21514d8981	3428	* @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz
AnnaBridge	156:ff21514d8981	3429	* @arg @ref RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset)
AnnaBridge	156:ff21514d8981	3430	* @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz
AnnaBridge	156:ff21514d8981	3431	* @arg @ref RCC_MSIRANGE_8 MSI clock is around 16 MHz
AnnaBridge	156:ff21514d8981	3432	* @arg @ref RCC_MSIRANGE_9 MSI clock is around 24 MHz
AnnaBridge	156:ff21514d8981	3433	* @arg @ref RCC_MSIRANGE_10 MSI clock is around 32 MHz
AnnaBridge	156:ff21514d8981	3434	* @arg @ref RCC_MSIRANGE_11 MSI clock is around 48 MHz
AnnaBridge	156:ff21514d8981	3435	* @retval None
AnnaBridge	156:ff21514d8981	3436	*/
AnnaBridge	156:ff21514d8981	3437	#define __HAL_RCC_MSI_RANGE_CONFIG(__MSIRANGEVALUE__) \
AnnaBridge	156:ff21514d8981	3438	do { \
AnnaBridge	156:ff21514d8981	3439	SET_BIT(RCC->CR, RCC_CR_MSIRGSEL); \
AnnaBridge	156:ff21514d8981	3440	MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, (__MSIRANGEVALUE__)); \
AnnaBridge	156:ff21514d8981	3441	} while(0)
AnnaBridge	156:ff21514d8981	3442
AnnaBridge	156:ff21514d8981	3443	/**
AnnaBridge	156:ff21514d8981	3444	* @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range after Standby mode
AnnaBridge	156:ff21514d8981	3445	* After Standby its frequency can be selected between 4 possible values (1, 2, 4 or 8 MHz).
AnnaBridge	156:ff21514d8981	3446	* @param __MSIRANGEVALUE__: specifies the MSI clock range.
AnnaBridge	156:ff21514d8981	3447	* This parameter must be one of the following values:
AnnaBridge	156:ff21514d8981	3448	* @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz
AnnaBridge	156:ff21514d8981	3449	* @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz
AnnaBridge	156:ff21514d8981	3450	* @arg @ref RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset)
AnnaBridge	156:ff21514d8981	3451	* @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz
AnnaBridge	156:ff21514d8981	3452	* @retval None
AnnaBridge	156:ff21514d8981	3453	*/
AnnaBridge	156:ff21514d8981	3454	#define __HAL_RCC_MSI_STANDBY_RANGE_CONFIG(__MSIRANGEVALUE__) \
AnnaBridge	156:ff21514d8981	3455	MODIFY_REG(RCC->CSR, RCC_CSR_MSISRANGE, (__MSIRANGEVALUE__) << 4U)
AnnaBridge	156:ff21514d8981	3456
AnnaBridge	156:ff21514d8981	3457	/** @brief Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode
AnnaBridge	156:ff21514d8981	3458	* @retval MSI clock range.
AnnaBridge	156:ff21514d8981	3459	* This parameter must be one of the following values:
AnnaBridge	156:ff21514d8981	3460	* @arg @ref RCC_MSIRANGE_0 MSI clock is around 100 KHz
AnnaBridge	156:ff21514d8981	3461	* @arg @ref RCC_MSIRANGE_1 MSI clock is around 200 KHz
AnnaBridge	156:ff21514d8981	3462	* @arg @ref RCC_MSIRANGE_2 MSI clock is around 400 KHz
AnnaBridge	156:ff21514d8981	3463	* @arg @ref RCC_MSIRANGE_3 MSI clock is around 800 KHz
AnnaBridge	156:ff21514d8981	3464	* @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz
AnnaBridge	156:ff21514d8981	3465	* @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz
AnnaBridge	156:ff21514d8981	3466	* @arg @ref RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset)
AnnaBridge	156:ff21514d8981	3467	* @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz
AnnaBridge	156:ff21514d8981	3468	* @arg @ref RCC_MSIRANGE_8 MSI clock is around 16 MHz
AnnaBridge	156:ff21514d8981	3469	* @arg @ref RCC_MSIRANGE_9 MSI clock is around 24 MHz
AnnaBridge	156:ff21514d8981	3470	* @arg @ref RCC_MSIRANGE_10 MSI clock is around 32 MHz
AnnaBridge	156:ff21514d8981	3471	* @arg @ref RCC_MSIRANGE_11 MSI clock is around 48 MHz
AnnaBridge	156:ff21514d8981	3472	*/
AnnaBridge	156:ff21514d8981	3473	#define __HAL_RCC_GET_MSI_RANGE() \
AnnaBridge	156:ff21514d8981	3474	((READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) != RESET) ? \
AnnaBridge	156:ff21514d8981	3475	(uint32_t)(READ_BIT(RCC->CR, RCC_CR_MSIRANGE)) : \
AnnaBridge	156:ff21514d8981	3476	(uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> 4))
AnnaBridge	156:ff21514d8981	3477
AnnaBridge	156:ff21514d8981	3478	/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
AnnaBridge	156:ff21514d8981	3479	* @note After enabling the LSI, the application software should wait on
AnnaBridge	156:ff21514d8981	3480	* LSIRDY flag to be set indicating that LSI clock is stable and can
AnnaBridge	156:ff21514d8981	3481	* be used to clock the IWDG and/or the RTC.
AnnaBridge	156:ff21514d8981	3482	* @note LSI can not be disabled if the IWDG is running.
AnnaBridge	156:ff21514d8981	3483	* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
AnnaBridge	156:ff21514d8981	3484	* clock cycles.
AnnaBridge	156:ff21514d8981	3485	* @retval None
AnnaBridge	156:ff21514d8981	3486	*/
AnnaBridge	156:ff21514d8981	3487	#define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
AnnaBridge	156:ff21514d8981	3488
AnnaBridge	156:ff21514d8981	3489	#define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
AnnaBridge	156:ff21514d8981	3490
AnnaBridge	156:ff21514d8981	3491	/**
AnnaBridge	156:ff21514d8981	3492	* @brief Macro to configure the External High Speed oscillator (HSE).
AnnaBridge	156:ff21514d8981	3493	* @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
AnnaBridge	156:ff21514d8981	3494	* supported by this macro. User should request a transition to HSE Off
AnnaBridge	156:ff21514d8981	3495	* first and then HSE On or HSE Bypass.
AnnaBridge	156:ff21514d8981	3496	* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
AnnaBridge	156:ff21514d8981	3497	* software should wait on HSERDY flag to be set indicating that HSE clock
AnnaBridge	156:ff21514d8981	3498	* is stable and can be used to clock the PLL and/or system clock.
AnnaBridge	156:ff21514d8981	3499	* @note HSE state can not be changed if it is used directly or through the
AnnaBridge	156:ff21514d8981	3500	* PLL as system clock. In this case, you have to select another source
AnnaBridge	156:ff21514d8981	3501	* of the system clock then change the HSE state (ex. disable it).
AnnaBridge	156:ff21514d8981	3502	* @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
AnnaBridge	156:ff21514d8981	3503	* @note This function reset the CSSON bit, so if the clock security system(CSS)
AnnaBridge	156:ff21514d8981	3504	* was previously enabled you have to enable it again after calling this
AnnaBridge	156:ff21514d8981	3505	* function.
AnnaBridge	156:ff21514d8981	3506	* @param __STATE__: specifies the new state of the HSE.
AnnaBridge	156:ff21514d8981	3507	* This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	3508	* @arg @ref RCC_HSE_OFF Turn OFF the HSE oscillator, HSERDY flag goes low after
AnnaBridge	156:ff21514d8981	3509	* 6 HSE oscillator clock cycles.
AnnaBridge	156:ff21514d8981	3510	* @arg @ref RCC_HSE_ON Turn ON the HSE oscillator.
AnnaBridge	156:ff21514d8981	3511	* @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock.
AnnaBridge	156:ff21514d8981	3512	* @retval None
AnnaBridge	156:ff21514d8981	3513	*/
AnnaBridge	156:ff21514d8981	3514	#define __HAL_RCC_HSE_CONFIG(__STATE__) \
AnnaBridge	156:ff21514d8981	3515	do { \
AnnaBridge	156:ff21514d8981	3516	if((__STATE__) == RCC_HSE_ON) \
AnnaBridge	156:ff21514d8981	3517	{ \
AnnaBridge	156:ff21514d8981	3518	SET_BIT(RCC->CR, RCC_CR_HSEON); \
AnnaBridge	156:ff21514d8981	3519	} \
AnnaBridge	156:ff21514d8981	3520	else if((__STATE__) == RCC_HSE_BYPASS) \
AnnaBridge	156:ff21514d8981	3521	{ \
AnnaBridge	156:ff21514d8981	3522	SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
AnnaBridge	156:ff21514d8981	3523	SET_BIT(RCC->CR, RCC_CR_HSEON); \
AnnaBridge	156:ff21514d8981	3524	} \
AnnaBridge	156:ff21514d8981	3525	else \
AnnaBridge	156:ff21514d8981	3526	{ \
AnnaBridge	156:ff21514d8981	3527	CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
AnnaBridge	156:ff21514d8981	3528	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
AnnaBridge	156:ff21514d8981	3529	} \
AnnaBridge	156:ff21514d8981	3530	} while(0)
AnnaBridge	156:ff21514d8981	3531
AnnaBridge	156:ff21514d8981	3532	/**
AnnaBridge	156:ff21514d8981	3533	* @brief Macro to configure the External Low Speed oscillator (LSE).
AnnaBridge	156:ff21514d8981	3534	* @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
AnnaBridge	156:ff21514d8981	3535	* supported by this macro. User should request a transition to LSE Off
AnnaBridge	156:ff21514d8981	3536	* first and then LSE On or LSE Bypass.
AnnaBridge	156:ff21514d8981	3537	* @note As the LSE is in the Backup domain and write access is denied to
AnnaBridge	156:ff21514d8981	3538	* this domain after reset, you have to enable write access using
AnnaBridge	156:ff21514d8981	3539	* HAL_PWR_EnableBkUpAccess() function before to configure the LSE
AnnaBridge	156:ff21514d8981	3540	* (to be done once after reset).
AnnaBridge	156:ff21514d8981	3541	* @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
AnnaBridge	156:ff21514d8981	3542	* software should wait on LSERDY flag to be set indicating that LSE clock
AnnaBridge	156:ff21514d8981	3543	* is stable and can be used to clock the RTC.
AnnaBridge	156:ff21514d8981	3544	* @param __STATE__: specifies the new state of the LSE.
AnnaBridge	156:ff21514d8981	3545	* This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	3546	* @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after
AnnaBridge	156:ff21514d8981	3547	* 6 LSE oscillator clock cycles.
AnnaBridge	156:ff21514d8981	3548	* @arg @ref RCC_LSE_ON Turn ON the LSE oscillator.
AnnaBridge	156:ff21514d8981	3549	* @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock.
AnnaBridge	156:ff21514d8981	3550	* @retval None
AnnaBridge	156:ff21514d8981	3551	*/
AnnaBridge	156:ff21514d8981	3552	#define __HAL_RCC_LSE_CONFIG(__STATE__) \
AnnaBridge	156:ff21514d8981	3553	do { \
AnnaBridge	156:ff21514d8981	3554	if((__STATE__) == RCC_LSE_ON) \
AnnaBridge	156:ff21514d8981	3555	{ \
AnnaBridge	156:ff21514d8981	3556	SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
AnnaBridge	156:ff21514d8981	3557	} \
AnnaBridge	156:ff21514d8981	3558	else if((__STATE__) == RCC_LSE_BYPASS) \
AnnaBridge	156:ff21514d8981	3559	{ \
AnnaBridge	156:ff21514d8981	3560	SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
AnnaBridge	156:ff21514d8981	3561	SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
AnnaBridge	156:ff21514d8981	3562	} \
AnnaBridge	156:ff21514d8981	3563	else \
AnnaBridge	156:ff21514d8981	3564	{ \
AnnaBridge	156:ff21514d8981	3565	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
AnnaBridge	156:ff21514d8981	3566	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
AnnaBridge	156:ff21514d8981	3567	} \
AnnaBridge	156:ff21514d8981	3568	} while(0)
AnnaBridge	156:ff21514d8981	3569
AnnaBridge	156:ff21514d8981	3570	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	156:ff21514d8981	3571
AnnaBridge	156:ff21514d8981	3572	/** @brief Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48).
AnnaBridge	156:ff21514d8981	3573	* @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
AnnaBridge	156:ff21514d8981	3574	* @note After enabling the HSI48, the application software should wait on HSI48RDY
AnnaBridge	156:ff21514d8981	3575	* flag to be set indicating that HSI48 clock is stable.
AnnaBridge	156:ff21514d8981	3576	* This parameter can be: ENABLE or DISABLE.
AnnaBridge	156:ff21514d8981	3577	* @retval None
AnnaBridge	156:ff21514d8981	3578	*/
AnnaBridge	156:ff21514d8981	3579	#define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON)
AnnaBridge	156:ff21514d8981	3580
AnnaBridge	156:ff21514d8981	3581	#define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON)
AnnaBridge	156:ff21514d8981	3582
AnnaBridge	156:ff21514d8981	3583	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	156:ff21514d8981	3584
AnnaBridge	156:ff21514d8981	3585	/** @brief Macros to configure the RTC clock (RTCCLK).
AnnaBridge	156:ff21514d8981	3586	* @note As the RTC clock configuration bits are in the Backup domain and write
AnnaBridge	156:ff21514d8981	3587	* access is denied to this domain after reset, you have to enable write
AnnaBridge	156:ff21514d8981	3588	* access using the Power Backup Access macro before to configure
AnnaBridge	156:ff21514d8981	3589	* the RTC clock source (to be done once after reset).
AnnaBridge	156:ff21514d8981	3590	* @note Once the RTC clock is configured it cannot be changed unless the
AnnaBridge	156:ff21514d8981	3591	* Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by
AnnaBridge	156:ff21514d8981	3592	* a Power On Reset (POR).
AnnaBridge	156:ff21514d8981	3593	*
AnnaBridge	156:ff21514d8981	3594	* @param __RTC_CLKSOURCE__: specifies the RTC clock source.
AnnaBridge	156:ff21514d8981	3595	* This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	3596	* @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock.
AnnaBridge	156:ff21514d8981	3597	* @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock.
AnnaBridge	156:ff21514d8981	3598	* @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock.
AnnaBridge	156:ff21514d8981	3599	* @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected
AnnaBridge	156:ff21514d8981	3600	*
AnnaBridge	156:ff21514d8981	3601	* @note If the LSE or LSI is used as RTC clock source, the RTC continues to
AnnaBridge	156:ff21514d8981	3602	* work in STOP and STANDBY modes, and can be used as wakeup source.
AnnaBridge	156:ff21514d8981	3603	* However, when the HSE clock is used as RTC clock source, the RTC
AnnaBridge	156:ff21514d8981	3604	* cannot be used in STOP and STANDBY modes.
AnnaBridge	156:ff21514d8981	3605	* @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
AnnaBridge	156:ff21514d8981	3606	* RTC clock source).
AnnaBridge	156:ff21514d8981	3607	* @retval None
AnnaBridge	156:ff21514d8981	3608	*/
AnnaBridge	156:ff21514d8981	3609	#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) \
AnnaBridge	156:ff21514d8981	3610	MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
AnnaBridge	156:ff21514d8981	3611
AnnaBridge	156:ff21514d8981	3612
AnnaBridge	156:ff21514d8981	3613	/** @brief Macro to get the RTC clock source.
AnnaBridge	156:ff21514d8981	3614	* @retval The returned value can be one of the following:
AnnaBridge	156:ff21514d8981	3615	* @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock.
AnnaBridge	156:ff21514d8981	3616	* @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock.
AnnaBridge	156:ff21514d8981	3617	* @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock.
AnnaBridge	156:ff21514d8981	3618	* @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected
AnnaBridge	156:ff21514d8981	3619	*/
AnnaBridge	156:ff21514d8981	3620	#define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)))
AnnaBridge	156:ff21514d8981	3621
AnnaBridge	156:ff21514d8981	3622	/** @brief Macros to enable or disable the main PLL.
AnnaBridge	156:ff21514d8981	3623	* @note After enabling the main PLL, the application software should wait on
AnnaBridge	156:ff21514d8981	3624	* PLLRDY flag to be set indicating that PLL clock is stable and can
AnnaBridge	156:ff21514d8981	3625	* be used as system clock source.
AnnaBridge	156:ff21514d8981	3626	* @note The main PLL can not be disabled if it is used as system clock source
AnnaBridge	156:ff21514d8981	3627	* @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
AnnaBridge	156:ff21514d8981	3628	* @retval None
AnnaBridge	156:ff21514d8981	3629	*/
AnnaBridge	156:ff21514d8981	3630	#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
AnnaBridge	156:ff21514d8981	3631
AnnaBridge	156:ff21514d8981	3632	#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
AnnaBridge	156:ff21514d8981	3633
AnnaBridge	156:ff21514d8981	3634	/** @brief Macro to configure the PLL clock source.
AnnaBridge	156:ff21514d8981	3635	* @note This function must be used only when the main PLL is disabled.
AnnaBridge	156:ff21514d8981	3636	* @param __PLLSOURCE__: specifies the PLL entry clock source.
AnnaBridge	156:ff21514d8981	3637	* This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	3638	* @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry
AnnaBridge	156:ff21514d8981	3639	* @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry
AnnaBridge	156:ff21514d8981	3640	* @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry
AnnaBridge	156:ff21514d8981	3641	* @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
AnnaBridge	156:ff21514d8981	3642	* @note This clock source is common for the main PLL and audio PLL (PLLSAI1 and PLLSAI2).
AnnaBridge	156:ff21514d8981	3643	* @retval None
AnnaBridge	156:ff21514d8981	3644	*
AnnaBridge	156:ff21514d8981	3645	*/
AnnaBridge	156:ff21514d8981	3646	#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) \
AnnaBridge	156:ff21514d8981	3647	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
AnnaBridge	156:ff21514d8981	3648
AnnaBridge	156:ff21514d8981	3649	/** @brief Macro to configure the PLL source division factor M.
AnnaBridge	156:ff21514d8981	3650	* @note This function must be used only when the main PLL is disabled.
AnnaBridge	156:ff21514d8981	3651	* @param __PLLM__: specifies the division factor for PLL VCO input clock
AnnaBridge	156:ff21514d8981	3652	* This parameter must be a number between Min_Data = 1 and Max_Data = 8.
AnnaBridge	156:ff21514d8981	3653	* @note You have to set the PLLM parameter correctly to ensure that the VCO input
AnnaBridge	156:ff21514d8981	3654	* frequency ranges from 4 to 16 MHz. It is recommended to select a frequency
AnnaBridge	156:ff21514d8981	3655	* of 16 MHz to limit PLL jitter.
AnnaBridge	156:ff21514d8981	3656	* @retval None
AnnaBridge	156:ff21514d8981	3657	*
AnnaBridge	156:ff21514d8981	3658	*/
AnnaBridge	156:ff21514d8981	3659	#define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) \
AnnaBridge	156:ff21514d8981	3660	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, ((__PLLM__) - 1) << 4U)
AnnaBridge	156:ff21514d8981	3661
AnnaBridge	156:ff21514d8981	3662	/**
AnnaBridge	156:ff21514d8981	3663	* @brief Macro to configure the main PLL clock source, multiplication and division factors.
AnnaBridge	156:ff21514d8981	3664	* @note This function must be used only when the main PLL is disabled.
AnnaBridge	156:ff21514d8981	3665	*
AnnaBridge	156:ff21514d8981	3666	* @param __PLLSOURCE__: specifies the PLL entry clock source.
AnnaBridge	156:ff21514d8981	3667	* This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	3668	* @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry
AnnaBridge	156:ff21514d8981	3669	* @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry
AnnaBridge	156:ff21514d8981	3670	* @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry
AnnaBridge	156:ff21514d8981	3671	* @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
AnnaBridge	156:ff21514d8981	3672	* @note This clock source is common for the main PLL and audio PLL (PLLSAI1 and PLLSAI2).
AnnaBridge	156:ff21514d8981	3673	*
AnnaBridge	156:ff21514d8981	3674	* @param __PLLM__: specifies the division factor for PLL VCO input clock.
AnnaBridge	156:ff21514d8981	3675	* This parameter must be a number between 1 and 8.
AnnaBridge	156:ff21514d8981	3676	* @note You have to set the PLLM parameter correctly to ensure that the VCO input
AnnaBridge	156:ff21514d8981	3677	* frequency ranges from 4 to 16 MHz. It is recommended to select a frequency
AnnaBridge	156:ff21514d8981	3678	* of 16 MHz to limit PLL jitter.
AnnaBridge	156:ff21514d8981	3679	*
AnnaBridge	156:ff21514d8981	3680	* @param __PLLN__: specifies the multiplication factor for PLL VCO output clock.
AnnaBridge	156:ff21514d8981	3681	* This parameter must be a number between 8 and 86.
AnnaBridge	156:ff21514d8981	3682	* @note You have to set the PLLN parameter correctly to ensure that the VCO
AnnaBridge	156:ff21514d8981	3683	* output frequency is between 64 and 344 MHz.
AnnaBridge	156:ff21514d8981	3684	*
AnnaBridge	156:ff21514d8981	3685	* @param __PLLP__: specifies the division factor for SAI clock.
AnnaBridge	156:ff21514d8981	3686	* This parameter must be a number in the range (7 or 17) for STM32L47x/STM32L48x
AnnaBridge	156:ff21514d8981	3687	* else (2 to 31).
AnnaBridge	156:ff21514d8981	3688	*
AnnaBridge	156:ff21514d8981	3689	* @param __PLLQ__: specifies the division factor for OTG FS, SDMMC1 and RNG clocks.
AnnaBridge	156:ff21514d8981	3690	* This parameter must be in the range (2, 4, 6 or 8).
AnnaBridge	156:ff21514d8981	3691	* @note If the USB OTG FS is used in your application, you have to set the
AnnaBridge	156:ff21514d8981	3692	* PLLQ parameter correctly to have 48 MHz clock for the USB. However,
AnnaBridge	156:ff21514d8981	3693	* the SDMMC1 and RNG need a frequency lower than or equal to 48 MHz to work
AnnaBridge	156:ff21514d8981	3694	* correctly.
AnnaBridge	156:ff21514d8981	3695	* @param __PLLR__: specifies the division factor for the main system clock.
AnnaBridge	156:ff21514d8981	3696	* @note You have to set the PLLR parameter correctly to not exceed 80MHZ.
AnnaBridge	156:ff21514d8981	3697	* This parameter must be in the range (2, 4, 6 or 8).
AnnaBridge	156:ff21514d8981	3698	* @retval None
AnnaBridge	156:ff21514d8981	3699	*/
AnnaBridge	156:ff21514d8981	3700	#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
AnnaBridge	156:ff21514d8981	3701
AnnaBridge	156:ff21514d8981	3702	#define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \
AnnaBridge	156:ff21514d8981	3703	(RCC->PLLCFGR = (uint32_t)(((__PLLM__) - 1U) << 4U) \| (uint32_t)((__PLLN__) << 8U) \| \
AnnaBridge	156:ff21514d8981	3704	(uint32_t)(__PLLSOURCE__) \| (uint32_t)((((__PLLQ__) >> 1U) - 1U) << 21U) \| (uint32_t)((((__PLLR__) >> 1U) - 1U) << 25U) \| \
AnnaBridge	156:ff21514d8981	3705	(uint32_t)((__PLLP__) << 27U))
AnnaBridge	156:ff21514d8981	3706
AnnaBridge	156:ff21514d8981	3707	#else
AnnaBridge	156:ff21514d8981	3708
AnnaBridge	156:ff21514d8981	3709	#define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \
AnnaBridge	156:ff21514d8981	3710	(RCC->PLLCFGR = (uint32_t)(((__PLLM__) - 1U) << 4U) \| (uint32_t)((__PLLN__) << 8U) \| (uint32_t)(((__PLLP__) >> 4U ) << 17U) \| \
AnnaBridge	156:ff21514d8981	3711	(uint32_t)(__PLLSOURCE__) \| (uint32_t)((((__PLLQ__) >> 1U) - 1U) << 21U) \| (uint32_t)((((__PLLR__) >> 1U) - 1U) << 25U))
AnnaBridge	156:ff21514d8981	3712
AnnaBridge	156:ff21514d8981	3713	#endif /* RCC_PLLP_DIV_2_31_SUPPORT */
AnnaBridge	156:ff21514d8981	3714
AnnaBridge	156:ff21514d8981	3715	/** @brief Macro to get the oscillator used as PLL clock source.
AnnaBridge	156:ff21514d8981	3716	* @retval The oscillator used as PLL clock source. The returned value can be one
AnnaBridge	156:ff21514d8981	3717	* of the following:
AnnaBridge	156:ff21514d8981	3718	* - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source.
AnnaBridge	156:ff21514d8981	3719	* - RCC_PLLSOURCE_MSI: MSI oscillator is used as PLL clock source.
AnnaBridge	156:ff21514d8981	3720	* - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
AnnaBridge	156:ff21514d8981	3721	* - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
AnnaBridge	156:ff21514d8981	3722	*/
AnnaBridge	156:ff21514d8981	3723	#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
AnnaBridge	156:ff21514d8981	3724
AnnaBridge	156:ff21514d8981	3725	/**
AnnaBridge	156:ff21514d8981	3726	* @brief Enable or disable each clock output (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK)
AnnaBridge	156:ff21514d8981	3727	* @note Enabling/disabling clock outputs RCC_PLL_SAI3CLK and RCC_PLL_48M1CLK can be done at anytime
AnnaBridge	156:ff21514d8981	3728	* without the need to stop the PLL in order to save power. But RCC_PLL_SYSCLK cannot
AnnaBridge	156:ff21514d8981	3729	* be stopped if used as System Clock.
AnnaBridge	156:ff21514d8981	3730	* @param __PLLCLOCKOUT__: specifies the PLL clock to be output.
AnnaBridge	156:ff21514d8981	3731	* This parameter can be one or a combination of the following values:
AnnaBridge	156:ff21514d8981	3732	* @arg @ref RCC_PLL_SAI3CLK This clock is used to generate an accurate clock to achieve
AnnaBridge	156:ff21514d8981	3733	* high-quality audio performance on SAI interface in case.
AnnaBridge	156:ff21514d8981	3734	* @arg @ref RCC_PLL_48M1CLK This Clock is used to generate the clock for the USB OTG FS (48 MHz),
AnnaBridge	156:ff21514d8981	3735	* the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).
AnnaBridge	156:ff21514d8981	3736	* @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 80MHz)
AnnaBridge	156:ff21514d8981	3737	* @retval None
AnnaBridge	156:ff21514d8981	3738	*/
AnnaBridge	156:ff21514d8981	3739	#define __HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__) SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
AnnaBridge	156:ff21514d8981	3740
AnnaBridge	156:ff21514d8981	3741	#define __HAL_RCC_PLLCLKOUT_DISABLE(__PLLCLOCKOUT__) CLEAR_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
AnnaBridge	156:ff21514d8981	3742
AnnaBridge	156:ff21514d8981	3743	/**
AnnaBridge	156:ff21514d8981	3744	* @brief Get clock output enable status (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK)
AnnaBridge	156:ff21514d8981	3745	* @param __PLLCLOCKOUT__: specifies the output PLL clock to be checked.
AnnaBridge	156:ff21514d8981	3746	* This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	3747	* @arg @ref RCC_PLL_SAI3CLK This clock is used to generate an accurate clock to achieve
AnnaBridge	156:ff21514d8981	3748	* high-quality audio performance on SAI interface in case.
AnnaBridge	156:ff21514d8981	3749	* @arg @ref RCC_PLL_48M1CLK This Clock is used to generate the clock for the USB OTG FS (48 MHz),
AnnaBridge	156:ff21514d8981	3750	* the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz).
AnnaBridge	156:ff21514d8981	3751	* @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 80MHz)
AnnaBridge	156:ff21514d8981	3752	* @retval SET / RESET
AnnaBridge	156:ff21514d8981	3753	*/
AnnaBridge	156:ff21514d8981	3754	#define __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLLCLOCKOUT__) READ_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
AnnaBridge	156:ff21514d8981	3755
AnnaBridge	156:ff21514d8981	3756	/**
AnnaBridge	156:ff21514d8981	3757	* @brief Macro to configure the system clock source.
AnnaBridge	156:ff21514d8981	3758	* @param __SYSCLKSOURCE__: specifies the system clock source.
AnnaBridge	156:ff21514d8981	3759	* This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	3760	* - RCC_SYSCLKSOURCE_MSI: MSI oscillator is used as system clock source.
AnnaBridge	156:ff21514d8981	3761	* - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
AnnaBridge	156:ff21514d8981	3762	* - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
AnnaBridge	156:ff21514d8981	3763	* - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
AnnaBridge	156:ff21514d8981	3764	* @retval None
AnnaBridge	156:ff21514d8981	3765	*/
AnnaBridge	156:ff21514d8981	3766	#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
AnnaBridge	156:ff21514d8981	3767	MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
AnnaBridge	156:ff21514d8981	3768
AnnaBridge	156:ff21514d8981	3769	/** @brief Macro to get the clock source used as system clock.
AnnaBridge	156:ff21514d8981	3770	* @retval The clock source used as system clock. The returned value can be one
AnnaBridge	156:ff21514d8981	3771	* of the following:
AnnaBridge	156:ff21514d8981	3772	* - RCC_SYSCLKSOURCE_STATUS_MSI: MSI used as system clock.
AnnaBridge	156:ff21514d8981	3773	* - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
AnnaBridge	156:ff21514d8981	3774	* - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
AnnaBridge	156:ff21514d8981	3775	* - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
AnnaBridge	156:ff21514d8981	3776	*/
AnnaBridge	156:ff21514d8981	3777	#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
AnnaBridge	156:ff21514d8981	3778
AnnaBridge	156:ff21514d8981	3779	/**
AnnaBridge	156:ff21514d8981	3780	* @brief Macro to configure the External Low Speed oscillator (LSE) drive capability.
AnnaBridge	156:ff21514d8981	3781	* @note As the LSE is in the Backup domain and write access is denied to
AnnaBridge	156:ff21514d8981	3782	* this domain after reset, you have to enable write access using
AnnaBridge	156:ff21514d8981	3783	* HAL_PWR_EnableBkUpAccess() function before to configure the LSE
AnnaBridge	156:ff21514d8981	3784	* (to be done once after reset).
AnnaBridge	156:ff21514d8981	3785	* @param __LSEDRIVE__: specifies the new state of the LSE drive capability.
AnnaBridge	156:ff21514d8981	3786	* This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	3787	* @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability.
AnnaBridge	156:ff21514d8981	3788	* @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability.
AnnaBridge	156:ff21514d8981	3789	* @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability.
AnnaBridge	156:ff21514d8981	3790	* @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability.
AnnaBridge	156:ff21514d8981	3791	* @retval None
AnnaBridge	156:ff21514d8981	3792	*/
AnnaBridge	156:ff21514d8981	3793	#define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \
AnnaBridge	156:ff21514d8981	3794	MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__))
AnnaBridge	156:ff21514d8981	3795
AnnaBridge	156:ff21514d8981	3796	/**
AnnaBridge	156:ff21514d8981	3797	* @brief Macro to configure the wake up from stop clock.
AnnaBridge	156:ff21514d8981	3798	* @param __STOPWUCLK__: specifies the clock source used after wake up from stop.
AnnaBridge	156:ff21514d8981	3799	* This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	3800	* @arg @ref RCC_STOP_WAKEUPCLOCK_MSI MSI selected as system clock source
AnnaBridge	156:ff21514d8981	3801	* @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI selected as system clock source
AnnaBridge	156:ff21514d8981	3802	* @retval None
AnnaBridge	156:ff21514d8981	3803	*/
AnnaBridge	156:ff21514d8981	3804	#define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__STOPWUCLK__) \
AnnaBridge	156:ff21514d8981	3805	MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__STOPWUCLK__))
AnnaBridge	156:ff21514d8981	3806
AnnaBridge	156:ff21514d8981	3807
AnnaBridge	156:ff21514d8981	3808	/** @brief Macro to configure the MCO clock.
AnnaBridge	156:ff21514d8981	3809	* @param __MCOCLKSOURCE__ specifies the MCO clock source.
AnnaBridge	156:ff21514d8981	3810	* This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	3811	* @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled
AnnaBridge	156:ff21514d8981	3812	* @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source
AnnaBridge	156:ff21514d8981	3813	* @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO source
AnnaBridge	156:ff21514d8981	3814	* @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source
AnnaBridge	156:ff21514d8981	3815	* @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee
AnnaBridge	156:ff21514d8981	3816	* @arg @ref RCC_MCO1SOURCE_PLLCLK Main PLL clock selected as MCO source
AnnaBridge	156:ff21514d8981	3817	* @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source
AnnaBridge	156:ff21514d8981	3818	* @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source
AnnaBridge	156:ff21514d8981	3819	@if STM32L443xx
AnnaBridge	156:ff21514d8981	3820	* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48
AnnaBridge	156:ff21514d8981	3821	@endif
AnnaBridge	156:ff21514d8981	3822	@if STM32L462xx
AnnaBridge	156:ff21514d8981	3823	* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48
AnnaBridge	156:ff21514d8981	3824	@endif
AnnaBridge	156:ff21514d8981	3825	@if STM32L4A6xx
AnnaBridge	156:ff21514d8981	3826	* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48
AnnaBridge	156:ff21514d8981	3827	@endif
AnnaBridge	156:ff21514d8981	3828	* @param __MCODIV__ specifies the MCO clock prescaler.
AnnaBridge	156:ff21514d8981	3829	* This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	3830	* @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1
AnnaBridge	156:ff21514d8981	3831	* @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2
AnnaBridge	156:ff21514d8981	3832	* @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4
AnnaBridge	156:ff21514d8981	3833	* @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8
AnnaBridge	156:ff21514d8981	3834	* @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16
AnnaBridge	156:ff21514d8981	3835	*/
AnnaBridge	156:ff21514d8981	3836	#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
AnnaBridge	156:ff21514d8981	3837	MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL \| RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) \| (__MCODIV__)))
AnnaBridge	156:ff21514d8981	3838
AnnaBridge	156:ff21514d8981	3839	/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
AnnaBridge	156:ff21514d8981	3840	* @brief macros to manage the specified RCC Flags and interrupts.
AnnaBridge	156:ff21514d8981	3841	* @{
AnnaBridge	156:ff21514d8981	3842	*/
AnnaBridge	156:ff21514d8981	3843
AnnaBridge	156:ff21514d8981	3844	/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
AnnaBridge	156:ff21514d8981	3845	* the selected interrupts).
AnnaBridge	156:ff21514d8981	3846	* @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
AnnaBridge	156:ff21514d8981	3847	* This parameter can be any combination of the following values:
AnnaBridge	156:ff21514d8981	3848	* @arg @ref RCC_IT_LSIRDY LSI ready interrupt
AnnaBridge	156:ff21514d8981	3849	* @arg @ref RCC_IT_LSERDY LSE ready interrupt
AnnaBridge	156:ff21514d8981	3850	* @arg @ref RCC_IT_MSIRDY HSI ready interrupt
AnnaBridge	156:ff21514d8981	3851	* @arg @ref RCC_IT_HSIRDY HSI ready interrupt
AnnaBridge	156:ff21514d8981	3852	* @arg @ref RCC_IT_HSERDY HSE ready interrupt
AnnaBridge	156:ff21514d8981	3853	* @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt
AnnaBridge	156:ff21514d8981	3854	* @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt
AnnaBridge	156:ff21514d8981	3855	* @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2
AnnaBridge	156:ff21514d8981	3856	* @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt
AnnaBridge	156:ff21514d8981	3857	@if STM32L443xx
AnnaBridge	156:ff21514d8981	3858	* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
AnnaBridge	156:ff21514d8981	3859	@endif
AnnaBridge	156:ff21514d8981	3860	@if STM32L462xx
AnnaBridge	156:ff21514d8981	3861	* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
AnnaBridge	156:ff21514d8981	3862	@endif
AnnaBridge	156:ff21514d8981	3863	@if STM32L4A6xx
AnnaBridge	156:ff21514d8981	3864	* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
AnnaBridge	156:ff21514d8981	3865	@endif
AnnaBridge	156:ff21514d8981	3866	* @retval None
AnnaBridge	156:ff21514d8981	3867	*/
AnnaBridge	156:ff21514d8981	3868	#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
AnnaBridge	156:ff21514d8981	3869
AnnaBridge	156:ff21514d8981	3870	/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
AnnaBridge	156:ff21514d8981	3871	* the selected interrupts).
AnnaBridge	156:ff21514d8981	3872	* @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
AnnaBridge	156:ff21514d8981	3873	* This parameter can be any combination of the following values:
AnnaBridge	156:ff21514d8981	3874	* @arg @ref RCC_IT_LSIRDY LSI ready interrupt
AnnaBridge	156:ff21514d8981	3875	* @arg @ref RCC_IT_LSERDY LSE ready interrupt
AnnaBridge	156:ff21514d8981	3876	* @arg @ref RCC_IT_MSIRDY HSI ready interrupt
AnnaBridge	156:ff21514d8981	3877	* @arg @ref RCC_IT_HSIRDY HSI ready interrupt
AnnaBridge	156:ff21514d8981	3878	* @arg @ref RCC_IT_HSERDY HSE ready interrupt
AnnaBridge	156:ff21514d8981	3879	* @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt
AnnaBridge	156:ff21514d8981	3880	* @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt
AnnaBridge	156:ff21514d8981	3881	* @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2
AnnaBridge	156:ff21514d8981	3882	* @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt
AnnaBridge	156:ff21514d8981	3883	@if STM32L443xx
AnnaBridge	156:ff21514d8981	3884	* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
AnnaBridge	156:ff21514d8981	3885	@endif
AnnaBridge	156:ff21514d8981	3886	@if STM32L462xx
AnnaBridge	156:ff21514d8981	3887	* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
AnnaBridge	156:ff21514d8981	3888	@endif
AnnaBridge	156:ff21514d8981	3889	@if STM32L4A6xx
AnnaBridge	156:ff21514d8981	3890	* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
AnnaBridge	156:ff21514d8981	3891	@endif
AnnaBridge	156:ff21514d8981	3892	* @retval None
AnnaBridge	156:ff21514d8981	3893	*/
AnnaBridge	156:ff21514d8981	3894	#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
AnnaBridge	156:ff21514d8981	3895
AnnaBridge	156:ff21514d8981	3896	/** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
AnnaBridge	156:ff21514d8981	3897	* bits to clear the selected interrupt pending bits.
AnnaBridge	156:ff21514d8981	3898	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
AnnaBridge	156:ff21514d8981	3899	* This parameter can be any combination of the following values:
AnnaBridge	156:ff21514d8981	3900	* @arg @ref RCC_IT_LSIRDY LSI ready interrupt
AnnaBridge	156:ff21514d8981	3901	* @arg @ref RCC_IT_LSERDY LSE ready interrupt
AnnaBridge	156:ff21514d8981	3902	* @arg @ref RCC_IT_MSIRDY MSI ready interrupt
AnnaBridge	156:ff21514d8981	3903	* @arg @ref RCC_IT_HSIRDY HSI ready interrupt
AnnaBridge	156:ff21514d8981	3904	* @arg @ref RCC_IT_HSERDY HSE ready interrupt
AnnaBridge	156:ff21514d8981	3905	* @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt
AnnaBridge	156:ff21514d8981	3906	* @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt
AnnaBridge	156:ff21514d8981	3907	* @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2
AnnaBridge	156:ff21514d8981	3908	* @arg @ref RCC_IT_CSS HSE Clock security system interrupt
AnnaBridge	156:ff21514d8981	3909	* @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt
AnnaBridge	156:ff21514d8981	3910	@if STM32L443xx
AnnaBridge	156:ff21514d8981	3911	* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
AnnaBridge	156:ff21514d8981	3912	@endif
AnnaBridge	156:ff21514d8981	3913	@if STM32L462xx
AnnaBridge	156:ff21514d8981	3914	* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
AnnaBridge	156:ff21514d8981	3915	@endif
AnnaBridge	156:ff21514d8981	3916	@if STM32L4A6xx
AnnaBridge	156:ff21514d8981	3917	* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
AnnaBridge	156:ff21514d8981	3918	@endif
AnnaBridge	156:ff21514d8981	3919	* @retval None
AnnaBridge	156:ff21514d8981	3920	*/
AnnaBridge	156:ff21514d8981	3921	#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))
AnnaBridge	156:ff21514d8981	3922
AnnaBridge	156:ff21514d8981	3923	/** @brief Check whether the RCC interrupt has occurred or not.
AnnaBridge	156:ff21514d8981	3924	* @param __INTERRUPT__: specifies the RCC interrupt source to check.
AnnaBridge	156:ff21514d8981	3925	* This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	3926	* @arg @ref RCC_IT_LSIRDY LSI ready interrupt
AnnaBridge	156:ff21514d8981	3927	* @arg @ref RCC_IT_LSERDY LSE ready interrupt
AnnaBridge	156:ff21514d8981	3928	* @arg @ref RCC_IT_MSIRDY MSI ready interrupt
AnnaBridge	156:ff21514d8981	3929	* @arg @ref RCC_IT_HSIRDY HSI ready interrupt
AnnaBridge	156:ff21514d8981	3930	* @arg @ref RCC_IT_HSERDY HSE ready interrupt
AnnaBridge	156:ff21514d8981	3931	* @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt
AnnaBridge	156:ff21514d8981	3932	* @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt
AnnaBridge	156:ff21514d8981	3933	* @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2
AnnaBridge	156:ff21514d8981	3934	* @arg @ref RCC_IT_CSS HSE Clock security system interrupt
AnnaBridge	156:ff21514d8981	3935	* @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt
AnnaBridge	156:ff21514d8981	3936	@if STM32L443xx
AnnaBridge	156:ff21514d8981	3937	* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
AnnaBridge	156:ff21514d8981	3938	@endif
AnnaBridge	156:ff21514d8981	3939	@if STM32L462xx
AnnaBridge	156:ff21514d8981	3940	* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
AnnaBridge	156:ff21514d8981	3941	@endif
AnnaBridge	156:ff21514d8981	3942	@if STM32L4A6xx
AnnaBridge	156:ff21514d8981	3943	* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
AnnaBridge	156:ff21514d8981	3944	@endif
AnnaBridge	156:ff21514d8981	3945	* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
AnnaBridge	156:ff21514d8981	3946	*/
AnnaBridge	156:ff21514d8981	3947	#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
AnnaBridge	156:ff21514d8981	3948
AnnaBridge	156:ff21514d8981	3949	/** @brief Set RMVF bit to clear the reset flags.
AnnaBridge	156:ff21514d8981	3950	* The reset flags are: RCC_FLAG_FWRRST, RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_BORRST,
AnnaBridge	156:ff21514d8981	3951	* RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
AnnaBridge	156:ff21514d8981	3952	* @retval None
AnnaBridge	156:ff21514d8981	3953	*/
AnnaBridge	156:ff21514d8981	3954	#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR \|= RCC_CSR_RMVF)
AnnaBridge	156:ff21514d8981	3955
AnnaBridge	156:ff21514d8981	3956	/** @brief Check whether the selected RCC flag is set or not.
AnnaBridge	156:ff21514d8981	3957	* @param __FLAG__: specifies the flag to check.
AnnaBridge	156:ff21514d8981	3958	* This parameter can be one of the following values:
AnnaBridge	156:ff21514d8981	3959	* @arg @ref RCC_FLAG_MSIRDY MSI oscillator clock ready
AnnaBridge	156:ff21514d8981	3960	* @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready
AnnaBridge	156:ff21514d8981	3961	* @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready
AnnaBridge	156:ff21514d8981	3962	* @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready
AnnaBridge	156:ff21514d8981	3963	* @arg @ref RCC_FLAG_PLLSAI1RDY PLLSAI1 clock ready
AnnaBridge	156:ff21514d8981	3964	* @arg @ref RCC_FLAG_PLLSAI2RDY PLLSAI2 clock ready for devices with PLLSAI2
AnnaBridge	156:ff21514d8981	3965	@if STM32L443xx
AnnaBridge	156:ff21514d8981	3966	* @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready for devices with HSI48
AnnaBridge	156:ff21514d8981	3967	@endif
AnnaBridge	156:ff21514d8981	3968	@if STM32L462xx
AnnaBridge	156:ff21514d8981	3969	* @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready for devices with HSI48
AnnaBridge	156:ff21514d8981	3970	@endif
AnnaBridge	156:ff21514d8981	3971	@if STM32L4A6xx
AnnaBridge	156:ff21514d8981	3972	* @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready for devices with HSI48
AnnaBridge	156:ff21514d8981	3973	@endif
AnnaBridge	156:ff21514d8981	3974	* @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready
AnnaBridge	156:ff21514d8981	3975	* @arg @ref RCC_FLAG_LSECSSD Clock security system failure on LSE oscillator detection
AnnaBridge	156:ff21514d8981	3976	* @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready
AnnaBridge	156:ff21514d8981	3977	* @arg @ref RCC_FLAG_BORRST BOR reset
AnnaBridge	156:ff21514d8981	3978	* @arg @ref RCC_FLAG_OBLRST OBLRST reset
AnnaBridge	156:ff21514d8981	3979	* @arg @ref RCC_FLAG_PINRST Pin reset
AnnaBridge	156:ff21514d8981	3980	* @arg @ref RCC_FLAG_FWRST FIREWALL reset
AnnaBridge	156:ff21514d8981	3981	* @arg @ref RCC_FLAG_RMVF Remove reset Flag
AnnaBridge	156:ff21514d8981	3982	* @arg @ref RCC_FLAG_SFTRST Software reset
AnnaBridge	156:ff21514d8981	3983	* @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset
AnnaBridge	156:ff21514d8981	3984	* @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset
AnnaBridge	156:ff21514d8981	3985	* @arg @ref RCC_FLAG_LPWRRST Low Power reset
AnnaBridge	156:ff21514d8981	3986	* @retval The new state of __FLAG__ (TRUE or FALSE).
AnnaBridge	156:ff21514d8981	3987	*/
AnnaBridge	156:ff21514d8981	3988	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	156:ff21514d8981	3989	#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \
AnnaBridge	156:ff21514d8981	3990	((((__FLAG__) >> 5U) == 4U) ? RCC->CRRCR : \
AnnaBridge	156:ff21514d8981	3991	((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \
AnnaBridge	156:ff21514d8981	3992	((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR)))) & \
AnnaBridge	156:ff21514d8981	3993	((uint32_t)1U << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) \
AnnaBridge	156:ff21514d8981	3994	? 1U : 0U)
AnnaBridge	156:ff21514d8981	3995	#else
AnnaBridge	156:ff21514d8981	3996	#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \
AnnaBridge	156:ff21514d8981	3997	((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \
AnnaBridge	156:ff21514d8981	3998	((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR))) & \
AnnaBridge	156:ff21514d8981	3999	((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) \
AnnaBridge	156:ff21514d8981	4000	? 1U : 0U)
AnnaBridge	156:ff21514d8981	4001	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	156:ff21514d8981	4002
AnnaBridge	156:ff21514d8981	4003	/**
AnnaBridge	156:ff21514d8981	4004	* @}
AnnaBridge	156:ff21514d8981	4005	*/
AnnaBridge	156:ff21514d8981	4006
AnnaBridge	156:ff21514d8981	4007	/**
AnnaBridge	156:ff21514d8981	4008	* @}
AnnaBridge	156:ff21514d8981	4009	*/
AnnaBridge	156:ff21514d8981	4010
AnnaBridge	156:ff21514d8981	4011	/* Private constants ---------------------------------------------------------*/
AnnaBridge	156:ff21514d8981	4012	/** @defgroup RCC_Private_Constants RCC Private Constants
AnnaBridge	156:ff21514d8981	4013	* @{
AnnaBridge	156:ff21514d8981	4014	*/
AnnaBridge	156:ff21514d8981	4015	/* Defines used for Flags */
AnnaBridge	156:ff21514d8981	4016	#define CR_REG_INDEX ((uint32_t)1U)
AnnaBridge	156:ff21514d8981	4017	#define BDCR_REG_INDEX ((uint32_t)2U)
AnnaBridge	156:ff21514d8981	4018	#define CSR_REG_INDEX ((uint32_t)3U)
AnnaBridge	156:ff21514d8981	4019	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	156:ff21514d8981	4020	#define CRRCR_REG_INDEX ((uint32_t)4U)
AnnaBridge	156:ff21514d8981	4021	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	156:ff21514d8981	4022
AnnaBridge	156:ff21514d8981	4023	#define RCC_FLAG_MASK ((uint32_t)0x1FU)
AnnaBridge	156:ff21514d8981	4024	/**
AnnaBridge	156:ff21514d8981	4025	* @}
AnnaBridge	156:ff21514d8981	4026	*/
AnnaBridge	156:ff21514d8981	4027
AnnaBridge	156:ff21514d8981	4028	/* Private macros ------------------------------------------------------------*/
AnnaBridge	156:ff21514d8981	4029	/** @addtogroup RCC_Private_Macros
AnnaBridge	156:ff21514d8981	4030	* @{
AnnaBridge	156:ff21514d8981	4031	*/
AnnaBridge	156:ff21514d8981	4032
AnnaBridge	156:ff21514d8981	4033	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	156:ff21514d8981	4034	#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) \|\| \
AnnaBridge	156:ff21514d8981	4035	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) \|\| \
AnnaBridge	156:ff21514d8981	4036	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) \|\| \
AnnaBridge	156:ff21514d8981	4037	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) \|\| \
AnnaBridge	156:ff21514d8981	4038	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) \|\| \
AnnaBridge	156:ff21514d8981	4039	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) \|\| \
AnnaBridge	156:ff21514d8981	4040	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
AnnaBridge	156:ff21514d8981	4041	#else
AnnaBridge	156:ff21514d8981	4042	#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) \|\| \
AnnaBridge	156:ff21514d8981	4043	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) \|\| \
AnnaBridge	156:ff21514d8981	4044	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) \|\| \
AnnaBridge	156:ff21514d8981	4045	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) \|\| \
AnnaBridge	156:ff21514d8981	4046	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) \|\| \
AnnaBridge	156:ff21514d8981	4047	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
AnnaBridge	156:ff21514d8981	4048	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	156:ff21514d8981	4049
AnnaBridge	156:ff21514d8981	4050	#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) \|\| ((__HSE__) == RCC_HSE_ON) \|\| \
AnnaBridge	156:ff21514d8981	4051	((__HSE__) == RCC_HSE_BYPASS))
AnnaBridge	156:ff21514d8981	4052
AnnaBridge	156:ff21514d8981	4053	#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) \|\| ((__LSE__) == RCC_LSE_ON) \|\| \
AnnaBridge	156:ff21514d8981	4054	((__LSE__) == RCC_LSE_BYPASS))
AnnaBridge	156:ff21514d8981	4055
AnnaBridge	156:ff21514d8981	4056	#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) \|\| ((__HSI__) == RCC_HSI_ON))
AnnaBridge	156:ff21514d8981	4057
AnnaBridge	156:ff21514d8981	4058	#define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)( RCC_ICSCR_HSITRIM >> POSITION_VAL(RCC_ICSCR_HSITRIM)))
AnnaBridge	156:ff21514d8981	4059
AnnaBridge	156:ff21514d8981	4060	#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) \|\| ((__LSI__) == RCC_LSI_ON))
AnnaBridge	156:ff21514d8981	4061
AnnaBridge	156:ff21514d8981	4062	#define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) \|\| ((__MSI__) == RCC_MSI_ON))
AnnaBridge	156:ff21514d8981	4063
AnnaBridge	156:ff21514d8981	4064	#define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)255U)
AnnaBridge	156:ff21514d8981	4065
AnnaBridge	156:ff21514d8981	4066	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	156:ff21514d8981	4067	#define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) \|\| ((__HSI48__) == RCC_HSI48_ON))
AnnaBridge	156:ff21514d8981	4068	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	156:ff21514d8981	4069
AnnaBridge	156:ff21514d8981	4070	#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) \|\|((__PLL__) == RCC_PLL_OFF) \|\| \
AnnaBridge	156:ff21514d8981	4071	((__PLL__) == RCC_PLL_ON))
AnnaBridge	156:ff21514d8981	4072
AnnaBridge	156:ff21514d8981	4073	#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_NONE) \|\| \
AnnaBridge	156:ff21514d8981	4074	((__SOURCE__) == RCC_PLLSOURCE_MSI) \|\| \
AnnaBridge	156:ff21514d8981	4075	((__SOURCE__) == RCC_PLLSOURCE_HSI) \|\| \
AnnaBridge	156:ff21514d8981	4076	((__SOURCE__) == RCC_PLLSOURCE_HSE))
AnnaBridge	156:ff21514d8981	4077
AnnaBridge	156:ff21514d8981	4078	#define IS_RCC_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U))
AnnaBridge	156:ff21514d8981	4079
AnnaBridge	156:ff21514d8981	4080	#define IS_RCC_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))
AnnaBridge	156:ff21514d8981	4081
AnnaBridge	156:ff21514d8981	4082	#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
AnnaBridge	156:ff21514d8981	4083	#define IS_RCC_PLLP_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U))
AnnaBridge	156:ff21514d8981	4084	#else
AnnaBridge	156:ff21514d8981	4085	#define IS_RCC_PLLP_VALUE(__VALUE__) (((__VALUE__) == 7U) \|\| ((__VALUE__) == 17U))
AnnaBridge	156:ff21514d8981	4086	#endif /RCC_PLLP_DIV_2_31_SUPPORT /
AnnaBridge	156:ff21514d8981	4087
AnnaBridge	156:ff21514d8981	4088	#define IS_RCC_PLLQ_VALUE(__VALUE__) (((__VALUE__) == 2U) \|\| ((__VALUE__) == 4U) \|\| \
AnnaBridge	156:ff21514d8981	4089	((__VALUE__) == 6U) \|\| ((__VALUE__) == 8U))
AnnaBridge	156:ff21514d8981	4090
AnnaBridge	156:ff21514d8981	4091	#define IS_RCC_PLLR_VALUE(__VALUE__) (((__VALUE__) == 2U) \|\| ((__VALUE__) == 4U) \|\| \
AnnaBridge	156:ff21514d8981	4092	((__VALUE__) == 6U) \|\| ((__VALUE__) == 8U))
AnnaBridge	156:ff21514d8981	4093
AnnaBridge	156:ff21514d8981	4094	#define IS_RCC_PLLSAI1CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI1_SAI1CLK) == RCC_PLLSAI1_SAI1CLK) \|\| \
AnnaBridge	156:ff21514d8981	4095	(((__VALUE__) & RCC_PLLSAI1_48M2CLK) == RCC_PLLSAI1_48M2CLK) \|\| \
AnnaBridge	156:ff21514d8981	4096	(((__VALUE__) & RCC_PLLSAI1_ADC1CLK) == RCC_PLLSAI1_ADC1CLK)) && \
AnnaBridge	156:ff21514d8981	4097	(((__VALUE__) & ~(RCC_PLLSAI1_SAI1CLK\|RCC_PLLSAI1_48M2CLK\|RCC_PLLSAI1_ADC1CLK)) == 0U))
AnnaBridge	156:ff21514d8981	4098
AnnaBridge	156:ff21514d8981	4099	#if defined(RCC_PLLSAI2_SUPPORT)
AnnaBridge	156:ff21514d8981	4100	#define IS_RCC_PLLSAI2CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI2_SAI2CLK) == RCC_PLLSAI2_SAI2CLK) \|\| \
AnnaBridge	156:ff21514d8981	4101	(((__VALUE__) & RCC_PLLSAI2_ADC2CLK) == RCC_PLLSAI2_ADC2CLK)) && \
AnnaBridge	156:ff21514d8981	4102	(((__VALUE__) & ~(RCC_PLLSAI2_SAI2CLK\|RCC_PLLSAI2_ADC2CLK)) == 0U))
AnnaBridge	156:ff21514d8981	4103	#endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge	156:ff21514d8981	4104
AnnaBridge	156:ff21514d8981	4105	#define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) \|\| \
AnnaBridge	156:ff21514d8981	4106	((__RANGE__) == RCC_MSIRANGE_1) \|\| \
AnnaBridge	156:ff21514d8981	4107	((__RANGE__) == RCC_MSIRANGE_2) \|\| \
AnnaBridge	156:ff21514d8981	4108	((__RANGE__) == RCC_MSIRANGE_3) \|\| \
AnnaBridge	156:ff21514d8981	4109	((__RANGE__) == RCC_MSIRANGE_4) \|\| \
AnnaBridge	156:ff21514d8981	4110	((__RANGE__) == RCC_MSIRANGE_5) \|\| \
AnnaBridge	156:ff21514d8981	4111	((__RANGE__) == RCC_MSIRANGE_6) \|\| \
AnnaBridge	156:ff21514d8981	4112	((__RANGE__) == RCC_MSIRANGE_7) \|\| \
AnnaBridge	156:ff21514d8981	4113	((__RANGE__) == RCC_MSIRANGE_8) \|\| \
AnnaBridge	156:ff21514d8981	4114	((__RANGE__) == RCC_MSIRANGE_9) \|\| \
AnnaBridge	156:ff21514d8981	4115	((__RANGE__) == RCC_MSIRANGE_10) \|\| \
AnnaBridge	156:ff21514d8981	4116	((__RANGE__) == RCC_MSIRANGE_11))
AnnaBridge	156:ff21514d8981	4117
AnnaBridge	156:ff21514d8981	4118	#define IS_RCC_MSI_STANDBY_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_4) \|\| \
AnnaBridge	156:ff21514d8981	4119	((__RANGE__) == RCC_MSIRANGE_5) \|\| \
AnnaBridge	156:ff21514d8981	4120	((__RANGE__) == RCC_MSIRANGE_6) \|\| \
AnnaBridge	156:ff21514d8981	4121	((__RANGE__) == RCC_MSIRANGE_7))
AnnaBridge	156:ff21514d8981	4122
AnnaBridge	156:ff21514d8981	4123	#define IS_RCC_CLOCKTYPE(__CLK__) ((1U <= (__CLK__)) && ((__CLK__) <= 15U))
AnnaBridge	156:ff21514d8981	4124
AnnaBridge	156:ff21514d8981	4125	#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) \|\| \
AnnaBridge	156:ff21514d8981	4126	((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) \|\| \
AnnaBridge	156:ff21514d8981	4127	((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) \|\| \
AnnaBridge	156:ff21514d8981	4128	((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
AnnaBridge	156:ff21514d8981	4129
AnnaBridge	156:ff21514d8981	4130	#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) \|\| ((__HCLK__) == RCC_SYSCLK_DIV2) \|\| \
AnnaBridge	156:ff21514d8981	4131	((__HCLK__) == RCC_SYSCLK_DIV4) \|\| ((__HCLK__) == RCC_SYSCLK_DIV8) \|\| \
AnnaBridge	156:ff21514d8981	4132	((__HCLK__) == RCC_SYSCLK_DIV16) \|\| ((__HCLK__) == RCC_SYSCLK_DIV64) \|\| \
AnnaBridge	156:ff21514d8981	4133	((__HCLK__) == RCC_SYSCLK_DIV128) \|\| ((__HCLK__) == RCC_SYSCLK_DIV256) \|\| \
AnnaBridge	156:ff21514d8981	4134	((__HCLK__) == RCC_SYSCLK_DIV512))
AnnaBridge	156:ff21514d8981	4135
AnnaBridge	156:ff21514d8981	4136	#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) \|\| ((__PCLK__) == RCC_HCLK_DIV2) \|\| \
AnnaBridge	156:ff21514d8981	4137	((__PCLK__) == RCC_HCLK_DIV4) \|\| ((__PCLK__) == RCC_HCLK_DIV8) \|\| \
AnnaBridge	156:ff21514d8981	4138	((__PCLK__) == RCC_HCLK_DIV16))
AnnaBridge	156:ff21514d8981	4139
AnnaBridge	156:ff21514d8981	4140	#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) \|\| \
AnnaBridge	156:ff21514d8981	4141	((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) \|\| \
AnnaBridge	156:ff21514d8981	4142	((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) \|\| \
AnnaBridge	156:ff21514d8981	4143	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32))
AnnaBridge	156:ff21514d8981	4144
AnnaBridge	156:ff21514d8981	4145	#define IS_RCC_MCO(__MCOX__) ((__MCOX__) == RCC_MCO1)
AnnaBridge	156:ff21514d8981	4146
AnnaBridge	156:ff21514d8981	4147	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	156:ff21514d8981	4148	#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) \|\| \
AnnaBridge	156:ff21514d8981	4149	((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) \|\| \
AnnaBridge	156:ff21514d8981	4150	((__SOURCE__) == RCC_MCO1SOURCE_MSI) \|\| \
AnnaBridge	156:ff21514d8981	4151	((__SOURCE__) == RCC_MCO1SOURCE_HSI) \|\| \
AnnaBridge	156:ff21514d8981	4152	((__SOURCE__) == RCC_MCO1SOURCE_HSE) \|\| \
AnnaBridge	156:ff21514d8981	4153	((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \|\| \
AnnaBridge	156:ff21514d8981	4154	((__SOURCE__) == RCC_MCO1SOURCE_LSI) \|\| \
AnnaBridge	156:ff21514d8981	4155	((__SOURCE__) == RCC_MCO1SOURCE_LSE) \|\| \
AnnaBridge	156:ff21514d8981	4156	((__SOURCE__) == RCC_MCO1SOURCE_HSI48))
AnnaBridge	156:ff21514d8981	4157	#else
AnnaBridge	156:ff21514d8981	4158	#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) \|\| \
AnnaBridge	156:ff21514d8981	4159	((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) \|\| \
AnnaBridge	156:ff21514d8981	4160	((__SOURCE__) == RCC_MCO1SOURCE_MSI) \|\| \
AnnaBridge	156:ff21514d8981	4161	((__SOURCE__) == RCC_MCO1SOURCE_HSI) \|\| \
AnnaBridge	156:ff21514d8981	4162	((__SOURCE__) == RCC_MCO1SOURCE_HSE) \|\| \
AnnaBridge	156:ff21514d8981	4163	((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \|\| \
AnnaBridge	156:ff21514d8981	4164	((__SOURCE__) == RCC_MCO1SOURCE_LSI) \|\| \
AnnaBridge	156:ff21514d8981	4165	((__SOURCE__) == RCC_MCO1SOURCE_LSE))
AnnaBridge	156:ff21514d8981	4166	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	156:ff21514d8981	4167
AnnaBridge	156:ff21514d8981	4168	#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) \|\| ((__DIV__) == RCC_MCODIV_2) \|\| \
AnnaBridge	156:ff21514d8981	4169	((__DIV__) == RCC_MCODIV_4) \|\| ((__DIV__) == RCC_MCODIV_8) \|\| \
AnnaBridge	156:ff21514d8981	4170	((__DIV__) == RCC_MCODIV_16))
AnnaBridge	156:ff21514d8981	4171
AnnaBridge	156:ff21514d8981	4172	#define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) \|\| \
AnnaBridge	156:ff21514d8981	4173	((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) \|\| \
AnnaBridge	156:ff21514d8981	4174	((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) \|\| \
AnnaBridge	156:ff21514d8981	4175	((__DRIVE__) == RCC_LSEDRIVE_HIGH))
AnnaBridge	156:ff21514d8981	4176
AnnaBridge	156:ff21514d8981	4177	#define IS_RCC_STOP_WAKEUPCLOCK(__SOURCE__) (((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_MSI) \|\| \
AnnaBridge	156:ff21514d8981	4178	((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_HSI))
AnnaBridge	156:ff21514d8981	4179	/**
AnnaBridge	156:ff21514d8981	4180	* @}
AnnaBridge	156:ff21514d8981	4181	*/
AnnaBridge	156:ff21514d8981	4182
AnnaBridge	156:ff21514d8981	4183	/* Include RCC HAL Extended module */
AnnaBridge	156:ff21514d8981	4184	#include "stm32l4xx_hal_rcc_ex.h"
AnnaBridge	156:ff21514d8981	4185
AnnaBridge	156:ff21514d8981	4186	/* Exported functions --------------------------------------------------------*/
AnnaBridge	156:ff21514d8981	4187	/** @addtogroup RCC_Exported_Functions
AnnaBridge	156:ff21514d8981	4188	* @{
AnnaBridge	156:ff21514d8981	4189	*/
AnnaBridge	156:ff21514d8981	4190
AnnaBridge	156:ff21514d8981	4191
AnnaBridge	156:ff21514d8981	4192	/** @addtogroup RCC_Exported_Functions_Group1
AnnaBridge	156:ff21514d8981	4193	* @{
AnnaBridge	156:ff21514d8981	4194	*/
AnnaBridge	156:ff21514d8981	4195
AnnaBridge	156:ff21514d8981	4196	/* Initialization and de-initialization functions ******************************/
AnnaBridge	156:ff21514d8981	4197	void HAL_RCC_DeInit(void);
AnnaBridge	156:ff21514d8981	4198	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
AnnaBridge	156:ff21514d8981	4199	HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
AnnaBridge	156:ff21514d8981	4200
AnnaBridge	156:ff21514d8981	4201	/**
AnnaBridge	156:ff21514d8981	4202	* @}
AnnaBridge	156:ff21514d8981	4203	*/
AnnaBridge	156:ff21514d8981	4204
AnnaBridge	156:ff21514d8981	4205	/** @addtogroup RCC_Exported_Functions_Group2
AnnaBridge	156:ff21514d8981	4206	* @{
AnnaBridge	156:ff21514d8981	4207	*/
AnnaBridge	156:ff21514d8981	4208
AnnaBridge	156:ff21514d8981	4209	/* Peripheral Control functions ************************************************/
AnnaBridge	156:ff21514d8981	4210	void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
AnnaBridge	156:ff21514d8981	4211	void HAL_RCC_EnableCSS(void);
AnnaBridge	156:ff21514d8981	4212	uint32_t HAL_RCC_GetSysClockFreq(void);
AnnaBridge	156:ff21514d8981	4213	uint32_t HAL_RCC_GetHCLKFreq(void);
AnnaBridge	156:ff21514d8981	4214	uint32_t HAL_RCC_GetPCLK1Freq(void);
AnnaBridge	156:ff21514d8981	4215	uint32_t HAL_RCC_GetPCLK2Freq(void);
AnnaBridge	156:ff21514d8981	4216	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
AnnaBridge	156:ff21514d8981	4217	void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef RCC_ClkInitStruct, uint32_t pFLatency);
AnnaBridge	156:ff21514d8981	4218	/* CSS NMI IRQ handler */
AnnaBridge	156:ff21514d8981	4219	void HAL_RCC_NMI_IRQHandler(void);
AnnaBridge	156:ff21514d8981	4220	/* User Callbacks in non blocking mode (IT mode) */
AnnaBridge	156:ff21514d8981	4221	void HAL_RCC_CSSCallback(void);
AnnaBridge	156:ff21514d8981	4222
AnnaBridge	156:ff21514d8981	4223	/**
AnnaBridge	156:ff21514d8981	4224	* @}
AnnaBridge	156:ff21514d8981	4225	*/
AnnaBridge	156:ff21514d8981	4226
AnnaBridge	156:ff21514d8981	4227	/**
AnnaBridge	156:ff21514d8981	4228	* @}
AnnaBridge	156:ff21514d8981	4229	*/
AnnaBridge	156:ff21514d8981	4230
AnnaBridge	156:ff21514d8981	4231	/**
AnnaBridge	156:ff21514d8981	4232	* @}
AnnaBridge	156:ff21514d8981	4233	*/
AnnaBridge	156:ff21514d8981	4234
AnnaBridge	156:ff21514d8981	4235	/**
AnnaBridge	156:ff21514d8981	4236	* @}
AnnaBridge	156:ff21514d8981	4237	*/
AnnaBridge	156:ff21514d8981	4238
AnnaBridge	156:ff21514d8981	4239	#ifdef __cplusplus
AnnaBridge	156:ff21514d8981	4240	}
AnnaBridge	156:ff21514d8981	4241	#endif
AnnaBridge	156:ff21514d8981	4242
AnnaBridge	156:ff21514d8981	4243	#endif /* __STM32L4xx_HAL_RCC_H */
AnnaBridge	156:ff21514d8981	4244
AnnaBridge	156:ff21514d8981	4245	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/