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TARGET_NUCLEO_L031K6/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_tim.h@156:ff21514d8981, 2017-11-08 (annotated)

Committer:
AnnaBridge
Date:
Wed Nov 08 17:18:06 2017 +0000
Revision:
156:ff21514d8981
Child:
167:84c0a372a020
Reverting back to release 154 of the mbed library

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 156:ff21514d8981 1 /**
AnnaBridge 156:ff21514d8981 2 ******************************************************************************
AnnaBridge 156:ff21514d8981 3 * @file stm32l0xx_hal_tim.h
AnnaBridge 156:ff21514d8981 4 * @author MCD Application Team
AnnaBridge 156:ff21514d8981 5 * @version V1.7.0
AnnaBridge 156:ff21514d8981 6 * @date 31-May-2016
AnnaBridge 156:ff21514d8981 7 * @brief Header file of TIM HAL module.
AnnaBridge 156:ff21514d8981 8 ******************************************************************************
AnnaBridge 156:ff21514d8981 9 * @attention
AnnaBridge 156:ff21514d8981 10 *
AnnaBridge 156:ff21514d8981 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge 156:ff21514d8981 12 *
AnnaBridge 156:ff21514d8981 13 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 156:ff21514d8981 14 * are permitted provided that the following conditions are met:
AnnaBridge 156:ff21514d8981 15 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 156:ff21514d8981 16 * this list of conditions and the following disclaimer.
AnnaBridge 156:ff21514d8981 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 156:ff21514d8981 18 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 156:ff21514d8981 19 * and/or other materials provided with the distribution.
AnnaBridge 156:ff21514d8981 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 156:ff21514d8981 21 * may be used to endorse or promote products derived from this software
AnnaBridge 156:ff21514d8981 22 * without specific prior written permission.
AnnaBridge 156:ff21514d8981 23 *
AnnaBridge 156:ff21514d8981 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 156:ff21514d8981 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 156:ff21514d8981 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 156:ff21514d8981 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 156:ff21514d8981 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 156:ff21514d8981 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 156:ff21514d8981 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 156:ff21514d8981 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 156:ff21514d8981 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 156:ff21514d8981 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 156:ff21514d8981 34 *
AnnaBridge 156:ff21514d8981 35 ******************************************************************************
AnnaBridge 156:ff21514d8981 36 */
AnnaBridge 156:ff21514d8981 37
AnnaBridge 156:ff21514d8981 38 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 156:ff21514d8981 39 #ifndef __STM32L0xx_HAL_TIM_H
AnnaBridge 156:ff21514d8981 40 #define __STM32L0xx_HAL_TIM_H
AnnaBridge 156:ff21514d8981 41
AnnaBridge 156:ff21514d8981 42 #ifdef __cplusplus
AnnaBridge 156:ff21514d8981 43 extern "C" {
AnnaBridge 156:ff21514d8981 44 #endif
AnnaBridge 156:ff21514d8981 45
AnnaBridge 156:ff21514d8981 46 /* Includes ------------------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 47 #include "stm32l0xx_hal_def.h"
AnnaBridge 156:ff21514d8981 48
AnnaBridge 156:ff21514d8981 49 /** @addtogroup STM32L0xx_HAL_Driver
AnnaBridge 156:ff21514d8981 50 * @{
AnnaBridge 156:ff21514d8981 51 */
AnnaBridge 156:ff21514d8981 52
AnnaBridge 156:ff21514d8981 53 /** @defgroup TIM TIM (Timer)
AnnaBridge 156:ff21514d8981 54 * @{
AnnaBridge 156:ff21514d8981 55 */
AnnaBridge 156:ff21514d8981 56
AnnaBridge 156:ff21514d8981 57 /* Exported types ------------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 58
AnnaBridge 156:ff21514d8981 59 /** @defgroup TIM_Exported_Types TIM Exported Types
AnnaBridge 156:ff21514d8981 60 * @{
AnnaBridge 156:ff21514d8981 61 */
AnnaBridge 156:ff21514d8981 62
AnnaBridge 156:ff21514d8981 63 /** @defgroup TIM_Base_Configuration TIM base configuration structure
AnnaBridge 156:ff21514d8981 64 * @{
AnnaBridge 156:ff21514d8981 65 */
AnnaBridge 156:ff21514d8981 66 /**
AnnaBridge 156:ff21514d8981 67 * @brief TIM Time base Configuration Structure definition
AnnaBridge 156:ff21514d8981 68 */
AnnaBridge 156:ff21514d8981 69 typedef struct
AnnaBridge 156:ff21514d8981 70 {
AnnaBridge 156:ff21514d8981 71 uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
AnnaBridge 156:ff21514d8981 72 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
AnnaBridge 156:ff21514d8981 73
AnnaBridge 156:ff21514d8981 74 uint32_t CounterMode; /*!< Specifies the counter mode.
AnnaBridge 156:ff21514d8981 75 This parameter can be a value of @ref TIM_Counter_Mode */
AnnaBridge 156:ff21514d8981 76
AnnaBridge 156:ff21514d8981 77 uint32_t Period; /*!< Specifies the period value to be loaded into the active
AnnaBridge 156:ff21514d8981 78 Auto-Reload Register at the next update event.
AnnaBridge 156:ff21514d8981 79 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
AnnaBridge 156:ff21514d8981 80
AnnaBridge 156:ff21514d8981 81 uint32_t ClockDivision; /*!< Specifies the clock division.
AnnaBridge 156:ff21514d8981 82 This parameter can be a value of @ref TIM_ClockDivision */
AnnaBridge 156:ff21514d8981 83 } TIM_Base_InitTypeDef;
AnnaBridge 156:ff21514d8981 84 /**
AnnaBridge 156:ff21514d8981 85 * @}
AnnaBridge 156:ff21514d8981 86 */
AnnaBridge 156:ff21514d8981 87
AnnaBridge 156:ff21514d8981 88 /** @defgroup TIM_Output_Configuration TIM output compare configuration structure
AnnaBridge 156:ff21514d8981 89 * @{
AnnaBridge 156:ff21514d8981 90 */
AnnaBridge 156:ff21514d8981 91
AnnaBridge 156:ff21514d8981 92 /**
AnnaBridge 156:ff21514d8981 93 * @brief TIM Output Compare Configuration Structure definition
AnnaBridge 156:ff21514d8981 94 */
AnnaBridge 156:ff21514d8981 95
AnnaBridge 156:ff21514d8981 96 typedef struct
AnnaBridge 156:ff21514d8981 97 {
AnnaBridge 156:ff21514d8981 98 uint32_t OCMode; /*!< Specifies the TIM mode.
AnnaBridge 156:ff21514d8981 99 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
AnnaBridge 156:ff21514d8981 100
AnnaBridge 156:ff21514d8981 101 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
AnnaBridge 156:ff21514d8981 102 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
AnnaBridge 156:ff21514d8981 103
AnnaBridge 156:ff21514d8981 104 uint32_t OCPolarity; /*!< Specifies the output polarity.
AnnaBridge 156:ff21514d8981 105 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
AnnaBridge 156:ff21514d8981 106
AnnaBridge 156:ff21514d8981 107 uint32_t OCFastMode; /*!< Specifies the Fast mode state.
AnnaBridge 156:ff21514d8981 108 This parameter can be a value of @ref TIM_Output_Fast_State
AnnaBridge 156:ff21514d8981 109 @note This parameter is valid only in PWM1 and PWM2 mode. */
AnnaBridge 156:ff21514d8981 110
AnnaBridge 156:ff21514d8981 111 } TIM_OC_InitTypeDef;
AnnaBridge 156:ff21514d8981 112 /**
AnnaBridge 156:ff21514d8981 113 * @}
AnnaBridge 156:ff21514d8981 114 */
AnnaBridge 156:ff21514d8981 115
AnnaBridge 156:ff21514d8981 116 /** @defgroup TIM_OnePulse_Configuration TIM One Pulse configuration structure
AnnaBridge 156:ff21514d8981 117 * @{
AnnaBridge 156:ff21514d8981 118 */
AnnaBridge 156:ff21514d8981 119 /**
AnnaBridge 156:ff21514d8981 120 * @brief TIM One Pulse Mode Configuration Structure definition
AnnaBridge 156:ff21514d8981 121 */
AnnaBridge 156:ff21514d8981 122 typedef struct
AnnaBridge 156:ff21514d8981 123 {
AnnaBridge 156:ff21514d8981 124 uint32_t OCMode; /*!< Specifies the TIM mode.
AnnaBridge 156:ff21514d8981 125 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
AnnaBridge 156:ff21514d8981 126
AnnaBridge 156:ff21514d8981 127 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
AnnaBridge 156:ff21514d8981 128 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
AnnaBridge 156:ff21514d8981 129
AnnaBridge 156:ff21514d8981 130 uint32_t OCPolarity; /*!< Specifies the output polarity.
AnnaBridge 156:ff21514d8981 131 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
AnnaBridge 156:ff21514d8981 132
AnnaBridge 156:ff21514d8981 133
AnnaBridge 156:ff21514d8981 134 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
AnnaBridge 156:ff21514d8981 135 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
AnnaBridge 156:ff21514d8981 136
AnnaBridge 156:ff21514d8981 137 uint32_t ICSelection; /*!< Specifies the input.
AnnaBridge 156:ff21514d8981 138 This parameter can be a value of @ref TIM_Input_Capture_Selection */
AnnaBridge 156:ff21514d8981 139
AnnaBridge 156:ff21514d8981 140 uint32_t ICFilter; /*!< Specifies the input capture filter.
AnnaBridge 156:ff21514d8981 141 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
AnnaBridge 156:ff21514d8981 142 } TIM_OnePulse_InitTypeDef;
AnnaBridge 156:ff21514d8981 143 /**
AnnaBridge 156:ff21514d8981 144 * @}
AnnaBridge 156:ff21514d8981 145 */
AnnaBridge 156:ff21514d8981 146
AnnaBridge 156:ff21514d8981 147 /** @defgroup TIM_Input_Capture TIM input capture configuration structure
AnnaBridge 156:ff21514d8981 148 * @{
AnnaBridge 156:ff21514d8981 149 */
AnnaBridge 156:ff21514d8981 150 /**
AnnaBridge 156:ff21514d8981 151 * @brief TIM Input Capture Configuration Structure definition
AnnaBridge 156:ff21514d8981 152 */
AnnaBridge 156:ff21514d8981 153
AnnaBridge 156:ff21514d8981 154 typedef struct
AnnaBridge 156:ff21514d8981 155 {
AnnaBridge 156:ff21514d8981 156 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
AnnaBridge 156:ff21514d8981 157 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
AnnaBridge 156:ff21514d8981 158
AnnaBridge 156:ff21514d8981 159 uint32_t ICSelection; /*!< Specifies the input.
AnnaBridge 156:ff21514d8981 160 This parameter can be a value of @ref TIM_Input_Capture_Selection */
AnnaBridge 156:ff21514d8981 161
AnnaBridge 156:ff21514d8981 162 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
AnnaBridge 156:ff21514d8981 163 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
AnnaBridge 156:ff21514d8981 164
AnnaBridge 156:ff21514d8981 165 uint32_t ICFilter; /*!< Specifies the input capture filter.
AnnaBridge 156:ff21514d8981 166 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
AnnaBridge 156:ff21514d8981 167 } TIM_IC_InitTypeDef;
AnnaBridge 156:ff21514d8981 168 /**
AnnaBridge 156:ff21514d8981 169 * @}
AnnaBridge 156:ff21514d8981 170 */
AnnaBridge 156:ff21514d8981 171
AnnaBridge 156:ff21514d8981 172 /** @defgroup TIM_Encoder TIM encoder configuration structure
AnnaBridge 156:ff21514d8981 173 * @{
AnnaBridge 156:ff21514d8981 174 */
AnnaBridge 156:ff21514d8981 175 /**
AnnaBridge 156:ff21514d8981 176 * @brief TIM Encoder Configuration Structure definition
AnnaBridge 156:ff21514d8981 177 */
AnnaBridge 156:ff21514d8981 178
AnnaBridge 156:ff21514d8981 179 typedef struct
AnnaBridge 156:ff21514d8981 180 {
AnnaBridge 156:ff21514d8981 181 uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
AnnaBridge 156:ff21514d8981 182 This parameter can be a value of @ref TIM_Encoder_Mode */
AnnaBridge 156:ff21514d8981 183
AnnaBridge 156:ff21514d8981 184 uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
AnnaBridge 156:ff21514d8981 185 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
AnnaBridge 156:ff21514d8981 186
AnnaBridge 156:ff21514d8981 187 uint32_t IC1Selection; /*!< Specifies the input.
AnnaBridge 156:ff21514d8981 188 This parameter can be a value of @ref TIM_Input_Capture_Selection */
AnnaBridge 156:ff21514d8981 189
AnnaBridge 156:ff21514d8981 190 uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
AnnaBridge 156:ff21514d8981 191 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
AnnaBridge 156:ff21514d8981 192
AnnaBridge 156:ff21514d8981 193 uint32_t IC1Filter; /*!< Specifies the input capture filter.
AnnaBridge 156:ff21514d8981 194 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
AnnaBridge 156:ff21514d8981 195
AnnaBridge 156:ff21514d8981 196 uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
AnnaBridge 156:ff21514d8981 197 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
AnnaBridge 156:ff21514d8981 198
AnnaBridge 156:ff21514d8981 199 uint32_t IC2Selection; /*!< Specifies the input.
AnnaBridge 156:ff21514d8981 200 This parameter can be a value of @ref TIM_Input_Capture_Selection */
AnnaBridge 156:ff21514d8981 201
AnnaBridge 156:ff21514d8981 202 uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
AnnaBridge 156:ff21514d8981 203 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
AnnaBridge 156:ff21514d8981 204
AnnaBridge 156:ff21514d8981 205 uint32_t IC2Filter; /*!< Specifies the input capture filter.
AnnaBridge 156:ff21514d8981 206 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
AnnaBridge 156:ff21514d8981 207 } TIM_Encoder_InitTypeDef;
AnnaBridge 156:ff21514d8981 208 /**
AnnaBridge 156:ff21514d8981 209 * @}
AnnaBridge 156:ff21514d8981 210 */
AnnaBridge 156:ff21514d8981 211
AnnaBridge 156:ff21514d8981 212 /** @defgroup TIM_Clock_Configuration TIM clock configuration structure
AnnaBridge 156:ff21514d8981 213 * @{
AnnaBridge 156:ff21514d8981 214 */
AnnaBridge 156:ff21514d8981 215 /**
AnnaBridge 156:ff21514d8981 216 * @brief Clock Configuration Handle Structure definition
AnnaBridge 156:ff21514d8981 217 */
AnnaBridge 156:ff21514d8981 218 typedef struct
AnnaBridge 156:ff21514d8981 219 {
AnnaBridge 156:ff21514d8981 220 uint32_t ClockSource; /*!< TIM clock sources.
AnnaBridge 156:ff21514d8981 221 This parameter can be a value of @ref TIM_Clock_Source */
AnnaBridge 156:ff21514d8981 222 uint32_t ClockPolarity; /*!< TIM clock polarity.
AnnaBridge 156:ff21514d8981 223 This parameter can be a value of @ref TIM_Clock_Polarity */
AnnaBridge 156:ff21514d8981 224 uint32_t ClockPrescaler; /*!< TIM clock prescaler.
AnnaBridge 156:ff21514d8981 225 This parameter can be a value of @ref TIM_Clock_Prescaler */
AnnaBridge 156:ff21514d8981 226 uint32_t ClockFilter; /*!< TIM clock filter.
AnnaBridge 156:ff21514d8981 227 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
AnnaBridge 156:ff21514d8981 228 }TIM_ClockConfigTypeDef;
AnnaBridge 156:ff21514d8981 229 /**
AnnaBridge 156:ff21514d8981 230 * @}
AnnaBridge 156:ff21514d8981 231 */
AnnaBridge 156:ff21514d8981 232
AnnaBridge 156:ff21514d8981 233 /** @defgroup TIM_Clear_Input_Configuration TIM clear input configuration structure
AnnaBridge 156:ff21514d8981 234 * @{
AnnaBridge 156:ff21514d8981 235 */
AnnaBridge 156:ff21514d8981 236 /**
AnnaBridge 156:ff21514d8981 237 * @brief Clear Input Configuration Handle Structure definition
AnnaBridge 156:ff21514d8981 238 */
AnnaBridge 156:ff21514d8981 239 typedef struct
AnnaBridge 156:ff21514d8981 240 {
AnnaBridge 156:ff21514d8981 241 uint32_t ClearInputState; /*!< TIM clear Input state.
AnnaBridge 156:ff21514d8981 242 This parameter can be ENABLE or DISABLE */
AnnaBridge 156:ff21514d8981 243 uint32_t ClearInputSource; /*!< TIM clear Input sources.
AnnaBridge 156:ff21514d8981 244 This parameter can be a value of @ref TIM_ClearInput_Source */
AnnaBridge 156:ff21514d8981 245 uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity.
AnnaBridge 156:ff21514d8981 246 This parameter can be a value of @ref TIM_ClearInput_Polarity */
AnnaBridge 156:ff21514d8981 247 uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler.
AnnaBridge 156:ff21514d8981 248 This parameter can be a value of @ref TIM_ClearInput_Prescaler */
AnnaBridge 156:ff21514d8981 249 uint32_t ClearInputFilter; /*!< TIM Clear Input filter.
AnnaBridge 156:ff21514d8981 250 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
AnnaBridge 156:ff21514d8981 251 }TIM_ClearInputConfigTypeDef;
AnnaBridge 156:ff21514d8981 252 /**
AnnaBridge 156:ff21514d8981 253 * @}
AnnaBridge 156:ff21514d8981 254 */
AnnaBridge 156:ff21514d8981 255
AnnaBridge 156:ff21514d8981 256 /** @defgroup TIM_Slave_Configuratio TIM slave configuration structure
AnnaBridge 156:ff21514d8981 257 * @{
AnnaBridge 156:ff21514d8981 258 */
AnnaBridge 156:ff21514d8981 259 /**
AnnaBridge 156:ff21514d8981 260 * @brief TIM Slave configuration Structure definition
AnnaBridge 156:ff21514d8981 261 */
AnnaBridge 156:ff21514d8981 262 typedef struct {
AnnaBridge 156:ff21514d8981 263 uint32_t SlaveMode; /*!< Slave mode selection.
AnnaBridge 156:ff21514d8981 264 This parameter can be a value of @ref TIM_Slave_Mode */
AnnaBridge 156:ff21514d8981 265 uint32_t InputTrigger; /*!< Input Trigger source.
AnnaBridge 156:ff21514d8981 266 This parameter can be a value of @ref TIM_Trigger_Selection */
AnnaBridge 156:ff21514d8981 267 uint32_t TriggerPolarity; /*!< Input Trigger polarity.
AnnaBridge 156:ff21514d8981 268 This parameter can be a value of @ref TIM_Trigger_Polarity */
AnnaBridge 156:ff21514d8981 269 uint32_t TriggerPrescaler; /*!< Input trigger prescaler.
AnnaBridge 156:ff21514d8981 270 This parameter can be a value of @ref TIM_Trigger_Prescaler */
AnnaBridge 156:ff21514d8981 271 uint32_t TriggerFilter; /*!< Input trigger filter.
AnnaBridge 156:ff21514d8981 272 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
AnnaBridge 156:ff21514d8981 273
AnnaBridge 156:ff21514d8981 274 }TIM_SlaveConfigTypeDef;
AnnaBridge 156:ff21514d8981 275 /**
AnnaBridge 156:ff21514d8981 276 * @}
AnnaBridge 156:ff21514d8981 277 */
AnnaBridge 156:ff21514d8981 278
AnnaBridge 156:ff21514d8981 279 /** @defgroup TIM_State_Definition TIM state definition
AnnaBridge 156:ff21514d8981 280 * @{
AnnaBridge 156:ff21514d8981 281 */
AnnaBridge 156:ff21514d8981 282 /**
AnnaBridge 156:ff21514d8981 283 * @brief HAL State structures definition
AnnaBridge 156:ff21514d8981 284 */
AnnaBridge 156:ff21514d8981 285 typedef enum
AnnaBridge 156:ff21514d8981 286 {
AnnaBridge 156:ff21514d8981 287 HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */
AnnaBridge 156:ff21514d8981 288 HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
AnnaBridge 156:ff21514d8981 289 HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
AnnaBridge 156:ff21514d8981 290 HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
AnnaBridge 156:ff21514d8981 291 HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
AnnaBridge 156:ff21514d8981 292 }HAL_TIM_StateTypeDef;
AnnaBridge 156:ff21514d8981 293 /**
AnnaBridge 156:ff21514d8981 294 * @}
AnnaBridge 156:ff21514d8981 295 */
AnnaBridge 156:ff21514d8981 296
AnnaBridge 156:ff21514d8981 297 /** @defgroup TIM_Active_Channel TIM active channel definition
AnnaBridge 156:ff21514d8981 298 * @{
AnnaBridge 156:ff21514d8981 299 */
AnnaBridge 156:ff21514d8981 300 /**
AnnaBridge 156:ff21514d8981 301 * @brief HAL Active channel structures definition
AnnaBridge 156:ff21514d8981 302 */
AnnaBridge 156:ff21514d8981 303 typedef enum
AnnaBridge 156:ff21514d8981 304 {
AnnaBridge 156:ff21514d8981 305 HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */
AnnaBridge 156:ff21514d8981 306 HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */
AnnaBridge 156:ff21514d8981 307 HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */
AnnaBridge 156:ff21514d8981 308 HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */
AnnaBridge 156:ff21514d8981 309 HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */
AnnaBridge 156:ff21514d8981 310 }HAL_TIM_ActiveChannel;
AnnaBridge 156:ff21514d8981 311 /**
AnnaBridge 156:ff21514d8981 312 * @}
AnnaBridge 156:ff21514d8981 313 */
AnnaBridge 156:ff21514d8981 314
AnnaBridge 156:ff21514d8981 315 /** @defgroup TIM_Handle TIM handler
AnnaBridge 156:ff21514d8981 316 * @{
AnnaBridge 156:ff21514d8981 317 */
AnnaBridge 156:ff21514d8981 318 /**
AnnaBridge 156:ff21514d8981 319 * @brief TIM Time Base Handle Structure definition
AnnaBridge 156:ff21514d8981 320 */
AnnaBridge 156:ff21514d8981 321 typedef struct
AnnaBridge 156:ff21514d8981 322 {
AnnaBridge 156:ff21514d8981 323 TIM_TypeDef *Instance; /*!< Register base address */
AnnaBridge 156:ff21514d8981 324 TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
AnnaBridge 156:ff21514d8981 325 HAL_TIM_ActiveChannel Channel; /*!< Active channel */
AnnaBridge 156:ff21514d8981 326 DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
AnnaBridge 156:ff21514d8981 327 This array is accessed by a @ref DMA_Handle_index */
AnnaBridge 156:ff21514d8981 328 HAL_LockTypeDef Lock; /*!< Locking object */
AnnaBridge 156:ff21514d8981 329 __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
AnnaBridge 156:ff21514d8981 330 }TIM_HandleTypeDef;
AnnaBridge 156:ff21514d8981 331 /**
AnnaBridge 156:ff21514d8981 332 * @}
AnnaBridge 156:ff21514d8981 333 */
AnnaBridge 156:ff21514d8981 334
AnnaBridge 156:ff21514d8981 335 /**
AnnaBridge 156:ff21514d8981 336 * @}
AnnaBridge 156:ff21514d8981 337 */
AnnaBridge 156:ff21514d8981 338 /* Exported constants --------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 339 /** @defgroup TIM_Exported_Constants TIM Exported Constants
AnnaBridge 156:ff21514d8981 340 * @{
AnnaBridge 156:ff21514d8981 341 */
AnnaBridge 156:ff21514d8981 342
AnnaBridge 156:ff21514d8981 343
AnnaBridge 156:ff21514d8981 344 #define IS_TIM_PERIOD(__PERIOD__) ((__PERIOD__) <= 0xFFFFU)
AnnaBridge 156:ff21514d8981 345
AnnaBridge 156:ff21514d8981 346 #define IS_TIM_PRESCALER(__PRESCALER__) ((__PRESCALER__) <= 0xFFFFU)
AnnaBridge 156:ff21514d8981 347
AnnaBridge 156:ff21514d8981 348
AnnaBridge 156:ff21514d8981 349 /** @defgroup TIM_Input_Channel_Polarity Input channel polarity
AnnaBridge 156:ff21514d8981 350 * @{
AnnaBridge 156:ff21514d8981 351 */
AnnaBridge 156:ff21514d8981 352 #define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000U) /*!< Polarity for TIx source */
AnnaBridge 156:ff21514d8981 353 #define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */
AnnaBridge 156:ff21514d8981 354 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */
AnnaBridge 156:ff21514d8981 355 /**
AnnaBridge 156:ff21514d8981 356 * @}
AnnaBridge 156:ff21514d8981 357 */
AnnaBridge 156:ff21514d8981 358
AnnaBridge 156:ff21514d8981 359 /** @defgroup TIM_ETR_Polarity ETR polarity
AnnaBridge 156:ff21514d8981 360 * @{
AnnaBridge 156:ff21514d8981 361 */
AnnaBridge 156:ff21514d8981 362 #define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */
AnnaBridge 156:ff21514d8981 363 #define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000U) /*!< Polarity for ETR source */
AnnaBridge 156:ff21514d8981 364 /**
AnnaBridge 156:ff21514d8981 365 * @}
AnnaBridge 156:ff21514d8981 366 */
AnnaBridge 156:ff21514d8981 367
AnnaBridge 156:ff21514d8981 368 /** @defgroup TIM_ETR_Prescaler ETR prescaler
AnnaBridge 156:ff21514d8981 369 * @{
AnnaBridge 156:ff21514d8981 370 */
AnnaBridge 156:ff21514d8981 371 #define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000U) /*!< No prescaler is used */
AnnaBridge 156:ff21514d8981 372 #define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */
AnnaBridge 156:ff21514d8981 373 #define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */
AnnaBridge 156:ff21514d8981 374 #define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */
AnnaBridge 156:ff21514d8981 375 /**
AnnaBridge 156:ff21514d8981 376 * @}
AnnaBridge 156:ff21514d8981 377 */
AnnaBridge 156:ff21514d8981 378
AnnaBridge 156:ff21514d8981 379 /** @defgroup TIM_Counter_Mode Counter mode
AnnaBridge 156:ff21514d8981 380 * @{
AnnaBridge 156:ff21514d8981 381 */
AnnaBridge 156:ff21514d8981 382 #define TIM_COUNTERMODE_UP ((uint32_t)0x0000U)
AnnaBridge 156:ff21514d8981 383 #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
AnnaBridge 156:ff21514d8981 384 #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
AnnaBridge 156:ff21514d8981 385 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
AnnaBridge 156:ff21514d8981 386 #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
AnnaBridge 156:ff21514d8981 387 /**
AnnaBridge 156:ff21514d8981 388 * @}
AnnaBridge 156:ff21514d8981 389 */
AnnaBridge 156:ff21514d8981 390 #define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \
AnnaBridge 156:ff21514d8981 391 ((__MODE__) == TIM_COUNTERMODE_DOWN) || \
AnnaBridge 156:ff21514d8981 392 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \
AnnaBridge 156:ff21514d8981 393 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \
AnnaBridge 156:ff21514d8981 394 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
AnnaBridge 156:ff21514d8981 395
AnnaBridge 156:ff21514d8981 396
AnnaBridge 156:ff21514d8981 397
AnnaBridge 156:ff21514d8981 398
AnnaBridge 156:ff21514d8981 399 /** @defgroup TIM_ClockDivision Clock division
AnnaBridge 156:ff21514d8981 400 * @{
AnnaBridge 156:ff21514d8981 401 */
AnnaBridge 156:ff21514d8981 402 #define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000U)
AnnaBridge 156:ff21514d8981 403 #define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
AnnaBridge 156:ff21514d8981 404 #define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
AnnaBridge 156:ff21514d8981 405 /**
AnnaBridge 156:ff21514d8981 406 * @}
AnnaBridge 156:ff21514d8981 407 */
AnnaBridge 156:ff21514d8981 408 #define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
AnnaBridge 156:ff21514d8981 409 ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
AnnaBridge 156:ff21514d8981 410 ((__DIV__) == TIM_CLOCKDIVISION_DIV4))
AnnaBridge 156:ff21514d8981 411
AnnaBridge 156:ff21514d8981 412
AnnaBridge 156:ff21514d8981 413 /** @defgroup TIM_Output_Compare_and_PWM_modes Output compare and PWM modes
AnnaBridge 156:ff21514d8981 414 * @{
AnnaBridge 156:ff21514d8981 415 */
AnnaBridge 156:ff21514d8981 416 #define TIM_OCMODE_TIMING ((uint32_t)0x0000U)
AnnaBridge 156:ff21514d8981 417 #define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)
AnnaBridge 156:ff21514d8981 418 #define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)
AnnaBridge 156:ff21514d8981 419 #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1)
AnnaBridge 156:ff21514d8981 420 #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
AnnaBridge 156:ff21514d8981 421 #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)
AnnaBridge 156:ff21514d8981 422 #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
AnnaBridge 156:ff21514d8981 423 #define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)
AnnaBridge 156:ff21514d8981 424 /**
AnnaBridge 156:ff21514d8981 425 * @}
AnnaBridge 156:ff21514d8981 426 */
AnnaBridge 156:ff21514d8981 427
AnnaBridge 156:ff21514d8981 428 #define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \
AnnaBridge 156:ff21514d8981 429 ((__MODE__) == TIM_OCMODE_PWM2))
AnnaBridge 156:ff21514d8981 430
AnnaBridge 156:ff21514d8981 431 #define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \
AnnaBridge 156:ff21514d8981 432 ((__MODE__) == TIM_OCMODE_ACTIVE) || \
AnnaBridge 156:ff21514d8981 433 ((__MODE__) == TIM_OCMODE_INACTIVE) || \
AnnaBridge 156:ff21514d8981 434 ((__MODE__) == TIM_OCMODE_TOGGLE) || \
AnnaBridge 156:ff21514d8981 435 ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \
AnnaBridge 156:ff21514d8981 436 ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE))
AnnaBridge 156:ff21514d8981 437
AnnaBridge 156:ff21514d8981 438
AnnaBridge 156:ff21514d8981 439 /** @defgroup TIM_Output_Compare_State Output compare state
AnnaBridge 156:ff21514d8981 440 * @{
AnnaBridge 156:ff21514d8981 441 */
AnnaBridge 156:ff21514d8981 442 #define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000U)
AnnaBridge 156:ff21514d8981 443 #define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
AnnaBridge 156:ff21514d8981 444 /**
AnnaBridge 156:ff21514d8981 445 * @}
AnnaBridge 156:ff21514d8981 446 */
AnnaBridge 156:ff21514d8981 447
AnnaBridge 156:ff21514d8981 448 /** @defgroup TIM_Output_Fast_State Output fast state
AnnaBridge 156:ff21514d8981 449 * @{
AnnaBridge 156:ff21514d8981 450 */
AnnaBridge 156:ff21514d8981 451 #define TIM_OCFAST_DISABLE ((uint32_t)0x0000U)
AnnaBridge 156:ff21514d8981 452 #define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
AnnaBridge 156:ff21514d8981 453 /**
AnnaBridge 156:ff21514d8981 454 * @}
AnnaBridge 156:ff21514d8981 455 */
AnnaBridge 156:ff21514d8981 456 #define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \
AnnaBridge 156:ff21514d8981 457 ((__STATE__) == TIM_OCFAST_ENABLE))
AnnaBridge 156:ff21514d8981 458
AnnaBridge 156:ff21514d8981 459 /** @defgroup TIM_Output_Compare_N_State Output compare N state
AnnaBridge 156:ff21514d8981 460 * @{
AnnaBridge 156:ff21514d8981 461 */
AnnaBridge 156:ff21514d8981 462 #define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000U)
AnnaBridge 156:ff21514d8981 463 #define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
AnnaBridge 156:ff21514d8981 464 /**
AnnaBridge 156:ff21514d8981 465 * @}
AnnaBridge 156:ff21514d8981 466 */
AnnaBridge 156:ff21514d8981 467
AnnaBridge 156:ff21514d8981 468 /** @defgroup TIM_Output_Compare_Polarity Output compare polarity
AnnaBridge 156:ff21514d8981 469 * @{
AnnaBridge 156:ff21514d8981 470 */
AnnaBridge 156:ff21514d8981 471 #define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000U)
AnnaBridge 156:ff21514d8981 472 #define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
AnnaBridge 156:ff21514d8981 473 /**
AnnaBridge 156:ff21514d8981 474 * @}
AnnaBridge 156:ff21514d8981 475 */
AnnaBridge 156:ff21514d8981 476 #define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
AnnaBridge 156:ff21514d8981 477 ((__POLARITY__) == TIM_OCPOLARITY_LOW))
AnnaBridge 156:ff21514d8981 478
AnnaBridge 156:ff21514d8981 479 /** @defgroup TIM_Channel TIM channels
AnnaBridge 156:ff21514d8981 480 * @{
AnnaBridge 156:ff21514d8981 481 */
AnnaBridge 156:ff21514d8981 482 #define TIM_CHANNEL_1 ((uint32_t)0x0000U)
AnnaBridge 156:ff21514d8981 483 #define TIM_CHANNEL_2 ((uint32_t)0x0004U)
AnnaBridge 156:ff21514d8981 484 #define TIM_CHANNEL_3 ((uint32_t)0x0008U)
AnnaBridge 156:ff21514d8981 485 #define TIM_CHANNEL_4 ((uint32_t)0x000CU)
AnnaBridge 156:ff21514d8981 486 #define TIM_CHANNEL_ALL ((uint32_t)0x0018U)
AnnaBridge 156:ff21514d8981 487 /**
AnnaBridge 156:ff21514d8981 488 * @}
AnnaBridge 156:ff21514d8981 489 */
AnnaBridge 156:ff21514d8981 490
AnnaBridge 156:ff21514d8981 491 #define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
AnnaBridge 156:ff21514d8981 492 ((__CHANNEL__) == TIM_CHANNEL_2) || \
AnnaBridge 156:ff21514d8981 493 ((__CHANNEL__) == TIM_CHANNEL_3) || \
AnnaBridge 156:ff21514d8981 494 ((__CHANNEL__) == TIM_CHANNEL_4) || \
AnnaBridge 156:ff21514d8981 495 ((__CHANNEL__) == TIM_CHANNEL_ALL))
AnnaBridge 156:ff21514d8981 496
AnnaBridge 156:ff21514d8981 497 #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
AnnaBridge 156:ff21514d8981 498 ((__CHANNEL__) == TIM_CHANNEL_2))
AnnaBridge 156:ff21514d8981 499
AnnaBridge 156:ff21514d8981 500
AnnaBridge 156:ff21514d8981 501 /** @defgroup TIM_Input_Capture_Polarity Input capture polarity
AnnaBridge 156:ff21514d8981 502 * @{
AnnaBridge 156:ff21514d8981 503 */
AnnaBridge 156:ff21514d8981 504 #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
AnnaBridge 156:ff21514d8981 505 #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
AnnaBridge 156:ff21514d8981 506 #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
AnnaBridge 156:ff21514d8981 507 /**
AnnaBridge 156:ff21514d8981 508 * @}
AnnaBridge 156:ff21514d8981 509 */
AnnaBridge 156:ff21514d8981 510 #define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \
AnnaBridge 156:ff21514d8981 511 ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \
AnnaBridge 156:ff21514d8981 512 ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
AnnaBridge 156:ff21514d8981 513
AnnaBridge 156:ff21514d8981 514
AnnaBridge 156:ff21514d8981 515 /** @defgroup TIM_Input_Capture_Selection Input capture selection
AnnaBridge 156:ff21514d8981 516 * @{
AnnaBridge 156:ff21514d8981 517 */
AnnaBridge 156:ff21514d8981 518 #define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
AnnaBridge 156:ff21514d8981 519 connected to IC1, IC2, IC3 or IC4, respectively */
AnnaBridge 156:ff21514d8981 520 #define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
AnnaBridge 156:ff21514d8981 521 connected to IC2, IC1, IC4 or IC3, respectively */
AnnaBridge 156:ff21514d8981 522 #define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
AnnaBridge 156:ff21514d8981 523
AnnaBridge 156:ff21514d8981 524 #define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
AnnaBridge 156:ff21514d8981 525 ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
AnnaBridge 156:ff21514d8981 526 ((__SELECTION__) == TIM_ICSELECTION_TRC))
AnnaBridge 156:ff21514d8981 527 /**
AnnaBridge 156:ff21514d8981 528 * @}
AnnaBridge 156:ff21514d8981 529 */
AnnaBridge 156:ff21514d8981 530
AnnaBridge 156:ff21514d8981 531 /** @defgroup TIM_Input_Capture_Prescaler Input capture prescaler
AnnaBridge 156:ff21514d8981 532 * @{
AnnaBridge 156:ff21514d8981 533 */
AnnaBridge 156:ff21514d8981 534 #define TIM_ICPSC_DIV1 ((uint32_t)0x0000U) /*!< Capture performed each time an edge is detected on the capture input */
AnnaBridge 156:ff21514d8981 535 #define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */
AnnaBridge 156:ff21514d8981 536 #define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */
AnnaBridge 156:ff21514d8981 537 #define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */
AnnaBridge 156:ff21514d8981 538 /**
AnnaBridge 156:ff21514d8981 539 * @}
AnnaBridge 156:ff21514d8981 540 */
AnnaBridge 156:ff21514d8981 541 #define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \
AnnaBridge 156:ff21514d8981 542 ((__PRESCALER__) == TIM_ICPSC_DIV2) || \
AnnaBridge 156:ff21514d8981 543 ((__PRESCALER__) == TIM_ICPSC_DIV4) || \
AnnaBridge 156:ff21514d8981 544 ((__PRESCALER__) == TIM_ICPSC_DIV8))
AnnaBridge 156:ff21514d8981 545
AnnaBridge 156:ff21514d8981 546 /** @defgroup TIM_One_Pulse_Mode One pulse mode
AnnaBridge 156:ff21514d8981 547 * @{
AnnaBridge 156:ff21514d8981 548 */
AnnaBridge 156:ff21514d8981 549 #define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
AnnaBridge 156:ff21514d8981 550 #define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000U)
AnnaBridge 156:ff21514d8981 551 /**
AnnaBridge 156:ff21514d8981 552 * @}
AnnaBridge 156:ff21514d8981 553 */
AnnaBridge 156:ff21514d8981 554 #define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \
AnnaBridge 156:ff21514d8981 555 ((__MODE__) == TIM_OPMODE_REPETITIVE))
AnnaBridge 156:ff21514d8981 556
AnnaBridge 156:ff21514d8981 557 /** @defgroup TIM_Encoder_Mode Encoder_Mode
AnnaBridge 156:ff21514d8981 558 * @{
AnnaBridge 156:ff21514d8981 559 */
AnnaBridge 156:ff21514d8981 560 #define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
AnnaBridge 156:ff21514d8981 561 #define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
AnnaBridge 156:ff21514d8981 562 #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
AnnaBridge 156:ff21514d8981 563 /**
AnnaBridge 156:ff21514d8981 564 * @}
AnnaBridge 156:ff21514d8981 565 */
AnnaBridge 156:ff21514d8981 566 #define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \
AnnaBridge 156:ff21514d8981 567 ((__MODE__) == TIM_ENCODERMODE_TI2) || \
AnnaBridge 156:ff21514d8981 568 ((__MODE__) == TIM_ENCODERMODE_TI12))
AnnaBridge 156:ff21514d8981 569
AnnaBridge 156:ff21514d8981 570 /** @defgroup TIM_Interrupt_definition Interrupt definition
AnnaBridge 156:ff21514d8981 571 * @{
AnnaBridge 156:ff21514d8981 572 */
AnnaBridge 156:ff21514d8981 573 #define TIM_IT_UPDATE (TIM_DIER_UIE)
AnnaBridge 156:ff21514d8981 574 #define TIM_IT_CC1 (TIM_DIER_CC1IE)
AnnaBridge 156:ff21514d8981 575 #define TIM_IT_CC2 (TIM_DIER_CC2IE)
AnnaBridge 156:ff21514d8981 576 #define TIM_IT_CC3 (TIM_DIER_CC3IE)
AnnaBridge 156:ff21514d8981 577 #define TIM_IT_CC4 (TIM_DIER_CC4IE)
AnnaBridge 156:ff21514d8981 578 #define TIM_IT_TRIGGER (TIM_DIER_TIE)
AnnaBridge 156:ff21514d8981 579 /**
AnnaBridge 156:ff21514d8981 580 * @}
AnnaBridge 156:ff21514d8981 581 */
AnnaBridge 156:ff21514d8981 582
AnnaBridge 156:ff21514d8981 583 /** @defgroup TIM_DMA_sources DMA sources
AnnaBridge 156:ff21514d8981 584 * @{
AnnaBridge 156:ff21514d8981 585 */
AnnaBridge 156:ff21514d8981 586 #define TIM_DMA_UPDATE (TIM_DIER_UDE)
AnnaBridge 156:ff21514d8981 587 #define TIM_DMA_CC1 (TIM_DIER_CC1DE)
AnnaBridge 156:ff21514d8981 588 #define TIM_DMA_CC2 (TIM_DIER_CC2DE)
AnnaBridge 156:ff21514d8981 589 #define TIM_DMA_CC3 (TIM_DIER_CC3DE)
AnnaBridge 156:ff21514d8981 590 #define TIM_DMA_CC4 (TIM_DIER_CC4DE)
AnnaBridge 156:ff21514d8981 591 #define TIM_DMA_TRIGGER (TIM_DIER_TDE)
AnnaBridge 156:ff21514d8981 592 /**
AnnaBridge 156:ff21514d8981 593 * @}
AnnaBridge 156:ff21514d8981 594 */
AnnaBridge 156:ff21514d8981 595 #define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFA0FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
AnnaBridge 156:ff21514d8981 596
AnnaBridge 156:ff21514d8981 597
AnnaBridge 156:ff21514d8981 598
AnnaBridge 156:ff21514d8981 599 /** @defgroup TIM_Event_Source Event sources
AnnaBridge 156:ff21514d8981 600 * @{
AnnaBridge 156:ff21514d8981 601 */
AnnaBridge 156:ff21514d8981 602 #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
AnnaBridge 156:ff21514d8981 603 #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
AnnaBridge 156:ff21514d8981 604 #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
AnnaBridge 156:ff21514d8981 605 #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
AnnaBridge 156:ff21514d8981 606 #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
AnnaBridge 156:ff21514d8981 607 #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
AnnaBridge 156:ff21514d8981 608 /**
AnnaBridge 156:ff21514d8981 609 * @}
AnnaBridge 156:ff21514d8981 610 */
AnnaBridge 156:ff21514d8981 611 #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFFA0U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
AnnaBridge 156:ff21514d8981 612
AnnaBridge 156:ff21514d8981 613
AnnaBridge 156:ff21514d8981 614 /** @defgroup TIM_Flag_definition Flag definition
AnnaBridge 156:ff21514d8981 615 * @{
AnnaBridge 156:ff21514d8981 616 */
AnnaBridge 156:ff21514d8981 617 #define TIM_FLAG_UPDATE (TIM_SR_UIF)
AnnaBridge 156:ff21514d8981 618 #define TIM_FLAG_CC1 (TIM_SR_CC1IF)
AnnaBridge 156:ff21514d8981 619 #define TIM_FLAG_CC2 (TIM_SR_CC2IF)
AnnaBridge 156:ff21514d8981 620 #define TIM_FLAG_CC3 (TIM_SR_CC3IF)
AnnaBridge 156:ff21514d8981 621 #define TIM_FLAG_CC4 (TIM_SR_CC4IF)
AnnaBridge 156:ff21514d8981 622 #define TIM_FLAG_TRIGGER (TIM_SR_TIF)
AnnaBridge 156:ff21514d8981 623 #define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
AnnaBridge 156:ff21514d8981 624 #define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
AnnaBridge 156:ff21514d8981 625 #define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
AnnaBridge 156:ff21514d8981 626 #define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
AnnaBridge 156:ff21514d8981 627 /**
AnnaBridge 156:ff21514d8981 628 * @}
AnnaBridge 156:ff21514d8981 629 */
AnnaBridge 156:ff21514d8981 630
AnnaBridge 156:ff21514d8981 631 /** @defgroup TIM_Clock_Source Clock source
AnnaBridge 156:ff21514d8981 632 * @{
AnnaBridge 156:ff21514d8981 633 */
AnnaBridge 156:ff21514d8981 634 #define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
AnnaBridge 156:ff21514d8981 635 #define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
AnnaBridge 156:ff21514d8981 636 #define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000U)
AnnaBridge 156:ff21514d8981 637 #define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
AnnaBridge 156:ff21514d8981 638 #define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
AnnaBridge 156:ff21514d8981 639 #define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
AnnaBridge 156:ff21514d8981 640 #define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
AnnaBridge 156:ff21514d8981 641 #define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
AnnaBridge 156:ff21514d8981 642 #define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
AnnaBridge 156:ff21514d8981 643 #define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
AnnaBridge 156:ff21514d8981 644 /**
AnnaBridge 156:ff21514d8981 645 * @}
AnnaBridge 156:ff21514d8981 646 */
AnnaBridge 156:ff21514d8981 647
AnnaBridge 156:ff21514d8981 648 #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
AnnaBridge 156:ff21514d8981 649 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
AnnaBridge 156:ff21514d8981 650 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
AnnaBridge 156:ff21514d8981 651 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
AnnaBridge 156:ff21514d8981 652 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
AnnaBridge 156:ff21514d8981 653 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
AnnaBridge 156:ff21514d8981 654 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
AnnaBridge 156:ff21514d8981 655 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
AnnaBridge 156:ff21514d8981 656 ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
AnnaBridge 156:ff21514d8981 657 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))
AnnaBridge 156:ff21514d8981 658
AnnaBridge 156:ff21514d8981 659
AnnaBridge 156:ff21514d8981 660 /** @defgroup TIM_Clock_Polarity Clock polarity
AnnaBridge 156:ff21514d8981 661 * @{
AnnaBridge 156:ff21514d8981 662 */
AnnaBridge 156:ff21514d8981 663 #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */
AnnaBridge 156:ff21514d8981 664 #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */
AnnaBridge 156:ff21514d8981 665 #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */
AnnaBridge 156:ff21514d8981 666 #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */
AnnaBridge 156:ff21514d8981 667 #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */
AnnaBridge 156:ff21514d8981 668 /**
AnnaBridge 156:ff21514d8981 669 * @}
AnnaBridge 156:ff21514d8981 670 */
AnnaBridge 156:ff21514d8981 671 #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \
AnnaBridge 156:ff21514d8981 672 ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
AnnaBridge 156:ff21514d8981 673 ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \
AnnaBridge 156:ff21514d8981 674 ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \
AnnaBridge 156:ff21514d8981 675 ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
AnnaBridge 156:ff21514d8981 676
AnnaBridge 156:ff21514d8981 677 /** @defgroup TIM_Clock_Prescaler Clock prescaler
AnnaBridge 156:ff21514d8981 678 * @{
AnnaBridge 156:ff21514d8981 679 */
AnnaBridge 156:ff21514d8981 680 #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
AnnaBridge 156:ff21514d8981 681 #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
AnnaBridge 156:ff21514d8981 682 #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
AnnaBridge 156:ff21514d8981 683 #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
AnnaBridge 156:ff21514d8981 684 /**
AnnaBridge 156:ff21514d8981 685 * @}
AnnaBridge 156:ff21514d8981 686 */
AnnaBridge 156:ff21514d8981 687 #define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
AnnaBridge 156:ff21514d8981 688 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
AnnaBridge 156:ff21514d8981 689 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
AnnaBridge 156:ff21514d8981 690 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
AnnaBridge 156:ff21514d8981 691
AnnaBridge 156:ff21514d8981 692
AnnaBridge 156:ff21514d8981 693 /* Check clock filter */
AnnaBridge 156:ff21514d8981 694 #define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
AnnaBridge 156:ff21514d8981 695
AnnaBridge 156:ff21514d8981 696 /** @defgroup TIM_ClearInput_Source Clear input source
AnnaBridge 156:ff21514d8981 697 * @{
AnnaBridge 156:ff21514d8981 698 */
AnnaBridge 156:ff21514d8981 699 #define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001U)
AnnaBridge 156:ff21514d8981 700 #define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000U)
AnnaBridge 156:ff21514d8981 701 /**
AnnaBridge 156:ff21514d8981 702 * @}
AnnaBridge 156:ff21514d8981 703 */
AnnaBridge 156:ff21514d8981 704
AnnaBridge 156:ff21514d8981 705 #define IS_TIM_CLEARINPUT_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_CLEARINPUTSOURCE_NONE) || \
AnnaBridge 156:ff21514d8981 706 ((__SOURCE__) == TIM_CLEARINPUTSOURCE_ETR))
AnnaBridge 156:ff21514d8981 707
AnnaBridge 156:ff21514d8981 708
AnnaBridge 156:ff21514d8981 709 /** @defgroup TIM_ClearInput_Polarity Clear input polarity
AnnaBridge 156:ff21514d8981 710 * @{
AnnaBridge 156:ff21514d8981 711 */
AnnaBridge 156:ff21514d8981 712 #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
AnnaBridge 156:ff21514d8981 713 #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
AnnaBridge 156:ff21514d8981 714 /**
AnnaBridge 156:ff21514d8981 715 * @}
AnnaBridge 156:ff21514d8981 716 */
AnnaBridge 156:ff21514d8981 717 #define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
AnnaBridge 156:ff21514d8981 718 ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
AnnaBridge 156:ff21514d8981 719
AnnaBridge 156:ff21514d8981 720
AnnaBridge 156:ff21514d8981 721 /** @defgroup TIM_ClearInput_Prescaler Clear input prescaler
AnnaBridge 156:ff21514d8981 722 * @{
AnnaBridge 156:ff21514d8981 723 */
AnnaBridge 156:ff21514d8981 724 #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
AnnaBridge 156:ff21514d8981 725 #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
AnnaBridge 156:ff21514d8981 726 #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
AnnaBridge 156:ff21514d8981 727 #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
AnnaBridge 156:ff21514d8981 728 /**
AnnaBridge 156:ff21514d8981 729 * @}
AnnaBridge 156:ff21514d8981 730 */
AnnaBridge 156:ff21514d8981 731 #define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
AnnaBridge 156:ff21514d8981 732 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
AnnaBridge 156:ff21514d8981 733 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
AnnaBridge 156:ff21514d8981 734 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
AnnaBridge 156:ff21514d8981 735
AnnaBridge 156:ff21514d8981 736
AnnaBridge 156:ff21514d8981 737 /* Check IC filter */
AnnaBridge 156:ff21514d8981 738 #define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xFU)
AnnaBridge 156:ff21514d8981 739
AnnaBridge 156:ff21514d8981 740
AnnaBridge 156:ff21514d8981 741 /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
AnnaBridge 156:ff21514d8981 742 * @{
AnnaBridge 156:ff21514d8981 743 */
AnnaBridge 156:ff21514d8981 744 #define TIM_TRGO_RESET ((uint32_t)0x0000U)
AnnaBridge 156:ff21514d8981 745 #define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
AnnaBridge 156:ff21514d8981 746 #define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
AnnaBridge 156:ff21514d8981 747 #define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
AnnaBridge 156:ff21514d8981 748 #define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
AnnaBridge 156:ff21514d8981 749 #define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
AnnaBridge 156:ff21514d8981 750 #define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
AnnaBridge 156:ff21514d8981 751 #define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
AnnaBridge 156:ff21514d8981 752 /**
AnnaBridge 156:ff21514d8981 753 * @}
AnnaBridge 156:ff21514d8981 754 */
AnnaBridge 156:ff21514d8981 755 #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \
AnnaBridge 156:ff21514d8981 756 ((__SOURCE__) == TIM_TRGO_ENABLE) || \
AnnaBridge 156:ff21514d8981 757 ((__SOURCE__) == TIM_TRGO_UPDATE) || \
AnnaBridge 156:ff21514d8981 758 ((__SOURCE__) == TIM_TRGO_OC1) || \
AnnaBridge 156:ff21514d8981 759 ((__SOURCE__) == TIM_TRGO_OC1REF) || \
AnnaBridge 156:ff21514d8981 760 ((__SOURCE__) == TIM_TRGO_OC2REF) || \
AnnaBridge 156:ff21514d8981 761 ((__SOURCE__) == TIM_TRGO_OC3REF) || \
AnnaBridge 156:ff21514d8981 762 ((__SOURCE__) == TIM_TRGO_OC4REF))
AnnaBridge 156:ff21514d8981 763
AnnaBridge 156:ff21514d8981 764
AnnaBridge 156:ff21514d8981 765
AnnaBridge 156:ff21514d8981 766 /** @defgroup TIM_Slave_Mode Slave mode
AnnaBridge 156:ff21514d8981 767 * @{
AnnaBridge 156:ff21514d8981 768 */
AnnaBridge 156:ff21514d8981 769 #define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000U)
AnnaBridge 156:ff21514d8981 770 #define TIM_SLAVEMODE_RESET ((uint32_t)0x0004U)
AnnaBridge 156:ff21514d8981 771 #define TIM_SLAVEMODE_GATED ((uint32_t)0x0005U)
AnnaBridge 156:ff21514d8981 772 #define TIM_SLAVEMODE_TRIGGER ((uint32_t)0x0006U)
AnnaBridge 156:ff21514d8981 773 #define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)0x0007U)
AnnaBridge 156:ff21514d8981 774 /**
AnnaBridge 156:ff21514d8981 775 * @}
AnnaBridge 156:ff21514d8981 776 */
AnnaBridge 156:ff21514d8981 777 #define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \
AnnaBridge 156:ff21514d8981 778 ((__MODE__) == TIM_SLAVEMODE_GATED) || \
AnnaBridge 156:ff21514d8981 779 ((__MODE__) == TIM_SLAVEMODE_RESET) || \
AnnaBridge 156:ff21514d8981 780 ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \
AnnaBridge 156:ff21514d8981 781 ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1))
AnnaBridge 156:ff21514d8981 782
AnnaBridge 156:ff21514d8981 783 /** @defgroup TIM_Master_Slave_Mode Master slave mode
AnnaBridge 156:ff21514d8981 784 * @{
AnnaBridge 156:ff21514d8981 785 */
AnnaBridge 156:ff21514d8981 786
AnnaBridge 156:ff21514d8981 787 #define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080U)
AnnaBridge 156:ff21514d8981 788 #define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000U)
AnnaBridge 156:ff21514d8981 789 /**
AnnaBridge 156:ff21514d8981 790 * @}
AnnaBridge 156:ff21514d8981 791 */
AnnaBridge 156:ff21514d8981 792 #define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
AnnaBridge 156:ff21514d8981 793 ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
AnnaBridge 156:ff21514d8981 794
AnnaBridge 156:ff21514d8981 795 /** @defgroup TIM_Trigger_Selection Trigger selection
AnnaBridge 156:ff21514d8981 796 * @{
AnnaBridge 156:ff21514d8981 797 */
AnnaBridge 156:ff21514d8981 798 #define TIM_TS_ITR0 ((uint32_t)0x0000U)
AnnaBridge 156:ff21514d8981 799 #define TIM_TS_ITR1 ((uint32_t)0x0010U)
AnnaBridge 156:ff21514d8981 800 #define TIM_TS_ITR2 ((uint32_t)0x0020U)
AnnaBridge 156:ff21514d8981 801 #define TIM_TS_ITR3 ((uint32_t)0x0030U)
AnnaBridge 156:ff21514d8981 802 #define TIM_TS_TI1F_ED ((uint32_t)0x0040U)
AnnaBridge 156:ff21514d8981 803 #define TIM_TS_TI1FP1 ((uint32_t)0x0050U)
AnnaBridge 156:ff21514d8981 804 #define TIM_TS_TI2FP2 ((uint32_t)0x0060U)
AnnaBridge 156:ff21514d8981 805 #define TIM_TS_ETRF ((uint32_t)0x0070U)
AnnaBridge 156:ff21514d8981 806 #define TIM_TS_NONE ((uint32_t)0xFFFFU)
AnnaBridge 156:ff21514d8981 807 /**
AnnaBridge 156:ff21514d8981 808 * @}
AnnaBridge 156:ff21514d8981 809 */
AnnaBridge 156:ff21514d8981 810 #define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
AnnaBridge 156:ff21514d8981 811 ((__SELECTION__) == TIM_TS_ITR1) || \
AnnaBridge 156:ff21514d8981 812 ((__SELECTION__) == TIM_TS_ITR2) || \
AnnaBridge 156:ff21514d8981 813 ((__SELECTION__) == TIM_TS_ITR3) || \
AnnaBridge 156:ff21514d8981 814 ((__SELECTION__) == TIM_TS_TI1F_ED) || \
AnnaBridge 156:ff21514d8981 815 ((__SELECTION__) == TIM_TS_TI1FP1) || \
AnnaBridge 156:ff21514d8981 816 ((__SELECTION__) == TIM_TS_TI2FP2) || \
AnnaBridge 156:ff21514d8981 817 ((__SELECTION__) == TIM_TS_ETRF))
AnnaBridge 156:ff21514d8981 818 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
AnnaBridge 156:ff21514d8981 819 ((__SELECTION__) == TIM_TS_ITR1) || \
AnnaBridge 156:ff21514d8981 820 ((__SELECTION__) == TIM_TS_ITR2) || \
AnnaBridge 156:ff21514d8981 821 ((__SELECTION__) == TIM_TS_ITR3) || \
AnnaBridge 156:ff21514d8981 822 ((__SELECTION__) == TIM_TS_NONE))
AnnaBridge 156:ff21514d8981 823
AnnaBridge 156:ff21514d8981 824
AnnaBridge 156:ff21514d8981 825 /** @defgroup TIM_Trigger_Polarity Trigger polarity
AnnaBridge 156:ff21514d8981 826 * @{
AnnaBridge 156:ff21514d8981 827 */
AnnaBridge 156:ff21514d8981 828 #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */
AnnaBridge 156:ff21514d8981 829 #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */
AnnaBridge 156:ff21514d8981 830 #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
AnnaBridge 156:ff21514d8981 831 #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
AnnaBridge 156:ff21514d8981 832 #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */
AnnaBridge 156:ff21514d8981 833 /**
AnnaBridge 156:ff21514d8981 834 * @}
AnnaBridge 156:ff21514d8981 835 */
AnnaBridge 156:ff21514d8981 836 #define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \
AnnaBridge 156:ff21514d8981 837 ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
AnnaBridge 156:ff21514d8981 838 ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \
AnnaBridge 156:ff21514d8981 839 ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \
AnnaBridge 156:ff21514d8981 840 ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
AnnaBridge 156:ff21514d8981 841
AnnaBridge 156:ff21514d8981 842
AnnaBridge 156:ff21514d8981 843 /** @defgroup TIM_Trigger_Prescaler Trigger prescaler
AnnaBridge 156:ff21514d8981 844 * @{
AnnaBridge 156:ff21514d8981 845 */
AnnaBridge 156:ff21514d8981 846 #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
AnnaBridge 156:ff21514d8981 847 #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
AnnaBridge 156:ff21514d8981 848 #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
AnnaBridge 156:ff21514d8981 849 #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
AnnaBridge 156:ff21514d8981 850 /**
AnnaBridge 156:ff21514d8981 851 * @}
AnnaBridge 156:ff21514d8981 852 */
AnnaBridge 156:ff21514d8981 853 #define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
AnnaBridge 156:ff21514d8981 854 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
AnnaBridge 156:ff21514d8981 855 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
AnnaBridge 156:ff21514d8981 856 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
AnnaBridge 156:ff21514d8981 857
AnnaBridge 156:ff21514d8981 858
AnnaBridge 156:ff21514d8981 859 /* Check trigger filter */
AnnaBridge 156:ff21514d8981 860 #define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
AnnaBridge 156:ff21514d8981 861
AnnaBridge 156:ff21514d8981 862
AnnaBridge 156:ff21514d8981 863 /** @defgroup TIM_TI1_Selection TI1 selection
AnnaBridge 156:ff21514d8981 864 * @{
AnnaBridge 156:ff21514d8981 865 */
AnnaBridge 156:ff21514d8981 866 #define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000U)
AnnaBridge 156:ff21514d8981 867 #define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
AnnaBridge 156:ff21514d8981 868 /**
AnnaBridge 156:ff21514d8981 869 * @}
AnnaBridge 156:ff21514d8981 870 */
AnnaBridge 156:ff21514d8981 871 #define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
AnnaBridge 156:ff21514d8981 872 ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
AnnaBridge 156:ff21514d8981 873
AnnaBridge 156:ff21514d8981 874
AnnaBridge 156:ff21514d8981 875 /** @defgroup TIM_DMA_Base_address DMA base address
AnnaBridge 156:ff21514d8981 876 * @{
AnnaBridge 156:ff21514d8981 877 */
AnnaBridge 156:ff21514d8981 878 #define TIM_DMABASE_CR1 (0x00000000U)
AnnaBridge 156:ff21514d8981 879 #define TIM_DMABASE_CR2 (0x00000001U)
AnnaBridge 156:ff21514d8981 880 #define TIM_DMABASE_SMCR (0x00000002U)
AnnaBridge 156:ff21514d8981 881 #define TIM_DMABASE_DIER (0x00000003U)
AnnaBridge 156:ff21514d8981 882 #define TIM_DMABASE_SR (0x00000004U)
AnnaBridge 156:ff21514d8981 883 #define TIM_DMABASE_EGR (0x00000005U)
AnnaBridge 156:ff21514d8981 884 #define TIM_DMABASE_CCMR1 (0x00000006U)
AnnaBridge 156:ff21514d8981 885 #define TIM_DMABASE_CCMR2 (0x00000007U)
AnnaBridge 156:ff21514d8981 886 #define TIM_DMABASE_CCER (0x00000008U)
AnnaBridge 156:ff21514d8981 887 #define TIM_DMABASE_CNT (0x00000009U)
AnnaBridge 156:ff21514d8981 888 #define TIM_DMABASE_PSC (0x0000000AU)
AnnaBridge 156:ff21514d8981 889 #define TIM_DMABASE_ARR (0x0000000BU)
AnnaBridge 156:ff21514d8981 890 #define TIM_DMABASE_CCR1 (0x0000000DU)
AnnaBridge 156:ff21514d8981 891 #define TIM_DMABASE_CCR2 (0x0000000EU)
AnnaBridge 156:ff21514d8981 892 #define TIM_DMABASE_CCR3 (0x0000000FU)
AnnaBridge 156:ff21514d8981 893 #define TIM_DMABASE_CCR4 (0x00000010U)
AnnaBridge 156:ff21514d8981 894 #define TIM_DMABASE_DCR (0x00000012U)
AnnaBridge 156:ff21514d8981 895 #define TIM_DMABASE_OR (0x00000013U)
AnnaBridge 156:ff21514d8981 896 /**
AnnaBridge 156:ff21514d8981 897 * @}
AnnaBridge 156:ff21514d8981 898 */
AnnaBridge 156:ff21514d8981 899 #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \
AnnaBridge 156:ff21514d8981 900 ((__BASE__) == TIM_DMABASE_CR2) || \
AnnaBridge 156:ff21514d8981 901 ((__BASE__) == TIM_DMABASE_SMCR) || \
AnnaBridge 156:ff21514d8981 902 ((__BASE__) == TIM_DMABASE_DIER) || \
AnnaBridge 156:ff21514d8981 903 ((__BASE__) == TIM_DMABASE_SR) || \
AnnaBridge 156:ff21514d8981 904 ((__BASE__) == TIM_DMABASE_EGR) || \
AnnaBridge 156:ff21514d8981 905 ((__BASE__) == TIM_DMABASE_CCMR1) || \
AnnaBridge 156:ff21514d8981 906 ((__BASE__) == TIM_DMABASE_CCMR2 ) || \
AnnaBridge 156:ff21514d8981 907 ((__BASE__) == TIM_DMABASE_CCER) || \
AnnaBridge 156:ff21514d8981 908 ((__BASE__) == TIM_DMABASE_CNT) || \
AnnaBridge 156:ff21514d8981 909 ((__BASE__) == TIM_DMABASE_PSC) || \
AnnaBridge 156:ff21514d8981 910 ((__BASE__) == TIM_DMABASE_ARR) || \
AnnaBridge 156:ff21514d8981 911 ((__BASE__) == TIM_DMABASE_CCR1) || \
AnnaBridge 156:ff21514d8981 912 ((__BASE__) == TIM_DMABASE_CCR2) || \
AnnaBridge 156:ff21514d8981 913 ((__BASE__) == TIM_DMABASE_CCR3) || \
AnnaBridge 156:ff21514d8981 914 ((__BASE__) == TIM_DMABASE_CCR4) || \
AnnaBridge 156:ff21514d8981 915 ((__BASE__) == TIM_DMABASE_DCR) || \
AnnaBridge 156:ff21514d8981 916 ((__BASE__) == TIM_DMABASE_OR))
AnnaBridge 156:ff21514d8981 917
AnnaBridge 156:ff21514d8981 918
AnnaBridge 156:ff21514d8981 919 /** @defgroup TIM_DMA_Burst_Length DMA burst length
AnnaBridge 156:ff21514d8981 920 * @{
AnnaBridge 156:ff21514d8981 921 */
AnnaBridge 156:ff21514d8981 922 #define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000U)
AnnaBridge 156:ff21514d8981 923 #define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100U)
AnnaBridge 156:ff21514d8981 924 #define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200U)
AnnaBridge 156:ff21514d8981 925 #define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300U)
AnnaBridge 156:ff21514d8981 926 #define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400U)
AnnaBridge 156:ff21514d8981 927 #define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500U)
AnnaBridge 156:ff21514d8981 928 #define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600U)
AnnaBridge 156:ff21514d8981 929 #define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700U)
AnnaBridge 156:ff21514d8981 930 #define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800U)
AnnaBridge 156:ff21514d8981 931 #define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900U)
AnnaBridge 156:ff21514d8981 932 #define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00U)
AnnaBridge 156:ff21514d8981 933 #define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00U)
AnnaBridge 156:ff21514d8981 934 #define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00U)
AnnaBridge 156:ff21514d8981 935 #define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00U)
AnnaBridge 156:ff21514d8981 936 #define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00U)
AnnaBridge 156:ff21514d8981 937 #define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00U)
AnnaBridge 156:ff21514d8981 938 #define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000U)
AnnaBridge 156:ff21514d8981 939 #define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100U)
AnnaBridge 156:ff21514d8981 940 /**
AnnaBridge 156:ff21514d8981 941 * @}
AnnaBridge 156:ff21514d8981 942 */
AnnaBridge 156:ff21514d8981 943 #define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER ) || \
AnnaBridge 156:ff21514d8981 944 ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
AnnaBridge 156:ff21514d8981 945 ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
AnnaBridge 156:ff21514d8981 946 ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
AnnaBridge 156:ff21514d8981 947 ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
AnnaBridge 156:ff21514d8981 948 ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
AnnaBridge 156:ff21514d8981 949 ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
AnnaBridge 156:ff21514d8981 950 ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
AnnaBridge 156:ff21514d8981 951 ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS ) || \
AnnaBridge 156:ff21514d8981 952 ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
AnnaBridge 156:ff21514d8981 953 ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS ) || \
AnnaBridge 156:ff21514d8981 954 ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
AnnaBridge 156:ff21514d8981 955 ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
AnnaBridge 156:ff21514d8981 956 ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
AnnaBridge 156:ff21514d8981 957 ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
AnnaBridge 156:ff21514d8981 958 ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
AnnaBridge 156:ff21514d8981 959 ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
AnnaBridge 156:ff21514d8981 960 ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS ))
AnnaBridge 156:ff21514d8981 961
AnnaBridge 156:ff21514d8981 962
AnnaBridge 156:ff21514d8981 963 /* Check IC filter */
AnnaBridge 156:ff21514d8981 964 #define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
AnnaBridge 156:ff21514d8981 965
AnnaBridge 156:ff21514d8981 966 /** @defgroup DMA_Handle_index DMA handle index
AnnaBridge 156:ff21514d8981 967 * @{
AnnaBridge 156:ff21514d8981 968 */
AnnaBridge 156:ff21514d8981 969 #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0U) /*!< Index of the DMA handle used for Update DMA requests */
AnnaBridge 156:ff21514d8981 970 #define TIM_DMA_ID_CC1 ((uint16_t) 0x1U) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
AnnaBridge 156:ff21514d8981 971 #define TIM_DMA_ID_CC2 ((uint16_t) 0x2U) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
AnnaBridge 156:ff21514d8981 972 #define TIM_DMA_ID_CC3 ((uint16_t) 0x3U) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
AnnaBridge 156:ff21514d8981 973 #define TIM_DMA_ID_CC4 ((uint16_t) 0x4U) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
AnnaBridge 156:ff21514d8981 974 #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x5U) /*!< Index of the DMA handle used for Trigger DMA requests */
AnnaBridge 156:ff21514d8981 975 /**
AnnaBridge 156:ff21514d8981 976 * @}
AnnaBridge 156:ff21514d8981 977 */
AnnaBridge 156:ff21514d8981 978
AnnaBridge 156:ff21514d8981 979 /** @defgroup Channel_CC_State Channel state
AnnaBridge 156:ff21514d8981 980 * @{
AnnaBridge 156:ff21514d8981 981 */
AnnaBridge 156:ff21514d8981 982 #define TIM_CCx_ENABLE ((uint32_t)0x0001U)
AnnaBridge 156:ff21514d8981 983 #define TIM_CCx_DISABLE ((uint32_t)0x0000U)
AnnaBridge 156:ff21514d8981 984 /**
AnnaBridge 156:ff21514d8981 985 * @}
AnnaBridge 156:ff21514d8981 986 */
AnnaBridge 156:ff21514d8981 987
AnnaBridge 156:ff21514d8981 988 /**
AnnaBridge 156:ff21514d8981 989 * @}
AnnaBridge 156:ff21514d8981 990 */
AnnaBridge 156:ff21514d8981 991
AnnaBridge 156:ff21514d8981 992 /* Exported macro ------------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 993 /** @defgroup TIM_Exported_Macro TIM Exported Macro
AnnaBridge 156:ff21514d8981 994 * @{
AnnaBridge 156:ff21514d8981 995 */
AnnaBridge 156:ff21514d8981 996
AnnaBridge 156:ff21514d8981 997 /** @brief Reset UART handle state
AnnaBridge 156:ff21514d8981 998 * @param __HANDLE__ : TIM handle
AnnaBridge 156:ff21514d8981 999 * @retval None
AnnaBridge 156:ff21514d8981 1000 */
AnnaBridge 156:ff21514d8981 1001 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
AnnaBridge 156:ff21514d8981 1002
AnnaBridge 156:ff21514d8981 1003 /**
AnnaBridge 156:ff21514d8981 1004 * @brief Enable the TIM peripheral.
AnnaBridge 156:ff21514d8981 1005 * @param __HANDLE__ : TIM handle
AnnaBridge 156:ff21514d8981 1006 * @retval None
AnnaBridge 156:ff21514d8981 1007 */
AnnaBridge 156:ff21514d8981 1008 #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
AnnaBridge 156:ff21514d8981 1009
AnnaBridge 156:ff21514d8981 1010 /* The counter of a timer instance is disabled only if all the CCx channels have
AnnaBridge 156:ff21514d8981 1011 been disabled */
AnnaBridge 156:ff21514d8981 1012 #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
AnnaBridge 156:ff21514d8981 1013
AnnaBridge 156:ff21514d8981 1014 /**
AnnaBridge 156:ff21514d8981 1015 * @brief Disable the TIM peripheral.
AnnaBridge 156:ff21514d8981 1016 * @param __HANDLE__ : TIM handle
AnnaBridge 156:ff21514d8981 1017 * @retval None
AnnaBridge 156:ff21514d8981 1018 */
AnnaBridge 156:ff21514d8981 1019 #define __HAL_TIM_DISABLE(__HANDLE__) \
AnnaBridge 156:ff21514d8981 1020 do { \
AnnaBridge 156:ff21514d8981 1021 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \
AnnaBridge 156:ff21514d8981 1022 { \
AnnaBridge 156:ff21514d8981 1023 (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
AnnaBridge 156:ff21514d8981 1024 } \
AnnaBridge 156:ff21514d8981 1025 } while(0)
AnnaBridge 156:ff21514d8981 1026
AnnaBridge 156:ff21514d8981 1027 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
AnnaBridge 156:ff21514d8981 1028 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
AnnaBridge 156:ff21514d8981 1029 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
AnnaBridge 156:ff21514d8981 1030 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
AnnaBridge 156:ff21514d8981 1031 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
AnnaBridge 156:ff21514d8981 1032 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
AnnaBridge 156:ff21514d8981 1033
AnnaBridge 156:ff21514d8981 1034 #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
AnnaBridge 156:ff21514d8981 1035 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
AnnaBridge 156:ff21514d8981 1036
AnnaBridge 156:ff21514d8981 1037 #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
AnnaBridge 156:ff21514d8981 1038 #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
AnnaBridge 156:ff21514d8981 1039
AnnaBridge 156:ff21514d8981 1040 #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
AnnaBridge 156:ff21514d8981 1041 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
AnnaBridge 156:ff21514d8981 1042 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
AnnaBridge 156:ff21514d8981 1043 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
AnnaBridge 156:ff21514d8981 1044 ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8)))
AnnaBridge 156:ff21514d8981 1045
AnnaBridge 156:ff21514d8981 1046 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
AnnaBridge 156:ff21514d8981 1047 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
AnnaBridge 156:ff21514d8981 1048 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
AnnaBridge 156:ff21514d8981 1049 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
AnnaBridge 156:ff21514d8981 1050 ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
AnnaBridge 156:ff21514d8981 1051
AnnaBridge 156:ff21514d8981 1052 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
AnnaBridge 156:ff21514d8981 1053 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
AnnaBridge 156:ff21514d8981 1054 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
AnnaBridge 156:ff21514d8981 1055 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
AnnaBridge 156:ff21514d8981 1056 ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U) & TIM_CCER_CC4P)))
AnnaBridge 156:ff21514d8981 1057
AnnaBridge 156:ff21514d8981 1058 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
AnnaBridge 156:ff21514d8981 1059 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
AnnaBridge 156:ff21514d8981 1060 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
AnnaBridge 156:ff21514d8981 1061 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
AnnaBridge 156:ff21514d8981 1062 ((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P))
AnnaBridge 156:ff21514d8981 1063
AnnaBridge 156:ff21514d8981 1064 /**
AnnaBridge 156:ff21514d8981 1065 * @brief Sets the TIM Capture Compare Register value on runtime without
AnnaBridge 156:ff21514d8981 1066 * calling another time ConfigChannel function.
AnnaBridge 156:ff21514d8981 1067 * @param __HANDLE__ : TIM handle.
AnnaBridge 156:ff21514d8981 1068 * @param __CHANNEL__ : TIM Channels to be configured.
AnnaBridge 156:ff21514d8981 1069 * This parameter can be one of the following values:
AnnaBridge 156:ff21514d8981 1070 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
AnnaBridge 156:ff21514d8981 1071 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
AnnaBridge 156:ff21514d8981 1072 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
AnnaBridge 156:ff21514d8981 1073 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
AnnaBridge 156:ff21514d8981 1074 * @param __COMPARE__: specifies the Capture Compare register new value.
AnnaBridge 156:ff21514d8981 1075 * @retval None
AnnaBridge 156:ff21514d8981 1076 */
AnnaBridge 156:ff21514d8981 1077 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
AnnaBridge 156:ff21514d8981 1078 (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)) = (__COMPARE__))
AnnaBridge 156:ff21514d8981 1079
AnnaBridge 156:ff21514d8981 1080 /**
AnnaBridge 156:ff21514d8981 1081 * @brief Gets the TIM Capture Compare Register value on runtime
AnnaBridge 156:ff21514d8981 1082 * @param __HANDLE__ : TIM handle.
AnnaBridge 156:ff21514d8981 1083 * @param __CHANNEL__ : TIM Channel associated with the capture compare register
AnnaBridge 156:ff21514d8981 1084 * This parameter can be one of the following values:
AnnaBridge 156:ff21514d8981 1085 * @arg TIM_CHANNEL_1: get capture/compare 1 register value
AnnaBridge 156:ff21514d8981 1086 * @arg TIM_CHANNEL_2: get capture/compare 2 register value
AnnaBridge 156:ff21514d8981 1087 * @arg TIM_CHANNEL_3: get capture/compare 3 register value
AnnaBridge 156:ff21514d8981 1088 * @arg TIM_CHANNEL_4: get capture/compare 4 register value
AnnaBridge 156:ff21514d8981 1089 * @retval None
AnnaBridge 156:ff21514d8981 1090 */
AnnaBridge 156:ff21514d8981 1091 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
AnnaBridge 156:ff21514d8981 1092 (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)))
AnnaBridge 156:ff21514d8981 1093
AnnaBridge 156:ff21514d8981 1094 /**
AnnaBridge 156:ff21514d8981 1095 * @brief Sets the TIM Counter Register value on runtime.
AnnaBridge 156:ff21514d8981 1096 * @param __HANDLE__ : TIM handle.
AnnaBridge 156:ff21514d8981 1097 * @param __COUNTER__: specifies the Counter register new value.
AnnaBridge 156:ff21514d8981 1098 * @retval None
AnnaBridge 156:ff21514d8981 1099 */
AnnaBridge 156:ff21514d8981 1100 #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
AnnaBridge 156:ff21514d8981 1101
AnnaBridge 156:ff21514d8981 1102 /**
AnnaBridge 156:ff21514d8981 1103 * @brief Gets the TIM Counter Register value on runtime.
AnnaBridge 156:ff21514d8981 1104 * @param __HANDLE__ : TIM handle.
AnnaBridge 156:ff21514d8981 1105 * @retval None
AnnaBridge 156:ff21514d8981 1106 */
AnnaBridge 156:ff21514d8981 1107 #define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
AnnaBridge 156:ff21514d8981 1108
AnnaBridge 156:ff21514d8981 1109 /**
AnnaBridge 156:ff21514d8981 1110 * @brief Sets the TIM Autoreload Register value on runtime without calling
AnnaBridge 156:ff21514d8981 1111 * another time any Init function.
AnnaBridge 156:ff21514d8981 1112 * @param __HANDLE__ : TIM handle.
AnnaBridge 156:ff21514d8981 1113 * @param __AUTORELOAD__: specifies the Counter register new value.
AnnaBridge 156:ff21514d8981 1114 * @retval None
AnnaBridge 156:ff21514d8981 1115 */
AnnaBridge 156:ff21514d8981 1116 #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
AnnaBridge 156:ff21514d8981 1117 do{ \
AnnaBridge 156:ff21514d8981 1118 (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
AnnaBridge 156:ff21514d8981 1119 (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
AnnaBridge 156:ff21514d8981 1120 } while(0)
AnnaBridge 156:ff21514d8981 1121 /**
AnnaBridge 156:ff21514d8981 1122 * @brief Gets the TIM Autoreload Register value on runtime
AnnaBridge 156:ff21514d8981 1123 * @param __HANDLE__ : TIM handle.
AnnaBridge 156:ff21514d8981 1124 * @retval None
AnnaBridge 156:ff21514d8981 1125 */
AnnaBridge 156:ff21514d8981 1126 #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
AnnaBridge 156:ff21514d8981 1127
AnnaBridge 156:ff21514d8981 1128 /**
AnnaBridge 156:ff21514d8981 1129 * @brief Sets the TIM Clock Division value on runtime without calling
AnnaBridge 156:ff21514d8981 1130 * another time any Init function.
AnnaBridge 156:ff21514d8981 1131 * @param __HANDLE__ : TIM handle.
AnnaBridge 156:ff21514d8981 1132 * @param __CKD__: specifies the clock division value.
AnnaBridge 156:ff21514d8981 1133 * This parameter can be one of the following value:
AnnaBridge 156:ff21514d8981 1134 * @arg TIM_CLOCKDIVISION_DIV1
AnnaBridge 156:ff21514d8981 1135 * @arg TIM_CLOCKDIVISION_DIV2
AnnaBridge 156:ff21514d8981 1136 * @arg TIM_CLOCKDIVISION_DIV4
AnnaBridge 156:ff21514d8981 1137 * @retval None
AnnaBridge 156:ff21514d8981 1138 */
AnnaBridge 156:ff21514d8981 1139 #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
AnnaBridge 156:ff21514d8981 1140 do{ \
AnnaBridge 156:ff21514d8981 1141 (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
AnnaBridge 156:ff21514d8981 1142 (__HANDLE__)->Instance->CR1 |= (__CKD__); \
AnnaBridge 156:ff21514d8981 1143 (__HANDLE__)->Init.ClockDivision = (__CKD__); \
AnnaBridge 156:ff21514d8981 1144 } while(0)
AnnaBridge 156:ff21514d8981 1145 /**
AnnaBridge 156:ff21514d8981 1146 * @brief Gets the TIM Clock Division value on runtime
AnnaBridge 156:ff21514d8981 1147 * @param __HANDLE__ : TIM handle.
AnnaBridge 156:ff21514d8981 1148 * @retval None
AnnaBridge 156:ff21514d8981 1149 */
AnnaBridge 156:ff21514d8981 1150 #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
AnnaBridge 156:ff21514d8981 1151
AnnaBridge 156:ff21514d8981 1152 /**
AnnaBridge 156:ff21514d8981 1153 * @brief Sets the TIM Input Capture prescaler on runtime without calling
AnnaBridge 156:ff21514d8981 1154 * another time HAL_TIM_IC_ConfigChannel() function.
AnnaBridge 156:ff21514d8981 1155 * @param __HANDLE__ : TIM handle.
AnnaBridge 156:ff21514d8981 1156 * @param __CHANNEL__ : TIM Channels to be configured.
AnnaBridge 156:ff21514d8981 1157 * This parameter can be one of the following values:
AnnaBridge 156:ff21514d8981 1158 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
AnnaBridge 156:ff21514d8981 1159 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
AnnaBridge 156:ff21514d8981 1160 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
AnnaBridge 156:ff21514d8981 1161 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
AnnaBridge 156:ff21514d8981 1162 * @param __ICPSC__: specifies the Input Capture4 prescaler new value.
AnnaBridge 156:ff21514d8981 1163 * This parameter can be one of the following values:
AnnaBridge 156:ff21514d8981 1164 * @arg TIM_ICPSC_DIV1: no prescaler
AnnaBridge 156:ff21514d8981 1165 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
AnnaBridge 156:ff21514d8981 1166 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
AnnaBridge 156:ff21514d8981 1167 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
AnnaBridge 156:ff21514d8981 1168 * @retval None
AnnaBridge 156:ff21514d8981 1169 */
AnnaBridge 156:ff21514d8981 1170 #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
AnnaBridge 156:ff21514d8981 1171 do{ \
AnnaBridge 156:ff21514d8981 1172 TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
AnnaBridge 156:ff21514d8981 1173 TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
AnnaBridge 156:ff21514d8981 1174 } while(0)
AnnaBridge 156:ff21514d8981 1175
AnnaBridge 156:ff21514d8981 1176 /**
AnnaBridge 156:ff21514d8981 1177 * @brief Gets the TIM Input Capture prescaler on runtime
AnnaBridge 156:ff21514d8981 1178 * @param __HANDLE__ : TIM handle.
AnnaBridge 156:ff21514d8981 1179 * @param __CHANNEL__ : TIM Channels to be configured.
AnnaBridge 156:ff21514d8981 1180 * This parameter can be one of the following values:
AnnaBridge 156:ff21514d8981 1181 * @arg TIM_CHANNEL_1: get input capture 1 prescaler value
AnnaBridge 156:ff21514d8981 1182 * @arg TIM_CHANNEL_2: get input capture 2 prescaler value
AnnaBridge 156:ff21514d8981 1183 * @arg TIM_CHANNEL_3: get input capture 3 prescaler value
AnnaBridge 156:ff21514d8981 1184 * @arg TIM_CHANNEL_4: get input capture 4 prescaler value
AnnaBridge 156:ff21514d8981 1185 * @retval None
AnnaBridge 156:ff21514d8981 1186 */
AnnaBridge 156:ff21514d8981 1187 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
AnnaBridge 156:ff21514d8981 1188 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
AnnaBridge 156:ff21514d8981 1189 ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
AnnaBridge 156:ff21514d8981 1190 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
AnnaBridge 156:ff21514d8981 1191 (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
AnnaBridge 156:ff21514d8981 1192
AnnaBridge 156:ff21514d8981 1193
AnnaBridge 156:ff21514d8981 1194 /**
AnnaBridge 156:ff21514d8981 1195 * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register
AnnaBridge 156:ff21514d8981 1196 * @param __HANDLE__: TIM handle.
AnnaBridge 156:ff21514d8981 1197 * @note When the URS bit of the TIMx_CR1 register is set, only counter
AnnaBridge 156:ff21514d8981 1198 * overflow/underflow generates an update interrupt or DMA request (if
AnnaBridge 156:ff21514d8981 1199 * enabled)
AnnaBridge 156:ff21514d8981 1200 * @retval None
AnnaBridge 156:ff21514d8981 1201 */
AnnaBridge 156:ff21514d8981 1202 #define __HAL_TIM_URS_ENABLE(__HANDLE__) \
AnnaBridge 156:ff21514d8981 1203 ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS))
AnnaBridge 156:ff21514d8981 1204
AnnaBridge 156:ff21514d8981 1205 /**
AnnaBridge 156:ff21514d8981 1206 * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register
AnnaBridge 156:ff21514d8981 1207 * @param __HANDLE__: TIM handle.
AnnaBridge 156:ff21514d8981 1208 * @note When the URS bit of the TIMx_CR1 register is reset, any of the
AnnaBridge 156:ff21514d8981 1209 * following events generate an update interrupt or DMA request (if
AnnaBridge 156:ff21514d8981 1210 * enabled):
AnnaBridge 156:ff21514d8981 1211 * Counter overflow/underflow
AnnaBridge 156:ff21514d8981 1212 * Setting the UG bit
AnnaBridge 156:ff21514d8981 1213 * Update generation through the slave mode controller
AnnaBridge 156:ff21514d8981 1214 * @retval None
AnnaBridge 156:ff21514d8981 1215 */
AnnaBridge 156:ff21514d8981 1216 #define __HAL_TIM_URS_DISABLE(__HANDLE__) \
AnnaBridge 156:ff21514d8981 1217 ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
AnnaBridge 156:ff21514d8981 1218
AnnaBridge 156:ff21514d8981 1219 /**
AnnaBridge 156:ff21514d8981 1220 * @brief Sets the TIM Capture x input polarity on runtime.
AnnaBridge 156:ff21514d8981 1221 * @param __HANDLE__: TIM handle.
AnnaBridge 156:ff21514d8981 1222 * @param __CHANNEL__: TIM Channels to be configured.
AnnaBridge 156:ff21514d8981 1223 * This parameter can be one of the following values:
AnnaBridge 156:ff21514d8981 1224 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
AnnaBridge 156:ff21514d8981 1225 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
AnnaBridge 156:ff21514d8981 1226 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
AnnaBridge 156:ff21514d8981 1227 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
AnnaBridge 156:ff21514d8981 1228 * @param __POLARITY__: Polarity for TIx source
AnnaBridge 156:ff21514d8981 1229 * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
AnnaBridge 156:ff21514d8981 1230 * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
AnnaBridge 156:ff21514d8981 1231 * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
AnnaBridge 156:ff21514d8981 1232 * @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4.
AnnaBridge 156:ff21514d8981 1233 * @retval None
AnnaBridge 156:ff21514d8981 1234 */
AnnaBridge 156:ff21514d8981 1235 #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
AnnaBridge 156:ff21514d8981 1236 do{ \
AnnaBridge 156:ff21514d8981 1237 TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
AnnaBridge 156:ff21514d8981 1238 TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
AnnaBridge 156:ff21514d8981 1239 }while(0)
AnnaBridge 156:ff21514d8981 1240
AnnaBridge 156:ff21514d8981 1241 /**
AnnaBridge 156:ff21514d8981 1242 * @}
AnnaBridge 156:ff21514d8981 1243 */
AnnaBridge 156:ff21514d8981 1244
AnnaBridge 156:ff21514d8981 1245 /* Include TIM HAL Extension module */
AnnaBridge 156:ff21514d8981 1246 #include "stm32l0xx_hal_tim_ex.h"
AnnaBridge 156:ff21514d8981 1247
AnnaBridge 156:ff21514d8981 1248 /* Exported functions --------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 1249 /** @defgroup TIM_Exported_Functions TIM Exported Functions
AnnaBridge 156:ff21514d8981 1250 * @{
AnnaBridge 156:ff21514d8981 1251 */
AnnaBridge 156:ff21514d8981 1252
AnnaBridge 156:ff21514d8981 1253 /* Exported functions --------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 1254 /* Time Base functions ********************************************************/
AnnaBridge 156:ff21514d8981 1255
AnnaBridge 156:ff21514d8981 1256 /** @defgroup TIM_Exported_Functions_Group1 Timer Base functions
AnnaBridge 156:ff21514d8981 1257 * @brief Time Base functions
AnnaBridge 156:ff21514d8981 1258 * @{
AnnaBridge 156:ff21514d8981 1259 */
AnnaBridge 156:ff21514d8981 1260 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1261 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1262 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1263 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1264 /* Blocking mode: Polling */
AnnaBridge 156:ff21514d8981 1265 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1266 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1267 /* Non-Blocking mode: Interrupt */
AnnaBridge 156:ff21514d8981 1268 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1269 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1270 /* Non-Blocking mode: DMA */
AnnaBridge 156:ff21514d8981 1271 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
AnnaBridge 156:ff21514d8981 1272 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1273
AnnaBridge 156:ff21514d8981 1274 /**
AnnaBridge 156:ff21514d8981 1275 * @}
AnnaBridge 156:ff21514d8981 1276 */
AnnaBridge 156:ff21514d8981 1277
AnnaBridge 156:ff21514d8981 1278
AnnaBridge 156:ff21514d8981 1279 /* Timer Output Compare functions **********************************************/
AnnaBridge 156:ff21514d8981 1280
AnnaBridge 156:ff21514d8981 1281 /** @defgroup TIM_Exported_Functions_Group2 Timer Output Compare functions
AnnaBridge 156:ff21514d8981 1282 * @brief Timer Output Compare functions
AnnaBridge 156:ff21514d8981 1283 * @{
AnnaBridge 156:ff21514d8981 1284 */
AnnaBridge 156:ff21514d8981 1285
AnnaBridge 156:ff21514d8981 1286 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1287 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1288 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1289 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1290 /* Blocking mode: Polling */
AnnaBridge 156:ff21514d8981 1291 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 156:ff21514d8981 1292 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 156:ff21514d8981 1293 /* Non-Blocking mode: Interrupt */
AnnaBridge 156:ff21514d8981 1294 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 156:ff21514d8981 1295 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 156:ff21514d8981 1296 /* Non-Blocking mode: DMA */
AnnaBridge 156:ff21514d8981 1297 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
AnnaBridge 156:ff21514d8981 1298 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 156:ff21514d8981 1299 /**
AnnaBridge 156:ff21514d8981 1300 * @}
AnnaBridge 156:ff21514d8981 1301 */
AnnaBridge 156:ff21514d8981 1302
AnnaBridge 156:ff21514d8981 1303
AnnaBridge 156:ff21514d8981 1304 /* Timer PWM functions *********************************************************/
AnnaBridge 156:ff21514d8981 1305
AnnaBridge 156:ff21514d8981 1306 /** @defgroup TIM_Exported_Functions_Group3 Timer PWM functions
AnnaBridge 156:ff21514d8981 1307 * @brief Timer PWM functions
AnnaBridge 156:ff21514d8981 1308 * @{
AnnaBridge 156:ff21514d8981 1309 */
AnnaBridge 156:ff21514d8981 1310 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1311 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1312 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1313 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1314 /* Blocking mode: Polling */
AnnaBridge 156:ff21514d8981 1315 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 156:ff21514d8981 1316 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 156:ff21514d8981 1317 /* Non-Blocking mode: Interrupt */
AnnaBridge 156:ff21514d8981 1318 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 156:ff21514d8981 1319 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 156:ff21514d8981 1320 /* Non-Blocking mode: DMA */
AnnaBridge 156:ff21514d8981 1321 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
AnnaBridge 156:ff21514d8981 1322 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 156:ff21514d8981 1323 /**
AnnaBridge 156:ff21514d8981 1324 * @}
AnnaBridge 156:ff21514d8981 1325 */
AnnaBridge 156:ff21514d8981 1326
AnnaBridge 156:ff21514d8981 1327 /* Timer Input Capture functions ***********************************************/
AnnaBridge 156:ff21514d8981 1328
AnnaBridge 156:ff21514d8981 1329 /** @defgroup TIM_Exported_Functions_Group4 Timer Input Capture functions
AnnaBridge 156:ff21514d8981 1330 * @brief Timer Input Capture functions
AnnaBridge 156:ff21514d8981 1331 * @{
AnnaBridge 156:ff21514d8981 1332 */
AnnaBridge 156:ff21514d8981 1333 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1334 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1335 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1336 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1337 /* Blocking mode: Polling */
AnnaBridge 156:ff21514d8981 1338 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 156:ff21514d8981 1339 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 156:ff21514d8981 1340 /* Non-Blocking mode: Interrupt */
AnnaBridge 156:ff21514d8981 1341 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 156:ff21514d8981 1342 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 156:ff21514d8981 1343 /* Non-Blocking mode: DMA */
AnnaBridge 156:ff21514d8981 1344 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
AnnaBridge 156:ff21514d8981 1345 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 156:ff21514d8981 1346 /**
AnnaBridge 156:ff21514d8981 1347 * @}
AnnaBridge 156:ff21514d8981 1348 */
AnnaBridge 156:ff21514d8981 1349
AnnaBridge 156:ff21514d8981 1350 /* Timer One Pulse functions ***************************************************/
AnnaBridge 156:ff21514d8981 1351
AnnaBridge 156:ff21514d8981 1352 /** @defgroup TIM_Exported_Functions_Group5 Timer One Pulse functions
AnnaBridge 156:ff21514d8981 1353 * @brief Timer One Pulse functions
AnnaBridge 156:ff21514d8981 1354 * @{
AnnaBridge 156:ff21514d8981 1355 */
AnnaBridge 156:ff21514d8981 1356 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
AnnaBridge 156:ff21514d8981 1357 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1358 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1359 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1360 /* Blocking mode: Polling */
AnnaBridge 156:ff21514d8981 1361 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
AnnaBridge 156:ff21514d8981 1362 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
AnnaBridge 156:ff21514d8981 1363
AnnaBridge 156:ff21514d8981 1364 /* Non-Blocking mode: Interrupt */
AnnaBridge 156:ff21514d8981 1365 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
AnnaBridge 156:ff21514d8981 1366 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
AnnaBridge 156:ff21514d8981 1367
AnnaBridge 156:ff21514d8981 1368 /**
AnnaBridge 156:ff21514d8981 1369 * @}
AnnaBridge 156:ff21514d8981 1370 */
AnnaBridge 156:ff21514d8981 1371
AnnaBridge 156:ff21514d8981 1372 /* Timer Encoder functions *****************************************************/
AnnaBridge 156:ff21514d8981 1373
AnnaBridge 156:ff21514d8981 1374 /** @defgroup TIM_Exported_Functions_Group6 Timer Encoder functions
AnnaBridge 156:ff21514d8981 1375 * @brief Timer Encoder functions
AnnaBridge 156:ff21514d8981 1376 * @{
AnnaBridge 156:ff21514d8981 1377 */
AnnaBridge 156:ff21514d8981 1378 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig);
AnnaBridge 156:ff21514d8981 1379 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1380 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1381 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1382 /* Blocking mode: Polling */
AnnaBridge 156:ff21514d8981 1383 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 156:ff21514d8981 1384 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 156:ff21514d8981 1385 /* Non-Blocking mode: Interrupt */
AnnaBridge 156:ff21514d8981 1386 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 156:ff21514d8981 1387 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 156:ff21514d8981 1388 /* Non-Blocking mode: DMA */
AnnaBridge 156:ff21514d8981 1389 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
AnnaBridge 156:ff21514d8981 1390 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 156:ff21514d8981 1391
AnnaBridge 156:ff21514d8981 1392 /**
AnnaBridge 156:ff21514d8981 1393 * @}
AnnaBridge 156:ff21514d8981 1394 */
AnnaBridge 156:ff21514d8981 1395
AnnaBridge 156:ff21514d8981 1396 /* Interrupt Handler functions **********************************************/
AnnaBridge 156:ff21514d8981 1397
AnnaBridge 156:ff21514d8981 1398 /** @defgroup TIM_Exported_Functions_Group7 Timer IRQ handler management
AnnaBridge 156:ff21514d8981 1399 * @brief Interrupt Handler functions
AnnaBridge 156:ff21514d8981 1400 * @{
AnnaBridge 156:ff21514d8981 1401 */
AnnaBridge 156:ff21514d8981 1402 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1403 /**
AnnaBridge 156:ff21514d8981 1404 * @}
AnnaBridge 156:ff21514d8981 1405 */
AnnaBridge 156:ff21514d8981 1406
AnnaBridge 156:ff21514d8981 1407 /* Control functions *********************************************************/
AnnaBridge 156:ff21514d8981 1408
AnnaBridge 156:ff21514d8981 1409 /** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
AnnaBridge 156:ff21514d8981 1410 * @brief Control functions
AnnaBridge 156:ff21514d8981 1411 * @{
AnnaBridge 156:ff21514d8981 1412 */
AnnaBridge 156:ff21514d8981 1413 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
AnnaBridge 156:ff21514d8981 1414 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
AnnaBridge 156:ff21514d8981 1415 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel);
AnnaBridge 156:ff21514d8981 1416 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel);
AnnaBridge 156:ff21514d8981 1417 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel);
AnnaBridge 156:ff21514d8981 1418 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig);
AnnaBridge 156:ff21514d8981 1419 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
AnnaBridge 156:ff21514d8981 1420 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
AnnaBridge 156:ff21514d8981 1421 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
AnnaBridge 156:ff21514d8981 1422 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
AnnaBridge 156:ff21514d8981 1423 uint32_t *BurstBuffer, uint32_t BurstLength);
AnnaBridge 156:ff21514d8981 1424 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
AnnaBridge 156:ff21514d8981 1425 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
AnnaBridge 156:ff21514d8981 1426 uint32_t *BurstBuffer, uint32_t BurstLength);
AnnaBridge 156:ff21514d8981 1427 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
AnnaBridge 156:ff21514d8981 1428 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
AnnaBridge 156:ff21514d8981 1429 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 156:ff21514d8981 1430
AnnaBridge 156:ff21514d8981 1431 /**
AnnaBridge 156:ff21514d8981 1432 * @}
AnnaBridge 156:ff21514d8981 1433 */
AnnaBridge 156:ff21514d8981 1434
AnnaBridge 156:ff21514d8981 1435 /* Callback in non blocking modes (Interrupt and DMA) *************************/
AnnaBridge 156:ff21514d8981 1436
AnnaBridge 156:ff21514d8981 1437 /** @defgroup TIM_Exported_Functions_Group9 Timer Callbacks functions
AnnaBridge 156:ff21514d8981 1438 * @brief Callback functions
AnnaBridge 156:ff21514d8981 1439 * @{
AnnaBridge 156:ff21514d8981 1440 */
AnnaBridge 156:ff21514d8981 1441 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1442 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1443 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1444 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1445 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1446 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1447 /**
AnnaBridge 156:ff21514d8981 1448 * @}
AnnaBridge 156:ff21514d8981 1449 */
AnnaBridge 156:ff21514d8981 1450
AnnaBridge 156:ff21514d8981 1451
AnnaBridge 156:ff21514d8981 1452 /* Peripheral State functions **************************************************/
AnnaBridge 156:ff21514d8981 1453
AnnaBridge 156:ff21514d8981 1454 /** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
AnnaBridge 156:ff21514d8981 1455 * @brief Peripheral State functions
AnnaBridge 156:ff21514d8981 1456 * @{
AnnaBridge 156:ff21514d8981 1457 */
AnnaBridge 156:ff21514d8981 1458 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1459 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1460 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1461 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1462 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1463 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1464 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
AnnaBridge 156:ff21514d8981 1465 void TIM_DMAError(DMA_HandleTypeDef *hdma);
AnnaBridge 156:ff21514d8981 1466 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
AnnaBridge 156:ff21514d8981 1467
AnnaBridge 156:ff21514d8981 1468 /**
AnnaBridge 156:ff21514d8981 1469 * @}
AnnaBridge 156:ff21514d8981 1470 */
AnnaBridge 156:ff21514d8981 1471
AnnaBridge 156:ff21514d8981 1472 /**
AnnaBridge 156:ff21514d8981 1473 * @}
AnnaBridge 156:ff21514d8981 1474 */
AnnaBridge 156:ff21514d8981 1475
AnnaBridge 156:ff21514d8981 1476 /* Define the private group ***********************************/
AnnaBridge 156:ff21514d8981 1477 /**************************************************************/
AnnaBridge 156:ff21514d8981 1478 /** @defgroup TIM_Private TIM Private
AnnaBridge 156:ff21514d8981 1479 * @{
AnnaBridge 156:ff21514d8981 1480 */
AnnaBridge 156:ff21514d8981 1481 /**
AnnaBridge 156:ff21514d8981 1482 * @}
AnnaBridge 156:ff21514d8981 1483 */
AnnaBridge 156:ff21514d8981 1484 /**************************************************************/
AnnaBridge 156:ff21514d8981 1485
AnnaBridge 156:ff21514d8981 1486 /**
AnnaBridge 156:ff21514d8981 1487 * @}
AnnaBridge 156:ff21514d8981 1488 */
AnnaBridge 156:ff21514d8981 1489
AnnaBridge 156:ff21514d8981 1490 /**
AnnaBridge 156:ff21514d8981 1491 * @}
AnnaBridge 156:ff21514d8981 1492 */
AnnaBridge 156:ff21514d8981 1493
AnnaBridge 156:ff21514d8981 1494 #ifdef __cplusplus
AnnaBridge 156:ff21514d8981 1495 }
AnnaBridge 156:ff21514d8981 1496 #endif
AnnaBridge 156:ff21514d8981 1497
AnnaBridge 156:ff21514d8981 1498 #endif /* __STM32L0xx_HAL_TIM_H */
AnnaBridge 156:ff21514d8981 1499
AnnaBridge 156:ff21514d8981 1500 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
AnnaBridge 156:ff21514d8981 1501