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Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

TARGET_NUCLEO_L152RE/stm32l1xx_hal_rcc_ex.h@122:f9eeca106725, 2016-07-07 (annotated)

Committer:
Kojto
Date:
Thu Jul 07 14:34:11 2016 +0100
Revision:
122:f9eeca106725
Parent:
90:cb3d968589d8 
Release 122 of the mbed library



Changes:

- new targets - Nucleo L432KC, Beetle, Nucleo F446ZE, Nucleo L011K4

- Thread safety addition - mbed API should contain a statement about thread safety

- critical section API addition

- CAS API (core_util_atomic_incr/decr)

- DEVICE_ are generated from targets.json file, device.h deprecated

- Callback replaces FunctionPointer to provide std like interface

- mbed HAL API docs improvements

- toolchain - prexif attributes with MBED_

            - add new attributes - packed, weak, forcedinline, align

- target.json - contains targets definitions

- ST - L1XX - Cube update to 1.5

     - SPI clock selection fix (clock from APB domain)

     - F7 - Cube update v1.4.0

     - L0 -  baudrate init fix

     - L1 - Cube update v1.5

     - F3 - baudrate init fix, 3 targets CAN support

     - F4 - Cube update v1.12.0, 3 targets CAN support

     - L4XX - Cube update v1.5.1

     - F0 - update Cube to v1.5.0

     - L4 - 2 targets (L476RG/VG) CAN support

- NXP - pwm clock fix for KSDK2 MCU

      - LPC2368 - remove ARM toolchain support - due to regression

      - KSDK2 - fix SPI , I2C address and repeat start

- Silabs - some fixes backported from mbed 3

- Renesas - RZ_A1H - SystemCoreClockUpdate addition

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 90:cb3d968589d8 1 /**
Kojto 90:cb3d968589d8 2 ******************************************************************************
Kojto 90:cb3d968589d8 3 * @file stm32l1xx_hal_rcc_ex.h
Kojto 90:cb3d968589d8 4 * @author MCD Application Team
Kojto 122:f9eeca106725 5 * @version V1.1.3
Kojto 122:f9eeca106725 6 * @date 04-March-2016
Kojto 90:cb3d968589d8 7 * @brief Header file of RCC HAL Extension module.
Kojto 90:cb3d968589d8 8 ******************************************************************************
Kojto 90:cb3d968589d8 9 * @attention
Kojto 90:cb3d968589d8 10 *
Kojto 122:f9eeca106725 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
Kojto 90:cb3d968589d8 12 *
Kojto 90:cb3d968589d8 13 * Redistribution and use in source and binary forms, with or without modification,
Kojto 90:cb3d968589d8 14 * are permitted provided that the following conditions are met:
Kojto 90:cb3d968589d8 15 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 90:cb3d968589d8 16 * this list of conditions and the following disclaimer.
Kojto 90:cb3d968589d8 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 90:cb3d968589d8 18 * this list of conditions and the following disclaimer in the documentation
Kojto 90:cb3d968589d8 19 * and/or other materials provided with the distribution.
Kojto 90:cb3d968589d8 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto 90:cb3d968589d8 21 * may be used to endorse or promote products derived from this software
Kojto 90:cb3d968589d8 22 * without specific prior written permission.
Kojto 90:cb3d968589d8 23 *
Kojto 90:cb3d968589d8 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 90:cb3d968589d8 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 90:cb3d968589d8 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 90:cb3d968589d8 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 90:cb3d968589d8 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 90:cb3d968589d8 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 90:cb3d968589d8 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 90:cb3d968589d8 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 90:cb3d968589d8 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 90:cb3d968589d8 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 90:cb3d968589d8 34 *
Kojto 90:cb3d968589d8 35 ******************************************************************************
Kojto 90:cb3d968589d8 36 */
Kojto 90:cb3d968589d8 37
Kojto 90:cb3d968589d8 38 /* Define to prevent recursive inclusion -------------------------------------*/
Kojto 90:cb3d968589d8 39 #ifndef __STM32L1xx_HAL_RCC_EX_H
Kojto 90:cb3d968589d8 40 #define __STM32L1xx_HAL_RCC_EX_H
Kojto 90:cb3d968589d8 41
Kojto 90:cb3d968589d8 42 #ifdef __cplusplus
Kojto 90:cb3d968589d8 43 extern "C" {
Kojto 90:cb3d968589d8 44 #endif
Kojto 90:cb3d968589d8 45
Kojto 90:cb3d968589d8 46 /* Includes ------------------------------------------------------------------*/
Kojto 90:cb3d968589d8 47 #include "stm32l1xx_hal_def.h"
Kojto 90:cb3d968589d8 48
Kojto 90:cb3d968589d8 49 /** @addtogroup STM32L1xx_HAL_Driver
Kojto 90:cb3d968589d8 50 * @{
Kojto 90:cb3d968589d8 51 */
Kojto 90:cb3d968589d8 52
Kojto 90:cb3d968589d8 53 /** @addtogroup RCCEx
Kojto 90:cb3d968589d8 54 * @{
Kojto 90:cb3d968589d8 55 */
Kojto 90:cb3d968589d8 56
Kojto 122:f9eeca106725 57 /** @addtogroup RCCEx_Private_Constants
Kojto 122:f9eeca106725 58 * @{
Kojto 122:f9eeca106725 59 */
Kojto 122:f9eeca106725 60
Kojto 122:f9eeca106725 61 #define LSI_VALUE ((uint32_t)37000) /* ~37kHz */
Kojto 122:f9eeca106725 62
Kojto 122:f9eeca106725 63 #if defined(STM32L100xBA) || defined(STM32L151xBA) || defined(STM32L152xBA)\
Kojto 122:f9eeca106725 64 || defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\
Kojto 122:f9eeca106725 65 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
Kojto 122:f9eeca106725 66 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
Kojto 122:f9eeca106725 67 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX)\
Kojto 122:f9eeca106725 68 || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
Kojto 122:f9eeca106725 69
Kojto 122:f9eeca106725 70 /* Alias word address of LSECSSON bit */
Kojto 122:f9eeca106725 71 #define LSECSSON_BITNUMBER POSITION_VAL(RCC_CSR_LSECSSON)
Kojto 122:f9eeca106725 72 #define CSR_LSECSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (LSECSSON_BITNUMBER * 4)))
Kojto 122:f9eeca106725 73
Kojto 122:f9eeca106725 74 #endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX*/
Kojto 122:f9eeca106725 75
Kojto 122:f9eeca106725 76 /**
Kojto 122:f9eeca106725 77 * @}
Kojto 122:f9eeca106725 78 */
Kojto 122:f9eeca106725 79
Kojto 122:f9eeca106725 80 /** @addtogroup RCCEx_Private_Macros
Kojto 122:f9eeca106725 81 * @{
Kojto 122:f9eeca106725 82 */
Kojto 122:f9eeca106725 83
Kojto 122:f9eeca106725 84 #if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\
Kojto 122:f9eeca106725 85 || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\
Kojto 122:f9eeca106725 86 || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\
Kojto 122:f9eeca106725 87 || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\
Kojto 122:f9eeca106725 88 || defined(STM32L162xE) || defined(STM32L162xDX)
Kojto 122:f9eeca106725 89
Kojto 122:f9eeca106725 90 #define IS_RCC_PERIPHCLOCK(__CLK__) ((RCC_PERIPHCLK_RTC <= (__CLK__)) && ((__CLK__) <= RCC_PERIPHCLK_LCD))
Kojto 122:f9eeca106725 91
Kojto 122:f9eeca106725 92 #else /* Not LCD LINE */
Kojto 122:f9eeca106725 93
Kojto 122:f9eeca106725 94 #define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) == RCC_PERIPHCLK_RTC)
Kojto 122:f9eeca106725 95
Kojto 122:f9eeca106725 96 #endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
Kojto 122:f9eeca106725 97
Kojto 122:f9eeca106725 98 /**
Kojto 122:f9eeca106725 99 * @}
Kojto 122:f9eeca106725 100 */
Kojto 122:f9eeca106725 101
Kojto 90:cb3d968589d8 102 /* Exported types ------------------------------------------------------------*/
Kojto 90:cb3d968589d8 103
Kojto 90:cb3d968589d8 104 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types
Kojto 90:cb3d968589d8 105 * @{
Kojto 90:cb3d968589d8 106 */
Kojto 90:cb3d968589d8 107
Kojto 90:cb3d968589d8 108 /**
Kojto 90:cb3d968589d8 109 * @brief RCC extended clocks structure definition
Kojto 90:cb3d968589d8 110 */
Kojto 90:cb3d968589d8 111 typedef struct
Kojto 90:cb3d968589d8 112 {
Kojto 90:cb3d968589d8 113 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto 90:cb3d968589d8 114 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto 90:cb3d968589d8 115
Kojto 90:cb3d968589d8 116 uint32_t RTCClockSelection; /*!< specifies the RTC clock source.
Kojto 90:cb3d968589d8 117 This parameter can be a value of @ref RCC_RTC_LCD_Clock_Source */
Kojto 90:cb3d968589d8 118
Kojto 122:f9eeca106725 119 #if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\
Kojto 122:f9eeca106725 120 || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\
Kojto 122:f9eeca106725 121 || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\
Kojto 122:f9eeca106725 122 || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\
Kojto 122:f9eeca106725 123 || defined(STM32L162xE) || defined(STM32L162xDX)
Kojto 90:cb3d968589d8 124
Kojto 90:cb3d968589d8 125 uint32_t LCDClockSelection; /*!< specifies the LCD clock source.
Kojto 90:cb3d968589d8 126 This parameter can be a value of @ref RCC_RTC_LCD_Clock_Source */
Kojto 90:cb3d968589d8 127
Kojto 122:f9eeca106725 128 #endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
Kojto 90:cb3d968589d8 129 } RCC_PeriphCLKInitTypeDef;
Kojto 90:cb3d968589d8 130
Kojto 90:cb3d968589d8 131 /**
Kojto 90:cb3d968589d8 132 * @}
Kojto 90:cb3d968589d8 133 */
Kojto 90:cb3d968589d8 134
Kojto 90:cb3d968589d8 135 /* Exported constants --------------------------------------------------------*/
Kojto 90:cb3d968589d8 136
Kojto 90:cb3d968589d8 137 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
Kojto 90:cb3d968589d8 138 * @{
Kojto 90:cb3d968589d8 139 */
Kojto 90:cb3d968589d8 140
Kojto 90:cb3d968589d8 141 /** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection
Kojto 90:cb3d968589d8 142 * @{
Kojto 90:cb3d968589d8 143 */
Kojto 90:cb3d968589d8 144 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000001)
Kojto 90:cb3d968589d8 145
Kojto 122:f9eeca106725 146 #if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\
Kojto 122:f9eeca106725 147 || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\
Kojto 122:f9eeca106725 148 || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\
Kojto 122:f9eeca106725 149 || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\
Kojto 122:f9eeca106725 150 || defined(STM32L162xE) || defined(STM32L162xDX)
Kojto 90:cb3d968589d8 151
Kojto 90:cb3d968589d8 152 #define RCC_PERIPHCLK_LCD ((uint32_t)0x00000002)
Kojto 90:cb3d968589d8 153
Kojto 122:f9eeca106725 154 #endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
Kojto 90:cb3d968589d8 155
Kojto 90:cb3d968589d8 156 /**
Kojto 90:cb3d968589d8 157 * @}
Kojto 90:cb3d968589d8 158 */
Kojto 90:cb3d968589d8 159
Kojto 122:f9eeca106725 160 #if defined(RCC_CSR_LSECSSON)
Kojto 122:f9eeca106725 161 /** @defgroup RCCEx_EXTI_LINE_LSECSS RCC LSE CSS external interrupt line
Kojto 122:f9eeca106725 162 * @{
Kojto 122:f9eeca106725 163 */
Kojto 122:f9eeca106725 164 #define RCC_EXTI_LINE_LSECSS (EXTI_IMR_MR19) /*!< External interrupt line 19 connected to the LSE CSS EXTI Line */
Kojto 122:f9eeca106725 165 /**
Kojto 122:f9eeca106725 166 * @}
Kojto 122:f9eeca106725 167 */
Kojto 122:f9eeca106725 168 #endif /* RCC_CSR_LSECSSON */
Kojto 90:cb3d968589d8 169
Kojto 90:cb3d968589d8 170
Kojto 90:cb3d968589d8 171 /**
Kojto 90:cb3d968589d8 172 * @}
Kojto 90:cb3d968589d8 173 */
Kojto 90:cb3d968589d8 174
Kojto 90:cb3d968589d8 175 /* Exported macro ------------------------------------------------------------*/
Kojto 90:cb3d968589d8 176 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
Kojto 90:cb3d968589d8 177 * @{
Kojto 90:cb3d968589d8 178 */
Kojto 90:cb3d968589d8 179
Kojto 90:cb3d968589d8 180 /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable
Kojto 90:cb3d968589d8 181 * @brief Enables or disables the AHB1 peripheral clock.
Kojto 90:cb3d968589d8 182 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 90:cb3d968589d8 183 * is disabled and the application software has to enable this clock before
Kojto 90:cb3d968589d8 184 * using it.
Kojto 90:cb3d968589d8 185 * @{
Kojto 90:cb3d968589d8 186 */
Kojto 122:f9eeca106725 187 #if defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L151xBA)\
Kojto 122:f9eeca106725 188 || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\
Kojto 122:f9eeca106725 189 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
Kojto 122:f9eeca106725 190 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
Kojto 122:f9eeca106725 191 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
Kojto 122:f9eeca106725 192 || defined(STM32L162xE) || defined(STM32L162xDX)
Kojto 90:cb3d968589d8 193
Kojto 122:f9eeca106725 194 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 195 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 196 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
Kojto 122:f9eeca106725 197 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 198 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
Kojto 122:f9eeca106725 199 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 200 } while(0)
Kojto 122:f9eeca106725 201 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
Kojto 122:f9eeca106725 202
Kojto 122:f9eeca106725 203 #endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
Kojto 90:cb3d968589d8 204
Kojto 122:f9eeca106725 205 #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
Kojto 122:f9eeca106725 206 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
Kojto 122:f9eeca106725 207 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
Kojto 90:cb3d968589d8 208
Kojto 122:f9eeca106725 209 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 210 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 211 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
Kojto 122:f9eeca106725 212 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 213 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
Kojto 122:f9eeca106725 214 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 215 } while(0)
Kojto 122:f9eeca106725 216 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 217 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 218 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOGEN);\
Kojto 122:f9eeca106725 219 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 220 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOGEN);\
Kojto 122:f9eeca106725 221 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 222 } while(0)
Kojto 90:cb3d968589d8 223
Kojto 122:f9eeca106725 224 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN))
Kojto 122:f9eeca106725 225 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOGEN))
Kojto 122:f9eeca106725 226
Kojto 122:f9eeca106725 227 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
Kojto 90:cb3d968589d8 228
Kojto 122:f9eeca106725 229 #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\
Kojto 122:f9eeca106725 230 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
Kojto 122:f9eeca106725 231 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
Kojto 122:f9eeca106725 232 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
Kojto 122:f9eeca106725 233 || defined(STM32L162xE) || defined(STM32L162xDX)
Kojto 122:f9eeca106725 234
Kojto 122:f9eeca106725 235 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 236 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 237 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
Kojto 122:f9eeca106725 238 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 239 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
Kojto 122:f9eeca106725 240 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 241 } while(0)
Kojto 90:cb3d968589d8 242
Kojto 122:f9eeca106725 243 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
Kojto 90:cb3d968589d8 244
Kojto 122:f9eeca106725 245 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
Kojto 122:f9eeca106725 246
Kojto 122:f9eeca106725 247 #if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD)\
Kojto 122:f9eeca106725 248 || defined(STM32L162xE) || defined(STM32L162xDX)
Kojto 90:cb3d968589d8 249
Kojto 122:f9eeca106725 250 #define __HAL_RCC_CRYP_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 251 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 252 SET_BIT(RCC->AHBENR, RCC_AHBENR_AESEN);\
Kojto 122:f9eeca106725 253 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 254 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_AESEN);\
Kojto 122:f9eeca106725 255 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 256 } while(0)
Kojto 122:f9eeca106725 257 #define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_AESEN))
Kojto 90:cb3d968589d8 258
Kojto 122:f9eeca106725 259 #endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */
Kojto 90:cb3d968589d8 260
Kojto 122:f9eeca106725 261 #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)
Kojto 90:cb3d968589d8 262
Kojto 122:f9eeca106725 263 #define __HAL_RCC_FSMC_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 264 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 265 SET_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\
Kojto 122:f9eeca106725 266 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 267 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\
Kojto 122:f9eeca106725 268 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 269 } while(0)
Kojto 122:f9eeca106725 270 #define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FSMCEN))
Kojto 90:cb3d968589d8 271
Kojto 90:cb3d968589d8 272 #endif /* STM32L151xD || STM32L152xD || STM32L162xD */
Kojto 90:cb3d968589d8 273
Kojto 122:f9eeca106725 274 #if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\
Kojto 122:f9eeca106725 275 || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\
Kojto 122:f9eeca106725 276 || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\
Kojto 122:f9eeca106725 277 || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\
Kojto 122:f9eeca106725 278 || defined(STM32L162xE) || defined(STM32L162xDX)
Kojto 90:cb3d968589d8 279
Kojto 122:f9eeca106725 280 #define __HAL_RCC_LCD_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 281 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 282 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LCDEN);\
Kojto 122:f9eeca106725 283 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 284 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LCDEN);\
Kojto 122:f9eeca106725 285 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 286 } while(0)
Kojto 122:f9eeca106725 287 #define __HAL_RCC_LCD_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LCDEN))
Kojto 90:cb3d968589d8 288
Kojto 122:f9eeca106725 289 #endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
Kojto 90:cb3d968589d8 290
Kojto 90:cb3d968589d8 291 /** @brief Enables or disables the Low Speed APB (APB1) peripheral clock.
Kojto 90:cb3d968589d8 292 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 90:cb3d968589d8 293 * is disabled and the application software has to enable this clock before
Kojto 90:cb3d968589d8 294 * using it.
Kojto 90:cb3d968589d8 295 */
Kojto 122:f9eeca106725 296 #if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\
Kojto 122:f9eeca106725 297 || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
Kojto 122:f9eeca106725 298 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
Kojto 122:f9eeca106725 299 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
Kojto 90:cb3d968589d8 300
Kojto 122:f9eeca106725 301 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 302 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 303 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
Kojto 122:f9eeca106725 304 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 305 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
Kojto 122:f9eeca106725 306 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 307 } while(0)
Kojto 122:f9eeca106725 308 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
Kojto 90:cb3d968589d8 309
Kojto 122:f9eeca106725 310 #endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
Kojto 90:cb3d968589d8 311
Kojto 122:f9eeca106725 312 #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\
Kojto 122:f9eeca106725 313 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
Kojto 122:f9eeca106725 314 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
Kojto 122:f9eeca106725 315 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
Kojto 122:f9eeca106725 316 || defined(STM32L162xE) || defined(STM32L162xDX)
Kojto 90:cb3d968589d8 317
Kojto 122:f9eeca106725 318 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 319 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 320 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
Kojto 122:f9eeca106725 321 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 322 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
Kojto 122:f9eeca106725 323 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 324 } while(0)
Kojto 122:f9eeca106725 325 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
Kojto 90:cb3d968589d8 326
Kojto 122:f9eeca106725 327 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
Kojto 90:cb3d968589d8 328
Kojto 122:f9eeca106725 329 #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\
Kojto 122:f9eeca106725 330 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
Kojto 90:cb3d968589d8 331
Kojto 122:f9eeca106725 332 #define __HAL_RCC_UART4_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 333 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 334 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
Kojto 122:f9eeca106725 335 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 336 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
Kojto 122:f9eeca106725 337 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 338 } while(0)
Kojto 122:f9eeca106725 339 #define __HAL_RCC_UART5_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 340 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 341 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
Kojto 122:f9eeca106725 342 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 343 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
Kojto 122:f9eeca106725 344 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 345 } while(0)
Kojto 90:cb3d968589d8 346
Kojto 122:f9eeca106725 347 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
Kojto 122:f9eeca106725 348 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
Kojto 122:f9eeca106725 349
Kojto 122:f9eeca106725 350 #endif /* STM32L151xD || STM32L152xD || STM32L162xD || (...) || STM32L152xDX || STM32L162xE || STM32L162xDX */
Kojto 122:f9eeca106725 351
Kojto 122:f9eeca106725 352 #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
Kojto 122:f9eeca106725 353 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
Kojto 122:f9eeca106725 354 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE)\
Kojto 122:f9eeca106725 355 || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\
Kojto 122:f9eeca106725 356 || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC)
Kojto 122:f9eeca106725 357
Kojto 122:f9eeca106725 358 #define __HAL_RCC_OPAMP_CLK_ENABLE() __HAL_RCC_COMP_CLK_ENABLE() /* Peripherals COMP and OPAMP share the same clock domain */
Kojto 122:f9eeca106725 359 #define __HAL_RCC_OPAMP_CLK_DISABLE() __HAL_RCC_COMP_CLK_DISABLE() /* Peripherals COMP and OPAMP share the same clock domain */
Kojto 90:cb3d968589d8 360
Kojto 122:f9eeca106725 361 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || (...) || STM32L162xC || STM32L152xC || STM32L151xC */
Kojto 90:cb3d968589d8 362
Kojto 90:cb3d968589d8 363 /** @brief Enables or disables the High Speed APB (APB2) peripheral clock.
Kojto 90:cb3d968589d8 364 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 90:cb3d968589d8 365 * is disabled and the application software has to enable this clock before
Kojto 90:cb3d968589d8 366 * using it.
Kojto 90:cb3d968589d8 367 */
Kojto 122:f9eeca106725 368 #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)
Kojto 90:cb3d968589d8 369
Kojto 122:f9eeca106725 370 #define __HAL_RCC_SDIO_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 371 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 372 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
Kojto 122:f9eeca106725 373 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 374 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
Kojto 122:f9eeca106725 375 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 376 } while(0)
Kojto 122:f9eeca106725 377 #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
Kojto 90:cb3d968589d8 378
Kojto 90:cb3d968589d8 379 #endif /* STM32L151xD || STM32L152xD || STM32L162xD */
Kojto 90:cb3d968589d8 380
Kojto 90:cb3d968589d8 381 /**
Kojto 90:cb3d968589d8 382 * @}
Kojto 90:cb3d968589d8 383 */
Kojto 90:cb3d968589d8 384
Kojto 90:cb3d968589d8 385
Kojto 90:cb3d968589d8 386 /** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset
Kojto 90:cb3d968589d8 387 * @brief Forces or releases AHB peripheral reset.
Kojto 90:cb3d968589d8 388 * @{
Kojto 90:cb3d968589d8 389 */
Kojto 122:f9eeca106725 390 #if defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L151xBA)\
Kojto 122:f9eeca106725 391 || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\
Kojto 122:f9eeca106725 392 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
Kojto 122:f9eeca106725 393 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
Kojto 122:f9eeca106725 394 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
Kojto 122:f9eeca106725 395 || defined(STM32L162xE) || defined(STM32L162xDX)
Kojto 90:cb3d968589d8 396
Kojto 122:f9eeca106725 397 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST))
Kojto 122:f9eeca106725 398 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))
Kojto 122:f9eeca106725 399
Kojto 122:f9eeca106725 400 #endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
Kojto 90:cb3d968589d8 401
Kojto 122:f9eeca106725 402 #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
Kojto 122:f9eeca106725 403 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
Kojto 122:f9eeca106725 404 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
Kojto 90:cb3d968589d8 405
Kojto 122:f9eeca106725 406 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOFRST))
Kojto 122:f9eeca106725 407 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOGRST))
Kojto 90:cb3d968589d8 408
Kojto 122:f9eeca106725 409 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST))
Kojto 122:f9eeca106725 410 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOGRST))
Kojto 122:f9eeca106725 411
Kojto 122:f9eeca106725 412 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
Kojto 90:cb3d968589d8 413
Kojto 122:f9eeca106725 414 #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\
Kojto 122:f9eeca106725 415 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
Kojto 122:f9eeca106725 416 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
Kojto 122:f9eeca106725 417 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
Kojto 122:f9eeca106725 418 || defined(STM32L162xE) || defined(STM32L162xDX)
Kojto 122:f9eeca106725 419
Kojto 122:f9eeca106725 420 #define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_DMA2RST))
Kojto 122:f9eeca106725 421 #define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_DMA2RST))
Kojto 90:cb3d968589d8 422
Kojto 122:f9eeca106725 423 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
Kojto 90:cb3d968589d8 424
Kojto 122:f9eeca106725 425 #if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD)\
Kojto 122:f9eeca106725 426 || defined(STM32L162xE) || defined(STM32L162xDX)
Kojto 90:cb3d968589d8 427
Kojto 122:f9eeca106725 428 #define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_AESRST))
Kojto 122:f9eeca106725 429 #define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_AESRST))
Kojto 90:cb3d968589d8 430
Kojto 122:f9eeca106725 431 #endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */
Kojto 90:cb3d968589d8 432
Kojto 122:f9eeca106725 433 #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)
Kojto 90:cb3d968589d8 434
Kojto 122:f9eeca106725 435 #define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_FSMCRST))
Kojto 122:f9eeca106725 436 #define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_FSMCRST))
Kojto 90:cb3d968589d8 437
Kojto 90:cb3d968589d8 438 #endif /* STM32L151xD || STM32L152xD || STM32L162xD */
Kojto 90:cb3d968589d8 439
Kojto 122:f9eeca106725 440 #if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\
Kojto 122:f9eeca106725 441 || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\
Kojto 122:f9eeca106725 442 || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\
Kojto 122:f9eeca106725 443 || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\
Kojto 122:f9eeca106725 444 || defined(STM32L162xE) || defined(STM32L162xDX)
Kojto 90:cb3d968589d8 445
Kojto 122:f9eeca106725 446 #define __HAL_RCC_LCD_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LCDRST))
Kojto 122:f9eeca106725 447 #define __HAL_RCC_LCD_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LCDRST))
Kojto 90:cb3d968589d8 448
Kojto 122:f9eeca106725 449 #endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
Kojto 90:cb3d968589d8 450
Kojto 90:cb3d968589d8 451 /** @brief Forces or releases APB1 peripheral reset.
Kojto 90:cb3d968589d8 452 */
Kojto 122:f9eeca106725 453 #if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\
Kojto 122:f9eeca106725 454 || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
Kojto 122:f9eeca106725 455 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
Kojto 122:f9eeca106725 456 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
Kojto 90:cb3d968589d8 457
Kojto 122:f9eeca106725 458 #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
Kojto 122:f9eeca106725 459 #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
Kojto 90:cb3d968589d8 460
Kojto 122:f9eeca106725 461 #endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
Kojto 90:cb3d968589d8 462
Kojto 122:f9eeca106725 463 #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\
Kojto 122:f9eeca106725 464 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
Kojto 122:f9eeca106725 465 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
Kojto 122:f9eeca106725 466 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
Kojto 122:f9eeca106725 467 || defined(STM32L162xE) || defined(STM32L162xDX)
Kojto 90:cb3d968589d8 468
Kojto 122:f9eeca106725 469 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
Kojto 122:f9eeca106725 470 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
Kojto 90:cb3d968589d8 471
Kojto 122:f9eeca106725 472 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
Kojto 90:cb3d968589d8 473
Kojto 122:f9eeca106725 474 #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\
Kojto 122:f9eeca106725 475 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
Kojto 90:cb3d968589d8 476
Kojto 122:f9eeca106725 477 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
Kojto 122:f9eeca106725 478 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
Kojto 90:cb3d968589d8 479
Kojto 122:f9eeca106725 480 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
Kojto 122:f9eeca106725 481 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
Kojto 90:cb3d968589d8 482
Kojto 122:f9eeca106725 483 #endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
Kojto 90:cb3d968589d8 484
Kojto 122:f9eeca106725 485 #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
Kojto 122:f9eeca106725 486 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
Kojto 122:f9eeca106725 487 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\
Kojto 122:f9eeca106725 488 || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC)
Kojto 122:f9eeca106725 489
Kojto 122:f9eeca106725 490 #define __HAL_RCC_OPAMP_FORCE_RESET() __HAL_RCC_COMP_FORCE_RESET() /* Peripherals COMP and OPAMP share the same clock domain */
Kojto 122:f9eeca106725 491 #define __HAL_RCC_OPAMP_RELEASE_RESET() __HAL_RCC_COMP_RELEASE_RESET() /* Peripherals COMP and OPAMP share the same clock domain */
Kojto 90:cb3d968589d8 492
Kojto 122:f9eeca106725 493 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */
Kojto 90:cb3d968589d8 494
Kojto 90:cb3d968589d8 495 /** @brief Forces or releases APB2 peripheral reset.
Kojto 90:cb3d968589d8 496 */
Kojto 122:f9eeca106725 497 #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)
Kojto 90:cb3d968589d8 498
Kojto 122:f9eeca106725 499 #define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
Kojto 122:f9eeca106725 500 #define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
Kojto 90:cb3d968589d8 501
Kojto 90:cb3d968589d8 502 #endif /* STM32L151xD || STM32L152xD || STM32L162xD */
Kojto 90:cb3d968589d8 503
Kojto 90:cb3d968589d8 504 /**
Kojto 90:cb3d968589d8 505 * @}
Kojto 90:cb3d968589d8 506 */
Kojto 90:cb3d968589d8 507
Kojto 90:cb3d968589d8 508 /** @defgroup RCCEx_Peripheral_Clock_Sleep_Enable_Disable RCCEx Peripheral Clock Sleep Enable Disable
Kojto 90:cb3d968589d8 509 * @brief Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode.
Kojto 90:cb3d968589d8 510 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 90:cb3d968589d8 511 * power consumption.
Kojto 90:cb3d968589d8 512 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 90:cb3d968589d8 513 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 90:cb3d968589d8 514 * @{
Kojto 90:cb3d968589d8 515 */
Kojto 122:f9eeca106725 516 #if defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L151xBA)\
Kojto 122:f9eeca106725 517 || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\
Kojto 122:f9eeca106725 518 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
Kojto 122:f9eeca106725 519 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
Kojto 122:f9eeca106725 520 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
Kojto 122:f9eeca106725 521 || defined(STM32L162xE) || defined(STM32L162xDX)
Kojto 90:cb3d968589d8 522
Kojto 122:f9eeca106725 523 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOELPEN))
Kojto 122:f9eeca106725 524 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOELPEN))
Kojto 90:cb3d968589d8 525
Kojto 122:f9eeca106725 526 #endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
Kojto 90:cb3d968589d8 527
Kojto 122:f9eeca106725 528 #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
Kojto 122:f9eeca106725 529 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
Kojto 122:f9eeca106725 530 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
Kojto 90:cb3d968589d8 531
Kojto 122:f9eeca106725 532 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOFLPEN))
Kojto 122:f9eeca106725 533 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOGLPEN))
Kojto 90:cb3d968589d8 534
Kojto 122:f9eeca106725 535 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOFLPEN))
Kojto 122:f9eeca106725 536 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOGLPEN))
Kojto 90:cb3d968589d8 537
Kojto 122:f9eeca106725 538 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
Kojto 90:cb3d968589d8 539
Kojto 122:f9eeca106725 540 #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\
Kojto 122:f9eeca106725 541 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
Kojto 122:f9eeca106725 542 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
Kojto 122:f9eeca106725 543 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
Kojto 122:f9eeca106725 544 || defined(STM32L162xE) || defined(STM32L162xDX)
Kojto 90:cb3d968589d8 545
Kojto 122:f9eeca106725 546 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_DMA2LPEN))
Kojto 122:f9eeca106725 547 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_DMA2LPEN))
Kojto 90:cb3d968589d8 548
Kojto 122:f9eeca106725 549 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
Kojto 90:cb3d968589d8 550
Kojto 122:f9eeca106725 551 #if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE) || defined(STM32L162xDX)
Kojto 122:f9eeca106725 552
Kojto 122:f9eeca106725 553 #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_AESLPEN))
Kojto 122:f9eeca106725 554 #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_AESLPEN))
Kojto 90:cb3d968589d8 555
Kojto 122:f9eeca106725 556 #endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */
Kojto 90:cb3d968589d8 557
Kojto 122:f9eeca106725 558 #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)
Kojto 90:cb3d968589d8 559
Kojto 122:f9eeca106725 560 #define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_FSMCLPEN))
Kojto 122:f9eeca106725 561 #define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_FSMCLPEN))
Kojto 90:cb3d968589d8 562
Kojto 90:cb3d968589d8 563 #endif /* STM32L151xD || STM32L152xD || STM32L162xD */
Kojto 90:cb3d968589d8 564
Kojto 122:f9eeca106725 565 #if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\
Kojto 122:f9eeca106725 566 || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\
Kojto 122:f9eeca106725 567 || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\
Kojto 122:f9eeca106725 568 || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\
Kojto 122:f9eeca106725 569 || defined(STM32L162xE) || defined(STM32L162xDX)
Kojto 90:cb3d968589d8 570
Kojto 122:f9eeca106725 571 #define __HAL_RCC_LCD_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LCDLPEN))
Kojto 122:f9eeca106725 572 #define __HAL_RCC_LCD_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LCDLPEN))
Kojto 90:cb3d968589d8 573
Kojto 122:f9eeca106725 574 #endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
Kojto 90:cb3d968589d8 575
Kojto 90:cb3d968589d8 576 /** @brief Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode.
Kojto 90:cb3d968589d8 577 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 90:cb3d968589d8 578 * power consumption.
Kojto 90:cb3d968589d8 579 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 90:cb3d968589d8 580 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 90:cb3d968589d8 581 */
Kojto 122:f9eeca106725 582 #if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\
Kojto 122:f9eeca106725 583 || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
Kojto 122:f9eeca106725 584 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
Kojto 122:f9eeca106725 585 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
Kojto 122:f9eeca106725 586
Kojto 122:f9eeca106725 587 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))
Kojto 122:f9eeca106725 588 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
Kojto 122:f9eeca106725 589
Kojto 122:f9eeca106725 590 #endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
Kojto 90:cb3d968589d8 591
Kojto 122:f9eeca106725 592 #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\
Kojto 122:f9eeca106725 593 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
Kojto 122:f9eeca106725 594 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
Kojto 122:f9eeca106725 595 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
Kojto 122:f9eeca106725 596 || defined(STM32L162xE) || defined(STM32L162xDX)
Kojto 90:cb3d968589d8 597
Kojto 122:f9eeca106725 598 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
Kojto 122:f9eeca106725 599 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
Kojto 90:cb3d968589d8 600
Kojto 122:f9eeca106725 601 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
Kojto 90:cb3d968589d8 602
Kojto 122:f9eeca106725 603 #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\
Kojto 122:f9eeca106725 604 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
Kojto 90:cb3d968589d8 605
Kojto 122:f9eeca106725 606 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
Kojto 122:f9eeca106725 607 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
Kojto 90:cb3d968589d8 608
Kojto 122:f9eeca106725 609 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
Kojto 122:f9eeca106725 610 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
Kojto 90:cb3d968589d8 611
Kojto 122:f9eeca106725 612 #endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
Kojto 90:cb3d968589d8 613
Kojto 122:f9eeca106725 614 #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
Kojto 122:f9eeca106725 615 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
Kojto 122:f9eeca106725 616 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\
Kojto 122:f9eeca106725 617 || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC)
Kojto 90:cb3d968589d8 618
Kojto 122:f9eeca106725 619 #define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() __HAL_RCC_COMP_CLK_SLEEP_ENABLE() /* Peripherals COMP and OPAMP share the same clock domain */
Kojto 122:f9eeca106725 620 #define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() __HAL_RCC_COMP_CLK_SLEEP_DISABLE() /* Peripherals COMP and OPAMP share the same clock domain */
Kojto 122:f9eeca106725 621
Kojto 122:f9eeca106725 622 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */
Kojto 90:cb3d968589d8 623
Kojto 90:cb3d968589d8 624 /** @brief Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode.
Kojto 90:cb3d968589d8 625 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 90:cb3d968589d8 626 * power consumption.
Kojto 90:cb3d968589d8 627 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 90:cb3d968589d8 628 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 90:cb3d968589d8 629 */
Kojto 122:f9eeca106725 630 #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)
Kojto 122:f9eeca106725 631
Kojto 122:f9eeca106725 632 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
Kojto 122:f9eeca106725 633 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
Kojto 122:f9eeca106725 634
Kojto 122:f9eeca106725 635 #endif /* STM32L151xD || STM32L152xD || STM32L162xD */
Kojto 122:f9eeca106725 636
Kojto 122:f9eeca106725 637 /**
Kojto 122:f9eeca106725 638 * @}
Kojto 122:f9eeca106725 639 */
Kojto 122:f9eeca106725 640
Kojto 122:f9eeca106725 641 /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable_Status Peripheral Clock Enable Disable Status
Kojto 122:f9eeca106725 642 * @brief Get the enable or disable status of peripheral clock.
Kojto 122:f9eeca106725 643 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 122:f9eeca106725 644 * is disabled and the application software has to enable this clock before
Kojto 122:f9eeca106725 645 * using it.
Kojto 122:f9eeca106725 646 * @{
Kojto 122:f9eeca106725 647 */
Kojto 122:f9eeca106725 648
Kojto 122:f9eeca106725 649 #if defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L151xBA)\
Kojto 122:f9eeca106725 650 || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\
Kojto 122:f9eeca106725 651 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
Kojto 122:f9eeca106725 652 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
Kojto 122:f9eeca106725 653 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
Kojto 122:f9eeca106725 654 || defined(STM32L162xE) || defined(STM32L162xDX)
Kojto 122:f9eeca106725 655
Kojto 122:f9eeca106725 656 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) != RESET)
Kojto 122:f9eeca106725 657 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) == RESET)
Kojto 122:f9eeca106725 658
Kojto 122:f9eeca106725 659 #endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
Kojto 122:f9eeca106725 660
Kojto 122:f9eeca106725 661 #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
Kojto 122:f9eeca106725 662 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
Kojto 122:f9eeca106725 663 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
Kojto 122:f9eeca106725 664
Kojto 122:f9eeca106725 665 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) != RESET)
Kojto 122:f9eeca106725 666 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOGEN)) != RESET)
Kojto 122:f9eeca106725 667 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) == RESET)
Kojto 122:f9eeca106725 668 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOGEN)) == RESET)
Kojto 122:f9eeca106725 669
Kojto 122:f9eeca106725 670 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
Kojto 122:f9eeca106725 671
Kojto 122:f9eeca106725 672 #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\
Kojto 122:f9eeca106725 673 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
Kojto 122:f9eeca106725 674 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
Kojto 122:f9eeca106725 675 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
Kojto 122:f9eeca106725 676 || defined(STM32L162xE) || defined(STM32L162xDX)
Kojto 122:f9eeca106725 677
Kojto 122:f9eeca106725 678 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET)
Kojto 122:f9eeca106725 679 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET)
Kojto 122:f9eeca106725 680
Kojto 122:f9eeca106725 681 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
Kojto 122:f9eeca106725 682
Kojto 122:f9eeca106725 683 #if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD)\
Kojto 122:f9eeca106725 684 || defined(STM32L162xE) || defined(STM32L162xDX)
Kojto 122:f9eeca106725 685
Kojto 122:f9eeca106725 686 #define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_AESEN)) != RESET)
Kojto 122:f9eeca106725 687 #define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_AESEN)) == RESET)
Kojto 122:f9eeca106725 688
Kojto 122:f9eeca106725 689 #endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */
Kojto 90:cb3d968589d8 690
Kojto 122:f9eeca106725 691 #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)
Kojto 122:f9eeca106725 692
Kojto 122:f9eeca106725 693 #define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) != RESET)
Kojto 122:f9eeca106725 694 #define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) == RESET)
Kojto 122:f9eeca106725 695
Kojto 122:f9eeca106725 696 #endif /* STM32L151xD || STM32L152xD || STM32L162xD */
Kojto 122:f9eeca106725 697
Kojto 122:f9eeca106725 698 #if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\
Kojto 122:f9eeca106725 699 || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\
Kojto 122:f9eeca106725 700 || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\
Kojto 122:f9eeca106725 701 || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\
Kojto 122:f9eeca106725 702 || defined(STM32L162xE) || defined(STM32L162xDX)
Kojto 122:f9eeca106725 703
Kojto 122:f9eeca106725 704 #define __HAL_RCC_LCD_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LCDEN)) != RESET)
Kojto 122:f9eeca106725 705 #define __HAL_RCC_LCD_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LCDEN)) == RESET)
Kojto 122:f9eeca106725 706
Kojto 122:f9eeca106725 707 #endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
Kojto 122:f9eeca106725 708
Kojto 122:f9eeca106725 709 #if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\
Kojto 122:f9eeca106725 710 || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
Kojto 122:f9eeca106725 711 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
Kojto 122:f9eeca106725 712 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
Kojto 122:f9eeca106725 713
Kojto 122:f9eeca106725 714 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
Kojto 122:f9eeca106725 715 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
Kojto 122:f9eeca106725 716
Kojto 122:f9eeca106725 717 #endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
Kojto 122:f9eeca106725 718
Kojto 122:f9eeca106725 719 #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\
Kojto 122:f9eeca106725 720 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
Kojto 122:f9eeca106725 721 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
Kojto 122:f9eeca106725 722 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
Kojto 122:f9eeca106725 723 || defined(STM32L162xE) || defined(STM32L162xDX)
Kojto 122:f9eeca106725 724
Kojto 122:f9eeca106725 725 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
Kojto 122:f9eeca106725 726 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
Kojto 122:f9eeca106725 727
Kojto 122:f9eeca106725 728 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
Kojto 122:f9eeca106725 729
Kojto 122:f9eeca106725 730 #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\
Kojto 122:f9eeca106725 731 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
Kojto 122:f9eeca106725 732
Kojto 122:f9eeca106725 733 #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
Kojto 122:f9eeca106725 734 #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
Kojto 122:f9eeca106725 735 #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
Kojto 122:f9eeca106725 736 #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
Kojto 122:f9eeca106725 737
Kojto 122:f9eeca106725 738 #endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
Kojto 122:f9eeca106725 739
Kojto 122:f9eeca106725 740 #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
Kojto 122:f9eeca106725 741 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
Kojto 122:f9eeca106725 742 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\
Kojto 122:f9eeca106725 743 || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC)
Kojto 122:f9eeca106725 744
Kojto 122:f9eeca106725 745 #define __HAL_RCC_OPAMP_IS_CLK_ENABLED() __HAL_RCC_COMP_IS_CLK_ENABLED()
Kojto 122:f9eeca106725 746 #define __HAL_RCC_OPAMP_IS_CLK_DISABLED() __HAL_RCC_COMP_IS_CLK_DISABLED()
Kojto 122:f9eeca106725 747
Kojto 122:f9eeca106725 748 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */
Kojto 122:f9eeca106725 749
Kojto 122:f9eeca106725 750 #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)
Kojto 122:f9eeca106725 751
Kojto 122:f9eeca106725 752 #define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
Kojto 122:f9eeca106725 753 #define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
Kojto 90:cb3d968589d8 754
Kojto 90:cb3d968589d8 755 #endif /* STM32L151xD || STM32L152xD || STM32L162xD */
Kojto 90:cb3d968589d8 756
Kojto 90:cb3d968589d8 757 /**
Kojto 90:cb3d968589d8 758 * @}
Kojto 90:cb3d968589d8 759 */
Kojto 90:cb3d968589d8 760
Kojto 122:f9eeca106725 761 /** @defgroup RCCEx_Peripheral_Clock_Sleep_Enable_Disable_Status Peripheral Clock Sleep Enable Disable Status
Kojto 122:f9eeca106725 762 * @brief Get the enable or disable status of peripheral clock during Low Power (Sleep) mode.
Kojto 122:f9eeca106725 763 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 122:f9eeca106725 764 * power consumption.
Kojto 122:f9eeca106725 765 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 122:f9eeca106725 766 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 122:f9eeca106725 767 * @{
Kojto 122:f9eeca106725 768 */
Kojto 122:f9eeca106725 769
Kojto 122:f9eeca106725 770 #if defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L151xBA)\
Kojto 122:f9eeca106725 771 || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\
Kojto 122:f9eeca106725 772 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
Kojto 122:f9eeca106725 773 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
Kojto 122:f9eeca106725 774 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
Kojto 122:f9eeca106725 775 || defined(STM32L162xE) || defined(STM32L162xDX)
Kojto 122:f9eeca106725 776
Kojto 122:f9eeca106725 777 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOELPEN)) != RESET)
Kojto 122:f9eeca106725 778 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOELPEN)) == RESET)
Kojto 122:f9eeca106725 779
Kojto 122:f9eeca106725 780 #endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
Kojto 122:f9eeca106725 781
Kojto 122:f9eeca106725 782 #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
Kojto 122:f9eeca106725 783 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
Kojto 122:f9eeca106725 784 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
Kojto 122:f9eeca106725 785
Kojto 122:f9eeca106725 786 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOFLPEN)) != RESET)
Kojto 122:f9eeca106725 787 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOGLPEN)) != RESET)
Kojto 122:f9eeca106725 788 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOFLPEN)) == RESET)
Kojto 122:f9eeca106725 789 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOGLPEN)) == RESET)
Kojto 122:f9eeca106725 790
Kojto 122:f9eeca106725 791 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
Kojto 122:f9eeca106725 792
Kojto 122:f9eeca106725 793 #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\
Kojto 122:f9eeca106725 794 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
Kojto 122:f9eeca106725 795 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
Kojto 122:f9eeca106725 796 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
Kojto 122:f9eeca106725 797 || defined(STM32L162xE) || defined(STM32L162xDX)
Kojto 122:f9eeca106725 798
Kojto 122:f9eeca106725 799 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_DMA2LPEN)) != RESET)
Kojto 122:f9eeca106725 800 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_DMA2LPEN)) == RESET)
Kojto 122:f9eeca106725 801
Kojto 122:f9eeca106725 802 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
Kojto 122:f9eeca106725 803
Kojto 122:f9eeca106725 804 #if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD)\
Kojto 122:f9eeca106725 805 || defined(STM32L162xE) || defined(STM32L162xDX)
Kojto 122:f9eeca106725 806
Kojto 122:f9eeca106725 807 #define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_AESLPEN)) != RESET)
Kojto 122:f9eeca106725 808 #define __HAL_RCC_CRYP_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_AESLPEN)) == RESET)
Kojto 122:f9eeca106725 809
Kojto 122:f9eeca106725 810 #endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */
Kojto 122:f9eeca106725 811
Kojto 122:f9eeca106725 812 #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)
Kojto 122:f9eeca106725 813
Kojto 122:f9eeca106725 814 #define __HAL_RCC_FSMC_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_FSMCLPEN)) != RESET)
Kojto 122:f9eeca106725 815 #define __HAL_RCC_FSMC_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_FSMCLPEN)) == RESET)
Kojto 122:f9eeca106725 816
Kojto 122:f9eeca106725 817 #endif /* STM32L151xD || STM32L152xD || STM32L162xD */
Kojto 122:f9eeca106725 818
Kojto 122:f9eeca106725 819 #if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\
Kojto 122:f9eeca106725 820 || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\
Kojto 122:f9eeca106725 821 || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\
Kojto 122:f9eeca106725 822 || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\
Kojto 122:f9eeca106725 823 || defined(STM32L162xE) || defined(STM32L162xDX)
Kojto 90:cb3d968589d8 824
Kojto 122:f9eeca106725 825 #define __HAL_RCC_LCD_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LCDLPEN)) != RESET)
Kojto 122:f9eeca106725 826 #define __HAL_RCC_LCD_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LCDLPEN)) == RESET)
Kojto 122:f9eeca106725 827
Kojto 122:f9eeca106725 828 #endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
Kojto 122:f9eeca106725 829
Kojto 122:f9eeca106725 830 #if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\
Kojto 122:f9eeca106725 831 || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
Kojto 122:f9eeca106725 832 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
Kojto 122:f9eeca106725 833 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
Kojto 122:f9eeca106725 834
Kojto 122:f9eeca106725 835 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) != RESET)
Kojto 122:f9eeca106725 836 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) == RESET)
Kojto 122:f9eeca106725 837
Kojto 122:f9eeca106725 838 #endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
Kojto 122:f9eeca106725 839
Kojto 122:f9eeca106725 840 #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\
Kojto 122:f9eeca106725 841 || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\
Kojto 122:f9eeca106725 842 || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\
Kojto 122:f9eeca106725 843 || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\
Kojto 122:f9eeca106725 844 || defined(STM32L162xE) || defined(STM32L162xDX)
Kojto 122:f9eeca106725 845
Kojto 122:f9eeca106725 846 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) != RESET)
Kojto 122:f9eeca106725 847 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) == RESET)
Kojto 122:f9eeca106725 848
Kojto 122:f9eeca106725 849 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
Kojto 122:f9eeca106725 850
Kojto 122:f9eeca106725 851 #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\
Kojto 122:f9eeca106725 852 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)
Kojto 122:f9eeca106725 853
Kojto 122:f9eeca106725 854 #define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) != RESET)
Kojto 122:f9eeca106725 855 #define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) != RESET)
Kojto 122:f9eeca106725 856 #define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) == RESET)
Kojto 122:f9eeca106725 857 #define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) == RESET)
Kojto 122:f9eeca106725 858
Kojto 122:f9eeca106725 859 #endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
Kojto 122:f9eeca106725 860
Kojto 122:f9eeca106725 861 #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\
Kojto 122:f9eeca106725 862 || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\
Kojto 122:f9eeca106725 863 || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\
Kojto 122:f9eeca106725 864 || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC)
Kojto 122:f9eeca106725 865
Kojto 122:f9eeca106725 866 #define __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED() __HAL_RCC_COMP_IS_CLK_SLEEP_ENABLED()
Kojto 122:f9eeca106725 867 #define __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED() __HAL_RCC_COMP_IS_CLK_SLEEP_DISABLED()
Kojto 122:f9eeca106725 868
Kojto 122:f9eeca106725 869 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */
Kojto 122:f9eeca106725 870
Kojto 122:f9eeca106725 871 #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)
Kojto 122:f9eeca106725 872
Kojto 122:f9eeca106725 873 #define __HAL_RCC_SDIO_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDIOLPEN)) != RESET)
Kojto 122:f9eeca106725 874 #define __HAL_RCC_SDIO_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDIOLPEN)) == RESET)
Kojto 122:f9eeca106725 875
Kojto 122:f9eeca106725 876 #endif /* STM32L151xD || STM32L152xD || STM32L162xD */
Kojto 122:f9eeca106725 877
Kojto 122:f9eeca106725 878 /**
Kojto 122:f9eeca106725 879 * @}
Kojto 122:f9eeca106725 880 */
Kojto 122:f9eeca106725 881
Kojto 122:f9eeca106725 882
Kojto 122:f9eeca106725 883 #if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\
Kojto 122:f9eeca106725 884 || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\
Kojto 122:f9eeca106725 885 || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\
Kojto 122:f9eeca106725 886 || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\
Kojto 122:f9eeca106725 887 || defined(STM32L162xE) || defined(STM32L162xDX)
Kojto 122:f9eeca106725 888
Kojto 122:f9eeca106725 889 /** @defgroup RCCEx_LCD_Configuration LCd Configuration
Kojto 122:f9eeca106725 890 * @brief Macros to configure clock source of LCD peripherals.
Kojto 122:f9eeca106725 891 * @{
Kojto 122:f9eeca106725 892 */
Kojto 90:cb3d968589d8 893
Kojto 90:cb3d968589d8 894 /** @brief Macro to configures LCD clock (LCDCLK).
Kojto 90:cb3d968589d8 895 * @note LCD and RTC use the same configuration
Kojto 90:cb3d968589d8 896 * @note LCD can however be used in the Stop low power mode if the LSE or LSI is used as the
Kojto 90:cb3d968589d8 897 * LCD clock source.
Kojto 90:cb3d968589d8 898 *
Kojto 122:f9eeca106725 899 * @param __LCD_CLKSOURCE__ specifies the LCD clock source.
Kojto 90:cb3d968589d8 900 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 901 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
Kojto 122:f9eeca106725 902 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
Kojto 122:f9eeca106725 903 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV2 HSE divided by 2 selected as RTC clock
Kojto 122:f9eeca106725 904 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV4 HSE divided by 4 selected as RTC clock
Kojto 122:f9eeca106725 905 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV8 HSE divided by 8 selected as RTC clock
Kojto 122:f9eeca106725 906 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV16 HSE divided by 16 selected as RTC clock
Kojto 90:cb3d968589d8 907 */
Kojto 90:cb3d968589d8 908 #define __HAL_RCC_LCD_CONFIG(__LCD_CLKSOURCE__) __HAL_RCC_RTC_CONFIG(__LCD_CLKSOURCE__)
Kojto 90:cb3d968589d8 909
Kojto 90:cb3d968589d8 910 /** @brief macros to get the LCD clock source.
Kojto 90:cb3d968589d8 911 */
Kojto 90:cb3d968589d8 912 #define __HAL_RCC_GET_LCD_SOURCE() __HAL_RCC_GET_RTC_SOURCE()
Kojto 90:cb3d968589d8 913
Kojto 122:f9eeca106725 914 /**
Kojto 122:f9eeca106725 915 * @}
Kojto 122:f9eeca106725 916 */
Kojto 122:f9eeca106725 917
Kojto 122:f9eeca106725 918 #endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
Kojto 122:f9eeca106725 919
Kojto 122:f9eeca106725 920 #if defined(RCC_CSR_LSECSSON)
Kojto 122:f9eeca106725 921
Kojto 122:f9eeca106725 922 /**
Kojto 122:f9eeca106725 923 * @brief Enable interrupt on RCC LSE CSS EXTI Line 19.
Kojto 122:f9eeca106725 924 * @retval None
Kojto 122:f9eeca106725 925 */
Kojto 122:f9eeca106725 926 #define __HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, RCC_EXTI_LINE_LSECSS)
Kojto 122:f9eeca106725 927
Kojto 122:f9eeca106725 928 /**
Kojto 122:f9eeca106725 929 * @brief Disable interrupt on RCC LSE CSS EXTI Line 19.
Kojto 122:f9eeca106725 930 * @retval None
Kojto 122:f9eeca106725 931 */
Kojto 122:f9eeca106725 932 #define __HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, RCC_EXTI_LINE_LSECSS)
Kojto 122:f9eeca106725 933
Kojto 122:f9eeca106725 934 /**
Kojto 122:f9eeca106725 935 * @brief Enable event on RCC LSE CSS EXTI Line 19.
Kojto 122:f9eeca106725 936 * @retval None.
Kojto 122:f9eeca106725 937 */
Kojto 122:f9eeca106725 938 #define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, RCC_EXTI_LINE_LSECSS)
Kojto 122:f9eeca106725 939
Kojto 122:f9eeca106725 940 /**
Kojto 122:f9eeca106725 941 * @brief Disable event on RCC LSE CSS EXTI Line 19.
Kojto 122:f9eeca106725 942 * @retval None.
Kojto 122:f9eeca106725 943 */
Kojto 122:f9eeca106725 944 #define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, RCC_EXTI_LINE_LSECSS)
Kojto 122:f9eeca106725 945
Kojto 122:f9eeca106725 946
Kojto 122:f9eeca106725 947 /**
Kojto 122:f9eeca106725 948 * @brief RCC LSE CSS EXTI line configuration: set falling edge trigger.
Kojto 122:f9eeca106725 949 * @retval None.
Kojto 122:f9eeca106725 950 */
Kojto 122:f9eeca106725 951 #define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, RCC_EXTI_LINE_LSECSS)
Kojto 122:f9eeca106725 952
Kojto 122:f9eeca106725 953
Kojto 122:f9eeca106725 954 /**
Kojto 122:f9eeca106725 955 * @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger.
Kojto 122:f9eeca106725 956 * @retval None.
Kojto 122:f9eeca106725 957 */
Kojto 122:f9eeca106725 958 #define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, RCC_EXTI_LINE_LSECSS)
Kojto 122:f9eeca106725 959
Kojto 122:f9eeca106725 960
Kojto 122:f9eeca106725 961 /**
Kojto 122:f9eeca106725 962 * @brief RCC LSE CSS EXTI line configuration: set rising edge trigger.
Kojto 122:f9eeca106725 963 * @retval None.
Kojto 122:f9eeca106725 964 */
Kojto 122:f9eeca106725 965 #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, RCC_EXTI_LINE_LSECSS)
Kojto 122:f9eeca106725 966
Kojto 122:f9eeca106725 967 /**
Kojto 122:f9eeca106725 968 * @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger.
Kojto 122:f9eeca106725 969 * @retval None.
Kojto 122:f9eeca106725 970 */
Kojto 122:f9eeca106725 971 #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, RCC_EXTI_LINE_LSECSS)
Kojto 122:f9eeca106725 972
Kojto 122:f9eeca106725 973 /**
Kojto 122:f9eeca106725 974 * @brief RCC LSE CSS EXTI line configuration: set rising & falling edge trigger.
Kojto 122:f9eeca106725 975 * @retval None.
Kojto 122:f9eeca106725 976 */
Kojto 122:f9eeca106725 977 #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE() \
Kojto 122:f9eeca106725 978 do { \
Kojto 122:f9eeca106725 979 __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); \
Kojto 122:f9eeca106725 980 __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); \
Kojto 122:f9eeca106725 981 } while(0)
Kojto 122:f9eeca106725 982
Kojto 122:f9eeca106725 983 /**
Kojto 122:f9eeca106725 984 * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
Kojto 122:f9eeca106725 985 * @retval None.
Kojto 122:f9eeca106725 986 */
Kojto 122:f9eeca106725 987 #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE() \
Kojto 122:f9eeca106725 988 do { \
Kojto 122:f9eeca106725 989 __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); \
Kojto 122:f9eeca106725 990 __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); \
Kojto 122:f9eeca106725 991 } while(0)
Kojto 122:f9eeca106725 992
Kojto 122:f9eeca106725 993 /**
Kojto 122:f9eeca106725 994 * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not.
Kojto 122:f9eeca106725 995 * @retval EXTI RCC LSE CSS Line Status.
Kojto 122:f9eeca106725 996 */
Kojto 122:f9eeca106725 997 #define __HAL_RCC_LSECSS_EXTI_GET_FLAG() (EXTI->PR & (RCC_EXTI_LINE_LSECSS))
Kojto 122:f9eeca106725 998
Kojto 122:f9eeca106725 999 /**
Kojto 122:f9eeca106725 1000 * @brief Clear the RCC LSE CSS EXTI flag.
Kojto 122:f9eeca106725 1001 * @retval None.
Kojto 122:f9eeca106725 1002 */
Kojto 122:f9eeca106725 1003 #define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() (EXTI->PR = (RCC_EXTI_LINE_LSECSS))
Kojto 122:f9eeca106725 1004
Kojto 122:f9eeca106725 1005 /**
Kojto 122:f9eeca106725 1006 * @brief Generate a Software interrupt on selected EXTI line.
Kojto 122:f9eeca106725 1007 * @retval None.
Kojto 122:f9eeca106725 1008 */
Kojto 122:f9eeca106725 1009 #define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, RCC_EXTI_LINE_LSECSS)
Kojto 122:f9eeca106725 1010
Kojto 122:f9eeca106725 1011 #endif /* RCC_CSR_LSECSSON */
Kojto 122:f9eeca106725 1012
Kojto 90:cb3d968589d8 1013
Kojto 90:cb3d968589d8 1014 /**
Kojto 90:cb3d968589d8 1015 * @}
Kojto 90:cb3d968589d8 1016 */
Kojto 90:cb3d968589d8 1017
Kojto 90:cb3d968589d8 1018 /* Exported functions --------------------------------------------------------*/
Kojto 122:f9eeca106725 1019 /** @addtogroup RCCEx_Exported_Functions
Kojto 90:cb3d968589d8 1020 * @{
Kojto 90:cb3d968589d8 1021 */
Kojto 90:cb3d968589d8 1022
Kojto 90:cb3d968589d8 1023 /** @addtogroup RCCEx_Exported_Functions_Group1
Kojto 90:cb3d968589d8 1024 * @{
Kojto 90:cb3d968589d8 1025 */
Kojto 90:cb3d968589d8 1026
Kojto 90:cb3d968589d8 1027 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
Kojto 90:cb3d968589d8 1028 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
Kojto 122:f9eeca106725 1029 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
Kojto 90:cb3d968589d8 1030
Kojto 122:f9eeca106725 1031 #if defined(RCC_CSR_LSECSSON)
Kojto 90:cb3d968589d8 1032
Kojto 90:cb3d968589d8 1033 void HAL_RCCEx_EnableLSECSS(void);
Kojto 90:cb3d968589d8 1034 void HAL_RCCEx_DisableLSECSS(void);
Kojto 122:f9eeca106725 1035 void HAL_RCCEx_EnableLSECSS_IT(void);
Kojto 122:f9eeca106725 1036 void HAL_RCCEx_LSECSS_IRQHandler(void);
Kojto 122:f9eeca106725 1037 void HAL_RCCEx_LSECSS_Callback(void);
Kojto 90:cb3d968589d8 1038
Kojto 122:f9eeca106725 1039 #endif /* RCC_CSR_LSECSSON */
Kojto 90:cb3d968589d8 1040 /**
Kojto 90:cb3d968589d8 1041 * @}
Kojto 90:cb3d968589d8 1042 */
Kojto 90:cb3d968589d8 1043
Kojto 90:cb3d968589d8 1044 /**
Kojto 90:cb3d968589d8 1045 * @}
Kojto 90:cb3d968589d8 1046 */
Kojto 90:cb3d968589d8 1047
Kojto 90:cb3d968589d8 1048 /**
Kojto 90:cb3d968589d8 1049 * @}
Kojto 90:cb3d968589d8 1050 */
Kojto 90:cb3d968589d8 1051
Kojto 90:cb3d968589d8 1052 /**
Kojto 90:cb3d968589d8 1053 * @}
Kojto 90:cb3d968589d8 1054 */
Kojto 90:cb3d968589d8 1055
Kojto 90:cb3d968589d8 1056 #ifdef __cplusplus
Kojto 90:cb3d968589d8 1057 }
Kojto 90:cb3d968589d8 1058 #endif
Kojto 90:cb3d968589d8 1059
Kojto 90:cb3d968589d8 1060 #endif /* __STM32L1xx_HAL_RCC_EX_H */
Kojto 90:cb3d968589d8 1061
Kojto 90:cb3d968589d8 1062 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Kojto 122:f9eeca106725 1063