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Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

TARGET_NUCLEO_F401RE/stm32f4xx_ll_fsmc.h@122:f9eeca106725, 2016-07-07 (annotated)

Committer:
Kojto
Date:
Thu Jul 07 14:34:11 2016 +0100
Revision:
122:f9eeca106725
Parent:
110:165afa46840b 
Release 122 of the mbed library



Changes:

- new targets - Nucleo L432KC, Beetle, Nucleo F446ZE, Nucleo L011K4

- Thread safety addition - mbed API should contain a statement about thread safety

- critical section API addition

- CAS API (core_util_atomic_incr/decr)

- DEVICE_ are generated from targets.json file, device.h deprecated

- Callback replaces FunctionPointer to provide std like interface

- mbed HAL API docs improvements

- toolchain - prexif attributes with MBED_

            - add new attributes - packed, weak, forcedinline, align

- target.json - contains targets definitions

- ST - L1XX - Cube update to 1.5

     - SPI clock selection fix (clock from APB domain)

     - F7 - Cube update v1.4.0

     - L0 -  baudrate init fix

     - L1 - Cube update v1.5

     - F3 - baudrate init fix, 3 targets CAN support

     - F4 - Cube update v1.12.0, 3 targets CAN support

     - L4XX - Cube update v1.5.1

     - F0 - update Cube to v1.5.0

     - L4 - 2 targets (L476RG/VG) CAN support

- NXP - pwm clock fix for KSDK2 MCU

      - LPC2368 - remove ARM toolchain support - due to regression

      - KSDK2 - fix SPI , I2C address and repeat start

- Silabs - some fixes backported from mbed 3

- Renesas - RZ_A1H - SystemCoreClockUpdate addition

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 77:869cf507173a 1 /**
emilmont 77:869cf507173a 2 ******************************************************************************
emilmont 77:869cf507173a 3 * @file stm32f4xx_ll_fsmc.h
emilmont 77:869cf507173a 4 * @author MCD Application Team
Kojto 122:f9eeca106725 5 * @version V1.5.0
Kojto 122:f9eeca106725 6 * @date 06-May-2016
emilmont 77:869cf507173a 7 * @brief Header file of FSMC HAL module.
emilmont 77:869cf507173a 8 ******************************************************************************
emilmont 77:869cf507173a 9 * @attention
emilmont 77:869cf507173a 10 *
Kojto 122:f9eeca106725 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
emilmont 77:869cf507173a 12 *
emilmont 77:869cf507173a 13 * Redistribution and use in source and binary forms, with or without modification,
emilmont 77:869cf507173a 14 * are permitted provided that the following conditions are met:
emilmont 77:869cf507173a 15 * 1. Redistributions of source code must retain the above copyright notice,
emilmont 77:869cf507173a 16 * this list of conditions and the following disclaimer.
emilmont 77:869cf507173a 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
emilmont 77:869cf507173a 18 * this list of conditions and the following disclaimer in the documentation
emilmont 77:869cf507173a 19 * and/or other materials provided with the distribution.
emilmont 77:869cf507173a 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
emilmont 77:869cf507173a 21 * may be used to endorse or promote products derived from this software
emilmont 77:869cf507173a 22 * without specific prior written permission.
emilmont 77:869cf507173a 23 *
emilmont 77:869cf507173a 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
emilmont 77:869cf507173a 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
emilmont 77:869cf507173a 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
emilmont 77:869cf507173a 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
emilmont 77:869cf507173a 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
emilmont 77:869cf507173a 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
emilmont 77:869cf507173a 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
emilmont 77:869cf507173a 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
emilmont 77:869cf507173a 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
emilmont 77:869cf507173a 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
emilmont 77:869cf507173a 34 *
emilmont 77:869cf507173a 35 ******************************************************************************
emilmont 77:869cf507173a 36 */
emilmont 77:869cf507173a 37
emilmont 77:869cf507173a 38 /* Define to prevent recursive inclusion -------------------------------------*/
emilmont 77:869cf507173a 39 #ifndef __STM32F4xx_LL_FSMC_H
emilmont 77:869cf507173a 40 #define __STM32F4xx_LL_FSMC_H
emilmont 77:869cf507173a 41
emilmont 77:869cf507173a 42 #ifdef __cplusplus
emilmont 77:869cf507173a 43 extern "C" {
emilmont 77:869cf507173a 44 #endif
emilmont 77:869cf507173a 45
emilmont 77:869cf507173a 46 /* Includes ------------------------------------------------------------------*/
emilmont 77:869cf507173a 47 #include "stm32f4xx_hal_def.h"
emilmont 77:869cf507173a 48
emilmont 77:869cf507173a 49 /** @addtogroup STM32F4xx_HAL_Driver
emilmont 77:869cf507173a 50 * @{
emilmont 77:869cf507173a 51 */
Kojto 99:dbbf35b96557 52
Kojto 99:dbbf35b96557 53 /** @addtogroup FSMC_LL
emilmont 77:869cf507173a 54 * @{
Kojto 99:dbbf35b96557 55 */
emilmont 77:869cf507173a 56
Kojto 122:f9eeca106725 57 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx)
Kojto 99:dbbf35b96557 58 /* Private types -------------------------------------------------------------*/
Kojto 99:dbbf35b96557 59 /** @defgroup FSMC_LL_Private_Types FSMC Private Types
Kojto 99:dbbf35b96557 60 * @{
Kojto 99:dbbf35b96557 61 */
emilmont 77:869cf507173a 62
emilmont 77:869cf507173a 63 /**
Kojto 99:dbbf35b96557 64 * @brief FSMC NORSRAM Configuration Structure definition
emilmont 77:869cf507173a 65 */
emilmont 77:869cf507173a 66 typedef struct
emilmont 77:869cf507173a 67 {
emilmont 77:869cf507173a 68 uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
bogdanm 85:024bf7f99721 69 This parameter can be a value of @ref FSMC_NORSRAM_Bank */
bogdanm 85:024bf7f99721 70
emilmont 77:869cf507173a 71 uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
emilmont 77:869cf507173a 72 multiplexed on the data bus or not.
emilmont 77:869cf507173a 73 This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
bogdanm 85:024bf7f99721 74
emilmont 77:869cf507173a 75 uint32_t MemoryType; /*!< Specifies the type of external memory attached to
emilmont 77:869cf507173a 76 the corresponding memory device.
emilmont 77:869cf507173a 77 This parameter can be a value of @ref FSMC_Memory_Type */
bogdanm 85:024bf7f99721 78
emilmont 77:869cf507173a 79 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
emilmont 77:869cf507173a 80 This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */
bogdanm 85:024bf7f99721 81
emilmont 77:869cf507173a 82 uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
emilmont 77:869cf507173a 83 valid only with synchronous burst Flash memories.
emilmont 77:869cf507173a 84 This parameter can be a value of @ref FSMC_Burst_Access_Mode */
bogdanm 85:024bf7f99721 85
emilmont 77:869cf507173a 86 uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
emilmont 77:869cf507173a 87 the Flash memory in burst mode.
emilmont 77:869cf507173a 88 This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
bogdanm 85:024bf7f99721 89
emilmont 77:869cf507173a 90 uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
emilmont 77:869cf507173a 91 memory, valid only when accessing Flash memories in burst mode.
Kojto 122:f9eeca106725 92 This parameter can be a value of @ref FSMC_Wrap_Mode
Kojto 122:f9eeca106725 93 This mode is available only for the STM32F405/407/4015/417xx devices */
bogdanm 85:024bf7f99721 94
emilmont 77:869cf507173a 95 uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
emilmont 77:869cf507173a 96 clock cycle before the wait state or during the wait state,
emilmont 77:869cf507173a 97 valid only when accessing memories in burst mode.
emilmont 77:869cf507173a 98 This parameter can be a value of @ref FSMC_Wait_Timing */
bogdanm 85:024bf7f99721 99
emilmont 77:869cf507173a 100 uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FSMC.
emilmont 77:869cf507173a 101 This parameter can be a value of @ref FSMC_Write_Operation */
bogdanm 85:024bf7f99721 102
emilmont 77:869cf507173a 103 uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
emilmont 77:869cf507173a 104 signal, valid for Flash memory access in burst mode.
emilmont 77:869cf507173a 105 This parameter can be a value of @ref FSMC_Wait_Signal */
bogdanm 85:024bf7f99721 106
emilmont 77:869cf507173a 107 uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
emilmont 77:869cf507173a 108 This parameter can be a value of @ref FSMC_Extended_Mode */
bogdanm 85:024bf7f99721 109
emilmont 77:869cf507173a 110 uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
emilmont 77:869cf507173a 111 valid only with asynchronous Flash memories.
emilmont 77:869cf507173a 112 This parameter can be a value of @ref FSMC_AsynchronousWait */
bogdanm 85:024bf7f99721 113
emilmont 77:869cf507173a 114 uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
bogdanm 85:024bf7f99721 115 This parameter can be a value of @ref FSMC_Write_Burst */
emilmont 77:869cf507173a 116
Kojto 122:f9eeca106725 117 uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
Kojto 122:f9eeca106725 118 This parameter is only enabled through the FMC_BCR1 register, and don't care
Kojto 122:f9eeca106725 119 through FMC_BCR2..4 registers.
Kojto 122:f9eeca106725 120 This parameter can be a value of @ref FMC_Continous_Clock
Kojto 122:f9eeca106725 121 This mode is available only for the STM32F412Vx/Zx/Rx devices */
Kojto 122:f9eeca106725 122
Kojto 122:f9eeca106725 123 uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller.
Kojto 122:f9eeca106725 124 This parameter is only enabled through the FMC_BCR1 register, and don't care
Kojto 122:f9eeca106725 125 through FMC_BCR2..4 registers.
Kojto 122:f9eeca106725 126 This parameter can be a value of @ref FMC_Write_FIFO
Kojto 122:f9eeca106725 127 This mode is available only for the STM32F412Vx/Vx devices */
Kojto 122:f9eeca106725 128
Kojto 122:f9eeca106725 129 uint32_t PageSize; /*!< Specifies the memory page size.
Kojto 122:f9eeca106725 130 This parameter can be a value of @ref FMC_Page_Size */
emilmont 77:869cf507173a 131 }FSMC_NORSRAM_InitTypeDef;
emilmont 77:869cf507173a 132
emilmont 77:869cf507173a 133 /**
Kojto 99:dbbf35b96557 134 * @brief FSMC NORSRAM Timing parameters structure definition
emilmont 77:869cf507173a 135 */
emilmont 77:869cf507173a 136 typedef struct
emilmont 77:869cf507173a 137 {
emilmont 77:869cf507173a 138 uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
emilmont 77:869cf507173a 139 the duration of the address setup time.
emilmont 77:869cf507173a 140 This parameter can be a value between Min_Data = 0 and Max_Data = 15.
emilmont 77:869cf507173a 141 @note This parameter is not used with synchronous NOR Flash memories. */
bogdanm 85:024bf7f99721 142
emilmont 77:869cf507173a 143 uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
emilmont 77:869cf507173a 144 the duration of the address hold time.
emilmont 77:869cf507173a 145 This parameter can be a value between Min_Data = 1 and Max_Data = 15.
emilmont 77:869cf507173a 146 @note This parameter is not used with synchronous NOR Flash memories. */
bogdanm 85:024bf7f99721 147
emilmont 77:869cf507173a 148 uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
emilmont 77:869cf507173a 149 the duration of the data setup time.
emilmont 77:869cf507173a 150 This parameter can be a value between Min_Data = 1 and Max_Data = 255.
emilmont 77:869cf507173a 151 @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
emilmont 77:869cf507173a 152 NOR Flash memories. */
bogdanm 85:024bf7f99721 153
emilmont 77:869cf507173a 154 uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
emilmont 77:869cf507173a 155 the duration of the bus turnaround.
emilmont 77:869cf507173a 156 This parameter can be a value between Min_Data = 0 and Max_Data = 15.
emilmont 77:869cf507173a 157 @note This parameter is only used for multiplexed NOR Flash memories. */
bogdanm 85:024bf7f99721 158
emilmont 77:869cf507173a 159 uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
emilmont 77:869cf507173a 160 HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
emilmont 77:869cf507173a 161 @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
emilmont 77:869cf507173a 162 accesses. */
bogdanm 85:024bf7f99721 163
emilmont 77:869cf507173a 164 uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
emilmont 77:869cf507173a 165 to the memory before getting the first data.
emilmont 77:869cf507173a 166 The parameter value depends on the memory type as shown below:
emilmont 77:869cf507173a 167 - It must be set to 0 in case of a CRAM
emilmont 77:869cf507173a 168 - It is don't care in asynchronous NOR, SRAM or ROM accesses
emilmont 77:869cf507173a 169 - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
emilmont 77:869cf507173a 170 with synchronous burst mode enable */
bogdanm 85:024bf7f99721 171
emilmont 77:869cf507173a 172 uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
emilmont 77:869cf507173a 173 This parameter can be a value of @ref FSMC_Access_Mode */
bogdanm 85:024bf7f99721 174
emilmont 77:869cf507173a 175 }FSMC_NORSRAM_TimingTypeDef;
emilmont 77:869cf507173a 176
Kojto 110:165afa46840b 177 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
emilmont 77:869cf507173a 178 /**
Kojto 99:dbbf35b96557 179 * @brief FSMC NAND Configuration Structure definition
emilmont 77:869cf507173a 180 */
emilmont 77:869cf507173a 181 typedef struct
emilmont 77:869cf507173a 182 {
emilmont 77:869cf507173a 183 uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
bogdanm 85:024bf7f99721 184 This parameter can be a value of @ref FSMC_NAND_Bank */
bogdanm 85:024bf7f99721 185
emilmont 77:869cf507173a 186 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
emilmont 77:869cf507173a 187 This parameter can be any value of @ref FSMC_Wait_feature */
bogdanm 85:024bf7f99721 188
emilmont 77:869cf507173a 189 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
emilmont 77:869cf507173a 190 This parameter can be any value of @ref FSMC_NAND_Data_Width */
bogdanm 85:024bf7f99721 191
emilmont 77:869cf507173a 192 uint32_t EccComputation; /*!< Enables or disables the ECC computation.
emilmont 77:869cf507173a 193 This parameter can be any value of @ref FSMC_ECC */
bogdanm 85:024bf7f99721 194
emilmont 77:869cf507173a 195 uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
emilmont 77:869cf507173a 196 This parameter can be any value of @ref FSMC_ECC_Page_Size */
bogdanm 85:024bf7f99721 197
emilmont 77:869cf507173a 198 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
emilmont 77:869cf507173a 199 delay between CLE low and RE low.
emilmont 77:869cf507173a 200 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
bogdanm 85:024bf7f99721 201
emilmont 77:869cf507173a 202 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
emilmont 77:869cf507173a 203 delay between ALE low and RE low.
emilmont 77:869cf507173a 204 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm 85:024bf7f99721 205
Kojto 122:f9eeca106725 206 }FSMC_NAND_InitTypeDef;
emilmont 77:869cf507173a 207
emilmont 77:869cf507173a 208 /**
Kojto 99:dbbf35b96557 209 * @brief FSMC NAND/PCCARD Timing parameters structure definition
emilmont 77:869cf507173a 210 */
emilmont 77:869cf507173a 211 typedef struct
emilmont 77:869cf507173a 212 {
emilmont 77:869cf507173a 213 uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
emilmont 77:869cf507173a 214 the command assertion for NAND-Flash read or write access
emilmont 77:869cf507173a 215 to common/Attribute or I/O memory space (depending on
emilmont 77:869cf507173a 216 the memory space timing to be configured).
emilmont 77:869cf507173a 217 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
bogdanm 85:024bf7f99721 218
emilmont 77:869cf507173a 219 uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
emilmont 77:869cf507173a 220 command for NAND-Flash read or write access to
emilmont 77:869cf507173a 221 common/Attribute or I/O memory space (depending on the
emilmont 77:869cf507173a 222 memory space timing to be configured).
emilmont 77:869cf507173a 223 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm 85:024bf7f99721 224
emilmont 77:869cf507173a 225 uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
emilmont 77:869cf507173a 226 (and data for write access) after the command de-assertion
emilmont 77:869cf507173a 227 for NAND-Flash read or write access to common/Attribute
emilmont 77:869cf507173a 228 or I/O memory space (depending on the memory space timing
emilmont 77:869cf507173a 229 to be configured).
emilmont 77:869cf507173a 230 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm 85:024bf7f99721 231
emilmont 77:869cf507173a 232 uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
emilmont 77:869cf507173a 233 data bus is kept in HiZ after the start of a NAND-Flash
emilmont 77:869cf507173a 234 write access to common/Attribute or I/O memory space (depending
emilmont 77:869cf507173a 235 on the memory space timing to be configured).
emilmont 77:869cf507173a 236 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm 85:024bf7f99721 237
emilmont 77:869cf507173a 238 }FSMC_NAND_PCC_TimingTypeDef;
emilmont 77:869cf507173a 239
emilmont 77:869cf507173a 240 /**
Kojto 99:dbbf35b96557 241 * @brief FSMC NAND Configuration Structure definition
bogdanm 85:024bf7f99721 242 */
emilmont 77:869cf507173a 243 typedef struct
emilmont 77:869cf507173a 244 {
emilmont 77:869cf507173a 245 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
emilmont 77:869cf507173a 246 This parameter can be any value of @ref FSMC_Wait_feature */
bogdanm 85:024bf7f99721 247
emilmont 77:869cf507173a 248 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
emilmont 77:869cf507173a 249 delay between CLE low and RE low.
emilmont 77:869cf507173a 250 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
bogdanm 85:024bf7f99721 251
emilmont 77:869cf507173a 252 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
emilmont 77:869cf507173a 253 delay between ALE low and RE low.
emilmont 77:869cf507173a 254 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm 85:024bf7f99721 255
bogdanm 85:024bf7f99721 256 }FSMC_PCCARD_InitTypeDef;
Kojto 99:dbbf35b96557 257 /**
Kojto 99:dbbf35b96557 258 * @}
Kojto 99:dbbf35b96557 259 */
Kojto 110:165afa46840b 260 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
emilmont 77:869cf507173a 261
Kojto 99:dbbf35b96557 262 /* Private constants ---------------------------------------------------------*/
Kojto 99:dbbf35b96557 263 /** @defgroup FSMC_LL_Private_Constants FSMC Private Constants
Kojto 99:dbbf35b96557 264 * @{
Kojto 99:dbbf35b96557 265 */
emilmont 77:869cf507173a 266
Kojto 99:dbbf35b96557 267 /** @defgroup FSMC_LL_NOR_SRAM_Controller FSMC NOR/SRAM Controller
emilmont 77:869cf507173a 268 * @{
emilmont 77:869cf507173a 269 */
Kojto 99:dbbf35b96557 270 /** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank
emilmont 77:869cf507173a 271 * @{
emilmont 77:869cf507173a 272 */
Kojto 122:f9eeca106725 273 #define FSMC_NORSRAM_BANK1 ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 274 #define FSMC_NORSRAM_BANK2 ((uint32_t)0x00000002U)
Kojto 122:f9eeca106725 275 #define FSMC_NORSRAM_BANK3 ((uint32_t)0x00000004U)
Kojto 122:f9eeca106725 276 #define FSMC_NORSRAM_BANK4 ((uint32_t)0x00000006U)
emilmont 77:869cf507173a 277 /**
emilmont 77:869cf507173a 278 * @}
emilmont 77:869cf507173a 279 */
emilmont 77:869cf507173a 280
Kojto 99:dbbf35b96557 281 /** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing
emilmont 77:869cf507173a 282 * @{
emilmont 77:869cf507173a 283 */
Kojto 122:f9eeca106725 284 #define FSMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 285 #define FSMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002U)
emilmont 77:869cf507173a 286 /**
emilmont 77:869cf507173a 287 * @}
emilmont 77:869cf507173a 288 */
emilmont 77:869cf507173a 289
Kojto 99:dbbf35b96557 290 /** @defgroup FSMC_Memory_Type FSMC Memory Type
emilmont 77:869cf507173a 291 * @{
emilmont 77:869cf507173a 292 */
Kojto 122:f9eeca106725 293 #define FSMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 294 #define FSMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004U)
Kojto 122:f9eeca106725 295 #define FSMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008U)
emilmont 77:869cf507173a 296 /**
emilmont 77:869cf507173a 297 * @}
emilmont 77:869cf507173a 298 */
emilmont 77:869cf507173a 299
Kojto 99:dbbf35b96557 300 /** @defgroup FSMC_NORSRAM_Data_Width FSMC NOR/SRAM Data Width
emilmont 77:869cf507173a 301 * @{
emilmont 77:869cf507173a 302 */
Kojto 122:f9eeca106725 303 #define FSMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 304 #define FSMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U)
Kojto 122:f9eeca106725 305 #define FSMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020U)
emilmont 77:869cf507173a 306 /**
emilmont 77:869cf507173a 307 * @}
emilmont 77:869cf507173a 308 */
emilmont 77:869cf507173a 309
Kojto 99:dbbf35b96557 310 /** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access
emilmont 77:869cf507173a 311 * @{
emilmont 77:869cf507173a 312 */
Kojto 122:f9eeca106725 313 #define FSMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040U)
Kojto 122:f9eeca106725 314 #define FSMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000U)
emilmont 77:869cf507173a 315 /**
emilmont 77:869cf507173a 316 * @}
emilmont 77:869cf507173a 317 */
emilmont 77:869cf507173a 318
Kojto 99:dbbf35b96557 319 /** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode
emilmont 77:869cf507173a 320 * @{
emilmont 77:869cf507173a 321 */
Kojto 122:f9eeca106725 322 #define FSMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 323 #define FSMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100U)
emilmont 77:869cf507173a 324 /**
emilmont 77:869cf507173a 325 * @}
emilmont 77:869cf507173a 326 */
emilmont 77:869cf507173a 327
Kojto 99:dbbf35b96557 328 /** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity
emilmont 77:869cf507173a 329 * @{
emilmont 77:869cf507173a 330 */
Kojto 122:f9eeca106725 331 #define FSMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 332 #define FSMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200U)
emilmont 77:869cf507173a 333 /**
emilmont 77:869cf507173a 334 * @}
emilmont 77:869cf507173a 335 */
emilmont 77:869cf507173a 336
Kojto 99:dbbf35b96557 337 /** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode
Kojto 122:f9eeca106725 338 * @note These values are available only for the STM32F405/415/407/417xx devices.
Kojto 99:dbbf35b96557 339 * @{
Kojto 99:dbbf35b96557 340 */
Kojto 122:f9eeca106725 341 #define FSMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 342 #define FSMC_WRAP_MODE_ENABLE ((uint32_t)0x00000400U)
Kojto 99:dbbf35b96557 343 /**
Kojto 99:dbbf35b96557 344 * @}
Kojto 99:dbbf35b96557 345 */
Kojto 99:dbbf35b96557 346
Kojto 99:dbbf35b96557 347 /** @defgroup FSMC_Wait_Timing FSMC Wait Timing
emilmont 77:869cf507173a 348 * @{
emilmont 77:869cf507173a 349 */
Kojto 122:f9eeca106725 350 #define FSMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 351 #define FSMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800U)
emilmont 77:869cf507173a 352 /**
emilmont 77:869cf507173a 353 * @}
emilmont 77:869cf507173a 354 */
emilmont 77:869cf507173a 355
Kojto 99:dbbf35b96557 356 /** @defgroup FSMC_Write_Operation FSMC Write Operation
emilmont 77:869cf507173a 357 * @{
emilmont 77:869cf507173a 358 */
Kojto 122:f9eeca106725 359 #define FSMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 360 #define FSMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000U)
emilmont 77:869cf507173a 361 /**
emilmont 77:869cf507173a 362 * @}
emilmont 77:869cf507173a 363 */
emilmont 77:869cf507173a 364
Kojto 99:dbbf35b96557 365 /** @defgroup FSMC_Wait_Signal FSMC Wait Signal
Kojto 99:dbbf35b96557 366 * @{
Kojto 99:dbbf35b96557 367 */
Kojto 122:f9eeca106725 368 #define FSMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 369 #define FSMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000U)
Kojto 99:dbbf35b96557 370 /**
Kojto 99:dbbf35b96557 371 * @}
Kojto 99:dbbf35b96557 372 */
Kojto 99:dbbf35b96557 373
Kojto 99:dbbf35b96557 374 /** @defgroup FSMC_Extended_Mode FSMC Extended Mode
Kojto 99:dbbf35b96557 375 * @{
Kojto 99:dbbf35b96557 376 */
Kojto 122:f9eeca106725 377 #define FSMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 378 #define FSMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000U)
Kojto 99:dbbf35b96557 379 /**
Kojto 99:dbbf35b96557 380 * @}
Kojto 99:dbbf35b96557 381 */
Kojto 99:dbbf35b96557 382
Kojto 99:dbbf35b96557 383 /** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait
emilmont 77:869cf507173a 384 * @{
emilmont 77:869cf507173a 385 */
Kojto 122:f9eeca106725 386 #define FSMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 387 #define FSMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000U)
emilmont 77:869cf507173a 388 /**
emilmont 77:869cf507173a 389 * @}
Kojto 122:f9eeca106725 390 */
Kojto 122:f9eeca106725 391
Kojto 122:f9eeca106725 392 /** @defgroup FSMC_Page_Size FSMC Page Size
Kojto 122:f9eeca106725 393 * @{
Kojto 122:f9eeca106725 394 */
Kojto 122:f9eeca106725 395 #define FSMC_PAGE_SIZE_NONE ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 396 #define FSMC_PAGE_SIZE_128 ((uint32_t)FSMC_BCR1_CPSIZE_0)
Kojto 122:f9eeca106725 397 #define FSMC_PAGE_SIZE_256 ((uint32_t)FSMC_BCR1_CPSIZE_1)
Kojto 122:f9eeca106725 398 #define FSMC_PAGE_SIZE_512 ((uint32_t)(FSMC_BCR1_CPSIZE_0 | FSMC_BCR1_CPSIZE_1))
Kojto 122:f9eeca106725 399 #define FSMC_PAGE_SIZE_1024 ((uint32_t)FSMC_BCR1_CPSIZE_2)
Kojto 122:f9eeca106725 400 /**
Kojto 122:f9eeca106725 401 * @}
Kojto 122:f9eeca106725 402 */
Kojto 122:f9eeca106725 403
Kojto 122:f9eeca106725 404 /** @defgroup FSMC_Write_FIFO FSMC Write FIFO
Kojto 122:f9eeca106725 405 * @note These values are available only for the STM32F412Vx/Zx/Rx devices.
Kojto 122:f9eeca106725 406 * @{
Kojto 122:f9eeca106725 407 */
Kojto 122:f9eeca106725 408 #define FSMC_WRITE_FIFO_DISABLE ((uint32_t)FSMC_BCR1_WFDIS)
Kojto 122:f9eeca106725 409 #define FSMC_WRITE_FIFO_ENABLE ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 410 /**
Kojto 122:f9eeca106725 411 * @}
Kojto 122:f9eeca106725 412 */
emilmont 77:869cf507173a 413
Kojto 99:dbbf35b96557 414 /** @defgroup FSMC_Write_Burst FSMC Write Burst
emilmont 77:869cf507173a 415 * @{
emilmont 77:869cf507173a 416 */
Kojto 122:f9eeca106725 417 #define FSMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 418 #define FSMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000U)
emilmont 77:869cf507173a 419 /**
emilmont 77:869cf507173a 420 * @}
emilmont 77:869cf507173a 421 */
emilmont 77:869cf507173a 422
Kojto 99:dbbf35b96557 423 /** @defgroup FSMC_Continous_Clock FSMC Continous Clock
Kojto 122:f9eeca106725 424 * @note These values are available only for the STM32F412Vx/Zx/Rx devices.
emilmont 77:869cf507173a 425 * @{
emilmont 77:869cf507173a 426 */
Kojto 122:f9eeca106725 427 #define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 428 #define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000U)
emilmont 77:869cf507173a 429 /**
emilmont 77:869cf507173a 430 * @}
emilmont 77:869cf507173a 431 */
emilmont 77:869cf507173a 432
Kojto 99:dbbf35b96557 433 /** @defgroup FSMC_Access_Mode FSMC Access Mode
emilmont 77:869cf507173a 434 * @{
emilmont 77:869cf507173a 435 */
Kojto 122:f9eeca106725 436 #define FSMC_ACCESS_MODE_A ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 437 #define FSMC_ACCESS_MODE_B ((uint32_t)0x10000000U)
Kojto 122:f9eeca106725 438 #define FSMC_ACCESS_MODE_C ((uint32_t)0x20000000U)
Kojto 122:f9eeca106725 439 #define FSMC_ACCESS_MODE_D ((uint32_t)0x30000000U)
emilmont 77:869cf507173a 440 /**
emilmont 77:869cf507173a 441 * @}
emilmont 77:869cf507173a 442 */
emilmont 77:869cf507173a 443 /**
emilmont 77:869cf507173a 444 * @}
emilmont 77:869cf507173a 445 */
emilmont 77:869cf507173a 446
Kojto 110:165afa46840b 447 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
Kojto 99:dbbf35b96557 448 /** @defgroup FSMC_LL_NAND_Controller FSMC NAND and PCCARD Controller
Kojto 99:dbbf35b96557 449 * @{
Kojto 99:dbbf35b96557 450 */
Kojto 99:dbbf35b96557 451 /** @defgroup FSMC_NAND_Bank FSMC NAND Bank
Kojto 99:dbbf35b96557 452 * @{
Kojto 99:dbbf35b96557 453 */
Kojto 122:f9eeca106725 454 #define FSMC_NAND_BANK2 ((uint32_t)0x00000010U)
Kojto 122:f9eeca106725 455 #define FSMC_NAND_BANK3 ((uint32_t)0x00000100U)
Kojto 99:dbbf35b96557 456 /**
Kojto 99:dbbf35b96557 457 * @}
Kojto 99:dbbf35b96557 458 */
Kojto 99:dbbf35b96557 459
Kojto 99:dbbf35b96557 460 /** @defgroup FSMC_Wait_feature FSMC Wait feature
emilmont 77:869cf507173a 461 * @{
emilmont 77:869cf507173a 462 */
Kojto 122:f9eeca106725 463 #define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 464 #define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002U)
emilmont 77:869cf507173a 465 /**
emilmont 77:869cf507173a 466 * @}
emilmont 77:869cf507173a 467 */
emilmont 77:869cf507173a 468
Kojto 99:dbbf35b96557 469 /** @defgroup FSMC_PCR_Memory_Type FSMC PCR Memory Type
emilmont 77:869cf507173a 470 * @{
emilmont 77:869cf507173a 471 */
Kojto 122:f9eeca106725 472 #define FSMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 473 #define FSMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008U)
emilmont 77:869cf507173a 474 /**
emilmont 77:869cf507173a 475 * @}
emilmont 77:869cf507173a 476 */
emilmont 77:869cf507173a 477
Kojto 99:dbbf35b96557 478 /** @defgroup FSMC_NAND_Data_Width FSMC NAND Data Width
emilmont 77:869cf507173a 479 * @{
emilmont 77:869cf507173a 480 */
Kojto 122:f9eeca106725 481 #define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 482 #define FSMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U)
emilmont 77:869cf507173a 483 /**
emilmont 77:869cf507173a 484 * @}
emilmont 77:869cf507173a 485 */
emilmont 77:869cf507173a 486
Kojto 99:dbbf35b96557 487 /** @defgroup FSMC_ECC FSMC ECC
emilmont 77:869cf507173a 488 * @{
emilmont 77:869cf507173a 489 */
Kojto 122:f9eeca106725 490 #define FSMC_NAND_ECC_DISABLE ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 491 #define FSMC_NAND_ECC_ENABLE ((uint32_t)0x00000040U)
emilmont 77:869cf507173a 492 /**
emilmont 77:869cf507173a 493 * @}
emilmont 77:869cf507173a 494 */
emilmont 77:869cf507173a 495
Kojto 99:dbbf35b96557 496 /** @defgroup FSMC_ECC_Page_Size FSMC ECC Page Size
emilmont 77:869cf507173a 497 * @{
emilmont 77:869cf507173a 498 */
Kojto 122:f9eeca106725 499 #define FSMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 500 #define FSMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000U)
Kojto 122:f9eeca106725 501 #define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000U)
Kojto 122:f9eeca106725 502 #define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000U)
Kojto 122:f9eeca106725 503 #define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000U)
Kojto 122:f9eeca106725 504 #define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000U)
emilmont 77:869cf507173a 505 /**
emilmont 77:869cf507173a 506 * @}
emilmont 77:869cf507173a 507 */
emilmont 77:869cf507173a 508 /**
emilmont 77:869cf507173a 509 * @}
emilmont 77:869cf507173a 510 */
Kojto 110:165afa46840b 511 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
Kojto 110:165afa46840b 512
Kojto 99:dbbf35b96557 513 /** @defgroup FSMC_LL_Interrupt_definition FSMC Interrupt definition
emilmont 77:869cf507173a 514 * @{
emilmont 77:869cf507173a 515 */
Kojto 122:f9eeca106725 516 #define FSMC_IT_RISING_EDGE ((uint32_t)0x00000008U)
Kojto 122:f9eeca106725 517 #define FSMC_IT_LEVEL ((uint32_t)0x00000010U)
Kojto 122:f9eeca106725 518 #define FSMC_IT_FALLING_EDGE ((uint32_t)0x00000020U)
Kojto 122:f9eeca106725 519 #define FSMC_IT_REFRESH_ERROR ((uint32_t)0x00004000U)
emilmont 77:869cf507173a 520 /**
emilmont 77:869cf507173a 521 * @}
emilmont 77:869cf507173a 522 */
emilmont 77:869cf507173a 523
Kojto 99:dbbf35b96557 524 /** @defgroup FSMC_LL_Flag_definition FSMC Flag definition
emilmont 77:869cf507173a 525 * @{
emilmont 77:869cf507173a 526 */
Kojto 122:f9eeca106725 527 #define FSMC_FLAG_RISING_EDGE ((uint32_t)0x00000001U)
Kojto 122:f9eeca106725 528 #define FSMC_FLAG_LEVEL ((uint32_t)0x00000002U)
Kojto 122:f9eeca106725 529 #define FSMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004U)
Kojto 122:f9eeca106725 530 #define FSMC_FLAG_FEMPT ((uint32_t)0x00000040U)
emilmont 77:869cf507173a 531 /**
emilmont 77:869cf507173a 532 * @}
emilmont 77:869cf507173a 533 */
emilmont 77:869cf507173a 534
Kojto 99:dbbf35b96557 535 /** @defgroup FSMC_LL_Alias_definition FSMC Alias definition
Kojto 99:dbbf35b96557 536 * @{
emilmont 77:869cf507173a 537 */
Kojto 99:dbbf35b96557 538 #define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef
Kojto 99:dbbf35b96557 539 #define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef
Kojto 110:165afa46840b 540 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
Kojto 99:dbbf35b96557 541 #define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef
Kojto 99:dbbf35b96557 542 #define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef
Kojto 110:165afa46840b 543 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
emilmont 77:869cf507173a 544
Kojto 99:dbbf35b96557 545 #define FSMC_NORSRAM_DEVICE FSMC_Bank1
Kojto 99:dbbf35b96557 546 #define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E
Kojto 110:165afa46840b 547 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
Kojto 99:dbbf35b96557 548 #define FSMC_NAND_DEVICE FSMC_Bank2_3
Kojto 99:dbbf35b96557 549 #define FSMC_PCCARD_DEVICE FSMC_Bank4
Kojto 110:165afa46840b 550 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
emilmont 77:869cf507173a 551
Kojto 122:f9eeca106725 552 #define FMC_NORSRAM_MEM_BUS_WIDTH_8 FSMC_NORSRAM_MEM_BUS_WIDTH_8
Kojto 122:f9eeca106725 553 #define FMC_NORSRAM_MEM_BUS_WIDTH_16 FSMC_NORSRAM_MEM_BUS_WIDTH_16
Kojto 122:f9eeca106725 554 #define FMC_NORSRAM_MEM_BUS_WIDTH_32 FSMC_NORSRAM_MEM_BUS_WIDTH_32
Kojto 122:f9eeca106725 555
emilmont 77:869cf507173a 556 #define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef
emilmont 77:869cf507173a 557 #define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef
emilmont 77:869cf507173a 558 #define FMC_NORSRAM_InitTypeDef FSMC_NORSRAM_InitTypeDef
emilmont 77:869cf507173a 559 #define FMC_NORSRAM_TimingTypeDef FSMC_NORSRAM_TimingTypeDef
emilmont 77:869cf507173a 560
emilmont 77:869cf507173a 561 #define FMC_NORSRAM_Init FSMC_NORSRAM_Init
emilmont 77:869cf507173a 562 #define FMC_NORSRAM_Timing_Init FSMC_NORSRAM_Timing_Init
emilmont 77:869cf507173a 563 #define FMC_NORSRAM_Extended_Timing_Init FSMC_NORSRAM_Extended_Timing_Init
emilmont 77:869cf507173a 564 #define FMC_NORSRAM_DeInit FSMC_NORSRAM_DeInit
emilmont 77:869cf507173a 565 #define FMC_NORSRAM_WriteOperation_Enable FSMC_NORSRAM_WriteOperation_Enable
emilmont 77:869cf507173a 566 #define FMC_NORSRAM_WriteOperation_Disable FSMC_NORSRAM_WriteOperation_Disable
emilmont 77:869cf507173a 567
emilmont 77:869cf507173a 568 #define __FMC_NORSRAM_ENABLE __FSMC_NORSRAM_ENABLE
emilmont 77:869cf507173a 569 #define __FMC_NORSRAM_DISABLE __FSMC_NORSRAM_DISABLE
emilmont 77:869cf507173a 570
Kojto 110:165afa46840b 571 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
emilmont 77:869cf507173a 572 #define FMC_NAND_InitTypeDef FSMC_NAND_InitTypeDef
emilmont 77:869cf507173a 573 #define FMC_PCCARD_InitTypeDef FSMC_PCCARD_InitTypeDef
emilmont 77:869cf507173a 574 #define FMC_NAND_PCC_TimingTypeDef FSMC_NAND_PCC_TimingTypeDef
emilmont 77:869cf507173a 575
emilmont 77:869cf507173a 576 #define FMC_NAND_Init FSMC_NAND_Init
emilmont 77:869cf507173a 577 #define FMC_NAND_CommonSpace_Timing_Init FSMC_NAND_CommonSpace_Timing_Init
emilmont 77:869cf507173a 578 #define FMC_NAND_AttributeSpace_Timing_Init FSMC_NAND_AttributeSpace_Timing_Init
emilmont 77:869cf507173a 579 #define FMC_NAND_DeInit FSMC_NAND_DeInit
emilmont 77:869cf507173a 580 #define FMC_NAND_ECC_Enable FSMC_NAND_ECC_Enable
emilmont 77:869cf507173a 581 #define FMC_NAND_ECC_Disable FSMC_NAND_ECC_Disable
emilmont 77:869cf507173a 582 #define FMC_NAND_GetECC FSMC_NAND_GetECC
emilmont 77:869cf507173a 583 #define FMC_PCCARD_Init FSMC_PCCARD_Init
emilmont 77:869cf507173a 584 #define FMC_PCCARD_CommonSpace_Timing_Init FSMC_PCCARD_CommonSpace_Timing_Init
emilmont 77:869cf507173a 585 #define FMC_PCCARD_AttributeSpace_Timing_Init FSMC_PCCARD_AttributeSpace_Timing_Init
emilmont 77:869cf507173a 586 #define FMC_PCCARD_IOSpace_Timing_Init FSMC_PCCARD_IOSpace_Timing_Init
emilmont 77:869cf507173a 587 #define FMC_PCCARD_DeInit FSMC_PCCARD_DeInit
emilmont 77:869cf507173a 588
emilmont 77:869cf507173a 589 #define __FMC_NAND_ENABLE __FSMC_NAND_ENABLE
emilmont 77:869cf507173a 590 #define __FMC_NAND_DISABLE __FSMC_NAND_DISABLE
emilmont 77:869cf507173a 591 #define __FMC_PCCARD_ENABLE __FSMC_PCCARD_ENABLE
emilmont 77:869cf507173a 592 #define __FMC_PCCARD_DISABLE __FSMC_PCCARD_DISABLE
emilmont 77:869cf507173a 593 #define __FMC_NAND_ENABLE_IT __FSMC_NAND_ENABLE_IT
emilmont 77:869cf507173a 594 #define __FMC_NAND_DISABLE_IT __FSMC_NAND_DISABLE_IT
emilmont 77:869cf507173a 595 #define __FMC_NAND_GET_FLAG __FSMC_NAND_GET_FLAG
emilmont 77:869cf507173a 596 #define __FMC_NAND_CLEAR_FLAG __FSMC_NAND_CLEAR_FLAG
emilmont 77:869cf507173a 597 #define __FMC_PCCARD_ENABLE_IT __FSMC_PCCARD_ENABLE_IT
emilmont 77:869cf507173a 598 #define __FMC_PCCARD_DISABLE_IT __FSMC_PCCARD_DISABLE_IT
emilmont 77:869cf507173a 599 #define __FMC_PCCARD_GET_FLAG __FSMC_PCCARD_GET_FLAG
emilmont 77:869cf507173a 600 #define __FMC_PCCARD_CLEAR_FLAG __FSMC_PCCARD_CLEAR_FLAG
Kojto 110:165afa46840b 601 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
emilmont 77:869cf507173a 602
emilmont 77:869cf507173a 603 #define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef
emilmont 77:869cf507173a 604 #define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef
Kojto 110:165afa46840b 605 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
emilmont 77:869cf507173a 606 #define FMC_NAND_TypeDef FSMC_NAND_TypeDef
emilmont 77:869cf507173a 607 #define FMC_PCCARD_TypeDef FSMC_PCCARD_TypeDef
Kojto 110:165afa46840b 608 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
emilmont 77:869cf507173a 609
Kojto 122:f9eeca106725 610 #define FMC_NORSRAM_DEVICE FSMC_NORSRAM_DEVICE
Kojto 110:165afa46840b 611 #define FMC_NORSRAM_EXTENDED_DEVICE FSMC_NORSRAM_EXTENDED_DEVICE
Kojto 110:165afa46840b 612 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
Kojto 122:f9eeca106725 613 #define FMC_NAND_DEVICE FSMC_NAND_DEVICE
emilmont 77:869cf507173a 614 #define FMC_PCCARD_DEVICE FSMC_PCCARD_DEVICE
emilmont 77:869cf507173a 615
emilmont 77:869cf507173a 616 #define FMC_NAND_BANK2 FSMC_NAND_BANK2
Kojto 110:165afa46840b 617 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
emilmont 77:869cf507173a 618
Kojto 90:cb3d968589d8 619 #define FMC_NORSRAM_BANK1 FSMC_NORSRAM_BANK1
Kojto 90:cb3d968589d8 620 #define FMC_NORSRAM_BANK2 FSMC_NORSRAM_BANK2
Kojto 90:cb3d968589d8 621 #define FMC_NORSRAM_BANK3 FSMC_NORSRAM_BANK3
Kojto 90:cb3d968589d8 622
emilmont 77:869cf507173a 623 #define FMC_IT_RISING_EDGE FSMC_IT_RISING_EDGE
emilmont 77:869cf507173a 624 #define FMC_IT_LEVEL FSMC_IT_LEVEL
emilmont 77:869cf507173a 625 #define FMC_IT_FALLING_EDGE FSMC_IT_FALLING_EDGE
emilmont 77:869cf507173a 626 #define FMC_IT_REFRESH_ERROR FSMC_IT_REFRESH_ERROR
emilmont 77:869cf507173a 627
emilmont 77:869cf507173a 628 #define FMC_FLAG_RISING_EDGE FSMC_FLAG_RISING_EDGE
emilmont 77:869cf507173a 629 #define FMC_FLAG_LEVEL FSMC_FLAG_LEVEL
emilmont 77:869cf507173a 630 #define FMC_FLAG_FALLING_EDGE FSMC_FLAG_FALLING_EDGE
emilmont 77:869cf507173a 631 #define FMC_FLAG_FEMPT FSMC_FLAG_FEMPT
Kojto 99:dbbf35b96557 632 /**
Kojto 99:dbbf35b96557 633 * @}
Kojto 99:dbbf35b96557 634 */
emilmont 77:869cf507173a 635
Kojto 99:dbbf35b96557 636 /**
Kojto 99:dbbf35b96557 637 * @}
Kojto 99:dbbf35b96557 638 */
Kojto 99:dbbf35b96557 639
Kojto 99:dbbf35b96557 640 /* Private macro -------------------------------------------------------------*/
Kojto 99:dbbf35b96557 641 /** @defgroup FSMC_LL_Private_Macros FSMC Private Macros
Kojto 99:dbbf35b96557 642 * @{
Kojto 99:dbbf35b96557 643 */
Kojto 99:dbbf35b96557 644
Kojto 99:dbbf35b96557 645 /** @defgroup FSMC_LL_NOR_Macros FSMC NOR/SRAM Exported Macros
Kojto 99:dbbf35b96557 646 * @brief macros to handle NOR device enable/disable and read/write operations
Kojto 99:dbbf35b96557 647 * @{
Kojto 99:dbbf35b96557 648 */
Kojto 99:dbbf35b96557 649 /**
Kojto 99:dbbf35b96557 650 * @brief Enable the NORSRAM device access.
Kojto 99:dbbf35b96557 651 * @param __INSTANCE__: FSMC_NORSRAM Instance
Kojto 99:dbbf35b96557 652 * @param __BANK__: FSMC_NORSRAM Bank
Kojto 99:dbbf35b96557 653 * @retval none
Kojto 99:dbbf35b96557 654 */
Kojto 99:dbbf35b96557 655 #define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FSMC_BCR1_MBKEN)
Kojto 99:dbbf35b96557 656
Kojto 99:dbbf35b96557 657 /**
Kojto 99:dbbf35b96557 658 * @brief Disable the NORSRAM device access.
Kojto 99:dbbf35b96557 659 * @param __INSTANCE__: FSMC_NORSRAM Instance
Kojto 99:dbbf35b96557 660 * @param __BANK__: FSMC_NORSRAM Bank
Kojto 99:dbbf35b96557 661 * @retval none
Kojto 99:dbbf35b96557 662 */
Kojto 99:dbbf35b96557 663 #define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FSMC_BCR1_MBKEN)
Kojto 99:dbbf35b96557 664 /**
Kojto 99:dbbf35b96557 665 * @}
Kojto 99:dbbf35b96557 666 */
Kojto 99:dbbf35b96557 667
Kojto 99:dbbf35b96557 668 /** @defgroup FSMC_LL_NAND_Macros FSMC NAND Macros
Kojto 99:dbbf35b96557 669 * @brief macros to handle NAND device enable/disable
Kojto 99:dbbf35b96557 670 * @{
Kojto 99:dbbf35b96557 671 */
Kojto 110:165afa46840b 672 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
Kojto 99:dbbf35b96557 673 /**
Kojto 99:dbbf35b96557 674 * @brief Enable the NAND device access.
Kojto 99:dbbf35b96557 675 * @param __INSTANCE__: FSMC_NAND Instance
Kojto 99:dbbf35b96557 676 * @param __BANK__: FSMC_NAND Bank
Kojto 99:dbbf35b96557 677 * @retval none
Kojto 99:dbbf35b96557 678 */
Kojto 99:dbbf35b96557 679 #define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FSMC_PCR2_PBKEN): \
Kojto 99:dbbf35b96557 680 ((__INSTANCE__)->PCR3 |= FSMC_PCR3_PBKEN))
Kojto 99:dbbf35b96557 681
Kojto 99:dbbf35b96557 682 /**
Kojto 99:dbbf35b96557 683 * @brief Disable the NAND device access.
Kojto 99:dbbf35b96557 684 * @param __INSTANCE__: FSMC_NAND Instance
Kojto 99:dbbf35b96557 685 * @param __BANK__: FSMC_NAND Bank
Kojto 99:dbbf35b96557 686 * @retval none
Kojto 99:dbbf35b96557 687 */
Kojto 99:dbbf35b96557 688 #define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FSMC_PCR2_PBKEN): \
Kojto 99:dbbf35b96557 689 ((__INSTANCE__)->PCR3 &= ~FSMC_PCR3_PBKEN))
Kojto 99:dbbf35b96557 690 /**
Kojto 99:dbbf35b96557 691 * @}
Kojto 99:dbbf35b96557 692 */
Kojto 99:dbbf35b96557 693
Kojto 99:dbbf35b96557 694 /** @defgroup FSMC_LL_PCCARD_Macros FSMC PCCARD Macros
Kojto 99:dbbf35b96557 695 * @brief macros to handle SRAM read/write operations
Kojto 99:dbbf35b96557 696 * @{
Kojto 99:dbbf35b96557 697 */
Kojto 99:dbbf35b96557 698 /**
Kojto 99:dbbf35b96557 699 * @brief Enable the PCCARD device access.
Kojto 99:dbbf35b96557 700 * @param __INSTANCE__: FSMC_PCCARD Instance
Kojto 99:dbbf35b96557 701 * @retval none
Kojto 99:dbbf35b96557 702 */
Kojto 99:dbbf35b96557 703 #define __FSMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FSMC_PCR4_PBKEN)
Kojto 99:dbbf35b96557 704
Kojto 99:dbbf35b96557 705 /**
Kojto 99:dbbf35b96557 706 * @brief Disable the PCCARD device access.
Kojto 99:dbbf35b96557 707 * @param __INSTANCE__: FSMC_PCCARD Instance
Kojto 99:dbbf35b96557 708 * @retval none
Kojto 99:dbbf35b96557 709 */
Kojto 99:dbbf35b96557 710 #define __FSMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FSMC_PCR4_PBKEN)
Kojto 99:dbbf35b96557 711 /**
Kojto 99:dbbf35b96557 712 * @}
Kojto 99:dbbf35b96557 713 */
Kojto 99:dbbf35b96557 714
Kojto 99:dbbf35b96557 715 /** @defgroup FSMC_LL_Flag_Interrupt_Macros FSMC Flag&Interrupt Macros
Kojto 99:dbbf35b96557 716 * @brief macros to handle FSMC flags and interrupts
Kojto 99:dbbf35b96557 717 * @{
Kojto 99:dbbf35b96557 718 */
Kojto 99:dbbf35b96557 719 /**
Kojto 99:dbbf35b96557 720 * @brief Enable the NAND device interrupt.
Kojto 99:dbbf35b96557 721 * @param __INSTANCE__: FSMC_NAND Instance
Kojto 99:dbbf35b96557 722 * @param __BANK__: FSMC_NAND Bank
Kojto 99:dbbf35b96557 723 * @param __INTERRUPT__: FSMC_NAND interrupt
Kojto 99:dbbf35b96557 724 * This parameter can be any combination of the following values:
Kojto 99:dbbf35b96557 725 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
Kojto 99:dbbf35b96557 726 * @arg FSMC_IT_LEVEL: Interrupt level.
Kojto 99:dbbf35b96557 727 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
Kojto 99:dbbf35b96557 728 * @retval None
Kojto 99:dbbf35b96557 729 */
Kojto 99:dbbf35b96557 730 #define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \
Kojto 122:f9eeca106725 731 ((__INSTANCE__)->SR3 |= (__INTERRUPT__)))
Kojto 99:dbbf35b96557 732
Kojto 99:dbbf35b96557 733 /**
Kojto 99:dbbf35b96557 734 * @brief Disable the NAND device interrupt.
Kojto 99:dbbf35b96557 735 * @param __INSTANCE__: FSMC_NAND Instance
Kojto 99:dbbf35b96557 736 * @param __BANK__: FSMC_NAND Bank
Kojto 99:dbbf35b96557 737 * @param __INTERRUPT__: FSMC_NAND interrupt
Kojto 99:dbbf35b96557 738 * This parameter can be any combination of the following values:
Kojto 99:dbbf35b96557 739 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
Kojto 99:dbbf35b96557 740 * @arg FSMC_IT_LEVEL: Interrupt level.
Kojto 99:dbbf35b96557 741 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
Kojto 99:dbbf35b96557 742 * @retval None
Kojto 99:dbbf35b96557 743 */
Kojto 99:dbbf35b96557 744 #define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
Kojto 122:f9eeca106725 745 ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
Kojto 122:f9eeca106725 746
Kojto 99:dbbf35b96557 747 /**
Kojto 99:dbbf35b96557 748 * @brief Get flag status of the NAND device.
Kojto 99:dbbf35b96557 749 * @param __INSTANCE__: FSMC_NAND Instance
Kojto 99:dbbf35b96557 750 * @param __BANK__ : FSMC_NAND Bank
Kojto 99:dbbf35b96557 751 * @param __FLAG__ : FSMC_NAND flag
Kojto 99:dbbf35b96557 752 * This parameter can be any combination of the following values:
Kojto 99:dbbf35b96557 753 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
Kojto 99:dbbf35b96557 754 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
Kojto 99:dbbf35b96557 755 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
Kojto 99:dbbf35b96557 756 * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
Kojto 99:dbbf35b96557 757 * @retval The state of FLAG (SET or RESET).
Kojto 99:dbbf35b96557 758 */
Kojto 99:dbbf35b96557 759 #define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
Kojto 122:f9eeca106725 760 (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
Kojto 122:f9eeca106725 761
Kojto 99:dbbf35b96557 762 /**
Kojto 99:dbbf35b96557 763 * @brief Clear flag status of the NAND device.
Kojto 99:dbbf35b96557 764 * @param __INSTANCE__: FSMC_NAND Instance
Kojto 99:dbbf35b96557 765 * @param __BANK__: FSMC_NAND Bank
Kojto 99:dbbf35b96557 766 * @param __FLAG__: FSMC_NAND flag
Kojto 99:dbbf35b96557 767 * This parameter can be any combination of the following values:
Kojto 99:dbbf35b96557 768 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
Kojto 99:dbbf35b96557 769 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
Kojto 99:dbbf35b96557 770 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
Kojto 99:dbbf35b96557 771 * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
Kojto 99:dbbf35b96557 772 * @retval None
Kojto 99:dbbf35b96557 773 */
Kojto 99:dbbf35b96557 774 #define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
Kojto 122:f9eeca106725 775 ((__INSTANCE__)->SR3 &= ~(__FLAG__)))
Kojto 122:f9eeca106725 776
Kojto 99:dbbf35b96557 777 /**
Kojto 99:dbbf35b96557 778 * @brief Enable the PCCARD device interrupt.
Kojto 99:dbbf35b96557 779 * @param __INSTANCE__: FSMC_PCCARD Instance
Kojto 99:dbbf35b96557 780 * @param __INTERRUPT__: FSMC_PCCARD interrupt
Kojto 99:dbbf35b96557 781 * This parameter can be any combination of the following values:
Kojto 99:dbbf35b96557 782 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
Kojto 99:dbbf35b96557 783 * @arg FSMC_IT_LEVEL: Interrupt level.
Kojto 99:dbbf35b96557 784 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
Kojto 99:dbbf35b96557 785 * @retval None
Kojto 99:dbbf35b96557 786 */
Kojto 99:dbbf35b96557 787 #define __FSMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 |= (__INTERRUPT__))
Kojto 99:dbbf35b96557 788
Kojto 99:dbbf35b96557 789 /**
Kojto 99:dbbf35b96557 790 * @brief Disable the PCCARD device interrupt.
Kojto 99:dbbf35b96557 791 * @param __INSTANCE__: FSMC_PCCARD Instance
Kojto 99:dbbf35b96557 792 * @param __INTERRUPT__: FSMC_PCCARD interrupt
Kojto 99:dbbf35b96557 793 * This parameter can be any combination of the following values:
Kojto 99:dbbf35b96557 794 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
Kojto 99:dbbf35b96557 795 * @arg FSMC_IT_LEVEL: Interrupt level.
Kojto 99:dbbf35b96557 796 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
Kojto 99:dbbf35b96557 797 * @retval None
Kojto 99:dbbf35b96557 798 */
Kojto 99:dbbf35b96557 799 #define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
Kojto 99:dbbf35b96557 800
Kojto 99:dbbf35b96557 801 /**
Kojto 99:dbbf35b96557 802 * @brief Get flag status of the PCCARD device.
Kojto 99:dbbf35b96557 803 * @param __INSTANCE__: FSMC_PCCARD Instance
Kojto 99:dbbf35b96557 804 * @param __FLAG__: FSMC_PCCARD flag
Kojto 99:dbbf35b96557 805 * This parameter can be any combination of the following values:
Kojto 99:dbbf35b96557 806 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
Kojto 99:dbbf35b96557 807 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
Kojto 99:dbbf35b96557 808 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
Kojto 99:dbbf35b96557 809 * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
Kojto 99:dbbf35b96557 810 * @retval The state of FLAG (SET or RESET).
Kojto 99:dbbf35b96557 811 */
Kojto 99:dbbf35b96557 812 #define __FSMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
Kojto 99:dbbf35b96557 813
Kojto 99:dbbf35b96557 814 /**
Kojto 99:dbbf35b96557 815 * @brief Clear flag status of the PCCARD device.
Kojto 99:dbbf35b96557 816 * @param __INSTANCE__: FSMC_PCCARD Instance
Kojto 99:dbbf35b96557 817 * @param __FLAG__: FSMC_PCCARD flag
Kojto 99:dbbf35b96557 818 * This parameter can be any combination of the following values:
Kojto 99:dbbf35b96557 819 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
Kojto 99:dbbf35b96557 820 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
Kojto 99:dbbf35b96557 821 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
Kojto 99:dbbf35b96557 822 * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
Kojto 99:dbbf35b96557 823 * @retval None
Kojto 99:dbbf35b96557 824 */
Kojto 99:dbbf35b96557 825 #define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
Kojto 99:dbbf35b96557 826 /**
Kojto 99:dbbf35b96557 827 * @}
Kojto 99:dbbf35b96557 828 */
Kojto 110:165afa46840b 829 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
Kojto 99:dbbf35b96557 830
Kojto 99:dbbf35b96557 831 /** @defgroup FSMC_LL_Assert_Macros FSMC Assert Macros
Kojto 99:dbbf35b96557 832 * @{
Kojto 99:dbbf35b96557 833 */
Kojto 99:dbbf35b96557 834 #define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) || \
Kojto 99:dbbf35b96557 835 ((__BANK__) == FSMC_NORSRAM_BANK2) || \
Kojto 99:dbbf35b96557 836 ((__BANK__) == FSMC_NORSRAM_BANK3) || \
Kojto 99:dbbf35b96557 837 ((__BANK__) == FSMC_NORSRAM_BANK4))
Kojto 99:dbbf35b96557 838
Kojto 99:dbbf35b96557 839 #define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \
Kojto 99:dbbf35b96557 840 ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE))
Kojto 99:dbbf35b96557 841
Kojto 99:dbbf35b96557 842 #define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \
Kojto 99:dbbf35b96557 843 ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \
Kojto 99:dbbf35b96557 844 ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR))
Kojto 99:dbbf35b96557 845
Kojto 99:dbbf35b96557 846 #define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) || \
Kojto 99:dbbf35b96557 847 ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \
Kojto 99:dbbf35b96557 848 ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32))
Kojto 99:dbbf35b96557 849
Kojto 99:dbbf35b96557 850 #define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \
Kojto 99:dbbf35b96557 851 ((__MODE__) == FSMC_ACCESS_MODE_B) || \
Kojto 99:dbbf35b96557 852 ((__MODE__) == FSMC_ACCESS_MODE_C) || \
Kojto 99:dbbf35b96557 853 ((__MODE__) == FSMC_ACCESS_MODE_D))
Kojto 99:dbbf35b96557 854
Kojto 99:dbbf35b96557 855 #define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_NAND_BANK2) || \
Kojto 99:dbbf35b96557 856 ((BANK) == FSMC_NAND_BANK3))
Kojto 99:dbbf35b96557 857
Kojto 99:dbbf35b96557 858 #define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
Kojto 99:dbbf35b96557 859 ((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE))
Kojto 99:dbbf35b96557 860
Kojto 99:dbbf35b96557 861 #define IS_FSMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
Kojto 99:dbbf35b96557 862 ((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16))
Kojto 99:dbbf35b96557 863
Kojto 99:dbbf35b96557 864 #define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_NAND_ECC_DISABLE) || \
Kojto 99:dbbf35b96557 865 ((STATE) == FSMC_NAND_ECC_ENABLE))
Kojto 99:dbbf35b96557 866
Kojto 99:dbbf35b96557 867 #define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
Kojto 99:dbbf35b96557 868 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
Kojto 99:dbbf35b96557 869 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
Kojto 99:dbbf35b96557 870 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
Kojto 99:dbbf35b96557 871 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
Kojto 99:dbbf35b96557 872 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE))
Kojto 99:dbbf35b96557 873
Kojto 122:f9eeca106725 874 #define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 255U)
Kojto 99:dbbf35b96557 875
Kojto 122:f9eeca106725 876 #define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 255U)
Kojto 99:dbbf35b96557 877
Kojto 122:f9eeca106725 878 #define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 255U)
Kojto 99:dbbf35b96557 879
Kojto 122:f9eeca106725 880 #define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 255U)
Kojto 99:dbbf35b96557 881
Kojto 122:f9eeca106725 882 #define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 255U)
Kojto 99:dbbf35b96557 883
Kojto 122:f9eeca106725 884 #define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 255U)
Kojto 99:dbbf35b96557 885
Kojto 99:dbbf35b96557 886 #define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE)
Kojto 99:dbbf35b96557 887
Kojto 99:dbbf35b96557 888 #define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE)
Kojto 99:dbbf35b96557 889
Kojto 99:dbbf35b96557 890 #define IS_FSMC_NAND_DEVICE(INSTANCE) ((INSTANCE) == FSMC_NAND_DEVICE)
Kojto 99:dbbf35b96557 891
Kojto 99:dbbf35b96557 892 #define IS_FSMC_PCCARD_DEVICE(INSTANCE) ((INSTANCE) == FSMC_PCCARD_DEVICE)
Kojto 99:dbbf35b96557 893
Kojto 99:dbbf35b96557 894 #define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \
Kojto 99:dbbf35b96557 895 ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE))
Kojto 99:dbbf35b96557 896
Kojto 99:dbbf35b96557 897 #define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \
Kojto 99:dbbf35b96557 898 ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH))
Kojto 99:dbbf35b96557 899
Kojto 99:dbbf35b96557 900 #define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \
Kojto 99:dbbf35b96557 901 ((__MODE__) == FSMC_WRAP_MODE_ENABLE))
Kojto 99:dbbf35b96557 902
Kojto 99:dbbf35b96557 903 #define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \
Kojto 99:dbbf35b96557 904 ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS))
Kojto 99:dbbf35b96557 905
Kojto 99:dbbf35b96557 906 #define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \
Kojto 99:dbbf35b96557 907 ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE))
Kojto 99:dbbf35b96557 908
Kojto 99:dbbf35b96557 909 #define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \
Kojto 99:dbbf35b96557 910 ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE))
Kojto 99:dbbf35b96557 911
Kojto 99:dbbf35b96557 912 #define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \
Kojto 99:dbbf35b96557 913 ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE))
Kojto 99:dbbf35b96557 914
Kojto 99:dbbf35b96557 915 #define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \
Kojto 99:dbbf35b96557 916 ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE))
Kojto 99:dbbf35b96557 917
Kojto 122:f9eeca106725 918 #define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))
Kojto 99:dbbf35b96557 919
Kojto 99:dbbf35b96557 920 #define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \
Kojto 99:dbbf35b96557 921 ((__BURST__) == FSMC_WRITE_BURST_ENABLE))
Kojto 99:dbbf35b96557 922
Kojto 122:f9eeca106725 923 #define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U)
Kojto 99:dbbf35b96557 924
Kojto 122:f9eeca106725 925 #define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U))
Kojto 99:dbbf35b96557 926
Kojto 122:f9eeca106725 927 #define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U))
Kojto 99:dbbf35b96557 928
Kojto 122:f9eeca106725 929 #define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U)
Kojto 99:dbbf35b96557 930
Kojto 99:dbbf35b96557 931 #define IS_FSMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
Kojto 99:dbbf35b96557 932 ((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
Kojto 99:dbbf35b96557 933
Kojto 122:f9eeca106725 934 #define IS_FSMC_CLK_DIV(DIV) (((DIV) > 1U) && ((DIV) <= 16U))
Kojto 122:f9eeca106725 935
Kojto 122:f9eeca106725 936 #define IS_FSMC_PAGESIZE(SIZE) (((SIZE) == FSMC_PAGE_SIZE_NONE) || \
Kojto 122:f9eeca106725 937 ((SIZE) == FSMC_PAGE_SIZE_128) || \
Kojto 122:f9eeca106725 938 ((SIZE) == FSMC_PAGE_SIZE_256) || \
Kojto 122:f9eeca106725 939 ((SIZE) == FSMC_PAGE_SIZE_1024))
Kojto 122:f9eeca106725 940
Kojto 122:f9eeca106725 941 #define IS_FSMC_WRITE_FIFO(FIFO) (((FIFO) == FSMC_WRITE_FIFO_DISABLE) || \
Kojto 122:f9eeca106725 942 ((FIFO) == FSMC_WRITE_FIFO_ENABLE))
Kojto 99:dbbf35b96557 943
Kojto 99:dbbf35b96557 944 /**
Kojto 99:dbbf35b96557 945 * @}
Kojto 99:dbbf35b96557 946 */
Kojto 99:dbbf35b96557 947 /**
Kojto 99:dbbf35b96557 948 * @}
Kojto 99:dbbf35b96557 949 */
Kojto 99:dbbf35b96557 950
Kojto 99:dbbf35b96557 951 /* Private functions ---------------------------------------------------------*/
Kojto 99:dbbf35b96557 952 /** @defgroup FSMC_LL_Private_Functions FSMC LL Private Functions
Kojto 99:dbbf35b96557 953 * @{
Kojto 99:dbbf35b96557 954 */
Kojto 99:dbbf35b96557 955
Kojto 99:dbbf35b96557 956 /** @defgroup FSMC_LL_NORSRAM NOR SRAM
Kojto 99:dbbf35b96557 957 * @{
Kojto 99:dbbf35b96557 958 */
Kojto 99:dbbf35b96557 959
Kojto 99:dbbf35b96557 960 /** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
Kojto 99:dbbf35b96557 961 * @{
Kojto 99:dbbf35b96557 962 */
Kojto 99:dbbf35b96557 963 HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef *Init);
Kojto 99:dbbf35b96557 964 HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
Kojto 99:dbbf35b96557 965 HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
Kojto 99:dbbf35b96557 966 HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
Kojto 99:dbbf35b96557 967 /**
Kojto 99:dbbf35b96557 968 * @}
Kojto 99:dbbf35b96557 969 */
Kojto 99:dbbf35b96557 970
Kojto 99:dbbf35b96557 971 /** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
Kojto 99:dbbf35b96557 972 * @{
Kojto 99:dbbf35b96557 973 */
Kojto 99:dbbf35b96557 974 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
Kojto 99:dbbf35b96557 975 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
Kojto 99:dbbf35b96557 976 /**
Kojto 99:dbbf35b96557 977 * @}
Kojto 99:dbbf35b96557 978 */
Kojto 99:dbbf35b96557 979 /**
Kojto 99:dbbf35b96557 980 * @}
Kojto 99:dbbf35b96557 981 */
Kojto 99:dbbf35b96557 982
Kojto 110:165afa46840b 983 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
Kojto 99:dbbf35b96557 984 /** @defgroup FSMC_LL_NAND NAND
Kojto 99:dbbf35b96557 985 * @{
Kojto 99:dbbf35b96557 986 */
Kojto 99:dbbf35b96557 987 /** @defgroup FSMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
Kojto 99:dbbf35b96557 988 * @{
Kojto 99:dbbf35b96557 989 */
Kojto 99:dbbf35b96557 990 HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init);
Kojto 99:dbbf35b96557 991 HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
Kojto 99:dbbf35b96557 992 HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
Kojto 99:dbbf35b96557 993 HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank);
Kojto 99:dbbf35b96557 994 /**
Kojto 99:dbbf35b96557 995 * @}
Kojto 99:dbbf35b96557 996 */
Kojto 99:dbbf35b96557 997
Kojto 99:dbbf35b96557 998 /** @defgroup FSMC_LL_NAND_Private_Functions_Group2 NAND Control functions
Kojto 99:dbbf35b96557 999 * @{
Kojto 99:dbbf35b96557 1000 */
Kojto 99:dbbf35b96557 1001 HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
Kojto 99:dbbf35b96557 1002 HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
Kojto 99:dbbf35b96557 1003 HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
Kojto 99:dbbf35b96557 1004 /**
Kojto 99:dbbf35b96557 1005 * @}
Kojto 99:dbbf35b96557 1006 */
Kojto 99:dbbf35b96557 1007 /**
Kojto 99:dbbf35b96557 1008 * @}
Kojto 99:dbbf35b96557 1009 */
Kojto 99:dbbf35b96557 1010
Kojto 99:dbbf35b96557 1011 /** @defgroup FSMC_LL_PCCARD PCCARD
Kojto 99:dbbf35b96557 1012 * @{
Kojto 99:dbbf35b96557 1013 */
Kojto 99:dbbf35b96557 1014 /** @defgroup FSMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions
Kojto 99:dbbf35b96557 1015 * @{
Kojto 99:dbbf35b96557 1016 */
Kojto 99:dbbf35b96557 1017 HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init);
Kojto 99:dbbf35b96557 1018 HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
Kojto 99:dbbf35b96557 1019 HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
Kojto 99:dbbf35b96557 1020 HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
Kojto 99:dbbf35b96557 1021 HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device);
Kojto 99:dbbf35b96557 1022 /**
Kojto 99:dbbf35b96557 1023 * @}
Kojto 99:dbbf35b96557 1024 */
Kojto 99:dbbf35b96557 1025 /**
Kojto 99:dbbf35b96557 1026 * @}
Kojto 99:dbbf35b96557 1027 */
Kojto 110:165afa46840b 1028 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
Kojto 99:dbbf35b96557 1029
Kojto 99:dbbf35b96557 1030 /**
Kojto 99:dbbf35b96557 1031 * @}
Kojto 99:dbbf35b96557 1032 */
Kojto 122:f9eeca106725 1033 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
emilmont 77:869cf507173a 1034
emilmont 77:869cf507173a 1035 /**
emilmont 77:869cf507173a 1036 * @}
emilmont 77:869cf507173a 1037 */
emilmont 77:869cf507173a 1038
emilmont 77:869cf507173a 1039 /**
emilmont 77:869cf507173a 1040 * @}
emilmont 77:869cf507173a 1041 */
emilmont 77:869cf507173a 1042
emilmont 77:869cf507173a 1043 #ifdef __cplusplus
emilmont 77:869cf507173a 1044 }
emilmont 77:869cf507173a 1045 #endif
emilmont 77:869cf507173a 1046
emilmont 77:869cf507173a 1047 #endif /* __STM32F4xx_LL_FSMC_H */
emilmont 77:869cf507173a 1048
emilmont 77:869cf507173a 1049 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/