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TARGET_DISCO_F469NI/stm32f469xx.h@122:f9eeca106725, 2016-07-07 (annotated)

Committer:: Kojto
Date:: Thu Jul 07 14:34:11 2016 +0100
Revision:: 122:f9eeca106725
Parent:: 110:165afa46840b

Release 122 of the mbed library



Changes:

- new targets - Nucleo L432KC, Beetle, Nucleo F446ZE, Nucleo L011K4

- Thread safety addition - mbed API should contain a statement about thread safety

- critical section API addition

- CAS API (core_util_atomic_incr/decr)

- DEVICE_ are generated from targets.json file, device.h deprecated

- Callback replaces FunctionPointer to provide std like interface

- mbed HAL API docs improvements

- toolchain - prexif attributes with MBED_

            - add new attributes - packed, weak, forcedinline, align

- target.json - contains targets definitions

- ST - L1XX - Cube update to 1.5

     - SPI clock selection fix (clock from APB domain)

     - F7 - Cube update v1.4.0

     - L0 -  baudrate init fix

     - L1 - Cube update v1.5

     - F3 - baudrate init fix, 3 targets CAN support

     - F4 - Cube update v1.12.0, 3 targets CAN support

     - L4XX - Cube update v1.5.1

     - F0 - update Cube to v1.5.0

     - L4 - 2 targets (L476RG/VG) CAN support

- NXP - pwm clock fix for KSDK2 MCU

      - LPC2368 - remove ARM toolchain support - due to regression

      - KSDK2 - fix SPI , I2C address and repeat start

- Silabs - some fixes backported from mbed 3

- Renesas - RZ_A1H - SystemCoreClockUpdate addition

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	110:165afa46840b	1	/**
Kojto	110:165afa46840b	2	******************************************************************************
Kojto	110:165afa46840b	3	* @file stm32f469xx.h
Kojto	110:165afa46840b	4	* @author MCD Application Team
Kojto	122:f9eeca106725	5	* @version V2.5.0
Kojto	122:f9eeca106725	6	* @date 22-April-2016
Kojto	110:165afa46840b	7	* @brief CMSIS STM32F469xx Device Peripheral Access Layer Header File.
Kojto	110:165afa46840b	8	*
Kojto	110:165afa46840b	9	* This file contains:
Kojto	110:165afa46840b	10	* - Data structures and the address mapping for all peripherals
Kojto	122:f9eeca106725	11	* - peripherals registers declarations and bits definition
Kojto	122:f9eeca106725	12	* - Macros to access peripheral's registers hardware
Kojto	110:165afa46840b	13	*
Kojto	110:165afa46840b	14	******************************************************************************
Kojto	110:165afa46840b	15	* @attention
Kojto	110:165afa46840b	16	*
Kojto	122:f9eeca106725	17	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
Kojto	110:165afa46840b	18	*
Kojto	110:165afa46840b	19	* Redistribution and use in source and binary forms, with or without modification,
Kojto	110:165afa46840b	20	* are permitted provided that the following conditions are met:
Kojto	110:165afa46840b	21	* 1. Redistributions of source code must retain the above copyright notice,
Kojto	110:165afa46840b	22	* this list of conditions and the following disclaimer.
Kojto	110:165afa46840b	23	* 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto	110:165afa46840b	24	* this list of conditions and the following disclaimer in the documentation
Kojto	110:165afa46840b	25	* and/or other materials provided with the distribution.
Kojto	110:165afa46840b	26	* 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto	110:165afa46840b	27	* may be used to endorse or promote products derived from this software
Kojto	110:165afa46840b	28	* without specific prior written permission.
Kojto	110:165afa46840b	29	*
Kojto	110:165afa46840b	30	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto	110:165afa46840b	31	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto	110:165afa46840b	32	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto	110:165afa46840b	33	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto	110:165afa46840b	34	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto	110:165afa46840b	35	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto	110:165afa46840b	36	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto	110:165afa46840b	37	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto	110:165afa46840b	38	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto	110:165afa46840b	39	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto	110:165afa46840b	40	*
Kojto	110:165afa46840b	41	******************************************************************************
Kojto	110:165afa46840b	42	*/
Kojto	110:165afa46840b	43
Kojto	110:165afa46840b	44	/** @addtogroup CMSIS_Device
Kojto	110:165afa46840b	45	* @{
Kojto	110:165afa46840b	46	*/
Kojto	110:165afa46840b	47
Kojto	110:165afa46840b	48	/** @addtogroup stm32f469xx
Kojto	110:165afa46840b	49	* @{
Kojto	110:165afa46840b	50	*/
Kojto	110:165afa46840b	51
Kojto	110:165afa46840b	52	#ifndef __STM32F469xx_H
Kojto	110:165afa46840b	53	#define __STM32F469xx_H
Kojto	110:165afa46840b	54
Kojto	110:165afa46840b	55	#ifdef __cplusplus
Kojto	110:165afa46840b	56	extern "C" {
Kojto	110:165afa46840b	57	#endif /* __cplusplus */
Kojto	110:165afa46840b	58
Kojto	110:165afa46840b	59	/** @addtogroup Configuration_section_for_CMSIS
Kojto	110:165afa46840b	60	* @{
Kojto	110:165afa46840b	61	*/
Kojto	110:165afa46840b	62
Kojto	110:165afa46840b	63	/**
Kojto	110:165afa46840b	64	* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
Kojto	110:165afa46840b	65	*/
Kojto	122:f9eeca106725	66	#define __CM4_REV 0x0001U /!< Core revision r0p1 /
Kojto	122:f9eeca106725	67	#define __MPU_PRESENT 1U /!< STM32F4XX provides an MPU /
Kojto	122:f9eeca106725	68	#define __NVIC_PRIO_BITS 4U /!< STM32F4XX uses 4 Bits for the Priority Levels /
Kojto	122:f9eeca106725	69	#define __Vendor_SysTickConfig 0U /!< Set to 1 if different SysTick Config is used /
Kojto	122:f9eeca106725	70	#ifndef __FPU_PRESENT
Kojto	122:f9eeca106725	71	#define __FPU_PRESENT 1U /!< FPU present /
Kojto	122:f9eeca106725	72	#endif /* __FPU_PRESENT */
Kojto	110:165afa46840b	73
Kojto	110:165afa46840b	74	/**
Kojto	110:165afa46840b	75	* @}
Kojto	110:165afa46840b	76	*/
Kojto	110:165afa46840b	77
Kojto	110:165afa46840b	78	/** @addtogroup Peripheral_interrupt_number_definition
Kojto	110:165afa46840b	79	* @{
Kojto	110:165afa46840b	80	*/
Kojto	110:165afa46840b	81
Kojto	110:165afa46840b	82	/**
Kojto	110:165afa46840b	83	* @brief STM32F4XX Interrupt Number Definition, according to the selected device
Kojto	110:165afa46840b	84	* in @ref Library_configuration_section
Kojto	110:165afa46840b	85	*/
Kojto	110:165afa46840b	86	typedef enum
Kojto	110:165afa46840b	87	{
Kojto	110:165afa46840b	88	/**** Cortex-M4 Processor Exceptions Numbers **************************************************************/
Kojto	110:165afa46840b	89	NonMaskableInt_IRQn = -14, /!< 2 Non Maskable Interrupt /
Kojto	110:165afa46840b	90	MemoryManagement_IRQn = -12, /!< 4 Cortex-M4 Memory Management Interrupt /
Kojto	110:165afa46840b	91	BusFault_IRQn = -11, /!< 5 Cortex-M4 Bus Fault Interrupt /
Kojto	110:165afa46840b	92	UsageFault_IRQn = -10, /!< 6 Cortex-M4 Usage Fault Interrupt /
Kojto	110:165afa46840b	93	SVCall_IRQn = -5, /!< 11 Cortex-M4 SV Call Interrupt /
Kojto	110:165afa46840b	94	DebugMonitor_IRQn = -4, /!< 12 Cortex-M4 Debug Monitor Interrupt /
Kojto	110:165afa46840b	95	PendSV_IRQn = -2, /!< 14 Cortex-M4 Pend SV Interrupt /
Kojto	110:165afa46840b	96	SysTick_IRQn = -1, /!< 15 Cortex-M4 System Tick Interrupt /
Kojto	110:165afa46840b	97	/**** STM32 specific Interrupt Numbers ********************************************************************/
Kojto	110:165afa46840b	98	WWDG_IRQn = 0, /!< Window WatchDog Interrupt /
Kojto	110:165afa46840b	99	PVD_IRQn = 1, /!< PVD through EXTI Line detection Interrupt /
Kojto	110:165afa46840b	100	TAMP_STAMP_IRQn = 2, /!< Tamper and TimeStamp interrupts through the EXTI line /
Kojto	110:165afa46840b	101	RTC_WKUP_IRQn = 3, /!< RTC Wakeup interrupt through the EXTI line /
Kojto	110:165afa46840b	102	FLASH_IRQn = 4, /!< FLASH global Interrupt /
Kojto	110:165afa46840b	103	RCC_IRQn = 5, /!< RCC global Interrupt /
Kojto	110:165afa46840b	104	EXTI0_IRQn = 6, /!< EXTI Line0 Interrupt /
Kojto	110:165afa46840b	105	EXTI1_IRQn = 7, /!< EXTI Line1 Interrupt /
Kojto	110:165afa46840b	106	EXTI2_IRQn = 8, /!< EXTI Line2 Interrupt /
Kojto	110:165afa46840b	107	EXTI3_IRQn = 9, /!< EXTI Line3 Interrupt /
Kojto	110:165afa46840b	108	EXTI4_IRQn = 10, /!< EXTI Line4 Interrupt /
Kojto	110:165afa46840b	109	DMA1_Stream0_IRQn = 11, /!< DMA1 Stream 0 global Interrupt /
Kojto	110:165afa46840b	110	DMA1_Stream1_IRQn = 12, /!< DMA1 Stream 1 global Interrupt /
Kojto	110:165afa46840b	111	DMA1_Stream2_IRQn = 13, /!< DMA1 Stream 2 global Interrupt /
Kojto	110:165afa46840b	112	DMA1_Stream3_IRQn = 14, /!< DMA1 Stream 3 global Interrupt /
Kojto	110:165afa46840b	113	DMA1_Stream4_IRQn = 15, /!< DMA1 Stream 4 global Interrupt /
Kojto	110:165afa46840b	114	DMA1_Stream5_IRQn = 16, /!< DMA1 Stream 5 global Interrupt /
Kojto	110:165afa46840b	115	DMA1_Stream6_IRQn = 17, /!< DMA1 Stream 6 global Interrupt /
Kojto	110:165afa46840b	116	ADC_IRQn = 18, /!< ADC1, ADC2 and ADC3 global Interrupts /
Kojto	110:165afa46840b	117	CAN1_TX_IRQn = 19, /!< CAN1 TX Interrupt /
Kojto	110:165afa46840b	118	CAN1_RX0_IRQn = 20, /!< CAN1 RX0 Interrupt /
Kojto	110:165afa46840b	119	CAN1_RX1_IRQn = 21, /!< CAN1 RX1 Interrupt /
Kojto	110:165afa46840b	120	CAN1_SCE_IRQn = 22, /!< CAN1 SCE Interrupt /
Kojto	110:165afa46840b	121	EXTI9_5_IRQn = 23, /!< External Line[9:5] Interrupts /
Kojto	110:165afa46840b	122	TIM1_BRK_TIM9_IRQn = 24, /!< TIM1 Break interrupt and TIM9 global interrupt /
Kojto	110:165afa46840b	123	TIM1_UP_TIM10_IRQn = 25, /!< TIM1 Update Interrupt and TIM10 global interrupt /
Kojto	110:165afa46840b	124	TIM1_TRG_COM_TIM11_IRQn = 26, /!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt /
Kojto	110:165afa46840b	125	TIM1_CC_IRQn = 27, /!< TIM1 Capture Compare Interrupt /
Kojto	110:165afa46840b	126	TIM2_IRQn = 28, /!< TIM2 global Interrupt /
Kojto	110:165afa46840b	127	TIM3_IRQn = 29, /!< TIM3 global Interrupt /
Kojto	110:165afa46840b	128	TIM4_IRQn = 30, /!< TIM4 global Interrupt /
Kojto	110:165afa46840b	129	I2C1_EV_IRQn = 31, /!< I2C1 Event Interrupt /
Kojto	110:165afa46840b	130	I2C1_ER_IRQn = 32, /!< I2C1 Error Interrupt /
Kojto	110:165afa46840b	131	I2C2_EV_IRQn = 33, /!< I2C2 Event Interrupt /
Kojto	110:165afa46840b	132	I2C2_ER_IRQn = 34, /!< I2C2 Error Interrupt /
Kojto	110:165afa46840b	133	SPI1_IRQn = 35, /!< SPI1 global Interrupt /
Kojto	110:165afa46840b	134	SPI2_IRQn = 36, /!< SPI2 global Interrupt /
Kojto	110:165afa46840b	135	USART1_IRQn = 37, /!< USART1 global Interrupt /
Kojto	110:165afa46840b	136	USART2_IRQn = 38, /!< USART2 global Interrupt /
Kojto	110:165afa46840b	137	USART3_IRQn = 39, /!< USART3 global Interrupt /
Kojto	110:165afa46840b	138	EXTI15_10_IRQn = 40, /!< External Line[15:10] Interrupts /
Kojto	110:165afa46840b	139	RTC_Alarm_IRQn = 41, /!< RTC Alarm (A and B) through EXTI Line Interrupt /
Kojto	110:165afa46840b	140	OTG_FS_WKUP_IRQn = 42, /!< USB OTG FS Wakeup through EXTI line interrupt /
Kojto	110:165afa46840b	141	TIM8_BRK_TIM12_IRQn = 43, /!< TIM8 Break Interrupt and TIM12 global interrupt /
Kojto	110:165afa46840b	142	TIM8_UP_TIM13_IRQn = 44, /!< TIM8 Update Interrupt and TIM13 global interrupt /
Kojto	110:165afa46840b	143	TIM8_TRG_COM_TIM14_IRQn = 45, /!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt /
Kojto	110:165afa46840b	144	TIM8_CC_IRQn = 46, /!< TIM8 Capture Compare global interrupt /
Kojto	110:165afa46840b	145	DMA1_Stream7_IRQn = 47, /!< DMA1 Stream7 Interrupt /
Kojto	110:165afa46840b	146	FMC_IRQn = 48, /!< FMC global Interrupt /
Kojto	110:165afa46840b	147	SDIO_IRQn = 49, /!< SDIO global Interrupt /
Kojto	110:165afa46840b	148	TIM5_IRQn = 50, /!< TIM5 global Interrupt /
Kojto	110:165afa46840b	149	SPI3_IRQn = 51, /!< SPI3 global Interrupt /
Kojto	110:165afa46840b	150	UART4_IRQn = 52, /!< UART4 global Interrupt /
Kojto	110:165afa46840b	151	UART5_IRQn = 53, /!< UART5 global Interrupt /
Kojto	110:165afa46840b	152	TIM6_DAC_IRQn = 54, /!< TIM6 global and DAC1&2 underrun error interrupts /
Kojto	110:165afa46840b	153	TIM7_IRQn = 55, /!< TIM7 global interrupt /
Kojto	110:165afa46840b	154	DMA2_Stream0_IRQn = 56, /!< DMA2 Stream 0 global Interrupt /
Kojto	110:165afa46840b	155	DMA2_Stream1_IRQn = 57, /!< DMA2 Stream 1 global Interrupt /
Kojto	110:165afa46840b	156	DMA2_Stream2_IRQn = 58, /!< DMA2 Stream 2 global Interrupt /
Kojto	110:165afa46840b	157	DMA2_Stream3_IRQn = 59, /!< DMA2 Stream 3 global Interrupt /
Kojto	110:165afa46840b	158	DMA2_Stream4_IRQn = 60, /!< DMA2 Stream 4 global Interrupt /
Kojto	110:165afa46840b	159	ETH_IRQn = 61, /!< Ethernet global Interrupt /
Kojto	110:165afa46840b	160	ETH_WKUP_IRQn = 62, /!< Ethernet Wakeup through EXTI line Interrupt /
Kojto	110:165afa46840b	161	CAN2_TX_IRQn = 63, /!< CAN2 TX Interrupt /
Kojto	110:165afa46840b	162	CAN2_RX0_IRQn = 64, /!< CAN2 RX0 Interrupt /
Kojto	110:165afa46840b	163	CAN2_RX1_IRQn = 65, /!< CAN2 RX1 Interrupt /
Kojto	110:165afa46840b	164	CAN2_SCE_IRQn = 66, /!< CAN2 SCE Interrupt /
Kojto	110:165afa46840b	165	OTG_FS_IRQn = 67, /!< USB OTG FS global Interrupt /
Kojto	110:165afa46840b	166	DMA2_Stream5_IRQn = 68, /!< DMA2 Stream 5 global interrupt /
Kojto	110:165afa46840b	167	DMA2_Stream6_IRQn = 69, /!< DMA2 Stream 6 global interrupt /
Kojto	110:165afa46840b	168	DMA2_Stream7_IRQn = 70, /!< DMA2 Stream 7 global interrupt /
Kojto	110:165afa46840b	169	USART6_IRQn = 71, /!< USART6 global interrupt /
Kojto	110:165afa46840b	170	I2C3_EV_IRQn = 72, /!< I2C3 event interrupt /
Kojto	110:165afa46840b	171	I2C3_ER_IRQn = 73, /!< I2C3 error interrupt /
Kojto	110:165afa46840b	172	OTG_HS_EP1_OUT_IRQn = 74, /!< USB OTG HS End Point 1 Out global interrupt /
Kojto	110:165afa46840b	173	OTG_HS_EP1_IN_IRQn = 75, /!< USB OTG HS End Point 1 In global interrupt /
Kojto	110:165afa46840b	174	OTG_HS_WKUP_IRQn = 76, /!< USB OTG HS Wakeup through EXTI interrupt /
Kojto	110:165afa46840b	175	OTG_HS_IRQn = 77, /!< USB OTG HS global interrupt /
Kojto	110:165afa46840b	176	DCMI_IRQn = 78, /!< DCMI global interrupt /
Kojto	110:165afa46840b	177	HASH_RNG_IRQn = 80, /!< Hash and Rng global interrupt /
Kojto	110:165afa46840b	178	FPU_IRQn = 81, /!< FPU global interrupt /
Kojto	110:165afa46840b	179	UART7_IRQn = 82, /!< UART7 global interrupt /
Kojto	110:165afa46840b	180	UART8_IRQn = 83, /!< UART8 global interrupt /
Kojto	110:165afa46840b	181	SPI4_IRQn = 84, /!< SPI4 global Interrupt /
Kojto	110:165afa46840b	182	SPI5_IRQn = 85, /!< SPI5 global Interrupt /
Kojto	110:165afa46840b	183	SPI6_IRQn = 86, /!< SPI6 global Interrupt /
Kojto	110:165afa46840b	184	SAI1_IRQn = 87, /!< SAI1 global Interrupt /
Kojto	110:165afa46840b	185	LTDC_IRQn = 88, /!< LTDC global Interrupt /
Kojto	110:165afa46840b	186	LTDC_ER_IRQn = 89, /!< LTDC Error global Interrupt /
Kojto	110:165afa46840b	187	DMA2D_IRQn = 90, /!< DMA2D global Interrupt /
Kojto	110:165afa46840b	188	QUADSPI_IRQn = 91, /!< QUADSPI global Interrupt /
Kojto	110:165afa46840b	189	DSI_IRQn = 92 /!< DSI global Interrupt /
Kojto	110:165afa46840b	190	} IRQn_Type;
Kojto	110:165afa46840b	191
Kojto	110:165afa46840b	192	/**
Kojto	110:165afa46840b	193	* @}
Kojto	110:165afa46840b	194	*/
Kojto	110:165afa46840b	195
Kojto	110:165afa46840b	196	#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
Kojto	110:165afa46840b	197	#include "system_stm32f4xx.h"
Kojto	110:165afa46840b	198	#include <stdint.h>
Kojto	110:165afa46840b	199
Kojto	110:165afa46840b	200	/** @addtogroup Peripheral_registers_structures
Kojto	110:165afa46840b	201	* @{
Kojto	110:165afa46840b	202	*/
Kojto	110:165afa46840b	203
Kojto	110:165afa46840b	204	/**
Kojto	110:165afa46840b	205	* @brief Analog to Digital Converter
Kojto	110:165afa46840b	206	*/
Kojto	110:165afa46840b	207
Kojto	110:165afa46840b	208	typedef struct
Kojto	110:165afa46840b	209	{
Kojto	110:165afa46840b	210	__IO uint32_t SR; /!< ADC status register, Address offset: 0x00 /
Kojto	110:165afa46840b	211	__IO uint32_t CR1; /!< ADC control register 1, Address offset: 0x04 /
Kojto	110:165afa46840b	212	__IO uint32_t CR2; /!< ADC control register 2, Address offset: 0x08 /
Kojto	110:165afa46840b	213	__IO uint32_t SMPR1; /!< ADC sample time register 1, Address offset: 0x0C /
Kojto	110:165afa46840b	214	__IO uint32_t SMPR2; /!< ADC sample time register 2, Address offset: 0x10 /
Kojto	110:165afa46840b	215	__IO uint32_t JOFR1; /!< ADC injected channel data offset register 1, Address offset: 0x14 /
Kojto	110:165afa46840b	216	__IO uint32_t JOFR2; /!< ADC injected channel data offset register 2, Address offset: 0x18 /
Kojto	110:165afa46840b	217	__IO uint32_t JOFR3; /!< ADC injected channel data offset register 3, Address offset: 0x1C /
Kojto	110:165afa46840b	218	__IO uint32_t JOFR4; /!< ADC injected channel data offset register 4, Address offset: 0x20 /
Kojto	110:165afa46840b	219	__IO uint32_t HTR; /!< ADC watchdog higher threshold register, Address offset: 0x24 /
Kojto	110:165afa46840b	220	__IO uint32_t LTR; /!< ADC watchdog lower threshold register, Address offset: 0x28 /
Kojto	110:165afa46840b	221	__IO uint32_t SQR1; /!< ADC regular sequence register 1, Address offset: 0x2C /
Kojto	110:165afa46840b	222	__IO uint32_t SQR2; /!< ADC regular sequence register 2, Address offset: 0x30 /
Kojto	110:165afa46840b	223	__IO uint32_t SQR3; /!< ADC regular sequence register 3, Address offset: 0x34 /
Kojto	110:165afa46840b	224	__IO uint32_t JSQR; /!< ADC injected sequence register, Address offset: 0x38/
Kojto	110:165afa46840b	225	__IO uint32_t JDR1; /!< ADC injected data register 1, Address offset: 0x3C /
Kojto	110:165afa46840b	226	__IO uint32_t JDR2; /!< ADC injected data register 2, Address offset: 0x40 /
Kojto	110:165afa46840b	227	__IO uint32_t JDR3; /!< ADC injected data register 3, Address offset: 0x44 /
Kojto	110:165afa46840b	228	__IO uint32_t JDR4; /!< ADC injected data register 4, Address offset: 0x48 /
Kojto	110:165afa46840b	229	__IO uint32_t DR; /!< ADC regular data register, Address offset: 0x4C /
Kojto	110:165afa46840b	230	} ADC_TypeDef;
Kojto	110:165afa46840b	231
Kojto	110:165afa46840b	232	typedef struct
Kojto	110:165afa46840b	233	{
Kojto	110:165afa46840b	234	__IO uint32_t CSR; /!< ADC Common status register, Address offset: ADC1 base address + 0x300 /
Kojto	110:165afa46840b	235	__IO uint32_t CCR; /!< ADC common control register, Address offset: ADC1 base address + 0x304 /
Kojto	110:165afa46840b	236	__IO uint32_t CDR; /*!< ADC common regular data register for dual
Kojto	110:165afa46840b	237	AND triple modes, Address offset: ADC1 base address + 0x308 */
Kojto	110:165afa46840b	238	} ADC_Common_TypeDef;
Kojto	110:165afa46840b	239
Kojto	110:165afa46840b	240
Kojto	110:165afa46840b	241	/**
Kojto	110:165afa46840b	242	* @brief Controller Area Network TxMailBox
Kojto	110:165afa46840b	243	*/
Kojto	110:165afa46840b	244
Kojto	110:165afa46840b	245	typedef struct
Kojto	110:165afa46840b	246	{
Kojto	110:165afa46840b	247	__IO uint32_t TIR; /!< CAN TX mailbox identifier register /
Kojto	110:165afa46840b	248	__IO uint32_t TDTR; /!< CAN mailbox data length control and time stamp register /
Kojto	110:165afa46840b	249	__IO uint32_t TDLR; /!< CAN mailbox data low register /
Kojto	110:165afa46840b	250	__IO uint32_t TDHR; /!< CAN mailbox data high register /
Kojto	110:165afa46840b	251	} CAN_TxMailBox_TypeDef;
Kojto	110:165afa46840b	252
Kojto	110:165afa46840b	253	/**
Kojto	110:165afa46840b	254	* @brief Controller Area Network FIFOMailBox
Kojto	110:165afa46840b	255	*/
Kojto	110:165afa46840b	256
Kojto	110:165afa46840b	257	typedef struct
Kojto	110:165afa46840b	258	{
Kojto	110:165afa46840b	259	__IO uint32_t RIR; /!< CAN receive FIFO mailbox identifier register /
Kojto	110:165afa46840b	260	__IO uint32_t RDTR; /!< CAN receive FIFO mailbox data length control and time stamp register /
Kojto	110:165afa46840b	261	__IO uint32_t RDLR; /!< CAN receive FIFO mailbox data low register /
Kojto	110:165afa46840b	262	__IO uint32_t RDHR; /!< CAN receive FIFO mailbox data high register /
Kojto	110:165afa46840b	263	} CAN_FIFOMailBox_TypeDef;
Kojto	110:165afa46840b	264
Kojto	110:165afa46840b	265	/**
Kojto	110:165afa46840b	266	* @brief Controller Area Network FilterRegister
Kojto	110:165afa46840b	267	*/
Kojto	110:165afa46840b	268
Kojto	110:165afa46840b	269	typedef struct
Kojto	110:165afa46840b	270	{
Kojto	110:165afa46840b	271	__IO uint32_t FR1; /!< CAN Filter bank register 1 /
Kojto	110:165afa46840b	272	__IO uint32_t FR2; /!< CAN Filter bank register 1 /
Kojto	110:165afa46840b	273	} CAN_FilterRegister_TypeDef;
Kojto	110:165afa46840b	274
Kojto	110:165afa46840b	275	/**
Kojto	110:165afa46840b	276	* @brief Controller Area Network
Kojto	110:165afa46840b	277	*/
Kojto	110:165afa46840b	278
Kojto	110:165afa46840b	279	typedef struct
Kojto	110:165afa46840b	280	{
Kojto	110:165afa46840b	281	__IO uint32_t MCR; /!< CAN master control register, Address offset: 0x00 /
Kojto	110:165afa46840b	282	__IO uint32_t MSR; /!< CAN master status register, Address offset: 0x04 /
Kojto	110:165afa46840b	283	__IO uint32_t TSR; /!< CAN transmit status register, Address offset: 0x08 /
Kojto	110:165afa46840b	284	__IO uint32_t RF0R; /!< CAN receive FIFO 0 register, Address offset: 0x0C /
Kojto	110:165afa46840b	285	__IO uint32_t RF1R; /!< CAN receive FIFO 1 register, Address offset: 0x10 /
Kojto	110:165afa46840b	286	__IO uint32_t IER; /!< CAN interrupt enable register, Address offset: 0x14 /
Kojto	110:165afa46840b	287	__IO uint32_t ESR; /!< CAN error status register, Address offset: 0x18 /
Kojto	110:165afa46840b	288	__IO uint32_t BTR; /!< CAN bit timing register, Address offset: 0x1C /
Kojto	110:165afa46840b	289	uint32_t RESERVED0[88]; /!< Reserved, 0x020 - 0x17F /
Kojto	110:165afa46840b	290	CAN_TxMailBox_TypeDef sTxMailBox[3]; /!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC /
Kojto	110:165afa46840b	291	CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC /
Kojto	110:165afa46840b	292	uint32_t RESERVED1[12]; /!< Reserved, 0x1D0 - 0x1FF /
Kojto	110:165afa46840b	293	__IO uint32_t FMR; /!< CAN filter master register, Address offset: 0x200 /
Kojto	110:165afa46840b	294	__IO uint32_t FM1R; /!< CAN filter mode register, Address offset: 0x204 /
Kojto	110:165afa46840b	295	uint32_t RESERVED2; /!< Reserved, 0x208 /
Kojto	110:165afa46840b	296	__IO uint32_t FS1R; /!< CAN filter scale register, Address offset: 0x20C /
Kojto	110:165afa46840b	297	uint32_t RESERVED3; /!< Reserved, 0x210 /
Kojto	110:165afa46840b	298	__IO uint32_t FFA1R; /!< CAN filter FIFO assignment register, Address offset: 0x214 /
Kojto	110:165afa46840b	299	uint32_t RESERVED4; /!< Reserved, 0x218 /
Kojto	110:165afa46840b	300	__IO uint32_t FA1R; /!< CAN filter activation register, Address offset: 0x21C /
Kojto	110:165afa46840b	301	uint32_t RESERVED5[8]; /!< Reserved, 0x220-0x23F /
Kojto	110:165afa46840b	302	CAN_FilterRegister_TypeDef sFilterRegister[28]; /!< CAN Filter Register, Address offset: 0x240-0x31C /
Kojto	110:165afa46840b	303	} CAN_TypeDef;
Kojto	110:165afa46840b	304
Kojto	110:165afa46840b	305	/**
Kojto	110:165afa46840b	306	* @brief CRC calculation unit
Kojto	110:165afa46840b	307	*/
Kojto	110:165afa46840b	308
Kojto	110:165afa46840b	309	typedef struct
Kojto	110:165afa46840b	310	{
Kojto	110:165afa46840b	311	__IO uint32_t DR; /!< CRC Data register, Address offset: 0x00 /
Kojto	110:165afa46840b	312	__IO uint8_t IDR; /!< CRC Independent data register, Address offset: 0x04 /
Kojto	110:165afa46840b	313	uint8_t RESERVED0; /!< Reserved, 0x05 /
Kojto	110:165afa46840b	314	uint16_t RESERVED1; /!< Reserved, 0x06 /
Kojto	110:165afa46840b	315	__IO uint32_t CR; /!< CRC Control register, Address offset: 0x08 /
Kojto	110:165afa46840b	316	} CRC_TypeDef;
Kojto	110:165afa46840b	317
Kojto	110:165afa46840b	318	/**
Kojto	110:165afa46840b	319	* @brief Digital to Analog Converter
Kojto	110:165afa46840b	320	*/
Kojto	110:165afa46840b	321
Kojto	110:165afa46840b	322	typedef struct
Kojto	110:165afa46840b	323	{
Kojto	110:165afa46840b	324	__IO uint32_t CR; /!< DAC control register, Address offset: 0x00 /
Kojto	110:165afa46840b	325	__IO uint32_t SWTRIGR; /!< DAC software trigger register, Address offset: 0x04 /
Kojto	110:165afa46840b	326	__IO uint32_t DHR12R1; /!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 /
Kojto	110:165afa46840b	327	__IO uint32_t DHR12L1; /!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C /
Kojto	110:165afa46840b	328	__IO uint32_t DHR8R1; /!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 /
Kojto	110:165afa46840b	329	__IO uint32_t DHR12R2; /!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 /
Kojto	110:165afa46840b	330	__IO uint32_t DHR12L2; /!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 /
Kojto	110:165afa46840b	331	__IO uint32_t DHR8R2; /!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C /
Kojto	110:165afa46840b	332	__IO uint32_t DHR12RD; /!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 /
Kojto	110:165afa46840b	333	__IO uint32_t DHR12LD; /!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 /
Kojto	110:165afa46840b	334	__IO uint32_t DHR8RD; /!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 /
Kojto	110:165afa46840b	335	__IO uint32_t DOR1; /!< DAC channel1 data output register, Address offset: 0x2C /
Kojto	110:165afa46840b	336	__IO uint32_t DOR2; /!< DAC channel2 data output register, Address offset: 0x30 /
Kojto	110:165afa46840b	337	__IO uint32_t SR; /!< DAC status register, Address offset: 0x34 /
Kojto	110:165afa46840b	338	} DAC_TypeDef;
Kojto	110:165afa46840b	339
Kojto	110:165afa46840b	340	/**
Kojto	110:165afa46840b	341	* @brief Debug MCU
Kojto	110:165afa46840b	342	*/
Kojto	110:165afa46840b	343
Kojto	110:165afa46840b	344	typedef struct
Kojto	110:165afa46840b	345	{
Kojto	110:165afa46840b	346	__IO uint32_t IDCODE; /!< MCU device ID code, Address offset: 0x00 /
Kojto	110:165afa46840b	347	__IO uint32_t CR; /!< Debug MCU configuration register, Address offset: 0x04 /
Kojto	110:165afa46840b	348	__IO uint32_t APB1FZ; /!< Debug MCU APB1 freeze register, Address offset: 0x08 /
Kojto	110:165afa46840b	349	__IO uint32_t APB2FZ; /!< Debug MCU APB2 freeze register, Address offset: 0x0C /
Kojto	110:165afa46840b	350	}DBGMCU_TypeDef;
Kojto	110:165afa46840b	351
Kojto	110:165afa46840b	352	/**
Kojto	110:165afa46840b	353	* @brief DCMI
Kojto	110:165afa46840b	354	*/
Kojto	110:165afa46840b	355
Kojto	110:165afa46840b	356	typedef struct
Kojto	110:165afa46840b	357	{
Kojto	110:165afa46840b	358	__IO uint32_t CR; /!< DCMI control register 1, Address offset: 0x00 /
Kojto	110:165afa46840b	359	__IO uint32_t SR; /!< DCMI status register, Address offset: 0x04 /
Kojto	110:165afa46840b	360	__IO uint32_t RISR; /!< DCMI raw interrupt status register, Address offset: 0x08 /
Kojto	110:165afa46840b	361	__IO uint32_t IER; /!< DCMI interrupt enable register, Address offset: 0x0C /
Kojto	110:165afa46840b	362	__IO uint32_t MISR; /!< DCMI masked interrupt status register, Address offset: 0x10 /
Kojto	110:165afa46840b	363	__IO uint32_t ICR; /!< DCMI interrupt clear register, Address offset: 0x14 /
Kojto	110:165afa46840b	364	__IO uint32_t ESCR; /!< DCMI embedded synchronization code register, Address offset: 0x18 /
Kojto	110:165afa46840b	365	__IO uint32_t ESUR; /!< DCMI embedded synchronization unmask register, Address offset: 0x1C /
Kojto	110:165afa46840b	366	__IO uint32_t CWSTRTR; /!< DCMI crop window start, Address offset: 0x20 /
Kojto	110:165afa46840b	367	__IO uint32_t CWSIZER; /!< DCMI crop window size, Address offset: 0x24 /
Kojto	110:165afa46840b	368	__IO uint32_t DR; /!< DCMI data register, Address offset: 0x28 /
Kojto	110:165afa46840b	369	} DCMI_TypeDef;
Kojto	110:165afa46840b	370
Kojto	110:165afa46840b	371	/**
Kojto	110:165afa46840b	372	* @brief DMA Controller
Kojto	110:165afa46840b	373	*/
Kojto	110:165afa46840b	374
Kojto	110:165afa46840b	375	typedef struct
Kojto	110:165afa46840b	376	{
Kojto	110:165afa46840b	377	__IO uint32_t CR; /!< DMA stream x configuration register /
Kojto	110:165afa46840b	378	__IO uint32_t NDTR; /!< DMA stream x number of data register /
Kojto	110:165afa46840b	379	__IO uint32_t PAR; /!< DMA stream x peripheral address register /
Kojto	110:165afa46840b	380	__IO uint32_t M0AR; /!< DMA stream x memory 0 address register /
Kojto	110:165afa46840b	381	__IO uint32_t M1AR; /!< DMA stream x memory 1 address register /
Kojto	110:165afa46840b	382	__IO uint32_t FCR; /!< DMA stream x FIFO control register /
Kojto	110:165afa46840b	383	} DMA_Stream_TypeDef;
Kojto	110:165afa46840b	384
Kojto	110:165afa46840b	385	typedef struct
Kojto	110:165afa46840b	386	{
Kojto	110:165afa46840b	387	__IO uint32_t LISR; /!< DMA low interrupt status register, Address offset: 0x00 /
Kojto	110:165afa46840b	388	__IO uint32_t HISR; /!< DMA high interrupt status register, Address offset: 0x04 /
Kojto	110:165afa46840b	389	__IO uint32_t LIFCR; /!< DMA low interrupt flag clear register, Address offset: 0x08 /
Kojto	110:165afa46840b	390	__IO uint32_t HIFCR; /!< DMA high interrupt flag clear register, Address offset: 0x0C /
Kojto	110:165afa46840b	391	} DMA_TypeDef;
Kojto	110:165afa46840b	392
Kojto	110:165afa46840b	393	/**
Kojto	110:165afa46840b	394	* @brief DMA2D Controller
Kojto	110:165afa46840b	395	*/
Kojto	110:165afa46840b	396
Kojto	110:165afa46840b	397	typedef struct
Kojto	110:165afa46840b	398	{
Kojto	110:165afa46840b	399	__IO uint32_t CR; /!< DMA2D Control Register, Address offset: 0x00 /
Kojto	110:165afa46840b	400	__IO uint32_t ISR; /!< DMA2D Interrupt Status Register, Address offset: 0x04 /
Kojto	110:165afa46840b	401	__IO uint32_t IFCR; /!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 /
Kojto	110:165afa46840b	402	__IO uint32_t FGMAR; /!< DMA2D Foreground Memory Address Register, Address offset: 0x0C /
Kojto	110:165afa46840b	403	__IO uint32_t FGOR; /!< DMA2D Foreground Offset Register, Address offset: 0x10 /
Kojto	110:165afa46840b	404	__IO uint32_t BGMAR; /!< DMA2D Background Memory Address Register, Address offset: 0x14 /
Kojto	110:165afa46840b	405	__IO uint32_t BGOR; /!< DMA2D Background Offset Register, Address offset: 0x18 /
Kojto	110:165afa46840b	406	__IO uint32_t FGPFCCR; /!< DMA2D Foreground PFC Control Register, Address offset: 0x1C /
Kojto	110:165afa46840b	407	__IO uint32_t FGCOLR; /!< DMA2D Foreground Color Register, Address offset: 0x20 /
Kojto	110:165afa46840b	408	__IO uint32_t BGPFCCR; /!< DMA2D Background PFC Control Register, Address offset: 0x24 /
Kojto	110:165afa46840b	409	__IO uint32_t BGCOLR; /!< DMA2D Background Color Register, Address offset: 0x28 /
Kojto	110:165afa46840b	410	__IO uint32_t FGCMAR; /!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C /
Kojto	110:165afa46840b	411	__IO uint32_t BGCMAR; /!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 /
Kojto	110:165afa46840b	412	__IO uint32_t OPFCCR; /!< DMA2D Output PFC Control Register, Address offset: 0x34 /
Kojto	110:165afa46840b	413	__IO uint32_t OCOLR; /!< DMA2D Output Color Register, Address offset: 0x38 /
Kojto	110:165afa46840b	414	__IO uint32_t OMAR; /!< DMA2D Output Memory Address Register, Address offset: 0x3C /
Kojto	110:165afa46840b	415	__IO uint32_t OOR; /!< DMA2D Output Offset Register, Address offset: 0x40 /
Kojto	110:165afa46840b	416	__IO uint32_t NLR; /!< DMA2D Number of Line Register, Address offset: 0x44 /
Kojto	110:165afa46840b	417	__IO uint32_t LWR; /!< DMA2D Line Watermark Register, Address offset: 0x48 /
Kojto	110:165afa46840b	418	__IO uint32_t AMTCR; /!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C /
Kojto	110:165afa46840b	419	uint32_t RESERVED[236]; /!< Reserved, 0x50-0x3FF /
Kojto	110:165afa46840b	420	__IO uint32_t FGCLUT[256]; /!< DMA2D Foreground CLUT, Address offset:400-7FF /
Kojto	110:165afa46840b	421	__IO uint32_t BGCLUT[256]; /!< DMA2D Background CLUT, Address offset:800-BFF /
Kojto	110:165afa46840b	422	} DMA2D_TypeDef;
Kojto	110:165afa46840b	423
Kojto	110:165afa46840b	424	/**
Kojto	110:165afa46840b	425	* @brief DSI Controller
Kojto	110:165afa46840b	426	*/
Kojto	110:165afa46840b	427
Kojto	110:165afa46840b	428	typedef struct
Kojto	110:165afa46840b	429	{
Kojto	110:165afa46840b	430	__IO uint32_t VR; /!< DSI Host Version Register, Address offset: 0x00 /
Kojto	110:165afa46840b	431	__IO uint32_t CR; /!< DSI Host Control Register, Address offset: 0x04 /
Kojto	110:165afa46840b	432	__IO uint32_t CCR; /!< DSI HOST Clock Control Register, Address offset: 0x08 /
Kojto	110:165afa46840b	433	__IO uint32_t LVCIDR; /!< DSI Host LTDC VCID Register, Address offset: 0x0C /
Kojto	110:165afa46840b	434	__IO uint32_t LCOLCR; /!< DSI Host LTDC Color Coding Register, Address offset: 0x10 /
Kojto	110:165afa46840b	435	__IO uint32_t LPCR; /!< DSI Host LTDC Polarity Configuration Register, Address offset: 0x14 /
Kojto	110:165afa46840b	436	__IO uint32_t LPMCR; /!< DSI Host Low-Power Mode Configuration Register, Address offset: 0x18 /
Kojto	110:165afa46840b	437	uint32_t RESERVED0[4]; /!< Reserved, 0x1C - 0x2B /
Kojto	110:165afa46840b	438	__IO uint32_t PCR; /!< DSI Host Protocol Configuration Register, Address offset: 0x2C /
Kojto	110:165afa46840b	439	__IO uint32_t GVCIDR; /!< DSI Host Generic VCID Register, Address offset: 0x30 /
Kojto	110:165afa46840b	440	__IO uint32_t MCR; /!< DSI Host Mode Configuration Register, Address offset: 0x34 /
Kojto	110:165afa46840b	441	__IO uint32_t VMCR; /!< DSI Host Video Mode Configuration Register, Address offset: 0x38 /
Kojto	110:165afa46840b	442	__IO uint32_t VPCR; /!< DSI Host Video Packet Configuration Register, Address offset: 0x3C /
Kojto	110:165afa46840b	443	__IO uint32_t VCCR; /!< DSI Host Video Chunks Configuration Register, Address offset: 0x40 /
Kojto	110:165afa46840b	444	__IO uint32_t VNPCR; /!< DSI Host Video Null Packet Configuration Register, Address offset: 0x44 /
Kojto	110:165afa46840b	445	__IO uint32_t VHSACR; /!< DSI Host Video HSA Configuration Register, Address offset: 0x48 /
Kojto	110:165afa46840b	446	__IO uint32_t VHBPCR; /!< DSI Host Video HBP Configuration Register, Address offset: 0x4C /
Kojto	110:165afa46840b	447	__IO uint32_t VLCR; /!< DSI Host Video Line Configuration Register, Address offset: 0x50 /
Kojto	110:165afa46840b	448	__IO uint32_t VVSACR; /!< DSI Host Video VSA Configuration Register, Address offset: 0x54 /
Kojto	110:165afa46840b	449	__IO uint32_t VVBPCR; /!< DSI Host Video VBP Configuration Register, Address offset: 0x58 /
Kojto	110:165afa46840b	450	__IO uint32_t VVFPCR; /!< DSI Host Video VFP Configuration Register, Address offset: 0x5C /
Kojto	110:165afa46840b	451	__IO uint32_t VVACR; /!< DSI Host Video VA Configuration Register, Address offset: 0x60 /
Kojto	110:165afa46840b	452	__IO uint32_t LCCR; /!< DSI Host LTDC Command Configuration Register, Address offset: 0x64 /
Kojto	110:165afa46840b	453	__IO uint32_t CMCR; /!< DSI Host Command Mode Configuration Register, Address offset: 0x68 /
Kojto	110:165afa46840b	454	__IO uint32_t GHCR; /!< DSI Host Generic Header Configuration Register, Address offset: 0x6C /
Kojto	110:165afa46840b	455	__IO uint32_t GPDR; /!< DSI Host Generic Payload Data Register, Address offset: 0x70 /
Kojto	110:165afa46840b	456	__IO uint32_t GPSR; /!< DSI Host Generic Packet Status Register, Address offset: 0x74 /
Kojto	110:165afa46840b	457	__IO uint32_t TCCR[6]; /!< DSI Host Timeout Counter Configuration Register, Address offset: 0x78-0x8F /
Kojto	110:165afa46840b	458	__IO uint32_t TDCR; /!< DSI Host 3D Configuration Register, Address offset: 0x90 /
Kojto	110:165afa46840b	459	__IO uint32_t CLCR; /!< DSI Host Clock Lane Configuration Register, Address offset: 0x94 /
Kojto	110:165afa46840b	460	__IO uint32_t CLTCR; /!< DSI Host Clock Lane Timer Configuration Register, Address offset: 0x98 /
Kojto	110:165afa46840b	461	__IO uint32_t DLTCR; /!< DSI Host Data Lane Timer Configuration Register, Address offset: 0x9C /
Kojto	110:165afa46840b	462	__IO uint32_t PCTLR; /!< DSI Host PHY Control Register, Address offset: 0xA0 /
Kojto	110:165afa46840b	463	__IO uint32_t PCONFR; /!< DSI Host PHY Configuration Register, Address offset: 0xA4 /
Kojto	110:165afa46840b	464	__IO uint32_t PUCR; /!< DSI Host PHY ULPS Control Register, Address offset: 0xA8 /
Kojto	110:165afa46840b	465	__IO uint32_t PTTCR; /!< DSI Host PHY TX Triggers Configuration Register, Address offset: 0xAC /
Kojto	110:165afa46840b	466	__IO uint32_t PSR; /!< DSI Host PHY Status Register, Address offset: 0xB0 /
Kojto	110:165afa46840b	467	uint32_t RESERVED1[2]; /!< Reserved, 0xB4 - 0xBB /
Kojto	110:165afa46840b	468	__IO uint32_t ISR[2]; /!< DSI Host Interrupt & Status Register, Address offset: 0xBC-0xC3 /
Kojto	110:165afa46840b	469	__IO uint32_t IER[2]; /!< DSI Host Interrupt Enable Register, Address offset: 0xC4-0xCB /
Kojto	110:165afa46840b	470	uint32_t RESERVED2[3]; /!< Reserved, 0xD0 - 0xD7 /
Kojto	110:165afa46840b	471	__IO uint32_t FIR[2]; /!< DSI Host Force Interrupt Register, Address offset: 0xD8-0xDF /
Kojto	110:165afa46840b	472	uint32_t RESERVED3[8]; /!< Reserved, 0xE0 - 0xFF /
Kojto	110:165afa46840b	473	__IO uint32_t VSCR; /!< DSI Host Video Shadow Control Register, Address offset: 0x100 /
Kojto	110:165afa46840b	474	uint32_t RESERVED4[2]; /!< Reserved, 0x104 - 0x10B /
Kojto	110:165afa46840b	475	__IO uint32_t LCVCIDR; /!< DSI Host LTDC Current VCID Register, Address offset: 0x10C /
Kojto	110:165afa46840b	476	__IO uint32_t LCCCR; /!< DSI Host LTDC Current Color Coding Register, Address offset: 0x110 /
Kojto	110:165afa46840b	477	uint32_t RESERVED5; /!< Reserved, 0x114 /
Kojto	110:165afa46840b	478	__IO uint32_t LPMCCR; /!< DSI Host Low-power Mode Current Configuration Register, Address offset: 0x118 /
Kojto	110:165afa46840b	479	uint32_t RESERVED6[7]; /!< Reserved, 0x11C - 0x137 /
Kojto	110:165afa46840b	480	__IO uint32_t VMCCR; /!< DSI Host Video Mode Current Configuration Register, Address offset: 0x138 /
Kojto	110:165afa46840b	481	__IO uint32_t VPCCR; /!< DSI Host Video Packet Current Configuration Register, Address offset: 0x13C /
Kojto	110:165afa46840b	482	__IO uint32_t VCCCR; /!< DSI Host Video Chuncks Current Configuration Register, Address offset: 0x140 /
Kojto	110:165afa46840b	483	__IO uint32_t VNPCCR; /!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144 /
Kojto	110:165afa46840b	484	__IO uint32_t VHSACCR; /!< DSI Host Video HSA Current Configuration Register, Address offset: 0x148 /
Kojto	110:165afa46840b	485	__IO uint32_t VHBPCCR; /!< DSI Host Video HBP Current Configuration Register, Address offset: 0x14C /
Kojto	110:165afa46840b	486	__IO uint32_t VLCCR; /!< DSI Host Video Line Current Configuration Register, Address offset: 0x150 /
Kojto	110:165afa46840b	487	__IO uint32_t VVSACCR; /!< DSI Host Video VSA Current Configuration Register, Address offset: 0x154 /
Kojto	110:165afa46840b	488	__IO uint32_t VVBPCCR; /!< DSI Host Video VBP Current Configuration Register, Address offset: 0x158 /
Kojto	110:165afa46840b	489	__IO uint32_t VVFPCCR; /!< DSI Host Video VFP Current Configuration Register, Address offset: 0x15C /
Kojto	110:165afa46840b	490	__IO uint32_t VVACCR; /!< DSI Host Video VA Current Configuration Register, Address offset: 0x160 /
Kojto	110:165afa46840b	491	uint32_t RESERVED7[11]; /!< Reserved, 0x164 - 0x18F /
Kojto	110:165afa46840b	492	__IO uint32_t TDCCR; /!< DSI Host 3D Current Configuration Register, Address offset: 0x190 /
Kojto	110:165afa46840b	493	uint32_t RESERVED8[155]; /!< Reserved, 0x194 - 0x3FF /
Kojto	110:165afa46840b	494	__IO uint32_t WCFGR; /!< DSI Wrapper Configuration Register, Address offset: 0x400 /
Kojto	110:165afa46840b	495	__IO uint32_t WCR; /!< DSI Wrapper Control Register, Address offset: 0x404 /
Kojto	110:165afa46840b	496	__IO uint32_t WIER; /!< DSI Wrapper Interrupt Enable Register, Address offset: 0x408 /
Kojto	110:165afa46840b	497	__IO uint32_t WISR; /!< DSI Wrapper Interrupt and Status Register, Address offset: 0x40C /
Kojto	110:165afa46840b	498	__IO uint32_t WIFCR; /!< DSI Wrapper Interrupt Flag Clear Register, Address offset: 0x410 /
Kojto	110:165afa46840b	499	uint32_t RESERVED9; /!< Reserved, 0x414 /
Kojto	110:165afa46840b	500	__IO uint32_t WPCR[5]; /!< DSI Wrapper PHY Configuration Register, Address offset: 0x418-0x42B /
Kojto	110:165afa46840b	501	uint32_t RESERVED10; /!< Reserved, 0x42C /
Kojto	110:165afa46840b	502	__IO uint32_t WRPCR; /!< DSI Wrapper Regulator and PLL Control Register, Address offset: 0x430 /
Kojto	110:165afa46840b	503	} DSI_TypeDef;
Kojto	110:165afa46840b	504
Kojto	110:165afa46840b	505	/**
Kojto	110:165afa46840b	506	* @brief Ethernet MAC
Kojto	110:165afa46840b	507	*/
Kojto	110:165afa46840b	508
Kojto	110:165afa46840b	509	typedef struct
Kojto	110:165afa46840b	510	{
Kojto	110:165afa46840b	511	__IO uint32_t MACCR;
Kojto	110:165afa46840b	512	__IO uint32_t MACFFR;
Kojto	110:165afa46840b	513	__IO uint32_t MACHTHR;
Kojto	110:165afa46840b	514	__IO uint32_t MACHTLR;
Kojto	110:165afa46840b	515	__IO uint32_t MACMIIAR;
Kojto	110:165afa46840b	516	__IO uint32_t MACMIIDR;
Kojto	110:165afa46840b	517	__IO uint32_t MACFCR;
Kojto	110:165afa46840b	518	__IO uint32_t MACVLANTR; /* 8 */
Kojto	110:165afa46840b	519	uint32_t RESERVED0[2];
Kojto	110:165afa46840b	520	__IO uint32_t MACRWUFFR; /* 11 */
Kojto	110:165afa46840b	521	__IO uint32_t MACPMTCSR;
Kojto	110:165afa46840b	522	uint32_t RESERVED1[2];
Kojto	110:165afa46840b	523	__IO uint32_t MACSR; /* 15 */
Kojto	110:165afa46840b	524	__IO uint32_t MACIMR;
Kojto	110:165afa46840b	525	__IO uint32_t MACA0HR;
Kojto	110:165afa46840b	526	__IO uint32_t MACA0LR;
Kojto	110:165afa46840b	527	__IO uint32_t MACA1HR;
Kojto	110:165afa46840b	528	__IO uint32_t MACA1LR;
Kojto	110:165afa46840b	529	__IO uint32_t MACA2HR;
Kojto	110:165afa46840b	530	__IO uint32_t MACA2LR;
Kojto	110:165afa46840b	531	__IO uint32_t MACA3HR;
Kojto	110:165afa46840b	532	__IO uint32_t MACA3LR; /* 24 */
Kojto	110:165afa46840b	533	uint32_t RESERVED2[40];
Kojto	110:165afa46840b	534	__IO uint32_t MMCCR; /* 65 */
Kojto	110:165afa46840b	535	__IO uint32_t MMCRIR;
Kojto	110:165afa46840b	536	__IO uint32_t MMCTIR;
Kojto	110:165afa46840b	537	__IO uint32_t MMCRIMR;
Kojto	110:165afa46840b	538	__IO uint32_t MMCTIMR; /* 69 */
Kojto	110:165afa46840b	539	uint32_t RESERVED3[14];
Kojto	110:165afa46840b	540	__IO uint32_t MMCTGFSCCR; /* 84 */
Kojto	110:165afa46840b	541	__IO uint32_t MMCTGFMSCCR;
Kojto	110:165afa46840b	542	uint32_t RESERVED4[5];
Kojto	110:165afa46840b	543	__IO uint32_t MMCTGFCR;
Kojto	110:165afa46840b	544	uint32_t RESERVED5[10];
Kojto	110:165afa46840b	545	__IO uint32_t MMCRFCECR;
Kojto	110:165afa46840b	546	__IO uint32_t MMCRFAECR;
Kojto	110:165afa46840b	547	uint32_t RESERVED6[10];
Kojto	110:165afa46840b	548	__IO uint32_t MMCRGUFCR;
Kojto	110:165afa46840b	549	uint32_t RESERVED7[334];
Kojto	110:165afa46840b	550	__IO uint32_t PTPTSCR;
Kojto	110:165afa46840b	551	__IO uint32_t PTPSSIR;
Kojto	110:165afa46840b	552	__IO uint32_t PTPTSHR;
Kojto	110:165afa46840b	553	__IO uint32_t PTPTSLR;
Kojto	110:165afa46840b	554	__IO uint32_t PTPTSHUR;
Kojto	110:165afa46840b	555	__IO uint32_t PTPTSLUR;
Kojto	110:165afa46840b	556	__IO uint32_t PTPTSAR;
Kojto	110:165afa46840b	557	__IO uint32_t PTPTTHR;
Kojto	110:165afa46840b	558	__IO uint32_t PTPTTLR;
Kojto	110:165afa46840b	559	__IO uint32_t RESERVED8;
Kojto	110:165afa46840b	560	__IO uint32_t PTPTSSR;
Kojto	110:165afa46840b	561	uint32_t RESERVED9[565];
Kojto	110:165afa46840b	562	__IO uint32_t DMABMR;
Kojto	110:165afa46840b	563	__IO uint32_t DMATPDR;
Kojto	110:165afa46840b	564	__IO uint32_t DMARPDR;
Kojto	110:165afa46840b	565	__IO uint32_t DMARDLAR;
Kojto	110:165afa46840b	566	__IO uint32_t DMATDLAR;
Kojto	110:165afa46840b	567	__IO uint32_t DMASR;
Kojto	110:165afa46840b	568	__IO uint32_t DMAOMR;
Kojto	110:165afa46840b	569	__IO uint32_t DMAIER;
Kojto	110:165afa46840b	570	__IO uint32_t DMAMFBOCR;
Kojto	110:165afa46840b	571	__IO uint32_t DMARSWTR;
Kojto	110:165afa46840b	572	uint32_t RESERVED10[8];
Kojto	110:165afa46840b	573	__IO uint32_t DMACHTDR;
Kojto	110:165afa46840b	574	__IO uint32_t DMACHRDR;
Kojto	110:165afa46840b	575	__IO uint32_t DMACHTBAR;
Kojto	110:165afa46840b	576	__IO uint32_t DMACHRBAR;
Kojto	110:165afa46840b	577	} ETH_TypeDef;
Kojto	110:165afa46840b	578
Kojto	110:165afa46840b	579	/**
Kojto	110:165afa46840b	580	* @brief External Interrupt/Event Controller
Kojto	110:165afa46840b	581	*/
Kojto	110:165afa46840b	582
Kojto	110:165afa46840b	583	typedef struct
Kojto	110:165afa46840b	584	{
Kojto	110:165afa46840b	585	__IO uint32_t IMR; /!< EXTI Interrupt mask register, Address offset: 0x00 /
Kojto	110:165afa46840b	586	__IO uint32_t EMR; /!< EXTI Event mask register, Address offset: 0x04 /
Kojto	110:165afa46840b	587	__IO uint32_t RTSR; /!< EXTI Rising trigger selection register, Address offset: 0x08 /
Kojto	110:165afa46840b	588	__IO uint32_t FTSR; /!< EXTI Falling trigger selection register, Address offset: 0x0C /
Kojto	110:165afa46840b	589	__IO uint32_t SWIER; /!< EXTI Software interrupt event register, Address offset: 0x10 /
Kojto	110:165afa46840b	590	__IO uint32_t PR; /!< EXTI Pending register, Address offset: 0x14 /
Kojto	110:165afa46840b	591	} EXTI_TypeDef;
Kojto	110:165afa46840b	592
Kojto	110:165afa46840b	593	/**
Kojto	110:165afa46840b	594	* @brief FLASH Registers
Kojto	110:165afa46840b	595	*/
Kojto	110:165afa46840b	596
Kojto	110:165afa46840b	597	typedef struct
Kojto	110:165afa46840b	598	{
Kojto	110:165afa46840b	599	__IO uint32_t ACR; /!< FLASH access control register, Address offset: 0x00 /
Kojto	110:165afa46840b	600	__IO uint32_t KEYR; /!< FLASH key register, Address offset: 0x04 /
Kojto	110:165afa46840b	601	__IO uint32_t OPTKEYR; /!< FLASH option key register, Address offset: 0x08 /
Kojto	110:165afa46840b	602	__IO uint32_t SR; /!< FLASH status register, Address offset: 0x0C /
Kojto	110:165afa46840b	603	__IO uint32_t CR; /!< FLASH control register, Address offset: 0x10 /
Kojto	110:165afa46840b	604	__IO uint32_t OPTCR; /!< FLASH option control register , Address offset: 0x14 /
Kojto	110:165afa46840b	605	__IO uint32_t OPTCR1; /!< FLASH option control register 1, Address offset: 0x18 /
Kojto	110:165afa46840b	606	} FLASH_TypeDef;
Kojto	110:165afa46840b	607
Kojto	110:165afa46840b	608	/**
Kojto	110:165afa46840b	609	* @brief Flexible Memory Controller
Kojto	110:165afa46840b	610	*/
Kojto	110:165afa46840b	611
Kojto	110:165afa46840b	612	typedef struct
Kojto	110:165afa46840b	613	{
Kojto	110:165afa46840b	614	__IO uint32_t BTCR[8]; /!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C /
Kojto	110:165afa46840b	615	} FMC_Bank1_TypeDef;
Kojto	110:165afa46840b	616
Kojto	110:165afa46840b	617	/**
Kojto	110:165afa46840b	618	* @brief Flexible Memory Controller Bank1E
Kojto	110:165afa46840b	619	*/
Kojto	110:165afa46840b	620
Kojto	110:165afa46840b	621	typedef struct
Kojto	110:165afa46840b	622	{
Kojto	110:165afa46840b	623	__IO uint32_t BWTR[7]; /!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C /
Kojto	110:165afa46840b	624	} FMC_Bank1E_TypeDef;
Kojto	110:165afa46840b	625
Kojto	110:165afa46840b	626	/**
Kojto	110:165afa46840b	627	* @brief Flexible Memory Controller Bank3
Kojto	110:165afa46840b	628	*/
Kojto	110:165afa46840b	629
Kojto	110:165afa46840b	630	typedef struct
Kojto	110:165afa46840b	631	{
Kojto	110:165afa46840b	632	__IO uint32_t PCR; /!< NAND Flash control register, Address offset: 0x80 /
Kojto	110:165afa46840b	633	__IO uint32_t SR; /!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 /
Kojto	110:165afa46840b	634	__IO uint32_t PMEM; /!< NAND Flash Common memory space timing register, Address offset: 0x88 /
Kojto	110:165afa46840b	635	__IO uint32_t PATT; /!< NAND Flash Attribute memory space timing register, Address offset: 0x8C /
Kojto	110:165afa46840b	636	uint32_t RESERVED; /!< Reserved, 0x90 /
Kojto	110:165afa46840b	637	__IO uint32_t ECCR; /!< NAND Flash ECC result registers, Address offset: 0x94 /
Kojto	110:165afa46840b	638	} FMC_Bank3_TypeDef;
Kojto	110:165afa46840b	639
Kojto	110:165afa46840b	640	/**
Kojto	110:165afa46840b	641	* @brief Flexible Memory Controller Bank5_6
Kojto	110:165afa46840b	642	*/
Kojto	110:165afa46840b	643
Kojto	110:165afa46840b	644	typedef struct
Kojto	110:165afa46840b	645	{
Kojto	110:165afa46840b	646	__IO uint32_t SDCR[2]; /!< SDRAM Control registers , Address offset: 0x140-0x144 /
Kojto	110:165afa46840b	647	__IO uint32_t SDTR[2]; /!< SDRAM Timing registers , Address offset: 0x148-0x14C /
Kojto	110:165afa46840b	648	__IO uint32_t SDCMR; /!< SDRAM Command Mode register, Address offset: 0x150 /
Kojto	110:165afa46840b	649	__IO uint32_t SDRTR; /!< SDRAM Refresh Timer register, Address offset: 0x154 /
Kojto	110:165afa46840b	650	__IO uint32_t SDSR; /!< SDRAM Status register, Address offset: 0x158 /
Kojto	110:165afa46840b	651	} FMC_Bank5_6_TypeDef;
Kojto	110:165afa46840b	652
Kojto	110:165afa46840b	653	/**
Kojto	110:165afa46840b	654	* @brief General Purpose I/O
Kojto	110:165afa46840b	655	*/
Kojto	110:165afa46840b	656
Kojto	110:165afa46840b	657	typedef struct
Kojto	110:165afa46840b	658	{
Kojto	110:165afa46840b	659	__IO uint32_t MODER; /!< GPIO port mode register, Address offset: 0x00 /
Kojto	110:165afa46840b	660	__IO uint32_t OTYPER; /!< GPIO port output type register, Address offset: 0x04 /
Kojto	110:165afa46840b	661	__IO uint32_t OSPEEDR; /!< GPIO port output speed register, Address offset: 0x08 /
Kojto	110:165afa46840b	662	__IO uint32_t PUPDR; /!< GPIO port pull-up/pull-down register, Address offset: 0x0C /
Kojto	110:165afa46840b	663	__IO uint32_t IDR; /!< GPIO port input data register, Address offset: 0x10 /
Kojto	110:165afa46840b	664	__IO uint32_t ODR; /!< GPIO port output data register, Address offset: 0x14 /
Kojto	110:165afa46840b	665	__IO uint32_t BSRR; /!< GPIO port bit set/reset register, Address offset: 0x18 /
Kojto	110:165afa46840b	666	__IO uint32_t LCKR; /!< GPIO port configuration lock register, Address offset: 0x1C /
Kojto	110:165afa46840b	667	__IO uint32_t AFR[2]; /!< GPIO alternate function registers, Address offset: 0x20-0x24 /
Kojto	110:165afa46840b	668	} GPIO_TypeDef;
Kojto	110:165afa46840b	669
Kojto	110:165afa46840b	670	/**
Kojto	110:165afa46840b	671	* @brief System configuration controller
Kojto	110:165afa46840b	672	*/
Kojto	110:165afa46840b	673
Kojto	110:165afa46840b	674	typedef struct
Kojto	110:165afa46840b	675	{
Kojto	110:165afa46840b	676	__IO uint32_t MEMRMP; /!< SYSCFG memory remap register, Address offset: 0x00 /
Kojto	110:165afa46840b	677	__IO uint32_t PMC; /!< SYSCFG peripheral mode configuration register, Address offset: 0x04 /
Kojto	110:165afa46840b	678	__IO uint32_t EXTICR[4]; /!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 /
Kojto	110:165afa46840b	679	uint32_t RESERVED[2]; /!< Reserved, 0x18-0x1C /
Kojto	110:165afa46840b	680	__IO uint32_t CMPCR; /!< SYSCFG Compensation cell control register, Address offset: 0x20 /
Kojto	110:165afa46840b	681	} SYSCFG_TypeDef;
Kojto	110:165afa46840b	682
Kojto	110:165afa46840b	683	/**
Kojto	110:165afa46840b	684	* @brief Inter-integrated Circuit Interface
Kojto	110:165afa46840b	685	*/
Kojto	110:165afa46840b	686
Kojto	110:165afa46840b	687	typedef struct
Kojto	110:165afa46840b	688	{
Kojto	110:165afa46840b	689	__IO uint32_t CR1; /!< I2C Control register 1, Address offset: 0x00 /
Kojto	110:165afa46840b	690	__IO uint32_t CR2; /!< I2C Control register 2, Address offset: 0x04 /
Kojto	110:165afa46840b	691	__IO uint32_t OAR1; /!< I2C Own address register 1, Address offset: 0x08 /
Kojto	110:165afa46840b	692	__IO uint32_t OAR2; /!< I2C Own address register 2, Address offset: 0x0C /
Kojto	110:165afa46840b	693	__IO uint32_t DR; /!< I2C Data register, Address offset: 0x10 /
Kojto	110:165afa46840b	694	__IO uint32_t SR1; /!< I2C Status register 1, Address offset: 0x14 /
Kojto	110:165afa46840b	695	__IO uint32_t SR2; /!< I2C Status register 2, Address offset: 0x18 /
Kojto	110:165afa46840b	696	__IO uint32_t CCR; /!< I2C Clock control register, Address offset: 0x1C /
Kojto	110:165afa46840b	697	__IO uint32_t TRISE; /!< I2C TRISE register, Address offset: 0x20 /
Kojto	110:165afa46840b	698	__IO uint32_t FLTR; /!< I2C FLTR register, Address offset: 0x24 /
Kojto	110:165afa46840b	699	} I2C_TypeDef;
Kojto	110:165afa46840b	700
Kojto	110:165afa46840b	701	/**
Kojto	110:165afa46840b	702	* @brief Independent WATCHDOG
Kojto	110:165afa46840b	703	*/
Kojto	110:165afa46840b	704
Kojto	110:165afa46840b	705	typedef struct
Kojto	110:165afa46840b	706	{
Kojto	110:165afa46840b	707	__IO uint32_t KR; /!< IWDG Key register, Address offset: 0x00 /
Kojto	110:165afa46840b	708	__IO uint32_t PR; /!< IWDG Prescaler register, Address offset: 0x04 /
Kojto	110:165afa46840b	709	__IO uint32_t RLR; /!< IWDG Reload register, Address offset: 0x08 /
Kojto	110:165afa46840b	710	__IO uint32_t SR; /!< IWDG Status register, Address offset: 0x0C /
Kojto	110:165afa46840b	711	} IWDG_TypeDef;
Kojto	110:165afa46840b	712
Kojto	110:165afa46840b	713	/**
Kojto	110:165afa46840b	714	* @brief LCD-TFT Display Controller
Kojto	110:165afa46840b	715	*/
Kojto	110:165afa46840b	716
Kojto	110:165afa46840b	717	typedef struct
Kojto	110:165afa46840b	718	{
Kojto	110:165afa46840b	719	uint32_t RESERVED0[2]; /!< Reserved, 0x00-0x04 /
Kojto	110:165afa46840b	720	__IO uint32_t SSCR; /!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 /
Kojto	110:165afa46840b	721	__IO uint32_t BPCR; /!< LTDC Back Porch Configuration Register, Address offset: 0x0C /
Kojto	110:165afa46840b	722	__IO uint32_t AWCR; /!< LTDC Active Width Configuration Register, Address offset: 0x10 /
Kojto	110:165afa46840b	723	__IO uint32_t TWCR; /!< LTDC Total Width Configuration Register, Address offset: 0x14 /
Kojto	110:165afa46840b	724	__IO uint32_t GCR; /!< LTDC Global Control Register, Address offset: 0x18 /
Kojto	110:165afa46840b	725	uint32_t RESERVED1[2]; /!< Reserved, 0x1C-0x20 /
Kojto	110:165afa46840b	726	__IO uint32_t SRCR; /!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 /
Kojto	110:165afa46840b	727	uint32_t RESERVED2[1]; /!< Reserved, 0x28 /
Kojto	110:165afa46840b	728	__IO uint32_t BCCR; /!< LTDC Background Color Configuration Register, Address offset: 0x2C /
Kojto	110:165afa46840b	729	uint32_t RESERVED3[1]; /!< Reserved, 0x30 /
Kojto	110:165afa46840b	730	__IO uint32_t IER; /!< LTDC Interrupt Enable Register, Address offset: 0x34 /
Kojto	110:165afa46840b	731	__IO uint32_t ISR; /!< LTDC Interrupt Status Register, Address offset: 0x38 /
Kojto	110:165afa46840b	732	__IO uint32_t ICR; /!< LTDC Interrupt Clear Register, Address offset: 0x3C /
Kojto	110:165afa46840b	733	__IO uint32_t LIPCR; /!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 /
Kojto	110:165afa46840b	734	__IO uint32_t CPSR; /!< LTDC Current Position Status Register, Address offset: 0x44 /
Kojto	110:165afa46840b	735	__IO uint32_t CDSR; /!< LTDC Current Display Status Register, Address offset: 0x48 /
Kojto	110:165afa46840b	736	} LTDC_TypeDef;
Kojto	110:165afa46840b	737
Kojto	110:165afa46840b	738	/**
Kojto	110:165afa46840b	739	* @brief LCD-TFT Display layer x Controller
Kojto	110:165afa46840b	740	*/
Kojto	110:165afa46840b	741
Kojto	110:165afa46840b	742	typedef struct
Kojto	110:165afa46840b	743	{
Kojto	110:165afa46840b	744	__IO uint32_t CR; /!< LTDC Layerx Control Register Address offset: 0x84 /
Kojto	110:165afa46840b	745	__IO uint32_t WHPCR; /!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 /
Kojto	110:165afa46840b	746	__IO uint32_t WVPCR; /!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C /
Kojto	110:165afa46840b	747	__IO uint32_t CKCR; /!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 /
Kojto	110:165afa46840b	748	__IO uint32_t PFCR; /!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 /
Kojto	110:165afa46840b	749	__IO uint32_t CACR; /!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 /
Kojto	110:165afa46840b	750	__IO uint32_t DCCR; /!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C /
Kojto	110:165afa46840b	751	__IO uint32_t BFCR; /!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 /
Kojto	110:165afa46840b	752	uint32_t RESERVED0[2]; /!< Reserved /
Kojto	110:165afa46840b	753	__IO uint32_t CFBAR; /!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC /
Kojto	110:165afa46840b	754	__IO uint32_t CFBLR; /!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 /
Kojto	110:165afa46840b	755	__IO uint32_t CFBLNR; /!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 /
Kojto	110:165afa46840b	756	uint32_t RESERVED1[3]; /!< Reserved /
Kojto	110:165afa46840b	757	__IO uint32_t CLUTWR; /!< LTDC Layerx CLUT Write Register Address offset: 0x144 /
Kojto	110:165afa46840b	758
Kojto	110:165afa46840b	759	} LTDC_Layer_TypeDef;
Kojto	110:165afa46840b	760
Kojto	110:165afa46840b	761	/**
Kojto	110:165afa46840b	762	* @brief Power Control
Kojto	110:165afa46840b	763	*/
Kojto	110:165afa46840b	764
Kojto	110:165afa46840b	765	typedef struct
Kojto	110:165afa46840b	766	{
Kojto	110:165afa46840b	767	__IO uint32_t CR; /!< PWR power control register, Address offset: 0x00 /
Kojto	110:165afa46840b	768	__IO uint32_t CSR; /!< PWR power control/status register, Address offset: 0x04 /
Kojto	110:165afa46840b	769	} PWR_TypeDef;
Kojto	110:165afa46840b	770
Kojto	110:165afa46840b	771	/**
Kojto	110:165afa46840b	772	* @brief Reset and Clock Control
Kojto	110:165afa46840b	773	*/
Kojto	110:165afa46840b	774
Kojto	110:165afa46840b	775	typedef struct
Kojto	110:165afa46840b	776	{
Kojto	110:165afa46840b	777	__IO uint32_t CR; /!< RCC clock control register, Address offset: 0x00 /
Kojto	110:165afa46840b	778	__IO uint32_t PLLCFGR; /!< RCC PLL configuration register, Address offset: 0x04 /
Kojto	110:165afa46840b	779	__IO uint32_t CFGR; /!< RCC clock configuration register, Address offset: 0x08 /
Kojto	110:165afa46840b	780	__IO uint32_t CIR; /!< RCC clock interrupt register, Address offset: 0x0C /
Kojto	110:165afa46840b	781	__IO uint32_t AHB1RSTR; /!< RCC AHB1 peripheral reset register, Address offset: 0x10 /
Kojto	110:165afa46840b	782	__IO uint32_t AHB2RSTR; /!< RCC AHB2 peripheral reset register, Address offset: 0x14 /
Kojto	110:165afa46840b	783	__IO uint32_t AHB3RSTR; /!< RCC AHB3 peripheral reset register, Address offset: 0x18 /
Kojto	110:165afa46840b	784	uint32_t RESERVED0; /!< Reserved, 0x1C /
Kojto	110:165afa46840b	785	__IO uint32_t APB1RSTR; /!< RCC APB1 peripheral reset register, Address offset: 0x20 /
Kojto	110:165afa46840b	786	__IO uint32_t APB2RSTR; /!< RCC APB2 peripheral reset register, Address offset: 0x24 /
Kojto	110:165afa46840b	787	uint32_t RESERVED1[2]; /!< Reserved, 0x28-0x2C /
Kojto	110:165afa46840b	788	__IO uint32_t AHB1ENR; /!< RCC AHB1 peripheral clock register, Address offset: 0x30 /
Kojto	110:165afa46840b	789	__IO uint32_t AHB2ENR; /!< RCC AHB2 peripheral clock register, Address offset: 0x34 /
Kojto	110:165afa46840b	790	__IO uint32_t AHB3ENR; /!< RCC AHB3 peripheral clock register, Address offset: 0x38 /
Kojto	110:165afa46840b	791	uint32_t RESERVED2; /!< Reserved, 0x3C /
Kojto	110:165afa46840b	792	__IO uint32_t APB1ENR; /!< RCC APB1 peripheral clock enable register, Address offset: 0x40 /
Kojto	110:165afa46840b	793	__IO uint32_t APB2ENR; /!< RCC APB2 peripheral clock enable register, Address offset: 0x44 /
Kojto	110:165afa46840b	794	uint32_t RESERVED3[2]; /!< Reserved, 0x48-0x4C /
Kojto	110:165afa46840b	795	__IO uint32_t AHB1LPENR; /!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 /
Kojto	110:165afa46840b	796	__IO uint32_t AHB2LPENR; /!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 /
Kojto	110:165afa46840b	797	__IO uint32_t AHB3LPENR; /!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 /
Kojto	110:165afa46840b	798	uint32_t RESERVED4; /!< Reserved, 0x5C /
Kojto	110:165afa46840b	799	__IO uint32_t APB1LPENR; /!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 /
Kojto	110:165afa46840b	800	__IO uint32_t APB2LPENR; /!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 /
Kojto	110:165afa46840b	801	uint32_t RESERVED5[2]; /!< Reserved, 0x68-0x6C /
Kojto	110:165afa46840b	802	__IO uint32_t BDCR; /!< RCC Backup domain control register, Address offset: 0x70 /
Kojto	110:165afa46840b	803	__IO uint32_t CSR; /!< RCC clock control & status register, Address offset: 0x74 /
Kojto	110:165afa46840b	804	uint32_t RESERVED6[2]; /!< Reserved, 0x78-0x7C /
Kojto	110:165afa46840b	805	__IO uint32_t SSCGR; /!< RCC spread spectrum clock generation register, Address offset: 0x80 /
Kojto	110:165afa46840b	806	__IO uint32_t PLLI2SCFGR; /!< RCC PLLI2S configuration register, Address offset: 0x84 /
Kojto	110:165afa46840b	807	__IO uint32_t PLLSAICFGR; /!< RCC PLLSAI configuration register, Address offset: 0x88 /
Kojto	110:165afa46840b	808	__IO uint32_t DCKCFGR; /!< RCC Dedicated Clocks configuration register, Address offset: 0x8C /
Kojto	110:165afa46840b	809
Kojto	110:165afa46840b	810	} RCC_TypeDef;
Kojto	110:165afa46840b	811
Kojto	110:165afa46840b	812	/**
Kojto	110:165afa46840b	813	* @brief Real-Time Clock
Kojto	110:165afa46840b	814	*/
Kojto	110:165afa46840b	815
Kojto	110:165afa46840b	816	typedef struct
Kojto	110:165afa46840b	817	{
Kojto	110:165afa46840b	818	__IO uint32_t TR; /!< RTC time register, Address offset: 0x00 /
Kojto	110:165afa46840b	819	__IO uint32_t DR; /!< RTC date register, Address offset: 0x04 /
Kojto	110:165afa46840b	820	__IO uint32_t CR; /!< RTC control register, Address offset: 0x08 /
Kojto	110:165afa46840b	821	__IO uint32_t ISR; /!< RTC initialization and status register, Address offset: 0x0C /
Kojto	110:165afa46840b	822	__IO uint32_t PRER; /!< RTC prescaler register, Address offset: 0x10 /
Kojto	110:165afa46840b	823	__IO uint32_t WUTR; /!< RTC wakeup timer register, Address offset: 0x14 /
Kojto	110:165afa46840b	824	__IO uint32_t CALIBR; /!< RTC calibration register, Address offset: 0x18 /
Kojto	110:165afa46840b	825	__IO uint32_t ALRMAR; /!< RTC alarm A register, Address offset: 0x1C /
Kojto	110:165afa46840b	826	__IO uint32_t ALRMBR; /!< RTC alarm B register, Address offset: 0x20 /
Kojto	110:165afa46840b	827	__IO uint32_t WPR; /!< RTC write protection register, Address offset: 0x24 /
Kojto	110:165afa46840b	828	__IO uint32_t SSR; /!< RTC sub second register, Address offset: 0x28 /
Kojto	110:165afa46840b	829	__IO uint32_t SHIFTR; /!< RTC shift control register, Address offset: 0x2C /
Kojto	110:165afa46840b	830	__IO uint32_t TSTR; /!< RTC time stamp time register, Address offset: 0x30 /
Kojto	110:165afa46840b	831	__IO uint32_t TSDR; /!< RTC time stamp date register, Address offset: 0x34 /
Kojto	110:165afa46840b	832	__IO uint32_t TSSSR; /!< RTC time-stamp sub second register, Address offset: 0x38 /
Kojto	110:165afa46840b	833	__IO uint32_t CALR; /!< RTC calibration register, Address offset: 0x3C /
Kojto	110:165afa46840b	834	__IO uint32_t TAFCR; /!< RTC tamper and alternate function configuration register, Address offset: 0x40 /
Kojto	110:165afa46840b	835	__IO uint32_t ALRMASSR;/!< RTC alarm A sub second register, Address offset: 0x44 /
Kojto	110:165afa46840b	836	__IO uint32_t ALRMBSSR;/!< RTC alarm B sub second register, Address offset: 0x48 /
Kojto	110:165afa46840b	837	uint32_t RESERVED7; /!< Reserved, 0x4C /
Kojto	110:165afa46840b	838	__IO uint32_t BKP0R; /!< RTC backup register 1, Address offset: 0x50 /
Kojto	110:165afa46840b	839	__IO uint32_t BKP1R; /!< RTC backup register 1, Address offset: 0x54 /
Kojto	110:165afa46840b	840	__IO uint32_t BKP2R; /!< RTC backup register 2, Address offset: 0x58 /
Kojto	110:165afa46840b	841	__IO uint32_t BKP3R; /!< RTC backup register 3, Address offset: 0x5C /
Kojto	110:165afa46840b	842	__IO uint32_t BKP4R; /!< RTC backup register 4, Address offset: 0x60 /
Kojto	110:165afa46840b	843	__IO uint32_t BKP5R; /!< RTC backup register 5, Address offset: 0x64 /
Kojto	110:165afa46840b	844	__IO uint32_t BKP6R; /!< RTC backup register 6, Address offset: 0x68 /
Kojto	110:165afa46840b	845	__IO uint32_t BKP7R; /!< RTC backup register 7, Address offset: 0x6C /
Kojto	110:165afa46840b	846	__IO uint32_t BKP8R; /!< RTC backup register 8, Address offset: 0x70 /
Kojto	110:165afa46840b	847	__IO uint32_t BKP9R; /!< RTC backup register 9, Address offset: 0x74 /
Kojto	110:165afa46840b	848	__IO uint32_t BKP10R; /!< RTC backup register 10, Address offset: 0x78 /
Kojto	110:165afa46840b	849	__IO uint32_t BKP11R; /!< RTC backup register 11, Address offset: 0x7C /
Kojto	110:165afa46840b	850	__IO uint32_t BKP12R; /!< RTC backup register 12, Address offset: 0x80 /
Kojto	110:165afa46840b	851	__IO uint32_t BKP13R; /!< RTC backup register 13, Address offset: 0x84 /
Kojto	110:165afa46840b	852	__IO uint32_t BKP14R; /!< RTC backup register 14, Address offset: 0x88 /
Kojto	110:165afa46840b	853	__IO uint32_t BKP15R; /!< RTC backup register 15, Address offset: 0x8C /
Kojto	110:165afa46840b	854	__IO uint32_t BKP16R; /!< RTC backup register 16, Address offset: 0x90 /
Kojto	110:165afa46840b	855	__IO uint32_t BKP17R; /!< RTC backup register 17, Address offset: 0x94 /
Kojto	110:165afa46840b	856	__IO uint32_t BKP18R; /!< RTC backup register 18, Address offset: 0x98 /
Kojto	110:165afa46840b	857	__IO uint32_t BKP19R; /!< RTC backup register 19, Address offset: 0x9C /
Kojto	110:165afa46840b	858	} RTC_TypeDef;
Kojto	110:165afa46840b	859
Kojto	110:165afa46840b	860	/**
Kojto	110:165afa46840b	861	* @brief Serial Audio Interface
Kojto	110:165afa46840b	862	*/
Kojto	110:165afa46840b	863
Kojto	110:165afa46840b	864	typedef struct
Kojto	110:165afa46840b	865	{
Kojto	110:165afa46840b	866	__IO uint32_t GCR; /!< SAI global configuration register, Address offset: 0x00 /
Kojto	110:165afa46840b	867	} SAI_TypeDef;
Kojto	110:165afa46840b	868
Kojto	110:165afa46840b	869	typedef struct
Kojto	110:165afa46840b	870	{
Kojto	110:165afa46840b	871	__IO uint32_t CR1; /!< SAI block x configuration register 1, Address offset: 0x04 /
Kojto	110:165afa46840b	872	__IO uint32_t CR2; /!< SAI block x configuration register 2, Address offset: 0x08 /
Kojto	110:165afa46840b	873	__IO uint32_t FRCR; /!< SAI block x frame configuration register, Address offset: 0x0C /
Kojto	110:165afa46840b	874	__IO uint32_t SLOTR; /!< SAI block x slot register, Address offset: 0x10 /
Kojto	110:165afa46840b	875	__IO uint32_t IMR; /!< SAI block x interrupt mask register, Address offset: 0x14 /
Kojto	110:165afa46840b	876	__IO uint32_t SR; /!< SAI block x status register, Address offset: 0x18 /
Kojto	110:165afa46840b	877	__IO uint32_t CLRFR; /!< SAI block x clear flag register, Address offset: 0x1C /
Kojto	110:165afa46840b	878	__IO uint32_t DR; /!< SAI block x data register, Address offset: 0x20 /
Kojto	110:165afa46840b	879	} SAI_Block_TypeDef;
Kojto	110:165afa46840b	880
Kojto	110:165afa46840b	881	/**
Kojto	110:165afa46840b	882	* @brief SD host Interface
Kojto	110:165afa46840b	883	*/
Kojto	110:165afa46840b	884
Kojto	110:165afa46840b	885	typedef struct
Kojto	110:165afa46840b	886	{
Kojto	110:165afa46840b	887	__IO uint32_t POWER; /!< SDIO power control register, Address offset: 0x00 /
Kojto	110:165afa46840b	888	__IO uint32_t CLKCR; /!< SDI clock control register, Address offset: 0x04 /
Kojto	110:165afa46840b	889	__IO uint32_t ARG; /!< SDIO argument register, Address offset: 0x08 /
Kojto	110:165afa46840b	890	__IO uint32_t CMD; /!< SDIO command register, Address offset: 0x0C /
Kojto	110:165afa46840b	891	__I uint32_t RESPCMD; /!< SDIO command response register, Address offset: 0x10 /
Kojto	110:165afa46840b	892	__I uint32_t RESP1; /!< SDIO response 1 register, Address offset: 0x14 /
Kojto	110:165afa46840b	893	__I uint32_t RESP2; /!< SDIO response 2 register, Address offset: 0x18 /
Kojto	110:165afa46840b	894	__I uint32_t RESP3; /!< SDIO response 3 register, Address offset: 0x1C /
Kojto	110:165afa46840b	895	__I uint32_t RESP4; /!< SDIO response 4 register, Address offset: 0x20 /
Kojto	110:165afa46840b	896	__IO uint32_t DTIMER; /!< SDIO data timer register, Address offset: 0x24 /
Kojto	110:165afa46840b	897	__IO uint32_t DLEN; /!< SDIO data length register, Address offset: 0x28 /
Kojto	110:165afa46840b	898	__IO uint32_t DCTRL; /!< SDIO data control register, Address offset: 0x2C /
Kojto	110:165afa46840b	899	__I uint32_t DCOUNT; /!< SDIO data counter register, Address offset: 0x30 /
Kojto	110:165afa46840b	900	__I uint32_t STA; /!< SDIO status register, Address offset: 0x34 /
Kojto	110:165afa46840b	901	__IO uint32_t ICR; /!< SDIO interrupt clear register, Address offset: 0x38 /
Kojto	110:165afa46840b	902	__IO uint32_t MASK; /!< SDIO mask register, Address offset: 0x3C /
Kojto	110:165afa46840b	903	uint32_t RESERVED0[2]; /!< Reserved, 0x40-0x44 /
Kojto	110:165afa46840b	904	__I uint32_t FIFOCNT; /!< SDIO FIFO counter register, Address offset: 0x48 /
Kojto	110:165afa46840b	905	uint32_t RESERVED1[13]; /!< Reserved, 0x4C-0x7C /
Kojto	110:165afa46840b	906	__IO uint32_t FIFO; /!< SDIO data FIFO register, Address offset: 0x80 /
Kojto	110:165afa46840b	907	} SDIO_TypeDef;
Kojto	110:165afa46840b	908
Kojto	110:165afa46840b	909	/**
Kojto	110:165afa46840b	910	* @brief Serial Peripheral Interface
Kojto	110:165afa46840b	911	*/
Kojto	110:165afa46840b	912
Kojto	110:165afa46840b	913	typedef struct
Kojto	110:165afa46840b	914	{
Kojto	110:165afa46840b	915	__IO uint32_t CR1; /!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 /
Kojto	110:165afa46840b	916	__IO uint32_t CR2; /!< SPI control register 2, Address offset: 0x04 /
Kojto	110:165afa46840b	917	__IO uint32_t SR; /!< SPI status register, Address offset: 0x08 /
Kojto	110:165afa46840b	918	__IO uint32_t DR; /!< SPI data register, Address offset: 0x0C /
Kojto	110:165afa46840b	919	__IO uint32_t CRCPR; /!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 /
Kojto	110:165afa46840b	920	__IO uint32_t RXCRCR; /!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 /
Kojto	110:165afa46840b	921	__IO uint32_t TXCRCR; /!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 /
Kojto	110:165afa46840b	922	__IO uint32_t I2SCFGR; /!< SPI_I2S configuration register, Address offset: 0x1C /
Kojto	110:165afa46840b	923	__IO uint32_t I2SPR; /!< SPI_I2S prescaler register, Address offset: 0x20 /
Kojto	110:165afa46840b	924	} SPI_TypeDef;
Kojto	110:165afa46840b	925
Kojto	110:165afa46840b	926	/**
Kojto	110:165afa46840b	927	* @brief QUAD Serial Peripheral Interface
Kojto	110:165afa46840b	928	*/
Kojto	110:165afa46840b	929
Kojto	110:165afa46840b	930	typedef struct
Kojto	110:165afa46840b	931	{
Kojto	110:165afa46840b	932	__IO uint32_t CR; /!< QUADSPI Control register, Address offset: 0x00 /
Kojto	110:165afa46840b	933	__IO uint32_t DCR; /!< QUADSPI Device Configuration register, Address offset: 0x04 /
Kojto	110:165afa46840b	934	__IO uint32_t SR; /!< QUADSPI Status register, Address offset: 0x08 /
Kojto	110:165afa46840b	935	__IO uint32_t FCR; /!< QUADSPI Flag Clear register, Address offset: 0x0C /
Kojto	110:165afa46840b	936	__IO uint32_t DLR; /!< QUADSPI Data Length register, Address offset: 0x10 /
Kojto	110:165afa46840b	937	__IO uint32_t CCR; /!< QUADSPI Communication Configuration register, Address offset: 0x14 /
Kojto	110:165afa46840b	938	__IO uint32_t AR; /!< QUADSPI Address register, Address offset: 0x18 /
Kojto	110:165afa46840b	939	__IO uint32_t ABR; /!< QUADSPI Alternate Bytes register, Address offset: 0x1C /
Kojto	110:165afa46840b	940	__IO uint32_t DR; /!< QUADSPI Data register, Address offset: 0x20 /
Kojto	110:165afa46840b	941	__IO uint32_t PSMKR; /!< QUADSPI Polling Status Mask register, Address offset: 0x24 /
Kojto	110:165afa46840b	942	__IO uint32_t PSMAR; /!< QUADSPI Polling Status Match register, Address offset: 0x28 /
Kojto	110:165afa46840b	943	__IO uint32_t PIR; /!< QUADSPI Polling Interval register, Address offset: 0x2C /
Kojto	110:165afa46840b	944	__IO uint32_t LPTR; /!< QUADSPI Low Power Timeout register, Address offset: 0x30 /
Kojto	110:165afa46840b	945	} QUADSPI_TypeDef;
Kojto	110:165afa46840b	946
Kojto	110:165afa46840b	947	/**
Kojto	110:165afa46840b	948	* @brief TIM
Kojto	110:165afa46840b	949	*/
Kojto	110:165afa46840b	950
Kojto	110:165afa46840b	951	typedef struct
Kojto	110:165afa46840b	952	{
Kojto	110:165afa46840b	953	__IO uint32_t CR1; /!< TIM control register 1, Address offset: 0x00 /
Kojto	110:165afa46840b	954	__IO uint32_t CR2; /!< TIM control register 2, Address offset: 0x04 /
Kojto	110:165afa46840b	955	__IO uint32_t SMCR; /!< TIM slave mode control register, Address offset: 0x08 /
Kojto	110:165afa46840b	956	__IO uint32_t DIER; /!< TIM DMA/interrupt enable register, Address offset: 0x0C /
Kojto	110:165afa46840b	957	__IO uint32_t SR; /!< TIM status register, Address offset: 0x10 /
Kojto	110:165afa46840b	958	__IO uint32_t EGR; /!< TIM event generation register, Address offset: 0x14 /
Kojto	110:165afa46840b	959	__IO uint32_t CCMR1; /!< TIM capture/compare mode register 1, Address offset: 0x18 /
Kojto	110:165afa46840b	960	__IO uint32_t CCMR2; /!< TIM capture/compare mode register 2, Address offset: 0x1C /
Kojto	110:165afa46840b	961	__IO uint32_t CCER; /!< TIM capture/compare enable register, Address offset: 0x20 /
Kojto	110:165afa46840b	962	__IO uint32_t CNT; /!< TIM counter register, Address offset: 0x24 /
Kojto	110:165afa46840b	963	__IO uint32_t PSC; /!< TIM prescaler, Address offset: 0x28 /
Kojto	110:165afa46840b	964	__IO uint32_t ARR; /!< TIM auto-reload register, Address offset: 0x2C /
Kojto	110:165afa46840b	965	__IO uint32_t RCR; /!< TIM repetition counter register, Address offset: 0x30 /
Kojto	110:165afa46840b	966	__IO uint32_t CCR1; /!< TIM capture/compare register 1, Address offset: 0x34 /
Kojto	110:165afa46840b	967	__IO uint32_t CCR2; /!< TIM capture/compare register 2, Address offset: 0x38 /
Kojto	110:165afa46840b	968	__IO uint32_t CCR3; /!< TIM capture/compare register 3, Address offset: 0x3C /
Kojto	110:165afa46840b	969	__IO uint32_t CCR4; /!< TIM capture/compare register 4, Address offset: 0x40 /
Kojto	110:165afa46840b	970	__IO uint32_t BDTR; /!< TIM break and dead-time register, Address offset: 0x44 /
Kojto	110:165afa46840b	971	__IO uint32_t DCR; /!< TIM DMA control register, Address offset: 0x48 /
Kojto	110:165afa46840b	972	__IO uint32_t DMAR; /!< TIM DMA address for full transfer, Address offset: 0x4C /
Kojto	110:165afa46840b	973	__IO uint32_t OR; /!< TIM option register, Address offset: 0x50 /
Kojto	110:165afa46840b	974	} TIM_TypeDef;
Kojto	110:165afa46840b	975
Kojto	110:165afa46840b	976	/**
Kojto	110:165afa46840b	977	* @brief Universal Synchronous Asynchronous Receiver Transmitter
Kojto	110:165afa46840b	978	*/
Kojto	110:165afa46840b	979
Kojto	110:165afa46840b	980	typedef struct
Kojto	110:165afa46840b	981	{
Kojto	110:165afa46840b	982	__IO uint32_t SR; /!< USART Status register, Address offset: 0x00 /
Kojto	110:165afa46840b	983	__IO uint32_t DR; /!< USART Data register, Address offset: 0x04 /
Kojto	110:165afa46840b	984	__IO uint32_t BRR; /!< USART Baud rate register, Address offset: 0x08 /
Kojto	110:165afa46840b	985	__IO uint32_t CR1; /!< USART Control register 1, Address offset: 0x0C /
Kojto	110:165afa46840b	986	__IO uint32_t CR2; /!< USART Control register 2, Address offset: 0x10 /
Kojto	110:165afa46840b	987	__IO uint32_t CR3; /!< USART Control register 3, Address offset: 0x14 /
Kojto	110:165afa46840b	988	__IO uint32_t GTPR; /!< USART Guard time and prescaler register, Address offset: 0x18 /
Kojto	110:165afa46840b	989	} USART_TypeDef;
Kojto	110:165afa46840b	990
Kojto	110:165afa46840b	991	/**
Kojto	110:165afa46840b	992	* @brief Window WATCHDOG
Kojto	110:165afa46840b	993	*/
Kojto	110:165afa46840b	994
Kojto	110:165afa46840b	995	typedef struct
Kojto	110:165afa46840b	996	{
Kojto	110:165afa46840b	997	__IO uint32_t CR; /!< WWDG Control register, Address offset: 0x00 /
Kojto	110:165afa46840b	998	__IO uint32_t CFR; /!< WWDG Configuration register, Address offset: 0x04 /
Kojto	110:165afa46840b	999	__IO uint32_t SR; /!< WWDG Status register, Address offset: 0x08 /
Kojto	110:165afa46840b	1000	} WWDG_TypeDef;
Kojto	110:165afa46840b	1001
Kojto	110:165afa46840b	1002	/**
Kojto	110:165afa46840b	1003	* @brief RNG
Kojto	110:165afa46840b	1004	*/
Kojto	110:165afa46840b	1005
Kojto	110:165afa46840b	1006	typedef struct
Kojto	110:165afa46840b	1007	{
Kojto	110:165afa46840b	1008	__IO uint32_t CR; /!< RNG control register, Address offset: 0x00 /
Kojto	110:165afa46840b	1009	__IO uint32_t SR; /!< RNG status register, Address offset: 0x04 /
Kojto	110:165afa46840b	1010	__IO uint32_t DR; /!< RNG data register, Address offset: 0x08 /
Kojto	110:165afa46840b	1011	} RNG_TypeDef;
Kojto	110:165afa46840b	1012
Kojto	110:165afa46840b	1013
Kojto	110:165afa46840b	1014	/**
Kojto	110:165afa46840b	1015	* @brief USB_OTG_Core_Registers
Kojto	110:165afa46840b	1016	*/
Kojto	110:165afa46840b	1017	typedef struct
Kojto	110:165afa46840b	1018	{
Kojto	110:165afa46840b	1019	__IO uint32_t GOTGCTL; /!< USB_OTG Control and Status Register 000h /
Kojto	110:165afa46840b	1020	__IO uint32_t GOTGINT; /!< USB_OTG Interrupt Register 004h /
Kojto	110:165afa46840b	1021	__IO uint32_t GAHBCFG; /!< Core AHB Configuration Register 008h /
Kojto	110:165afa46840b	1022	__IO uint32_t GUSBCFG; /!< Core USB Configuration Register 00Ch /
Kojto	110:165afa46840b	1023	__IO uint32_t GRSTCTL; /!< Core Reset Register 010h /
Kojto	110:165afa46840b	1024	__IO uint32_t GINTSTS; /!< Core Interrupt Register 014h /
Kojto	110:165afa46840b	1025	__IO uint32_t GINTMSK; /!< Core Interrupt Mask Register 018h /
Kojto	110:165afa46840b	1026	__IO uint32_t GRXSTSR; /!< Receive Sts Q Read Register 01Ch /
Kojto	110:165afa46840b	1027	__IO uint32_t GRXSTSP; /!< Receive Sts Q Read & POP Register 020h /
Kojto	110:165afa46840b	1028	__IO uint32_t GRXFSIZ; /!< Receive FIFO Size Register 024h /
Kojto	110:165afa46840b	1029	__IO uint32_t DIEPTXF0_HNPTXFSIZ; /!< EP0 / Non Periodic Tx FIFO Size Register 028h /
Kojto	110:165afa46840b	1030	__IO uint32_t HNPTXSTS; /!< Non Periodic Tx FIFO/Queue Sts reg 02Ch /
Kojto	110:165afa46840b	1031	uint32_t Reserved30[2]; /!< Reserved 030h /
Kojto	110:165afa46840b	1032	__IO uint32_t GCCFG; /!< General Purpose IO Register 038h /
Kojto	110:165afa46840b	1033	__IO uint32_t CID; /!< User ID Register 03Ch /
Kojto	110:165afa46840b	1034	uint32_t Reserved5[3]; /!< Reserved 040h-048h /
Kojto	110:165afa46840b	1035	__IO uint32_t GHWCFG3; /!< User HW config3 04Ch /
Kojto	110:165afa46840b	1036	uint32_t Reserved6; /!< Reserved 050h /
Kojto	110:165afa46840b	1037	__IO uint32_t GLPMCFG; /!< LPM Register 054h /
Kojto	122:f9eeca106725	1038	uint32_t Reserved; /!< Reserved 058h /
Kojto	110:165afa46840b	1039	__IO uint32_t GDFIFOCFG; /!< DFIFO Software Config Register 05Ch /
Kojto	122:f9eeca106725	1040	uint32_t Reserved43[40]; /!< Reserved 058h-0FFh /
Kojto	110:165afa46840b	1041	__IO uint32_t HPTXFSIZ; /!< Host Periodic Tx FIFO Size Reg 100h /
Kojto	110:165afa46840b	1042	__IO uint32_t DIEPTXF[0x0F]; /!< dev Periodic Transmit FIFO /
Kojto	110:165afa46840b	1043	} USB_OTG_GlobalTypeDef;
Kojto	110:165afa46840b	1044
Kojto	110:165afa46840b	1045	/**
Kojto	110:165afa46840b	1046	* @brief USB_OTG_device_Registers
Kojto	110:165afa46840b	1047	*/
Kojto	110:165afa46840b	1048	typedef struct
Kojto	110:165afa46840b	1049	{
Kojto	110:165afa46840b	1050	__IO uint32_t DCFG; /!< dev Configuration Register 800h /
Kojto	110:165afa46840b	1051	__IO uint32_t DCTL; /!< dev Control Register 804h /
Kojto	110:165afa46840b	1052	__IO uint32_t DSTS; /!< dev Status Register (RO) 808h /
Kojto	110:165afa46840b	1053	uint32_t Reserved0C; /!< Reserved 80Ch /
Kojto	110:165afa46840b	1054	__IO uint32_t DIEPMSK; /!< dev IN Endpoint Mask 810h /
Kojto	110:165afa46840b	1055	__IO uint32_t DOEPMSK; /!< dev OUT Endpoint Mask 814h /
Kojto	110:165afa46840b	1056	__IO uint32_t DAINT; /!< dev All Endpoints Itr Reg 818h /
Kojto	110:165afa46840b	1057	__IO uint32_t DAINTMSK; /!< dev All Endpoints Itr Mask 81Ch /
Kojto	110:165afa46840b	1058	uint32_t Reserved20; /!< Reserved 820h /
Kojto	110:165afa46840b	1059	uint32_t Reserved9; /!< Reserved 824h /
Kojto	110:165afa46840b	1060	__IO uint32_t DVBUSDIS; /!< dev VBUS discharge Register 828h /
Kojto	110:165afa46840b	1061	__IO uint32_t DVBUSPULSE; /!< dev VBUS Pulse Register 82Ch /
Kojto	110:165afa46840b	1062	__IO uint32_t DTHRCTL; /!< dev threshold 830h /
Kojto	110:165afa46840b	1063	__IO uint32_t DIEPEMPMSK; /!< dev empty msk 834h /
Kojto	110:165afa46840b	1064	__IO uint32_t DEACHINT; /!< dedicated EP interrupt 838h /
Kojto	110:165afa46840b	1065	__IO uint32_t DEACHMSK; /!< dedicated EP msk 83Ch /
Kojto	110:165afa46840b	1066	uint32_t Reserved40; /!< dedicated EP mask 840h /
Kojto	110:165afa46840b	1067	__IO uint32_t DINEP1MSK; /!< dedicated EP mask 844h /
Kojto	110:165afa46840b	1068	uint32_t Reserved44[15]; /!< Reserved 844-87Ch /
Kojto	110:165afa46840b	1069	__IO uint32_t DOUTEP1MSK; /!< dedicated EP msk 884h /
Kojto	110:165afa46840b	1070	} USB_OTG_DeviceTypeDef;
Kojto	110:165afa46840b	1071
Kojto	110:165afa46840b	1072	/**
Kojto	110:165afa46840b	1073	* @brief USB_OTG_IN_Endpoint-Specific_Register
Kojto	110:165afa46840b	1074	*/
Kojto	110:165afa46840b	1075	typedef struct
Kojto	110:165afa46840b	1076	{
Kojto	110:165afa46840b	1077	__IO uint32_t DIEPCTL; /!< dev IN Endpoint Control Reg 900h + (ep_num 20h) + 00h */
Kojto	110:165afa46840b	1078	uint32_t Reserved04; /!< Reserved 900h + (ep_num 20h) + 04h */
Kojto	110:165afa46840b	1079	__IO uint32_t DIEPINT; /!< dev IN Endpoint Itr Reg 900h + (ep_num 20h) + 08h */
Kojto	110:165afa46840b	1080	uint32_t Reserved0C; /!< Reserved 900h + (ep_num 20h) + 0Ch */
Kojto	110:165afa46840b	1081	__IO uint32_t DIEPTSIZ; /!< IN Endpoint Txfer Size 900h + (ep_num 20h) + 10h */
Kojto	110:165afa46840b	1082	__IO uint32_t DIEPDMA; /!< IN Endpoint DMA Address Reg 900h + (ep_num 20h) + 14h */
Kojto	110:165afa46840b	1083	__IO uint32_t DTXFSTS; /!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num 20h) + 18h */
Kojto	110:165afa46840b	1084	uint32_t Reserved18; /!< Reserved 900h+(ep_num20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
Kojto	110:165afa46840b	1085	} USB_OTG_INEndpointTypeDef;
Kojto	110:165afa46840b	1086
Kojto	110:165afa46840b	1087	/**
Kojto	110:165afa46840b	1088	* @brief USB_OTG_OUT_Endpoint-Specific_Registers
Kojto	110:165afa46840b	1089	*/
Kojto	110:165afa46840b	1090	typedef struct
Kojto	110:165afa46840b	1091	{
Kojto	110:165afa46840b	1092	__IO uint32_t DOEPCTL; /!< dev OUT Endpoint Control Reg B00h + (ep_num 20h) + 00h */
Kojto	110:165afa46840b	1093	uint32_t Reserved04; /!< Reserved B00h + (ep_num 20h) + 04h */
Kojto	110:165afa46840b	1094	__IO uint32_t DOEPINT; /!< dev OUT Endpoint Itr Reg B00h + (ep_num 20h) + 08h */
Kojto	110:165afa46840b	1095	uint32_t Reserved0C; /!< Reserved B00h + (ep_num 20h) + 0Ch */
Kojto	110:165afa46840b	1096	__IO uint32_t DOEPTSIZ; /!< dev OUT Endpoint Txfer Size B00h + (ep_num 20h) + 10h */
Kojto	110:165afa46840b	1097	__IO uint32_t DOEPDMA; /!< dev OUT Endpoint DMA Address B00h + (ep_num 20h) + 14h */
Kojto	110:165afa46840b	1098	uint32_t Reserved18[2]; /!< Reserved B00h + (ep_num 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
Kojto	110:165afa46840b	1099	} USB_OTG_OUTEndpointTypeDef;
Kojto	110:165afa46840b	1100
Kojto	110:165afa46840b	1101	/**
Kojto	110:165afa46840b	1102	* @brief USB_OTG_Host_Mode_Register_Structures
Kojto	110:165afa46840b	1103	*/
Kojto	110:165afa46840b	1104	typedef struct
Kojto	110:165afa46840b	1105	{
Kojto	110:165afa46840b	1106	__IO uint32_t HCFG; /!< Host Configuration Register 400h /
Kojto	110:165afa46840b	1107	__IO uint32_t HFIR; /!< Host Frame Interval Register 404h /
Kojto	110:165afa46840b	1108	__IO uint32_t HFNUM; /!< Host Frame Nbr/Frame Remaining 408h /
Kojto	110:165afa46840b	1109	uint32_t Reserved40C; /!< Reserved 40Ch /
Kojto	110:165afa46840b	1110	__IO uint32_t HPTXSTS; /!< Host Periodic Tx FIFO/ Queue Status 410h /
Kojto	110:165afa46840b	1111	__IO uint32_t HAINT; /!< Host All Channels Interrupt Register 414h /
Kojto	110:165afa46840b	1112	__IO uint32_t HAINTMSK; /!< Host All Channels Interrupt Mask 418h /
Kojto	110:165afa46840b	1113	} USB_OTG_HostTypeDef;
Kojto	110:165afa46840b	1114
Kojto	110:165afa46840b	1115	/**
Kojto	110:165afa46840b	1116	* @brief USB_OTG_Host_Channel_Specific_Registers
Kojto	110:165afa46840b	1117	*/
Kojto	110:165afa46840b	1118	typedef struct
Kojto	110:165afa46840b	1119	{
Kojto	110:165afa46840b	1120	__IO uint32_t HCCHAR; /!< Host Channel Characteristics Register 500h /
Kojto	110:165afa46840b	1121	__IO uint32_t HCSPLT; /!< Host Channel Split Control Register 504h /
Kojto	110:165afa46840b	1122	__IO uint32_t HCINT; /!< Host Channel Interrupt Register 508h /
Kojto	110:165afa46840b	1123	__IO uint32_t HCINTMSK; /!< Host Channel Interrupt Mask Register 50Ch /
Kojto	110:165afa46840b	1124	__IO uint32_t HCTSIZ; /!< Host Channel Transfer Size Register 510h /
Kojto	110:165afa46840b	1125	__IO uint32_t HCDMA; /!< Host Channel DMA Address Register 514h /
Kojto	110:165afa46840b	1126	uint32_t Reserved[2]; /!< Reserved /
Kojto	110:165afa46840b	1127	} USB_OTG_HostChannelTypeDef;
Kojto	110:165afa46840b	1128
Kojto	110:165afa46840b	1129	/**
Kojto	110:165afa46840b	1130	* @}
Kojto	110:165afa46840b	1131	*/
Kojto	110:165afa46840b	1132
Kojto	110:165afa46840b	1133	/** @addtogroup Peripheral_memory_map
Kojto	110:165afa46840b	1134	* @{
Kojto	110:165afa46840b	1135	*/
Kojto	122:f9eeca106725	1136	#define FLASH_BASE 0x08000000U /!< FLASH(up to 1 MB) base address in the alias region /
Kojto	122:f9eeca106725	1137	#define CCMDATARAM_BASE 0x10000000U /!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region /
Kojto	122:f9eeca106725	1138	#define SRAM1_BASE 0x20000000U /!< SRAM1(160 KB) base address in the alias region /
Kojto	122:f9eeca106725	1139	#define SRAM2_BASE 0x20028000U /!< SRAM2(32 KB) base address in the alias region /
Kojto	122:f9eeca106725	1140	#define SRAM3_BASE 0x20030000U /!< SRAM3(128 KB) base address in the alias region /
Kojto	122:f9eeca106725	1141	#define PERIPH_BASE 0x40000000U /!< Peripheral base address in the alias region /
Kojto	122:f9eeca106725	1142	#define BKPSRAM_BASE 0x40024000U /!< Backup SRAM(4 KB) base address in the alias region /
Kojto	122:f9eeca106725	1143	#define FMC_R_BASE 0xA0000000U /!< FMC registers base address /
Kojto	122:f9eeca106725	1144	#define QSPI_R_BASE 0xA0001000U /!< QuadSPI registers base address /
Kojto	122:f9eeca106725	1145	#define SRAM1_BB_BASE 0x22000000U /!< SRAM1(112 KB) base address in the bit-band region /
Kojto	122:f9eeca106725	1146	#define SRAM2_BB_BASE 0x22500000U /!< SRAM2(16 KB) base address in the bit-band region /
Kojto	122:f9eeca106725	1147	#define SRAM3_BB_BASE 0x22600000U /!< SRAM3(64 KB) base address in the bit-band region /
Kojto	122:f9eeca106725	1148	#define PERIPH_BB_BASE 0x42000000U /!< Peripheral base address in the bit-band region /
Kojto	122:f9eeca106725	1149	#define BKPSRAM_BB_BASE 0x42480000U /!< Backup SRAM(4 KB) base address in the bit-band region /
Kojto	122:f9eeca106725	1150	#define FLASH_END 0x081FFFFFU /!< FLASH end address /
Kojto	122:f9eeca106725	1151	#define CCMDATARAM_END 0x1000FFFFU /!< CCM data RAM end address /
Kojto	110:165afa46840b	1152
Kojto	110:165afa46840b	1153	/* Legacy defines */
Kojto	110:165afa46840b	1154	#define SRAM_BASE SRAM1_BASE
Kojto	110:165afa46840b	1155	#define SRAM_BB_BASE SRAM1_BB_BASE
Kojto	110:165afa46840b	1156
Kojto	110:165afa46840b	1157
Kojto	110:165afa46840b	1158	/!< Peripheral memory map /
Kojto	110:165afa46840b	1159	#define APB1PERIPH_BASE PERIPH_BASE
Kojto	122:f9eeca106725	1160	#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
Kojto	122:f9eeca106725	1161	#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
Kojto	122:f9eeca106725	1162	#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
Kojto	110:165afa46840b	1163
Kojto	110:165afa46840b	1164	/!< APB1 peripherals /
Kojto	122:f9eeca106725	1165	#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
Kojto	122:f9eeca106725	1166	#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
Kojto	122:f9eeca106725	1167	#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
Kojto	122:f9eeca106725	1168	#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
Kojto	122:f9eeca106725	1169	#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
Kojto	122:f9eeca106725	1170	#define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
Kojto	122:f9eeca106725	1171	#define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
Kojto	122:f9eeca106725	1172	#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
Kojto	122:f9eeca106725	1173	#define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
Kojto	122:f9eeca106725	1174	#define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
Kojto	122:f9eeca106725	1175	#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
Kojto	122:f9eeca106725	1176	#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
Kojto	122:f9eeca106725	1177	#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
Kojto	122:f9eeca106725	1178	#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
Kojto	122:f9eeca106725	1179	#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
Kojto	122:f9eeca106725	1180	#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
Kojto	122:f9eeca106725	1181	#define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
Kojto	122:f9eeca106725	1182	#define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
Kojto	122:f9eeca106725	1183	#define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
Kojto	122:f9eeca106725	1184	#define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
Kojto	122:f9eeca106725	1185	#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
Kojto	122:f9eeca106725	1186	#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
Kojto	122:f9eeca106725	1187	#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
Kojto	122:f9eeca106725	1188	#define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
Kojto	122:f9eeca106725	1189	#define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
Kojto	122:f9eeca106725	1190	#define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
Kojto	122:f9eeca106725	1191	#define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
Kojto	122:f9eeca106725	1192	#define UART7_BASE (APB1PERIPH_BASE + 0x7800U)
Kojto	122:f9eeca106725	1193	#define UART8_BASE (APB1PERIPH_BASE + 0x7C00U)
Kojto	110:165afa46840b	1194
Kojto	110:165afa46840b	1195	/!< APB2 peripherals /
Kojto	122:f9eeca106725	1196	#define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
Kojto	122:f9eeca106725	1197	#define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
Kojto	122:f9eeca106725	1198	#define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
Kojto	122:f9eeca106725	1199	#define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
Kojto	122:f9eeca106725	1200	#define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
Kojto	122:f9eeca106725	1201	#define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
Kojto	122:f9eeca106725	1202	#define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
Kojto	122:f9eeca106725	1203	#define ADC_BASE (APB2PERIPH_BASE + 0x2300U)
Kojto	122:f9eeca106725	1204	#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
Kojto	122:f9eeca106725	1205	#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
Kojto	122:f9eeca106725	1206	#define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
Kojto	122:f9eeca106725	1207	#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
Kojto	122:f9eeca106725	1208	#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
Kojto	122:f9eeca106725	1209	#define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
Kojto	122:f9eeca106725	1210	#define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
Kojto	122:f9eeca106725	1211	#define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
Kojto	122:f9eeca106725	1212	#define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
Kojto	122:f9eeca106725	1213	#define SPI6_BASE (APB2PERIPH_BASE + 0x5400U)
Kojto	122:f9eeca106725	1214	#define SAI1_BASE (APB2PERIPH_BASE + 0x5800U)
Kojto	122:f9eeca106725	1215	#define SAI1_Block_A_BASE (SAI1_BASE + 0x004U)
Kojto	122:f9eeca106725	1216	#define SAI1_Block_B_BASE (SAI1_BASE + 0x024U)
Kojto	122:f9eeca106725	1217	#define LTDC_BASE (APB2PERIPH_BASE + 0x6800U)
Kojto	122:f9eeca106725	1218	#define LTDC_Layer1_BASE (LTDC_BASE + 0x84U)
Kojto	122:f9eeca106725	1219	#define LTDC_Layer2_BASE (LTDC_BASE + 0x104U)
Kojto	122:f9eeca106725	1220	#define DSI_BASE (APB2PERIPH_BASE + 0x6C00U)
Kojto	110:165afa46840b	1221
Kojto	110:165afa46840b	1222	/!< AHB1 peripherals /
Kojto	122:f9eeca106725	1223	#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
Kojto	122:f9eeca106725	1224	#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
Kojto	122:f9eeca106725	1225	#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
Kojto	122:f9eeca106725	1226	#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
Kojto	122:f9eeca106725	1227	#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
Kojto	122:f9eeca106725	1228	#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
Kojto	122:f9eeca106725	1229	#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
Kojto	122:f9eeca106725	1230	#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
Kojto	122:f9eeca106725	1231	#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U)
Kojto	122:f9eeca106725	1232	#define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400U)
Kojto	122:f9eeca106725	1233	#define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800U)
Kojto	122:f9eeca106725	1234	#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
Kojto	122:f9eeca106725	1235	#define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
Kojto	122:f9eeca106725	1236	#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
Kojto	122:f9eeca106725	1237	#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
Kojto	122:f9eeca106725	1238	#define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
Kojto	122:f9eeca106725	1239	#define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
Kojto	122:f9eeca106725	1240	#define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
Kojto	122:f9eeca106725	1241	#define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
Kojto	122:f9eeca106725	1242	#define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
Kojto	122:f9eeca106725	1243	#define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
Kojto	122:f9eeca106725	1244	#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
Kojto	122:f9eeca106725	1245	#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
Kojto	122:f9eeca106725	1246	#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
Kojto	122:f9eeca106725	1247	#define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
Kojto	122:f9eeca106725	1248	#define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
Kojto	122:f9eeca106725	1249	#define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
Kojto	122:f9eeca106725	1250	#define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
Kojto	122:f9eeca106725	1251	#define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
Kojto	122:f9eeca106725	1252	#define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
Kojto	122:f9eeca106725	1253	#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
Kojto	122:f9eeca106725	1254	#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
Kojto	122:f9eeca106725	1255	#define ETH_BASE (AHB1PERIPH_BASE + 0x8000U)
Kojto	110:165afa46840b	1256	#define ETH_MAC_BASE (ETH_BASE)
Kojto	122:f9eeca106725	1257	#define ETH_MMC_BASE (ETH_BASE + 0x0100U)
Kojto	122:f9eeca106725	1258	#define ETH_PTP_BASE (ETH_BASE + 0x0700U)
Kojto	122:f9eeca106725	1259	#define ETH_DMA_BASE (ETH_BASE + 0x1000U)
Kojto	122:f9eeca106725	1260	#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000U)
Kojto	110:165afa46840b	1261
Kojto	110:165afa46840b	1262	/!< AHB2 peripherals /
Kojto	122:f9eeca106725	1263	#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U)
Kojto	122:f9eeca106725	1264	#define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
Kojto	110:165afa46840b	1265
Kojto	110:165afa46840b	1266	/!< FMC Bankx registers base address /
Kojto	122:f9eeca106725	1267	#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U)
Kojto	122:f9eeca106725	1268	#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U)
Kojto	122:f9eeca106725	1269	#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U)
Kojto	122:f9eeca106725	1270	#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140U)
Kojto	110:165afa46840b	1271
Kojto	110:165afa46840b	1272	/!< Debug MCU registers base address /
Kojto	122:f9eeca106725	1273	#define DBGMCU_BASE 0xE0042000U
Kojto	110:165afa46840b	1274
Kojto	110:165afa46840b	1275	/!< USB registers base address /
Kojto	122:f9eeca106725	1276	#define USB_OTG_HS_PERIPH_BASE 0x40040000U
Kojto	122:f9eeca106725	1277	#define USB_OTG_FS_PERIPH_BASE 0x50000000U
Kojto	122:f9eeca106725	1278
Kojto	122:f9eeca106725	1279	#define USB_OTG_GLOBAL_BASE 0x000U
Kojto	122:f9eeca106725	1280	#define USB_OTG_DEVICE_BASE 0x800U
Kojto	122:f9eeca106725	1281	#define USB_OTG_IN_ENDPOINT_BASE 0x900U
Kojto	122:f9eeca106725	1282	#define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
Kojto	122:f9eeca106725	1283	#define USB_OTG_EP_REG_SIZE 0x20U
Kojto	122:f9eeca106725	1284	#define USB_OTG_HOST_BASE 0x400U
Kojto	122:f9eeca106725	1285	#define USB_OTG_HOST_PORT_BASE 0x440U
Kojto	122:f9eeca106725	1286	#define USB_OTG_HOST_CHANNEL_BASE 0x500U
Kojto	122:f9eeca106725	1287	#define USB_OTG_HOST_CHANNEL_SIZE 0x20U
Kojto	122:f9eeca106725	1288	#define USB_OTG_PCGCCTL_BASE 0xE00U
Kojto	122:f9eeca106725	1289	#define USB_OTG_FIFO_BASE 0x1000U
Kojto	122:f9eeca106725	1290	#define USB_OTG_FIFO_SIZE 0x1000U
Kojto	110:165afa46840b	1291
Kojto	110:165afa46840b	1292	/**
Kojto	110:165afa46840b	1293	* @}
Kojto	110:165afa46840b	1294	*/
Kojto	110:165afa46840b	1295
Kojto	110:165afa46840b	1296	/** @addtogroup Peripheral_declaration
Kojto	110:165afa46840b	1297	* @{
Kojto	110:165afa46840b	1298	*/
Kojto	110:165afa46840b	1299	#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
Kojto	110:165afa46840b	1300	#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
Kojto	110:165afa46840b	1301	#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
Kojto	110:165afa46840b	1302	#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
Kojto	110:165afa46840b	1303	#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
Kojto	110:165afa46840b	1304	#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
Kojto	110:165afa46840b	1305	#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
Kojto	110:165afa46840b	1306	#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
Kojto	110:165afa46840b	1307	#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
Kojto	110:165afa46840b	1308	#define RTC ((RTC_TypeDef *) RTC_BASE)
Kojto	110:165afa46840b	1309	#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
Kojto	110:165afa46840b	1310	#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
Kojto	110:165afa46840b	1311	#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
Kojto	110:165afa46840b	1312	#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
Kojto	110:165afa46840b	1313	#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
Kojto	110:165afa46840b	1314	#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
Kojto	110:165afa46840b	1315	#define USART2 ((USART_TypeDef *) USART2_BASE)
Kojto	110:165afa46840b	1316	#define USART3 ((USART_TypeDef *) USART3_BASE)
Kojto	110:165afa46840b	1317	#define UART4 ((USART_TypeDef *) UART4_BASE)
Kojto	110:165afa46840b	1318	#define UART5 ((USART_TypeDef *) UART5_BASE)
Kojto	110:165afa46840b	1319	#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
Kojto	110:165afa46840b	1320	#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
Kojto	110:165afa46840b	1321	#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
Kojto	110:165afa46840b	1322	#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
Kojto	110:165afa46840b	1323	#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
Kojto	110:165afa46840b	1324	#define PWR ((PWR_TypeDef *) PWR_BASE)
Kojto	110:165afa46840b	1325	#define DAC ((DAC_TypeDef *) DAC_BASE)
Kojto	110:165afa46840b	1326	#define UART7 ((USART_TypeDef *) UART7_BASE)
Kojto	110:165afa46840b	1327	#define UART8 ((USART_TypeDef *) UART8_BASE)
Kojto	110:165afa46840b	1328	#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
Kojto	110:165afa46840b	1329	#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
Kojto	110:165afa46840b	1330	#define USART1 ((USART_TypeDef *) USART1_BASE)
Kojto	110:165afa46840b	1331	#define USART6 ((USART_TypeDef *) USART6_BASE)
Kojto	110:165afa46840b	1332	#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
Kojto	110:165afa46840b	1333	#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
Kojto	110:165afa46840b	1334	#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
Kojto	110:165afa46840b	1335	#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
Kojto	110:165afa46840b	1336	#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
Kojto	110:165afa46840b	1337	#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
Kojto	110:165afa46840b	1338	#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
Kojto	110:165afa46840b	1339	#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
Kojto	110:165afa46840b	1340	#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
Kojto	110:165afa46840b	1341	#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
Kojto	110:165afa46840b	1342	#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
Kojto	110:165afa46840b	1343	#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
Kojto	110:165afa46840b	1344	#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
Kojto	110:165afa46840b	1345	#define SPI6 ((SPI_TypeDef *) SPI6_BASE)
Kojto	110:165afa46840b	1346	#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
Kojto	110:165afa46840b	1347	#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
Kojto	110:165afa46840b	1348	#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
Kojto	110:165afa46840b	1349	#define LTDC ((LTDC_TypeDef *)LTDC_BASE)
Kojto	110:165afa46840b	1350	#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
Kojto	110:165afa46840b	1351	#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
Kojto	110:165afa46840b	1352	#define DSI ((DSI_TypeDef *)DSI_BASE)
Kojto	110:165afa46840b	1353
Kojto	110:165afa46840b	1354	#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
Kojto	110:165afa46840b	1355	#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
Kojto	110:165afa46840b	1356	#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
Kojto	110:165afa46840b	1357	#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
Kojto	110:165afa46840b	1358	#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
Kojto	110:165afa46840b	1359	#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
Kojto	110:165afa46840b	1360	#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
Kojto	110:165afa46840b	1361	#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
Kojto	110:165afa46840b	1362	#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
Kojto	110:165afa46840b	1363	#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
Kojto	110:165afa46840b	1364	#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
Kojto	110:165afa46840b	1365	#define CRC ((CRC_TypeDef *) CRC_BASE)
Kojto	110:165afa46840b	1366	#define RCC ((RCC_TypeDef *) RCC_BASE)
Kojto	110:165afa46840b	1367	#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
Kojto	110:165afa46840b	1368	#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
Kojto	110:165afa46840b	1369	#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
Kojto	110:165afa46840b	1370	#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
Kojto	110:165afa46840b	1371	#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
Kojto	110:165afa46840b	1372	#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
Kojto	110:165afa46840b	1373	#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
Kojto	110:165afa46840b	1374	#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
Kojto	110:165afa46840b	1375	#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
Kojto	110:165afa46840b	1376	#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
Kojto	110:165afa46840b	1377	#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
Kojto	110:165afa46840b	1378	#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
Kojto	110:165afa46840b	1379	#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
Kojto	110:165afa46840b	1380	#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
Kojto	110:165afa46840b	1381	#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
Kojto	110:165afa46840b	1382	#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
Kojto	110:165afa46840b	1383	#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
Kojto	110:165afa46840b	1384	#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
Kojto	110:165afa46840b	1385	#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
Kojto	110:165afa46840b	1386	#define ETH ((ETH_TypeDef *) ETH_BASE)
Kojto	110:165afa46840b	1387	#define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
Kojto	110:165afa46840b	1388	#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
Kojto	110:165afa46840b	1389	#define RNG ((RNG_TypeDef *) RNG_BASE)
Kojto	110:165afa46840b	1390	#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
Kojto	110:165afa46840b	1391	#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
Kojto	110:165afa46840b	1392	#define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
Kojto	110:165afa46840b	1393	#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
Kojto	110:165afa46840b	1394	#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
Kojto	110:165afa46840b	1395
Kojto	110:165afa46840b	1396	#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
Kojto	110:165afa46840b	1397
Kojto	110:165afa46840b	1398	#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
Kojto	110:165afa46840b	1399	#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
Kojto	110:165afa46840b	1400
Kojto	110:165afa46840b	1401	/**
Kojto	110:165afa46840b	1402	* @}
Kojto	110:165afa46840b	1403	*/
Kojto	110:165afa46840b	1404
Kojto	110:165afa46840b	1405	/** @addtogroup Exported_constants
Kojto	110:165afa46840b	1406	* @{
Kojto	110:165afa46840b	1407	*/
Kojto	110:165afa46840b	1408
Kojto	110:165afa46840b	1409	/** @addtogroup Peripheral_Registers_Bits_Definition
Kojto	110:165afa46840b	1410	* @{
Kojto	110:165afa46840b	1411	*/
Kojto	110:165afa46840b	1412
Kojto	110:165afa46840b	1413	/******************************************************************************/
Kojto	110:165afa46840b	1414	/* Peripheral Registers_Bits_Definition */
Kojto	110:165afa46840b	1415	/******************************************************************************/
Kojto	110:165afa46840b	1416
Kojto	110:165afa46840b	1417	/******************************************************************************/
Kojto	110:165afa46840b	1418	/* */
Kojto	110:165afa46840b	1419	/* Analog to Digital Converter */
Kojto	110:165afa46840b	1420	/* */
Kojto	110:165afa46840b	1421	/******************************************************************************/
Kojto	110:165afa46840b	1422	/****************** Bit definition for ADC_SR register ******************/
Kojto	122:f9eeca106725	1423	#define ADC_SR_AWD 0x00000001U /!<Analog watchdog flag /
Kojto	122:f9eeca106725	1424	#define ADC_SR_EOC 0x00000002U /!<End of conversion /
Kojto	122:f9eeca106725	1425	#define ADC_SR_JEOC 0x00000004U /!<Injected channel end of conversion /
Kojto	122:f9eeca106725	1426	#define ADC_SR_JSTRT 0x00000008U /!<Injected channel Start flag /
Kojto	122:f9eeca106725	1427	#define ADC_SR_STRT 0x00000010U /!<Regular channel Start flag /
Kojto	122:f9eeca106725	1428	#define ADC_SR_OVR 0x00000020U /!<Overrun flag /
Kojto	110:165afa46840b	1429
Kojto	110:165afa46840b	1430	/***************** Bit definition for ADC_CR1 register ******************/
Kojto	122:f9eeca106725	1431	#define ADC_CR1_AWDCH 0x0000001FU /!<AWDCH[4:0] bits (Analog watchdog channel select bits) /
Kojto	122:f9eeca106725	1432	#define ADC_CR1_AWDCH_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	1433	#define ADC_CR1_AWDCH_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	1434	#define ADC_CR1_AWDCH_2 0x00000004U /!<Bit 2 /
Kojto	122:f9eeca106725	1435	#define ADC_CR1_AWDCH_3 0x00000008U /!<Bit 3 /
Kojto	122:f9eeca106725	1436	#define ADC_CR1_AWDCH_4 0x00000010U /!<Bit 4 /
Kojto	122:f9eeca106725	1437	#define ADC_CR1_EOCIE 0x00000020U /!<Interrupt enable for EOC /
Kojto	122:f9eeca106725	1438	#define ADC_CR1_AWDIE 0x00000040U /!<AAnalog Watchdog interrupt enable /
Kojto	122:f9eeca106725	1439	#define ADC_CR1_JEOCIE 0x00000080U /!<Interrupt enable for injected channels /
Kojto	122:f9eeca106725	1440	#define ADC_CR1_SCAN 0x00000100U /!<Scan mode /
Kojto	122:f9eeca106725	1441	#define ADC_CR1_AWDSGL 0x00000200U /!<Enable the watchdog on a single channel in scan mode /
Kojto	122:f9eeca106725	1442	#define ADC_CR1_JAUTO 0x00000400U /!<Automatic injected group conversion /
Kojto	122:f9eeca106725	1443	#define ADC_CR1_DISCEN 0x00000800U /!<Discontinuous mode on regular channels /
Kojto	122:f9eeca106725	1444	#define ADC_CR1_JDISCEN 0x00001000U /!<Discontinuous mode on injected channels /
Kojto	122:f9eeca106725	1445	#define ADC_CR1_DISCNUM 0x0000E000U /!<DISCNUM[2:0] bits (Discontinuous mode channel count) /
Kojto	122:f9eeca106725	1446	#define ADC_CR1_DISCNUM_0 0x00002000U /!<Bit 0 /
Kojto	122:f9eeca106725	1447	#define ADC_CR1_DISCNUM_1 0x00004000U /!<Bit 1 /
Kojto	122:f9eeca106725	1448	#define ADC_CR1_DISCNUM_2 0x00008000U /!<Bit 2 /
Kojto	122:f9eeca106725	1449	#define ADC_CR1_JAWDEN 0x00400000U /!<Analog watchdog enable on injected channels /
Kojto	122:f9eeca106725	1450	#define ADC_CR1_AWDEN 0x00800000U /!<Analog watchdog enable on regular channels /
Kojto	122:f9eeca106725	1451	#define ADC_CR1_RES 0x03000000U /!<RES[2:0] bits (Resolution) /
Kojto	122:f9eeca106725	1452	#define ADC_CR1_RES_0 0x01000000U /!<Bit 0 /
Kojto	122:f9eeca106725	1453	#define ADC_CR1_RES_1 0x02000000U /!<Bit 1 /
Kojto	122:f9eeca106725	1454	#define ADC_CR1_OVRIE 0x04000000U /!<overrun interrupt enable /
Kojto	110:165afa46840b	1455
Kojto	110:165afa46840b	1456	/***************** Bit definition for ADC_CR2 register ******************/
Kojto	122:f9eeca106725	1457	#define ADC_CR2_ADON 0x00000001U /!<A/D Converter ON / OFF /
Kojto	122:f9eeca106725	1458	#define ADC_CR2_CONT 0x00000002U /!<Continuous Conversion /
Kojto	122:f9eeca106725	1459	#define ADC_CR2_DMA 0x00000100U /!<Direct Memory access mode /
Kojto	122:f9eeca106725	1460	#define ADC_CR2_DDS 0x00000200U /!<DMA disable selection (Single ADC) /
Kojto	122:f9eeca106725	1461	#define ADC_CR2_EOCS 0x00000400U /!<End of conversion selection /
Kojto	122:f9eeca106725	1462	#define ADC_CR2_ALIGN 0x00000800U /!<Data Alignment /
Kojto	122:f9eeca106725	1463	#define ADC_CR2_JEXTSEL 0x000F0000U /!<JEXTSEL[3:0] bits (External event select for injected group) /
Kojto	122:f9eeca106725	1464	#define ADC_CR2_JEXTSEL_0 0x00010000U /!<Bit 0 /
Kojto	122:f9eeca106725	1465	#define ADC_CR2_JEXTSEL_1 0x00020000U /!<Bit 1 /
Kojto	122:f9eeca106725	1466	#define ADC_CR2_JEXTSEL_2 0x00040000U /!<Bit 2 /
Kojto	122:f9eeca106725	1467	#define ADC_CR2_JEXTSEL_3 0x00080000U /!<Bit 3 /
Kojto	122:f9eeca106725	1468	#define ADC_CR2_JEXTEN 0x00300000U /!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) /
Kojto	122:f9eeca106725	1469	#define ADC_CR2_JEXTEN_0 0x00100000U /!<Bit 0 /
Kojto	122:f9eeca106725	1470	#define ADC_CR2_JEXTEN_1 0x00200000U /!<Bit 1 /
Kojto	122:f9eeca106725	1471	#define ADC_CR2_JSWSTART 0x00400000U /!<Start Conversion of injected channels /
Kojto	122:f9eeca106725	1472	#define ADC_CR2_EXTSEL 0x0F000000U /!<EXTSEL[3:0] bits (External Event Select for regular group) /
Kojto	122:f9eeca106725	1473	#define ADC_CR2_EXTSEL_0 0x01000000U /!<Bit 0 /
Kojto	122:f9eeca106725	1474	#define ADC_CR2_EXTSEL_1 0x02000000U /!<Bit 1 /
Kojto	122:f9eeca106725	1475	#define ADC_CR2_EXTSEL_2 0x04000000U /!<Bit 2 /
Kojto	122:f9eeca106725	1476	#define ADC_CR2_EXTSEL_3 0x08000000U /!<Bit 3 /
Kojto	122:f9eeca106725	1477	#define ADC_CR2_EXTEN 0x30000000U /!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) /
Kojto	122:f9eeca106725	1478	#define ADC_CR2_EXTEN_0 0x10000000U /!<Bit 0 /
Kojto	122:f9eeca106725	1479	#define ADC_CR2_EXTEN_1 0x20000000U /!<Bit 1 /
Kojto	122:f9eeca106725	1480	#define ADC_CR2_SWSTART 0x40000000U /!<Start Conversion of regular channels /
Kojto	110:165afa46840b	1481
Kojto	110:165afa46840b	1482	/**************** Bit definition for ADC_SMPR1 register *****************/
Kojto	122:f9eeca106725	1483	#define ADC_SMPR1_SMP10 0x00000007U /!<SMP10[2:0] bits (Channel 10 Sample time selection) /
Kojto	122:f9eeca106725	1484	#define ADC_SMPR1_SMP10_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	1485	#define ADC_SMPR1_SMP10_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	1486	#define ADC_SMPR1_SMP10_2 0x00000004U /!<Bit 2 /
Kojto	122:f9eeca106725	1487	#define ADC_SMPR1_SMP11 0x00000038U /!<SMP11[2:0] bits (Channel 11 Sample time selection) /
Kojto	122:f9eeca106725	1488	#define ADC_SMPR1_SMP11_0 0x00000008U /!<Bit 0 /
Kojto	122:f9eeca106725	1489	#define ADC_SMPR1_SMP11_1 0x00000010U /!<Bit 1 /
Kojto	122:f9eeca106725	1490	#define ADC_SMPR1_SMP11_2 0x00000020U /!<Bit 2 /
Kojto	122:f9eeca106725	1491	#define ADC_SMPR1_SMP12 0x000001C0U /!<SMP12[2:0] bits (Channel 12 Sample time selection) /
Kojto	122:f9eeca106725	1492	#define ADC_SMPR1_SMP12_0 0x00000040U /!<Bit 0 /
Kojto	122:f9eeca106725	1493	#define ADC_SMPR1_SMP12_1 0x00000080U /!<Bit 1 /
Kojto	122:f9eeca106725	1494	#define ADC_SMPR1_SMP12_2 0x00000100U /!<Bit 2 /
Kojto	122:f9eeca106725	1495	#define ADC_SMPR1_SMP13 0x00000E00U /!<SMP13[2:0] bits (Channel 13 Sample time selection) /
Kojto	122:f9eeca106725	1496	#define ADC_SMPR1_SMP13_0 0x00000200U /!<Bit 0 /
Kojto	122:f9eeca106725	1497	#define ADC_SMPR1_SMP13_1 0x00000400U /!<Bit 1 /
Kojto	122:f9eeca106725	1498	#define ADC_SMPR1_SMP13_2 0x00000800U /!<Bit 2 /
Kojto	122:f9eeca106725	1499	#define ADC_SMPR1_SMP14 0x00007000U /!<SMP14[2:0] bits (Channel 14 Sample time selection) /
Kojto	122:f9eeca106725	1500	#define ADC_SMPR1_SMP14_0 0x00001000U /!<Bit 0 /
Kojto	122:f9eeca106725	1501	#define ADC_SMPR1_SMP14_1 0x00002000U /!<Bit 1 /
Kojto	122:f9eeca106725	1502	#define ADC_SMPR1_SMP14_2 0x00004000U /!<Bit 2 /
Kojto	122:f9eeca106725	1503	#define ADC_SMPR1_SMP15 0x00038000U /!<SMP15[2:0] bits (Channel 15 Sample time selection) /
Kojto	122:f9eeca106725	1504	#define ADC_SMPR1_SMP15_0 0x00008000U /!<Bit 0 /
Kojto	122:f9eeca106725	1505	#define ADC_SMPR1_SMP15_1 0x00010000U /!<Bit 1 /
Kojto	122:f9eeca106725	1506	#define ADC_SMPR1_SMP15_2 0x00020000U /!<Bit 2 /
Kojto	122:f9eeca106725	1507	#define ADC_SMPR1_SMP16 0x001C0000U /!<SMP16[2:0] bits (Channel 16 Sample time selection) /
Kojto	122:f9eeca106725	1508	#define ADC_SMPR1_SMP16_0 0x00040000U /!<Bit 0 /
Kojto	122:f9eeca106725	1509	#define ADC_SMPR1_SMP16_1 0x00080000U /!<Bit 1 /
Kojto	122:f9eeca106725	1510	#define ADC_SMPR1_SMP16_2 0x00100000U /!<Bit 2 /
Kojto	122:f9eeca106725	1511	#define ADC_SMPR1_SMP17 0x00E00000U /!<SMP17[2:0] bits (Channel 17 Sample time selection) /
Kojto	122:f9eeca106725	1512	#define ADC_SMPR1_SMP17_0 0x00200000U /!<Bit 0 /
Kojto	122:f9eeca106725	1513	#define ADC_SMPR1_SMP17_1 0x00400000U /!<Bit 1 /
Kojto	122:f9eeca106725	1514	#define ADC_SMPR1_SMP17_2 0x00800000U /!<Bit 2 /
Kojto	122:f9eeca106725	1515	#define ADC_SMPR1_SMP18 0x07000000U /!<SMP18[2:0] bits (Channel 18 Sample time selection) /
Kojto	122:f9eeca106725	1516	#define ADC_SMPR1_SMP18_0 0x01000000U /!<Bit 0 /
Kojto	122:f9eeca106725	1517	#define ADC_SMPR1_SMP18_1 0x02000000U /!<Bit 1 /
Kojto	122:f9eeca106725	1518	#define ADC_SMPR1_SMP18_2 0x04000000U /!<Bit 2 /
Kojto	110:165afa46840b	1519
Kojto	110:165afa46840b	1520	/**************** Bit definition for ADC_SMPR2 register *****************/
Kojto	122:f9eeca106725	1521	#define ADC_SMPR2_SMP0 0x00000007U /!<SMP0[2:0] bits (Channel 0 Sample time selection) /
Kojto	122:f9eeca106725	1522	#define ADC_SMPR2_SMP0_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	1523	#define ADC_SMPR2_SMP0_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	1524	#define ADC_SMPR2_SMP0_2 0x00000004U /!<Bit 2 /
Kojto	122:f9eeca106725	1525	#define ADC_SMPR2_SMP1 0x00000038U /!<SMP1[2:0] bits (Channel 1 Sample time selection) /
Kojto	122:f9eeca106725	1526	#define ADC_SMPR2_SMP1_0 0x00000008U /!<Bit 0 /
Kojto	122:f9eeca106725	1527	#define ADC_SMPR2_SMP1_1 0x00000010U /!<Bit 1 /
Kojto	122:f9eeca106725	1528	#define ADC_SMPR2_SMP1_2 0x00000020U /!<Bit 2 /
Kojto	122:f9eeca106725	1529	#define ADC_SMPR2_SMP2 0x000001C0U /!<SMP2[2:0] bits (Channel 2 Sample time selection) /
Kojto	122:f9eeca106725	1530	#define ADC_SMPR2_SMP2_0 0x00000040U /!<Bit 0 /
Kojto	122:f9eeca106725	1531	#define ADC_SMPR2_SMP2_1 0x00000080U /!<Bit 1 /
Kojto	122:f9eeca106725	1532	#define ADC_SMPR2_SMP2_2 0x00000100U /!<Bit 2 /
Kojto	122:f9eeca106725	1533	#define ADC_SMPR2_SMP3 0x00000E00U /!<SMP3[2:0] bits (Channel 3 Sample time selection) /
Kojto	122:f9eeca106725	1534	#define ADC_SMPR2_SMP3_0 0x00000200U /!<Bit 0 /
Kojto	122:f9eeca106725	1535	#define ADC_SMPR2_SMP3_1 0x00000400U /!<Bit 1 /
Kojto	122:f9eeca106725	1536	#define ADC_SMPR2_SMP3_2 0x00000800U /!<Bit 2 /
Kojto	122:f9eeca106725	1537	#define ADC_SMPR2_SMP4 0x00007000U /!<SMP4[2:0] bits (Channel 4 Sample time selection) /
Kojto	122:f9eeca106725	1538	#define ADC_SMPR2_SMP4_0 0x00001000U /!<Bit 0 /
Kojto	122:f9eeca106725	1539	#define ADC_SMPR2_SMP4_1 0x00002000U /!<Bit 1 /
Kojto	122:f9eeca106725	1540	#define ADC_SMPR2_SMP4_2 0x00004000U /!<Bit 2 /
Kojto	122:f9eeca106725	1541	#define ADC_SMPR2_SMP5 0x00038000U /!<SMP5[2:0] bits (Channel 5 Sample time selection) /
Kojto	122:f9eeca106725	1542	#define ADC_SMPR2_SMP5_0 0x00008000U /!<Bit 0 /
Kojto	122:f9eeca106725	1543	#define ADC_SMPR2_SMP5_1 0x00010000U /!<Bit 1 /
Kojto	122:f9eeca106725	1544	#define ADC_SMPR2_SMP5_2 0x00020000U /!<Bit 2 /
Kojto	122:f9eeca106725	1545	#define ADC_SMPR2_SMP6 0x001C0000U /!<SMP6[2:0] bits (Channel 6 Sample time selection) /
Kojto	122:f9eeca106725	1546	#define ADC_SMPR2_SMP6_0 0x00040000U /!<Bit 0 /
Kojto	122:f9eeca106725	1547	#define ADC_SMPR2_SMP6_1 0x00080000U /!<Bit 1 /
Kojto	122:f9eeca106725	1548	#define ADC_SMPR2_SMP6_2 0x00100000U /!<Bit 2 /
Kojto	122:f9eeca106725	1549	#define ADC_SMPR2_SMP7 0x00E00000U /!<SMP7[2:0] bits (Channel 7 Sample time selection) /
Kojto	122:f9eeca106725	1550	#define ADC_SMPR2_SMP7_0 0x00200000U /!<Bit 0 /
Kojto	122:f9eeca106725	1551	#define ADC_SMPR2_SMP7_1 0x00400000U /!<Bit 1 /
Kojto	122:f9eeca106725	1552	#define ADC_SMPR2_SMP7_2 0x00800000U /!<Bit 2 /
Kojto	122:f9eeca106725	1553	#define ADC_SMPR2_SMP8 0x07000000U /!<SMP8[2:0] bits (Channel 8 Sample time selection) /
Kojto	122:f9eeca106725	1554	#define ADC_SMPR2_SMP8_0 0x01000000U /!<Bit 0 /
Kojto	122:f9eeca106725	1555	#define ADC_SMPR2_SMP8_1 0x02000000U /!<Bit 1 /
Kojto	122:f9eeca106725	1556	#define ADC_SMPR2_SMP8_2 0x04000000U /!<Bit 2 /
Kojto	122:f9eeca106725	1557	#define ADC_SMPR2_SMP9 0x38000000U /!<SMP9[2:0] bits (Channel 9 Sample time selection) /
Kojto	122:f9eeca106725	1558	#define ADC_SMPR2_SMP9_0 0x08000000U /!<Bit 0 /
Kojto	122:f9eeca106725	1559	#define ADC_SMPR2_SMP9_1 0x10000000U /!<Bit 1 /
Kojto	122:f9eeca106725	1560	#define ADC_SMPR2_SMP9_2 0x20000000U /!<Bit 2 /
Kojto	110:165afa46840b	1561
Kojto	110:165afa46840b	1562	/**************** Bit definition for ADC_JOFR1 register *****************/
Kojto	122:f9eeca106725	1563	#define ADC_JOFR1_JOFFSET1 0x0FFFU /!<Data offset for injected channel 1 /
Kojto	110:165afa46840b	1564
Kojto	110:165afa46840b	1565	/**************** Bit definition for ADC_JOFR2 register *****************/
Kojto	122:f9eeca106725	1566	#define ADC_JOFR2_JOFFSET2 0x0FFFU /!<Data offset for injected channel 2 /
Kojto	110:165afa46840b	1567
Kojto	110:165afa46840b	1568	/**************** Bit definition for ADC_JOFR3 register *****************/
Kojto	122:f9eeca106725	1569	#define ADC_JOFR3_JOFFSET3 0x0FFFU /!<Data offset for injected channel 3 /
Kojto	110:165afa46840b	1570
Kojto	110:165afa46840b	1571	/**************** Bit definition for ADC_JOFR4 register *****************/
Kojto	122:f9eeca106725	1572	#define ADC_JOFR4_JOFFSET4 0x0FFFU /!<Data offset for injected channel 4 /
Kojto	110:165afa46840b	1573
Kojto	110:165afa46840b	1574	/***************** Bit definition for ADC_HTR register ******************/
Kojto	122:f9eeca106725	1575	#define ADC_HTR_HT 0x0FFFU /!<Analog watchdog high threshold /
Kojto	110:165afa46840b	1576
Kojto	110:165afa46840b	1577	/***************** Bit definition for ADC_LTR register ******************/
Kojto	122:f9eeca106725	1578	#define ADC_LTR_LT 0x0FFFU /!<Analog watchdog low threshold /
Kojto	110:165afa46840b	1579
Kojto	110:165afa46840b	1580	/***************** Bit definition for ADC_SQR1 register *****************/
Kojto	122:f9eeca106725	1581	#define ADC_SQR1_SQ13 0x0000001FU /!<SQ13[4:0] bits (13th conversion in regular sequence) /
Kojto	122:f9eeca106725	1582	#define ADC_SQR1_SQ13_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	1583	#define ADC_SQR1_SQ13_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	1584	#define ADC_SQR1_SQ13_2 0x00000004U /!<Bit 2 /
Kojto	122:f9eeca106725	1585	#define ADC_SQR1_SQ13_3 0x00000008U /!<Bit 3 /
Kojto	122:f9eeca106725	1586	#define ADC_SQR1_SQ13_4 0x00000010U /!<Bit 4 /
Kojto	122:f9eeca106725	1587	#define ADC_SQR1_SQ14 0x000003E0U /!<SQ14[4:0] bits (14th conversion in regular sequence) /
Kojto	122:f9eeca106725	1588	#define ADC_SQR1_SQ14_0 0x00000020U /!<Bit 0 /
Kojto	122:f9eeca106725	1589	#define ADC_SQR1_SQ14_1 0x00000040U /!<Bit 1 /
Kojto	122:f9eeca106725	1590	#define ADC_SQR1_SQ14_2 0x00000080U /!<Bit 2 /
Kojto	122:f9eeca106725	1591	#define ADC_SQR1_SQ14_3 0x00000100U /!<Bit 3 /
Kojto	122:f9eeca106725	1592	#define ADC_SQR1_SQ14_4 0x00000200U /!<Bit 4 /
Kojto	122:f9eeca106725	1593	#define ADC_SQR1_SQ15 0x00007C00U /!<SQ15[4:0] bits (15th conversion in regular sequence) /
Kojto	122:f9eeca106725	1594	#define ADC_SQR1_SQ15_0 0x00000400U /!<Bit 0 /
Kojto	122:f9eeca106725	1595	#define ADC_SQR1_SQ15_1 0x00000800U /!<Bit 1 /
Kojto	122:f9eeca106725	1596	#define ADC_SQR1_SQ15_2 0x00001000U /!<Bit 2 /
Kojto	122:f9eeca106725	1597	#define ADC_SQR1_SQ15_3 0x00002000U /!<Bit 3 /
Kojto	122:f9eeca106725	1598	#define ADC_SQR1_SQ15_4 0x00004000U /!<Bit 4 /
Kojto	122:f9eeca106725	1599	#define ADC_SQR1_SQ16 0x000F8000U /!<SQ16[4:0] bits (16th conversion in regular sequence) /
Kojto	122:f9eeca106725	1600	#define ADC_SQR1_SQ16_0 0x00008000U /!<Bit 0 /
Kojto	122:f9eeca106725	1601	#define ADC_SQR1_SQ16_1 0x00010000U /!<Bit 1 /
Kojto	122:f9eeca106725	1602	#define ADC_SQR1_SQ16_2 0x00020000U /!<Bit 2 /
Kojto	122:f9eeca106725	1603	#define ADC_SQR1_SQ16_3 0x00040000U /!<Bit 3 /
Kojto	122:f9eeca106725	1604	#define ADC_SQR1_SQ16_4 0x00080000U /!<Bit 4 /
Kojto	122:f9eeca106725	1605	#define ADC_SQR1_L 0x00F00000U /!<L[3:0] bits (Regular channel sequence length) /
Kojto	122:f9eeca106725	1606	#define ADC_SQR1_L_0 0x00100000U /!<Bit 0 /
Kojto	122:f9eeca106725	1607	#define ADC_SQR1_L_1 0x00200000U /!<Bit 1 /
Kojto	122:f9eeca106725	1608	#define ADC_SQR1_L_2 0x00400000U /!<Bit 2 /
Kojto	122:f9eeca106725	1609	#define ADC_SQR1_L_3 0x00800000U /!<Bit 3 /
Kojto	110:165afa46840b	1610
Kojto	110:165afa46840b	1611	/***************** Bit definition for ADC_SQR2 register *****************/
Kojto	122:f9eeca106725	1612	#define ADC_SQR2_SQ7 0x0000001FU /!<SQ7[4:0] bits (7th conversion in regular sequence) /
Kojto	122:f9eeca106725	1613	#define ADC_SQR2_SQ7_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	1614	#define ADC_SQR2_SQ7_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	1615	#define ADC_SQR2_SQ7_2 0x00000004U /!<Bit 2 /
Kojto	122:f9eeca106725	1616	#define ADC_SQR2_SQ7_3 0x00000008U /!<Bit 3 /
Kojto	122:f9eeca106725	1617	#define ADC_SQR2_SQ7_4 0x00000010U /!<Bit 4 /
Kojto	122:f9eeca106725	1618	#define ADC_SQR2_SQ8 0x000003E0U /!<SQ8[4:0] bits (8th conversion in regular sequence) /
Kojto	122:f9eeca106725	1619	#define ADC_SQR2_SQ8_0 0x00000020U /!<Bit 0 /
Kojto	122:f9eeca106725	1620	#define ADC_SQR2_SQ8_1 0x00000040U /!<Bit 1 /
Kojto	122:f9eeca106725	1621	#define ADC_SQR2_SQ8_2 0x00000080U /!<Bit 2 /
Kojto	122:f9eeca106725	1622	#define ADC_SQR2_SQ8_3 0x00000100U /!<Bit 3 /
Kojto	122:f9eeca106725	1623	#define ADC_SQR2_SQ8_4 0x00000200U /!<Bit 4 /
Kojto	122:f9eeca106725	1624	#define ADC_SQR2_SQ9 0x00007C00U /!<SQ9[4:0] bits (9th conversion in regular sequence) /
Kojto	122:f9eeca106725	1625	#define ADC_SQR2_SQ9_0 0x00000400U /!<Bit 0 /
Kojto	122:f9eeca106725	1626	#define ADC_SQR2_SQ9_1 0x00000800U /!<Bit 1 /
Kojto	122:f9eeca106725	1627	#define ADC_SQR2_SQ9_2 0x00001000U /!<Bit 2 /
Kojto	122:f9eeca106725	1628	#define ADC_SQR2_SQ9_3 0x00002000U /!<Bit 3 /
Kojto	122:f9eeca106725	1629	#define ADC_SQR2_SQ9_4 0x00004000U /!<Bit 4 /
Kojto	122:f9eeca106725	1630	#define ADC_SQR2_SQ10 0x000F8000U /!<SQ10[4:0] bits (10th conversion in regular sequence) /
Kojto	122:f9eeca106725	1631	#define ADC_SQR2_SQ10_0 0x00008000U /!<Bit 0 /
Kojto	122:f9eeca106725	1632	#define ADC_SQR2_SQ10_1 0x00010000U /!<Bit 1 /
Kojto	122:f9eeca106725	1633	#define ADC_SQR2_SQ10_2 0x00020000U /!<Bit 2 /
Kojto	122:f9eeca106725	1634	#define ADC_SQR2_SQ10_3 0x00040000U /!<Bit 3 /
Kojto	122:f9eeca106725	1635	#define ADC_SQR2_SQ10_4 0x00080000U /!<Bit 4 /
Kojto	122:f9eeca106725	1636	#define ADC_SQR2_SQ11 0x01F00000U /!<SQ11[4:0] bits (11th conversion in regular sequence) /
Kojto	122:f9eeca106725	1637	#define ADC_SQR2_SQ11_0 0x00100000U /!<Bit 0 /
Kojto	122:f9eeca106725	1638	#define ADC_SQR2_SQ11_1 0x00200000U /!<Bit 1 /
Kojto	122:f9eeca106725	1639	#define ADC_SQR2_SQ11_2 0x00400000U /!<Bit 2 /
Kojto	122:f9eeca106725	1640	#define ADC_SQR2_SQ11_3 0x00800000U /!<Bit 3 /
Kojto	122:f9eeca106725	1641	#define ADC_SQR2_SQ11_4 0x01000000U /!<Bit 4 /
Kojto	122:f9eeca106725	1642	#define ADC_SQR2_SQ12 0x3E000000U /!<SQ12[4:0] bits (12th conversion in regular sequence) /
Kojto	122:f9eeca106725	1643	#define ADC_SQR2_SQ12_0 0x02000000U /!<Bit 0 /
Kojto	122:f9eeca106725	1644	#define ADC_SQR2_SQ12_1 0x04000000U /!<Bit 1 /
Kojto	122:f9eeca106725	1645	#define ADC_SQR2_SQ12_2 0x08000000U /!<Bit 2 /
Kojto	122:f9eeca106725	1646	#define ADC_SQR2_SQ12_3 0x10000000U /!<Bit 3 /
Kojto	122:f9eeca106725	1647	#define ADC_SQR2_SQ12_4 0x20000000U /!<Bit 4 /
Kojto	110:165afa46840b	1648
Kojto	110:165afa46840b	1649	/***************** Bit definition for ADC_SQR3 register *****************/
Kojto	122:f9eeca106725	1650	#define ADC_SQR3_SQ1 0x0000001FU /!<SQ1[4:0] bits (1st conversion in regular sequence) /
Kojto	122:f9eeca106725	1651	#define ADC_SQR3_SQ1_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	1652	#define ADC_SQR3_SQ1_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	1653	#define ADC_SQR3_SQ1_2 0x00000004U /!<Bit 2 /
Kojto	122:f9eeca106725	1654	#define ADC_SQR3_SQ1_3 0x00000008U /!<Bit 3 /
Kojto	122:f9eeca106725	1655	#define ADC_SQR3_SQ1_4 0x00000010U /!<Bit 4 /
Kojto	122:f9eeca106725	1656	#define ADC_SQR3_SQ2 0x000003E0U /!<SQ2[4:0] bits (2nd conversion in regular sequence) /
Kojto	122:f9eeca106725	1657	#define ADC_SQR3_SQ2_0 0x00000020U /!<Bit 0 /
Kojto	122:f9eeca106725	1658	#define ADC_SQR3_SQ2_1 0x00000040U /!<Bit 1 /
Kojto	122:f9eeca106725	1659	#define ADC_SQR3_SQ2_2 0x00000080U /!<Bit 2 /
Kojto	122:f9eeca106725	1660	#define ADC_SQR3_SQ2_3 0x00000100U /!<Bit 3 /
Kojto	122:f9eeca106725	1661	#define ADC_SQR3_SQ2_4 0x00000200U /!<Bit 4 /
Kojto	122:f9eeca106725	1662	#define ADC_SQR3_SQ3 0x00007C00U /!<SQ3[4:0] bits (3rd conversion in regular sequence) /
Kojto	122:f9eeca106725	1663	#define ADC_SQR3_SQ3_0 0x00000400U /!<Bit 0 /
Kojto	122:f9eeca106725	1664	#define ADC_SQR3_SQ3_1 0x00000800U /!<Bit 1 /
Kojto	122:f9eeca106725	1665	#define ADC_SQR3_SQ3_2 0x00001000U /!<Bit 2 /
Kojto	122:f9eeca106725	1666	#define ADC_SQR3_SQ3_3 0x00002000U /!<Bit 3 /
Kojto	122:f9eeca106725	1667	#define ADC_SQR3_SQ3_4 0x00004000U /!<Bit 4 /
Kojto	122:f9eeca106725	1668	#define ADC_SQR3_SQ4 0x000F8000U /!<SQ4[4:0] bits (4th conversion in regular sequence) /
Kojto	122:f9eeca106725	1669	#define ADC_SQR3_SQ4_0 0x00008000U /!<Bit 0 /
Kojto	122:f9eeca106725	1670	#define ADC_SQR3_SQ4_1 0x00010000U /!<Bit 1 /
Kojto	122:f9eeca106725	1671	#define ADC_SQR3_SQ4_2 0x00020000U /!<Bit 2 /
Kojto	122:f9eeca106725	1672	#define ADC_SQR3_SQ4_3 0x00040000U /!<Bit 3 /
Kojto	122:f9eeca106725	1673	#define ADC_SQR3_SQ4_4 0x00080000U /!<Bit 4 /
Kojto	122:f9eeca106725	1674	#define ADC_SQR3_SQ5 0x01F00000U /!<SQ5[4:0] bits (5th conversion in regular sequence) /
Kojto	122:f9eeca106725	1675	#define ADC_SQR3_SQ5_0 0x00100000U /!<Bit 0 /
Kojto	122:f9eeca106725	1676	#define ADC_SQR3_SQ5_1 0x00200000U /!<Bit 1 /
Kojto	122:f9eeca106725	1677	#define ADC_SQR3_SQ5_2 0x00400000U /!<Bit 2 /
Kojto	122:f9eeca106725	1678	#define ADC_SQR3_SQ5_3 0x00800000U /!<Bit 3 /
Kojto	122:f9eeca106725	1679	#define ADC_SQR3_SQ5_4 0x01000000U /!<Bit 4 /
Kojto	122:f9eeca106725	1680	#define ADC_SQR3_SQ6 0x3E000000U /!<SQ6[4:0] bits (6th conversion in regular sequence) /
Kojto	122:f9eeca106725	1681	#define ADC_SQR3_SQ6_0 0x02000000U /!<Bit 0 /
Kojto	122:f9eeca106725	1682	#define ADC_SQR3_SQ6_1 0x04000000U /!<Bit 1 /
Kojto	122:f9eeca106725	1683	#define ADC_SQR3_SQ6_2 0x08000000U /!<Bit 2 /
Kojto	122:f9eeca106725	1684	#define ADC_SQR3_SQ6_3 0x10000000U /!<Bit 3 /
Kojto	122:f9eeca106725	1685	#define ADC_SQR3_SQ6_4 0x20000000U /!<Bit 4 /
Kojto	110:165afa46840b	1686
Kojto	110:165afa46840b	1687	/***************** Bit definition for ADC_JSQR register *****************/
Kojto	122:f9eeca106725	1688	#define ADC_JSQR_JSQ1 0x0000001FU /!<JSQ1[4:0] bits (1st conversion in injected sequence) /
Kojto	122:f9eeca106725	1689	#define ADC_JSQR_JSQ1_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	1690	#define ADC_JSQR_JSQ1_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	1691	#define ADC_JSQR_JSQ1_2 0x00000004U /!<Bit 2 /
Kojto	122:f9eeca106725	1692	#define ADC_JSQR_JSQ1_3 0x00000008U /!<Bit 3 /
Kojto	122:f9eeca106725	1693	#define ADC_JSQR_JSQ1_4 0x00000010U /!<Bit 4 /
Kojto	122:f9eeca106725	1694	#define ADC_JSQR_JSQ2 0x000003E0U /!<JSQ2[4:0] bits (2nd conversion in injected sequence) /
Kojto	122:f9eeca106725	1695	#define ADC_JSQR_JSQ2_0 0x00000020U /!<Bit 0 /
Kojto	122:f9eeca106725	1696	#define ADC_JSQR_JSQ2_1 0x00000040U /!<Bit 1 /
Kojto	122:f9eeca106725	1697	#define ADC_JSQR_JSQ2_2 0x00000080U /!<Bit 2 /
Kojto	122:f9eeca106725	1698	#define ADC_JSQR_JSQ2_3 0x00000100U /!<Bit 3 /
Kojto	122:f9eeca106725	1699	#define ADC_JSQR_JSQ2_4 0x00000200U /!<Bit 4 /
Kojto	122:f9eeca106725	1700	#define ADC_JSQR_JSQ3 0x00007C00U /!<JSQ3[4:0] bits (3rd conversion in injected sequence) /
Kojto	122:f9eeca106725	1701	#define ADC_JSQR_JSQ3_0 0x00000400U /!<Bit 0 /
Kojto	122:f9eeca106725	1702	#define ADC_JSQR_JSQ3_1 0x00000800U /!<Bit 1 /
Kojto	122:f9eeca106725	1703	#define ADC_JSQR_JSQ3_2 0x00001000U /!<Bit 2 /
Kojto	122:f9eeca106725	1704	#define ADC_JSQR_JSQ3_3 0x00002000U /!<Bit 3 /
Kojto	122:f9eeca106725	1705	#define ADC_JSQR_JSQ3_4 0x00004000U /!<Bit 4 /
Kojto	122:f9eeca106725	1706	#define ADC_JSQR_JSQ4 0x000F8000U /!<JSQ4[4:0] bits (4th conversion in injected sequence) /
Kojto	122:f9eeca106725	1707	#define ADC_JSQR_JSQ4_0 0x00008000U /!<Bit 0 /
Kojto	122:f9eeca106725	1708	#define ADC_JSQR_JSQ4_1 0x00010000U /!<Bit 1 /
Kojto	122:f9eeca106725	1709	#define ADC_JSQR_JSQ4_2 0x00020000U /!<Bit 2 /
Kojto	122:f9eeca106725	1710	#define ADC_JSQR_JSQ4_3 0x00040000U /!<Bit 3 /
Kojto	122:f9eeca106725	1711	#define ADC_JSQR_JSQ4_4 0x00080000U /!<Bit 4 /
Kojto	122:f9eeca106725	1712	#define ADC_JSQR_JL 0x00300000U /!<JL[1:0] bits (Injected Sequence length) /
Kojto	122:f9eeca106725	1713	#define ADC_JSQR_JL_0 0x00100000U /!<Bit 0 /
Kojto	122:f9eeca106725	1714	#define ADC_JSQR_JL_1 0x00200000U /!<Bit 1 /
Kojto	110:165afa46840b	1715
Kojto	110:165afa46840b	1716	/***************** Bit definition for ADC_JDR1 register *****************/
Kojto	122:f9eeca106725	1717	#define ADC_JDR1_JDATA 0xFFFFU /!<Injected data /
Kojto	110:165afa46840b	1718
Kojto	110:165afa46840b	1719	/***************** Bit definition for ADC_JDR2 register *****************/
Kojto	122:f9eeca106725	1720	#define ADC_JDR2_JDATA 0xFFFFU /!<Injected data /
Kojto	110:165afa46840b	1721
Kojto	110:165afa46840b	1722	/***************** Bit definition for ADC_JDR3 register *****************/
Kojto	122:f9eeca106725	1723	#define ADC_JDR3_JDATA 0xFFFFU /!<Injected data /
Kojto	110:165afa46840b	1724
Kojto	110:165afa46840b	1725	/***************** Bit definition for ADC_JDR4 register *****************/
Kojto	122:f9eeca106725	1726	#define ADC_JDR4_JDATA 0xFFFFU /!<Injected data /
Kojto	110:165afa46840b	1727
Kojto	110:165afa46840b	1728	/****************** Bit definition for ADC_DR register ******************/
Kojto	122:f9eeca106725	1729	#define ADC_DR_DATA 0x0000FFFFU /!<Regular data /
Kojto	122:f9eeca106725	1730	#define ADC_DR_ADC2DATA 0xFFFF0000U /!<ADC2 data /
Kojto	110:165afa46840b	1731
Kojto	110:165afa46840b	1732	/***************** Bit definition for ADC_CSR register ******************/
Kojto	122:f9eeca106725	1733	#define ADC_CSR_AWD1 0x00000001U /!<ADC1 Analog watchdog flag /
Kojto	122:f9eeca106725	1734	#define ADC_CSR_EOC1 0x00000002U /!<ADC1 End of conversion /
Kojto	122:f9eeca106725	1735	#define ADC_CSR_JEOC1 0x00000004U /!<ADC1 Injected channel end of conversion /
Kojto	122:f9eeca106725	1736	#define ADC_CSR_JSTRT1 0x00000008U /!<ADC1 Injected channel Start flag /
Kojto	122:f9eeca106725	1737	#define ADC_CSR_STRT1 0x00000010U /!<ADC1 Regular channel Start flag /
Kojto	122:f9eeca106725	1738	#define ADC_CSR_OVR1 0x00000020U /!<ADC1 DMA overrun flag /
Kojto	122:f9eeca106725	1739	#define ADC_CSR_AWD2 0x00000100U /!<ADC2 Analog watchdog flag /
Kojto	122:f9eeca106725	1740	#define ADC_CSR_EOC2 0x00000200U /!<ADC2 End of conversion /
Kojto	122:f9eeca106725	1741	#define ADC_CSR_JEOC2 0x00000400U /!<ADC2 Injected channel end of conversion /
Kojto	122:f9eeca106725	1742	#define ADC_CSR_JSTRT2 0x00000800U /!<ADC2 Injected channel Start flag /
Kojto	122:f9eeca106725	1743	#define ADC_CSR_STRT2 0x00001000U /!<ADC2 Regular channel Start flag /
Kojto	122:f9eeca106725	1744	#define ADC_CSR_OVR2 0x00002000U /!<ADC2 DMA overrun flag /
Kojto	122:f9eeca106725	1745	#define ADC_CSR_AWD3 0x00010000U /!<ADC3 Analog watchdog flag /
Kojto	122:f9eeca106725	1746	#define ADC_CSR_EOC3 0x00020000U /!<ADC3 End of conversion /
Kojto	122:f9eeca106725	1747	#define ADC_CSR_JEOC3 0x00040000U /!<ADC3 Injected channel end of conversion /
Kojto	122:f9eeca106725	1748	#define ADC_CSR_JSTRT3 0x00080000U /!<ADC3 Injected channel Start flag /
Kojto	122:f9eeca106725	1749	#define ADC_CSR_STRT3 0x00100000U /!<ADC3 Regular channel Start flag /
Kojto	122:f9eeca106725	1750	#define ADC_CSR_OVR3 0x00200000U /!<ADC3 DMA overrun flag /
Kojto	122:f9eeca106725	1751
Kojto	122:f9eeca106725	1752	/* Legacy defines */
Kojto	122:f9eeca106725	1753	#define ADC_CSR_DOVR1 ADC_CSR_OVR1
Kojto	122:f9eeca106725	1754	#define ADC_CSR_DOVR2 ADC_CSR_OVR2
Kojto	122:f9eeca106725	1755	#define ADC_CSR_DOVR3 ADC_CSR_OVR3
Kojto	110:165afa46840b	1756
Kojto	110:165afa46840b	1757	/***************** Bit definition for ADC_CCR register ******************/
Kojto	122:f9eeca106725	1758	#define ADC_CCR_MULTI 0x0000001FU /!<MULTI[4:0] bits (Multi-ADC mode selection) /
Kojto	122:f9eeca106725	1759	#define ADC_CCR_MULTI_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	1760	#define ADC_CCR_MULTI_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	1761	#define ADC_CCR_MULTI_2 0x00000004U /!<Bit 2 /
Kojto	122:f9eeca106725	1762	#define ADC_CCR_MULTI_3 0x00000008U /!<Bit 3 /
Kojto	122:f9eeca106725	1763	#define ADC_CCR_MULTI_4 0x00000010U /!<Bit 4 /
Kojto	122:f9eeca106725	1764	#define ADC_CCR_DELAY 0x00000F00U /!<DELAY[3:0] bits (Delay between 2 sampling phases) /
Kojto	122:f9eeca106725	1765	#define ADC_CCR_DELAY_0 0x00000100U /!<Bit 0 /
Kojto	122:f9eeca106725	1766	#define ADC_CCR_DELAY_1 0x00000200U /!<Bit 1 /
Kojto	122:f9eeca106725	1767	#define ADC_CCR_DELAY_2 0x00000400U /!<Bit 2 /
Kojto	122:f9eeca106725	1768	#define ADC_CCR_DELAY_3 0x00000800U /!<Bit 3 /
Kojto	122:f9eeca106725	1769	#define ADC_CCR_DDS 0x00002000U /!<DMA disable selection (Multi-ADC mode) /
Kojto	122:f9eeca106725	1770	#define ADC_CCR_DMA 0x0000C000U /!<DMA[1:0] bits (Direct Memory Access mode for multimode) /
Kojto	122:f9eeca106725	1771	#define ADC_CCR_DMA_0 0x00004000U /!<Bit 0 /
Kojto	122:f9eeca106725	1772	#define ADC_CCR_DMA_1 0x00008000U /!<Bit 1 /
Kojto	122:f9eeca106725	1773	#define ADC_CCR_ADCPRE 0x00030000U /!<ADCPRE[1:0] bits (ADC prescaler) /
Kojto	122:f9eeca106725	1774	#define ADC_CCR_ADCPRE_0 0x00010000U /!<Bit 0 /
Kojto	122:f9eeca106725	1775	#define ADC_CCR_ADCPRE_1 0x00020000U /!<Bit 1 /
Kojto	122:f9eeca106725	1776	#define ADC_CCR_VBATE 0x00400000U /!<VBAT Enable /
Kojto	122:f9eeca106725	1777	#define ADC_CCR_TSVREFE 0x00800000U /!<Temperature Sensor and VREFINT Enable /
Kojto	110:165afa46840b	1778
Kojto	110:165afa46840b	1779	/***************** Bit definition for ADC_CDR register ******************/
Kojto	122:f9eeca106725	1780	#define ADC_CDR_DATA1 0x0000FFFFU /!<1st data of a pair of regular conversions /
Kojto	122:f9eeca106725	1781	#define ADC_CDR_DATA2 0xFFFF0000U /!<2nd data of a pair of regular conversions /
Kojto	110:165afa46840b	1782
Kojto	110:165afa46840b	1783	/******************************************************************************/
Kojto	110:165afa46840b	1784	/* */
Kojto	110:165afa46840b	1785	/* Controller Area Network */
Kojto	110:165afa46840b	1786	/* */
Kojto	110:165afa46840b	1787	/******************************************************************************/
Kojto	110:165afa46840b	1788	/!<CAN control and status registers /
Kojto	110:165afa46840b	1789	/***************** Bit definition for CAN_MCR register ******************/
Kojto	122:f9eeca106725	1790	#define CAN_MCR_INRQ 0x00000001U /!<Initialization Request /
Kojto	122:f9eeca106725	1791	#define CAN_MCR_SLEEP 0x00000002U /!<Sleep Mode Request /
Kojto	122:f9eeca106725	1792	#define CAN_MCR_TXFP 0x00000004U /!<Transmit FIFO Priority /
Kojto	122:f9eeca106725	1793	#define CAN_MCR_RFLM 0x00000008U /!<Receive FIFO Locked Mode /
Kojto	122:f9eeca106725	1794	#define CAN_MCR_NART 0x00000010U /!<No Automatic Retransmission /
Kojto	122:f9eeca106725	1795	#define CAN_MCR_AWUM 0x00000020U /!<Automatic Wakeup Mode /
Kojto	122:f9eeca106725	1796	#define CAN_MCR_ABOM 0x00000040U /!<Automatic Bus-Off Management /
Kojto	122:f9eeca106725	1797	#define CAN_MCR_TTCM 0x00000080U /!<Time Triggered Communication Mode /
Kojto	122:f9eeca106725	1798	#define CAN_MCR_RESET 0x00008000U /!<bxCAN software master reset /
Kojto	122:f9eeca106725	1799	#define CAN_MCR_DBF 0x00010000U /!<bxCAN Debug freeze /
Kojto	110:165afa46840b	1800	/***************** Bit definition for CAN_MSR register ******************/
Kojto	122:f9eeca106725	1801	#define CAN_MSR_INAK 0x0001U /!<Initialization Acknowledge /
Kojto	122:f9eeca106725	1802	#define CAN_MSR_SLAK 0x0002U /!<Sleep Acknowledge /
Kojto	122:f9eeca106725	1803	#define CAN_MSR_ERRI 0x0004U /!<Error Interrupt /
Kojto	122:f9eeca106725	1804	#define CAN_MSR_WKUI 0x0008U /!<Wakeup Interrupt /
Kojto	122:f9eeca106725	1805	#define CAN_MSR_SLAKI 0x0010U /!<Sleep Acknowledge Interrupt /
Kojto	122:f9eeca106725	1806	#define CAN_MSR_TXM 0x0100U /!<Transmit Mode /
Kojto	122:f9eeca106725	1807	#define CAN_MSR_RXM 0x0200U /!<Receive Mode /
Kojto	122:f9eeca106725	1808	#define CAN_MSR_SAMP 0x0400U /!<Last Sample Point /
Kojto	122:f9eeca106725	1809	#define CAN_MSR_RX 0x0800U /!<CAN Rx Signal /
Kojto	110:165afa46840b	1810
Kojto	110:165afa46840b	1811	/***************** Bit definition for CAN_TSR register ******************/
Kojto	122:f9eeca106725	1812	#define CAN_TSR_RQCP0 0x00000001U /!<Request Completed Mailbox0 /
Kojto	122:f9eeca106725	1813	#define CAN_TSR_TXOK0 0x00000002U /!<Transmission OK of Mailbox0 /
Kojto	122:f9eeca106725	1814	#define CAN_TSR_ALST0 0x00000004U /!<Arbitration Lost for Mailbox0 /
Kojto	122:f9eeca106725	1815	#define CAN_TSR_TERR0 0x00000008U /!<Transmission Error of Mailbox0 /
Kojto	122:f9eeca106725	1816	#define CAN_TSR_ABRQ0 0x00000080U /!<Abort Request for Mailbox0 /
Kojto	122:f9eeca106725	1817	#define CAN_TSR_RQCP1 0x00000100U /!<Request Completed Mailbox1 /
Kojto	122:f9eeca106725	1818	#define CAN_TSR_TXOK1 0x00000200U /!<Transmission OK of Mailbox1 /
Kojto	122:f9eeca106725	1819	#define CAN_TSR_ALST1 0x00000400U /!<Arbitration Lost for Mailbox1 /
Kojto	122:f9eeca106725	1820	#define CAN_TSR_TERR1 0x00000800U /!<Transmission Error of Mailbox1 /
Kojto	122:f9eeca106725	1821	#define CAN_TSR_ABRQ1 0x00008000U /!<Abort Request for Mailbox 1 /
Kojto	122:f9eeca106725	1822	#define CAN_TSR_RQCP2 0x00010000U /!<Request Completed Mailbox2 /
Kojto	122:f9eeca106725	1823	#define CAN_TSR_TXOK2 0x00020000U /!<Transmission OK of Mailbox 2 /
Kojto	122:f9eeca106725	1824	#define CAN_TSR_ALST2 0x00040000U /!<Arbitration Lost for mailbox 2 /
Kojto	122:f9eeca106725	1825	#define CAN_TSR_TERR2 0x00080000U /!<Transmission Error of Mailbox 2 /
Kojto	122:f9eeca106725	1826	#define CAN_TSR_ABRQ2 0x00800000U /!<Abort Request for Mailbox 2 /
Kojto	122:f9eeca106725	1827	#define CAN_TSR_CODE 0x03000000U /!<Mailbox Code /
Kojto	122:f9eeca106725	1828
Kojto	122:f9eeca106725	1829	#define CAN_TSR_TME 0x1C000000U /!<TME[2:0] bits /
Kojto	122:f9eeca106725	1830	#define CAN_TSR_TME0 0x04000000U /!<Transmit Mailbox 0 Empty /
Kojto	122:f9eeca106725	1831	#define CAN_TSR_TME1 0x08000000U /!<Transmit Mailbox 1 Empty /
Kojto	122:f9eeca106725	1832	#define CAN_TSR_TME2 0x10000000U /!<Transmit Mailbox 2 Empty /
Kojto	122:f9eeca106725	1833
Kojto	122:f9eeca106725	1834	#define CAN_TSR_LOW 0xE0000000U /!<LOW[2:0] bits /
Kojto	122:f9eeca106725	1835	#define CAN_TSR_LOW0 0x20000000U /!<Lowest Priority Flag for Mailbox 0 /
Kojto	122:f9eeca106725	1836	#define CAN_TSR_LOW1 0x40000000U /!<Lowest Priority Flag for Mailbox 1 /
Kojto	122:f9eeca106725	1837	#define CAN_TSR_LOW2 0x80000000U /!<Lowest Priority Flag for Mailbox 2 /
Kojto	110:165afa46840b	1838
Kojto	110:165afa46840b	1839	/***************** Bit definition for CAN_RF0R register *****************/
Kojto	122:f9eeca106725	1840	#define CAN_RF0R_FMP0 0x03U /!<FIFO 0 Message Pending /
Kojto	122:f9eeca106725	1841	#define CAN_RF0R_FULL0 0x08U /!<FIFO 0 Full /
Kojto	122:f9eeca106725	1842	#define CAN_RF0R_FOVR0 0x10U /!<FIFO 0 Overrun /
Kojto	122:f9eeca106725	1843	#define CAN_RF0R_RFOM0 0x20U /!<Release FIFO 0 Output Mailbox /
Kojto	110:165afa46840b	1844
Kojto	110:165afa46840b	1845	/***************** Bit definition for CAN_RF1R register *****************/
Kojto	122:f9eeca106725	1846	#define CAN_RF1R_FMP1 0x03U /!<FIFO 1 Message Pending /
Kojto	122:f9eeca106725	1847	#define CAN_RF1R_FULL1 0x08U /!<FIFO 1 Full /
Kojto	122:f9eeca106725	1848	#define CAN_RF1R_FOVR1 0x10U /!<FIFO 1 Overrun /
Kojto	122:f9eeca106725	1849	#define CAN_RF1R_RFOM1 0x20U /!<Release FIFO 1 Output Mailbox /
Kojto	110:165afa46840b	1850
Kojto	110:165afa46840b	1851	/****************** Bit definition for CAN_IER register *****************/
Kojto	122:f9eeca106725	1852	#define CAN_IER_TMEIE 0x00000001U /!<Transmit Mailbox Empty Interrupt Enable /
Kojto	122:f9eeca106725	1853	#define CAN_IER_FMPIE0 0x00000002U /!<FIFO Message Pending Interrupt Enable /
Kojto	122:f9eeca106725	1854	#define CAN_IER_FFIE0 0x00000004U /!<FIFO Full Interrupt Enable /
Kojto	122:f9eeca106725	1855	#define CAN_IER_FOVIE0 0x00000008U /!<FIFO Overrun Interrupt Enable /
Kojto	122:f9eeca106725	1856	#define CAN_IER_FMPIE1 0x00000010U /!<FIFO Message Pending Interrupt Enable /
Kojto	122:f9eeca106725	1857	#define CAN_IER_FFIE1 0x00000020U /!<FIFO Full Interrupt Enable /
Kojto	122:f9eeca106725	1858	#define CAN_IER_FOVIE1 0x00000040U /!<FIFO Overrun Interrupt Enable /
Kojto	122:f9eeca106725	1859	#define CAN_IER_EWGIE 0x00000100U /!<Error Warning Interrupt Enable /
Kojto	122:f9eeca106725	1860	#define CAN_IER_EPVIE 0x00000200U /!<Error Passive Interrupt Enable /
Kojto	122:f9eeca106725	1861	#define CAN_IER_BOFIE 0x00000400U /!<Bus-Off Interrupt Enable /
Kojto	122:f9eeca106725	1862	#define CAN_IER_LECIE 0x00000800U /!<Last Error Code Interrupt Enable /
Kojto	122:f9eeca106725	1863	#define CAN_IER_ERRIE 0x00008000U /!<Error Interrupt Enable /
Kojto	122:f9eeca106725	1864	#define CAN_IER_WKUIE 0x00010000U /!<Wakeup Interrupt Enable /
Kojto	122:f9eeca106725	1865	#define CAN_IER_SLKIE 0x00020000U /!<Sleep Interrupt Enable /
Kojto	122:f9eeca106725	1866	#define CAN_IER_EWGIE 0x00000100U /!<Error warning interrupt enable /
Kojto	122:f9eeca106725	1867	#define CAN_IER_EPVIE 0x00000200U /!<Error passive interrupt enable /
Kojto	122:f9eeca106725	1868	#define CAN_IER_BOFIE 0x00000400U /!<Bus-off interrupt enable /
Kojto	122:f9eeca106725	1869	#define CAN_IER_LECIE 0x00000800U /!<Last error code interrupt enable /
Kojto	122:f9eeca106725	1870	#define CAN_IER_ERRIE 0x00008000U /!<Error interrupt enable /
Kojto	110:165afa46840b	1871
Kojto	110:165afa46840b	1872
Kojto	110:165afa46840b	1873	/****************** Bit definition for CAN_ESR register *****************/
Kojto	122:f9eeca106725	1874	#define CAN_ESR_EWGF 0x00000001U /!<Error Warning Flag /
Kojto	122:f9eeca106725	1875	#define CAN_ESR_EPVF 0x00000002U /!<Error Passive Flag /
Kojto	122:f9eeca106725	1876	#define CAN_ESR_BOFF 0x00000004U /!<Bus-Off Flag /
Kojto	122:f9eeca106725	1877
Kojto	122:f9eeca106725	1878	#define CAN_ESR_LEC 0x00000070U /!<LEC[2:0] bits (Last Error Code) /
Kojto	122:f9eeca106725	1879	#define CAN_ESR_LEC_0 0x00000010U /!<Bit 0 /
Kojto	122:f9eeca106725	1880	#define CAN_ESR_LEC_1 0x00000020U /!<Bit 1 /
Kojto	122:f9eeca106725	1881	#define CAN_ESR_LEC_2 0x00000040U /!<Bit 2 /
Kojto	122:f9eeca106725	1882
Kojto	122:f9eeca106725	1883	#define CAN_ESR_TEC 0x00FF0000U /!<Least significant byte of the 9-bit Transmit Error Counter /
Kojto	122:f9eeca106725	1884	#define CAN_ESR_REC 0xFF000000U /!<Receive Error Counter /
Kojto	110:165afa46840b	1885
Kojto	110:165afa46840b	1886	/***************** Bit definition for CAN_BTR register ******************/
Kojto	122:f9eeca106725	1887	#define CAN_BTR_BRP 0x000003FFU /!<Baud Rate Prescaler /
Kojto	122:f9eeca106725	1888	#define CAN_BTR_TS1 0x000F0000U /!<Time Segment 1 /
Kojto	122:f9eeca106725	1889	#define CAN_BTR_TS1_0 0x00010000U /!<Bit 0 /
Kojto	122:f9eeca106725	1890	#define CAN_BTR_TS1_1 0x00020000U /!<Bit 1 /
Kojto	122:f9eeca106725	1891	#define CAN_BTR_TS1_2 0x00040000U /!<Bit 2 /
Kojto	122:f9eeca106725	1892	#define CAN_BTR_TS1_3 0x00080000U /!<Bit 3 /
Kojto	122:f9eeca106725	1893	#define CAN_BTR_TS2 0x00700000U /!<Time Segment 2 /
Kojto	122:f9eeca106725	1894	#define CAN_BTR_TS2_0 0x00100000U /!<Bit 0 /
Kojto	122:f9eeca106725	1895	#define CAN_BTR_TS2_1 0x00200000U /!<Bit 1 /
Kojto	122:f9eeca106725	1896	#define CAN_BTR_TS2_2 0x00400000U /!<Bit 2 /
Kojto	122:f9eeca106725	1897	#define CAN_BTR_SJW 0x03000000U /!<Resynchronization Jump Width /
Kojto	122:f9eeca106725	1898	#define CAN_BTR_SJW_0 0x01000000U /!<Bit 0 /
Kojto	122:f9eeca106725	1899	#define CAN_BTR_SJW_1 0x02000000U /!<Bit 1 /
Kojto	122:f9eeca106725	1900	#define CAN_BTR_LBKM 0x40000000U /!<Loop Back Mode (Debug) /
Kojto	122:f9eeca106725	1901	#define CAN_BTR_SILM 0x80000000U /!<Silent Mode /
Kojto	110:165afa46840b	1902
Kojto	110:165afa46840b	1903
Kojto	110:165afa46840b	1904	/!<Mailbox registers /
Kojto	110:165afa46840b	1905	/**************** Bit definition for CAN_TI0R register ******************/
Kojto	122:f9eeca106725	1906	#define CAN_TI0R_TXRQ 0x00000001U /!<Transmit Mailbox Request /
Kojto	122:f9eeca106725	1907	#define CAN_TI0R_RTR 0x00000002U /!<Remote Transmission Request /
Kojto	122:f9eeca106725	1908	#define CAN_TI0R_IDE 0x00000004U /!<Identifier Extension /
Kojto	122:f9eeca106725	1909	#define CAN_TI0R_EXID 0x001FFFF8U /!<Extended Identifier /
Kojto	122:f9eeca106725	1910	#define CAN_TI0R_STID 0xFFE00000U /!<Standard Identifier or Extended Identifier /
Kojto	110:165afa46840b	1911
Kojto	110:165afa46840b	1912	/**************** Bit definition for CAN_TDT0R register *****************/
Kojto	122:f9eeca106725	1913	#define CAN_TDT0R_DLC 0x0000000FU /!<Data Length Code /
Kojto	122:f9eeca106725	1914	#define CAN_TDT0R_TGT 0x00000100U /!<Transmit Global Time /
Kojto	122:f9eeca106725	1915	#define CAN_TDT0R_TIME 0xFFFF0000U /!<Message Time Stamp /
Kojto	110:165afa46840b	1916
Kojto	110:165afa46840b	1917	/**************** Bit definition for CAN_TDL0R register *****************/
Kojto	122:f9eeca106725	1918	#define CAN_TDL0R_DATA0 0x000000FFU /!<Data byte 0 /
Kojto	122:f9eeca106725	1919	#define CAN_TDL0R_DATA1 0x0000FF00U /!<Data byte 1 /
Kojto	122:f9eeca106725	1920	#define CAN_TDL0R_DATA2 0x00FF0000U /!<Data byte 2 /
Kojto	122:f9eeca106725	1921	#define CAN_TDL0R_DATA3 0xFF000000U /!<Data byte 3 /
Kojto	110:165afa46840b	1922
Kojto	110:165afa46840b	1923	/**************** Bit definition for CAN_TDH0R register *****************/
Kojto	122:f9eeca106725	1924	#define CAN_TDH0R_DATA4 0x000000FFU /!<Data byte 4 /
Kojto	122:f9eeca106725	1925	#define CAN_TDH0R_DATA5 0x0000FF00U /!<Data byte 5 /
Kojto	122:f9eeca106725	1926	#define CAN_TDH0R_DATA6 0x00FF0000U /!<Data byte 6 /
Kojto	122:f9eeca106725	1927	#define CAN_TDH0R_DATA7 0xFF000000U /!<Data byte 7 /
Kojto	110:165afa46840b	1928
Kojto	110:165afa46840b	1929	/***************** Bit definition for CAN_TI1R register *****************/
Kojto	122:f9eeca106725	1930	#define CAN_TI1R_TXRQ 0x00000001U /!<Transmit Mailbox Request /
Kojto	122:f9eeca106725	1931	#define CAN_TI1R_RTR 0x00000002U /!<Remote Transmission Request /
Kojto	122:f9eeca106725	1932	#define CAN_TI1R_IDE 0x00000004U /!<Identifier Extension /
Kojto	122:f9eeca106725	1933	#define CAN_TI1R_EXID 0x001FFFF8U /!<Extended Identifier /
Kojto	122:f9eeca106725	1934	#define CAN_TI1R_STID 0xFFE00000U /!<Standard Identifier or Extended Identifier /
Kojto	110:165afa46840b	1935
Kojto	110:165afa46840b	1936	/***************** Bit definition for CAN_TDT1R register ****************/
Kojto	122:f9eeca106725	1937	#define CAN_TDT1R_DLC 0x0000000FU /!<Data Length Code /
Kojto	122:f9eeca106725	1938	#define CAN_TDT1R_TGT 0x00000100U /!<Transmit Global Time /
Kojto	122:f9eeca106725	1939	#define CAN_TDT1R_TIME 0xFFFF0000U /!<Message Time Stamp /
Kojto	110:165afa46840b	1940
Kojto	110:165afa46840b	1941	/***************** Bit definition for CAN_TDL1R register ****************/
Kojto	122:f9eeca106725	1942	#define CAN_TDL1R_DATA0 0x000000FFU /!<Data byte 0 /
Kojto	122:f9eeca106725	1943	#define CAN_TDL1R_DATA1 0x0000FF00U /!<Data byte 1 /
Kojto	122:f9eeca106725	1944	#define CAN_TDL1R_DATA2 0x00FF0000U /!<Data byte 2 /
Kojto	122:f9eeca106725	1945	#define CAN_TDL1R_DATA3 0xFF000000U /!<Data byte 3 /
Kojto	110:165afa46840b	1946
Kojto	110:165afa46840b	1947	/***************** Bit definition for CAN_TDH1R register ****************/
Kojto	122:f9eeca106725	1948	#define CAN_TDH1R_DATA4 0x000000FFU /!<Data byte 4 /
Kojto	122:f9eeca106725	1949	#define CAN_TDH1R_DATA5 0x0000FF00U /!<Data byte 5 /
Kojto	122:f9eeca106725	1950	#define CAN_TDH1R_DATA6 0x00FF0000U /!<Data byte 6 /
Kojto	122:f9eeca106725	1951	#define CAN_TDH1R_DATA7 0xFF000000U /!<Data byte 7 /
Kojto	110:165afa46840b	1952
Kojto	110:165afa46840b	1953	/***************** Bit definition for CAN_TI2R register *****************/
Kojto	122:f9eeca106725	1954	#define CAN_TI2R_TXRQ 0x00000001U /!<Transmit Mailbox Request /
Kojto	122:f9eeca106725	1955	#define CAN_TI2R_RTR 0x00000002U /!<Remote Transmission Request /
Kojto	122:f9eeca106725	1956	#define CAN_TI2R_IDE 0x00000004U /!<Identifier Extension /
Kojto	122:f9eeca106725	1957	#define CAN_TI2R_EXID 0x001FFFF8U /!<Extended identifier /
Kojto	122:f9eeca106725	1958	#define CAN_TI2R_STID 0xFFE00000U /!<Standard Identifier or Extended Identifier /
Kojto	110:165afa46840b	1959
Kojto	110:165afa46840b	1960	/***************** Bit definition for CAN_TDT2R register ****************/
Kojto	122:f9eeca106725	1961	#define CAN_TDT2R_DLC 0x0000000FU /!<Data Length Code /
Kojto	122:f9eeca106725	1962	#define CAN_TDT2R_TGT 0x00000100U /!<Transmit Global Time /
Kojto	122:f9eeca106725	1963	#define CAN_TDT2R_TIME 0xFFFF0000U /!<Message Time Stamp /
Kojto	110:165afa46840b	1964
Kojto	110:165afa46840b	1965	/***************** Bit definition for CAN_TDL2R register ****************/
Kojto	122:f9eeca106725	1966	#define CAN_TDL2R_DATA0 0x000000FFU /!<Data byte 0 /
Kojto	122:f9eeca106725	1967	#define CAN_TDL2R_DATA1 0x0000FF00U /!<Data byte 1 /
Kojto	122:f9eeca106725	1968	#define CAN_TDL2R_DATA2 0x00FF0000U /!<Data byte 2 /
Kojto	122:f9eeca106725	1969	#define CAN_TDL2R_DATA3 0xFF000000U /!<Data byte 3 /
Kojto	110:165afa46840b	1970
Kojto	110:165afa46840b	1971	/***************** Bit definition for CAN_TDH2R register ****************/
Kojto	122:f9eeca106725	1972	#define CAN_TDH2R_DATA4 0x000000FFU /!<Data byte 4 /
Kojto	122:f9eeca106725	1973	#define CAN_TDH2R_DATA5 0x0000FF00U /!<Data byte 5 /
Kojto	122:f9eeca106725	1974	#define CAN_TDH2R_DATA6 0x00FF0000U /!<Data byte 6 /
Kojto	122:f9eeca106725	1975	#define CAN_TDH2R_DATA7 0xFF000000U /!<Data byte 7 /
Kojto	110:165afa46840b	1976
Kojto	110:165afa46840b	1977	/***************** Bit definition for CAN_RI0R register *****************/
Kojto	122:f9eeca106725	1978	#define CAN_RI0R_RTR 0x00000002U /!<Remote Transmission Request /
Kojto	122:f9eeca106725	1979	#define CAN_RI0R_IDE 0x00000004U /!<Identifier Extension /
Kojto	122:f9eeca106725	1980	#define CAN_RI0R_EXID 0x001FFFF8U /!<Extended Identifier /
Kojto	122:f9eeca106725	1981	#define CAN_RI0R_STID 0xFFE00000U /!<Standard Identifier or Extended Identifier /
Kojto	110:165afa46840b	1982
Kojto	110:165afa46840b	1983	/***************** Bit definition for CAN_RDT0R register ****************/
Kojto	122:f9eeca106725	1984	#define CAN_RDT0R_DLC 0x0000000FU /!<Data Length Code /
Kojto	122:f9eeca106725	1985	#define CAN_RDT0R_FMI 0x0000FF00U /!<Filter Match Index /
Kojto	122:f9eeca106725	1986	#define CAN_RDT0R_TIME 0xFFFF0000U /!<Message Time Stamp /
Kojto	110:165afa46840b	1987
Kojto	110:165afa46840b	1988	/***************** Bit definition for CAN_RDL0R register ****************/
Kojto	122:f9eeca106725	1989	#define CAN_RDL0R_DATA0 0x000000FFU /!<Data byte 0 /
Kojto	122:f9eeca106725	1990	#define CAN_RDL0R_DATA1 0x0000FF00U /!<Data byte 1 /
Kojto	122:f9eeca106725	1991	#define CAN_RDL0R_DATA2 0x00FF0000U /!<Data byte 2 /
Kojto	122:f9eeca106725	1992	#define CAN_RDL0R_DATA3 0xFF000000U /!<Data byte 3 /
Kojto	110:165afa46840b	1993
Kojto	110:165afa46840b	1994	/***************** Bit definition for CAN_RDH0R register ****************/
Kojto	122:f9eeca106725	1995	#define CAN_RDH0R_DATA4 0x000000FFU /!<Data byte 4 /
Kojto	122:f9eeca106725	1996	#define CAN_RDH0R_DATA5 0x0000FF00U /!<Data byte 5 /
Kojto	122:f9eeca106725	1997	#define CAN_RDH0R_DATA6 0x00FF0000U /!<Data byte 6 /
Kojto	122:f9eeca106725	1998	#define CAN_RDH0R_DATA7 0xFF000000U /!<Data byte 7 /
Kojto	110:165afa46840b	1999
Kojto	110:165afa46840b	2000	/***************** Bit definition for CAN_RI1R register *****************/
Kojto	122:f9eeca106725	2001	#define CAN_RI1R_RTR 0x00000002U /!<Remote Transmission Request /
Kojto	122:f9eeca106725	2002	#define CAN_RI1R_IDE 0x00000004U /!<Identifier Extension /
Kojto	122:f9eeca106725	2003	#define CAN_RI1R_EXID 0x001FFFF8U /!<Extended identifier /
Kojto	122:f9eeca106725	2004	#define CAN_RI1R_STID 0xFFE00000U /!<Standard Identifier or Extended Identifier /
Kojto	110:165afa46840b	2005
Kojto	110:165afa46840b	2006	/***************** Bit definition for CAN_RDT1R register ****************/
Kojto	122:f9eeca106725	2007	#define CAN_RDT1R_DLC 0x0000000FU /!<Data Length Code /
Kojto	122:f9eeca106725	2008	#define CAN_RDT1R_FMI 0x0000FF00U /!<Filter Match Index /
Kojto	122:f9eeca106725	2009	#define CAN_RDT1R_TIME 0xFFFF0000U /!<Message Time Stamp /
Kojto	110:165afa46840b	2010
Kojto	110:165afa46840b	2011	/***************** Bit definition for CAN_RDL1R register ****************/
Kojto	122:f9eeca106725	2012	#define CAN_RDL1R_DATA0 0x000000FFU /!<Data byte 0 /
Kojto	122:f9eeca106725	2013	#define CAN_RDL1R_DATA1 0x0000FF00U /!<Data byte 1 /
Kojto	122:f9eeca106725	2014	#define CAN_RDL1R_DATA2 0x00FF0000U /!<Data byte 2 /
Kojto	122:f9eeca106725	2015	#define CAN_RDL1R_DATA3 0xFF000000U /!<Data byte 3 /
Kojto	110:165afa46840b	2016
Kojto	110:165afa46840b	2017	/***************** Bit definition for CAN_RDH1R register ****************/
Kojto	122:f9eeca106725	2018	#define CAN_RDH1R_DATA4 0x000000FFU /!<Data byte 4 /
Kojto	122:f9eeca106725	2019	#define CAN_RDH1R_DATA5 0x0000FF00U /!<Data byte 5 /
Kojto	122:f9eeca106725	2020	#define CAN_RDH1R_DATA6 0x00FF0000U /!<Data byte 6 /
Kojto	122:f9eeca106725	2021	#define CAN_RDH1R_DATA7 0xFF000000U /!<Data byte 7 /
Kojto	110:165afa46840b	2022
Kojto	110:165afa46840b	2023	/!<CAN filter registers /
Kojto	110:165afa46840b	2024	/***************** Bit definition for CAN_FMR register ******************/
Kojto	122:f9eeca106725	2025	#define CAN_FMR_FINIT 0x01U /!<Filter Init Mode /
Kojto	122:f9eeca106725	2026	#define CAN_FMR_CAN2SB 0x00003F00U /!<CAN2 start bank /
Kojto	110:165afa46840b	2027
Kojto	110:165afa46840b	2028	/***************** Bit definition for CAN_FM1R register *****************/
Kojto	122:f9eeca106725	2029	#define CAN_FM1R_FBM 0x0FFFFFFFU /!<Filter Mode /
Kojto	122:f9eeca106725	2030	#define CAN_FM1R_FBM0 0x00000001U /!<Filter Init Mode bit 0 /
Kojto	122:f9eeca106725	2031	#define CAN_FM1R_FBM1 0x00000002U /!<Filter Init Mode bit 1 /
Kojto	122:f9eeca106725	2032	#define CAN_FM1R_FBM2 0x00000004U /!<Filter Init Mode bit 2 /
Kojto	122:f9eeca106725	2033	#define CAN_FM1R_FBM3 0x00000008U /!<Filter Init Mode bit 3 /
Kojto	122:f9eeca106725	2034	#define CAN_FM1R_FBM4 0x00000010U /!<Filter Init Mode bit 4 /
Kojto	122:f9eeca106725	2035	#define CAN_FM1R_FBM5 0x00000020U /!<Filter Init Mode bit 5 /
Kojto	122:f9eeca106725	2036	#define CAN_FM1R_FBM6 0x00000040U /!<Filter Init Mode bit 6 /
Kojto	122:f9eeca106725	2037	#define CAN_FM1R_FBM7 0x00000080U /!<Filter Init Mode bit 7 /
Kojto	122:f9eeca106725	2038	#define CAN_FM1R_FBM8 0x00000100U /!<Filter Init Mode bit 8 /
Kojto	122:f9eeca106725	2039	#define CAN_FM1R_FBM9 0x00000200U /!<Filter Init Mode bit 9 /
Kojto	122:f9eeca106725	2040	#define CAN_FM1R_FBM10 0x00000400U /!<Filter Init Mode bit 10 /
Kojto	122:f9eeca106725	2041	#define CAN_FM1R_FBM11 0x00000800U /!<Filter Init Mode bit 11 /
Kojto	122:f9eeca106725	2042	#define CAN_FM1R_FBM12 0x00001000U /!<Filter Init Mode bit 12 /
Kojto	122:f9eeca106725	2043	#define CAN_FM1R_FBM13 0x00002000U /!<Filter Init Mode bit 13 /
Kojto	122:f9eeca106725	2044	#define CAN_FM1R_FBM14 0x00004000U /!<Filter Init Mode bit 14 /
Kojto	122:f9eeca106725	2045	#define CAN_FM1R_FBM15 0x00008000U /!<Filter Init Mode bit 15 /
Kojto	122:f9eeca106725	2046	#define CAN_FM1R_FBM16 0x00010000U /!<Filter Init Mode bit 16 /
Kojto	122:f9eeca106725	2047	#define CAN_FM1R_FBM17 0x00020000U /!<Filter Init Mode bit 17 /
Kojto	122:f9eeca106725	2048	#define CAN_FM1R_FBM18 0x00040000U /!<Filter Init Mode bit 18 /
Kojto	122:f9eeca106725	2049	#define CAN_FM1R_FBM19 0x00080000U /!<Filter Init Mode bit 19 /
Kojto	122:f9eeca106725	2050	#define CAN_FM1R_FBM20 0x00100000U /!<Filter Init Mode bit 20 /
Kojto	122:f9eeca106725	2051	#define CAN_FM1R_FBM21 0x00200000U /!<Filter Init Mode bit 21 /
Kojto	122:f9eeca106725	2052	#define CAN_FM1R_FBM22 0x00400000U /!<Filter Init Mode bit 22 /
Kojto	122:f9eeca106725	2053	#define CAN_FM1R_FBM23 0x00800000U /!<Filter Init Mode bit 23 /
Kojto	122:f9eeca106725	2054	#define CAN_FM1R_FBM24 0x01000000U /!<Filter Init Mode bit 24 /
Kojto	122:f9eeca106725	2055	#define CAN_FM1R_FBM25 0x02000000U /!<Filter Init Mode bit 25 /
Kojto	122:f9eeca106725	2056	#define CAN_FM1R_FBM26 0x04000000U /!<Filter Init Mode bit 26 /
Kojto	122:f9eeca106725	2057	#define CAN_FM1R_FBM27 0x08000000U /!<Filter Init Mode bit 27 /
Kojto	110:165afa46840b	2058
Kojto	110:165afa46840b	2059	/***************** Bit definition for CAN_FS1R register *****************/
Kojto	122:f9eeca106725	2060	#define CAN_FS1R_FSC 0x0FFFFFFFU /!<Filter Scale Configuration /
Kojto	122:f9eeca106725	2061	#define CAN_FS1R_FSC0 0x00000001U /!<Filter Scale Configuration bit 0 /
Kojto	122:f9eeca106725	2062	#define CAN_FS1R_FSC1 0x00000002U /!<Filter Scale Configuration bit 1 /
Kojto	122:f9eeca106725	2063	#define CAN_FS1R_FSC2 0x00000004U /!<Filter Scale Configuration bit 2 /
Kojto	122:f9eeca106725	2064	#define CAN_FS1R_FSC3 0x00000008U /!<Filter Scale Configuration bit 3 /
Kojto	122:f9eeca106725	2065	#define CAN_FS1R_FSC4 0x00000010U /!<Filter Scale Configuration bit 4 /
Kojto	122:f9eeca106725	2066	#define CAN_FS1R_FSC5 0x00000020U /!<Filter Scale Configuration bit 5 /
Kojto	122:f9eeca106725	2067	#define CAN_FS1R_FSC6 0x00000040U /!<Filter Scale Configuration bit 6 /
Kojto	122:f9eeca106725	2068	#define CAN_FS1R_FSC7 0x00000080U /!<Filter Scale Configuration bit 7 /
Kojto	122:f9eeca106725	2069	#define CAN_FS1R_FSC8 0x00000100U /!<Filter Scale Configuration bit 8 /
Kojto	122:f9eeca106725	2070	#define CAN_FS1R_FSC9 0x00000200U /!<Filter Scale Configuration bit 9 /
Kojto	122:f9eeca106725	2071	#define CAN_FS1R_FSC10 0x00000400U /!<Filter Scale Configuration bit 10 /
Kojto	122:f9eeca106725	2072	#define CAN_FS1R_FSC11 0x00000800U /!<Filter Scale Configuration bit 11 /
Kojto	122:f9eeca106725	2073	#define CAN_FS1R_FSC12 0x00001000U /!<Filter Scale Configuration bit 12 /
Kojto	122:f9eeca106725	2074	#define CAN_FS1R_FSC13 0x00002000U /!<Filter Scale Configuration bit 13 /
Kojto	122:f9eeca106725	2075	#define CAN_FS1R_FSC14 0x00004000U /!<Filter Scale Configuration bit 14 /
Kojto	122:f9eeca106725	2076	#define CAN_FS1R_FSC15 0x00008000U /!<Filter Scale Configuration bit 15 /
Kojto	122:f9eeca106725	2077	#define CAN_FS1R_FSC16 0x00010000U /!<Filter Scale Configuration bit 16 /
Kojto	122:f9eeca106725	2078	#define CAN_FS1R_FSC17 0x00020000U /!<Filter Scale Configuration bit 17 /
Kojto	122:f9eeca106725	2079	#define CAN_FS1R_FSC18 0x00040000U /!<Filter Scale Configuration bit 18 /
Kojto	122:f9eeca106725	2080	#define CAN_FS1R_FSC19 0x00080000U /!<Filter Scale Configuration bit 19 /
Kojto	122:f9eeca106725	2081	#define CAN_FS1R_FSC20 0x00100000U /!<Filter Scale Configuration bit 20 /
Kojto	122:f9eeca106725	2082	#define CAN_FS1R_FSC21 0x00200000U /!<Filter Scale Configuration bit 21 /
Kojto	122:f9eeca106725	2083	#define CAN_FS1R_FSC22 0x00400000U /!<Filter Scale Configuration bit 22 /
Kojto	122:f9eeca106725	2084	#define CAN_FS1R_FSC23 0x00800000U /!<Filter Scale Configuration bit 23 /
Kojto	122:f9eeca106725	2085	#define CAN_FS1R_FSC24 0x01000000U /!<Filter Scale Configuration bit 24 /
Kojto	122:f9eeca106725	2086	#define CAN_FS1R_FSC25 0x02000000U /!<Filter Scale Configuration bit 25 /
Kojto	122:f9eeca106725	2087	#define CAN_FS1R_FSC26 0x04000000U /!<Filter Scale Configuration bit 26 /
Kojto	122:f9eeca106725	2088	#define CAN_FS1R_FSC27 0x08000000U /!<Filter Scale Configuration bit 27 /
Kojto	110:165afa46840b	2089
Kojto	110:165afa46840b	2090	/**************** Bit definition for CAN_FFA1R register *****************/
Kojto	122:f9eeca106725	2091	#define CAN_FFA1R_FFA 0x0FFFFFFFU /!<Filter FIFO Assignment /
Kojto	122:f9eeca106725	2092	#define CAN_FFA1R_FFA0 0x00000001U /!<Filter FIFO Assignment bit 0 /
Kojto	122:f9eeca106725	2093	#define CAN_FFA1R_FFA1 0x00000002U /!<Filter FIFO Assignment bit 1 /
Kojto	122:f9eeca106725	2094	#define CAN_FFA1R_FFA2 0x00000004U /!<Filter FIFO Assignment bit 2 /
Kojto	122:f9eeca106725	2095	#define CAN_FFA1R_FFA3 0x00000008U /!<Filter FIFO Assignment bit 3 /
Kojto	122:f9eeca106725	2096	#define CAN_FFA1R_FFA4 0x00000010U /!<Filter FIFO Assignment bit 4 /
Kojto	122:f9eeca106725	2097	#define CAN_FFA1R_FFA5 0x00000020U /!<Filter FIFO Assignment bit 5 /
Kojto	122:f9eeca106725	2098	#define CAN_FFA1R_FFA6 0x00000040U /!<Filter FIFO Assignment bit 6 /
Kojto	122:f9eeca106725	2099	#define CAN_FFA1R_FFA7 0x00000080U /!<Filter FIFO Assignment bit 7 /
Kojto	122:f9eeca106725	2100	#define CAN_FFA1R_FFA8 0x00000100U /!<Filter FIFO Assignment bit 8 /
Kojto	122:f9eeca106725	2101	#define CAN_FFA1R_FFA9 0x00000200U /!<Filter FIFO Assignment bit 9 /
Kojto	122:f9eeca106725	2102	#define CAN_FFA1R_FFA10 0x00000400U /!<Filter FIFO Assignment bit 10 /
Kojto	122:f9eeca106725	2103	#define CAN_FFA1R_FFA11 0x00000800U /!<Filter FIFO Assignment bit 11 /
Kojto	122:f9eeca106725	2104	#define CAN_FFA1R_FFA12 0x00001000U /!<Filter FIFO Assignment bit 12 /
Kojto	122:f9eeca106725	2105	#define CAN_FFA1R_FFA13 0x00002000U /!<Filter FIFO Assignment bit 13 /
Kojto	122:f9eeca106725	2106	#define CAN_FFA1R_FFA14 0x00004000U /!<Filter FIFO Assignment bit 14 /
Kojto	122:f9eeca106725	2107	#define CAN_FFA1R_FFA15 0x00008000U /!<Filter FIFO Assignment bit 15 /
Kojto	122:f9eeca106725	2108	#define CAN_FFA1R_FFA16 0x00010000U /!<Filter FIFO Assignment bit 16 /
Kojto	122:f9eeca106725	2109	#define CAN_FFA1R_FFA17 0x00020000U /!<Filter FIFO Assignment bit 17 /
Kojto	122:f9eeca106725	2110	#define CAN_FFA1R_FFA18 0x00040000U /!<Filter FIFO Assignment bit 18 /
Kojto	122:f9eeca106725	2111	#define CAN_FFA1R_FFA19 0x00080000U /!<Filter FIFO Assignment bit 19 /
Kojto	122:f9eeca106725	2112	#define CAN_FFA1R_FFA20 0x00100000U /!<Filter FIFO Assignment bit 20 /
Kojto	122:f9eeca106725	2113	#define CAN_FFA1R_FFA21 0x00200000U /!<Filter FIFO Assignment bit 21 /
Kojto	122:f9eeca106725	2114	#define CAN_FFA1R_FFA22 0x00400000U /!<Filter FIFO Assignment bit 22 /
Kojto	122:f9eeca106725	2115	#define CAN_FFA1R_FFA23 0x00800000U /!<Filter FIFO Assignment bit 23 /
Kojto	122:f9eeca106725	2116	#define CAN_FFA1R_FFA24 0x01000000U /!<Filter FIFO Assignment bit 24 /
Kojto	122:f9eeca106725	2117	#define CAN_FFA1R_FFA25 0x02000000U /!<Filter FIFO Assignment bit 25 /
Kojto	122:f9eeca106725	2118	#define CAN_FFA1R_FFA26 0x04000000U /!<Filter FIFO Assignment bit 26 /
Kojto	122:f9eeca106725	2119	#define CAN_FFA1R_FFA27 0x08000000U /!<Filter FIFO Assignment bit 27 /
Kojto	110:165afa46840b	2120
Kojto	110:165afa46840b	2121	/***************** Bit definition for CAN_FA1R register *****************/
Kojto	122:f9eeca106725	2122	#define CAN_FA1R_FACT 0x0FFFFFFFU /!<Filter Active /
Kojto	122:f9eeca106725	2123	#define CAN_FA1R_FACT0 0x00000001U /!<Filter Active bit 0 /
Kojto	122:f9eeca106725	2124	#define CAN_FA1R_FACT1 0x00000002U /!<Filter Active bit 1 /
Kojto	122:f9eeca106725	2125	#define CAN_FA1R_FACT2 0x00000004U /!<Filter Active bit 2 /
Kojto	122:f9eeca106725	2126	#define CAN_FA1R_FACT3 0x00000008U /!<Filter Active bit 3 /
Kojto	122:f9eeca106725	2127	#define CAN_FA1R_FACT4 0x00000010U /!<Filter Active bit 4 /
Kojto	122:f9eeca106725	2128	#define CAN_FA1R_FACT5 0x00000020U /!<Filter Active bit 5 /
Kojto	122:f9eeca106725	2129	#define CAN_FA1R_FACT6 0x00000040U /!<Filter Active bit 6 /
Kojto	122:f9eeca106725	2130	#define CAN_FA1R_FACT7 0x00000080U /!<Filter Active bit 7 /
Kojto	122:f9eeca106725	2131	#define CAN_FA1R_FACT8 0x00000100U /!<Filter Active bit 8 /
Kojto	122:f9eeca106725	2132	#define CAN_FA1R_FACT9 0x00000200U /!<Filter Active bit 9 /
Kojto	122:f9eeca106725	2133	#define CAN_FA1R_FACT10 0x00000400U /!<Filter Active bit 10 /
Kojto	122:f9eeca106725	2134	#define CAN_FA1R_FACT11 0x00000800U /!<Filter Active bit 11 /
Kojto	122:f9eeca106725	2135	#define CAN_FA1R_FACT12 0x00001000U /!<Filter Active bit 12 /
Kojto	122:f9eeca106725	2136	#define CAN_FA1R_FACT13 0x00002000U /!<Filter Active bit 13 /
Kojto	122:f9eeca106725	2137	#define CAN_FA1R_FACT14 0x00004000U /!<Filter Active bit 14 /
Kojto	122:f9eeca106725	2138	#define CAN_FA1R_FACT15 0x00008000U /!<Filter Active bit 15 /
Kojto	122:f9eeca106725	2139	#define CAN_FA1R_FACT16 0x00010000U /!<Filter Active bit 16 /
Kojto	122:f9eeca106725	2140	#define CAN_FA1R_FACT17 0x00020000U /!<Filter Active bit 17 /
Kojto	122:f9eeca106725	2141	#define CAN_FA1R_FACT18 0x00040000U /!<Filter Active bit 18 /
Kojto	122:f9eeca106725	2142	#define CAN_FA1R_FACT19 0x00080000U /!<Filter Active bit 19 /
Kojto	122:f9eeca106725	2143	#define CAN_FA1R_FACT20 0x00100000U /!<Filter Active bit 20 /
Kojto	122:f9eeca106725	2144	#define CAN_FA1R_FACT21 0x00200000U /!<Filter Active bit 21 /
Kojto	122:f9eeca106725	2145	#define CAN_FA1R_FACT22 0x00400000U /!<Filter Active bit 22 /
Kojto	122:f9eeca106725	2146	#define CAN_FA1R_FACT23 0x00800000U /!<Filter Active bit 23 /
Kojto	122:f9eeca106725	2147	#define CAN_FA1R_FACT24 0x01000000U /!<Filter Active bit 24 /
Kojto	122:f9eeca106725	2148	#define CAN_FA1R_FACT25 0x02000000U /!<Filter Active bit 25 /
Kojto	122:f9eeca106725	2149	#define CAN_FA1R_FACT26 0x04000000U /!<Filter Active bit 26 /
Kojto	122:f9eeca106725	2150	#define CAN_FA1R_FACT27 0x08000000U /!<Filter Active bit 27 /
Kojto	110:165afa46840b	2151
Kojto	110:165afa46840b	2152
Kojto	110:165afa46840b	2153	/***************** Bit definition for CAN_F0R1 register *****************/
Kojto	122:f9eeca106725	2154	#define CAN_F0R1_FB0 0x00000001U /!<Filter bit 0 /
Kojto	122:f9eeca106725	2155	#define CAN_F0R1_FB1 0x00000002U /!<Filter bit 1 /
Kojto	122:f9eeca106725	2156	#define CAN_F0R1_FB2 0x00000004U /!<Filter bit 2 /
Kojto	122:f9eeca106725	2157	#define CAN_F0R1_FB3 0x00000008U /!<Filter bit 3 /
Kojto	122:f9eeca106725	2158	#define CAN_F0R1_FB4 0x00000010U /!<Filter bit 4 /
Kojto	122:f9eeca106725	2159	#define CAN_F0R1_FB5 0x00000020U /!<Filter bit 5 /
Kojto	122:f9eeca106725	2160	#define CAN_F0R1_FB6 0x00000040U /!<Filter bit 6 /
Kojto	122:f9eeca106725	2161	#define CAN_F0R1_FB7 0x00000080U /!<Filter bit 7 /
Kojto	122:f9eeca106725	2162	#define CAN_F0R1_FB8 0x00000100U /!<Filter bit 8 /
Kojto	122:f9eeca106725	2163	#define CAN_F0R1_FB9 0x00000200U /!<Filter bit 9 /
Kojto	122:f9eeca106725	2164	#define CAN_F0R1_FB10 0x00000400U /!<Filter bit 10 /
Kojto	122:f9eeca106725	2165	#define CAN_F0R1_FB11 0x00000800U /!<Filter bit 11 /
Kojto	122:f9eeca106725	2166	#define CAN_F0R1_FB12 0x00001000U /!<Filter bit 12 /
Kojto	122:f9eeca106725	2167	#define CAN_F0R1_FB13 0x00002000U /!<Filter bit 13 /
Kojto	122:f9eeca106725	2168	#define CAN_F0R1_FB14 0x00004000U /!<Filter bit 14 /
Kojto	122:f9eeca106725	2169	#define CAN_F0R1_FB15 0x00008000U /!<Filter bit 15 /
Kojto	122:f9eeca106725	2170	#define CAN_F0R1_FB16 0x00010000U /!<Filter bit 16 /
Kojto	122:f9eeca106725	2171	#define CAN_F0R1_FB17 0x00020000U /!<Filter bit 17 /
Kojto	122:f9eeca106725	2172	#define CAN_F0R1_FB18 0x00040000U /!<Filter bit 18 /
Kojto	122:f9eeca106725	2173	#define CAN_F0R1_FB19 0x00080000U /!<Filter bit 19 /
Kojto	122:f9eeca106725	2174	#define CAN_F0R1_FB20 0x00100000U /!<Filter bit 20 /
Kojto	122:f9eeca106725	2175	#define CAN_F0R1_FB21 0x00200000U /!<Filter bit 21 /
Kojto	122:f9eeca106725	2176	#define CAN_F0R1_FB22 0x00400000U /!<Filter bit 22 /
Kojto	122:f9eeca106725	2177	#define CAN_F0R1_FB23 0x00800000U /!<Filter bit 23 /
Kojto	122:f9eeca106725	2178	#define CAN_F0R1_FB24 0x01000000U /!<Filter bit 24 /
Kojto	122:f9eeca106725	2179	#define CAN_F0R1_FB25 0x02000000U /!<Filter bit 25 /
Kojto	122:f9eeca106725	2180	#define CAN_F0R1_FB26 0x04000000U /!<Filter bit 26 /
Kojto	122:f9eeca106725	2181	#define CAN_F0R1_FB27 0x08000000U /!<Filter bit 27 /
Kojto	122:f9eeca106725	2182	#define CAN_F0R1_FB28 0x10000000U /!<Filter bit 28 /
Kojto	122:f9eeca106725	2183	#define CAN_F0R1_FB29 0x20000000U /!<Filter bit 29 /
Kojto	122:f9eeca106725	2184	#define CAN_F0R1_FB30 0x40000000U /!<Filter bit 30 /
Kojto	122:f9eeca106725	2185	#define CAN_F0R1_FB31 0x80000000U /!<Filter bit 31 /
Kojto	110:165afa46840b	2186
Kojto	110:165afa46840b	2187	/***************** Bit definition for CAN_F1R1 register *****************/
Kojto	122:f9eeca106725	2188	#define CAN_F1R1_FB0 0x00000001U /!<Filter bit 0 /
Kojto	122:f9eeca106725	2189	#define CAN_F1R1_FB1 0x00000002U /!<Filter bit 1 /
Kojto	122:f9eeca106725	2190	#define CAN_F1R1_FB2 0x00000004U /!<Filter bit 2 /
Kojto	122:f9eeca106725	2191	#define CAN_F1R1_FB3 0x00000008U /!<Filter bit 3 /
Kojto	122:f9eeca106725	2192	#define CAN_F1R1_FB4 0x00000010U /!<Filter bit 4 /
Kojto	122:f9eeca106725	2193	#define CAN_F1R1_FB5 0x00000020U /!<Filter bit 5 /
Kojto	122:f9eeca106725	2194	#define CAN_F1R1_FB6 0x00000040U /!<Filter bit 6 /
Kojto	122:f9eeca106725	2195	#define CAN_F1R1_FB7 0x00000080U /!<Filter bit 7 /
Kojto	122:f9eeca106725	2196	#define CAN_F1R1_FB8 0x00000100U /!<Filter bit 8 /
Kojto	122:f9eeca106725	2197	#define CAN_F1R1_FB9 0x00000200U /!<Filter bit 9 /
Kojto	122:f9eeca106725	2198	#define CAN_F1R1_FB10 0x00000400U /!<Filter bit 10 /
Kojto	122:f9eeca106725	2199	#define CAN_F1R1_FB11 0x00000800U /!<Filter bit 11 /
Kojto	122:f9eeca106725	2200	#define CAN_F1R1_FB12 0x00001000U /!<Filter bit 12 /
Kojto	122:f9eeca106725	2201	#define CAN_F1R1_FB13 0x00002000U /!<Filter bit 13 /
Kojto	122:f9eeca106725	2202	#define CAN_F1R1_FB14 0x00004000U /!<Filter bit 14 /
Kojto	122:f9eeca106725	2203	#define CAN_F1R1_FB15 0x00008000U /!<Filter bit 15 /
Kojto	122:f9eeca106725	2204	#define CAN_F1R1_FB16 0x00010000U /!<Filter bit 16 /
Kojto	122:f9eeca106725	2205	#define CAN_F1R1_FB17 0x00020000U /!<Filter bit 17 /
Kojto	122:f9eeca106725	2206	#define CAN_F1R1_FB18 0x00040000U /!<Filter bit 18 /
Kojto	122:f9eeca106725	2207	#define CAN_F1R1_FB19 0x00080000U /!<Filter bit 19 /
Kojto	122:f9eeca106725	2208	#define CAN_F1R1_FB20 0x00100000U /!<Filter bit 20 /
Kojto	122:f9eeca106725	2209	#define CAN_F1R1_FB21 0x00200000U /!<Filter bit 21 /
Kojto	122:f9eeca106725	2210	#define CAN_F1R1_FB22 0x00400000U /!<Filter bit 22 /
Kojto	122:f9eeca106725	2211	#define CAN_F1R1_FB23 0x00800000U /!<Filter bit 23 /
Kojto	122:f9eeca106725	2212	#define CAN_F1R1_FB24 0x01000000U /!<Filter bit 24 /
Kojto	122:f9eeca106725	2213	#define CAN_F1R1_FB25 0x02000000U /!<Filter bit 25 /
Kojto	122:f9eeca106725	2214	#define CAN_F1R1_FB26 0x04000000U /!<Filter bit 26 /
Kojto	122:f9eeca106725	2215	#define CAN_F1R1_FB27 0x08000000U /!<Filter bit 27 /
Kojto	122:f9eeca106725	2216	#define CAN_F1R1_FB28 0x10000000U /!<Filter bit 28 /
Kojto	122:f9eeca106725	2217	#define CAN_F1R1_FB29 0x20000000U /!<Filter bit 29 /
Kojto	122:f9eeca106725	2218	#define CAN_F1R1_FB30 0x40000000U /!<Filter bit 30 /
Kojto	122:f9eeca106725	2219	#define CAN_F1R1_FB31 0x80000000U /!<Filter bit 31 /
Kojto	110:165afa46840b	2220
Kojto	110:165afa46840b	2221	/***************** Bit definition for CAN_F2R1 register *****************/
Kojto	122:f9eeca106725	2222	#define CAN_F2R1_FB0 0x00000001U /!<Filter bit 0 /
Kojto	122:f9eeca106725	2223	#define CAN_F2R1_FB1 0x00000002U /!<Filter bit 1 /
Kojto	122:f9eeca106725	2224	#define CAN_F2R1_FB2 0x00000004U /!<Filter bit 2 /
Kojto	122:f9eeca106725	2225	#define CAN_F2R1_FB3 0x00000008U /!<Filter bit 3 /
Kojto	122:f9eeca106725	2226	#define CAN_F2R1_FB4 0x00000010U /!<Filter bit 4 /
Kojto	122:f9eeca106725	2227	#define CAN_F2R1_FB5 0x00000020U /!<Filter bit 5 /
Kojto	122:f9eeca106725	2228	#define CAN_F2R1_FB6 0x00000040U /!<Filter bit 6 /
Kojto	122:f9eeca106725	2229	#define CAN_F2R1_FB7 0x00000080U /!<Filter bit 7 /
Kojto	122:f9eeca106725	2230	#define CAN_F2R1_FB8 0x00000100U /!<Filter bit 8 /
Kojto	122:f9eeca106725	2231	#define CAN_F2R1_FB9 0x00000200U /!<Filter bit 9 /
Kojto	122:f9eeca106725	2232	#define CAN_F2R1_FB10 0x00000400U /!<Filter bit 10 /
Kojto	122:f9eeca106725	2233	#define CAN_F2R1_FB11 0x00000800U /!<Filter bit 11 /
Kojto	122:f9eeca106725	2234	#define CAN_F2R1_FB12 0x00001000U /!<Filter bit 12 /
Kojto	122:f9eeca106725	2235	#define CAN_F2R1_FB13 0x00002000U /!<Filter bit 13 /
Kojto	122:f9eeca106725	2236	#define CAN_F2R1_FB14 0x00004000U /!<Filter bit 14 /
Kojto	122:f9eeca106725	2237	#define CAN_F2R1_FB15 0x00008000U /!<Filter bit 15 /
Kojto	122:f9eeca106725	2238	#define CAN_F2R1_FB16 0x00010000U /!<Filter bit 16 /
Kojto	122:f9eeca106725	2239	#define CAN_F2R1_FB17 0x00020000U /!<Filter bit 17 /
Kojto	122:f9eeca106725	2240	#define CAN_F2R1_FB18 0x00040000U /!<Filter bit 18 /
Kojto	122:f9eeca106725	2241	#define CAN_F2R1_FB19 0x00080000U /!<Filter bit 19 /
Kojto	122:f9eeca106725	2242	#define CAN_F2R1_FB20 0x00100000U /!<Filter bit 20 /
Kojto	122:f9eeca106725	2243	#define CAN_F2R1_FB21 0x00200000U /!<Filter bit 21 /
Kojto	122:f9eeca106725	2244	#define CAN_F2R1_FB22 0x00400000U /!<Filter bit 22 /
Kojto	122:f9eeca106725	2245	#define CAN_F2R1_FB23 0x00800000U /!<Filter bit 23 /
Kojto	122:f9eeca106725	2246	#define CAN_F2R1_FB24 0x01000000U /!<Filter bit 24 /
Kojto	122:f9eeca106725	2247	#define CAN_F2R1_FB25 0x02000000U /!<Filter bit 25 /
Kojto	122:f9eeca106725	2248	#define CAN_F2R1_FB26 0x04000000U /!<Filter bit 26 /
Kojto	122:f9eeca106725	2249	#define CAN_F2R1_FB27 0x08000000U /!<Filter bit 27 /
Kojto	122:f9eeca106725	2250	#define CAN_F2R1_FB28 0x10000000U /!<Filter bit 28 /
Kojto	122:f9eeca106725	2251	#define CAN_F2R1_FB29 0x20000000U /!<Filter bit 29 /
Kojto	122:f9eeca106725	2252	#define CAN_F2R1_FB30 0x40000000U /!<Filter bit 30 /
Kojto	122:f9eeca106725	2253	#define CAN_F2R1_FB31 0x80000000U /!<Filter bit 31 /
Kojto	110:165afa46840b	2254
Kojto	110:165afa46840b	2255	/***************** Bit definition for CAN_F3R1 register *****************/
Kojto	122:f9eeca106725	2256	#define CAN_F3R1_FB0 0x00000001U /!<Filter bit 0 /
Kojto	122:f9eeca106725	2257	#define CAN_F3R1_FB1 0x00000002U /!<Filter bit 1 /
Kojto	122:f9eeca106725	2258	#define CAN_F3R1_FB2 0x00000004U /!<Filter bit 2 /
Kojto	122:f9eeca106725	2259	#define CAN_F3R1_FB3 0x00000008U /!<Filter bit 3 /
Kojto	122:f9eeca106725	2260	#define CAN_F3R1_FB4 0x00000010U /!<Filter bit 4 /
Kojto	122:f9eeca106725	2261	#define CAN_F3R1_FB5 0x00000020U /!<Filter bit 5 /
Kojto	122:f9eeca106725	2262	#define CAN_F3R1_FB6 0x00000040U /!<Filter bit 6 /
Kojto	122:f9eeca106725	2263	#define CAN_F3R1_FB7 0x00000080U /!<Filter bit 7 /
Kojto	122:f9eeca106725	2264	#define CAN_F3R1_FB8 0x00000100U /!<Filter bit 8 /
Kojto	122:f9eeca106725	2265	#define CAN_F3R1_FB9 0x00000200U /!<Filter bit 9 /
Kojto	122:f9eeca106725	2266	#define CAN_F3R1_FB10 0x00000400U /!<Filter bit 10 /
Kojto	122:f9eeca106725	2267	#define CAN_F3R1_FB11 0x00000800U /!<Filter bit 11 /
Kojto	122:f9eeca106725	2268	#define CAN_F3R1_FB12 0x00001000U /!<Filter bit 12 /
Kojto	122:f9eeca106725	2269	#define CAN_F3R1_FB13 0x00002000U /!<Filter bit 13 /
Kojto	122:f9eeca106725	2270	#define CAN_F3R1_FB14 0x00004000U /!<Filter bit 14 /
Kojto	122:f9eeca106725	2271	#define CAN_F3R1_FB15 0x00008000U /!<Filter bit 15 /
Kojto	122:f9eeca106725	2272	#define CAN_F3R1_FB16 0x00010000U /!<Filter bit 16 /
Kojto	122:f9eeca106725	2273	#define CAN_F3R1_FB17 0x00020000U /!<Filter bit 17 /
Kojto	122:f9eeca106725	2274	#define CAN_F3R1_FB18 0x00040000U /!<Filter bit 18 /
Kojto	122:f9eeca106725	2275	#define CAN_F3R1_FB19 0x00080000U /!<Filter bit 19 /
Kojto	122:f9eeca106725	2276	#define CAN_F3R1_FB20 0x00100000U /!<Filter bit 20 /
Kojto	122:f9eeca106725	2277	#define CAN_F3R1_FB21 0x00200000U /!<Filter bit 21 /
Kojto	122:f9eeca106725	2278	#define CAN_F3R1_FB22 0x00400000U /!<Filter bit 22 /
Kojto	122:f9eeca106725	2279	#define CAN_F3R1_FB23 0x00800000U /!<Filter bit 23 /
Kojto	122:f9eeca106725	2280	#define CAN_F3R1_FB24 0x01000000U /!<Filter bit 24 /
Kojto	122:f9eeca106725	2281	#define CAN_F3R1_FB25 0x02000000U /!<Filter bit 25 /
Kojto	122:f9eeca106725	2282	#define CAN_F3R1_FB26 0x04000000U /!<Filter bit 26 /
Kojto	122:f9eeca106725	2283	#define CAN_F3R1_FB27 0x08000000U /!<Filter bit 27 /
Kojto	122:f9eeca106725	2284	#define CAN_F3R1_FB28 0x10000000U /!<Filter bit 28 /
Kojto	122:f9eeca106725	2285	#define CAN_F3R1_FB29 0x20000000U /!<Filter bit 29 /
Kojto	122:f9eeca106725	2286	#define CAN_F3R1_FB30 0x40000000U /!<Filter bit 30 /
Kojto	122:f9eeca106725	2287	#define CAN_F3R1_FB31 0x80000000U /!<Filter bit 31 /
Kojto	110:165afa46840b	2288
Kojto	110:165afa46840b	2289	/***************** Bit definition for CAN_F4R1 register *****************/
Kojto	122:f9eeca106725	2290	#define CAN_F4R1_FB0 0x00000001U /!<Filter bit 0 /
Kojto	122:f9eeca106725	2291	#define CAN_F4R1_FB1 0x00000002U /!<Filter bit 1 /
Kojto	122:f9eeca106725	2292	#define CAN_F4R1_FB2 0x00000004U /!<Filter bit 2 /
Kojto	122:f9eeca106725	2293	#define CAN_F4R1_FB3 0x00000008U /!<Filter bit 3 /
Kojto	122:f9eeca106725	2294	#define CAN_F4R1_FB4 0x00000010U /!<Filter bit 4 /
Kojto	122:f9eeca106725	2295	#define CAN_F4R1_FB5 0x00000020U /!<Filter bit 5 /
Kojto	122:f9eeca106725	2296	#define CAN_F4R1_FB6 0x00000040U /!<Filter bit 6 /
Kojto	122:f9eeca106725	2297	#define CAN_F4R1_FB7 0x00000080U /!<Filter bit 7 /
Kojto	122:f9eeca106725	2298	#define CAN_F4R1_FB8 0x00000100U /!<Filter bit 8 /
Kojto	122:f9eeca106725	2299	#define CAN_F4R1_FB9 0x00000200U /!<Filter bit 9 /
Kojto	122:f9eeca106725	2300	#define CAN_F4R1_FB10 0x00000400U /!<Filter bit 10 /
Kojto	122:f9eeca106725	2301	#define CAN_F4R1_FB11 0x00000800U /!<Filter bit 11 /
Kojto	122:f9eeca106725	2302	#define CAN_F4R1_FB12 0x00001000U /!<Filter bit 12 /
Kojto	122:f9eeca106725	2303	#define CAN_F4R1_FB13 0x00002000U /!<Filter bit 13 /
Kojto	122:f9eeca106725	2304	#define CAN_F4R1_FB14 0x00004000U /!<Filter bit 14 /
Kojto	122:f9eeca106725	2305	#define CAN_F4R1_FB15 0x00008000U /!<Filter bit 15 /
Kojto	122:f9eeca106725	2306	#define CAN_F4R1_FB16 0x00010000U /!<Filter bit 16 /
Kojto	122:f9eeca106725	2307	#define CAN_F4R1_FB17 0x00020000U /!<Filter bit 17 /
Kojto	122:f9eeca106725	2308	#define CAN_F4R1_FB18 0x00040000U /!<Filter bit 18 /
Kojto	122:f9eeca106725	2309	#define CAN_F4R1_FB19 0x00080000U /!<Filter bit 19 /
Kojto	122:f9eeca106725	2310	#define CAN_F4R1_FB20 0x00100000U /!<Filter bit 20 /
Kojto	122:f9eeca106725	2311	#define CAN_F4R1_FB21 0x00200000U /!<Filter bit 21 /
Kojto	122:f9eeca106725	2312	#define CAN_F4R1_FB22 0x00400000U /!<Filter bit 22 /
Kojto	122:f9eeca106725	2313	#define CAN_F4R1_FB23 0x00800000U /!<Filter bit 23 /
Kojto	122:f9eeca106725	2314	#define CAN_F4R1_FB24 0x01000000U /!<Filter bit 24 /
Kojto	122:f9eeca106725	2315	#define CAN_F4R1_FB25 0x02000000U /!<Filter bit 25 /
Kojto	122:f9eeca106725	2316	#define CAN_F4R1_FB26 0x04000000U /!<Filter bit 26 /
Kojto	122:f9eeca106725	2317	#define CAN_F4R1_FB27 0x08000000U /!<Filter bit 27 /
Kojto	122:f9eeca106725	2318	#define CAN_F4R1_FB28 0x10000000U /!<Filter bit 28 /
Kojto	122:f9eeca106725	2319	#define CAN_F4R1_FB29 0x20000000U /!<Filter bit 29 /
Kojto	122:f9eeca106725	2320	#define CAN_F4R1_FB30 0x40000000U /!<Filter bit 30 /
Kojto	122:f9eeca106725	2321	#define CAN_F4R1_FB31 0x80000000U /!<Filter bit 31 /
Kojto	110:165afa46840b	2322
Kojto	110:165afa46840b	2323	/***************** Bit definition for CAN_F5R1 register *****************/
Kojto	122:f9eeca106725	2324	#define CAN_F5R1_FB0 0x00000001U /!<Filter bit 0 /
Kojto	122:f9eeca106725	2325	#define CAN_F5R1_FB1 0x00000002U /!<Filter bit 1 /
Kojto	122:f9eeca106725	2326	#define CAN_F5R1_FB2 0x00000004U /!<Filter bit 2 /
Kojto	122:f9eeca106725	2327	#define CAN_F5R1_FB3 0x00000008U /!<Filter bit 3 /
Kojto	122:f9eeca106725	2328	#define CAN_F5R1_FB4 0x00000010U /!<Filter bit 4 /
Kojto	122:f9eeca106725	2329	#define CAN_F5R1_FB5 0x00000020U /!<Filter bit 5 /
Kojto	122:f9eeca106725	2330	#define CAN_F5R1_FB6 0x00000040U /!<Filter bit 6 /
Kojto	122:f9eeca106725	2331	#define CAN_F5R1_FB7 0x00000080U /!<Filter bit 7 /
Kojto	122:f9eeca106725	2332	#define CAN_F5R1_FB8 0x00000100U /!<Filter bit 8 /
Kojto	122:f9eeca106725	2333	#define CAN_F5R1_FB9 0x00000200U /!<Filter bit 9 /
Kojto	122:f9eeca106725	2334	#define CAN_F5R1_FB10 0x00000400U /!<Filter bit 10 /
Kojto	122:f9eeca106725	2335	#define CAN_F5R1_FB11 0x00000800U /!<Filter bit 11 /
Kojto	122:f9eeca106725	2336	#define CAN_F5R1_FB12 0x00001000U /!<Filter bit 12 /
Kojto	122:f9eeca106725	2337	#define CAN_F5R1_FB13 0x00002000U /!<Filter bit 13 /
Kojto	122:f9eeca106725	2338	#define CAN_F5R1_FB14 0x00004000U /!<Filter bit 14 /
Kojto	122:f9eeca106725	2339	#define CAN_F5R1_FB15 0x00008000U /!<Filter bit 15 /
Kojto	122:f9eeca106725	2340	#define CAN_F5R1_FB16 0x00010000U /!<Filter bit 16 /
Kojto	122:f9eeca106725	2341	#define CAN_F5R1_FB17 0x00020000U /!<Filter bit 17 /
Kojto	122:f9eeca106725	2342	#define CAN_F5R1_FB18 0x00040000U /!<Filter bit 18 /
Kojto	122:f9eeca106725	2343	#define CAN_F5R1_FB19 0x00080000U /!<Filter bit 19 /
Kojto	122:f9eeca106725	2344	#define CAN_F5R1_FB20 0x00100000U /!<Filter bit 20 /
Kojto	122:f9eeca106725	2345	#define CAN_F5R1_FB21 0x00200000U /!<Filter bit 21 /
Kojto	122:f9eeca106725	2346	#define CAN_F5R1_FB22 0x00400000U /!<Filter bit 22 /
Kojto	122:f9eeca106725	2347	#define CAN_F5R1_FB23 0x00800000U /!<Filter bit 23 /
Kojto	122:f9eeca106725	2348	#define CAN_F5R1_FB24 0x01000000U /!<Filter bit 24 /
Kojto	122:f9eeca106725	2349	#define CAN_F5R1_FB25 0x02000000U /!<Filter bit 25 /
Kojto	122:f9eeca106725	2350	#define CAN_F5R1_FB26 0x04000000U /!<Filter bit 26 /
Kojto	122:f9eeca106725	2351	#define CAN_F5R1_FB27 0x08000000U /!<Filter bit 27 /
Kojto	122:f9eeca106725	2352	#define CAN_F5R1_FB28 0x10000000U /!<Filter bit 28 /
Kojto	122:f9eeca106725	2353	#define CAN_F5R1_FB29 0x20000000U /!<Filter bit 29 /
Kojto	122:f9eeca106725	2354	#define CAN_F5R1_FB30 0x40000000U /!<Filter bit 30 /
Kojto	122:f9eeca106725	2355	#define CAN_F5R1_FB31 0x80000000U /!<Filter bit 31 /
Kojto	110:165afa46840b	2356
Kojto	110:165afa46840b	2357	/***************** Bit definition for CAN_F6R1 register *****************/
Kojto	122:f9eeca106725	2358	#define CAN_F6R1_FB0 0x00000001U /!<Filter bit 0 /
Kojto	122:f9eeca106725	2359	#define CAN_F6R1_FB1 0x00000002U /!<Filter bit 1 /
Kojto	122:f9eeca106725	2360	#define CAN_F6R1_FB2 0x00000004U /!<Filter bit 2 /
Kojto	122:f9eeca106725	2361	#define CAN_F6R1_FB3 0x00000008U /!<Filter bit 3 /
Kojto	122:f9eeca106725	2362	#define CAN_F6R1_FB4 0x00000010U /!<Filter bit 4 /
Kojto	122:f9eeca106725	2363	#define CAN_F6R1_FB5 0x00000020U /!<Filter bit 5 /
Kojto	122:f9eeca106725	2364	#define CAN_F6R1_FB6 0x00000040U /!<Filter bit 6 /
Kojto	122:f9eeca106725	2365	#define CAN_F6R1_FB7 0x00000080U /!<Filter bit 7 /
Kojto	122:f9eeca106725	2366	#define CAN_F6R1_FB8 0x00000100U /!<Filter bit 8 /
Kojto	122:f9eeca106725	2367	#define CAN_F6R1_FB9 0x00000200U /!<Filter bit 9 /
Kojto	122:f9eeca106725	2368	#define CAN_F6R1_FB10 0x00000400U /!<Filter bit 10 /
Kojto	122:f9eeca106725	2369	#define CAN_F6R1_FB11 0x00000800U /!<Filter bit 11 /
Kojto	122:f9eeca106725	2370	#define CAN_F6R1_FB12 0x00001000U /!<Filter bit 12 /
Kojto	122:f9eeca106725	2371	#define CAN_F6R1_FB13 0x00002000U /!<Filter bit 13 /
Kojto	122:f9eeca106725	2372	#define CAN_F6R1_FB14 0x00004000U /!<Filter bit 14 /
Kojto	122:f9eeca106725	2373	#define CAN_F6R1_FB15 0x00008000U /!<Filter bit 15 /
Kojto	122:f9eeca106725	2374	#define CAN_F6R1_FB16 0x00010000U /!<Filter bit 16 /
Kojto	122:f9eeca106725	2375	#define CAN_F6R1_FB17 0x00020000U /!<Filter bit 17 /
Kojto	122:f9eeca106725	2376	#define CAN_F6R1_FB18 0x00040000U /!<Filter bit 18 /
Kojto	122:f9eeca106725	2377	#define CAN_F6R1_FB19 0x00080000U /!<Filter bit 19 /
Kojto	122:f9eeca106725	2378	#define CAN_F6R1_FB20 0x00100000U /!<Filter bit 20 /
Kojto	122:f9eeca106725	2379	#define CAN_F6R1_FB21 0x00200000U /!<Filter bit 21 /
Kojto	122:f9eeca106725	2380	#define CAN_F6R1_FB22 0x00400000U /!<Filter bit 22 /
Kojto	122:f9eeca106725	2381	#define CAN_F6R1_FB23 0x00800000U /!<Filter bit 23 /
Kojto	122:f9eeca106725	2382	#define CAN_F6R1_FB24 0x01000000U /!<Filter bit 24 /
Kojto	122:f9eeca106725	2383	#define CAN_F6R1_FB25 0x02000000U /!<Filter bit 25 /
Kojto	122:f9eeca106725	2384	#define CAN_F6R1_FB26 0x04000000U /!<Filter bit 26 /
Kojto	122:f9eeca106725	2385	#define CAN_F6R1_FB27 0x08000000U /!<Filter bit 27 /
Kojto	122:f9eeca106725	2386	#define CAN_F6R1_FB28 0x10000000U /!<Filter bit 28 /
Kojto	122:f9eeca106725	2387	#define CAN_F6R1_FB29 0x20000000U /!<Filter bit 29 /
Kojto	122:f9eeca106725	2388	#define CAN_F6R1_FB30 0x40000000U /!<Filter bit 30 /
Kojto	122:f9eeca106725	2389	#define CAN_F6R1_FB31 0x80000000U /!<Filter bit 31 /
Kojto	110:165afa46840b	2390
Kojto	110:165afa46840b	2391	/***************** Bit definition for CAN_F7R1 register *****************/
Kojto	122:f9eeca106725	2392	#define CAN_F7R1_FB0 0x00000001U /!<Filter bit 0 /
Kojto	122:f9eeca106725	2393	#define CAN_F7R1_FB1 0x00000002U /!<Filter bit 1 /
Kojto	122:f9eeca106725	2394	#define CAN_F7R1_FB2 0x00000004U /!<Filter bit 2 /
Kojto	122:f9eeca106725	2395	#define CAN_F7R1_FB3 0x00000008U /!<Filter bit 3 /
Kojto	122:f9eeca106725	2396	#define CAN_F7R1_FB4 0x00000010U /!<Filter bit 4 /
Kojto	122:f9eeca106725	2397	#define CAN_F7R1_FB5 0x00000020U /!<Filter bit 5 /
Kojto	122:f9eeca106725	2398	#define CAN_F7R1_FB6 0x00000040U /!<Filter bit 6 /
Kojto	122:f9eeca106725	2399	#define CAN_F7R1_FB7 0x00000080U /!<Filter bit 7 /
Kojto	122:f9eeca106725	2400	#define CAN_F7R1_FB8 0x00000100U /!<Filter bit 8 /
Kojto	122:f9eeca106725	2401	#define CAN_F7R1_FB9 0x00000200U /!<Filter bit 9 /
Kojto	122:f9eeca106725	2402	#define CAN_F7R1_FB10 0x00000400U /!<Filter bit 10 /
Kojto	122:f9eeca106725	2403	#define CAN_F7R1_FB11 0x00000800U /!<Filter bit 11 /
Kojto	122:f9eeca106725	2404	#define CAN_F7R1_FB12 0x00001000U /!<Filter bit 12 /
Kojto	122:f9eeca106725	2405	#define CAN_F7R1_FB13 0x00002000U /!<Filter bit 13 /
Kojto	122:f9eeca106725	2406	#define CAN_F7R1_FB14 0x00004000U /!<Filter bit 14 /
Kojto	122:f9eeca106725	2407	#define CAN_F7R1_FB15 0x00008000U /!<Filter bit 15 /
Kojto	122:f9eeca106725	2408	#define CAN_F7R1_FB16 0x00010000U /!<Filter bit 16 /
Kojto	122:f9eeca106725	2409	#define CAN_F7R1_FB17 0x00020000U /!<Filter bit 17 /
Kojto	122:f9eeca106725	2410	#define CAN_F7R1_FB18 0x00040000U /!<Filter bit 18 /
Kojto	122:f9eeca106725	2411	#define CAN_F7R1_FB19 0x00080000U /!<Filter bit 19 /
Kojto	122:f9eeca106725	2412	#define CAN_F7R1_FB20 0x00100000U /!<Filter bit 20 /
Kojto	122:f9eeca106725	2413	#define CAN_F7R1_FB21 0x00200000U /!<Filter bit 21 /
Kojto	122:f9eeca106725	2414	#define CAN_F7R1_FB22 0x00400000U /!<Filter bit 22 /
Kojto	122:f9eeca106725	2415	#define CAN_F7R1_FB23 0x00800000U /!<Filter bit 23 /
Kojto	122:f9eeca106725	2416	#define CAN_F7R1_FB24 0x01000000U /!<Filter bit 24 /
Kojto	122:f9eeca106725	2417	#define CAN_F7R1_FB25 0x02000000U /!<Filter bit 25 /
Kojto	122:f9eeca106725	2418	#define CAN_F7R1_FB26 0x04000000U /!<Filter bit 26 /
Kojto	122:f9eeca106725	2419	#define CAN_F7R1_FB27 0x08000000U /!<Filter bit 27 /
Kojto	122:f9eeca106725	2420	#define CAN_F7R1_FB28 0x10000000U /!<Filter bit 28 /
Kojto	122:f9eeca106725	2421	#define CAN_F7R1_FB29 0x20000000U /!<Filter bit 29 /
Kojto	122:f9eeca106725	2422	#define CAN_F7R1_FB30 0x40000000U /!<Filter bit 30 /
Kojto	122:f9eeca106725	2423	#define CAN_F7R1_FB31 0x80000000U /!<Filter bit 31 /
Kojto	110:165afa46840b	2424
Kojto	110:165afa46840b	2425	/***************** Bit definition for CAN_F8R1 register *****************/
Kojto	122:f9eeca106725	2426	#define CAN_F8R1_FB0 0x00000001U /!<Filter bit 0 /
Kojto	122:f9eeca106725	2427	#define CAN_F8R1_FB1 0x00000002U /!<Filter bit 1 /
Kojto	122:f9eeca106725	2428	#define CAN_F8R1_FB2 0x00000004U /!<Filter bit 2 /
Kojto	122:f9eeca106725	2429	#define CAN_F8R1_FB3 0x00000008U /!<Filter bit 3 /
Kojto	122:f9eeca106725	2430	#define CAN_F8R1_FB4 0x00000010U /!<Filter bit 4 /
Kojto	122:f9eeca106725	2431	#define CAN_F8R1_FB5 0x00000020U /!<Filter bit 5 /
Kojto	122:f9eeca106725	2432	#define CAN_F8R1_FB6 0x00000040U /!<Filter bit 6 /
Kojto	122:f9eeca106725	2433	#define CAN_F8R1_FB7 0x00000080U /!<Filter bit 7 /
Kojto	122:f9eeca106725	2434	#define CAN_F8R1_FB8 0x00000100U /!<Filter bit 8 /
Kojto	122:f9eeca106725	2435	#define CAN_F8R1_FB9 0x00000200U /!<Filter bit 9 /
Kojto	122:f9eeca106725	2436	#define CAN_F8R1_FB10 0x00000400U /!<Filter bit 10 /
Kojto	122:f9eeca106725	2437	#define CAN_F8R1_FB11 0x00000800U /!<Filter bit 11 /
Kojto	122:f9eeca106725	2438	#define CAN_F8R1_FB12 0x00001000U /!<Filter bit 12 /
Kojto	122:f9eeca106725	2439	#define CAN_F8R1_FB13 0x00002000U /!<Filter bit 13 /
Kojto	122:f9eeca106725	2440	#define CAN_F8R1_FB14 0x00004000U /!<Filter bit 14 /
Kojto	122:f9eeca106725	2441	#define CAN_F8R1_FB15 0x00008000U /!<Filter bit 15 /
Kojto	122:f9eeca106725	2442	#define CAN_F8R1_FB16 0x00010000U /!<Filter bit 16 /
Kojto	122:f9eeca106725	2443	#define CAN_F8R1_FB17 0x00020000U /!<Filter bit 17 /
Kojto	122:f9eeca106725	2444	#define CAN_F8R1_FB18 0x00040000U /!<Filter bit 18 /
Kojto	122:f9eeca106725	2445	#define CAN_F8R1_FB19 0x00080000U /!<Filter bit 19 /
Kojto	122:f9eeca106725	2446	#define CAN_F8R1_FB20 0x00100000U /!<Filter bit 20 /
Kojto	122:f9eeca106725	2447	#define CAN_F8R1_FB21 0x00200000U /!<Filter bit 21 /
Kojto	122:f9eeca106725	2448	#define CAN_F8R1_FB22 0x00400000U /!<Filter bit 22 /
Kojto	122:f9eeca106725	2449	#define CAN_F8R1_FB23 0x00800000U /!<Filter bit 23 /
Kojto	122:f9eeca106725	2450	#define CAN_F8R1_FB24 0x01000000U /!<Filter bit 24 /
Kojto	122:f9eeca106725	2451	#define CAN_F8R1_FB25 0x02000000U /!<Filter bit 25 /
Kojto	122:f9eeca106725	2452	#define CAN_F8R1_FB26 0x04000000U /!<Filter bit 26 /
Kojto	122:f9eeca106725	2453	#define CAN_F8R1_FB27 0x08000000U /!<Filter bit 27 /
Kojto	122:f9eeca106725	2454	#define CAN_F8R1_FB28 0x10000000U /!<Filter bit 28 /
Kojto	122:f9eeca106725	2455	#define CAN_F8R1_FB29 0x20000000U /!<Filter bit 29 /
Kojto	122:f9eeca106725	2456	#define CAN_F8R1_FB30 0x40000000U /!<Filter bit 30 /
Kojto	122:f9eeca106725	2457	#define CAN_F8R1_FB31 0x80000000U /!<Filter bit 31 /
Kojto	110:165afa46840b	2458
Kojto	110:165afa46840b	2459	/***************** Bit definition for CAN_F9R1 register *****************/
Kojto	122:f9eeca106725	2460	#define CAN_F9R1_FB0 0x00000001U /!<Filter bit 0 /
Kojto	122:f9eeca106725	2461	#define CAN_F9R1_FB1 0x00000002U /!<Filter bit 1 /
Kojto	122:f9eeca106725	2462	#define CAN_F9R1_FB2 0x00000004U /!<Filter bit 2 /
Kojto	122:f9eeca106725	2463	#define CAN_F9R1_FB3 0x00000008U /!<Filter bit 3 /
Kojto	122:f9eeca106725	2464	#define CAN_F9R1_FB4 0x00000010U /!<Filter bit 4 /
Kojto	122:f9eeca106725	2465	#define CAN_F9R1_FB5 0x00000020U /!<Filter bit 5 /
Kojto	122:f9eeca106725	2466	#define CAN_F9R1_FB6 0x00000040U /!<Filter bit 6 /
Kojto	122:f9eeca106725	2467	#define CAN_F9R1_FB7 0x00000080U /!<Filter bit 7 /
Kojto	122:f9eeca106725	2468	#define CAN_F9R1_FB8 0x00000100U /!<Filter bit 8 /
Kojto	122:f9eeca106725	2469	#define CAN_F9R1_FB9 0x00000200U /!<Filter bit 9 /
Kojto	122:f9eeca106725	2470	#define CAN_F9R1_FB10 0x00000400U /!<Filter bit 10 /
Kojto	122:f9eeca106725	2471	#define CAN_F9R1_FB11 0x00000800U /!<Filter bit 11 /
Kojto	122:f9eeca106725	2472	#define CAN_F9R1_FB12 0x00001000U /!<Filter bit 12 /
Kojto	122:f9eeca106725	2473	#define CAN_F9R1_FB13 0x00002000U /!<Filter bit 13 /
Kojto	122:f9eeca106725	2474	#define CAN_F9R1_FB14 0x00004000U /!<Filter bit 14 /
Kojto	122:f9eeca106725	2475	#define CAN_F9R1_FB15 0x00008000U /!<Filter bit 15 /
Kojto	122:f9eeca106725	2476	#define CAN_F9R1_FB16 0x00010000U /!<Filter bit 16 /
Kojto	122:f9eeca106725	2477	#define CAN_F9R1_FB17 0x00020000U /!<Filter bit 17 /
Kojto	122:f9eeca106725	2478	#define CAN_F9R1_FB18 0x00040000U /!<Filter bit 18 /
Kojto	122:f9eeca106725	2479	#define CAN_F9R1_FB19 0x00080000U /!<Filter bit 19 /
Kojto	122:f9eeca106725	2480	#define CAN_F9R1_FB20 0x00100000U /!<Filter bit 20 /
Kojto	122:f9eeca106725	2481	#define CAN_F9R1_FB21 0x00200000U /!<Filter bit 21 /
Kojto	122:f9eeca106725	2482	#define CAN_F9R1_FB22 0x00400000U /!<Filter bit 22 /
Kojto	122:f9eeca106725	2483	#define CAN_F9R1_FB23 0x00800000U /!<Filter bit 23 /
Kojto	122:f9eeca106725	2484	#define CAN_F9R1_FB24 0x01000000U /!<Filter bit 24 /
Kojto	122:f9eeca106725	2485	#define CAN_F9R1_FB25 0x02000000U /!<Filter bit 25 /
Kojto	122:f9eeca106725	2486	#define CAN_F9R1_FB26 0x04000000U /!<Filter bit 26 /
Kojto	122:f9eeca106725	2487	#define CAN_F9R1_FB27 0x08000000U /!<Filter bit 27 /
Kojto	122:f9eeca106725	2488	#define CAN_F9R1_FB28 0x10000000U /!<Filter bit 28 /
Kojto	122:f9eeca106725	2489	#define CAN_F9R1_FB29 0x20000000U /!<Filter bit 29 /
Kojto	122:f9eeca106725	2490	#define CAN_F9R1_FB30 0x40000000U /!<Filter bit 30 /
Kojto	122:f9eeca106725	2491	#define CAN_F9R1_FB31 0x80000000U /!<Filter bit 31 /
Kojto	110:165afa46840b	2492
Kojto	110:165afa46840b	2493	/***************** Bit definition for CAN_F10R1 register ****************/
Kojto	122:f9eeca106725	2494	#define CAN_F10R1_FB0 0x00000001U /!<Filter bit 0 /
Kojto	122:f9eeca106725	2495	#define CAN_F10R1_FB1 0x00000002U /!<Filter bit 1 /
Kojto	122:f9eeca106725	2496	#define CAN_F10R1_FB2 0x00000004U /!<Filter bit 2 /
Kojto	122:f9eeca106725	2497	#define CAN_F10R1_FB3 0x00000008U /!<Filter bit 3 /
Kojto	122:f9eeca106725	2498	#define CAN_F10R1_FB4 0x00000010U /!<Filter bit 4 /
Kojto	122:f9eeca106725	2499	#define CAN_F10R1_FB5 0x00000020U /!<Filter bit 5 /
Kojto	122:f9eeca106725	2500	#define CAN_F10R1_FB6 0x00000040U /!<Filter bit 6 /
Kojto	122:f9eeca106725	2501	#define CAN_F10R1_FB7 0x00000080U /!<Filter bit 7 /
Kojto	122:f9eeca106725	2502	#define CAN_F10R1_FB8 0x00000100U /!<Filter bit 8 /
Kojto	122:f9eeca106725	2503	#define CAN_F10R1_FB9 0x00000200U /!<Filter bit 9 /
Kojto	122:f9eeca106725	2504	#define CAN_F10R1_FB10 0x00000400U /!<Filter bit 10 /
Kojto	122:f9eeca106725	2505	#define CAN_F10R1_FB11 0x00000800U /!<Filter bit 11 /
Kojto	122:f9eeca106725	2506	#define CAN_F10R1_FB12 0x00001000U /!<Filter bit 12 /
Kojto	122:f9eeca106725	2507	#define CAN_F10R1_FB13 0x00002000U /!<Filter bit 13 /
Kojto	122:f9eeca106725	2508	#define CAN_F10R1_FB14 0x00004000U /!<Filter bit 14 /
Kojto	122:f9eeca106725	2509	#define CAN_F10R1_FB15 0x00008000U /!<Filter bit 15 /
Kojto	122:f9eeca106725	2510	#define CAN_F10R1_FB16 0x00010000U /!<Filter bit 16 /
Kojto	122:f9eeca106725	2511	#define CAN_F10R1_FB17 0x00020000U /!<Filter bit 17 /
Kojto	122:f9eeca106725	2512	#define CAN_F10R1_FB18 0x00040000U /!<Filter bit 18 /
Kojto	122:f9eeca106725	2513	#define CAN_F10R1_FB19 0x00080000U /!<Filter bit 19 /
Kojto	122:f9eeca106725	2514	#define CAN_F10R1_FB20 0x00100000U /!<Filter bit 20 /
Kojto	122:f9eeca106725	2515	#define CAN_F10R1_FB21 0x00200000U /!<Filter bit 21 /
Kojto	122:f9eeca106725	2516	#define CAN_F10R1_FB22 0x00400000U /!<Filter bit 22 /
Kojto	122:f9eeca106725	2517	#define CAN_F10R1_FB23 0x00800000U /!<Filter bit 23 /
Kojto	122:f9eeca106725	2518	#define CAN_F10R1_FB24 0x01000000U /!<Filter bit 24 /
Kojto	122:f9eeca106725	2519	#define CAN_F10R1_FB25 0x02000000U /!<Filter bit 25 /
Kojto	122:f9eeca106725	2520	#define CAN_F10R1_FB26 0x04000000U /!<Filter bit 26 /
Kojto	122:f9eeca106725	2521	#define CAN_F10R1_FB27 0x08000000U /!<Filter bit 27 /
Kojto	122:f9eeca106725	2522	#define CAN_F10R1_FB28 0x10000000U /!<Filter bit 28 /
Kojto	122:f9eeca106725	2523	#define CAN_F10R1_FB29 0x20000000U /!<Filter bit 29 /
Kojto	122:f9eeca106725	2524	#define CAN_F10R1_FB30 0x40000000U /!<Filter bit 30 /
Kojto	122:f9eeca106725	2525	#define CAN_F10R1_FB31 0x80000000U /!<Filter bit 31 /
Kojto	110:165afa46840b	2526
Kojto	110:165afa46840b	2527	/***************** Bit definition for CAN_F11R1 register ****************/
Kojto	122:f9eeca106725	2528	#define CAN_F11R1_FB0 0x00000001U /!<Filter bit 0 /
Kojto	122:f9eeca106725	2529	#define CAN_F11R1_FB1 0x00000002U /!<Filter bit 1 /
Kojto	122:f9eeca106725	2530	#define CAN_F11R1_FB2 0x00000004U /!<Filter bit 2 /
Kojto	122:f9eeca106725	2531	#define CAN_F11R1_FB3 0x00000008U /!<Filter bit 3 /
Kojto	122:f9eeca106725	2532	#define CAN_F11R1_FB4 0x00000010U /!<Filter bit 4 /
Kojto	122:f9eeca106725	2533	#define CAN_F11R1_FB5 0x00000020U /!<Filter bit 5 /
Kojto	122:f9eeca106725	2534	#define CAN_F11R1_FB6 0x00000040U /!<Filter bit 6 /
Kojto	122:f9eeca106725	2535	#define CAN_F11R1_FB7 0x00000080U /!<Filter bit 7 /
Kojto	122:f9eeca106725	2536	#define CAN_F11R1_FB8 0x00000100U /!<Filter bit 8 /
Kojto	122:f9eeca106725	2537	#define CAN_F11R1_FB9 0x00000200U /!<Filter bit 9 /
Kojto	122:f9eeca106725	2538	#define CAN_F11R1_FB10 0x00000400U /!<Filter bit 10 /
Kojto	122:f9eeca106725	2539	#define CAN_F11R1_FB11 0x00000800U /!<Filter bit 11 /
Kojto	122:f9eeca106725	2540	#define CAN_F11R1_FB12 0x00001000U /!<Filter bit 12 /
Kojto	122:f9eeca106725	2541	#define CAN_F11R1_FB13 0x00002000U /!<Filter bit 13 /
Kojto	122:f9eeca106725	2542	#define CAN_F11R1_FB14 0x00004000U /!<Filter bit 14 /
Kojto	122:f9eeca106725	2543	#define CAN_F11R1_FB15 0x00008000U /!<Filter bit 15 /
Kojto	122:f9eeca106725	2544	#define CAN_F11R1_FB16 0x00010000U /!<Filter bit 16 /
Kojto	122:f9eeca106725	2545	#define CAN_F11R1_FB17 0x00020000U /!<Filter bit 17 /
Kojto	122:f9eeca106725	2546	#define CAN_F11R1_FB18 0x00040000U /!<Filter bit 18 /
Kojto	122:f9eeca106725	2547	#define CAN_F11R1_FB19 0x00080000U /!<Filter bit 19 /
Kojto	122:f9eeca106725	2548	#define CAN_F11R1_FB20 0x00100000U /!<Filter bit 20 /
Kojto	122:f9eeca106725	2549	#define CAN_F11R1_FB21 0x00200000U /!<Filter bit 21 /
Kojto	122:f9eeca106725	2550	#define CAN_F11R1_FB22 0x00400000U /!<Filter bit 22 /
Kojto	122:f9eeca106725	2551	#define CAN_F11R1_FB23 0x00800000U /!<Filter bit 23 /
Kojto	122:f9eeca106725	2552	#define CAN_F11R1_FB24 0x01000000U /!<Filter bit 24 /
Kojto	122:f9eeca106725	2553	#define CAN_F11R1_FB25 0x02000000U /!<Filter bit 25 /
Kojto	122:f9eeca106725	2554	#define CAN_F11R1_FB26 0x04000000U /!<Filter bit 26 /
Kojto	122:f9eeca106725	2555	#define CAN_F11R1_FB27 0x08000000U /!<Filter bit 27 /
Kojto	122:f9eeca106725	2556	#define CAN_F11R1_FB28 0x10000000U /!<Filter bit 28 /
Kojto	122:f9eeca106725	2557	#define CAN_F11R1_FB29 0x20000000U /!<Filter bit 29 /
Kojto	122:f9eeca106725	2558	#define CAN_F11R1_FB30 0x40000000U /!<Filter bit 30 /
Kojto	122:f9eeca106725	2559	#define CAN_F11R1_FB31 0x80000000U /!<Filter bit 31 /
Kojto	110:165afa46840b	2560
Kojto	110:165afa46840b	2561	/***************** Bit definition for CAN_F12R1 register ****************/
Kojto	122:f9eeca106725	2562	#define CAN_F12R1_FB0 0x00000001U /!<Filter bit 0 /
Kojto	122:f9eeca106725	2563	#define CAN_F12R1_FB1 0x00000002U /!<Filter bit 1 /
Kojto	122:f9eeca106725	2564	#define CAN_F12R1_FB2 0x00000004U /!<Filter bit 2 /
Kojto	122:f9eeca106725	2565	#define CAN_F12R1_FB3 0x00000008U /!<Filter bit 3 /
Kojto	122:f9eeca106725	2566	#define CAN_F12R1_FB4 0x00000010U /!<Filter bit 4 /
Kojto	122:f9eeca106725	2567	#define CAN_F12R1_FB5 0x00000020U /!<Filter bit 5 /
Kojto	122:f9eeca106725	2568	#define CAN_F12R1_FB6 0x00000040U /!<Filter bit 6 /
Kojto	122:f9eeca106725	2569	#define CAN_F12R1_FB7 0x00000080U /!<Filter bit 7 /
Kojto	122:f9eeca106725	2570	#define CAN_F12R1_FB8 0x00000100U /!<Filter bit 8 /
Kojto	122:f9eeca106725	2571	#define CAN_F12R1_FB9 0x00000200U /!<Filter bit 9 /
Kojto	122:f9eeca106725	2572	#define CAN_F12R1_FB10 0x00000400U /!<Filter bit 10 /
Kojto	122:f9eeca106725	2573	#define CAN_F12R1_FB11 0x00000800U /!<Filter bit 11 /
Kojto	122:f9eeca106725	2574	#define CAN_F12R1_FB12 0x00001000U /!<Filter bit 12 /
Kojto	122:f9eeca106725	2575	#define CAN_F12R1_FB13 0x00002000U /!<Filter bit 13 /
Kojto	122:f9eeca106725	2576	#define CAN_F12R1_FB14 0x00004000U /!<Filter bit 14 /
Kojto	122:f9eeca106725	2577	#define CAN_F12R1_FB15 0x00008000U /!<Filter bit 15 /
Kojto	122:f9eeca106725	2578	#define CAN_F12R1_FB16 0x00010000U /!<Filter bit 16 /
Kojto	122:f9eeca106725	2579	#define CAN_F12R1_FB17 0x00020000U /!<Filter bit 17 /
Kojto	122:f9eeca106725	2580	#define CAN_F12R1_FB18 0x00040000U /!<Filter bit 18 /
Kojto	122:f9eeca106725	2581	#define CAN_F12R1_FB19 0x00080000U /!<Filter bit 19 /
Kojto	122:f9eeca106725	2582	#define CAN_F12R1_FB20 0x00100000U /!<Filter bit 20 /
Kojto	122:f9eeca106725	2583	#define CAN_F12R1_FB21 0x00200000U /!<Filter bit 21 /
Kojto	122:f9eeca106725	2584	#define CAN_F12R1_FB22 0x00400000U /!<Filter bit 22 /
Kojto	122:f9eeca106725	2585	#define CAN_F12R1_FB23 0x00800000U /!<Filter bit 23 /
Kojto	122:f9eeca106725	2586	#define CAN_F12R1_FB24 0x01000000U /!<Filter bit 24 /
Kojto	122:f9eeca106725	2587	#define CAN_F12R1_FB25 0x02000000U /!<Filter bit 25 /
Kojto	122:f9eeca106725	2588	#define CAN_F12R1_FB26 0x04000000U /!<Filter bit 26 /
Kojto	122:f9eeca106725	2589	#define CAN_F12R1_FB27 0x08000000U /!<Filter bit 27 /
Kojto	122:f9eeca106725	2590	#define CAN_F12R1_FB28 0x10000000U /!<Filter bit 28 /
Kojto	122:f9eeca106725	2591	#define CAN_F12R1_FB29 0x20000000U /!<Filter bit 29 /
Kojto	122:f9eeca106725	2592	#define CAN_F12R1_FB30 0x40000000U /!<Filter bit 30 /
Kojto	122:f9eeca106725	2593	#define CAN_F12R1_FB31 0x80000000U /!<Filter bit 31 /
Kojto	110:165afa46840b	2594
Kojto	110:165afa46840b	2595	/***************** Bit definition for CAN_F13R1 register ****************/
Kojto	122:f9eeca106725	2596	#define CAN_F13R1_FB0 0x00000001U /!<Filter bit 0 /
Kojto	122:f9eeca106725	2597	#define CAN_F13R1_FB1 0x00000002U /!<Filter bit 1 /
Kojto	122:f9eeca106725	2598	#define CAN_F13R1_FB2 0x00000004U /!<Filter bit 2 /
Kojto	122:f9eeca106725	2599	#define CAN_F13R1_FB3 0x00000008U /!<Filter bit 3 /
Kojto	122:f9eeca106725	2600	#define CAN_F13R1_FB4 0x00000010U /!<Filter bit 4 /
Kojto	122:f9eeca106725	2601	#define CAN_F13R1_FB5 0x00000020U /!<Filter bit 5 /
Kojto	122:f9eeca106725	2602	#define CAN_F13R1_FB6 0x00000040U /!<Filter bit 6 /
Kojto	122:f9eeca106725	2603	#define CAN_F13R1_FB7 0x00000080U /!<Filter bit 7 /
Kojto	122:f9eeca106725	2604	#define CAN_F13R1_FB8 0x00000100U /!<Filter bit 8 /
Kojto	122:f9eeca106725	2605	#define CAN_F13R1_FB9 0x00000200U /!<Filter bit 9 /
Kojto	122:f9eeca106725	2606	#define CAN_F13R1_FB10 0x00000400U /!<Filter bit 10 /
Kojto	122:f9eeca106725	2607	#define CAN_F13R1_FB11 0x00000800U /!<Filter bit 11 /
Kojto	122:f9eeca106725	2608	#define CAN_F13R1_FB12 0x00001000U /!<Filter bit 12 /
Kojto	122:f9eeca106725	2609	#define CAN_F13R1_FB13 0x00002000U /!<Filter bit 13 /
Kojto	122:f9eeca106725	2610	#define CAN_F13R1_FB14 0x00004000U /!<Filter bit 14 /
Kojto	122:f9eeca106725	2611	#define CAN_F13R1_FB15 0x00008000U /!<Filter bit 15 /
Kojto	122:f9eeca106725	2612	#define CAN_F13R1_FB16 0x00010000U /!<Filter bit 16 /
Kojto	122:f9eeca106725	2613	#define CAN_F13R1_FB17 0x00020000U /!<Filter bit 17 /
Kojto	122:f9eeca106725	2614	#define CAN_F13R1_FB18 0x00040000U /!<Filter bit 18 /
Kojto	122:f9eeca106725	2615	#define CAN_F13R1_FB19 0x00080000U /!<Filter bit 19 /
Kojto	122:f9eeca106725	2616	#define CAN_F13R1_FB20 0x00100000U /!<Filter bit 20 /
Kojto	122:f9eeca106725	2617	#define CAN_F13R1_FB21 0x00200000U /!<Filter bit 21 /
Kojto	122:f9eeca106725	2618	#define CAN_F13R1_FB22 0x00400000U /!<Filter bit 22 /
Kojto	122:f9eeca106725	2619	#define CAN_F13R1_FB23 0x00800000U /!<Filter bit 23 /
Kojto	122:f9eeca106725	2620	#define CAN_F13R1_FB24 0x01000000U /!<Filter bit 24 /
Kojto	122:f9eeca106725	2621	#define CAN_F13R1_FB25 0x02000000U /!<Filter bit 25 /
Kojto	122:f9eeca106725	2622	#define CAN_F13R1_FB26 0x04000000U /!<Filter bit 26 /
Kojto	122:f9eeca106725	2623	#define CAN_F13R1_FB27 0x08000000U /!<Filter bit 27 /
Kojto	122:f9eeca106725	2624	#define CAN_F13R1_FB28 0x10000000U /!<Filter bit 28 /
Kojto	122:f9eeca106725	2625	#define CAN_F13R1_FB29 0x20000000U /!<Filter bit 29 /
Kojto	122:f9eeca106725	2626	#define CAN_F13R1_FB30 0x40000000U /!<Filter bit 30 /
Kojto	122:f9eeca106725	2627	#define CAN_F13R1_FB31 0x80000000U /!<Filter bit 31 /
Kojto	110:165afa46840b	2628
Kojto	110:165afa46840b	2629	/***************** Bit definition for CAN_F0R2 register *****************/
Kojto	122:f9eeca106725	2630	#define CAN_F0R2_FB0 0x00000001U /!<Filter bit 0 /
Kojto	122:f9eeca106725	2631	#define CAN_F0R2_FB1 0x00000002U /!<Filter bit 1 /
Kojto	122:f9eeca106725	2632	#define CAN_F0R2_FB2 0x00000004U /!<Filter bit 2 /
Kojto	122:f9eeca106725	2633	#define CAN_F0R2_FB3 0x00000008U /!<Filter bit 3 /
Kojto	122:f9eeca106725	2634	#define CAN_F0R2_FB4 0x00000010U /!<Filter bit 4 /
Kojto	122:f9eeca106725	2635	#define CAN_F0R2_FB5 0x00000020U /!<Filter bit 5 /
Kojto	122:f9eeca106725	2636	#define CAN_F0R2_FB6 0x00000040U /!<Filter bit 6 /
Kojto	122:f9eeca106725	2637	#define CAN_F0R2_FB7 0x00000080U /!<Filter bit 7 /
Kojto	122:f9eeca106725	2638	#define CAN_F0R2_FB8 0x00000100U /!<Filter bit 8 /
Kojto	122:f9eeca106725	2639	#define CAN_F0R2_FB9 0x00000200U /!<Filter bit 9 /
Kojto	122:f9eeca106725	2640	#define CAN_F0R2_FB10 0x00000400U /!<Filter bit 10 /
Kojto	122:f9eeca106725	2641	#define CAN_F0R2_FB11 0x00000800U /!<Filter bit 11 /
Kojto	122:f9eeca106725	2642	#define CAN_F0R2_FB12 0x00001000U /!<Filter bit 12 /
Kojto	122:f9eeca106725	2643	#define CAN_F0R2_FB13 0x00002000U /!<Filter bit 13 /
Kojto	122:f9eeca106725	2644	#define CAN_F0R2_FB14 0x00004000U /!<Filter bit 14 /
Kojto	122:f9eeca106725	2645	#define CAN_F0R2_FB15 0x00008000U /!<Filter bit 15 /
Kojto	122:f9eeca106725	2646	#define CAN_F0R2_FB16 0x00010000U /!<Filter bit 16 /
Kojto	122:f9eeca106725	2647	#define CAN_F0R2_FB17 0x00020000U /!<Filter bit 17 /
Kojto	122:f9eeca106725	2648	#define CAN_F0R2_FB18 0x00040000U /!<Filter bit 18 /
Kojto	122:f9eeca106725	2649	#define CAN_F0R2_FB19 0x00080000U /!<Filter bit 19 /
Kojto	122:f9eeca106725	2650	#define CAN_F0R2_FB20 0x00100000U /!<Filter bit 20 /
Kojto	122:f9eeca106725	2651	#define CAN_F0R2_FB21 0x00200000U /!<Filter bit 21 /
Kojto	122:f9eeca106725	2652	#define CAN_F0R2_FB22 0x00400000U /!<Filter bit 22 /
Kojto	122:f9eeca106725	2653	#define CAN_F0R2_FB23 0x00800000U /!<Filter bit 23 /
Kojto	122:f9eeca106725	2654	#define CAN_F0R2_FB24 0x01000000U /!<Filter bit 24 /
Kojto	122:f9eeca106725	2655	#define CAN_F0R2_FB25 0x02000000U /!<Filter bit 25 /
Kojto	122:f9eeca106725	2656	#define CAN_F0R2_FB26 0x04000000U /!<Filter bit 26 /
Kojto	122:f9eeca106725	2657	#define CAN_F0R2_FB27 0x08000000U /!<Filter bit 27 /
Kojto	122:f9eeca106725	2658	#define CAN_F0R2_FB28 0x10000000U /!<Filter bit 28 /
Kojto	122:f9eeca106725	2659	#define CAN_F0R2_FB29 0x20000000U /!<Filter bit 29 /
Kojto	122:f9eeca106725	2660	#define CAN_F0R2_FB30 0x40000000U /!<Filter bit 30 /
Kojto	122:f9eeca106725	2661	#define CAN_F0R2_FB31 0x80000000U /!<Filter bit 31 /
Kojto	110:165afa46840b	2662
Kojto	110:165afa46840b	2663	/***************** Bit definition for CAN_F1R2 register *****************/
Kojto	122:f9eeca106725	2664	#define CAN_F1R2_FB0 0x00000001U /!<Filter bit 0 /
Kojto	122:f9eeca106725	2665	#define CAN_F1R2_FB1 0x00000002U /!<Filter bit 1 /
Kojto	122:f9eeca106725	2666	#define CAN_F1R2_FB2 0x00000004U /!<Filter bit 2 /
Kojto	122:f9eeca106725	2667	#define CAN_F1R2_FB3 0x00000008U /!<Filter bit 3 /
Kojto	122:f9eeca106725	2668	#define CAN_F1R2_FB4 0x00000010U /!<Filter bit 4 /
Kojto	122:f9eeca106725	2669	#define CAN_F1R2_FB5 0x00000020U /!<Filter bit 5 /
Kojto	122:f9eeca106725	2670	#define CAN_F1R2_FB6 0x00000040U /!<Filter bit 6 /
Kojto	122:f9eeca106725	2671	#define CAN_F1R2_FB7 0x00000080U /!<Filter bit 7 /
Kojto	122:f9eeca106725	2672	#define CAN_F1R2_FB8 0x00000100U /!<Filter bit 8 /
Kojto	122:f9eeca106725	2673	#define CAN_F1R2_FB9 0x00000200U /!<Filter bit 9 /
Kojto	122:f9eeca106725	2674	#define CAN_F1R2_FB10 0x00000400U /!<Filter bit 10 /
Kojto	122:f9eeca106725	2675	#define CAN_F1R2_FB11 0x00000800U /!<Filter bit 11 /
Kojto	122:f9eeca106725	2676	#define CAN_F1R2_FB12 0x00001000U /!<Filter bit 12 /
Kojto	122:f9eeca106725	2677	#define CAN_F1R2_FB13 0x00002000U /!<Filter bit 13 /
Kojto	122:f9eeca106725	2678	#define CAN_F1R2_FB14 0x00004000U /!<Filter bit 14 /
Kojto	122:f9eeca106725	2679	#define CAN_F1R2_FB15 0x00008000U /!<Filter bit 15 /
Kojto	122:f9eeca106725	2680	#define CAN_F1R2_FB16 0x00010000U /!<Filter bit 16 /
Kojto	122:f9eeca106725	2681	#define CAN_F1R2_FB17 0x00020000U /!<Filter bit 17 /
Kojto	122:f9eeca106725	2682	#define CAN_F1R2_FB18 0x00040000U /!<Filter bit 18 /
Kojto	122:f9eeca106725	2683	#define CAN_F1R2_FB19 0x00080000U /!<Filter bit 19 /
Kojto	122:f9eeca106725	2684	#define CAN_F1R2_FB20 0x00100000U /!<Filter bit 20 /
Kojto	122:f9eeca106725	2685	#define CAN_F1R2_FB21 0x00200000U /!<Filter bit 21 /
Kojto	122:f9eeca106725	2686	#define CAN_F1R2_FB22 0x00400000U /!<Filter bit 22 /
Kojto	122:f9eeca106725	2687	#define CAN_F1R2_FB23 0x00800000U /!<Filter bit 23 /
Kojto	122:f9eeca106725	2688	#define CAN_F1R2_FB24 0x01000000U /!<Filter bit 24 /
Kojto	122:f9eeca106725	2689	#define CAN_F1R2_FB25 0x02000000U /!<Filter bit 25 /
Kojto	122:f9eeca106725	2690	#define CAN_F1R2_FB26 0x04000000U /!<Filter bit 26 /
Kojto	122:f9eeca106725	2691	#define CAN_F1R2_FB27 0x08000000U /!<Filter bit 27 /
Kojto	122:f9eeca106725	2692	#define CAN_F1R2_FB28 0x10000000U /!<Filter bit 28 /
Kojto	122:f9eeca106725	2693	#define CAN_F1R2_FB29 0x20000000U /!<Filter bit 29 /
Kojto	122:f9eeca106725	2694	#define CAN_F1R2_FB30 0x40000000U /!<Filter bit 30 /
Kojto	122:f9eeca106725	2695	#define CAN_F1R2_FB31 0x80000000U /!<Filter bit 31 /
Kojto	110:165afa46840b	2696
Kojto	110:165afa46840b	2697	/***************** Bit definition for CAN_F2R2 register *****************/
Kojto	122:f9eeca106725	2698	#define CAN_F2R2_FB0 0x00000001U /!<Filter bit 0 /
Kojto	122:f9eeca106725	2699	#define CAN_F2R2_FB1 0x00000002U /!<Filter bit 1 /
Kojto	122:f9eeca106725	2700	#define CAN_F2R2_FB2 0x00000004U /!<Filter bit 2 /
Kojto	122:f9eeca106725	2701	#define CAN_F2R2_FB3 0x00000008U /!<Filter bit 3 /
Kojto	122:f9eeca106725	2702	#define CAN_F2R2_FB4 0x00000010U /!<Filter bit 4 /
Kojto	122:f9eeca106725	2703	#define CAN_F2R2_FB5 0x00000020U /!<Filter bit 5 /
Kojto	122:f9eeca106725	2704	#define CAN_F2R2_FB6 0x00000040U /!<Filter bit 6 /
Kojto	122:f9eeca106725	2705	#define CAN_F2R2_FB7 0x00000080U /!<Filter bit 7 /
Kojto	122:f9eeca106725	2706	#define CAN_F2R2_FB8 0x00000100U /!<Filter bit 8 /
Kojto	122:f9eeca106725	2707	#define CAN_F2R2_FB9 0x00000200U /!<Filter bit 9 /
Kojto	122:f9eeca106725	2708	#define CAN_F2R2_FB10 0x00000400U /!<Filter bit 10 /
Kojto	122:f9eeca106725	2709	#define CAN_F2R2_FB11 0x00000800U /!<Filter bit 11 /
Kojto	122:f9eeca106725	2710	#define CAN_F2R2_FB12 0x00001000U /!<Filter bit 12 /
Kojto	122:f9eeca106725	2711	#define CAN_F2R2_FB13 0x00002000U /!<Filter bit 13 /
Kojto	122:f9eeca106725	2712	#define CAN_F2R2_FB14 0x00004000U /!<Filter bit 14 /
Kojto	122:f9eeca106725	2713	#define CAN_F2R2_FB15 0x00008000U /!<Filter bit 15 /
Kojto	122:f9eeca106725	2714	#define CAN_F2R2_FB16 0x00010000U /!<Filter bit 16 /
Kojto	122:f9eeca106725	2715	#define CAN_F2R2_FB17 0x00020000U /!<Filter bit 17 /
Kojto	122:f9eeca106725	2716	#define CAN_F2R2_FB18 0x00040000U /!<Filter bit 18 /
Kojto	122:f9eeca106725	2717	#define CAN_F2R2_FB19 0x00080000U /!<Filter bit 19 /
Kojto	122:f9eeca106725	2718	#define CAN_F2R2_FB20 0x00100000U /!<Filter bit 20 /
Kojto	122:f9eeca106725	2719	#define CAN_F2R2_FB21 0x00200000U /!<Filter bit 21 /
Kojto	122:f9eeca106725	2720	#define CAN_F2R2_FB22 0x00400000U /!<Filter bit 22 /
Kojto	122:f9eeca106725	2721	#define CAN_F2R2_FB23 0x00800000U /!<Filter bit 23 /
Kojto	122:f9eeca106725	2722	#define CAN_F2R2_FB24 0x01000000U /!<Filter bit 24 /
Kojto	122:f9eeca106725	2723	#define CAN_F2R2_FB25 0x02000000U /!<Filter bit 25 /
Kojto	122:f9eeca106725	2724	#define CAN_F2R2_FB26 0x04000000U /!<Filter bit 26 /
Kojto	122:f9eeca106725	2725	#define CAN_F2R2_FB27 0x08000000U /!<Filter bit 27 /
Kojto	122:f9eeca106725	2726	#define CAN_F2R2_FB28 0x10000000U /!<Filter bit 28 /
Kojto	122:f9eeca106725	2727	#define CAN_F2R2_FB29 0x20000000U /!<Filter bit 29 /
Kojto	122:f9eeca106725	2728	#define CAN_F2R2_FB30 0x40000000U /!<Filter bit 30 /
Kojto	122:f9eeca106725	2729	#define CAN_F2R2_FB31 0x80000000U /!<Filter bit 31 /
Kojto	110:165afa46840b	2730
Kojto	110:165afa46840b	2731	/***************** Bit definition for CAN_F3R2 register *****************/
Kojto	122:f9eeca106725	2732	#define CAN_F3R2_FB0 0x00000001U /!<Filter bit 0 /
Kojto	122:f9eeca106725	2733	#define CAN_F3R2_FB1 0x00000002U /!<Filter bit 1 /
Kojto	122:f9eeca106725	2734	#define CAN_F3R2_FB2 0x00000004U /!<Filter bit 2 /
Kojto	122:f9eeca106725	2735	#define CAN_F3R2_FB3 0x00000008U /!<Filter bit 3 /
Kojto	122:f9eeca106725	2736	#define CAN_F3R2_FB4 0x00000010U /!<Filter bit 4 /
Kojto	122:f9eeca106725	2737	#define CAN_F3R2_FB5 0x00000020U /!<Filter bit 5 /
Kojto	122:f9eeca106725	2738	#define CAN_F3R2_FB6 0x00000040U /!<Filter bit 6 /
Kojto	122:f9eeca106725	2739	#define CAN_F3R2_FB7 0x00000080U /!<Filter bit 7 /
Kojto	122:f9eeca106725	2740	#define CAN_F3R2_FB8 0x00000100U /!<Filter bit 8 /
Kojto	122:f9eeca106725	2741	#define CAN_F3R2_FB9 0x00000200U /!<Filter bit 9 /
Kojto	122:f9eeca106725	2742	#define CAN_F3R2_FB10 0x00000400U /!<Filter bit 10 /
Kojto	122:f9eeca106725	2743	#define CAN_F3R2_FB11 0x00000800U /!<Filter bit 11 /
Kojto	122:f9eeca106725	2744	#define CAN_F3R2_FB12 0x00001000U /!<Filter bit 12 /
Kojto	122:f9eeca106725	2745	#define CAN_F3R2_FB13 0x00002000U /!<Filter bit 13 /
Kojto	122:f9eeca106725	2746	#define CAN_F3R2_FB14 0x00004000U /!<Filter bit 14 /
Kojto	122:f9eeca106725	2747	#define CAN_F3R2_FB15 0x00008000U /!<Filter bit 15 /
Kojto	122:f9eeca106725	2748	#define CAN_F3R2_FB16 0x00010000U /!<Filter bit 16 /
Kojto	122:f9eeca106725	2749	#define CAN_F3R2_FB17 0x00020000U /!<Filter bit 17 /
Kojto	122:f9eeca106725	2750	#define CAN_F3R2_FB18 0x00040000U /!<Filter bit 18 /
Kojto	122:f9eeca106725	2751	#define CAN_F3R2_FB19 0x00080000U /!<Filter bit 19 /
Kojto	122:f9eeca106725	2752	#define CAN_F3R2_FB20 0x00100000U /!<Filter bit 20 /
Kojto	122:f9eeca106725	2753	#define CAN_F3R2_FB21 0x00200000U /!<Filter bit 21 /
Kojto	122:f9eeca106725	2754	#define CAN_F3R2_FB22 0x00400000U /!<Filter bit 22 /
Kojto	122:f9eeca106725	2755	#define CAN_F3R2_FB23 0x00800000U /!<Filter bit 23 /
Kojto	122:f9eeca106725	2756	#define CAN_F3R2_FB24 0x01000000U /!<Filter bit 24 /
Kojto	122:f9eeca106725	2757	#define CAN_F3R2_FB25 0x02000000U /!<Filter bit 25 /
Kojto	122:f9eeca106725	2758	#define CAN_F3R2_FB26 0x04000000U /!<Filter bit 26 /
Kojto	122:f9eeca106725	2759	#define CAN_F3R2_FB27 0x08000000U /!<Filter bit 27 /
Kojto	122:f9eeca106725	2760	#define CAN_F3R2_FB28 0x10000000U /!<Filter bit 28 /
Kojto	122:f9eeca106725	2761	#define CAN_F3R2_FB29 0x20000000U /!<Filter bit 29 /
Kojto	122:f9eeca106725	2762	#define CAN_F3R2_FB30 0x40000000U /!<Filter bit 30 /
Kojto	122:f9eeca106725	2763	#define CAN_F3R2_FB31 0x80000000U /!<Filter bit 31 /
Kojto	110:165afa46840b	2764
Kojto	110:165afa46840b	2765	/***************** Bit definition for CAN_F4R2 register *****************/
Kojto	122:f9eeca106725	2766	#define CAN_F4R2_FB0 0x00000001U /!<Filter bit 0 /
Kojto	122:f9eeca106725	2767	#define CAN_F4R2_FB1 0x00000002U /!<Filter bit 1 /
Kojto	122:f9eeca106725	2768	#define CAN_F4R2_FB2 0x00000004U /!<Filter bit 2 /
Kojto	122:f9eeca106725	2769	#define CAN_F4R2_FB3 0x00000008U /!<Filter bit 3 /
Kojto	122:f9eeca106725	2770	#define CAN_F4R2_FB4 0x00000010U /!<Filter bit 4 /
Kojto	122:f9eeca106725	2771	#define CAN_F4R2_FB5 0x00000020U /!<Filter bit 5 /
Kojto	122:f9eeca106725	2772	#define CAN_F4R2_FB6 0x00000040U /!<Filter bit 6 /
Kojto	122:f9eeca106725	2773	#define CAN_F4R2_FB7 0x00000080U /!<Filter bit 7 /
Kojto	122:f9eeca106725	2774	#define CAN_F4R2_FB8 0x00000100U /!<Filter bit 8 /
Kojto	122:f9eeca106725	2775	#define CAN_F4R2_FB9 0x00000200U /!<Filter bit 9 /
Kojto	122:f9eeca106725	2776	#define CAN_F4R2_FB10 0x00000400U /!<Filter bit 10 /
Kojto	122:f9eeca106725	2777	#define CAN_F4R2_FB11 0x00000800U /!<Filter bit 11 /
Kojto	122:f9eeca106725	2778	#define CAN_F4R2_FB12 0x00001000U /!<Filter bit 12 /
Kojto	122:f9eeca106725	2779	#define CAN_F4R2_FB13 0x00002000U /!<Filter bit 13 /
Kojto	122:f9eeca106725	2780	#define CAN_F4R2_FB14 0x00004000U /!<Filter bit 14 /
Kojto	122:f9eeca106725	2781	#define CAN_F4R2_FB15 0x00008000U /!<Filter bit 15 /
Kojto	122:f9eeca106725	2782	#define CAN_F4R2_FB16 0x00010000U /!<Filter bit 16 /
Kojto	122:f9eeca106725	2783	#define CAN_F4R2_FB17 0x00020000U /!<Filter bit 17 /
Kojto	122:f9eeca106725	2784	#define CAN_F4R2_FB18 0x00040000U /!<Filter bit 18 /
Kojto	122:f9eeca106725	2785	#define CAN_F4R2_FB19 0x00080000U /!<Filter bit 19 /
Kojto	122:f9eeca106725	2786	#define CAN_F4R2_FB20 0x00100000U /!<Filter bit 20 /
Kojto	122:f9eeca106725	2787	#define CAN_F4R2_FB21 0x00200000U /!<Filter bit 21 /
Kojto	122:f9eeca106725	2788	#define CAN_F4R2_FB22 0x00400000U /!<Filter bit 22 /
Kojto	122:f9eeca106725	2789	#define CAN_F4R2_FB23 0x00800000U /!<Filter bit 23 /
Kojto	122:f9eeca106725	2790	#define CAN_F4R2_FB24 0x01000000U /!<Filter bit 24 /
Kojto	122:f9eeca106725	2791	#define CAN_F4R2_FB25 0x02000000U /!<Filter bit 25 /
Kojto	122:f9eeca106725	2792	#define CAN_F4R2_FB26 0x04000000U /!<Filter bit 26 /
Kojto	122:f9eeca106725	2793	#define CAN_F4R2_FB27 0x08000000U /!<Filter bit 27 /
Kojto	122:f9eeca106725	2794	#define CAN_F4R2_FB28 0x10000000U /!<Filter bit 28 /
Kojto	122:f9eeca106725	2795	#define CAN_F4R2_FB29 0x20000000U /!<Filter bit 29 /
Kojto	122:f9eeca106725	2796	#define CAN_F4R2_FB30 0x40000000U /!<Filter bit 30 /
Kojto	122:f9eeca106725	2797	#define CAN_F4R2_FB31 0x80000000U /!<Filter bit 31 /
Kojto	110:165afa46840b	2798
Kojto	110:165afa46840b	2799	/***************** Bit definition for CAN_F5R2 register *****************/
Kojto	122:f9eeca106725	2800	#define CAN_F5R2_FB0 0x00000001U /!<Filter bit 0 /
Kojto	122:f9eeca106725	2801	#define CAN_F5R2_FB1 0x00000002U /!<Filter bit 1 /
Kojto	122:f9eeca106725	2802	#define CAN_F5R2_FB2 0x00000004U /!<Filter bit 2 /
Kojto	122:f9eeca106725	2803	#define CAN_F5R2_FB3 0x00000008U /!<Filter bit 3 /
Kojto	122:f9eeca106725	2804	#define CAN_F5R2_FB4 0x00000010U /!<Filter bit 4 /
Kojto	122:f9eeca106725	2805	#define CAN_F5R2_FB5 0x00000020U /!<Filter bit 5 /
Kojto	122:f9eeca106725	2806	#define CAN_F5R2_FB6 0x00000040U /!<Filter bit 6 /
Kojto	122:f9eeca106725	2807	#define CAN_F5R2_FB7 0x00000080U /!<Filter bit 7 /
Kojto	122:f9eeca106725	2808	#define CAN_F5R2_FB8 0x00000100U /!<Filter bit 8 /
Kojto	122:f9eeca106725	2809	#define CAN_F5R2_FB9 0x00000200U /!<Filter bit 9 /
Kojto	122:f9eeca106725	2810	#define CAN_F5R2_FB10 0x00000400U /!<Filter bit 10 /
Kojto	122:f9eeca106725	2811	#define CAN_F5R2_FB11 0x00000800U /!<Filter bit 11 /
Kojto	122:f9eeca106725	2812	#define CAN_F5R2_FB12 0x00001000U /!<Filter bit 12 /
Kojto	122:f9eeca106725	2813	#define CAN_F5R2_FB13 0x00002000U /!<Filter bit 13 /
Kojto	122:f9eeca106725	2814	#define CAN_F5R2_FB14 0x00004000U /!<Filter bit 14 /
Kojto	122:f9eeca106725	2815	#define CAN_F5R2_FB15 0x00008000U /!<Filter bit 15 /
Kojto	122:f9eeca106725	2816	#define CAN_F5R2_FB16 0x00010000U /!<Filter bit 16 /
Kojto	122:f9eeca106725	2817	#define CAN_F5R2_FB17 0x00020000U /!<Filter bit 17 /
Kojto	122:f9eeca106725	2818	#define CAN_F5R2_FB18 0x00040000U /!<Filter bit 18 /
Kojto	122:f9eeca106725	2819	#define CAN_F5R2_FB19 0x00080000U /!<Filter bit 19 /
Kojto	122:f9eeca106725	2820	#define CAN_F5R2_FB20 0x00100000U /!<Filter bit 20 /
Kojto	122:f9eeca106725	2821	#define CAN_F5R2_FB21 0x00200000U /!<Filter bit 21 /
Kojto	122:f9eeca106725	2822	#define CAN_F5R2_FB22 0x00400000U /!<Filter bit 22 /
Kojto	122:f9eeca106725	2823	#define CAN_F5R2_FB23 0x00800000U /!<Filter bit 23 /
Kojto	122:f9eeca106725	2824	#define CAN_F5R2_FB24 0x01000000U /!<Filter bit 24 /
Kojto	122:f9eeca106725	2825	#define CAN_F5R2_FB25 0x02000000U /!<Filter bit 25 /
Kojto	122:f9eeca106725	2826	#define CAN_F5R2_FB26 0x04000000U /!<Filter bit 26 /
Kojto	122:f9eeca106725	2827	#define CAN_F5R2_FB27 0x08000000U /!<Filter bit 27 /
Kojto	122:f9eeca106725	2828	#define CAN_F5R2_FB28 0x10000000U /!<Filter bit 28 /
Kojto	122:f9eeca106725	2829	#define CAN_F5R2_FB29 0x20000000U /!<Filter bit 29 /
Kojto	122:f9eeca106725	2830	#define CAN_F5R2_FB30 0x40000000U /!<Filter bit 30 /
Kojto	122:f9eeca106725	2831	#define CAN_F5R2_FB31 0x80000000U /!<Filter bit 31 /
Kojto	110:165afa46840b	2832
Kojto	110:165afa46840b	2833	/***************** Bit definition for CAN_F6R2 register *****************/
Kojto	122:f9eeca106725	2834	#define CAN_F6R2_FB0 0x00000001U /!<Filter bit 0 /
Kojto	122:f9eeca106725	2835	#define CAN_F6R2_FB1 0x00000002U /!<Filter bit 1 /
Kojto	122:f9eeca106725	2836	#define CAN_F6R2_FB2 0x00000004U /!<Filter bit 2 /
Kojto	122:f9eeca106725	2837	#define CAN_F6R2_FB3 0x00000008U /!<Filter bit 3 /
Kojto	122:f9eeca106725	2838	#define CAN_F6R2_FB4 0x00000010U /!<Filter bit 4 /
Kojto	122:f9eeca106725	2839	#define CAN_F6R2_FB5 0x00000020U /!<Filter bit 5 /
Kojto	122:f9eeca106725	2840	#define CAN_F6R2_FB6 0x00000040U /!<Filter bit 6 /
Kojto	122:f9eeca106725	2841	#define CAN_F6R2_FB7 0x00000080U /!<Filter bit 7 /
Kojto	122:f9eeca106725	2842	#define CAN_F6R2_FB8 0x00000100U /!<Filter bit 8 /
Kojto	122:f9eeca106725	2843	#define CAN_F6R2_FB9 0x00000200U /!<Filter bit 9 /
Kojto	122:f9eeca106725	2844	#define CAN_F6R2_FB10 0x00000400U /!<Filter bit 10 /
Kojto	122:f9eeca106725	2845	#define CAN_F6R2_FB11 0x00000800U /!<Filter bit 11 /
Kojto	122:f9eeca106725	2846	#define CAN_F6R2_FB12 0x00001000U /!<Filter bit 12 /
Kojto	122:f9eeca106725	2847	#define CAN_F6R2_FB13 0x00002000U /!<Filter bit 13 /
Kojto	122:f9eeca106725	2848	#define CAN_F6R2_FB14 0x00004000U /!<Filter bit 14 /
Kojto	122:f9eeca106725	2849	#define CAN_F6R2_FB15 0x00008000U /!<Filter bit 15 /
Kojto	122:f9eeca106725	2850	#define CAN_F6R2_FB16 0x00010000U /!<Filter bit 16 /
Kojto	122:f9eeca106725	2851	#define CAN_F6R2_FB17 0x00020000U /!<Filter bit 17 /
Kojto	122:f9eeca106725	2852	#define CAN_F6R2_FB18 0x00040000U /!<Filter bit 18 /
Kojto	122:f9eeca106725	2853	#define CAN_F6R2_FB19 0x00080000U /!<Filter bit 19 /
Kojto	122:f9eeca106725	2854	#define CAN_F6R2_FB20 0x00100000U /!<Filter bit 20 /
Kojto	122:f9eeca106725	2855	#define CAN_F6R2_FB21 0x00200000U /!<Filter bit 21 /
Kojto	122:f9eeca106725	2856	#define CAN_F6R2_FB22 0x00400000U /!<Filter bit 22 /
Kojto	122:f9eeca106725	2857	#define CAN_F6R2_FB23 0x00800000U /!<Filter bit 23 /
Kojto	122:f9eeca106725	2858	#define CAN_F6R2_FB24 0x01000000U /!<Filter bit 24 /
Kojto	122:f9eeca106725	2859	#define CAN_F6R2_FB25 0x02000000U /!<Filter bit 25 /
Kojto	122:f9eeca106725	2860	#define CAN_F6R2_FB26 0x04000000U /!<Filter bit 26 /
Kojto	122:f9eeca106725	2861	#define CAN_F6R2_FB27 0x08000000U /!<Filter bit 27 /
Kojto	122:f9eeca106725	2862	#define CAN_F6R2_FB28 0x10000000U /!<Filter bit 28 /
Kojto	122:f9eeca106725	2863	#define CAN_F6R2_FB29 0x20000000U /!<Filter bit 29 /
Kojto	122:f9eeca106725	2864	#define CAN_F6R2_FB30 0x40000000U /!<Filter bit 30 /
Kojto	122:f9eeca106725	2865	#define CAN_F6R2_FB31 0x80000000U /!<Filter bit 31 /
Kojto	110:165afa46840b	2866
Kojto	110:165afa46840b	2867	/***************** Bit definition for CAN_F7R2 register *****************/
Kojto	122:f9eeca106725	2868	#define CAN_F7R2_FB0 0x00000001U /!<Filter bit 0 /
Kojto	122:f9eeca106725	2869	#define CAN_F7R2_FB1 0x00000002U /!<Filter bit 1 /
Kojto	122:f9eeca106725	2870	#define CAN_F7R2_FB2 0x00000004U /!<Filter bit 2 /
Kojto	122:f9eeca106725	2871	#define CAN_F7R2_FB3 0x00000008U /!<Filter bit 3 /
Kojto	122:f9eeca106725	2872	#define CAN_F7R2_FB4 0x00000010U /!<Filter bit 4 /
Kojto	122:f9eeca106725	2873	#define CAN_F7R2_FB5 0x00000020U /!<Filter bit 5 /
Kojto	122:f9eeca106725	2874	#define CAN_F7R2_FB6 0x00000040U /!<Filter bit 6 /
Kojto	122:f9eeca106725	2875	#define CAN_F7R2_FB7 0x00000080U /!<Filter bit 7 /
Kojto	122:f9eeca106725	2876	#define CAN_F7R2_FB8 0x00000100U /!<Filter bit 8 /
Kojto	122:f9eeca106725	2877	#define CAN_F7R2_FB9 0x00000200U /!<Filter bit 9 /
Kojto	122:f9eeca106725	2878	#define CAN_F7R2_FB10 0x00000400U /!<Filter bit 10 /
Kojto	122:f9eeca106725	2879	#define CAN_F7R2_FB11 0x00000800U /!<Filter bit 11 /
Kojto	122:f9eeca106725	2880	#define CAN_F7R2_FB12 0x00001000U /!<Filter bit 12 /
Kojto	122:f9eeca106725	2881	#define CAN_F7R2_FB13 0x00002000U /!<Filter bit 13 /
Kojto	122:f9eeca106725	2882	#define CAN_F7R2_FB14 0x00004000U /!<Filter bit 14 /
Kojto	122:f9eeca106725	2883	#define CAN_F7R2_FB15 0x00008000U /!<Filter bit 15 /
Kojto	122:f9eeca106725	2884	#define CAN_F7R2_FB16 0x00010000U /!<Filter bit 16 /
Kojto	122:f9eeca106725	2885	#define CAN_F7R2_FB17 0x00020000U /!<Filter bit 17 /
Kojto	122:f9eeca106725	2886	#define CAN_F7R2_FB18 0x00040000U /!<Filter bit 18 /
Kojto	122:f9eeca106725	2887	#define CAN_F7R2_FB19 0x00080000U /!<Filter bit 19 /
Kojto	122:f9eeca106725	2888	#define CAN_F7R2_FB20 0x00100000U /!<Filter bit 20 /
Kojto	122:f9eeca106725	2889	#define CAN_F7R2_FB21 0x00200000U /!<Filter bit 21 /
Kojto	122:f9eeca106725	2890	#define CAN_F7R2_FB22 0x00400000U /!<Filter bit 22 /
Kojto	122:f9eeca106725	2891	#define CAN_F7R2_FB23 0x00800000U /!<Filter bit 23 /
Kojto	122:f9eeca106725	2892	#define CAN_F7R2_FB24 0x01000000U /!<Filter bit 24 /
Kojto	122:f9eeca106725	2893	#define CAN_F7R2_FB25 0x02000000U /!<Filter bit 25 /
Kojto	122:f9eeca106725	2894	#define CAN_F7R2_FB26 0x04000000U /!<Filter bit 26 /
Kojto	122:f9eeca106725	2895	#define CAN_F7R2_FB27 0x08000000U /!<Filter bit 27 /
Kojto	122:f9eeca106725	2896	#define CAN_F7R2_FB28 0x10000000U /!<Filter bit 28 /
Kojto	122:f9eeca106725	2897	#define CAN_F7R2_FB29 0x20000000U /!<Filter bit 29 /
Kojto	122:f9eeca106725	2898	#define CAN_F7R2_FB30 0x40000000U /!<Filter bit 30 /
Kojto	122:f9eeca106725	2899	#define CAN_F7R2_FB31 0x80000000U /!<Filter bit 31 /
Kojto	110:165afa46840b	2900
Kojto	110:165afa46840b	2901	/***************** Bit definition for CAN_F8R2 register *****************/
Kojto	122:f9eeca106725	2902	#define CAN_F8R2_FB0 0x00000001U /!<Filter bit 0 /
Kojto	122:f9eeca106725	2903	#define CAN_F8R2_FB1 0x00000002U /!<Filter bit 1 /
Kojto	122:f9eeca106725	2904	#define CAN_F8R2_FB2 0x00000004U /!<Filter bit 2 /
Kojto	122:f9eeca106725	2905	#define CAN_F8R2_FB3 0x00000008U /!<Filter bit 3 /
Kojto	122:f9eeca106725	2906	#define CAN_F8R2_FB4 0x00000010U /!<Filter bit 4 /
Kojto	122:f9eeca106725	2907	#define CAN_F8R2_FB5 0x00000020U /!<Filter bit 5 /
Kojto	122:f9eeca106725	2908	#define CAN_F8R2_FB6 0x00000040U /!<Filter bit 6 /
Kojto	122:f9eeca106725	2909	#define CAN_F8R2_FB7 0x00000080U /!<Filter bit 7 /
Kojto	122:f9eeca106725	2910	#define CAN_F8R2_FB8 0x00000100U /!<Filter bit 8 /
Kojto	122:f9eeca106725	2911	#define CAN_F8R2_FB9 0x00000200U /!<Filter bit 9 /
Kojto	122:f9eeca106725	2912	#define CAN_F8R2_FB10 0x00000400U /!<Filter bit 10 /
Kojto	122:f9eeca106725	2913	#define CAN_F8R2_FB11 0x00000800U /!<Filter bit 11 /
Kojto	122:f9eeca106725	2914	#define CAN_F8R2_FB12 0x00001000U /!<Filter bit 12 /
Kojto	122:f9eeca106725	2915	#define CAN_F8R2_FB13 0x00002000U /!<Filter bit 13 /
Kojto	122:f9eeca106725	2916	#define CAN_F8R2_FB14 0x00004000U /!<Filter bit 14 /
Kojto	122:f9eeca106725	2917	#define CAN_F8R2_FB15 0x00008000U /!<Filter bit 15 /
Kojto	122:f9eeca106725	2918	#define CAN_F8R2_FB16 0x00010000U /!<Filter bit 16 /
Kojto	122:f9eeca106725	2919	#define CAN_F8R2_FB17 0x00020000U /!<Filter bit 17 /
Kojto	122:f9eeca106725	2920	#define CAN_F8R2_FB18 0x00040000U /!<Filter bit 18 /
Kojto	122:f9eeca106725	2921	#define CAN_F8R2_FB19 0x00080000U /!<Filter bit 19 /
Kojto	122:f9eeca106725	2922	#define CAN_F8R2_FB20 0x00100000U /!<Filter bit 20 /
Kojto	122:f9eeca106725	2923	#define CAN_F8R2_FB21 0x00200000U /!<Filter bit 21 /
Kojto	122:f9eeca106725	2924	#define CAN_F8R2_FB22 0x00400000U /!<Filter bit 22 /
Kojto	122:f9eeca106725	2925	#define CAN_F8R2_FB23 0x00800000U /!<Filter bit 23 /
Kojto	122:f9eeca106725	2926	#define CAN_F8R2_FB24 0x01000000U /!<Filter bit 24 /
Kojto	122:f9eeca106725	2927	#define CAN_F8R2_FB25 0x02000000U /!<Filter bit 25 /
Kojto	122:f9eeca106725	2928	#define CAN_F8R2_FB26 0x04000000U /!<Filter bit 26 /
Kojto	122:f9eeca106725	2929	#define CAN_F8R2_FB27 0x08000000U /!<Filter bit 27 /
Kojto	122:f9eeca106725	2930	#define CAN_F8R2_FB28 0x10000000U /!<Filter bit 28 /
Kojto	122:f9eeca106725	2931	#define CAN_F8R2_FB29 0x20000000U /!<Filter bit 29 /
Kojto	122:f9eeca106725	2932	#define CAN_F8R2_FB30 0x40000000U /!<Filter bit 30 /
Kojto	122:f9eeca106725	2933	#define CAN_F8R2_FB31 0x80000000U /!<Filter bit 31 /
Kojto	110:165afa46840b	2934
Kojto	110:165afa46840b	2935	/***************** Bit definition for CAN_F9R2 register *****************/
Kojto	122:f9eeca106725	2936	#define CAN_F9R2_FB0 0x00000001U /!<Filter bit 0 /
Kojto	122:f9eeca106725	2937	#define CAN_F9R2_FB1 0x00000002U /!<Filter bit 1 /
Kojto	122:f9eeca106725	2938	#define CAN_F9R2_FB2 0x00000004U /!<Filter bit 2 /
Kojto	122:f9eeca106725	2939	#define CAN_F9R2_FB3 0x00000008U /!<Filter bit 3 /
Kojto	122:f9eeca106725	2940	#define CAN_F9R2_FB4 0x00000010U /!<Filter bit 4 /
Kojto	122:f9eeca106725	2941	#define CAN_F9R2_FB5 0x00000020U /!<Filter bit 5 /
Kojto	122:f9eeca106725	2942	#define CAN_F9R2_FB6 0x00000040U /!<Filter bit 6 /
Kojto	122:f9eeca106725	2943	#define CAN_F9R2_FB7 0x00000080U /!<Filter bit 7 /
Kojto	122:f9eeca106725	2944	#define CAN_F9R2_FB8 0x00000100U /!<Filter bit 8 /
Kojto	122:f9eeca106725	2945	#define CAN_F9R2_FB9 0x00000200U /!<Filter bit 9 /
Kojto	122:f9eeca106725	2946	#define CAN_F9R2_FB10 0x00000400U /!<Filter bit 10 /
Kojto	122:f9eeca106725	2947	#define CAN_F9R2_FB11 0x00000800U /!<Filter bit 11 /
Kojto	122:f9eeca106725	2948	#define CAN_F9R2_FB12 0x00001000U /!<Filter bit 12 /
Kojto	122:f9eeca106725	2949	#define CAN_F9R2_FB13 0x00002000U /!<Filter bit 13 /
Kojto	122:f9eeca106725	2950	#define CAN_F9R2_FB14 0x00004000U /!<Filter bit 14 /
Kojto	122:f9eeca106725	2951	#define CAN_F9R2_FB15 0x00008000U /!<Filter bit 15 /
Kojto	122:f9eeca106725	2952	#define CAN_F9R2_FB16 0x00010000U /!<Filter bit 16 /
Kojto	122:f9eeca106725	2953	#define CAN_F9R2_FB17 0x00020000U /!<Filter bit 17 /
Kojto	122:f9eeca106725	2954	#define CAN_F9R2_FB18 0x00040000U /!<Filter bit 18 /
Kojto	122:f9eeca106725	2955	#define CAN_F9R2_FB19 0x00080000U /!<Filter bit 19 /
Kojto	122:f9eeca106725	2956	#define CAN_F9R2_FB20 0x00100000U /!<Filter bit 20 /
Kojto	122:f9eeca106725	2957	#define CAN_F9R2_FB21 0x00200000U /!<Filter bit 21 /
Kojto	122:f9eeca106725	2958	#define CAN_F9R2_FB22 0x00400000U /!<Filter bit 22 /
Kojto	122:f9eeca106725	2959	#define CAN_F9R2_FB23 0x00800000U /!<Filter bit 23 /
Kojto	122:f9eeca106725	2960	#define CAN_F9R2_FB24 0x01000000U /!<Filter bit 24 /
Kojto	122:f9eeca106725	2961	#define CAN_F9R2_FB25 0x02000000U /!<Filter bit 25 /
Kojto	122:f9eeca106725	2962	#define CAN_F9R2_FB26 0x04000000U /!<Filter bit 26 /
Kojto	122:f9eeca106725	2963	#define CAN_F9R2_FB27 0x08000000U /!<Filter bit 27 /
Kojto	122:f9eeca106725	2964	#define CAN_F9R2_FB28 0x10000000U /!<Filter bit 28 /
Kojto	122:f9eeca106725	2965	#define CAN_F9R2_FB29 0x20000000U /!<Filter bit 29 /
Kojto	122:f9eeca106725	2966	#define CAN_F9R2_FB30 0x40000000U /!<Filter bit 30 /
Kojto	122:f9eeca106725	2967	#define CAN_F9R2_FB31 0x80000000U /!<Filter bit 31 /
Kojto	110:165afa46840b	2968
Kojto	110:165afa46840b	2969	/***************** Bit definition for CAN_F10R2 register ****************/
Kojto	122:f9eeca106725	2970	#define CAN_F10R2_FB0 0x00000001U /!<Filter bit 0 /
Kojto	122:f9eeca106725	2971	#define CAN_F10R2_FB1 0x00000002U /!<Filter bit 1 /
Kojto	122:f9eeca106725	2972	#define CAN_F10R2_FB2 0x00000004U /!<Filter bit 2 /
Kojto	122:f9eeca106725	2973	#define CAN_F10R2_FB3 0x00000008U /!<Filter bit 3 /
Kojto	122:f9eeca106725	2974	#define CAN_F10R2_FB4 0x00000010U /!<Filter bit 4 /
Kojto	122:f9eeca106725	2975	#define CAN_F10R2_FB5 0x00000020U /!<Filter bit 5 /
Kojto	122:f9eeca106725	2976	#define CAN_F10R2_FB6 0x00000040U /!<Filter bit 6 /
Kojto	122:f9eeca106725	2977	#define CAN_F10R2_FB7 0x00000080U /!<Filter bit 7 /
Kojto	122:f9eeca106725	2978	#define CAN_F10R2_FB8 0x00000100U /!<Filter bit 8 /
Kojto	122:f9eeca106725	2979	#define CAN_F10R2_FB9 0x00000200U /!<Filter bit 9 /
Kojto	122:f9eeca106725	2980	#define CAN_F10R2_FB10 0x00000400U /!<Filter bit 10 /
Kojto	122:f9eeca106725	2981	#define CAN_F10R2_FB11 0x00000800U /!<Filter bit 11 /
Kojto	122:f9eeca106725	2982	#define CAN_F10R2_FB12 0x00001000U /!<Filter bit 12 /
Kojto	122:f9eeca106725	2983	#define CAN_F10R2_FB13 0x00002000U /!<Filter bit 13 /
Kojto	122:f9eeca106725	2984	#define CAN_F10R2_FB14 0x00004000U /!<Filter bit 14 /
Kojto	122:f9eeca106725	2985	#define CAN_F10R2_FB15 0x00008000U /!<Filter bit 15 /
Kojto	122:f9eeca106725	2986	#define CAN_F10R2_FB16 0x00010000U /!<Filter bit 16 /
Kojto	122:f9eeca106725	2987	#define CAN_F10R2_FB17 0x00020000U /!<Filter bit 17 /
Kojto	122:f9eeca106725	2988	#define CAN_F10R2_FB18 0x00040000U /!<Filter bit 18 /
Kojto	122:f9eeca106725	2989	#define CAN_F10R2_FB19 0x00080000U /!<Filter bit 19 /
Kojto	122:f9eeca106725	2990	#define CAN_F10R2_FB20 0x00100000U /!<Filter bit 20 /
Kojto	122:f9eeca106725	2991	#define CAN_F10R2_FB21 0x00200000U /!<Filter bit 21 /
Kojto	122:f9eeca106725	2992	#define CAN_F10R2_FB22 0x00400000U /!<Filter bit 22 /
Kojto	122:f9eeca106725	2993	#define CAN_F10R2_FB23 0x00800000U /!<Filter bit 23 /
Kojto	122:f9eeca106725	2994	#define CAN_F10R2_FB24 0x01000000U /!<Filter bit 24 /
Kojto	122:f9eeca106725	2995	#define CAN_F10R2_FB25 0x02000000U /!<Filter bit 25 /
Kojto	122:f9eeca106725	2996	#define CAN_F10R2_FB26 0x04000000U /!<Filter bit 26 /
Kojto	122:f9eeca106725	2997	#define CAN_F10R2_FB27 0x08000000U /!<Filter bit 27 /
Kojto	122:f9eeca106725	2998	#define CAN_F10R2_FB28 0x10000000U /!<Filter bit 28 /
Kojto	122:f9eeca106725	2999	#define CAN_F10R2_FB29 0x20000000U /!<Filter bit 29 /
Kojto	122:f9eeca106725	3000	#define CAN_F10R2_FB30 0x40000000U /!<Filter bit 30 /
Kojto	122:f9eeca106725	3001	#define CAN_F10R2_FB31 0x80000000U /!<Filter bit 31 /
Kojto	110:165afa46840b	3002
Kojto	110:165afa46840b	3003	/***************** Bit definition for CAN_F11R2 register ****************/
Kojto	122:f9eeca106725	3004	#define CAN_F11R2_FB0 0x00000001U /!<Filter bit 0 /
Kojto	122:f9eeca106725	3005	#define CAN_F11R2_FB1 0x00000002U /!<Filter bit 1 /
Kojto	122:f9eeca106725	3006	#define CAN_F11R2_FB2 0x00000004U /!<Filter bit 2 /
Kojto	122:f9eeca106725	3007	#define CAN_F11R2_FB3 0x00000008U /!<Filter bit 3 /
Kojto	122:f9eeca106725	3008	#define CAN_F11R2_FB4 0x00000010U /!<Filter bit 4 /
Kojto	122:f9eeca106725	3009	#define CAN_F11R2_FB5 0x00000020U /!<Filter bit 5 /
Kojto	122:f9eeca106725	3010	#define CAN_F11R2_FB6 0x00000040U /!<Filter bit 6 /
Kojto	122:f9eeca106725	3011	#define CAN_F11R2_FB7 0x00000080U /!<Filter bit 7 /
Kojto	122:f9eeca106725	3012	#define CAN_F11R2_FB8 0x00000100U /!<Filter bit 8 /
Kojto	122:f9eeca106725	3013	#define CAN_F11R2_FB9 0x00000200U /!<Filter bit 9 /
Kojto	122:f9eeca106725	3014	#define CAN_F11R2_FB10 0x00000400U /!<Filter bit 10 /
Kojto	122:f9eeca106725	3015	#define CAN_F11R2_FB11 0x00000800U /!<Filter bit 11 /
Kojto	122:f9eeca106725	3016	#define CAN_F11R2_FB12 0x00001000U /!<Filter bit 12 /
Kojto	122:f9eeca106725	3017	#define CAN_F11R2_FB13 0x00002000U /!<Filter bit 13 /
Kojto	122:f9eeca106725	3018	#define CAN_F11R2_FB14 0x00004000U /!<Filter bit 14 /
Kojto	122:f9eeca106725	3019	#define CAN_F11R2_FB15 0x00008000U /!<Filter bit 15 /
Kojto	122:f9eeca106725	3020	#define CAN_F11R2_FB16 0x00010000U /!<Filter bit 16 /
Kojto	122:f9eeca106725	3021	#define CAN_F11R2_FB17 0x00020000U /!<Filter bit 17 /
Kojto	122:f9eeca106725	3022	#define CAN_F11R2_FB18 0x00040000U /!<Filter bit 18 /
Kojto	122:f9eeca106725	3023	#define CAN_F11R2_FB19 0x00080000U /!<Filter bit 19 /
Kojto	122:f9eeca106725	3024	#define CAN_F11R2_FB20 0x00100000U /!<Filter bit 20 /
Kojto	122:f9eeca106725	3025	#define CAN_F11R2_FB21 0x00200000U /!<Filter bit 21 /
Kojto	122:f9eeca106725	3026	#define CAN_F11R2_FB22 0x00400000U /!<Filter bit 22 /
Kojto	122:f9eeca106725	3027	#define CAN_F11R2_FB23 0x00800000U /!<Filter bit 23 /
Kojto	122:f9eeca106725	3028	#define CAN_F11R2_FB24 0x01000000U /!<Filter bit 24 /
Kojto	122:f9eeca106725	3029	#define CAN_F11R2_FB25 0x02000000U /!<Filter bit 25 /
Kojto	122:f9eeca106725	3030	#define CAN_F11R2_FB26 0x04000000U /!<Filter bit 26 /
Kojto	122:f9eeca106725	3031	#define CAN_F11R2_FB27 0x08000000U /!<Filter bit 27 /
Kojto	122:f9eeca106725	3032	#define CAN_F11R2_FB28 0x10000000U /!<Filter bit 28 /
Kojto	122:f9eeca106725	3033	#define CAN_F11R2_FB29 0x20000000U /!<Filter bit 29 /
Kojto	122:f9eeca106725	3034	#define CAN_F11R2_FB30 0x40000000U /!<Filter bit 30 /
Kojto	122:f9eeca106725	3035	#define CAN_F11R2_FB31 0x80000000U /!<Filter bit 31 /
Kojto	110:165afa46840b	3036
Kojto	110:165afa46840b	3037	/***************** Bit definition for CAN_F12R2 register ****************/
Kojto	122:f9eeca106725	3038	#define CAN_F12R2_FB0 0x00000001U /!<Filter bit 0 /
Kojto	122:f9eeca106725	3039	#define CAN_F12R2_FB1 0x00000002U /!<Filter bit 1 /
Kojto	122:f9eeca106725	3040	#define CAN_F12R2_FB2 0x00000004U /!<Filter bit 2 /
Kojto	122:f9eeca106725	3041	#define CAN_F12R2_FB3 0x00000008U /!<Filter bit 3 /
Kojto	122:f9eeca106725	3042	#define CAN_F12R2_FB4 0x00000010U /!<Filter bit 4 /
Kojto	122:f9eeca106725	3043	#define CAN_F12R2_FB5 0x00000020U /!<Filter bit 5 /
Kojto	122:f9eeca106725	3044	#define CAN_F12R2_FB6 0x00000040U /!<Filter bit 6 /
Kojto	122:f9eeca106725	3045	#define CAN_F12R2_FB7 0x00000080U /!<Filter bit 7 /
Kojto	122:f9eeca106725	3046	#define CAN_F12R2_FB8 0x00000100U /!<Filter bit 8 /
Kojto	122:f9eeca106725	3047	#define CAN_F12R2_FB9 0x00000200U /!<Filter bit 9 /
Kojto	122:f9eeca106725	3048	#define CAN_F12R2_FB10 0x00000400U /!<Filter bit 10 /
Kojto	122:f9eeca106725	3049	#define CAN_F12R2_FB11 0x00000800U /!<Filter bit 11 /
Kojto	122:f9eeca106725	3050	#define CAN_F12R2_FB12 0x00001000U /!<Filter bit 12 /
Kojto	122:f9eeca106725	3051	#define CAN_F12R2_FB13 0x00002000U /!<Filter bit 13 /
Kojto	122:f9eeca106725	3052	#define CAN_F12R2_FB14 0x00004000U /!<Filter bit 14 /
Kojto	122:f9eeca106725	3053	#define CAN_F12R2_FB15 0x00008000U /!<Filter bit 15 /
Kojto	122:f9eeca106725	3054	#define CAN_F12R2_FB16 0x00010000U /!<Filter bit 16 /
Kojto	122:f9eeca106725	3055	#define CAN_F12R2_FB17 0x00020000U /!<Filter bit 17 /
Kojto	122:f9eeca106725	3056	#define CAN_F12R2_FB18 0x00040000U /!<Filter bit 18 /
Kojto	122:f9eeca106725	3057	#define CAN_F12R2_FB19 0x00080000U /!<Filter bit 19 /
Kojto	122:f9eeca106725	3058	#define CAN_F12R2_FB20 0x00100000U /!<Filter bit 20 /
Kojto	122:f9eeca106725	3059	#define CAN_F12R2_FB21 0x00200000U /!<Filter bit 21 /
Kojto	122:f9eeca106725	3060	#define CAN_F12R2_FB22 0x00400000U /!<Filter bit 22 /
Kojto	122:f9eeca106725	3061	#define CAN_F12R2_FB23 0x00800000U /!<Filter bit 23 /
Kojto	122:f9eeca106725	3062	#define CAN_F12R2_FB24 0x01000000U /!<Filter bit 24 /
Kojto	122:f9eeca106725	3063	#define CAN_F12R2_FB25 0x02000000U /!<Filter bit 25 /
Kojto	122:f9eeca106725	3064	#define CAN_F12R2_FB26 0x04000000U /!<Filter bit 26 /
Kojto	122:f9eeca106725	3065	#define CAN_F12R2_FB27 0x08000000U /!<Filter bit 27 /
Kojto	122:f9eeca106725	3066	#define CAN_F12R2_FB28 0x10000000U /!<Filter bit 28 /
Kojto	122:f9eeca106725	3067	#define CAN_F12R2_FB29 0x20000000U /!<Filter bit 29 /
Kojto	122:f9eeca106725	3068	#define CAN_F12R2_FB30 0x40000000U /!<Filter bit 30 /
Kojto	122:f9eeca106725	3069	#define CAN_F12R2_FB31 0x80000000U /!<Filter bit 31 /
Kojto	110:165afa46840b	3070
Kojto	110:165afa46840b	3071	/***************** Bit definition for CAN_F13R2 register ****************/
Kojto	122:f9eeca106725	3072	#define CAN_F13R2_FB0 0x00000001U /!<Filter bit 0 /
Kojto	122:f9eeca106725	3073	#define CAN_F13R2_FB1 0x00000002U /!<Filter bit 1 /
Kojto	122:f9eeca106725	3074	#define CAN_F13R2_FB2 0x00000004U /!<Filter bit 2 /
Kojto	122:f9eeca106725	3075	#define CAN_F13R2_FB3 0x00000008U /!<Filter bit 3 /
Kojto	122:f9eeca106725	3076	#define CAN_F13R2_FB4 0x00000010U /!<Filter bit 4 /
Kojto	122:f9eeca106725	3077	#define CAN_F13R2_FB5 0x00000020U /!<Filter bit 5 /
Kojto	122:f9eeca106725	3078	#define CAN_F13R2_FB6 0x00000040U /!<Filter bit 6 /
Kojto	122:f9eeca106725	3079	#define CAN_F13R2_FB7 0x00000080U /!<Filter bit 7 /
Kojto	122:f9eeca106725	3080	#define CAN_F13R2_FB8 0x00000100U /!<Filter bit 8 /
Kojto	122:f9eeca106725	3081	#define CAN_F13R2_FB9 0x00000200U /!<Filter bit 9 /
Kojto	122:f9eeca106725	3082	#define CAN_F13R2_FB10 0x00000400U /!<Filter bit 10 /
Kojto	122:f9eeca106725	3083	#define CAN_F13R2_FB11 0x00000800U /!<Filter bit 11 /
Kojto	122:f9eeca106725	3084	#define CAN_F13R2_FB12 0x00001000U /!<Filter bit 12 /
Kojto	122:f9eeca106725	3085	#define CAN_F13R2_FB13 0x00002000U /!<Filter bit 13 /
Kojto	122:f9eeca106725	3086	#define CAN_F13R2_FB14 0x00004000U /!<Filter bit 14 /
Kojto	122:f9eeca106725	3087	#define CAN_F13R2_FB15 0x00008000U /!<Filter bit 15 /
Kojto	122:f9eeca106725	3088	#define CAN_F13R2_FB16 0x00010000U /!<Filter bit 16 /
Kojto	122:f9eeca106725	3089	#define CAN_F13R2_FB17 0x00020000U /!<Filter bit 17 /
Kojto	122:f9eeca106725	3090	#define CAN_F13R2_FB18 0x00040000U /!<Filter bit 18 /
Kojto	122:f9eeca106725	3091	#define CAN_F13R2_FB19 0x00080000U /!<Filter bit 19 /
Kojto	122:f9eeca106725	3092	#define CAN_F13R2_FB20 0x00100000U /!<Filter bit 20 /
Kojto	122:f9eeca106725	3093	#define CAN_F13R2_FB21 0x00200000U /!<Filter bit 21 /
Kojto	122:f9eeca106725	3094	#define CAN_F13R2_FB22 0x00400000U /!<Filter bit 22 /
Kojto	122:f9eeca106725	3095	#define CAN_F13R2_FB23 0x00800000U /!<Filter bit 23 /
Kojto	122:f9eeca106725	3096	#define CAN_F13R2_FB24 0x01000000U /!<Filter bit 24 /
Kojto	122:f9eeca106725	3097	#define CAN_F13R2_FB25 0x02000000U /!<Filter bit 25 /
Kojto	122:f9eeca106725	3098	#define CAN_F13R2_FB26 0x04000000U /!<Filter bit 26 /
Kojto	122:f9eeca106725	3099	#define CAN_F13R2_FB27 0x08000000U /!<Filter bit 27 /
Kojto	122:f9eeca106725	3100	#define CAN_F13R2_FB28 0x10000000U /!<Filter bit 28 /
Kojto	122:f9eeca106725	3101	#define CAN_F13R2_FB29 0x20000000U /!<Filter bit 29 /
Kojto	122:f9eeca106725	3102	#define CAN_F13R2_FB30 0x40000000U /!<Filter bit 30 /
Kojto	122:f9eeca106725	3103	#define CAN_F13R2_FB31 0x80000000U /!<Filter bit 31 /
Kojto	110:165afa46840b	3104
Kojto	110:165afa46840b	3105	/******************************************************************************/
Kojto	110:165afa46840b	3106	/* */
Kojto	110:165afa46840b	3107	/* CRC calculation unit */
Kojto	110:165afa46840b	3108	/* */
Kojto	110:165afa46840b	3109	/******************************************************************************/
Kojto	110:165afa46840b	3110	/***************** Bit definition for CRC_DR register *******************/
Kojto	122:f9eeca106725	3111	#define CRC_DR_DR 0xFFFFFFFFU /!< Data register bits /
Kojto	110:165afa46840b	3112
Kojto	110:165afa46840b	3113
Kojto	110:165afa46840b	3114	/***************** Bit definition for CRC_IDR register ******************/
Kojto	122:f9eeca106725	3115	#define CRC_IDR_IDR 0xFFU /!< General-purpose 8-bit data register bits /
Kojto	110:165afa46840b	3116
Kojto	110:165afa46840b	3117
Kojto	110:165afa46840b	3118	/****************** Bit definition for CRC_CR register ******************/
Kojto	122:f9eeca106725	3119	#define CRC_CR_RESET 0x01U /!< RESET bit /
Kojto	110:165afa46840b	3120
Kojto	110:165afa46840b	3121
Kojto	110:165afa46840b	3122	/******************************************************************************/
Kojto	110:165afa46840b	3123	/* */
Kojto	110:165afa46840b	3124	/* Digital to Analog Converter */
Kojto	110:165afa46840b	3125	/* */
Kojto	110:165afa46840b	3126	/******************************************************************************/
Kojto	110:165afa46840b	3127	/****************** Bit definition for DAC_CR register ******************/
Kojto	122:f9eeca106725	3128	#define DAC_CR_EN1 0x00000001U /!<DAC channel1 enable /
Kojto	122:f9eeca106725	3129	#define DAC_CR_BOFF1 0x00000002U /!<DAC channel1 output buffer disable /
Kojto	122:f9eeca106725	3130	#define DAC_CR_TEN1 0x00000004U /!<DAC channel1 Trigger enable /
Kojto	122:f9eeca106725	3131
Kojto	122:f9eeca106725	3132	#define DAC_CR_TSEL1 0x00000038U /!<TSEL1[2:0] (DAC channel1 Trigger selection) /
Kojto	122:f9eeca106725	3133	#define DAC_CR_TSEL1_0 0x00000008U /!<Bit 0 /
Kojto	122:f9eeca106725	3134	#define DAC_CR_TSEL1_1 0x00000010U /!<Bit 1 /
Kojto	122:f9eeca106725	3135	#define DAC_CR_TSEL1_2 0x00000020U /!<Bit 2 /
Kojto	122:f9eeca106725	3136
Kojto	122:f9eeca106725	3137	#define DAC_CR_WAVE1 0x000000C0U /!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) /
Kojto	122:f9eeca106725	3138	#define DAC_CR_WAVE1_0 0x00000040U /!<Bit 0 /
Kojto	122:f9eeca106725	3139	#define DAC_CR_WAVE1_1 0x00000080U /!<Bit 1 /
Kojto	122:f9eeca106725	3140
Kojto	122:f9eeca106725	3141	#define DAC_CR_MAMP1 0x00000F00U /!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) /
Kojto	122:f9eeca106725	3142	#define DAC_CR_MAMP1_0 0x00000100U /!<Bit 0 /
Kojto	122:f9eeca106725	3143	#define DAC_CR_MAMP1_1 0x00000200U /!<Bit 1 /
Kojto	122:f9eeca106725	3144	#define DAC_CR_MAMP1_2 0x00000400U /!<Bit 2 /
Kojto	122:f9eeca106725	3145	#define DAC_CR_MAMP1_3 0x00000800U /!<Bit 3 /
Kojto	122:f9eeca106725	3146
Kojto	122:f9eeca106725	3147	#define DAC_CR_DMAEN1 0x00001000U /!<DAC channel1 DMA enable /
Kojto	122:f9eeca106725	3148	#define DAC_CR_DMAUDRIE1 0x00002000U /!<DAC channel1 DMA underrun interrupt enable/
Kojto	122:f9eeca106725	3149	#define DAC_CR_EN2 0x00010000U /!<DAC channel2 enable /
Kojto	122:f9eeca106725	3150	#define DAC_CR_BOFF2 0x00020000U /!<DAC channel2 output buffer disable /
Kojto	122:f9eeca106725	3151	#define DAC_CR_TEN2 0x00040000U /!<DAC channel2 Trigger enable /
Kojto	122:f9eeca106725	3152
Kojto	122:f9eeca106725	3153	#define DAC_CR_TSEL2 0x00380000U /!<TSEL2[2:0] (DAC channel2 Trigger selection) /
Kojto	122:f9eeca106725	3154	#define DAC_CR_TSEL2_0 0x00080000U /!<Bit 0 /
Kojto	122:f9eeca106725	3155	#define DAC_CR_TSEL2_1 0x00100000U /!<Bit 1 /
Kojto	122:f9eeca106725	3156	#define DAC_CR_TSEL2_2 0x00200000U /!<Bit 2 /
Kojto	122:f9eeca106725	3157
Kojto	122:f9eeca106725	3158	#define DAC_CR_WAVE2 0x00C00000U /!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) /
Kojto	122:f9eeca106725	3159	#define DAC_CR_WAVE2_0 0x00400000U /!<Bit 0 /
Kojto	122:f9eeca106725	3160	#define DAC_CR_WAVE2_1 0x00800000U /!<Bit 1 /
Kojto	122:f9eeca106725	3161
Kojto	122:f9eeca106725	3162	#define DAC_CR_MAMP2 0x0F000000U /!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) /
Kojto	122:f9eeca106725	3163	#define DAC_CR_MAMP2_0 0x01000000U /!<Bit 0 /
Kojto	122:f9eeca106725	3164	#define DAC_CR_MAMP2_1 0x02000000U /!<Bit 1 /
Kojto	122:f9eeca106725	3165	#define DAC_CR_MAMP2_2 0x04000000U /!<Bit 2 /
Kojto	122:f9eeca106725	3166	#define DAC_CR_MAMP2_3 0x08000000U /!<Bit 3 /
Kojto	122:f9eeca106725	3167
Kojto	122:f9eeca106725	3168	#define DAC_CR_DMAEN2 0x10000000U /!<DAC channel2 DMA enabled /
Kojto	122:f9eeca106725	3169	#define DAC_CR_DMAUDRIE2 0x20000000U /!<DAC channel2 DMA underrun interrupt enable/
Kojto	110:165afa46840b	3170
Kojto	110:165afa46840b	3171	/*************** Bit definition for DAC_SWTRIGR register ****************/
Kojto	122:f9eeca106725	3172	#define DAC_SWTRIGR_SWTRIG1 0x01U /!<DAC channel1 software trigger /
Kojto	122:f9eeca106725	3173	#define DAC_SWTRIGR_SWTRIG2 0x02U /!<DAC channel2 software trigger /
Kojto	110:165afa46840b	3174
Kojto	110:165afa46840b	3175	/*************** Bit definition for DAC_DHR12R1 register ****************/
Kojto	122:f9eeca106725	3176	#define DAC_DHR12R1_DACC1DHR 0x0FFFU /!<DAC channel1 12-bit Right aligned data /
Kojto	110:165afa46840b	3177
Kojto	110:165afa46840b	3178	/*************** Bit definition for DAC_DHR12L1 register ****************/
Kojto	122:f9eeca106725	3179	#define DAC_DHR12L1_DACC1DHR 0xFFF0U /!<DAC channel1 12-bit Left aligned data /
Kojto	110:165afa46840b	3180
Kojto	110:165afa46840b	3181	/**************** Bit definition for DAC_DHR8R1 register ****************/
Kojto	122:f9eeca106725	3182	#define DAC_DHR8R1_DACC1DHR 0xFFU /!<DAC channel1 8-bit Right aligned data /
Kojto	110:165afa46840b	3183
Kojto	110:165afa46840b	3184	/*************** Bit definition for DAC_DHR12R2 register ****************/
Kojto	122:f9eeca106725	3185	#define DAC_DHR12R2_DACC2DHR 0x0FFFU /!<DAC channel2 12-bit Right aligned data /
Kojto	110:165afa46840b	3186
Kojto	110:165afa46840b	3187	/*************** Bit definition for DAC_DHR12L2 register ****************/
Kojto	122:f9eeca106725	3188	#define DAC_DHR12L2_DACC2DHR 0xFFF0U /!<DAC channel2 12-bit Left aligned data /
Kojto	110:165afa46840b	3189
Kojto	110:165afa46840b	3190	/**************** Bit definition for DAC_DHR8R2 register ****************/
Kojto	122:f9eeca106725	3191	#define DAC_DHR8R2_DACC2DHR 0xFFU /!<DAC channel2 8-bit Right aligned data /
Kojto	110:165afa46840b	3192
Kojto	110:165afa46840b	3193	/*************** Bit definition for DAC_DHR12RD register ****************/
Kojto	122:f9eeca106725	3194	#define DAC_DHR12RD_DACC1DHR 0x00000FFFU /!<DAC channel1 12-bit Right aligned data /
Kojto	122:f9eeca106725	3195	#define DAC_DHR12RD_DACC2DHR 0x0FFF0000U /!<DAC channel2 12-bit Right aligned data /
Kojto	110:165afa46840b	3196
Kojto	110:165afa46840b	3197	/*************** Bit definition for DAC_DHR12LD register ****************/
Kojto	122:f9eeca106725	3198	#define DAC_DHR12LD_DACC1DHR 0x0000FFF0U /!<DAC channel1 12-bit Left aligned data /
Kojto	122:f9eeca106725	3199	#define DAC_DHR12LD_DACC2DHR 0xFFF00000U /!<DAC channel2 12-bit Left aligned data /
Kojto	110:165afa46840b	3200
Kojto	110:165afa46840b	3201	/**************** Bit definition for DAC_DHR8RD register ****************/
Kojto	122:f9eeca106725	3202	#define DAC_DHR8RD_DACC1DHR 0x00FFU /!<DAC channel1 8-bit Right aligned data /
Kojto	122:f9eeca106725	3203	#define DAC_DHR8RD_DACC2DHR 0xFF00U /!<DAC channel2 8-bit Right aligned data /
Kojto	110:165afa46840b	3204
Kojto	110:165afa46840b	3205	/***************** Bit definition for DAC_DOR1 register *****************/
Kojto	122:f9eeca106725	3206	#define DAC_DOR1_DACC1DOR 0x0FFFU /!<DAC channel1 data output /
Kojto	110:165afa46840b	3207
Kojto	110:165afa46840b	3208	/***************** Bit definition for DAC_DOR2 register *****************/
Kojto	122:f9eeca106725	3209	#define DAC_DOR2_DACC2DOR 0x0FFFU /!<DAC channel2 data output /
Kojto	110:165afa46840b	3210
Kojto	110:165afa46840b	3211	/****************** Bit definition for DAC_SR register ******************/
Kojto	122:f9eeca106725	3212	#define DAC_SR_DMAUDR1 0x00002000U /!<DAC channel1 DMA underrun flag /
Kojto	122:f9eeca106725	3213	#define DAC_SR_DMAUDR2 0x20000000U /!<DAC channel2 DMA underrun flag /
Kojto	110:165afa46840b	3214
Kojto	110:165afa46840b	3215	/******************************************************************************/
Kojto	110:165afa46840b	3216	/* */
Kojto	110:165afa46840b	3217	/* Debug MCU */
Kojto	110:165afa46840b	3218	/* */
Kojto	110:165afa46840b	3219	/******************************************************************************/
Kojto	110:165afa46840b	3220
Kojto	110:165afa46840b	3221	/******************************************************************************/
Kojto	110:165afa46840b	3222	/* */
Kojto	110:165afa46840b	3223	/* DCMI */
Kojto	110:165afa46840b	3224	/* */
Kojto	110:165afa46840b	3225	/******************************************************************************/
Kojto	110:165afa46840b	3226	/****************** Bits definition for DCMI_CR register ****************/
Kojto	122:f9eeca106725	3227	#define DCMI_CR_CAPTURE 0x00000001U
Kojto	122:f9eeca106725	3228	#define DCMI_CR_CM 0x00000002U
Kojto	122:f9eeca106725	3229	#define DCMI_CR_CROP 0x00000004U
Kojto	122:f9eeca106725	3230	#define DCMI_CR_JPEG 0x00000008U
Kojto	122:f9eeca106725	3231	#define DCMI_CR_ESS 0x00000010U
Kojto	122:f9eeca106725	3232	#define DCMI_CR_PCKPOL 0x00000020U
Kojto	122:f9eeca106725	3233	#define DCMI_CR_HSPOL 0x00000040U
Kojto	122:f9eeca106725	3234	#define DCMI_CR_VSPOL 0x00000080U
Kojto	122:f9eeca106725	3235	#define DCMI_CR_FCRC_0 0x00000100U
Kojto	122:f9eeca106725	3236	#define DCMI_CR_FCRC_1 0x00000200U
Kojto	122:f9eeca106725	3237	#define DCMI_CR_EDM_0 0x00000400U
Kojto	122:f9eeca106725	3238	#define DCMI_CR_EDM_1 0x00000800U
Kojto	122:f9eeca106725	3239	#define DCMI_CR_OUTEN 0x00002000U
Kojto	122:f9eeca106725	3240	#define DCMI_CR_ENABLE 0x00004000U
Kojto	122:f9eeca106725	3241	#define DCMI_CR_BSM_0 0x00010000U
Kojto	122:f9eeca106725	3242	#define DCMI_CR_BSM_1 0x00020000U
Kojto	122:f9eeca106725	3243	#define DCMI_CR_OEBS 0x00040000U
Kojto	122:f9eeca106725	3244	#define DCMI_CR_LSM 0x00080000U
Kojto	122:f9eeca106725	3245	#define DCMI_CR_OELS 0x00100000U
Kojto	110:165afa46840b	3246
Kojto	110:165afa46840b	3247	/****************** Bits definition for DCMI_SR register ****************/
Kojto	122:f9eeca106725	3248	#define DCMI_SR_HSYNC 0x00000001U
Kojto	122:f9eeca106725	3249	#define DCMI_SR_VSYNC 0x00000002U
Kojto	122:f9eeca106725	3250	#define DCMI_SR_FNE 0x00000004U
Kojto	122:f9eeca106725	3251
Kojto	122:f9eeca106725	3252	/****************** Bits definition for DCMI_RIS register ***************/
Kojto	122:f9eeca106725	3253	#define DCMI_RIS_FRAME_RIS 0x00000001U
Kojto	122:f9eeca106725	3254	#define DCMI_RIS_OVR_RIS 0x00000002U
Kojto	122:f9eeca106725	3255	#define DCMI_RIS_ERR_RIS 0x00000004U
Kojto	122:f9eeca106725	3256	#define DCMI_RIS_VSYNC_RIS 0x00000008U
Kojto	122:f9eeca106725	3257	#define DCMI_RIS_LINE_RIS 0x00000010U
Kojto	122:f9eeca106725	3258	/* Legacy defines */
Kojto	122:f9eeca106725	3259	#define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
Kojto	122:f9eeca106725	3260	#define DCMI_RISR_OVR_RIS DCMI_RIS_OVR_RIS
Kojto	122:f9eeca106725	3261	#define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
Kojto	122:f9eeca106725	3262	#define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
Kojto	122:f9eeca106725	3263	#define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
Kojto	122:f9eeca106725	3264	#define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
Kojto	110:165afa46840b	3265
Kojto	110:165afa46840b	3266	/****************** Bits definition for DCMI_IER register ***************/
Kojto	122:f9eeca106725	3267	#define DCMI_IER_FRAME_IE 0x00000001U
Kojto	122:f9eeca106725	3268	#define DCMI_IER_OVR_IE 0x00000002U
Kojto	122:f9eeca106725	3269	#define DCMI_IER_ERR_IE 0x00000004U
Kojto	122:f9eeca106725	3270	#define DCMI_IER_VSYNC_IE 0x00000008U
Kojto	122:f9eeca106725	3271	#define DCMI_IER_LINE_IE 0x00000010U
Kojto	122:f9eeca106725	3272	/* Legacy defines */
Kojto	122:f9eeca106725	3273	#define DCMI_IER_OVF_IE DCMI_IER_OVR_IE
Kojto	122:f9eeca106725	3274	/****************** Bits definition for DCMI_MIS register ***************/
Kojto	122:f9eeca106725	3275	#define DCMI_MIS_FRAME_MIS 0x00000001U
Kojto	122:f9eeca106725	3276	#define DCMI_MIS_OVR_MIS 0x00000002U
Kojto	122:f9eeca106725	3277	#define DCMI_MIS_ERR_MIS 0x00000004U
Kojto	122:f9eeca106725	3278	#define DCMI_MIS_VSYNC_MIS 0x00000008U
Kojto	122:f9eeca106725	3279	#define DCMI_MIS_LINE_MIS 0x00000010U
Kojto	122:f9eeca106725	3280
Kojto	122:f9eeca106725	3281	/* Legacy defines */
Kojto	122:f9eeca106725	3282	#define DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS
Kojto	122:f9eeca106725	3283	#define DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS
Kojto	122:f9eeca106725	3284	#define DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS
Kojto	122:f9eeca106725	3285	#define DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS
Kojto	122:f9eeca106725	3286	#define DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS
Kojto	110:165afa46840b	3287
Kojto	110:165afa46840b	3288	/****************** Bits definition for DCMI_ICR register ***************/
Kojto	122:f9eeca106725	3289	#define DCMI_ICR_FRAME_ISC 0x00000001U
Kojto	122:f9eeca106725	3290	#define DCMI_ICR_OVR_ISC 0x00000002U
Kojto	122:f9eeca106725	3291	#define DCMI_ICR_ERR_ISC 0x00000004U
Kojto	122:f9eeca106725	3292	#define DCMI_ICR_VSYNC_ISC 0x00000008U
Kojto	122:f9eeca106725	3293	#define DCMI_ICR_LINE_ISC 0x00000010U
Kojto	122:f9eeca106725	3294
Kojto	122:f9eeca106725	3295	/* Legacy defines */
Kojto	122:f9eeca106725	3296	#define DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC
Kojto	122:f9eeca106725	3297
Kojto	122:f9eeca106725	3298	/****************** Bits definition for DCMI_ESCR register ****************/
Kojto	122:f9eeca106725	3299	#define DCMI_ESCR_FSC 0x000000FFU
Kojto	122:f9eeca106725	3300	#define DCMI_ESCR_LSC 0x0000FF00U
Kojto	122:f9eeca106725	3301	#define DCMI_ESCR_LEC 0x00FF0000U
Kojto	122:f9eeca106725	3302	#define DCMI_ESCR_FEC 0xFF000000U
Kojto	122:f9eeca106725	3303
Kojto	122:f9eeca106725	3304	/****************** Bits definition for DCMI_ESUR register ****************/
Kojto	122:f9eeca106725	3305	#define DCMI_ESUR_FSU 0x000000FFU
Kojto	122:f9eeca106725	3306	#define DCMI_ESUR_LSU 0x0000FF00U
Kojto	122:f9eeca106725	3307	#define DCMI_ESUR_LEU 0x00FF0000U
Kojto	122:f9eeca106725	3308	#define DCMI_ESUR_FEU 0xFF000000U
Kojto	122:f9eeca106725	3309
Kojto	122:f9eeca106725	3310	/****************** Bits definition for DCMI_CWSTRT register ****************/
Kojto	122:f9eeca106725	3311	#define DCMI_CWSTRT_HOFFCNT 0x00003FFFU
Kojto	122:f9eeca106725	3312	#define DCMI_CWSTRT_VST 0x1FFF0000U
Kojto	122:f9eeca106725	3313
Kojto	122:f9eeca106725	3314	/****************** Bits definition for DCMI_CWSIZE register ****************/
Kojto	122:f9eeca106725	3315	#define DCMI_CWSIZE_CAPCNT 0x00003FFFU
Kojto	122:f9eeca106725	3316	#define DCMI_CWSIZE_VLINE 0x3FFF0000U
Kojto	122:f9eeca106725	3317
Kojto	122:f9eeca106725	3318	/****************** Bits definition for DCMI_DR register ****************/
Kojto	122:f9eeca106725	3319	#define DCMI_DR_BYTE0 0x000000FFU
Kojto	122:f9eeca106725	3320	#define DCMI_DR_BYTE1 0x0000FF00U
Kojto	122:f9eeca106725	3321	#define DCMI_DR_BYTE2 0x00FF0000U
Kojto	122:f9eeca106725	3322	#define DCMI_DR_BYTE3 0xFF000000U
Kojto	110:165afa46840b	3323
Kojto	110:165afa46840b	3324	/******************************************************************************/
Kojto	110:165afa46840b	3325	/* */
Kojto	110:165afa46840b	3326	/* DMA Controller */
Kojto	110:165afa46840b	3327	/* */
Kojto	110:165afa46840b	3328	/******************************************************************************/
Kojto	122:f9eeca106725	3329	/****************** Bits definition for DMA_SxCR register ***************/
Kojto	122:f9eeca106725	3330	#define DMA_SxCR_CHSEL 0x0E000000U
Kojto	122:f9eeca106725	3331	#define DMA_SxCR_CHSEL_0 0x02000000U
Kojto	122:f9eeca106725	3332	#define DMA_SxCR_CHSEL_1 0x04000000U
Kojto	122:f9eeca106725	3333	#define DMA_SxCR_CHSEL_2 0x08000000U
Kojto	122:f9eeca106725	3334	#define DMA_SxCR_MBURST 0x01800000U
Kojto	122:f9eeca106725	3335	#define DMA_SxCR_MBURST_0 0x00800000U
Kojto	122:f9eeca106725	3336	#define DMA_SxCR_MBURST_1 0x01000000U
Kojto	122:f9eeca106725	3337	#define DMA_SxCR_PBURST 0x00600000U
Kojto	122:f9eeca106725	3338	#define DMA_SxCR_PBURST_0 0x00200000U
Kojto	122:f9eeca106725	3339	#define DMA_SxCR_PBURST_1 0x00400000U
Kojto	122:f9eeca106725	3340	#define DMA_SxCR_CT 0x00080000U
Kojto	122:f9eeca106725	3341	#define DMA_SxCR_DBM 0x00040000U
Kojto	122:f9eeca106725	3342	#define DMA_SxCR_PL 0x00030000U
Kojto	122:f9eeca106725	3343	#define DMA_SxCR_PL_0 0x00010000U
Kojto	122:f9eeca106725	3344	#define DMA_SxCR_PL_1 0x00020000U
Kojto	122:f9eeca106725	3345	#define DMA_SxCR_PINCOS 0x00008000U
Kojto	122:f9eeca106725	3346	#define DMA_SxCR_MSIZE 0x00006000U
Kojto	122:f9eeca106725	3347	#define DMA_SxCR_MSIZE_0 0x00002000U
Kojto	122:f9eeca106725	3348	#define DMA_SxCR_MSIZE_1 0x00004000U
Kojto	122:f9eeca106725	3349	#define DMA_SxCR_PSIZE 0x00001800U
Kojto	122:f9eeca106725	3350	#define DMA_SxCR_PSIZE_0 0x00000800U
Kojto	122:f9eeca106725	3351	#define DMA_SxCR_PSIZE_1 0x00001000U
Kojto	122:f9eeca106725	3352	#define DMA_SxCR_MINC 0x00000400U
Kojto	122:f9eeca106725	3353	#define DMA_SxCR_PINC 0x00000200U
Kojto	122:f9eeca106725	3354	#define DMA_SxCR_CIRC 0x00000100U
Kojto	122:f9eeca106725	3355	#define DMA_SxCR_DIR 0x000000C0U
Kojto	122:f9eeca106725	3356	#define DMA_SxCR_DIR_0 0x00000040U
Kojto	122:f9eeca106725	3357	#define DMA_SxCR_DIR_1 0x00000080U
Kojto	122:f9eeca106725	3358	#define DMA_SxCR_PFCTRL 0x00000020U
Kojto	122:f9eeca106725	3359	#define DMA_SxCR_TCIE 0x00000010U
Kojto	122:f9eeca106725	3360	#define DMA_SxCR_HTIE 0x00000008U
Kojto	122:f9eeca106725	3361	#define DMA_SxCR_TEIE 0x00000004U
Kojto	122:f9eeca106725	3362	#define DMA_SxCR_DMEIE 0x00000002U
Kojto	122:f9eeca106725	3363	#define DMA_SxCR_EN 0x00000001U
Kojto	122:f9eeca106725	3364
Kojto	122:f9eeca106725	3365	/* Legacy defines */
Kojto	122:f9eeca106725	3366	#define DMA_SxCR_ACK 0x00100000U
Kojto	110:165afa46840b	3367
Kojto	110:165afa46840b	3368	/****************** Bits definition for DMA_SxCNDTR register ************/
Kojto	122:f9eeca106725	3369	#define DMA_SxNDT 0x0000FFFFU
Kojto	122:f9eeca106725	3370	#define DMA_SxNDT_0 0x00000001U
Kojto	122:f9eeca106725	3371	#define DMA_SxNDT_1 0x00000002U
Kojto	122:f9eeca106725	3372	#define DMA_SxNDT_2 0x00000004U
Kojto	122:f9eeca106725	3373	#define DMA_SxNDT_3 0x00000008U
Kojto	122:f9eeca106725	3374	#define DMA_SxNDT_4 0x00000010U
Kojto	122:f9eeca106725	3375	#define DMA_SxNDT_5 0x00000020U
Kojto	122:f9eeca106725	3376	#define DMA_SxNDT_6 0x00000040U
Kojto	122:f9eeca106725	3377	#define DMA_SxNDT_7 0x00000080U
Kojto	122:f9eeca106725	3378	#define DMA_SxNDT_8 0x00000100U
Kojto	122:f9eeca106725	3379	#define DMA_SxNDT_9 0x00000200U
Kojto	122:f9eeca106725	3380	#define DMA_SxNDT_10 0x00000400U
Kojto	122:f9eeca106725	3381	#define DMA_SxNDT_11 0x00000800U
Kojto	122:f9eeca106725	3382	#define DMA_SxNDT_12 0x00001000U
Kojto	122:f9eeca106725	3383	#define DMA_SxNDT_13 0x00002000U
Kojto	122:f9eeca106725	3384	#define DMA_SxNDT_14 0x00004000U
Kojto	122:f9eeca106725	3385	#define DMA_SxNDT_15 0x00008000U
Kojto	110:165afa46840b	3386
Kojto	110:165afa46840b	3387	/****************** Bits definition for DMA_SxFCR register **************/
Kojto	122:f9eeca106725	3388	#define DMA_SxFCR_FEIE 0x00000080U
Kojto	122:f9eeca106725	3389	#define DMA_SxFCR_FS 0x00000038U
Kojto	122:f9eeca106725	3390	#define DMA_SxFCR_FS_0 0x00000008U
Kojto	122:f9eeca106725	3391	#define DMA_SxFCR_FS_1 0x00000010U
Kojto	122:f9eeca106725	3392	#define DMA_SxFCR_FS_2 0x00000020U
Kojto	122:f9eeca106725	3393	#define DMA_SxFCR_DMDIS 0x00000004U
Kojto	122:f9eeca106725	3394	#define DMA_SxFCR_FTH 0x00000003U
Kojto	122:f9eeca106725	3395	#define DMA_SxFCR_FTH_0 0x00000001U
Kojto	122:f9eeca106725	3396	#define DMA_SxFCR_FTH_1 0x00000002U
Kojto	110:165afa46840b	3397
Kojto	110:165afa46840b	3398	/****************** Bits definition for DMA_LISR register ***************/
Kojto	122:f9eeca106725	3399	#define DMA_LISR_TCIF3 0x08000000U
Kojto	122:f9eeca106725	3400	#define DMA_LISR_HTIF3 0x04000000U
Kojto	122:f9eeca106725	3401	#define DMA_LISR_TEIF3 0x02000000U
Kojto	122:f9eeca106725	3402	#define DMA_LISR_DMEIF3 0x01000000U
Kojto	122:f9eeca106725	3403	#define DMA_LISR_FEIF3 0x00400000U
Kojto	122:f9eeca106725	3404	#define DMA_LISR_TCIF2 0x00200000U
Kojto	122:f9eeca106725	3405	#define DMA_LISR_HTIF2 0x00100000U
Kojto	122:f9eeca106725	3406	#define DMA_LISR_TEIF2 0x00080000U
Kojto	122:f9eeca106725	3407	#define DMA_LISR_DMEIF2 0x00040000U
Kojto	122:f9eeca106725	3408	#define DMA_LISR_FEIF2 0x00010000U
Kojto	122:f9eeca106725	3409	#define DMA_LISR_TCIF1 0x00000800U
Kojto	122:f9eeca106725	3410	#define DMA_LISR_HTIF1 0x00000400U
Kojto	122:f9eeca106725	3411	#define DMA_LISR_TEIF1 0x00000200U
Kojto	122:f9eeca106725	3412	#define DMA_LISR_DMEIF1 0x00000100U
Kojto	122:f9eeca106725	3413	#define DMA_LISR_FEIF1 0x00000040U
Kojto	122:f9eeca106725	3414	#define DMA_LISR_TCIF0 0x00000020U
Kojto	122:f9eeca106725	3415	#define DMA_LISR_HTIF0 0x00000010U
Kojto	122:f9eeca106725	3416	#define DMA_LISR_TEIF0 0x00000008U
Kojto	122:f9eeca106725	3417	#define DMA_LISR_DMEIF0 0x00000004U
Kojto	122:f9eeca106725	3418	#define DMA_LISR_FEIF0 0x00000001U
Kojto	110:165afa46840b	3419
Kojto	110:165afa46840b	3420	/****************** Bits definition for DMA_HISR register ***************/
Kojto	122:f9eeca106725	3421	#define DMA_HISR_TCIF7 0x08000000U
Kojto	122:f9eeca106725	3422	#define DMA_HISR_HTIF7 0x04000000U
Kojto	122:f9eeca106725	3423	#define DMA_HISR_TEIF7 0x02000000U
Kojto	122:f9eeca106725	3424	#define DMA_HISR_DMEIF7 0x01000000U
Kojto	122:f9eeca106725	3425	#define DMA_HISR_FEIF7 0x00400000U
Kojto	122:f9eeca106725	3426	#define DMA_HISR_TCIF6 0x00200000U
Kojto	122:f9eeca106725	3427	#define DMA_HISR_HTIF6 0x00100000U
Kojto	122:f9eeca106725	3428	#define DMA_HISR_TEIF6 0x00080000U
Kojto	122:f9eeca106725	3429	#define DMA_HISR_DMEIF6 0x00040000U
Kojto	122:f9eeca106725	3430	#define DMA_HISR_FEIF6 0x00010000U
Kojto	122:f9eeca106725	3431	#define DMA_HISR_TCIF5 0x00000800U
Kojto	122:f9eeca106725	3432	#define DMA_HISR_HTIF5 0x00000400U
Kojto	122:f9eeca106725	3433	#define DMA_HISR_TEIF5 0x00000200U
Kojto	122:f9eeca106725	3434	#define DMA_HISR_DMEIF5 0x00000100U
Kojto	122:f9eeca106725	3435	#define DMA_HISR_FEIF5 0x00000040U
Kojto	122:f9eeca106725	3436	#define DMA_HISR_TCIF4 0x00000020U
Kojto	122:f9eeca106725	3437	#define DMA_HISR_HTIF4 0x00000010U
Kojto	122:f9eeca106725	3438	#define DMA_HISR_TEIF4 0x00000008U
Kojto	122:f9eeca106725	3439	#define DMA_HISR_DMEIF4 0x00000004U
Kojto	122:f9eeca106725	3440	#define DMA_HISR_FEIF4 0x00000001U
Kojto	110:165afa46840b	3441
Kojto	110:165afa46840b	3442	/****************** Bits definition for DMA_LIFCR register **************/
Kojto	122:f9eeca106725	3443	#define DMA_LIFCR_CTCIF3 0x08000000U
Kojto	122:f9eeca106725	3444	#define DMA_LIFCR_CHTIF3 0x04000000U
Kojto	122:f9eeca106725	3445	#define DMA_LIFCR_CTEIF3 0x02000000U
Kojto	122:f9eeca106725	3446	#define DMA_LIFCR_CDMEIF3 0x01000000U
Kojto	122:f9eeca106725	3447	#define DMA_LIFCR_CFEIF3 0x00400000U
Kojto	122:f9eeca106725	3448	#define DMA_LIFCR_CTCIF2 0x00200000U
Kojto	122:f9eeca106725	3449	#define DMA_LIFCR_CHTIF2 0x00100000U
Kojto	122:f9eeca106725	3450	#define DMA_LIFCR_CTEIF2 0x00080000U
Kojto	122:f9eeca106725	3451	#define DMA_LIFCR_CDMEIF2 0x00040000U
Kojto	122:f9eeca106725	3452	#define DMA_LIFCR_CFEIF2 0x00010000U
Kojto	122:f9eeca106725	3453	#define DMA_LIFCR_CTCIF1 0x00000800U
Kojto	122:f9eeca106725	3454	#define DMA_LIFCR_CHTIF1 0x00000400U
Kojto	122:f9eeca106725	3455	#define DMA_LIFCR_CTEIF1 0x00000200U
Kojto	122:f9eeca106725	3456	#define DMA_LIFCR_CDMEIF1 0x00000100U
Kojto	122:f9eeca106725	3457	#define DMA_LIFCR_CFEIF1 0x00000040U
Kojto	122:f9eeca106725	3458	#define DMA_LIFCR_CTCIF0 0x00000020U
Kojto	122:f9eeca106725	3459	#define DMA_LIFCR_CHTIF0 0x00000010U
Kojto	122:f9eeca106725	3460	#define DMA_LIFCR_CTEIF0 0x00000008U
Kojto	122:f9eeca106725	3461	#define DMA_LIFCR_CDMEIF0 0x00000004U
Kojto	122:f9eeca106725	3462	#define DMA_LIFCR_CFEIF0 0x00000001U
Kojto	110:165afa46840b	3463
Kojto	110:165afa46840b	3464	/****************** Bits definition for DMA_HIFCR register **************/
Kojto	122:f9eeca106725	3465	#define DMA_HIFCR_CTCIF7 0x08000000U
Kojto	122:f9eeca106725	3466	#define DMA_HIFCR_CHTIF7 0x04000000U
Kojto	122:f9eeca106725	3467	#define DMA_HIFCR_CTEIF7 0x02000000U
Kojto	122:f9eeca106725	3468	#define DMA_HIFCR_CDMEIF7 0x01000000U
Kojto	122:f9eeca106725	3469	#define DMA_HIFCR_CFEIF7 0x00400000U
Kojto	122:f9eeca106725	3470	#define DMA_HIFCR_CTCIF6 0x00200000U
Kojto	122:f9eeca106725	3471	#define DMA_HIFCR_CHTIF6 0x00100000U
Kojto	122:f9eeca106725	3472	#define DMA_HIFCR_CTEIF6 0x00080000U
Kojto	122:f9eeca106725	3473	#define DMA_HIFCR_CDMEIF6 0x00040000U
Kojto	122:f9eeca106725	3474	#define DMA_HIFCR_CFEIF6 0x00010000U
Kojto	122:f9eeca106725	3475	#define DMA_HIFCR_CTCIF5 0x00000800U
Kojto	122:f9eeca106725	3476	#define DMA_HIFCR_CHTIF5 0x00000400U
Kojto	122:f9eeca106725	3477	#define DMA_HIFCR_CTEIF5 0x00000200U
Kojto	122:f9eeca106725	3478	#define DMA_HIFCR_CDMEIF5 0x00000100U
Kojto	122:f9eeca106725	3479	#define DMA_HIFCR_CFEIF5 0x00000040U
Kojto	122:f9eeca106725	3480	#define DMA_HIFCR_CTCIF4 0x00000020U
Kojto	122:f9eeca106725	3481	#define DMA_HIFCR_CHTIF4 0x00000010U
Kojto	122:f9eeca106725	3482	#define DMA_HIFCR_CTEIF4 0x00000008U
Kojto	122:f9eeca106725	3483	#define DMA_HIFCR_CDMEIF4 0x00000004U
Kojto	122:f9eeca106725	3484	#define DMA_HIFCR_CFEIF4 0x00000001U
Kojto	110:165afa46840b	3485
Kojto	110:165afa46840b	3486
Kojto	110:165afa46840b	3487	/******************************************************************************/
Kojto	110:165afa46840b	3488	/* */
Kojto	110:165afa46840b	3489	/* AHB Master DMA2D Controller (DMA2D) */
Kojto	110:165afa46840b	3490	/* */
Kojto	110:165afa46840b	3491	/******************************************************************************/
Kojto	110:165afa46840b	3492
Kojto	110:165afa46840b	3493	/****************** Bit definition for DMA2D_CR register ****************/
Kojto	110:165afa46840b	3494
Kojto	122:f9eeca106725	3495	#define DMA2D_CR_START 0x00000001U /!< Start transfer /
Kojto	122:f9eeca106725	3496	#define DMA2D_CR_SUSP 0x00000002U /!< Suspend transfer /
Kojto	122:f9eeca106725	3497	#define DMA2D_CR_ABORT 0x00000004U /!< Abort transfer /
Kojto	122:f9eeca106725	3498	#define DMA2D_CR_TEIE 0x00000100U /!< Transfer Error Interrupt Enable /
Kojto	122:f9eeca106725	3499	#define DMA2D_CR_TCIE 0x00000200U /!< Transfer Complete Interrupt Enable /
Kojto	122:f9eeca106725	3500	#define DMA2D_CR_TWIE 0x00000400U /!< Transfer Watermark Interrupt Enable /
Kojto	122:f9eeca106725	3501	#define DMA2D_CR_CAEIE 0x00000800U /!< CLUT Access Error Interrupt Enable /
Kojto	122:f9eeca106725	3502	#define DMA2D_CR_CTCIE 0x00001000U /!< CLUT Transfer Complete Interrupt Enable /
Kojto	122:f9eeca106725	3503	#define DMA2D_CR_CEIE 0x00002000U /!< Configuration Error Interrupt Enable /
Kojto	122:f9eeca106725	3504	#define DMA2D_CR_MODE 0x00030000U /!< DMA2D Mode[1:0] /
Kojto	122:f9eeca106725	3505	#define DMA2D_CR_MODE_0 0x00010000U /!< DMA2D Mode bit 0 /
Kojto	122:f9eeca106725	3506	#define DMA2D_CR_MODE_1 0x00020000U /!< DMA2D Mode bit 1 /
Kojto	110:165afa46840b	3507
Kojto	110:165afa46840b	3508	/****************** Bit definition for DMA2D_ISR register ***************/
Kojto	110:165afa46840b	3509
Kojto	122:f9eeca106725	3510	#define DMA2D_ISR_TEIF 0x00000001U /!< Transfer Error Interrupt Flag /
Kojto	122:f9eeca106725	3511	#define DMA2D_ISR_TCIF 0x00000002U /!< Transfer Complete Interrupt Flag /
Kojto	122:f9eeca106725	3512	#define DMA2D_ISR_TWIF 0x00000004U /!< Transfer Watermark Interrupt Flag /
Kojto	122:f9eeca106725	3513	#define DMA2D_ISR_CAEIF 0x00000008U /!< CLUT Access Error Interrupt Flag /
Kojto	122:f9eeca106725	3514	#define DMA2D_ISR_CTCIF 0x00000010U /!< CLUT Transfer Complete Interrupt Flag /
Kojto	122:f9eeca106725	3515	#define DMA2D_ISR_CEIF 0x00000020U /!< Configuration Error Interrupt Flag /
Kojto	122:f9eeca106725	3516
Kojto	122:f9eeca106725	3517	/****************** Bit definition for DMA2D_IFCR register **************/
Kojto	122:f9eeca106725	3518
Kojto	122:f9eeca106725	3519	#define DMA2D_IFCR_CTEIF 0x00000001U /!< Clears Transfer Error Interrupt Flag /
Kojto	122:f9eeca106725	3520	#define DMA2D_IFCR_CTCIF 0x00000002U /!< Clears Transfer Complete Interrupt Flag /
Kojto	122:f9eeca106725	3521	#define DMA2D_IFCR_CTWIF 0x00000004U /!< Clears Transfer Watermark Interrupt Flag /
Kojto	122:f9eeca106725	3522	#define DMA2D_IFCR_CAECIF 0x00000008U /!< Clears CLUT Access Error Interrupt Flag /
Kojto	122:f9eeca106725	3523	#define DMA2D_IFCR_CCTCIF 0x00000010U /!< Clears CLUT Transfer Complete Interrupt Flag /
Kojto	122:f9eeca106725	3524	#define DMA2D_IFCR_CCEIF 0x00000020U /!< Clears Configuration Error Interrupt Flag /
Kojto	122:f9eeca106725	3525
Kojto	122:f9eeca106725	3526	/* Legacy defines */
Kojto	122:f9eeca106725	3527	#define DMA2D_IFSR_CTEIF DMA2D_IFCR_CTEIF /!< Clears Transfer Error Interrupt Flag /
Kojto	122:f9eeca106725	3528	#define DMA2D_IFSR_CTCIF DMA2D_IFCR_CTCIF /!< Clears Transfer Complete Interrupt Flag /
Kojto	122:f9eeca106725	3529	#define DMA2D_IFSR_CTWIF DMA2D_IFCR_CTWIF /!< Clears Transfer Watermark Interrupt Flag /
Kojto	122:f9eeca106725	3530	#define DMA2D_IFSR_CCAEIF DMA2D_IFCR_CAECIF /!< Clears CLUT Access Error Interrupt Flag /
Kojto	122:f9eeca106725	3531	#define DMA2D_IFSR_CCTCIF DMA2D_IFCR_CCTCIF /!< Clears CLUT Transfer Complete Interrupt Flag /
Kojto	122:f9eeca106725	3532	#define DMA2D_IFSR_CCEIF DMA2D_IFCR_CCEIF /!< Clears Configuration Error Interrupt Flag /
Kojto	110:165afa46840b	3533
Kojto	110:165afa46840b	3534	/****************** Bit definition for DMA2D_FGMAR register *************/
Kojto	110:165afa46840b	3535
Kojto	122:f9eeca106725	3536	#define DMA2D_FGMAR_MA 0xFFFFFFFFU /!< Memory Address /
Kojto	110:165afa46840b	3537
Kojto	110:165afa46840b	3538	/****************** Bit definition for DMA2D_FGOR register **************/
Kojto	110:165afa46840b	3539
Kojto	122:f9eeca106725	3540	#define DMA2D_FGOR_LO 0x00003FFFU /!< Line Offset /
Kojto	110:165afa46840b	3541
Kojto	110:165afa46840b	3542	/****************** Bit definition for DMA2D_BGMAR register *************/
Kojto	110:165afa46840b	3543
Kojto	122:f9eeca106725	3544	#define DMA2D_BGMAR_MA 0xFFFFFFFFU /!< Memory Address /
Kojto	110:165afa46840b	3545
Kojto	110:165afa46840b	3546	/****************** Bit definition for DMA2D_BGOR register **************/
Kojto	110:165afa46840b	3547
Kojto	122:f9eeca106725	3548	#define DMA2D_BGOR_LO 0x00003FFFU /!< Line Offset /
Kojto	110:165afa46840b	3549
Kojto	110:165afa46840b	3550	/****************** Bit definition for DMA2D_FGPFCCR register ***********/
Kojto	110:165afa46840b	3551
Kojto	122:f9eeca106725	3552	#define DMA2D_FGPFCCR_CM 0x0000000FU /!< Input color mode CM[3:0] /
Kojto	122:f9eeca106725	3553	#define DMA2D_FGPFCCR_CM_0 0x00000001U /!< Input color mode CM bit 0 /
Kojto	122:f9eeca106725	3554	#define DMA2D_FGPFCCR_CM_1 0x00000002U /!< Input color mode CM bit 1 /
Kojto	122:f9eeca106725	3555	#define DMA2D_FGPFCCR_CM_2 0x00000004U /!< Input color mode CM bit 2 /
Kojto	122:f9eeca106725	3556	#define DMA2D_FGPFCCR_CM_3 0x00000008U /!< Input color mode CM bit 3 /
Kojto	122:f9eeca106725	3557	#define DMA2D_FGPFCCR_CCM 0x00000010U /!< CLUT Color mode /
Kojto	122:f9eeca106725	3558	#define DMA2D_FGPFCCR_START 0x00000020U /!< Start /
Kojto	122:f9eeca106725	3559	#define DMA2D_FGPFCCR_CS 0x0000FF00U /!< CLUT size /
Kojto	122:f9eeca106725	3560	#define DMA2D_FGPFCCR_AM 0x00030000U /!< Alpha mode AM[1:0] /
Kojto	122:f9eeca106725	3561	#define DMA2D_FGPFCCR_AM_0 0x00010000U /!< Alpha mode AM bit 0 /
Kojto	122:f9eeca106725	3562	#define DMA2D_FGPFCCR_AM_1 0x00020000U /!< Alpha mode AM bit 1 /
Kojto	122:f9eeca106725	3563	#define DMA2D_FGPFCCR_ALPHA 0xFF000000U /!< Alpha value /
Kojto	110:165afa46840b	3564
Kojto	110:165afa46840b	3565	/****************** Bit definition for DMA2D_FGCOLR register ************/
Kojto	110:165afa46840b	3566
Kojto	122:f9eeca106725	3567	#define DMA2D_FGCOLR_BLUE 0x000000FFU /!< Blue Value /
Kojto	122:f9eeca106725	3568	#define DMA2D_FGCOLR_GREEN 0x0000FF00U /!< Green Value /
Kojto	122:f9eeca106725	3569	#define DMA2D_FGCOLR_RED 0x00FF0000U /!< Red Value /
Kojto	110:165afa46840b	3570
Kojto	110:165afa46840b	3571	/****************** Bit definition for DMA2D_BGPFCCR register ***********/
Kojto	110:165afa46840b	3572
Kojto	122:f9eeca106725	3573	#define DMA2D_BGPFCCR_CM 0x0000000FU /!< Input color mode CM[3:0] /
Kojto	122:f9eeca106725	3574	#define DMA2D_BGPFCCR_CM_0 0x00000001U /!< Input color mode CM bit 0 /
Kojto	122:f9eeca106725	3575	#define DMA2D_BGPFCCR_CM_1 0x00000002U /!< Input color mode CM bit 1 /
Kojto	122:f9eeca106725	3576	#define DMA2D_BGPFCCR_CM_2 0x00000004U /!< Input color mode CM bit 2 /
Kojto	122:f9eeca106725	3577	#define DMA2D_FGPFCCR_CM_3 0x00000008U /!< Input color mode CM bit 3 /
Kojto	122:f9eeca106725	3578	#define DMA2D_BGPFCCR_CCM 0x00000010U /!< CLUT Color mode /
Kojto	122:f9eeca106725	3579	#define DMA2D_BGPFCCR_START 0x00000020U /!< Start /
Kojto	122:f9eeca106725	3580	#define DMA2D_BGPFCCR_CS 0x0000FF00U /!< CLUT size /
Kojto	122:f9eeca106725	3581	#define DMA2D_BGPFCCR_AM 0x00030000U /!< Alpha mode AM[1:0] /
Kojto	122:f9eeca106725	3582	#define DMA2D_BGPFCCR_AM_0 0x00010000U /!< Alpha mode AM bit 0 /
Kojto	122:f9eeca106725	3583	#define DMA2D_BGPFCCR_AM_1 0x00020000U /!< Alpha mode AM bit 1 /
Kojto	122:f9eeca106725	3584	#define DMA2D_BGPFCCR_ALPHA 0xFF000000U /!< background Input Alpha value /
Kojto	110:165afa46840b	3585
Kojto	110:165afa46840b	3586	/****************** Bit definition for DMA2D_BGCOLR register ************/
Kojto	110:165afa46840b	3587
Kojto	122:f9eeca106725	3588	#define DMA2D_BGCOLR_BLUE 0x000000FFU /!< Blue Value /
Kojto	122:f9eeca106725	3589	#define DMA2D_BGCOLR_GREEN 0x0000FF00U /!< Green Value /
Kojto	122:f9eeca106725	3590	#define DMA2D_BGCOLR_RED 0x00FF0000U /!< Red Value /
Kojto	110:165afa46840b	3591
Kojto	110:165afa46840b	3592	/****************** Bit definition for DMA2D_FGCMAR register ************/
Kojto	110:165afa46840b	3593
Kojto	122:f9eeca106725	3594	#define DMA2D_FGCMAR_MA 0xFFFFFFFFU /!< Memory Address /
Kojto	110:165afa46840b	3595
Kojto	110:165afa46840b	3596	/****************** Bit definition for DMA2D_BGCMAR register ************/
Kojto	110:165afa46840b	3597
Kojto	122:f9eeca106725	3598	#define DMA2D_BGCMAR_MA 0xFFFFFFFFU /!< Memory Address /
Kojto	110:165afa46840b	3599
Kojto	110:165afa46840b	3600	/****************** Bit definition for DMA2D_OPFCCR register ************/
Kojto	110:165afa46840b	3601
Kojto	122:f9eeca106725	3602	#define DMA2D_OPFCCR_CM 0x00000007U /!< Color mode CM[2:0] /
Kojto	122:f9eeca106725	3603	#define DMA2D_OPFCCR_CM_0 0x00000001U /!< Color mode CM bit 0 /
Kojto	122:f9eeca106725	3604	#define DMA2D_OPFCCR_CM_1 0x00000002U /!< Color mode CM bit 1 /
Kojto	122:f9eeca106725	3605	#define DMA2D_OPFCCR_CM_2 0x00000004U /!< Color mode CM bit 2 /
Kojto	110:165afa46840b	3606
Kojto	110:165afa46840b	3607	/****************** Bit definition for DMA2D_OCOLR register *************/
Kojto	110:165afa46840b	3608
Kojto	110:165afa46840b	3609	/!<Mode_ARGB8888/RGB888 /
Kojto	110:165afa46840b	3610
Kojto	122:f9eeca106725	3611	#define DMA2D_OCOLR_BLUE_1 0x000000FFU /!< BLUE Value /
Kojto	122:f9eeca106725	3612	#define DMA2D_OCOLR_GREEN_1 0x0000FF00U /!< GREEN Value /
Kojto	122:f9eeca106725	3613	#define DMA2D_OCOLR_RED_1 0x00FF0000U /!< Red Value /
Kojto	122:f9eeca106725	3614	#define DMA2D_OCOLR_ALPHA_1 0xFF000000U /!< Alpha Channel Value /
Kojto	110:165afa46840b	3615
Kojto	110:165afa46840b	3616	/!<Mode_RGB565 /
Kojto	122:f9eeca106725	3617	#define DMA2D_OCOLR_BLUE_2 0x0000001FU /!< BLUE Value /
Kojto	122:f9eeca106725	3618	#define DMA2D_OCOLR_GREEN_2 0x000007E0U /!< GREEN Value /
Kojto	122:f9eeca106725	3619	#define DMA2D_OCOLR_RED_2 0x0000F800U /!< Red Value /
Kojto	110:165afa46840b	3620
Kojto	110:165afa46840b	3621	/!<Mode_ARGB1555 /
Kojto	122:f9eeca106725	3622	#define DMA2D_OCOLR_BLUE_3 0x0000001FU /!< BLUE Value /
Kojto	122:f9eeca106725	3623	#define DMA2D_OCOLR_GREEN_3 0x000003E0U /!< GREEN Value /
Kojto	122:f9eeca106725	3624	#define DMA2D_OCOLR_RED_3 0x00007C00U /!< Red Value /
Kojto	122:f9eeca106725	3625	#define DMA2D_OCOLR_ALPHA_3 0x00008000U /!< Alpha Channel Value /
Kojto	110:165afa46840b	3626
Kojto	110:165afa46840b	3627	/!<Mode_ARGB4444 /
Kojto	122:f9eeca106725	3628	#define DMA2D_OCOLR_BLUE_4 0x0000000FU /!< BLUE Value /
Kojto	122:f9eeca106725	3629	#define DMA2D_OCOLR_GREEN_4 0x000000F0U /!< GREEN Value /
Kojto	122:f9eeca106725	3630	#define DMA2D_OCOLR_RED_4 0x00000F00U /!< Red Value /
Kojto	122:f9eeca106725	3631	#define DMA2D_OCOLR_ALPHA_4 0x0000F000U /!< Alpha Channel Value /
Kojto	110:165afa46840b	3632
Kojto	110:165afa46840b	3633	/****************** Bit definition for DMA2D_OMAR register **************/
Kojto	110:165afa46840b	3634
Kojto	122:f9eeca106725	3635	#define DMA2D_OMAR_MA 0xFFFFFFFFU /!< Memory Address /
Kojto	110:165afa46840b	3636
Kojto	110:165afa46840b	3637	/****************** Bit definition for DMA2D_OOR register ***************/
Kojto	110:165afa46840b	3638
Kojto	122:f9eeca106725	3639	#define DMA2D_OOR_LO 0x00003FFFU /!< Line Offset /
Kojto	110:165afa46840b	3640
Kojto	110:165afa46840b	3641	/****************** Bit definition for DMA2D_NLR register ***************/
Kojto	110:165afa46840b	3642
Kojto	122:f9eeca106725	3643	#define DMA2D_NLR_NL 0x0000FFFFU /!< Number of Lines /
Kojto	122:f9eeca106725	3644	#define DMA2D_NLR_PL 0x3FFF0000U /!< Pixel per Lines /
Kojto	110:165afa46840b	3645
Kojto	110:165afa46840b	3646	/****************** Bit definition for DMA2D_LWR register ***************/
Kojto	110:165afa46840b	3647
Kojto	122:f9eeca106725	3648	#define DMA2D_LWR_LW 0x0000FFFFU /!< Line Watermark /
Kojto	110:165afa46840b	3649
Kojto	110:165afa46840b	3650	/****************** Bit definition for DMA2D_AMTCR register *************/
Kojto	110:165afa46840b	3651
Kojto	122:f9eeca106725	3652	#define DMA2D_AMTCR_EN 0x00000001U /!< Enable /
Kojto	122:f9eeca106725	3653	#define DMA2D_AMTCR_DT 0x0000FF00U /!< Dead Time /
Kojto	110:165afa46840b	3654
Kojto	110:165afa46840b	3655	/****************** Bit definition for DMA2D_FGCLUT register ************/
Kojto	110:165afa46840b	3656
Kojto	110:165afa46840b	3657	/****************** Bit definition for DMA2D_BGCLUT register ************/
Kojto	110:165afa46840b	3658
Kojto	110:165afa46840b	3659
Kojto	110:165afa46840b	3660	/******************************************************************************/
Kojto	110:165afa46840b	3661	/* */
Kojto	110:165afa46840b	3662	/* Display Serial Interface (DSI) */
Kojto	110:165afa46840b	3663	/* */
Kojto	110:165afa46840b	3664	/******************************************************************************/
Kojto	110:165afa46840b	3665	/***************** Bit definition for DSI_VR register ***************/
Kojto	122:f9eeca106725	3666	#define DSI_VR 0x3133302AU /!< DSI Host Version /
Kojto	110:165afa46840b	3667
Kojto	110:165afa46840b	3668	/***************** Bit definition for DSI_CR register ***************/
Kojto	122:f9eeca106725	3669	#define DSI_CR_EN 0x00000001U /!< DSI Host power up and reset /
Kojto	110:165afa46840b	3670
Kojto	110:165afa46840b	3671	/***************** Bit definition for DSI_CCR register **************/
Kojto	122:f9eeca106725	3672	#define DSI_CCR_TXECKDIV 0x000000FFU /!< TX Escape Clock Division /
Kojto	122:f9eeca106725	3673	#define DSI_CCR_TXECKDIV0 0x00000001U
Kojto	122:f9eeca106725	3674	#define DSI_CCR_TXECKDIV1 0x00000002U
Kojto	122:f9eeca106725	3675	#define DSI_CCR_TXECKDIV2 0x00000004U
Kojto	122:f9eeca106725	3676	#define DSI_CCR_TXECKDIV3 0x00000008U
Kojto	122:f9eeca106725	3677	#define DSI_CCR_TXECKDIV4 0x00000010U
Kojto	122:f9eeca106725	3678	#define DSI_CCR_TXECKDIV5 0x00000020U
Kojto	122:f9eeca106725	3679	#define DSI_CCR_TXECKDIV6 0x00000040U
Kojto	122:f9eeca106725	3680	#define DSI_CCR_TXECKDIV7 0x00000080U
Kojto	122:f9eeca106725	3681
Kojto	122:f9eeca106725	3682	#define DSI_CCR_TOCKDIV 0x0000FF00U /!< Timeout Clock Division /
Kojto	122:f9eeca106725	3683	#define DSI_CCR_TOCKDIV0 0x00000100U
Kojto	122:f9eeca106725	3684	#define DSI_CCR_TOCKDIV1 0x00000200U
Kojto	122:f9eeca106725	3685	#define DSI_CCR_TOCKDIV2 0x00000400U
Kojto	122:f9eeca106725	3686	#define DSI_CCR_TOCKDIV3 0x00000800U
Kojto	122:f9eeca106725	3687	#define DSI_CCR_TOCKDIV4 0x00001000U
Kojto	122:f9eeca106725	3688	#define DSI_CCR_TOCKDIV5 0x00002000U
Kojto	122:f9eeca106725	3689	#define DSI_CCR_TOCKDIV6 0x00004000U
Kojto	122:f9eeca106725	3690	#define DSI_CCR_TOCKDIV7 0x00008000U
Kojto	110:165afa46840b	3691
Kojto	110:165afa46840b	3692	/***************** Bit definition for DSI_LVCIDR register ***********/
Kojto	122:f9eeca106725	3693	#define DSI_LVCIDR_VCID 0x00000003U /!< Virtual Channel ID /
Kojto	122:f9eeca106725	3694	#define DSI_LVCIDR_VCID0 0x00000001U
Kojto	122:f9eeca106725	3695	#define DSI_LVCIDR_VCID1 0x00000002U
Kojto	110:165afa46840b	3696
Kojto	110:165afa46840b	3697	/***************** Bit definition for DSI_LCOLCR register ***********/
Kojto	122:f9eeca106725	3698	#define DSI_LCOLCR_COLC 0x0000000FU /!< Color Coding /
Kojto	122:f9eeca106725	3699	#define DSI_LCOLCR_COLC0 0x00000001U
Kojto	122:f9eeca106725	3700	#define DSI_LCOLCR_COLC1 0x00000020U
Kojto	122:f9eeca106725	3701	#define DSI_LCOLCR_COLC2 0x00000040U
Kojto	122:f9eeca106725	3702	#define DSI_LCOLCR_COLC3 0x00000080U
Kojto	122:f9eeca106725	3703
Kojto	122:f9eeca106725	3704	#define DSI_LCOLCR_LPE 0x00000100U /!< Loosly Packet Enable /
Kojto	110:165afa46840b	3705
Kojto	110:165afa46840b	3706	/***************** Bit definition for DSI_LPCR register *************/
Kojto	122:f9eeca106725	3707	#define DSI_LPCR_DEP 0x00000001U /!< Data Enable Polarity /
Kojto	122:f9eeca106725	3708	#define DSI_LPCR_VSP 0x00000002U /!< VSYNC Polarity /
Kojto	122:f9eeca106725	3709	#define DSI_LPCR_HSP 0x00000004U /!< HSYNC Polarity /
Kojto	110:165afa46840b	3710
Kojto	110:165afa46840b	3711	/***************** Bit definition for DSI_LPMCR register ************/
Kojto	122:f9eeca106725	3712	#define DSI_LPMCR_VLPSIZE 0x000000FFU /!< VACT Largest Packet Size /
Kojto	122:f9eeca106725	3713	#define DSI_LPMCR_VLPSIZE0 0x00000001U
Kojto	122:f9eeca106725	3714	#define DSI_LPMCR_VLPSIZE1 0x00000002U
Kojto	122:f9eeca106725	3715	#define DSI_LPMCR_VLPSIZE2 0x00000004U
Kojto	122:f9eeca106725	3716	#define DSI_LPMCR_VLPSIZE3 0x00000008U
Kojto	122:f9eeca106725	3717	#define DSI_LPMCR_VLPSIZE4 0x00000010U
Kojto	122:f9eeca106725	3718	#define DSI_LPMCR_VLPSIZE5 0x00000020U
Kojto	122:f9eeca106725	3719	#define DSI_LPMCR_VLPSIZE6 0x00000040U
Kojto	122:f9eeca106725	3720	#define DSI_LPMCR_VLPSIZE7 0x00000080U
Kojto	122:f9eeca106725	3721
Kojto	122:f9eeca106725	3722	#define DSI_LPMCR_LPSIZE 0x00FF0000U /!< Largest Packet Size /
Kojto	122:f9eeca106725	3723	#define DSI_LPMCR_LPSIZE0 0x00010000U
Kojto	122:f9eeca106725	3724	#define DSI_LPMCR_LPSIZE1 0x00020000U
Kojto	122:f9eeca106725	3725	#define DSI_LPMCR_LPSIZE2 0x00040000U
Kojto	122:f9eeca106725	3726	#define DSI_LPMCR_LPSIZE3 0x00080000U
Kojto	122:f9eeca106725	3727	#define DSI_LPMCR_LPSIZE4 0x00100000U
Kojto	122:f9eeca106725	3728	#define DSI_LPMCR_LPSIZE5 0x00200000U
Kojto	122:f9eeca106725	3729	#define DSI_LPMCR_LPSIZE6 0x00400000U
Kojto	122:f9eeca106725	3730	#define DSI_LPMCR_LPSIZE7 0x00800000U
Kojto	110:165afa46840b	3731
Kojto	110:165afa46840b	3732	/***************** Bit definition for DSI_PCR register **************/
Kojto	122:f9eeca106725	3733	#define DSI_PCR_ETTXE 0x00000001U /!< EoTp Transmission Enable /
Kojto	122:f9eeca106725	3734	#define DSI_PCR_ETRXE 0x00000002U /!< EoTp Reception Enable /
Kojto	122:f9eeca106725	3735	#define DSI_PCR_BTAE 0x00000004U /!< Bus Turn Around Enable /
Kojto	122:f9eeca106725	3736	#define DSI_PCR_ECCRXE 0x00000008U /!< ECC Reception Enable /
Kojto	122:f9eeca106725	3737	#define DSI_PCR_CRCRXE 0x00000010U /!< CRC Reception Enable /
Kojto	110:165afa46840b	3738
Kojto	110:165afa46840b	3739	/***************** Bit definition for DSI_GVCIDR register ***********/
Kojto	122:f9eeca106725	3740	#define DSI_GVCIDR_VCID 0x00000003U /!< Virtual Channel ID /
Kojto	122:f9eeca106725	3741	#define DSI_GVCIDR_VCID0 0x00000001U
Kojto	122:f9eeca106725	3742	#define DSI_GVCIDR_VCID1 0x00000002U
Kojto	110:165afa46840b	3743
Kojto	110:165afa46840b	3744	/***************** Bit definition for DSI_MCR register **************/
Kojto	122:f9eeca106725	3745	#define DSI_MCR_CMDM 0x00000001U /!< Command Mode /
Kojto	110:165afa46840b	3746
Kojto	110:165afa46840b	3747	/***************** Bit definition for DSI_VMCR register *************/
Kojto	122:f9eeca106725	3748	#define DSI_VMCR_VMT 0x00000003U /!< Video Mode Type /
Kojto	122:f9eeca106725	3749	#define DSI_VMCR_VMT0 0x00000001U
Kojto	122:f9eeca106725	3750	#define DSI_VMCR_VMT1 0x00000002U
Kojto	122:f9eeca106725	3751
Kojto	122:f9eeca106725	3752	#define DSI_VMCR_LPVSAE 0x00000100U /!< Low-Power Vertical Sync Active Enable /
Kojto	122:f9eeca106725	3753	#define DSI_VMCR_LPVBPE 0x00000200U /!< Low-power Vertical Back-Porch Enable /
Kojto	122:f9eeca106725	3754	#define DSI_VMCR_LPVFPE 0x00000400U /!< Low-power Vertical Front-porch Enable /
Kojto	122:f9eeca106725	3755	#define DSI_VMCR_LPVAE 0x00000800U /!< Low-Power Vertical Active Enable /
Kojto	122:f9eeca106725	3756	#define DSI_VMCR_LPHBPE 0x00001000U /!< Low-Power Horizontal Back-Porch Enable /
Kojto	122:f9eeca106725	3757	#define DSI_VMCR_LPHFPE 0x00002000U /!< Low-Power Horizontal Front-Porch Enable /
Kojto	122:f9eeca106725	3758	#define DSI_VMCR_FBTAAE 0x00004000U /!< Frame Bus-Turn-Around Acknowledge Enable /
Kojto	122:f9eeca106725	3759	#define DSI_VMCR_LPCE 0x00008000U /!< Low-Power Command Enable /
Kojto	122:f9eeca106725	3760	#define DSI_VMCR_PGE 0x00010000U /!< Pattern Generator Enable /
Kojto	122:f9eeca106725	3761	#define DSI_VMCR_PGM 0x00100000U /!< Pattern Generator Mode /
Kojto	122:f9eeca106725	3762	#define DSI_VMCR_PGO 0x01000000U /!< Pattern Generator Orientation /
Kojto	110:165afa46840b	3763
Kojto	110:165afa46840b	3764	/***************** Bit definition for DSI_VPCR register *************/
Kojto	122:f9eeca106725	3765	#define DSI_VPCR_VPSIZE 0x00003FFFU /!< Video Packet Size /
Kojto	122:f9eeca106725	3766	#define DSI_VPCR_VPSIZE0 0x00000001U
Kojto	122:f9eeca106725	3767	#define DSI_VPCR_VPSIZE1 0x00000002U
Kojto	122:f9eeca106725	3768	#define DSI_VPCR_VPSIZE2 0x00000004U
Kojto	122:f9eeca106725	3769	#define DSI_VPCR_VPSIZE3 0x00000008U
Kojto	122:f9eeca106725	3770	#define DSI_VPCR_VPSIZE4 0x00000010U
Kojto	122:f9eeca106725	3771	#define DSI_VPCR_VPSIZE5 0x00000020U
Kojto	122:f9eeca106725	3772	#define DSI_VPCR_VPSIZE6 0x00000040U
Kojto	122:f9eeca106725	3773	#define DSI_VPCR_VPSIZE7 0x00000080U
Kojto	122:f9eeca106725	3774	#define DSI_VPCR_VPSIZE8 0x00000100U
Kojto	122:f9eeca106725	3775	#define DSI_VPCR_VPSIZE9 0x00000200U
Kojto	122:f9eeca106725	3776	#define DSI_VPCR_VPSIZE10 0x00000400U
Kojto	122:f9eeca106725	3777	#define DSI_VPCR_VPSIZE11 0x00000800U
Kojto	122:f9eeca106725	3778	#define DSI_VPCR_VPSIZE12 0x00001000U
Kojto	122:f9eeca106725	3779	#define DSI_VPCR_VPSIZE13 0x00002000U
Kojto	110:165afa46840b	3780
Kojto	110:165afa46840b	3781	/***************** Bit definition for DSI_VCCR register *************/
Kojto	122:f9eeca106725	3782	#define DSI_VCCR_NUMC 0x00001FFFU /!< Number of Chunks /
Kojto	122:f9eeca106725	3783	#define DSI_VCCR_NUMC0 0x00000001U
Kojto	122:f9eeca106725	3784	#define DSI_VCCR_NUMC1 0x00000002U
Kojto	122:f9eeca106725	3785	#define DSI_VCCR_NUMC2 0x00000004U
Kojto	122:f9eeca106725	3786	#define DSI_VCCR_NUMC3 0x00000008U
Kojto	122:f9eeca106725	3787	#define DSI_VCCR_NUMC4 0x00000010U
Kojto	122:f9eeca106725	3788	#define DSI_VCCR_NUMC5 0x00000020U
Kojto	122:f9eeca106725	3789	#define DSI_VCCR_NUMC6 0x00000040U
Kojto	122:f9eeca106725	3790	#define DSI_VCCR_NUMC7 0x00000080U
Kojto	122:f9eeca106725	3791	#define DSI_VCCR_NUMC8 0x00000100U
Kojto	122:f9eeca106725	3792	#define DSI_VCCR_NUMC9 0x00000200U
Kojto	122:f9eeca106725	3793	#define DSI_VCCR_NUMC10 0x00000400U
Kojto	122:f9eeca106725	3794	#define DSI_VCCR_NUMC11 0x00000800U
Kojto	122:f9eeca106725	3795	#define DSI_VCCR_NUMC12 0x00001000U
Kojto	110:165afa46840b	3796
Kojto	110:165afa46840b	3797	/***************** Bit definition for DSI_VNPCR register ************/
Kojto	122:f9eeca106725	3798	#define DSI_VNPCR_NPSIZE 0x00001FFFU /!< Null Packet Size /
Kojto	122:f9eeca106725	3799	#define DSI_VNPCR_NPSIZE0 0x00000001U
Kojto	122:f9eeca106725	3800	#define DSI_VNPCR_NPSIZE1 0x00000002U
Kojto	122:f9eeca106725	3801	#define DSI_VNPCR_NPSIZE2 0x00000004U
Kojto	122:f9eeca106725	3802	#define DSI_VNPCR_NPSIZE3 0x00000008U
Kojto	122:f9eeca106725	3803	#define DSI_VNPCR_NPSIZE4 0x00000010U
Kojto	122:f9eeca106725	3804	#define DSI_VNPCR_NPSIZE5 0x00000020U
Kojto	122:f9eeca106725	3805	#define DSI_VNPCR_NPSIZE6 0x00000040U
Kojto	122:f9eeca106725	3806	#define DSI_VNPCR_NPSIZE7 0x00000080U
Kojto	122:f9eeca106725	3807	#define DSI_VNPCR_NPSIZE8 0x00000100U
Kojto	122:f9eeca106725	3808	#define DSI_VNPCR_NPSIZE9 0x00000200U
Kojto	122:f9eeca106725	3809	#define DSI_VNPCR_NPSIZE10 0x00000400U
Kojto	122:f9eeca106725	3810	#define DSI_VNPCR_NPSIZE11 0x00000800U
Kojto	122:f9eeca106725	3811	#define DSI_VNPCR_NPSIZE12 0x00001000U
Kojto	110:165afa46840b	3812
Kojto	110:165afa46840b	3813	/***************** Bit definition for DSI_VHSACR register ***********/
Kojto	122:f9eeca106725	3814	#define DSI_VHSACR_HSA 0x00000FFFU /!< Horizontal Synchronism Active duration /
Kojto	122:f9eeca106725	3815	#define DSI_VHSACR_HSA0 0x00000001U
Kojto	122:f9eeca106725	3816	#define DSI_VHSACR_HSA1 0x00000002U
Kojto	122:f9eeca106725	3817	#define DSI_VHSACR_HSA2 0x00000004U
Kojto	122:f9eeca106725	3818	#define DSI_VHSACR_HSA3 0x00000008U
Kojto	122:f9eeca106725	3819	#define DSI_VHSACR_HSA4 0x00000010U
Kojto	122:f9eeca106725	3820	#define DSI_VHSACR_HSA5 0x00000020U
Kojto	122:f9eeca106725	3821	#define DSI_VHSACR_HSA6 0x00000040U
Kojto	122:f9eeca106725	3822	#define DSI_VHSACR_HSA7 0x00000080U
Kojto	122:f9eeca106725	3823	#define DSI_VHSACR_HSA8 0x00000100U
Kojto	122:f9eeca106725	3824	#define DSI_VHSACR_HSA9 0x00000200U
Kojto	122:f9eeca106725	3825	#define DSI_VHSACR_HSA10 0x00000400U
Kojto	122:f9eeca106725	3826	#define DSI_VHSACR_HSA11 0x00000800U
Kojto	110:165afa46840b	3827
Kojto	110:165afa46840b	3828	/***************** Bit definition for DSI_VHBPCR register ***********/
Kojto	122:f9eeca106725	3829	#define DSI_VHBPCR_HBP 0x00000FFFU /!< Horizontal Back-Porch duration /
Kojto	122:f9eeca106725	3830	#define DSI_VHBPCR_HBP0 0x00000001U
Kojto	122:f9eeca106725	3831	#define DSI_VHBPCR_HBP1 0x00000002U
Kojto	122:f9eeca106725	3832	#define DSI_VHBPCR_HBP2 0x00000004U
Kojto	122:f9eeca106725	3833	#define DSI_VHBPCR_HBP3 0x00000008U
Kojto	122:f9eeca106725	3834	#define DSI_VHBPCR_HBP4 0x00000010U
Kojto	122:f9eeca106725	3835	#define DSI_VHBPCR_HBP5 0x00000020U
Kojto	122:f9eeca106725	3836	#define DSI_VHBPCR_HBP6 0x00000040U
Kojto	122:f9eeca106725	3837	#define DSI_VHBPCR_HBP7 0x00000080U
Kojto	122:f9eeca106725	3838	#define DSI_VHBPCR_HBP8 0x00000100U
Kojto	122:f9eeca106725	3839	#define DSI_VHBPCR_HBP9 0x00000200U
Kojto	122:f9eeca106725	3840	#define DSI_VHBPCR_HBP10 0x00000400U
Kojto	122:f9eeca106725	3841	#define DSI_VHBPCR_HBP11 0x00000800U
Kojto	110:165afa46840b	3842
Kojto	110:165afa46840b	3843	/***************** Bit definition for DSI_VLCR register *************/
Kojto	122:f9eeca106725	3844	#define DSI_VLCR_HLINE 0x00007FFFU /!< Horizontal Line duration /
Kojto	122:f9eeca106725	3845	#define DSI_VLCR_HLINE0 0x00000001U
Kojto	122:f9eeca106725	3846	#define DSI_VLCR_HLINE1 0x00000002U
Kojto	122:f9eeca106725	3847	#define DSI_VLCR_HLINE2 0x00000004U
Kojto	122:f9eeca106725	3848	#define DSI_VLCR_HLINE3 0x00000008U
Kojto	122:f9eeca106725	3849	#define DSI_VLCR_HLINE4 0x00000010U
Kojto	122:f9eeca106725	3850	#define DSI_VLCR_HLINE5 0x00000020U
Kojto	122:f9eeca106725	3851	#define DSI_VLCR_HLINE6 0x00000040U
Kojto	122:f9eeca106725	3852	#define DSI_VLCR_HLINE7 0x00000080U
Kojto	122:f9eeca106725	3853	#define DSI_VLCR_HLINE8 0x00000100U
Kojto	122:f9eeca106725	3854	#define DSI_VLCR_HLINE9 0x00000200U
Kojto	122:f9eeca106725	3855	#define DSI_VLCR_HLINE10 0x00000400U
Kojto	122:f9eeca106725	3856	#define DSI_VLCR_HLINE11 0x00000800U
Kojto	122:f9eeca106725	3857	#define DSI_VLCR_HLINE12 0x00001000U
Kojto	122:f9eeca106725	3858	#define DSI_VLCR_HLINE13 0x00002000U
Kojto	122:f9eeca106725	3859	#define DSI_VLCR_HLINE14 0x00004000U
Kojto	110:165afa46840b	3860
Kojto	110:165afa46840b	3861	/***************** Bit definition for DSI_VVSACR register ***********/
Kojto	122:f9eeca106725	3862	#define DSI_VVSACR_VSA 0x000003FFU /!< Vertical Synchronism Active duration /
Kojto	122:f9eeca106725	3863	#define DSI_VVSACR_VSA0 0x00000001U
Kojto	122:f9eeca106725	3864	#define DSI_VVSACR_VSA1 0x00000002U
Kojto	122:f9eeca106725	3865	#define DSI_VVSACR_VSA2 0x00000004U
Kojto	122:f9eeca106725	3866	#define DSI_VVSACR_VSA3 0x00000008U
Kojto	122:f9eeca106725	3867	#define DSI_VVSACR_VSA4 0x00000010U
Kojto	122:f9eeca106725	3868	#define DSI_VVSACR_VSA5 0x00000020U
Kojto	122:f9eeca106725	3869	#define DSI_VVSACR_VSA6 0x00000040U
Kojto	122:f9eeca106725	3870	#define DSI_VVSACR_VSA7 0x00000080U
Kojto	122:f9eeca106725	3871	#define DSI_VVSACR_VSA8 0x00000100U
Kojto	122:f9eeca106725	3872	#define DSI_VVSACR_VSA9 0x00000200U
Kojto	110:165afa46840b	3873
Kojto	110:165afa46840b	3874	/***************** Bit definition for DSI_VVBPCR register ***********/
Kojto	122:f9eeca106725	3875	#define DSI_VVBPCR_VBP 0x000003FFU /!< Vertical Back-Porch duration /
Kojto	122:f9eeca106725	3876	#define DSI_VVBPCR_VBP0 0x00000001U
Kojto	122:f9eeca106725	3877	#define DSI_VVBPCR_VBP1 0x00000002U
Kojto	122:f9eeca106725	3878	#define DSI_VVBPCR_VBP2 0x00000004U
Kojto	122:f9eeca106725	3879	#define DSI_VVBPCR_VBP3 0x00000008U
Kojto	122:f9eeca106725	3880	#define DSI_VVBPCR_VBP4 0x00000010U
Kojto	122:f9eeca106725	3881	#define DSI_VVBPCR_VBP5 0x00000020U
Kojto	122:f9eeca106725	3882	#define DSI_VVBPCR_VBP6 0x00000040U
Kojto	122:f9eeca106725	3883	#define DSI_VVBPCR_VBP7 0x00000080U
Kojto	122:f9eeca106725	3884	#define DSI_VVBPCR_VBP8 0x00000100U
Kojto	122:f9eeca106725	3885	#define DSI_VVBPCR_VBP9 0x00000200U
Kojto	110:165afa46840b	3886
Kojto	110:165afa46840b	3887	/***************** Bit definition for DSI_VVFPCR register ***********/
Kojto	122:f9eeca106725	3888	#define DSI_VVFPCR_VFP 0x000003FFU /!< Vertical Front-Porch duration /
Kojto	122:f9eeca106725	3889	#define DSI_VVFPCR_VFP0 0x00000001U
Kojto	122:f9eeca106725	3890	#define DSI_VVFPCR_VFP1 0x00000002U
Kojto	122:f9eeca106725	3891	#define DSI_VVFPCR_VFP2 0x00000004U
Kojto	122:f9eeca106725	3892	#define DSI_VVFPCR_VFP3 0x00000008U
Kojto	122:f9eeca106725	3893	#define DSI_VVFPCR_VFP4 0x00000010U
Kojto	122:f9eeca106725	3894	#define DSI_VVFPCR_VFP5 0x00000020U
Kojto	122:f9eeca106725	3895	#define DSI_VVFPCR_VFP6 0x00000040U
Kojto	122:f9eeca106725	3896	#define DSI_VVFPCR_VFP7 0x00000080U
Kojto	122:f9eeca106725	3897	#define DSI_VVFPCR_VFP8 0x00000100U
Kojto	122:f9eeca106725	3898	#define DSI_VVFPCR_VFP9 0x00000200U
Kojto	110:165afa46840b	3899
Kojto	110:165afa46840b	3900	/***************** Bit definition for DSI_VVACR register ************/
Kojto	122:f9eeca106725	3901	#define DSI_VVACR_VA 0x00003FFFU /!< Vertical Active duration /
Kojto	122:f9eeca106725	3902	#define DSI_VVACR_VA0 0x00000001U
Kojto	122:f9eeca106725	3903	#define DSI_VVACR_VA1 0x00000002U
Kojto	122:f9eeca106725	3904	#define DSI_VVACR_VA2 0x00000004U
Kojto	122:f9eeca106725	3905	#define DSI_VVACR_VA3 0x00000008U
Kojto	122:f9eeca106725	3906	#define DSI_VVACR_VA4 0x00000010U
Kojto	122:f9eeca106725	3907	#define DSI_VVACR_VA5 0x00000020U
Kojto	122:f9eeca106725	3908	#define DSI_VVACR_VA6 0x00000040U
Kojto	122:f9eeca106725	3909	#define DSI_VVACR_VA7 0x00000080U
Kojto	122:f9eeca106725	3910	#define DSI_VVACR_VA8 0x00000100U
Kojto	122:f9eeca106725	3911	#define DSI_VVACR_VA9 0x00000200U
Kojto	122:f9eeca106725	3912	#define DSI_VVACR_VA10 0x00000400U
Kojto	122:f9eeca106725	3913	#define DSI_VVACR_VA11 0x00000800U
Kojto	122:f9eeca106725	3914	#define DSI_VVACR_VA12 0x00001000U
Kojto	122:f9eeca106725	3915	#define DSI_VVACR_VA13 0x00002000U
Kojto	110:165afa46840b	3916
Kojto	110:165afa46840b	3917	/***************** Bit definition for DSI_LCCR register *************/
Kojto	122:f9eeca106725	3918	#define DSI_LCCR_CMDSIZE 0x0000FFFFU /!< Command Size /
Kojto	122:f9eeca106725	3919	#define DSI_LCCR_CMDSIZE0 0x00000001U
Kojto	122:f9eeca106725	3920	#define DSI_LCCR_CMDSIZE1 0x00000002U
Kojto	122:f9eeca106725	3921	#define DSI_LCCR_CMDSIZE2 0x00000004U
Kojto	122:f9eeca106725	3922	#define DSI_LCCR_CMDSIZE3 0x00000008U
Kojto	122:f9eeca106725	3923	#define DSI_LCCR_CMDSIZE4 0x00000010U
Kojto	122:f9eeca106725	3924	#define DSI_LCCR_CMDSIZE5 0x00000020U
Kojto	122:f9eeca106725	3925	#define DSI_LCCR_CMDSIZE6 0x00000040U
Kojto	122:f9eeca106725	3926	#define DSI_LCCR_CMDSIZE7 0x00000080U
Kojto	122:f9eeca106725	3927	#define DSI_LCCR_CMDSIZE8 0x00000100U
Kojto	122:f9eeca106725	3928	#define DSI_LCCR_CMDSIZE9 0x00000200U
Kojto	122:f9eeca106725	3929	#define DSI_LCCR_CMDSIZE10 0x00000400U
Kojto	122:f9eeca106725	3930	#define DSI_LCCR_CMDSIZE11 0x00000800U
Kojto	122:f9eeca106725	3931	#define DSI_LCCR_CMDSIZE12 0x00001000U
Kojto	122:f9eeca106725	3932	#define DSI_LCCR_CMDSIZE13 0x00002000U
Kojto	122:f9eeca106725	3933	#define DSI_LCCR_CMDSIZE14 0x00004000U
Kojto	122:f9eeca106725	3934	#define DSI_LCCR_CMDSIZE15 0x00008000U
Kojto	110:165afa46840b	3935
Kojto	110:165afa46840b	3936	/***************** Bit definition for DSI_CMCR register *************/
Kojto	122:f9eeca106725	3937	#define DSI_CMCR_TEARE 0x00000001U /!< Tearing Effect Acknowledge Request Enable /
Kojto	122:f9eeca106725	3938	#define DSI_CMCR_ARE 0x00000002U /!< Acknowledge Request Enable /
Kojto	122:f9eeca106725	3939	#define DSI_CMCR_GSW0TX 0x00000100U /!< Generic Short Write Zero parameters Transmission /
Kojto	122:f9eeca106725	3940	#define DSI_CMCR_GSW1TX 0x00000200U /!< Generic Short Write One parameters Transmission /
Kojto	122:f9eeca106725	3941	#define DSI_CMCR_GSW2TX 0x00000400U /!< Generic Short Write Two parameters Transmission /
Kojto	122:f9eeca106725	3942	#define DSI_CMCR_GSR0TX 0x00000800U /!< Generic Short Read Zero parameters Transmission /
Kojto	122:f9eeca106725	3943	#define DSI_CMCR_GSR1TX 0x00001000U /!< Generic Short Read One parameters Transmission /
Kojto	122:f9eeca106725	3944	#define DSI_CMCR_GSR2TX 0x00002000U /!< Generic Short Read Two parameters Transmission /
Kojto	122:f9eeca106725	3945	#define DSI_CMCR_GLWTX 0x00004000U /!< Generic Long Write Transmission /
Kojto	122:f9eeca106725	3946	#define DSI_CMCR_DSW0TX 0x00010000U /!< DCS Short Write Zero parameter Transmission /
Kojto	122:f9eeca106725	3947	#define DSI_CMCR_DSW1TX 0x00020000U /!< DCS Short Read One parameter Transmission /
Kojto	122:f9eeca106725	3948	#define DSI_CMCR_DSR0TX 0x00040000U /!< DCS Short Read Zero parameter Transmission /
Kojto	122:f9eeca106725	3949	#define DSI_CMCR_DLWTX 0x00080000U /!< DCS Long Write Transmission /
Kojto	122:f9eeca106725	3950	#define DSI_CMCR_MRDPS 0x01000000U /!< Maximum Read Packet Size /
Kojto	110:165afa46840b	3951
Kojto	110:165afa46840b	3952	/***************** Bit definition for DSI_GHCR register *************/
Kojto	122:f9eeca106725	3953	#define DSI_GHCR_DT 0x0000003FU /!< Type /
Kojto	122:f9eeca106725	3954	#define DSI_GHCR_DT0 0x00000001U
Kojto	122:f9eeca106725	3955	#define DSI_GHCR_DT1 0x00000002U
Kojto	122:f9eeca106725	3956	#define DSI_GHCR_DT2 0x00000004U
Kojto	122:f9eeca106725	3957	#define DSI_GHCR_DT3 0x00000008U
Kojto	122:f9eeca106725	3958	#define DSI_GHCR_DT4 0x00000010U
Kojto	122:f9eeca106725	3959	#define DSI_GHCR_DT5 0x00000020U
Kojto	122:f9eeca106725	3960
Kojto	122:f9eeca106725	3961	#define DSI_GHCR_VCID 0x000000C0U /!< Channel /
Kojto	122:f9eeca106725	3962	#define DSI_GHCR_VCID0 0x00000040U
Kojto	122:f9eeca106725	3963	#define DSI_GHCR_VCID1 0x00000080U
Kojto	122:f9eeca106725	3964
Kojto	122:f9eeca106725	3965	#define DSI_GHCR_WCLSB 0x0000FF00U /!< WordCount LSB /
Kojto	122:f9eeca106725	3966	#define DSI_GHCR_WCLSB0 0x00000100U
Kojto	122:f9eeca106725	3967	#define DSI_GHCR_WCLSB1 0x00000200U
Kojto	122:f9eeca106725	3968	#define DSI_GHCR_WCLSB2 0x00000400U
Kojto	122:f9eeca106725	3969	#define DSI_GHCR_WCLSB3 0x00000800U
Kojto	122:f9eeca106725	3970	#define DSI_GHCR_WCLSB4 0x00001000U
Kojto	122:f9eeca106725	3971	#define DSI_GHCR_WCLSB5 0x00002000U
Kojto	122:f9eeca106725	3972	#define DSI_GHCR_WCLSB6 0x00004000U
Kojto	122:f9eeca106725	3973	#define DSI_GHCR_WCLSB7 0x00008000U
Kojto	122:f9eeca106725	3974
Kojto	122:f9eeca106725	3975	#define DSI_GHCR_WCMSB 0x00FF0000U /!< WordCount MSB /
Kojto	122:f9eeca106725	3976	#define DSI_GHCR_WCMSB0 0x00010000U
Kojto	122:f9eeca106725	3977	#define DSI_GHCR_WCMSB1 0x00020000U
Kojto	122:f9eeca106725	3978	#define DSI_GHCR_WCMSB2 0x00040000U
Kojto	122:f9eeca106725	3979	#define DSI_GHCR_WCMSB3 0x00080000U
Kojto	122:f9eeca106725	3980	#define DSI_GHCR_WCMSB4 0x00100000U
Kojto	122:f9eeca106725	3981	#define DSI_GHCR_WCMSB5 0x00200000U
Kojto	122:f9eeca106725	3982	#define DSI_GHCR_WCMSB6 0x00400000U
Kojto	122:f9eeca106725	3983	#define DSI_GHCR_WCMSB7 0x00800000U
Kojto	110:165afa46840b	3984
Kojto	110:165afa46840b	3985	/***************** Bit definition for DSI_GPDR register *************/
Kojto	122:f9eeca106725	3986	#define DSI_GPDR_DATA1 0x000000FFU /!< Payload Byte 1 /
Kojto	122:f9eeca106725	3987	#define DSI_GPDR_DATA1_0 0x00000001U
Kojto	122:f9eeca106725	3988	#define DSI_GPDR_DATA1_1 0x00000002U
Kojto	122:f9eeca106725	3989	#define DSI_GPDR_DATA1_2 0x00000004U
Kojto	122:f9eeca106725	3990	#define DSI_GPDR_DATA1_3 0x00000008U
Kojto	122:f9eeca106725	3991	#define DSI_GPDR_DATA1_4 0x00000010U
Kojto	122:f9eeca106725	3992	#define DSI_GPDR_DATA1_5 0x00000020U
Kojto	122:f9eeca106725	3993	#define DSI_GPDR_DATA1_6 0x00000040U
Kojto	122:f9eeca106725	3994	#define DSI_GPDR_DATA1_7 0x00000080U
Kojto	122:f9eeca106725	3995
Kojto	122:f9eeca106725	3996	#define DSI_GPDR_DATA2 0x0000FF00U /!< Payload Byte 2 /
Kojto	122:f9eeca106725	3997	#define DSI_GPDR_DATA2_0 0x00000100U
Kojto	122:f9eeca106725	3998	#define DSI_GPDR_DATA2_1 0x00000200U
Kojto	122:f9eeca106725	3999	#define DSI_GPDR_DATA2_2 0x00000400U
Kojto	122:f9eeca106725	4000	#define DSI_GPDR_DATA2_3 0x00000800U
Kojto	122:f9eeca106725	4001	#define DSI_GPDR_DATA2_4 0x00001000U
Kojto	122:f9eeca106725	4002	#define DSI_GPDR_DATA2_5 0x00002000U
Kojto	122:f9eeca106725	4003	#define DSI_GPDR_DATA2_6 0x00004000U
Kojto	122:f9eeca106725	4004	#define DSI_GPDR_DATA2_7 0x00008000U
Kojto	122:f9eeca106725	4005
Kojto	122:f9eeca106725	4006	#define DSI_GPDR_DATA3 0x00FF0000U /!< Payload Byte 3 /
Kojto	122:f9eeca106725	4007	#define DSI_GPDR_DATA3_0 0x00010000U
Kojto	122:f9eeca106725	4008	#define DSI_GPDR_DATA3_1 0x00020000U
Kojto	122:f9eeca106725	4009	#define DSI_GPDR_DATA3_2 0x00040000U
Kojto	122:f9eeca106725	4010	#define DSI_GPDR_DATA3_3 0x00080000U
Kojto	122:f9eeca106725	4011	#define DSI_GPDR_DATA3_4 0x00100000U
Kojto	122:f9eeca106725	4012	#define DSI_GPDR_DATA3_5 0x00200000U
Kojto	122:f9eeca106725	4013	#define DSI_GPDR_DATA3_6 0x00400000U
Kojto	122:f9eeca106725	4014	#define DSI_GPDR_DATA3_7 0x00800000U
Kojto	122:f9eeca106725	4015
Kojto	122:f9eeca106725	4016	#define DSI_GPDR_DATA4 0xFF000000U /!< Payload Byte 4 /
Kojto	122:f9eeca106725	4017	#define DSI_GPDR_DATA4_0 0x01000000U
Kojto	122:f9eeca106725	4018	#define DSI_GPDR_DATA4_1 0x02000000U
Kojto	122:f9eeca106725	4019	#define DSI_GPDR_DATA4_2 0x04000000U
Kojto	122:f9eeca106725	4020	#define DSI_GPDR_DATA4_3 0x08000000U
Kojto	122:f9eeca106725	4021	#define DSI_GPDR_DATA4_4 0x10000000U
Kojto	122:f9eeca106725	4022	#define DSI_GPDR_DATA4_5 0x20000000U
Kojto	122:f9eeca106725	4023	#define DSI_GPDR_DATA4_6 0x40000000U
Kojto	122:f9eeca106725	4024	#define DSI_GPDR_DATA4_7 0x80000000U
Kojto	110:165afa46840b	4025
Kojto	110:165afa46840b	4026	/***************** Bit definition for DSI_GPSR register *************/
Kojto	122:f9eeca106725	4027	#define DSI_GPSR_CMDFE 0x00000001U /!< Command FIFO Empty /
Kojto	122:f9eeca106725	4028	#define DSI_GPSR_CMDFF 0x00000002U /!< Command FIFO Full /
Kojto	122:f9eeca106725	4029	#define DSI_GPSR_PWRFE 0x00000004U /!< Payload Write FIFO Empty /
Kojto	122:f9eeca106725	4030	#define DSI_GPSR_PWRFF 0x00000008U /!< Payload Write FIFO Full /
Kojto	122:f9eeca106725	4031	#define DSI_GPSR_PRDFE 0x00000010U /!< Payload Read FIFO Empty /
Kojto	122:f9eeca106725	4032	#define DSI_GPSR_PRDFF 0x00000020U /!< Payload Read FIFO Full /
Kojto	122:f9eeca106725	4033	#define DSI_GPSR_RCB 0x00000040U /!< Read Command Busy /
Kojto	110:165afa46840b	4034
Kojto	110:165afa46840b	4035	/***************** Bit definition for DSI_TCCR0 register ************/
Kojto	122:f9eeca106725	4036	#define DSI_TCCR0_LPRX_TOCNT 0x0000FFFFU /!< Low-power Reception Timeout Counter /
Kojto	122:f9eeca106725	4037	#define DSI_TCCR0_LPRX_TOCNT0 0x00000001U
Kojto	122:f9eeca106725	4038	#define DSI_TCCR0_LPRX_TOCNT1 0x00000002U
Kojto	122:f9eeca106725	4039	#define DSI_TCCR0_LPRX_TOCNT2 0x00000004U
Kojto	122:f9eeca106725	4040	#define DSI_TCCR0_LPRX_TOCNT3 0x00000008U
Kojto	122:f9eeca106725	4041	#define DSI_TCCR0_LPRX_TOCNT4 0x00000010U
Kojto	122:f9eeca106725	4042	#define DSI_TCCR0_LPRX_TOCNT5 0x00000020U
Kojto	122:f9eeca106725	4043	#define DSI_TCCR0_LPRX_TOCNT6 0x00000040U
Kojto	122:f9eeca106725	4044	#define DSI_TCCR0_LPRX_TOCNT7 0x00000080U
Kojto	122:f9eeca106725	4045	#define DSI_TCCR0_LPRX_TOCNT8 0x00000100U
Kojto	122:f9eeca106725	4046	#define DSI_TCCR0_LPRX_TOCNT9 0x00000200U
Kojto	122:f9eeca106725	4047	#define DSI_TCCR0_LPRX_TOCNT10 0x00000400U
Kojto	122:f9eeca106725	4048	#define DSI_TCCR0_LPRX_TOCNT11 0x00000800U
Kojto	122:f9eeca106725	4049	#define DSI_TCCR0_LPRX_TOCNT12 0x00001000U
Kojto	122:f9eeca106725	4050	#define DSI_TCCR0_LPRX_TOCNT13 0x00002000U
Kojto	122:f9eeca106725	4051	#define DSI_TCCR0_LPRX_TOCNT14 0x00004000U
Kojto	122:f9eeca106725	4052	#define DSI_TCCR0_LPRX_TOCNT15 0x00008000U
Kojto	122:f9eeca106725	4053
Kojto	122:f9eeca106725	4054	#define DSI_TCCR0_HSTX_TOCNT 0xFFFF0000U /!< High-Speed Transmission Timeout Counter /
Kojto	122:f9eeca106725	4055	#define DSI_TCCR0_HSTX_TOCNT0 0x00010000U
Kojto	122:f9eeca106725	4056	#define DSI_TCCR0_HSTX_TOCNT1 0x00020000U
Kojto	122:f9eeca106725	4057	#define DSI_TCCR0_HSTX_TOCNT2 0x00040000U
Kojto	122:f9eeca106725	4058	#define DSI_TCCR0_HSTX_TOCNT3 0x00080000U
Kojto	122:f9eeca106725	4059	#define DSI_TCCR0_HSTX_TOCNT4 0x00100000U
Kojto	122:f9eeca106725	4060	#define DSI_TCCR0_HSTX_TOCNT5 0x00200000U
Kojto	122:f9eeca106725	4061	#define DSI_TCCR0_HSTX_TOCNT6 0x00400000U
Kojto	122:f9eeca106725	4062	#define DSI_TCCR0_HSTX_TOCNT7 0x00800000U
Kojto	122:f9eeca106725	4063	#define DSI_TCCR0_HSTX_TOCNT8 0x01000000U
Kojto	122:f9eeca106725	4064	#define DSI_TCCR0_HSTX_TOCNT9 0x02000000U
Kojto	122:f9eeca106725	4065	#define DSI_TCCR0_HSTX_TOCNT10 0x04000000U
Kojto	122:f9eeca106725	4066	#define DSI_TCCR0_HSTX_TOCNT11 0x08000000U
Kojto	122:f9eeca106725	4067	#define DSI_TCCR0_HSTX_TOCNT12 0x10000000U
Kojto	122:f9eeca106725	4068	#define DSI_TCCR0_HSTX_TOCNT13 0x20000000U
Kojto	122:f9eeca106725	4069	#define DSI_TCCR0_HSTX_TOCNT14 0x40000000U
Kojto	122:f9eeca106725	4070	#define DSI_TCCR0_HSTX_TOCNT15 0x80000000U
Kojto	110:165afa46840b	4071
Kojto	110:165afa46840b	4072	/***************** Bit definition for DSI_TCCR1 register ************/
Kojto	122:f9eeca106725	4073	#define DSI_TCCR1_HSRD_TOCNT 0x0000FFFFU /!< High-Speed Read Timeout Counter /
Kojto	122:f9eeca106725	4074	#define DSI_TCCR1_HSRD_TOCNT0 0x00000001U
Kojto	122:f9eeca106725	4075	#define DSI_TCCR1_HSRD_TOCNT1 0x00000002U
Kojto	122:f9eeca106725	4076	#define DSI_TCCR1_HSRD_TOCNT2 0x00000004U
Kojto	122:f9eeca106725	4077	#define DSI_TCCR1_HSRD_TOCNT3 0x00000008U
Kojto	122:f9eeca106725	4078	#define DSI_TCCR1_HSRD_TOCNT4 0x00000010U
Kojto	122:f9eeca106725	4079	#define DSI_TCCR1_HSRD_TOCNT5 0x00000020U
Kojto	122:f9eeca106725	4080	#define DSI_TCCR1_HSRD_TOCNT6 0x00000040U
Kojto	122:f9eeca106725	4081	#define DSI_TCCR1_HSRD_TOCNT7 0x00000080U
Kojto	122:f9eeca106725	4082	#define DSI_TCCR1_HSRD_TOCNT8 0x00000100U
Kojto	122:f9eeca106725	4083	#define DSI_TCCR1_HSRD_TOCNT9 0x00000200U
Kojto	122:f9eeca106725	4084	#define DSI_TCCR1_HSRD_TOCNT10 0x00000400U
Kojto	122:f9eeca106725	4085	#define DSI_TCCR1_HSRD_TOCNT11 0x00000800U
Kojto	122:f9eeca106725	4086	#define DSI_TCCR1_HSRD_TOCNT12 0x00001000U
Kojto	122:f9eeca106725	4087	#define DSI_TCCR1_HSRD_TOCNT13 0x00002000U
Kojto	122:f9eeca106725	4088	#define DSI_TCCR1_HSRD_TOCNT14 0x00004000U
Kojto	122:f9eeca106725	4089	#define DSI_TCCR1_HSRD_TOCNT15 0x00008000U
Kojto	110:165afa46840b	4090
Kojto	110:165afa46840b	4091	/***************** Bit definition for DSI_TCCR2 register ************/
Kojto	122:f9eeca106725	4092	#define DSI_TCCR2_LPRD_TOCNT 0x0000FFFFU /!< Low-Power Read Timeout Counter /
Kojto	122:f9eeca106725	4093	#define DSI_TCCR2_LPRD_TOCNT0 0x00000001U
Kojto	122:f9eeca106725	4094	#define DSI_TCCR2_LPRD_TOCNT1 0x00000002U
Kojto	122:f9eeca106725	4095	#define DSI_TCCR2_LPRD_TOCNT2 0x00000004U
Kojto	122:f9eeca106725	4096	#define DSI_TCCR2_LPRD_TOCNT3 0x00000008U
Kojto	122:f9eeca106725	4097	#define DSI_TCCR2_LPRD_TOCNT4 0x00000010U
Kojto	122:f9eeca106725	4098	#define DSI_TCCR2_LPRD_TOCNT5 0x00000020U
Kojto	122:f9eeca106725	4099	#define DSI_TCCR2_LPRD_TOCNT6 0x00000040U
Kojto	122:f9eeca106725	4100	#define DSI_TCCR2_LPRD_TOCNT7 0x00000080U
Kojto	122:f9eeca106725	4101	#define DSI_TCCR2_LPRD_TOCNT8 0x00000100U
Kojto	122:f9eeca106725	4102	#define DSI_TCCR2_LPRD_TOCNT9 0x00000200U
Kojto	122:f9eeca106725	4103	#define DSI_TCCR2_LPRD_TOCNT10 0x00000400U
Kojto	122:f9eeca106725	4104	#define DSI_TCCR2_LPRD_TOCNT11 0x00000800U
Kojto	122:f9eeca106725	4105	#define DSI_TCCR2_LPRD_TOCNT12 0x00001000U
Kojto	122:f9eeca106725	4106	#define DSI_TCCR2_LPRD_TOCNT13 0x00002000U
Kojto	122:f9eeca106725	4107	#define DSI_TCCR2_LPRD_TOCNT14 0x00004000U
Kojto	122:f9eeca106725	4108	#define DSI_TCCR2_LPRD_TOCNT15 0x00008000U
Kojto	110:165afa46840b	4109
Kojto	110:165afa46840b	4110	/***************** Bit definition for DSI_TCCR3 register ************/
Kojto	122:f9eeca106725	4111	#define DSI_TCCR3_HSWR_TOCNT 0x0000FFFFU /!< High-Speed Write Timeout Counter /
Kojto	122:f9eeca106725	4112	#define DSI_TCCR3_HSWR_TOCNT0 0x00000001U
Kojto	122:f9eeca106725	4113	#define DSI_TCCR3_HSWR_TOCNT1 0x00000002U
Kojto	122:f9eeca106725	4114	#define DSI_TCCR3_HSWR_TOCNT2 0x00000004U
Kojto	122:f9eeca106725	4115	#define DSI_TCCR3_HSWR_TOCNT3 0x00000008U
Kojto	122:f9eeca106725	4116	#define DSI_TCCR3_HSWR_TOCNT4 0x00000010U
Kojto	122:f9eeca106725	4117	#define DSI_TCCR3_HSWR_TOCNT5 0x00000020U
Kojto	122:f9eeca106725	4118	#define DSI_TCCR3_HSWR_TOCNT6 0x00000040U
Kojto	122:f9eeca106725	4119	#define DSI_TCCR3_HSWR_TOCNT7 0x00000080U
Kojto	122:f9eeca106725	4120	#define DSI_TCCR3_HSWR_TOCNT8 0x00000100U
Kojto	122:f9eeca106725	4121	#define DSI_TCCR3_HSWR_TOCNT9 0x00000200U
Kojto	122:f9eeca106725	4122	#define DSI_TCCR3_HSWR_TOCNT10 0x00000400U
Kojto	122:f9eeca106725	4123	#define DSI_TCCR3_HSWR_TOCNT11 0x00000800U
Kojto	122:f9eeca106725	4124	#define DSI_TCCR3_HSWR_TOCNT12 0x00001000U
Kojto	122:f9eeca106725	4125	#define DSI_TCCR3_HSWR_TOCNT13 0x00002000U
Kojto	122:f9eeca106725	4126	#define DSI_TCCR3_HSWR_TOCNT14 0x00004000U
Kojto	122:f9eeca106725	4127	#define DSI_TCCR3_HSWR_TOCNT15 0x00008000U
Kojto	122:f9eeca106725	4128
Kojto	122:f9eeca106725	4129	#define DSI_TCCR3_PM 0x01000000U /!< Presp Mode /
Kojto	110:165afa46840b	4130
Kojto	110:165afa46840b	4131	/***************** Bit definition for DSI_TCCR4 register ************/
Kojto	122:f9eeca106725	4132	#define DSI_TCCR4_LPWR_TOCNT 0x0000FFFFU /!< Low-Power Write Timeout Counter /
Kojto	122:f9eeca106725	4133	#define DSI_TCCR4_LPWR_TOCNT0 0x00000001U
Kojto	122:f9eeca106725	4134	#define DSI_TCCR4_LPWR_TOCNT1 0x00000002U
Kojto	122:f9eeca106725	4135	#define DSI_TCCR4_LPWR_TOCNT2 0x00000004U
Kojto	122:f9eeca106725	4136	#define DSI_TCCR4_LPWR_TOCNT3 0x00000008U
Kojto	122:f9eeca106725	4137	#define DSI_TCCR4_LPWR_TOCNT4 0x00000010U
Kojto	122:f9eeca106725	4138	#define DSI_TCCR4_LPWR_TOCNT5 0x00000020U
Kojto	122:f9eeca106725	4139	#define DSI_TCCR4_LPWR_TOCNT6 0x00000040U
Kojto	122:f9eeca106725	4140	#define DSI_TCCR4_LPWR_TOCNT7 0x00000080U
Kojto	122:f9eeca106725	4141	#define DSI_TCCR4_LPWR_TOCNT8 0x00000100U
Kojto	122:f9eeca106725	4142	#define DSI_TCCR4_LPWR_TOCNT9 0x00000200U
Kojto	122:f9eeca106725	4143	#define DSI_TCCR4_LPWR_TOCNT10 0x00000400U
Kojto	122:f9eeca106725	4144	#define DSI_TCCR4_LPWR_TOCNT11 0x00000800U
Kojto	122:f9eeca106725	4145	#define DSI_TCCR4_LPWR_TOCNT12 0x00001000U
Kojto	122:f9eeca106725	4146	#define DSI_TCCR4_LPWR_TOCNT13 0x00002000U
Kojto	122:f9eeca106725	4147	#define DSI_TCCR4_LPWR_TOCNT14 0x00004000U
Kojto	122:f9eeca106725	4148	#define DSI_TCCR4_LPWR_TOCNT15 0x00008000U
Kojto	110:165afa46840b	4149
Kojto	110:165afa46840b	4150	/***************** Bit definition for DSI_TCCR5 register ************/
Kojto	122:f9eeca106725	4151	#define DSI_TCCR5_BTA_TOCNT 0x0000FFFFU /!< Bus-Turn-Around Timeout Counter /
Kojto	122:f9eeca106725	4152	#define DSI_TCCR5_BTA_TOCNT0 0x00000001U
Kojto	122:f9eeca106725	4153	#define DSI_TCCR5_BTA_TOCNT1 0x00000002U
Kojto	122:f9eeca106725	4154	#define DSI_TCCR5_BTA_TOCNT2 0x00000004U
Kojto	122:f9eeca106725	4155	#define DSI_TCCR5_BTA_TOCNT3 0x00000008U
Kojto	122:f9eeca106725	4156	#define DSI_TCCR5_BTA_TOCNT4 0x00000010U
Kojto	122:f9eeca106725	4157	#define DSI_TCCR5_BTA_TOCNT5 0x00000020U
Kojto	122:f9eeca106725	4158	#define DSI_TCCR5_BTA_TOCNT6 0x00000040U
Kojto	122:f9eeca106725	4159	#define DSI_TCCR5_BTA_TOCNT7 0x00000080U
Kojto	122:f9eeca106725	4160	#define DSI_TCCR5_BTA_TOCNT8 0x00000100U
Kojto	122:f9eeca106725	4161	#define DSI_TCCR5_BTA_TOCNT9 0x00000200U
Kojto	122:f9eeca106725	4162	#define DSI_TCCR5_BTA_TOCNT10 0x00000400U
Kojto	122:f9eeca106725	4163	#define DSI_TCCR5_BTA_TOCNT11 0x00000800U
Kojto	122:f9eeca106725	4164	#define DSI_TCCR5_BTA_TOCNT12 0x00001000U
Kojto	122:f9eeca106725	4165	#define DSI_TCCR5_BTA_TOCNT13 0x00002000U
Kojto	122:f9eeca106725	4166	#define DSI_TCCR5_BTA_TOCNT14 0x00004000U
Kojto	122:f9eeca106725	4167	#define DSI_TCCR5_BTA_TOCNT15 0x00008000U
Kojto	110:165afa46840b	4168
Kojto	110:165afa46840b	4169	/***************** Bit definition for DSI_TDCR register *************/
Kojto	122:f9eeca106725	4170	#define DSI_TDCR_3DM 0x00000003U /!< 3D Mode /
Kojto	122:f9eeca106725	4171	#define DSI_TDCR_3DM0 0x00000001U
Kojto	122:f9eeca106725	4172	#define DSI_TDCR_3DM1 0x00000002U
Kojto	122:f9eeca106725	4173
Kojto	122:f9eeca106725	4174	#define DSI_TDCR_3DF 0x0000000CU /!< 3D Format /
Kojto	122:f9eeca106725	4175	#define DSI_TDCR_3DF0 0x00000004U
Kojto	122:f9eeca106725	4176	#define DSI_TDCR_3DF1 0x00000008U
Kojto	122:f9eeca106725	4177
Kojto	122:f9eeca106725	4178	#define DSI_TDCR_SVS 0x00000010U /!< Second VSYNC /
Kojto	122:f9eeca106725	4179	#define DSI_TDCR_RF 0x00000020U /!< Right First /
Kojto	122:f9eeca106725	4180	#define DSI_TDCR_S3DC 0x00010000U /!< Send 3D Control /
Kojto	110:165afa46840b	4181
Kojto	110:165afa46840b	4182	/***************** Bit definition for DSI_CLCR register *************/
Kojto	122:f9eeca106725	4183	#define DSI_CLCR_DPCC 0x00000001U /!< D-PHY Clock Control /
Kojto	122:f9eeca106725	4184	#define DSI_CLCR_ACR 0x00000002U /!< Automatic Clocklane Control /
Kojto	110:165afa46840b	4185
Kojto	110:165afa46840b	4186	/***************** Bit definition for DSI_CLTCR register ************/
Kojto	122:f9eeca106725	4187	#define DSI_CLTCR_LP2HS_TIME 0x000003FFU /!< Low-Power to High-Speed Time /
Kojto	122:f9eeca106725	4188	#define DSI_CLTCR_LP2HS_TIME0 0x00000001U
Kojto	122:f9eeca106725	4189	#define DSI_CLTCR_LP2HS_TIME1 0x00000002U
Kojto	122:f9eeca106725	4190	#define DSI_CLTCR_LP2HS_TIME2 0x00000004U
Kojto	122:f9eeca106725	4191	#define DSI_CLTCR_LP2HS_TIME3 0x00000008U
Kojto	122:f9eeca106725	4192	#define DSI_CLTCR_LP2HS_TIME4 0x00000010U
Kojto	122:f9eeca106725	4193	#define DSI_CLTCR_LP2HS_TIME5 0x00000020U
Kojto	122:f9eeca106725	4194	#define DSI_CLTCR_LP2HS_TIME6 0x00000040U
Kojto	122:f9eeca106725	4195	#define DSI_CLTCR_LP2HS_TIME7 0x00000080U
Kojto	122:f9eeca106725	4196	#define DSI_CLTCR_LP2HS_TIME8 0x00000100U
Kojto	122:f9eeca106725	4197	#define DSI_CLTCR_LP2HS_TIME9 0x00000200U
Kojto	122:f9eeca106725	4198
Kojto	122:f9eeca106725	4199	#define DSI_CLTCR_HS2LP_TIME 0x03FF0000U /!< High-Speed to Low-Power Time /
Kojto	122:f9eeca106725	4200	#define DSI_CLTCR_HS2LP_TIME0 0x00010000U
Kojto	122:f9eeca106725	4201	#define DSI_CLTCR_HS2LP_TIME1 0x00020000U
Kojto	122:f9eeca106725	4202	#define DSI_CLTCR_HS2LP_TIME2 0x00040000U
Kojto	122:f9eeca106725	4203	#define DSI_CLTCR_HS2LP_TIME3 0x00080000U
Kojto	122:f9eeca106725	4204	#define DSI_CLTCR_HS2LP_TIME4 0x00100000U
Kojto	122:f9eeca106725	4205	#define DSI_CLTCR_HS2LP_TIME5 0x00200000U
Kojto	122:f9eeca106725	4206	#define DSI_CLTCR_HS2LP_TIME6 0x00400000U
Kojto	122:f9eeca106725	4207	#define DSI_CLTCR_HS2LP_TIME7 0x00800000U
Kojto	122:f9eeca106725	4208	#define DSI_CLTCR_HS2LP_TIME8 0x01000000U
Kojto	122:f9eeca106725	4209	#define DSI_CLTCR_HS2LP_TIME9 0x02000000U
Kojto	110:165afa46840b	4210
Kojto	110:165afa46840b	4211	/***************** Bit definition for DSI_DLTCR register ************/
Kojto	122:f9eeca106725	4212	#define DSI_DLTCR_MRD_TIME 0x00007FFFU /!< Maximum Read Time /
Kojto	122:f9eeca106725	4213	#define DSI_DLTCR_MRD_TIME0 0x00000001U
Kojto	122:f9eeca106725	4214	#define DSI_DLTCR_MRD_TIME1 0x00000002U
Kojto	122:f9eeca106725	4215	#define DSI_DLTCR_MRD_TIME2 0x00000004U
Kojto	122:f9eeca106725	4216	#define DSI_DLTCR_MRD_TIME3 0x00000008U
Kojto	122:f9eeca106725	4217	#define DSI_DLTCR_MRD_TIME4 0x00000010U
Kojto	122:f9eeca106725	4218	#define DSI_DLTCR_MRD_TIME5 0x00000020U
Kojto	122:f9eeca106725	4219	#define DSI_DLTCR_MRD_TIME6 0x00000040U
Kojto	122:f9eeca106725	4220	#define DSI_DLTCR_MRD_TIME7 0x00000080U
Kojto	122:f9eeca106725	4221	#define DSI_DLTCR_MRD_TIME8 0x00000100U
Kojto	122:f9eeca106725	4222	#define DSI_DLTCR_MRD_TIME9 0x00000200U
Kojto	122:f9eeca106725	4223	#define DSI_DLTCR_MRD_TIME10 0x00000400U
Kojto	122:f9eeca106725	4224	#define DSI_DLTCR_MRD_TIME11 0x00000800U
Kojto	122:f9eeca106725	4225	#define DSI_DLTCR_MRD_TIME12 0x00001000U
Kojto	122:f9eeca106725	4226	#define DSI_DLTCR_MRD_TIME13 0x00002000U
Kojto	122:f9eeca106725	4227	#define DSI_DLTCR_MRD_TIME14 0x00004000U
Kojto	122:f9eeca106725	4228
Kojto	122:f9eeca106725	4229	#define DSI_DLTCR_LP2HS_TIME 0x00FF0000U /!< Low-Power To High-Speed Time /
Kojto	122:f9eeca106725	4230	#define DSI_DLTCR_LP2HS_TIME0 0x00010000U
Kojto	122:f9eeca106725	4231	#define DSI_DLTCR_LP2HS_TIME1 0x00020000U
Kojto	122:f9eeca106725	4232	#define DSI_DLTCR_LP2HS_TIME2 0x00040000U
Kojto	122:f9eeca106725	4233	#define DSI_DLTCR_LP2HS_TIME3 0x00080000U
Kojto	122:f9eeca106725	4234	#define DSI_DLTCR_LP2HS_TIME4 0x00100000U
Kojto	122:f9eeca106725	4235	#define DSI_DLTCR_LP2HS_TIME5 0x00200000U
Kojto	122:f9eeca106725	4236	#define DSI_DLTCR_LP2HS_TIME6 0x00400000U
Kojto	122:f9eeca106725	4237	#define DSI_DLTCR_LP2HS_TIME7 0x00800000U
Kojto	122:f9eeca106725	4238
Kojto	122:f9eeca106725	4239	#define DSI_DLTCR_HS2LP_TIME 0xFF000000U /!< High-Speed To Low-Power Time /
Kojto	122:f9eeca106725	4240	#define DSI_DLTCR_HS2LP_TIME0 0x01000000U
Kojto	122:f9eeca106725	4241	#define DSI_DLTCR_HS2LP_TIME1 0x02000000U
Kojto	122:f9eeca106725	4242	#define DSI_DLTCR_HS2LP_TIME2 0x04000000U
Kojto	122:f9eeca106725	4243	#define DSI_DLTCR_HS2LP_TIME3 0x08000000U
Kojto	122:f9eeca106725	4244	#define DSI_DLTCR_HS2LP_TIME4 0x10000000U
Kojto	122:f9eeca106725	4245	#define DSI_DLTCR_HS2LP_TIME5 0x20000000U
Kojto	122:f9eeca106725	4246	#define DSI_DLTCR_HS2LP_TIME6 0x40000000U
Kojto	122:f9eeca106725	4247	#define DSI_DLTCR_HS2LP_TIME7 0x80000000U
Kojto	110:165afa46840b	4248
Kojto	110:165afa46840b	4249	/***************** Bit definition for DSI_PCTLR register ************/
Kojto	122:f9eeca106725	4250	#define DSI_PCTLR_DEN 0x00000002U /!< Digital Enable /
Kojto	122:f9eeca106725	4251	#define DSI_PCTLR_CKE 0x00000004U /!< Clock Enable /
Kojto	110:165afa46840b	4252
Kojto	110:165afa46840b	4253	/***************** Bit definition for DSI_PCONFR register ***********/
Kojto	122:f9eeca106725	4254	#define DSI_PCONFR_NL 0x00000003U /!< Number of Lanes /
Kojto	122:f9eeca106725	4255	#define DSI_PCONFR_NL0 0x00000001U
Kojto	122:f9eeca106725	4256	#define DSI_PCONFR_NL1 0x00000002U
Kojto	122:f9eeca106725	4257
Kojto	122:f9eeca106725	4258	#define DSI_PCONFR_SW_TIME 0x0000FF00U /!< Stop Wait Time /
Kojto	122:f9eeca106725	4259	#define DSI_PCONFR_SW_TIME0 0x00000100U
Kojto	122:f9eeca106725	4260	#define DSI_PCONFR_SW_TIME1 0x00000200U
Kojto	122:f9eeca106725	4261	#define DSI_PCONFR_SW_TIME2 0x00000400U
Kojto	122:f9eeca106725	4262	#define DSI_PCONFR_SW_TIME3 0x00000800U
Kojto	122:f9eeca106725	4263	#define DSI_PCONFR_SW_TIME4 0x00001000U
Kojto	122:f9eeca106725	4264	#define DSI_PCONFR_SW_TIME5 0x00002000U
Kojto	122:f9eeca106725	4265	#define DSI_PCONFR_SW_TIME6 0x00004000U
Kojto	122:f9eeca106725	4266	#define DSI_PCONFR_SW_TIME7 0x00008000U
Kojto	110:165afa46840b	4267
Kojto	110:165afa46840b	4268	/***************** Bit definition for DSI_PUCR register *************/
Kojto	122:f9eeca106725	4269	#define DSI_PUCR_URCL 0x00000001U /!< ULPS Request on Clock Lane /
Kojto	122:f9eeca106725	4270	#define DSI_PUCR_UECL 0x00000002U /!< ULPS Exit on Clock Lane /
Kojto	122:f9eeca106725	4271	#define DSI_PUCR_URDL 0x00000004U /!< ULPS Request on Data Lane /
Kojto	122:f9eeca106725	4272	#define DSI_PUCR_UEDL 0x00000008U /!< ULPS Exit on Data Lane /
Kojto	110:165afa46840b	4273
Kojto	110:165afa46840b	4274	/***************** Bit definition for DSI_PTTCR register ************/
Kojto	122:f9eeca106725	4275	#define DSI_PTTCR_TX_TRIG 0x0000000FU /!< Transmission Trigger /
Kojto	122:f9eeca106725	4276	#define DSI_PTTCR_TX_TRIG0 0x00000001U
Kojto	122:f9eeca106725	4277	#define DSI_PTTCR_TX_TRIG1 0x00000002U
Kojto	122:f9eeca106725	4278	#define DSI_PTTCR_TX_TRIG2 0x00000004U
Kojto	122:f9eeca106725	4279	#define DSI_PTTCR_TX_TRIG3 0x00000008U
Kojto	110:165afa46840b	4280
Kojto	110:165afa46840b	4281	/***************** Bit definition for DSI_PSR register **************/
Kojto	122:f9eeca106725	4282	#define DSI_PSR_PD 0x00000002U /!< PHY Direction /
Kojto	122:f9eeca106725	4283	#define DSI_PSR_PSSC 0x00000004U /!< PHY Stop State Clock lane /
Kojto	122:f9eeca106725	4284	#define DSI_PSR_UANC 0x00000008U /!< ULPS Active Not Clock lane /
Kojto	122:f9eeca106725	4285	#define DSI_PSR_PSS0 0x00000010U /!< PHY Stop State lane 0 /
Kojto	122:f9eeca106725	4286	#define DSI_PSR_UAN0 0x00000020U /!< ULPS Active Not lane 0 /
Kojto	122:f9eeca106725	4287	#define DSI_PSR_RUE0 0x00000040U /!< RX ULPS Escape lane 0 /
Kojto	122:f9eeca106725	4288	#define DSI_PSR_PSS1 0x00000080U /!< PHY Stop State lane 1 /
Kojto	122:f9eeca106725	4289	#define DSI_PSR_UAN1 0x00000100U /!< ULPS Active Not lane 1 /
Kojto	110:165afa46840b	4290
Kojto	110:165afa46840b	4291	/***************** Bit definition for DSI_ISR0 register *************/
Kojto	122:f9eeca106725	4292	#define DSI_ISR0_AE0 0x00000001U /!< Acknowledge Error 0 /
Kojto	122:f9eeca106725	4293	#define DSI_ISR0_AE1 0x00000002U /!< Acknowledge Error 1 /
Kojto	122:f9eeca106725	4294	#define DSI_ISR0_AE2 0x00000004U /!< Acknowledge Error 2 /
Kojto	122:f9eeca106725	4295	#define DSI_ISR0_AE3 0x00000008U /!< Acknowledge Error 3 /
Kojto	122:f9eeca106725	4296	#define DSI_ISR0_AE4 0x00000010U /!< Acknowledge Error 4 /
Kojto	122:f9eeca106725	4297	#define DSI_ISR0_AE5 0x00000020U /!< Acknowledge Error 5 /
Kojto	122:f9eeca106725	4298	#define DSI_ISR0_AE6 0x00000040U /!< Acknowledge Error 6 /
Kojto	122:f9eeca106725	4299	#define DSI_ISR0_AE7 0x00000080U /!< Acknowledge Error 7 /
Kojto	122:f9eeca106725	4300	#define DSI_ISR0_AE8 0x00000100U /!< Acknowledge Error 8 /
Kojto	122:f9eeca106725	4301	#define DSI_ISR0_AE9 0x00000200U /!< Acknowledge Error 9 /
Kojto	122:f9eeca106725	4302	#define DSI_ISR0_AE10 0x00000400U /!< Acknowledge Error 10 /
Kojto	122:f9eeca106725	4303	#define DSI_ISR0_AE11 0x00000800U /!< Acknowledge Error 11 /
Kojto	122:f9eeca106725	4304	#define DSI_ISR0_AE12 0x00001000U /!< Acknowledge Error 12 /
Kojto	122:f9eeca106725	4305	#define DSI_ISR0_AE13 0x00002000U /!< Acknowledge Error 13 /
Kojto	122:f9eeca106725	4306	#define DSI_ISR0_AE14 0x00004000U /!< Acknowledge Error 14 /
Kojto	122:f9eeca106725	4307	#define DSI_ISR0_AE15 0x00008000U /!< Acknowledge Error 15 /
Kojto	122:f9eeca106725	4308	#define DSI_ISR0_PE0 0x00010000U /!< PHY Error 0 /
Kojto	122:f9eeca106725	4309	#define DSI_ISR0_PE1 0x00020000U /!< PHY Error 1 /
Kojto	122:f9eeca106725	4310	#define DSI_ISR0_PE2 0x00040000U /!< PHY Error 2 /
Kojto	122:f9eeca106725	4311	#define DSI_ISR0_PE3 0x00080000U /!< PHY Error 3 /
Kojto	122:f9eeca106725	4312	#define DSI_ISR0_PE4 0x00100000U /!< PHY Error 4 /
Kojto	110:165afa46840b	4313
Kojto	110:165afa46840b	4314	/***************** Bit definition for DSI_ISR1 register *************/
Kojto	122:f9eeca106725	4315	#define DSI_ISR1_TOHSTX 0x00000001U /!< Timeout High-Speed Transmission /
Kojto	122:f9eeca106725	4316	#define DSI_ISR1_TOLPRX 0x00000002U /!< Timeout Low-Power Reception /
Kojto	122:f9eeca106725	4317	#define DSI_ISR1_ECCSE 0x00000004U /!< ECC Single-bit Error /
Kojto	122:f9eeca106725	4318	#define DSI_ISR1_ECCME 0x00000008U /!< ECC Multi-bit Error /
Kojto	122:f9eeca106725	4319	#define DSI_ISR1_CRCE 0x00000010U /!< CRC Error /
Kojto	122:f9eeca106725	4320	#define DSI_ISR1_PSE 0x00000020U /!< Packet Size Error /
Kojto	122:f9eeca106725	4321	#define DSI_ISR1_EOTPE 0x00000040U /!< EoTp Error /
Kojto	122:f9eeca106725	4322	#define DSI_ISR1_LPWRE 0x00000080U /!< LTDC Payload Write Error /
Kojto	122:f9eeca106725	4323	#define DSI_ISR1_GCWRE 0x00000100U /!< Generic Command Write Error /
Kojto	122:f9eeca106725	4324	#define DSI_ISR1_GPWRE 0x00000200U /!< Generic Payload Write Error /
Kojto	122:f9eeca106725	4325	#define DSI_ISR1_GPTXE 0x00000400U /!< Generic Payload Transmit Error /
Kojto	122:f9eeca106725	4326	#define DSI_ISR1_GPRDE 0x00000800U /!< Generic Payload Read Error /
Kojto	122:f9eeca106725	4327	#define DSI_ISR1_GPRXE 0x00001000U /!< Generic Payload Receive Error /
Kojto	110:165afa46840b	4328
Kojto	110:165afa46840b	4329	/***************** Bit definition for DSI_IER0 register *************/
Kojto	122:f9eeca106725	4330	#define DSI_IER0_AE0IE 0x00000001U /!< Acknowledge Error 0 Interrupt Enable /
Kojto	122:f9eeca106725	4331	#define DSI_IER0_AE1IE 0x00000002U /!< Acknowledge Error 1 Interrupt Enable /
Kojto	122:f9eeca106725	4332	#define DSI_IER0_AE2IE 0x00000004U /!< Acknowledge Error 2 Interrupt Enable /
Kojto	122:f9eeca106725	4333	#define DSI_IER0_AE3IE 0x00000008U /!< Acknowledge Error 3 Interrupt Enable /
Kojto	122:f9eeca106725	4334	#define DSI_IER0_AE4IE 0x00000010U /!< Acknowledge Error 4 Interrupt Enable /
Kojto	122:f9eeca106725	4335	#define DSI_IER0_AE5IE 0x00000020U /!< Acknowledge Error 5 Interrupt Enable /
Kojto	122:f9eeca106725	4336	#define DSI_IER0_AE6IE 0x00000040U /!< Acknowledge Error 6 Interrupt Enable /
Kojto	122:f9eeca106725	4337	#define DSI_IER0_AE7IE 0x00000080U /!< Acknowledge Error 7 Interrupt Enable /
Kojto	122:f9eeca106725	4338	#define DSI_IER0_AE8IE 0x00000100U /!< Acknowledge Error 8 Interrupt Enable /
Kojto	122:f9eeca106725	4339	#define DSI_IER0_AE9IE 0x00000200U /!< Acknowledge Error 9 Interrupt Enable /
Kojto	122:f9eeca106725	4340	#define DSI_IER0_AE10IE 0x00000400U /!< Acknowledge Error 10 Interrupt Enable /
Kojto	122:f9eeca106725	4341	#define DSI_IER0_AE11IE 0x00000800U /!< Acknowledge Error 11 Interrupt Enable /
Kojto	122:f9eeca106725	4342	#define DSI_IER0_AE12IE 0x00001000U /!< Acknowledge Error 12 Interrupt Enable /
Kojto	122:f9eeca106725	4343	#define DSI_IER0_AE13IE 0x00002000U /!< Acknowledge Error 13 Interrupt Enable /
Kojto	122:f9eeca106725	4344	#define DSI_IER0_AE14IE 0x00004000U /!< Acknowledge Error 14 Interrupt Enable /
Kojto	122:f9eeca106725	4345	#define DSI_IER0_AE15IE 0x00008000U /!< Acknowledge Error 15 Interrupt Enable /
Kojto	122:f9eeca106725	4346	#define DSI_IER0_PE0IE 0x00010000U /!< PHY Error 0 Interrupt Enable /
Kojto	122:f9eeca106725	4347	#define DSI_IER0_PE1IE 0x00020000U /!< PHY Error 1 Interrupt Enable /
Kojto	122:f9eeca106725	4348	#define DSI_IER0_PE2IE 0x00040000U /!< PHY Error 2 Interrupt Enable /
Kojto	122:f9eeca106725	4349	#define DSI_IER0_PE3IE 0x00080000U /!< PHY Error 3 Interrupt Enable /
Kojto	122:f9eeca106725	4350	#define DSI_IER0_PE4IE 0x00100000U /!< PHY Error 4 Interrupt Enable /
Kojto	110:165afa46840b	4351
Kojto	110:165afa46840b	4352	/***************** Bit definition for DSI_IER1 register *************/
Kojto	122:f9eeca106725	4353	#define DSI_IER1_TOHSTXIE 0x00000001U /!< Timeout High-Speed Transmission Interrupt Enable /
Kojto	122:f9eeca106725	4354	#define DSI_IER1_TOLPRXIE 0x00000002U /!< Timeout Low-Power Reception Interrupt Enable /
Kojto	122:f9eeca106725	4355	#define DSI_IER1_ECCSEIE 0x00000004U /!< ECC Single-bit Error Interrupt Enable /
Kojto	122:f9eeca106725	4356	#define DSI_IER1_ECCMEIE 0x00000008U /!< ECC Multi-bit Error Interrupt Enable /
Kojto	122:f9eeca106725	4357	#define DSI_IER1_CRCEIE 0x00000010U /!< CRC Error Interrupt Enable /
Kojto	122:f9eeca106725	4358	#define DSI_IER1_PSEIE 0x00000020U /!< Packet Size Error Interrupt Enable /
Kojto	122:f9eeca106725	4359	#define DSI_IER1_EOTPEIE 0x00000040U /!< EoTp Error Interrupt Enable /
Kojto	122:f9eeca106725	4360	#define DSI_IER1_LPWREIE 0x00000080U /!< LTDC Payload Write Error Interrupt Enable /
Kojto	122:f9eeca106725	4361	#define DSI_IER1_GCWREIE 0x00000100U /!< Generic Command Write Error Interrupt Enable /
Kojto	122:f9eeca106725	4362	#define DSI_IER1_GPWREIE 0x00000200U /!< Generic Payload Write Error Interrupt Enable /
Kojto	122:f9eeca106725	4363	#define DSI_IER1_GPTXEIE 0x00000400U /!< Generic Payload Transmit Error Interrupt Enable /
Kojto	122:f9eeca106725	4364	#define DSI_IER1_GPRDEIE 0x00000800U /!< Generic Payload Read Error Interrupt Enable /
Kojto	122:f9eeca106725	4365	#define DSI_IER1_GPRXEIE 0x00001000U /!< Generic Payload Receive Error Interrupt Enable /
Kojto	110:165afa46840b	4366
Kojto	110:165afa46840b	4367	/***************** Bit definition for DSI_FIR0 register *************/
Kojto	122:f9eeca106725	4368	#define DSI_FIR0_FAE0 0x00000001U /!< Force Acknowledge Error 0 /
Kojto	122:f9eeca106725	4369	#define DSI_FIR0_FAE1 0x00000002U /!< Force Acknowledge Error 1 /
Kojto	122:f9eeca106725	4370	#define DSI_FIR0_FAE2 0x00000004U /!< Force Acknowledge Error 2 /
Kojto	122:f9eeca106725	4371	#define DSI_FIR0_FAE3 0x00000008U /!< Force Acknowledge Error 3 /
Kojto	122:f9eeca106725	4372	#define DSI_FIR0_FAE4 0x00000010U /!< Force Acknowledge Error 4 /
Kojto	122:f9eeca106725	4373	#define DSI_FIR0_FAE5 0x00000020U /!< Force Acknowledge Error 5 /
Kojto	122:f9eeca106725	4374	#define DSI_FIR0_FAE6 0x00000040U /!< Force Acknowledge Error 6 /
Kojto	122:f9eeca106725	4375	#define DSI_FIR0_FAE7 0x00000080U /!< Force Acknowledge Error 7 /
Kojto	122:f9eeca106725	4376	#define DSI_FIR0_FAE8 0x00000100U /!< Force Acknowledge Error 8 /
Kojto	122:f9eeca106725	4377	#define DSI_FIR0_FAE9 0x00000200U /!< Force Acknowledge Error 9 /
Kojto	122:f9eeca106725	4378	#define DSI_FIR0_FAE10 0x00000400U /!< Force Acknowledge Error 10 /
Kojto	122:f9eeca106725	4379	#define DSI_FIR0_FAE11 0x00000800U /!< Force Acknowledge Error 11 /
Kojto	122:f9eeca106725	4380	#define DSI_FIR0_FAE12 0x00001000U /!< Force Acknowledge Error 12 /
Kojto	122:f9eeca106725	4381	#define DSI_FIR0_FAE13 0x00002000U /!< Force Acknowledge Error 13 /
Kojto	122:f9eeca106725	4382	#define DSI_FIR0_FAE14 0x00004000U /!< Force Acknowledge Error 14 /
Kojto	122:f9eeca106725	4383	#define DSI_FIR0_FAE15 0x00008000U /!< Force Acknowledge Error 15 /
Kojto	122:f9eeca106725	4384	#define DSI_FIR0_FPE0 0x00010000U /!< Force PHY Error 0 /
Kojto	122:f9eeca106725	4385	#define DSI_FIR0_FPE1 0x00020000U /!< Force PHY Error 1 /
Kojto	122:f9eeca106725	4386	#define DSI_FIR0_FPE2 0x00040000U /!< Force PHY Error 2 /
Kojto	122:f9eeca106725	4387	#define DSI_FIR0_FPE3 0x00080000U /!< Force PHY Error 3 /
Kojto	122:f9eeca106725	4388	#define DSI_FIR0_FPE4 0x00100000U /!< Force PHY Error 4 /
Kojto	110:165afa46840b	4389
Kojto	110:165afa46840b	4390	/***************** Bit definition for DSI_FIR1 register *************/
Kojto	122:f9eeca106725	4391	#define DSI_FIR1_FTOHSTX 0x00000001U /!< Force Timeout High-Speed Transmission /
Kojto	122:f9eeca106725	4392	#define DSI_FIR1_FTOLPRX 0x00000002U /!< Force Timeout Low-Power Reception /
Kojto	122:f9eeca106725	4393	#define DSI_FIR1_FECCSE 0x00000004U /!< Force ECC Single-bit Error /
Kojto	122:f9eeca106725	4394	#define DSI_FIR1_FECCME 0x00000008U /!< Force ECC Multi-bit Error /
Kojto	122:f9eeca106725	4395	#define DSI_FIR1_FCRCE 0x00000010U /!< Force CRC Error /
Kojto	122:f9eeca106725	4396	#define DSI_FIR1_FPSE 0x00000020U /!< Force Packet Size Error /
Kojto	122:f9eeca106725	4397	#define DSI_FIR1_FEOTPE 0x00000040U /!< Force EoTp Error /
Kojto	122:f9eeca106725	4398	#define DSI_FIR1_FLPWRE 0x00000080U /!< Force LTDC Payload Write Error /
Kojto	122:f9eeca106725	4399	#define DSI_FIR1_FGCWRE 0x00000100U /!< Force Generic Command Write Error /
Kojto	122:f9eeca106725	4400	#define DSI_FIR1_FGPWRE 0x00000200U /!< Force Generic Payload Write Error /
Kojto	122:f9eeca106725	4401	#define DSI_FIR1_FGPTXE 0x00000400U /!< Force Generic Payload Transmit Error /
Kojto	122:f9eeca106725	4402	#define DSI_FIR1_FGPRDE 0x00000800U /!< Force Generic Payload Read Error /
Kojto	122:f9eeca106725	4403	#define DSI_FIR1_FGPRXE 0x00001000U /!< Force Generic Payload Receive Error /
Kojto	110:165afa46840b	4404
Kojto	110:165afa46840b	4405	/***************** Bit definition for DSI_VSCR register *************/
Kojto	122:f9eeca106725	4406	#define DSI_VSCR_EN 0x00000001U /!< Enable /
Kojto	122:f9eeca106725	4407	#define DSI_VSCR_UR 0x00000100U /!< Update Register /
Kojto	110:165afa46840b	4408
Kojto	110:165afa46840b	4409	/***************** Bit definition for DSI_LCVCIDR register **********/
Kojto	122:f9eeca106725	4410	#define DSI_LCVCIDR_VCID 0x00000003U /!< Virtual Channel ID /
Kojto	122:f9eeca106725	4411	#define DSI_LCVCIDR_VCID0 0x00000001U
Kojto	122:f9eeca106725	4412	#define DSI_LCVCIDR_VCID1 0x00000002U
Kojto	110:165afa46840b	4413
Kojto	110:165afa46840b	4414	/***************** Bit definition for DSI_LCCCR register ************/
Kojto	122:f9eeca106725	4415	#define DSI_LCCCR_COLC 0x0000000FU /!< Color Coding /
Kojto	122:f9eeca106725	4416	#define DSI_LCCCR_COLC0 0x00000001U
Kojto	122:f9eeca106725	4417	#define DSI_LCCCR_COLC1 0x00000002U
Kojto	122:f9eeca106725	4418	#define DSI_LCCCR_COLC2 0x00000004U
Kojto	122:f9eeca106725	4419	#define DSI_LCCCR_COLC3 0x00000008U
Kojto	122:f9eeca106725	4420
Kojto	122:f9eeca106725	4421	#define DSI_LCCCR_LPE 0x00000100U /!< Loosely Packed Enable /
Kojto	110:165afa46840b	4422
Kojto	110:165afa46840b	4423	/***************** Bit definition for DSI_LPMCCR register ***********/
Kojto	122:f9eeca106725	4424	#define DSI_LPMCCR_VLPSIZE 0x000000FFU /!< VACT Largest Packet Size /
Kojto	122:f9eeca106725	4425	#define DSI_LPMCCR_VLPSIZE0 0x00000001U
Kojto	122:f9eeca106725	4426	#define DSI_LPMCCR_VLPSIZE1 0x00000002U
Kojto	122:f9eeca106725	4427	#define DSI_LPMCCR_VLPSIZE2 0x00000004U
Kojto	122:f9eeca106725	4428	#define DSI_LPMCCR_VLPSIZE3 0x00000008U
Kojto	122:f9eeca106725	4429	#define DSI_LPMCCR_VLPSIZE4 0x00000010U
Kojto	122:f9eeca106725	4430	#define DSI_LPMCCR_VLPSIZE5 0x00000020U
Kojto	122:f9eeca106725	4431	#define DSI_LPMCCR_VLPSIZE6 0x00000040U
Kojto	122:f9eeca106725	4432	#define DSI_LPMCCR_VLPSIZE7 0x00000080U
Kojto	122:f9eeca106725	4433
Kojto	122:f9eeca106725	4434	#define DSI_LPMCCR_LPSIZE 0x00FF0000U /!< Largest Packet Size /
Kojto	122:f9eeca106725	4435	#define DSI_LPMCCR_LPSIZE0 0x00010000U
Kojto	122:f9eeca106725	4436	#define DSI_LPMCCR_LPSIZE1 0x00020000U
Kojto	122:f9eeca106725	4437	#define DSI_LPMCCR_LPSIZE2 0x00040000U
Kojto	122:f9eeca106725	4438	#define DSI_LPMCCR_LPSIZE3 0x00080000U
Kojto	122:f9eeca106725	4439	#define DSI_LPMCCR_LPSIZE4 0x00100000U
Kojto	122:f9eeca106725	4440	#define DSI_LPMCCR_LPSIZE5 0x00200000U
Kojto	122:f9eeca106725	4441	#define DSI_LPMCCR_LPSIZE6 0x00400000U
Kojto	122:f9eeca106725	4442	#define DSI_LPMCCR_LPSIZE7 0x00800000U
Kojto	110:165afa46840b	4443
Kojto	110:165afa46840b	4444	/***************** Bit definition for DSI_VMCCR register ************/
Kojto	122:f9eeca106725	4445	#define DSI_VMCCR_VMT 0x00000003U /!< Video Mode Type /
Kojto	122:f9eeca106725	4446	#define DSI_VMCCR_VMT0 0x00000001U
Kojto	122:f9eeca106725	4447	#define DSI_VMCCR_VMT1 0x00000002U
Kojto	122:f9eeca106725	4448
Kojto	122:f9eeca106725	4449	#define DSI_VMCCR_LPVSAE 0x00000100U /!< Low-power Vertical Sync time Enable /
Kojto	122:f9eeca106725	4450	#define DSI_VMCCR_LPVBPE 0x00000200U /!< Low-power Vertical Back-porch Enable /
Kojto	122:f9eeca106725	4451	#define DSI_VMCCR_LPVFPE 0x00000400U /!< Low-power Vertical Front-porch Enable /
Kojto	122:f9eeca106725	4452	#define DSI_VMCCR_LPVAE 0x00000800U /!< Low-power Vertical Active Enable /
Kojto	122:f9eeca106725	4453	#define DSI_VMCCR_LPHBPE 0x00001000U /!< Low-power Horizontal Back-porch Enable /
Kojto	122:f9eeca106725	4454	#define DSI_VMCCR_LPHFE 0x00002000U /!< Low-power Horizontal Front-porch Enable /
Kojto	122:f9eeca106725	4455	#define DSI_VMCCR_FBTAAE 0x00004000U /!< Frame BTA Acknowledge Enable /
Kojto	122:f9eeca106725	4456	#define DSI_VMCCR_LPCE 0x00008000U /!< Low-power Command Enable /
Kojto	110:165afa46840b	4457
Kojto	110:165afa46840b	4458	/***************** Bit definition for DSI_VPCCR register ************/
Kojto	122:f9eeca106725	4459	#define DSI_VPCCR_VPSIZE 0x00003FFFU /!< Video Packet Size /
Kojto	122:f9eeca106725	4460	#define DSI_VPCCR_VPSIZE0 0x00000001U
Kojto	122:f9eeca106725	4461	#define DSI_VPCCR_VPSIZE1 0x00000002U
Kojto	122:f9eeca106725	4462	#define DSI_VPCCR_VPSIZE2 0x00000004U
Kojto	122:f9eeca106725	4463	#define DSI_VPCCR_VPSIZE3 0x00000008U
Kojto	122:f9eeca106725	4464	#define DSI_VPCCR_VPSIZE4 0x00000010U
Kojto	122:f9eeca106725	4465	#define DSI_VPCCR_VPSIZE5 0x00000020U
Kojto	122:f9eeca106725	4466	#define DSI_VPCCR_VPSIZE6 0x00000040U
Kojto	122:f9eeca106725	4467	#define DSI_VPCCR_VPSIZE7 0x00000080U
Kojto	122:f9eeca106725	4468	#define DSI_VPCCR_VPSIZE8 0x00000100U
Kojto	122:f9eeca106725	4469	#define DSI_VPCCR_VPSIZE9 0x00000200U
Kojto	122:f9eeca106725	4470	#define DSI_VPCCR_VPSIZE10 0x00000400U
Kojto	122:f9eeca106725	4471	#define DSI_VPCCR_VPSIZE11 0x00000800U
Kojto	122:f9eeca106725	4472	#define DSI_VPCCR_VPSIZE12 0x00001000U
Kojto	122:f9eeca106725	4473	#define DSI_VPCCR_VPSIZE13 0x00002000U
Kojto	110:165afa46840b	4474
Kojto	110:165afa46840b	4475	/***************** Bit definition for DSI_VCCCR register ************/
Kojto	122:f9eeca106725	4476	#define DSI_VCCCR_NUMC 0x00001FFFU /!< Number of Chunks /
Kojto	122:f9eeca106725	4477	#define DSI_VCCCR_NUMC0 0x00000001U
Kojto	122:f9eeca106725	4478	#define DSI_VCCCR_NUMC1 0x00000002U
Kojto	122:f9eeca106725	4479	#define DSI_VCCCR_NUMC2 0x00000004U
Kojto	122:f9eeca106725	4480	#define DSI_VCCCR_NUMC3 0x00000008U
Kojto	122:f9eeca106725	4481	#define DSI_VCCCR_NUMC4 0x00000010U
Kojto	122:f9eeca106725	4482	#define DSI_VCCCR_NUMC5 0x00000020U
Kojto	122:f9eeca106725	4483	#define DSI_VCCCR_NUMC6 0x00000040U
Kojto	122:f9eeca106725	4484	#define DSI_VCCCR_NUMC7 0x00000080U
Kojto	122:f9eeca106725	4485	#define DSI_VCCCR_NUMC8 0x00000100U
Kojto	122:f9eeca106725	4486	#define DSI_VCCCR_NUMC9 0x00000200U
Kojto	122:f9eeca106725	4487	#define DSI_VCCCR_NUMC10 0x00000400U
Kojto	122:f9eeca106725	4488	#define DSI_VCCCR_NUMC11 0x00000800U
Kojto	122:f9eeca106725	4489	#define DSI_VCCCR_NUMC12 0x00001000U
Kojto	110:165afa46840b	4490
Kojto	110:165afa46840b	4491	/***************** Bit definition for DSI_VNPCCR register ***********/
Kojto	122:f9eeca106725	4492	#define DSI_VNPCCR_NPSIZE 0x00001FFFU /!< Number of Chunks /
Kojto	122:f9eeca106725	4493	#define DSI_VNPCCR_NPSIZE0 0x00000001U
Kojto	122:f9eeca106725	4494	#define DSI_VNPCCR_NPSIZE1 0x00000002U
Kojto	122:f9eeca106725	4495	#define DSI_VNPCCR_NPSIZE2 0x00000004U
Kojto	122:f9eeca106725	4496	#define DSI_VNPCCR_NPSIZE3 0x00000008U
Kojto	122:f9eeca106725	4497	#define DSI_VNPCCR_NPSIZE4 0x00000010U
Kojto	122:f9eeca106725	4498	#define DSI_VNPCCR_NPSIZE5 0x00000020U
Kojto	122:f9eeca106725	4499	#define DSI_VNPCCR_NPSIZE6 0x00000040U
Kojto	122:f9eeca106725	4500	#define DSI_VNPCCR_NPSIZE7 0x00000080U
Kojto	122:f9eeca106725	4501	#define DSI_VNPCCR_NPSIZE8 0x00000100U
Kojto	122:f9eeca106725	4502	#define DSI_VNPCCR_NPSIZE9 0x00000200U
Kojto	122:f9eeca106725	4503	#define DSI_VNPCCR_NPSIZE10 0x00000400U
Kojto	122:f9eeca106725	4504	#define DSI_VNPCCR_NPSIZE11 0x00000800U
Kojto	122:f9eeca106725	4505	#define DSI_VNPCCR_NPSIZE12 0x00001000U
Kojto	110:165afa46840b	4506
Kojto	110:165afa46840b	4507	/***************** Bit definition for DSI_VHSACCR register **********/
Kojto	122:f9eeca106725	4508	#define DSI_VHSACCR_HSA 0x00000FFFU /!< Horizontal Synchronism Active duration /
Kojto	122:f9eeca106725	4509	#define DSI_VHSACCR_HSA0 0x00000001U
Kojto	122:f9eeca106725	4510	#define DSI_VHSACCR_HSA1 0x00000002U
Kojto	122:f9eeca106725	4511	#define DSI_VHSACCR_HSA2 0x00000004U
Kojto	122:f9eeca106725	4512	#define DSI_VHSACCR_HSA3 0x00000008U
Kojto	122:f9eeca106725	4513	#define DSI_VHSACCR_HSA4 0x00000010U
Kojto	122:f9eeca106725	4514	#define DSI_VHSACCR_HSA5 0x00000020U
Kojto	122:f9eeca106725	4515	#define DSI_VHSACCR_HSA6 0x00000040U
Kojto	122:f9eeca106725	4516	#define DSI_VHSACCR_HSA7 0x00000080U
Kojto	122:f9eeca106725	4517	#define DSI_VHSACCR_HSA8 0x00000100U
Kojto	122:f9eeca106725	4518	#define DSI_VHSACCR_HSA9 0x00000200U
Kojto	122:f9eeca106725	4519	#define DSI_VHSACCR_HSA10 0x00000400U
Kojto	122:f9eeca106725	4520	#define DSI_VHSACCR_HSA11 0x00000800U
Kojto	110:165afa46840b	4521
Kojto	110:165afa46840b	4522	/***************** Bit definition for DSI_VHBPCCR register **********/
Kojto	122:f9eeca106725	4523	#define DSI_VHBPCCR_HBP 0x00000FFFU /!< Horizontal Back-Porch duration /
Kojto	122:f9eeca106725	4524	#define DSI_VHBPCCR_HBP0 0x00000001U
Kojto	122:f9eeca106725	4525	#define DSI_VHBPCCR_HBP1 0x00000002U
Kojto	122:f9eeca106725	4526	#define DSI_VHBPCCR_HBP2 0x00000004U
Kojto	122:f9eeca106725	4527	#define DSI_VHBPCCR_HBP3 0x00000008U
Kojto	122:f9eeca106725	4528	#define DSI_VHBPCCR_HBP4 0x00000010U
Kojto	122:f9eeca106725	4529	#define DSI_VHBPCCR_HBP5 0x00000020U
Kojto	122:f9eeca106725	4530	#define DSI_VHBPCCR_HBP6 0x00000040U
Kojto	122:f9eeca106725	4531	#define DSI_VHBPCCR_HBP7 0x00000080U
Kojto	122:f9eeca106725	4532	#define DSI_VHBPCCR_HBP8 0x00000100U
Kojto	122:f9eeca106725	4533	#define DSI_VHBPCCR_HBP9 0x00000200U
Kojto	122:f9eeca106725	4534	#define DSI_VHBPCCR_HBP10 0x00000400U
Kojto	122:f9eeca106725	4535	#define DSI_VHBPCCR_HBP11 0x00000800U
Kojto	110:165afa46840b	4536
Kojto	110:165afa46840b	4537	/***************** Bit definition for DSI_VLCCR register ************/
Kojto	122:f9eeca106725	4538	#define DSI_VLCCR_HLINE 0x00007FFFU /!< Horizontal Line duration /
Kojto	122:f9eeca106725	4539	#define DSI_VLCCR_HLINE0 0x00000001U
Kojto	122:f9eeca106725	4540	#define DSI_VLCCR_HLINE1 0x00000002U
Kojto	122:f9eeca106725	4541	#define DSI_VLCCR_HLINE2 0x00000004U
Kojto	122:f9eeca106725	4542	#define DSI_VLCCR_HLINE3 0x00000008U
Kojto	122:f9eeca106725	4543	#define DSI_VLCCR_HLINE4 0x00000010U
Kojto	122:f9eeca106725	4544	#define DSI_VLCCR_HLINE5 0x00000020U
Kojto	122:f9eeca106725	4545	#define DSI_VLCCR_HLINE6 0x00000040U
Kojto	122:f9eeca106725	4546	#define DSI_VLCCR_HLINE7 0x00000080U
Kojto	122:f9eeca106725	4547	#define DSI_VLCCR_HLINE8 0x00000100U
Kojto	122:f9eeca106725	4548	#define DSI_VLCCR_HLINE9 0x00000200U
Kojto	122:f9eeca106725	4549	#define DSI_VLCCR_HLINE10 0x00000400U
Kojto	122:f9eeca106725	4550	#define DSI_VLCCR_HLINE11 0x00000800U
Kojto	122:f9eeca106725	4551	#define DSI_VLCCR_HLINE12 0x00001000U
Kojto	122:f9eeca106725	4552	#define DSI_VLCCR_HLINE13 0x00002000U
Kojto	122:f9eeca106725	4553	#define DSI_VLCCR_HLINE14 0x00004000U
Kojto	110:165afa46840b	4554
Kojto	110:165afa46840b	4555	/***************** Bit definition for DSI_VVSACCR register *************/
Kojto	122:f9eeca106725	4556	#define DSI_VVSACCR_VSA 0x000003FFU /!< Vertical Synchronism Active duration /
Kojto	122:f9eeca106725	4557	#define DSI_VVSACCR_VSA0 0x00000001U
Kojto	122:f9eeca106725	4558	#define DSI_VVSACCR_VSA1 0x00000002U
Kojto	122:f9eeca106725	4559	#define DSI_VVSACCR_VSA2 0x00000004U
Kojto	122:f9eeca106725	4560	#define DSI_VVSACCR_VSA3 0x00000008U
Kojto	122:f9eeca106725	4561	#define DSI_VVSACCR_VSA4 0x00000010U
Kojto	122:f9eeca106725	4562	#define DSI_VVSACCR_VSA5 0x00000020U
Kojto	122:f9eeca106725	4563	#define DSI_VVSACCR_VSA6 0x00000040U
Kojto	122:f9eeca106725	4564	#define DSI_VVSACCR_VSA7 0x00000080U
Kojto	122:f9eeca106725	4565	#define DSI_VVSACCR_VSA8 0x00000100U
Kojto	122:f9eeca106725	4566	#define DSI_VVSACCR_VSA9 0x00000200U
Kojto	110:165afa46840b	4567
Kojto	110:165afa46840b	4568	/***************** Bit definition for DSI_VVBPCCR register **********/
Kojto	122:f9eeca106725	4569	#define DSI_VVBPCCR_VBP 0x000003FFU /!< Vertical Back-Porch duration /
Kojto	122:f9eeca106725	4570	#define DSI_VVBPCCR_VBP0 0x00000001U
Kojto	122:f9eeca106725	4571	#define DSI_VVBPCCR_VBP1 0x00000002U
Kojto	122:f9eeca106725	4572	#define DSI_VVBPCCR_VBP2 0x00000004U
Kojto	122:f9eeca106725	4573	#define DSI_VVBPCCR_VBP3 0x00000008U
Kojto	122:f9eeca106725	4574	#define DSI_VVBPCCR_VBP4 0x00000010U
Kojto	122:f9eeca106725	4575	#define DSI_VVBPCCR_VBP5 0x00000020U
Kojto	122:f9eeca106725	4576	#define DSI_VVBPCCR_VBP6 0x00000040U
Kojto	122:f9eeca106725	4577	#define DSI_VVBPCCR_VBP7 0x00000080U
Kojto	122:f9eeca106725	4578	#define DSI_VVBPCCR_VBP8 0x00000100U
Kojto	122:f9eeca106725	4579	#define DSI_VVBPCCR_VBP9 0x00000200U
Kojto	110:165afa46840b	4580
Kojto	110:165afa46840b	4581	/***************** Bit definition for DSI_VVFPCCR register **********/
Kojto	122:f9eeca106725	4582	#define DSI_VVFPCCR_VFP 0x000003FFU /!< Vertical Front-Porch duration /
Kojto	122:f9eeca106725	4583	#define DSI_VVFPCCR_VFP0 0x00000001U
Kojto	122:f9eeca106725	4584	#define DSI_VVFPCCR_VFP1 0x00000002U
Kojto	122:f9eeca106725	4585	#define DSI_VVFPCCR_VFP2 0x00000004U
Kojto	122:f9eeca106725	4586	#define DSI_VVFPCCR_VFP3 0x00000008U
Kojto	122:f9eeca106725	4587	#define DSI_VVFPCCR_VFP4 0x00000010U
Kojto	122:f9eeca106725	4588	#define DSI_VVFPCCR_VFP5 0x00000020U
Kojto	122:f9eeca106725	4589	#define DSI_VVFPCCR_VFP6 0x00000040U
Kojto	122:f9eeca106725	4590	#define DSI_VVFPCCR_VFP7 0x00000080U
Kojto	122:f9eeca106725	4591	#define DSI_VVFPCCR_VFP8 0x00000100U
Kojto	122:f9eeca106725	4592	#define DSI_VVFPCCR_VFP9 0x00000200U
Kojto	110:165afa46840b	4593
Kojto	110:165afa46840b	4594	/***************** Bit definition for DSI_VVACCR register ***********/
Kojto	122:f9eeca106725	4595	#define DSI_VVACCR_VA 0x00003FFFU /!< Vertical Active duration /
Kojto	122:f9eeca106725	4596	#define DSI_VVACCR_VA0 0x00000001U
Kojto	122:f9eeca106725	4597	#define DSI_VVACCR_VA1 0x00000002U
Kojto	122:f9eeca106725	4598	#define DSI_VVACCR_VA2 0x00000004U
Kojto	122:f9eeca106725	4599	#define DSI_VVACCR_VA3 0x00000008U
Kojto	122:f9eeca106725	4600	#define DSI_VVACCR_VA4 0x00000010U
Kojto	122:f9eeca106725	4601	#define DSI_VVACCR_VA5 0x00000020U
Kojto	122:f9eeca106725	4602	#define DSI_VVACCR_VA6 0x00000040U
Kojto	122:f9eeca106725	4603	#define DSI_VVACCR_VA7 0x00000080U
Kojto	122:f9eeca106725	4604	#define DSI_VVACCR_VA8 0x00000100U
Kojto	122:f9eeca106725	4605	#define DSI_VVACCR_VA9 0x00000200U
Kojto	122:f9eeca106725	4606	#define DSI_VVACCR_VA10 0x00000400U
Kojto	122:f9eeca106725	4607	#define DSI_VVACCR_VA11 0x00000800U
Kojto	122:f9eeca106725	4608	#define DSI_VVACCR_VA12 0x00001000U
Kojto	122:f9eeca106725	4609	#define DSI_VVACCR_VA13 0x00002000U
Kojto	110:165afa46840b	4610
Kojto	110:165afa46840b	4611	/***************** Bit definition for DSI_TDCCR register ************/
Kojto	122:f9eeca106725	4612	#define DSI_TDCCR_3DM 0x00000003U /!< 3D Mode /
Kojto	122:f9eeca106725	4613	#define DSI_TDCCR_3DM0 0x00000001U
Kojto	122:f9eeca106725	4614	#define DSI_TDCCR_3DM1 0x00000002U
Kojto	122:f9eeca106725	4615
Kojto	122:f9eeca106725	4616	#define DSI_TDCCR_3DF 0x0000000CU /!< 3D Format /
Kojto	122:f9eeca106725	4617	#define DSI_TDCCR_3DF0 0x00000004U
Kojto	122:f9eeca106725	4618	#define DSI_TDCCR_3DF1 0x00000008U
Kojto	122:f9eeca106725	4619
Kojto	122:f9eeca106725	4620	#define DSI_TDCCR_SVS 0x00000010U /!< Second VSYNC /
Kojto	122:f9eeca106725	4621	#define DSI_TDCCR_RF 0x00000020U /!< Right First /
Kojto	122:f9eeca106725	4622	#define DSI_TDCCR_S3DC 0x00010000U /!< Send 3D Control /
Kojto	110:165afa46840b	4623
Kojto	110:165afa46840b	4624	/***************** Bit definition for DSI_WCFGR register *************/
Kojto	122:f9eeca106725	4625	#define DSI_WCFGR_DSIM 0x00000001U /!< DSI Mode /
Kojto	122:f9eeca106725	4626	#define DSI_WCFGR_COLMUX 0x0000000EU /!< Color Multiplexing /
Kojto	122:f9eeca106725	4627	#define DSI_WCFGR_COLMUX0 0x00000002U
Kojto	122:f9eeca106725	4628	#define DSI_WCFGR_COLMUX1 0x00000004U
Kojto	122:f9eeca106725	4629	#define DSI_WCFGR_COLMUX2 0x00000008U
Kojto	122:f9eeca106725	4630
Kojto	122:f9eeca106725	4631	#define DSI_WCFGR_TESRC 0x00000010U /!< Tearing Effect Source /
Kojto	122:f9eeca106725	4632	#define DSI_WCFGR_TEPOL 0x00000020U /!< Tearing Effect Polarity /
Kojto	122:f9eeca106725	4633	#define DSI_WCFGR_AR 0x00000040U /!< Automatic Refresh /
Kojto	122:f9eeca106725	4634	#define DSI_WCFGR_VSPOL 0x00000080U /!< VSync Polarity /
Kojto	110:165afa46840b	4635
Kojto	110:165afa46840b	4636	/***************** Bit definition for DSI_WCR register ***************/
Kojto	122:f9eeca106725	4637	#define DSI_WCR_COLM 0x00000001U /!< Color Mode /
Kojto	122:f9eeca106725	4638	#define DSI_WCR_SHTDN 0x00000002U /!< Shutdown /
Kojto	122:f9eeca106725	4639	#define DSI_WCR_LTDCEN 0x00000004U /!< LTDC Enable /
Kojto	122:f9eeca106725	4640	#define DSI_WCR_DSIEN 0x00000008U /!< DSI Enable /
Kojto	110:165afa46840b	4641
Kojto	110:165afa46840b	4642	/***************** Bit definition for DSI_WIER register **************/
Kojto	122:f9eeca106725	4643	#define DSI_WIER_TEIE 0x00000001U /!< Tearing Effect Interrupt Enable /
Kojto	122:f9eeca106725	4644	#define DSI_WIER_ERIE 0x00000002U /!< End of Refresh Interrupt Enable /
Kojto	122:f9eeca106725	4645	#define DSI_WIER_PLLLIE 0x00000200U /!< PLL Lock Interrupt Enable /
Kojto	122:f9eeca106725	4646	#define DSI_WIER_PLLUIE 0x00000400U /!< PLL Unlock Interrupt Enable /
Kojto	122:f9eeca106725	4647	#define DSI_WIER_RRIE 0x00002000U /!< Regulator Ready Interrupt Enable /
Kojto	110:165afa46840b	4648
Kojto	110:165afa46840b	4649	/***************** Bit definition for DSI_WISR register **************/
Kojto	122:f9eeca106725	4650	#define DSI_WISR_TEIF 0x00000001U /!< Tearing Effect Interrupt Flag /
Kojto	122:f9eeca106725	4651	#define DSI_WISR_ERIF 0x00000002U /!< End of Refresh Interrupt Flag /
Kojto	122:f9eeca106725	4652	#define DSI_WISR_BUSY 0x00000004U /!< Busy Flag /
Kojto	122:f9eeca106725	4653	#define DSI_WISR_PLLLS 0x00000100U /!< PLL Lock Status /
Kojto	122:f9eeca106725	4654	#define DSI_WISR_PLLLIF 0x00000200U /!< PLL Lock Interrupt Flag /
Kojto	122:f9eeca106725	4655	#define DSI_WISR_PLLUIF 0x00000400U /!< PLL Unlock Interrupt Flag /
Kojto	122:f9eeca106725	4656	#define DSI_WISR_RRS 0x00001000U /!< Regulator Ready Flag /
Kojto	122:f9eeca106725	4657	#define DSI_WISR_RRIF 0x00002000U /!< Regulator Ready Interrupt Flag /
Kojto	110:165afa46840b	4658
Kojto	110:165afa46840b	4659	/***************** Bit definition for DSI_WIFCR register *************/
Kojto	122:f9eeca106725	4660	#define DSI_WIFCR_CTEIF 0x00000001U /!< Clear Tearing Effect Interrupt Flag /
Kojto	122:f9eeca106725	4661	#define DSI_WIFCR_CERIF 0x00000002U /!< Clear End of Refresh Interrupt Flag /
Kojto	122:f9eeca106725	4662	#define DSI_WIFCR_CPLLLIF 0x00000200U /!< Clear PLL Lock Interrupt Flag /
Kojto	122:f9eeca106725	4663	#define DSI_WIFCR_CPLLUIF 0x00000400U /!< Clear PLL Unlock Interrupt Flag /
Kojto	122:f9eeca106725	4664	#define DSI_WIFCR_CRRIF 0x00002000U /!< Clear Regulator Ready Interrupt Flag /
Kojto	110:165afa46840b	4665
Kojto	110:165afa46840b	4666	/***************** Bit definition for DSI_WPCR0 register *************/
Kojto	122:f9eeca106725	4667	#define DSI_WPCR0_UIX4 0x0000003FU /!< Unit Interval multiplied by 4 /
Kojto	122:f9eeca106725	4668	#define DSI_WPCR0_UIX4_0 0x00000001U
Kojto	122:f9eeca106725	4669	#define DSI_WPCR0_UIX4_1 0x00000002U
Kojto	122:f9eeca106725	4670	#define DSI_WPCR0_UIX4_2 0x00000004U
Kojto	122:f9eeca106725	4671	#define DSI_WPCR0_UIX4_3 0x00000008U
Kojto	122:f9eeca106725	4672	#define DSI_WPCR0_UIX4_4 0x00000010U
Kojto	122:f9eeca106725	4673	#define DSI_WPCR0_UIX4_5 0x00000020U
Kojto	122:f9eeca106725	4674
Kojto	122:f9eeca106725	4675	#define DSI_WPCR0_SWCL 0x00000040U /!< Swap pins on clock lane /
Kojto	122:f9eeca106725	4676	#define DSI_WPCR0_SWDL0 0x00000080U /!< Swap pins on data lane 1 /
Kojto	122:f9eeca106725	4677	#define DSI_WPCR0_SWDL1 0x00000100U /!< Swap pins on data lane 2 /
Kojto	122:f9eeca106725	4678	#define DSI_WPCR0_HSICL 0x00000200U /!< Invert the high-speed data signal on clock lane /
Kojto	122:f9eeca106725	4679	#define DSI_WPCR0_HSIDL0 0x00000400U /!< Invert the high-speed data signal on lane 1 /
Kojto	122:f9eeca106725	4680	#define DSI_WPCR0_HSIDL1 0x00000800U /!< Invert the high-speed data signal on lane 2 /
Kojto	122:f9eeca106725	4681	#define DSI_WPCR0_FTXSMCL 0x00001000U /!< Force clock lane in TX stop mode /
Kojto	122:f9eeca106725	4682	#define DSI_WPCR0_FTXSMDL 0x00002000U /!< Force data lanes in TX stop mode /
Kojto	122:f9eeca106725	4683	#define DSI_WPCR0_CDOFFDL 0x00004000U /!< Contention detection OFF /
Kojto	122:f9eeca106725	4684	#define DSI_WPCR0_TDDL 0x00010000U /!< Turn Disable Data Lanes /
Kojto	122:f9eeca106725	4685	#define DSI_WPCR0_PDEN 0x00040000U /!< Pull-Down Enable /
Kojto	122:f9eeca106725	4686	#define DSI_WPCR0_TCLKPREPEN 0x00080000U /!< Timer for t-CLKPREP Enable /
Kojto	122:f9eeca106725	4687	#define DSI_WPCR0_TCLKZEROEN 0x00100000U /!< Timer for t-CLKZERO Enable /
Kojto	122:f9eeca106725	4688	#define DSI_WPCR0_THSPREPEN 0x00200000U /!< Timer for t-HSPREP Enable /
Kojto	122:f9eeca106725	4689	#define DSI_WPCR0_THSTRAILEN 0x00400000U /!< Timer for t-HSTRAIL Enable /
Kojto	122:f9eeca106725	4690	#define DSI_WPCR0_THSZEROEN 0x00800000U /!< Timer for t-HSZERO Enable /
Kojto	122:f9eeca106725	4691	#define DSI_WPCR0_TLPXDEN 0x01000000U /!< Timer for t-LPXD Enable /
Kojto	122:f9eeca106725	4692	#define DSI_WPCR0_THSEXITEN 0x02000000U /!< Timer for t-HSEXIT Enable /
Kojto	122:f9eeca106725	4693	#define DSI_WPCR0_TLPXCEN 0x04000000U /!< Timer for t-LPXC Enable /
Kojto	122:f9eeca106725	4694	#define DSI_WPCR0_TCLKPOSTEN 0x08000000U /!< Timer for t-CLKPOST Enable /
Kojto	110:165afa46840b	4695
Kojto	110:165afa46840b	4696	/***************** Bit definition for DSI_WPCR1 register *************/
Kojto	122:f9eeca106725	4697	#define DSI_WPCR1_HSTXDCL 0x00000003U /!< High-Speed Transmission Delay on Clock Lane /
Kojto	122:f9eeca106725	4698	#define DSI_WPCR1_HSTXDCL0 0x00000001U
Kojto	122:f9eeca106725	4699	#define DSI_WPCR1_HSTXDCL1 0x00000002U
Kojto	122:f9eeca106725	4700
Kojto	122:f9eeca106725	4701	#define DSI_WPCR1_HSTXDDL 0x0000000CU /!< High-Speed Transmission Delay on Data Lane /
Kojto	122:f9eeca106725	4702	#define DSI_WPCR1_HSTXDDL0 0x00000004U
Kojto	122:f9eeca106725	4703	#define DSI_WPCR1_HSTXDDL1 0x00000008U
Kojto	122:f9eeca106725	4704
Kojto	122:f9eeca106725	4705	#define DSI_WPCR1_LPSRCCL 0x000000C0U /!< Low-Power transmission Slew Rate Compensation on Clock Lane /
Kojto	122:f9eeca106725	4706	#define DSI_WPCR1_LPSRCCL0 0x00000040U
Kojto	122:f9eeca106725	4707	#define DSI_WPCR1_LPSRCCL1 0x00000080U
Kojto	122:f9eeca106725	4708
Kojto	122:f9eeca106725	4709	#define DSI_WPCR1_LPSRCDL 0x00000300U /!< Low-Power transmission Slew Rate Compensation on Data Lane /
Kojto	122:f9eeca106725	4710	#define DSI_WPCR1_LPSRCDL0 0x00000100U
Kojto	122:f9eeca106725	4711	#define DSI_WPCR1_LPSRCDL1 0x00000200U
Kojto	122:f9eeca106725	4712
Kojto	122:f9eeca106725	4713	#define DSI_WPCR1_SDDC 0x00001000U /!< SDD Control /
Kojto	122:f9eeca106725	4714
Kojto	122:f9eeca106725	4715	#define DSI_WPCR1_LPRXVCDL 0x0000C000U /!< Low-Power Reception V-IL Compensation on Data Lanes /
Kojto	122:f9eeca106725	4716	#define DSI_WPCR1_LPRXVCDL0 0x00004000U
Kojto	122:f9eeca106725	4717	#define DSI_WPCR1_LPRXVCDL1 0x00008000U
Kojto	122:f9eeca106725	4718
Kojto	122:f9eeca106725	4719	#define DSI_WPCR1_HSTXSRCCL 0x00030000U /!< High-Speed Transmission Delay on Clock Lane /
Kojto	122:f9eeca106725	4720	#define DSI_WPCR1_HSTXSRCCL0 0x00010000U
Kojto	122:f9eeca106725	4721	#define DSI_WPCR1_HSTXSRCCL1 0x00020000U
Kojto	122:f9eeca106725	4722
Kojto	122:f9eeca106725	4723	#define DSI_WPCR1_HSTXSRCDL 0x000C0000U /!< High-Speed Transmission Delay on Data Lane /
Kojto	122:f9eeca106725	4724	#define DSI_WPCR1_HSTXSRCDL0 0x00040000U
Kojto	122:f9eeca106725	4725	#define DSI_WPCR1_HSTXSRCDL1 0x00080000U
Kojto	122:f9eeca106725	4726
Kojto	122:f9eeca106725	4727	#define DSI_WPCR1_FLPRXLPM 0x00400000U /!< Forces LP Receiver in Low-Power Mode /
Kojto	122:f9eeca106725	4728
Kojto	122:f9eeca106725	4729	#define DSI_WPCR1_LPRXFT 0x06000000U /!< Low-Power RX low-pass Filtering Tuning /
Kojto	122:f9eeca106725	4730	#define DSI_WPCR1_LPRXFT0 0x02000000U
Kojto	122:f9eeca106725	4731	#define DSI_WPCR1_LPRXFT1 0x04000000U
Kojto	110:165afa46840b	4732
Kojto	110:165afa46840b	4733	/***************** Bit definition for DSI_WPCR2 register *************/
Kojto	122:f9eeca106725	4734	#define DSI_WPCR2_TCLKPREP 0x000000FFU /!< t-CLKPREP /
Kojto	122:f9eeca106725	4735	#define DSI_WPCR2_TCLKPREP0 0x00000001U
Kojto	122:f9eeca106725	4736	#define DSI_WPCR2_TCLKPREP1 0x00000002U
Kojto	122:f9eeca106725	4737	#define DSI_WPCR2_TCLKPREP2 0x00000004U
Kojto	122:f9eeca106725	4738	#define DSI_WPCR2_TCLKPREP3 0x00000008U
Kojto	122:f9eeca106725	4739	#define DSI_WPCR2_TCLKPREP4 0x00000010U
Kojto	122:f9eeca106725	4740	#define DSI_WPCR2_TCLKPREP5 0x00000020U
Kojto	122:f9eeca106725	4741	#define DSI_WPCR2_TCLKPREP6 0x00000040U
Kojto	122:f9eeca106725	4742	#define DSI_WPCR2_TCLKPREP7 0x00000080U
Kojto	122:f9eeca106725	4743
Kojto	122:f9eeca106725	4744	#define DSI_WPCR2_TCLKZERO 0x0000FF00U /!< t-CLKZERO /
Kojto	122:f9eeca106725	4745	#define DSI_WPCR2_TCLKZERO0 0x00000100U
Kojto	122:f9eeca106725	4746	#define DSI_WPCR2_TCLKZERO1 0x00000200U
Kojto	122:f9eeca106725	4747	#define DSI_WPCR2_TCLKZERO2 0x00000400U
Kojto	122:f9eeca106725	4748	#define DSI_WPCR2_TCLKZERO3 0x00000800U
Kojto	122:f9eeca106725	4749	#define DSI_WPCR2_TCLKZERO4 0x00001000U
Kojto	122:f9eeca106725	4750	#define DSI_WPCR2_TCLKZERO5 0x00002000U
Kojto	122:f9eeca106725	4751	#define DSI_WPCR2_TCLKZERO6 0x00004000U
Kojto	122:f9eeca106725	4752	#define DSI_WPCR2_TCLKZERO7 0x00008000U
Kojto	122:f9eeca106725	4753
Kojto	122:f9eeca106725	4754	#define DSI_WPCR2_THSPREP 0x00FF0000U /!< t-HSPREP /
Kojto	122:f9eeca106725	4755	#define DSI_WPCR2_THSPREP0 0x00010000U
Kojto	122:f9eeca106725	4756	#define DSI_WPCR2_THSPREP1 0x00020000U
Kojto	122:f9eeca106725	4757	#define DSI_WPCR2_THSPREP2 0x00040000U
Kojto	122:f9eeca106725	4758	#define DSI_WPCR2_THSPREP3 0x00080000U
Kojto	122:f9eeca106725	4759	#define DSI_WPCR2_THSPREP4 0x00100000U
Kojto	122:f9eeca106725	4760	#define DSI_WPCR2_THSPREP5 0x00200000U
Kojto	122:f9eeca106725	4761	#define DSI_WPCR2_THSPREP6 0x00400000U
Kojto	122:f9eeca106725	4762	#define DSI_WPCR2_THSPREP7 0x00800000U
Kojto	122:f9eeca106725	4763
Kojto	122:f9eeca106725	4764	#define DSI_WPCR2_THSTRAIL 0xFF000000U /!< t-HSTRAIL /
Kojto	122:f9eeca106725	4765	#define DSI_WPCR2_THSTRAIL0 0x01000000U
Kojto	122:f9eeca106725	4766	#define DSI_WPCR2_THSTRAIL1 0x02000000U
Kojto	122:f9eeca106725	4767	#define DSI_WPCR2_THSTRAIL2 0x04000000U
Kojto	122:f9eeca106725	4768	#define DSI_WPCR2_THSTRAIL3 0x08000000U
Kojto	122:f9eeca106725	4769	#define DSI_WPCR2_THSTRAIL4 0x10000000U
Kojto	122:f9eeca106725	4770	#define DSI_WPCR2_THSTRAIL5 0x20000000U
Kojto	122:f9eeca106725	4771	#define DSI_WPCR2_THSTRAIL6 0x40000000U
Kojto	122:f9eeca106725	4772	#define DSI_WPCR2_THSTRAIL7 0x80000000U
Kojto	110:165afa46840b	4773
Kojto	110:165afa46840b	4774	/***************** Bit definition for DSI_WPCR3 register *************/
Kojto	122:f9eeca106725	4775	#define DSI_WPCR3_THSZERO 0x000000FFU /!< t-HSZERO /
Kojto	122:f9eeca106725	4776	#define DSI_WPCR3_THSZERO0 0x00000001U
Kojto	122:f9eeca106725	4777	#define DSI_WPCR3_THSZERO1 0x00000002U
Kojto	122:f9eeca106725	4778	#define DSI_WPCR3_THSZERO2 0x00000004U
Kojto	122:f9eeca106725	4779	#define DSI_WPCR3_THSZERO3 0x00000008U
Kojto	122:f9eeca106725	4780	#define DSI_WPCR3_THSZERO4 0x00000010U
Kojto	122:f9eeca106725	4781	#define DSI_WPCR3_THSZERO5 0x00000020U
Kojto	122:f9eeca106725	4782	#define DSI_WPCR3_THSZERO6 0x00000040U
Kojto	122:f9eeca106725	4783	#define DSI_WPCR3_THSZERO7 0x00000080U
Kojto	122:f9eeca106725	4784
Kojto	122:f9eeca106725	4785	#define DSI_WPCR3_TLPXD 0x0000FF00U /!< t-LPXD /
Kojto	122:f9eeca106725	4786	#define DSI_WPCR3_TLPXD0 0x00000100U
Kojto	122:f9eeca106725	4787	#define DSI_WPCR3_TLPXD1 0x00000200U
Kojto	122:f9eeca106725	4788	#define DSI_WPCR3_TLPXD2 0x00000400U
Kojto	122:f9eeca106725	4789	#define DSI_WPCR3_TLPXD3 0x00000800U
Kojto	122:f9eeca106725	4790	#define DSI_WPCR3_TLPXD4 0x00001000U
Kojto	122:f9eeca106725	4791	#define DSI_WPCR3_TLPXD5 0x00002000U
Kojto	122:f9eeca106725	4792	#define DSI_WPCR3_TLPXD6 0x00004000U
Kojto	122:f9eeca106725	4793	#define DSI_WPCR3_TLPXD7 0x00008000U
Kojto	122:f9eeca106725	4794
Kojto	122:f9eeca106725	4795	#define DSI_WPCR3_THSEXIT 0x00FF0000U /!< t-HSEXIT /
Kojto	122:f9eeca106725	4796	#define DSI_WPCR3_THSEXIT0 0x00010000U
Kojto	122:f9eeca106725	4797	#define DSI_WPCR3_THSEXIT1 0x00020000U
Kojto	122:f9eeca106725	4798	#define DSI_WPCR3_THSEXIT2 0x00040000U
Kojto	122:f9eeca106725	4799	#define DSI_WPCR3_THSEXIT3 0x00080000U
Kojto	122:f9eeca106725	4800	#define DSI_WPCR3_THSEXIT4 0x00100000U
Kojto	122:f9eeca106725	4801	#define DSI_WPCR3_THSEXIT5 0x00200000U
Kojto	122:f9eeca106725	4802	#define DSI_WPCR3_THSEXIT6 0x00400000U
Kojto	122:f9eeca106725	4803	#define DSI_WPCR3_THSEXIT7 0x00800000U
Kojto	122:f9eeca106725	4804
Kojto	122:f9eeca106725	4805	#define DSI_WPCR3_TLPXC 0xFF000000U /!< t-LPXC /
Kojto	122:f9eeca106725	4806	#define DSI_WPCR3_TLPXC0 0x01000000U
Kojto	122:f9eeca106725	4807	#define DSI_WPCR3_TLPXC1 0x02000000U
Kojto	122:f9eeca106725	4808	#define DSI_WPCR3_TLPXC2 0x04000000U
Kojto	122:f9eeca106725	4809	#define DSI_WPCR3_TLPXC3 0x08000000U
Kojto	122:f9eeca106725	4810	#define DSI_WPCR3_TLPXC4 0x10000000U
Kojto	122:f9eeca106725	4811	#define DSI_WPCR3_TLPXC5 0x20000000U
Kojto	122:f9eeca106725	4812	#define DSI_WPCR3_TLPXC6 0x40000000U
Kojto	122:f9eeca106725	4813	#define DSI_WPCR3_TLPXC7 0x80000000U
Kojto	110:165afa46840b	4814
Kojto	110:165afa46840b	4815	/***************** Bit definition for DSI_WPCR4 register *************/
Kojto	122:f9eeca106725	4816	#define DSI_WPCR4_TCLKPOST 0x000000FFU /!< t-CLKPOST /
Kojto	122:f9eeca106725	4817	#define DSI_WPCR4_TCLKPOST0 0x00000001U
Kojto	122:f9eeca106725	4818	#define DSI_WPCR4_TCLKPOST1 0x00000002U
Kojto	122:f9eeca106725	4819	#define DSI_WPCR4_TCLKPOST2 0x00000004U
Kojto	122:f9eeca106725	4820	#define DSI_WPCR4_TCLKPOST3 0x00000008U
Kojto	122:f9eeca106725	4821	#define DSI_WPCR4_TCLKPOST4 0x00000010U
Kojto	122:f9eeca106725	4822	#define DSI_WPCR4_TCLKPOST5 0x00000020U
Kojto	122:f9eeca106725	4823	#define DSI_WPCR4_TCLKPOST6 0x00000040U
Kojto	122:f9eeca106725	4824	#define DSI_WPCR4_TCLKPOST7 0x00000080U
Kojto	110:165afa46840b	4825
Kojto	110:165afa46840b	4826	/***************** Bit definition for DSI_WRPCR register *************/
Kojto	122:f9eeca106725	4827	#define DSI_WRPCR_PLLEN 0x00000001U /!< PLL Enable /
Kojto	122:f9eeca106725	4828	#define DSI_WRPCR_PLL_NDIV 0x000001FCU /!< PLL Loop Division Factor /
Kojto	122:f9eeca106725	4829	#define DSI_WRPCR_PLL_NDIV0 0x00000004U
Kojto	122:f9eeca106725	4830	#define DSI_WRPCR_PLL_NDIV1 0x00000008U
Kojto	122:f9eeca106725	4831	#define DSI_WRPCR_PLL_NDIV2 0x00000010U
Kojto	122:f9eeca106725	4832	#define DSI_WRPCR_PLL_NDIV3 0x00000020U
Kojto	122:f9eeca106725	4833	#define DSI_WRPCR_PLL_NDIV4 0x00000040U
Kojto	122:f9eeca106725	4834	#define DSI_WRPCR_PLL_NDIV5 0x00000080U
Kojto	122:f9eeca106725	4835	#define DSI_WRPCR_PLL_NDIV6 0x00000100U
Kojto	122:f9eeca106725	4836
Kojto	122:f9eeca106725	4837	#define DSI_WRPCR_PLL_IDF 0x00007800U /!< PLL Input Division Factor /
Kojto	122:f9eeca106725	4838	#define DSI_WRPCR_PLL_IDF0 0x00000800U
Kojto	122:f9eeca106725	4839	#define DSI_WRPCR_PLL_IDF1 0x00001000U
Kojto	122:f9eeca106725	4840	#define DSI_WRPCR_PLL_IDF2 0x00002000U
Kojto	122:f9eeca106725	4841	#define DSI_WRPCR_PLL_IDF3 0x00004000U
Kojto	122:f9eeca106725	4842
Kojto	122:f9eeca106725	4843	#define DSI_WRPCR_PLL_ODF 0x00030000U /!< PLL Output Division Factor /
Kojto	122:f9eeca106725	4844	#define DSI_WRPCR_PLL_ODF0 0x00010000U
Kojto	122:f9eeca106725	4845	#define DSI_WRPCR_PLL_ODF1 0x00020000U
Kojto	122:f9eeca106725	4846
Kojto	122:f9eeca106725	4847	#define DSI_WRPCR_REGEN 0x01000000U /!< Regulator Enable /
Kojto	110:165afa46840b	4848
Kojto	110:165afa46840b	4849	/******************************************************************************/
Kojto	110:165afa46840b	4850	/* */
Kojto	110:165afa46840b	4851	/* External Interrupt/Event Controller */
Kojto	110:165afa46840b	4852	/* */
Kojto	110:165afa46840b	4853	/******************************************************************************/
Kojto	110:165afa46840b	4854	/***************** Bit definition for EXTI_IMR register *****************/
Kojto	122:f9eeca106725	4855	#define EXTI_IMR_MR0 0x00000001U /!< Interrupt Mask on line 0 /
Kojto	122:f9eeca106725	4856	#define EXTI_IMR_MR1 0x00000002U /!< Interrupt Mask on line 1 /
Kojto	122:f9eeca106725	4857	#define EXTI_IMR_MR2 0x00000004U /!< Interrupt Mask on line 2 /
Kojto	122:f9eeca106725	4858	#define EXTI_IMR_MR3 0x00000008U /!< Interrupt Mask on line 3 /
Kojto	122:f9eeca106725	4859	#define EXTI_IMR_MR4 0x00000010U /!< Interrupt Mask on line 4 /
Kojto	122:f9eeca106725	4860	#define EXTI_IMR_MR5 0x00000020U /!< Interrupt Mask on line 5 /
Kojto	122:f9eeca106725	4861	#define EXTI_IMR_MR6 0x00000040U /!< Interrupt Mask on line 6 /
Kojto	122:f9eeca106725	4862	#define EXTI_IMR_MR7 0x00000080U /!< Interrupt Mask on line 7 /
Kojto	122:f9eeca106725	4863	#define EXTI_IMR_MR8 0x00000100U /!< Interrupt Mask on line 8 /
Kojto	122:f9eeca106725	4864	#define EXTI_IMR_MR9 0x00000200U /!< Interrupt Mask on line 9 /
Kojto	122:f9eeca106725	4865	#define EXTI_IMR_MR10 0x00000400U /!< Interrupt Mask on line 10 /
Kojto	122:f9eeca106725	4866	#define EXTI_IMR_MR11 0x00000800U /!< Interrupt Mask on line 11 /
Kojto	122:f9eeca106725	4867	#define EXTI_IMR_MR12 0x00001000U /!< Interrupt Mask on line 12 /
Kojto	122:f9eeca106725	4868	#define EXTI_IMR_MR13 0x00002000U /!< Interrupt Mask on line 13 /
Kojto	122:f9eeca106725	4869	#define EXTI_IMR_MR14 0x00004000U /!< Interrupt Mask on line 14 /
Kojto	122:f9eeca106725	4870	#define EXTI_IMR_MR15 0x00008000U /!< Interrupt Mask on line 15 /
Kojto	122:f9eeca106725	4871	#define EXTI_IMR_MR16 0x00010000U /!< Interrupt Mask on line 16 /
Kojto	122:f9eeca106725	4872	#define EXTI_IMR_MR17 0x00020000U /!< Interrupt Mask on line 17 /
Kojto	122:f9eeca106725	4873	#define EXTI_IMR_MR18 0x00040000U /!< Interrupt Mask on line 18 /
Kojto	122:f9eeca106725	4874	#define EXTI_IMR_MR19 0x00080000U /!< Interrupt Mask on line 19 /
Kojto	122:f9eeca106725	4875	#define EXTI_IMR_MR20 0x00100000U /!< Interrupt Mask on line 20 /
Kojto	122:f9eeca106725	4876	#define EXTI_IMR_MR21 0x00200000U /!< Interrupt Mask on line 21 /
Kojto	122:f9eeca106725	4877	#define EXTI_IMR_MR22 0x00400000U /!< Interrupt Mask on line 22 /
Kojto	110:165afa46840b	4878
Kojto	110:165afa46840b	4879	/***************** Bit definition for EXTI_EMR register *****************/
Kojto	122:f9eeca106725	4880	#define EXTI_EMR_MR0 0x00000001U /!< Event Mask on line 0 /
Kojto	122:f9eeca106725	4881	#define EXTI_EMR_MR1 0x00000002U /!< Event Mask on line 1 /
Kojto	122:f9eeca106725	4882	#define EXTI_EMR_MR2 0x00000004U /!< Event Mask on line 2 /
Kojto	122:f9eeca106725	4883	#define EXTI_EMR_MR3 0x00000008U /!< Event Mask on line 3 /
Kojto	122:f9eeca106725	4884	#define EXTI_EMR_MR4 0x00000010U /!< Event Mask on line 4 /
Kojto	122:f9eeca106725	4885	#define EXTI_EMR_MR5 0x00000020U /!< Event Mask on line 5 /
Kojto	122:f9eeca106725	4886	#define EXTI_EMR_MR6 0x00000040U /!< Event Mask on line 6 /
Kojto	122:f9eeca106725	4887	#define EXTI_EMR_MR7 0x00000080U /!< Event Mask on line 7 /
Kojto	122:f9eeca106725	4888	#define EXTI_EMR_MR8 0x00000100U /!< Event Mask on line 8 /
Kojto	122:f9eeca106725	4889	#define EXTI_EMR_MR9 0x00000200U /!< Event Mask on line 9 /
Kojto	122:f9eeca106725	4890	#define EXTI_EMR_MR10 0x00000400U /!< Event Mask on line 10 /
Kojto	122:f9eeca106725	4891	#define EXTI_EMR_MR11 0x00000800U /!< Event Mask on line 11 /
Kojto	122:f9eeca106725	4892	#define EXTI_EMR_MR12 0x00001000U /!< Event Mask on line 12 /
Kojto	122:f9eeca106725	4893	#define EXTI_EMR_MR13 0x00002000U /!< Event Mask on line 13 /
Kojto	122:f9eeca106725	4894	#define EXTI_EMR_MR14 0x00004000U /!< Event Mask on line 14 /
Kojto	122:f9eeca106725	4895	#define EXTI_EMR_MR15 0x00008000U /!< Event Mask on line 15 /
Kojto	122:f9eeca106725	4896	#define EXTI_EMR_MR16 0x00010000U /!< Event Mask on line 16 /
Kojto	122:f9eeca106725	4897	#define EXTI_EMR_MR17 0x00020000U /!< Event Mask on line 17 /
Kojto	122:f9eeca106725	4898	#define EXTI_EMR_MR18 0x00040000U /!< Event Mask on line 18 /
Kojto	122:f9eeca106725	4899	#define EXTI_EMR_MR19 0x00080000U /!< Event Mask on line 19 /
Kojto	122:f9eeca106725	4900	#define EXTI_EMR_MR20 0x00100000U /!< Event Mask on line 20 /
Kojto	122:f9eeca106725	4901	#define EXTI_EMR_MR21 0x00200000U /!< Event Mask on line 21 /
Kojto	122:f9eeca106725	4902	#define EXTI_EMR_MR22 0x00400000U /!< Event Mask on line 22 /
Kojto	110:165afa46840b	4903
Kojto	110:165afa46840b	4904	/**************** Bit definition for EXTI_RTSR register *****************/
Kojto	122:f9eeca106725	4905	#define EXTI_RTSR_TR0 0x00000001U /!< Rising trigger event configuration bit of line 0 /
Kojto	122:f9eeca106725	4906	#define EXTI_RTSR_TR1 0x00000002U /!< Rising trigger event configuration bit of line 1 /
Kojto	122:f9eeca106725	4907	#define EXTI_RTSR_TR2 0x00000004U /!< Rising trigger event configuration bit of line 2 /
Kojto	122:f9eeca106725	4908	#define EXTI_RTSR_TR3 0x00000008U /!< Rising trigger event configuration bit of line 3 /
Kojto	122:f9eeca106725	4909	#define EXTI_RTSR_TR4 0x00000010U /!< Rising trigger event configuration bit of line 4 /
Kojto	122:f9eeca106725	4910	#define EXTI_RTSR_TR5 0x00000020U /!< Rising trigger event configuration bit of line 5 /
Kojto	122:f9eeca106725	4911	#define EXTI_RTSR_TR6 0x00000040U /!< Rising trigger event configuration bit of line 6 /
Kojto	122:f9eeca106725	4912	#define EXTI_RTSR_TR7 0x00000080U /!< Rising trigger event configuration bit of line 7 /
Kojto	122:f9eeca106725	4913	#define EXTI_RTSR_TR8 0x00000100U /!< Rising trigger event configuration bit of line 8 /
Kojto	122:f9eeca106725	4914	#define EXTI_RTSR_TR9 0x00000200U /!< Rising trigger event configuration bit of line 9 /
Kojto	122:f9eeca106725	4915	#define EXTI_RTSR_TR10 0x00000400U /!< Rising trigger event configuration bit of line 10 /
Kojto	122:f9eeca106725	4916	#define EXTI_RTSR_TR11 0x00000800U /!< Rising trigger event configuration bit of line 11 /
Kojto	122:f9eeca106725	4917	#define EXTI_RTSR_TR12 0x00001000U /!< Rising trigger event configuration bit of line 12 /
Kojto	122:f9eeca106725	4918	#define EXTI_RTSR_TR13 0x00002000U /!< Rising trigger event configuration bit of line 13 /
Kojto	122:f9eeca106725	4919	#define EXTI_RTSR_TR14 0x00004000U /!< Rising trigger event configuration bit of line 14 /
Kojto	122:f9eeca106725	4920	#define EXTI_RTSR_TR15 0x00008000U /!< Rising trigger event configuration bit of line 15 /
Kojto	122:f9eeca106725	4921	#define EXTI_RTSR_TR16 0x00010000U /!< Rising trigger event configuration bit of line 16 /
Kojto	122:f9eeca106725	4922	#define EXTI_RTSR_TR17 0x00020000U /!< Rising trigger event configuration bit of line 17 /
Kojto	122:f9eeca106725	4923	#define EXTI_RTSR_TR18 0x00040000U /!< Rising trigger event configuration bit of line 18 /
Kojto	122:f9eeca106725	4924	#define EXTI_RTSR_TR19 0x00080000U /!< Rising trigger event configuration bit of line 19 /
Kojto	122:f9eeca106725	4925	#define EXTI_RTSR_TR20 0x00100000U /!< Rising trigger event configuration bit of line 20 /
Kojto	122:f9eeca106725	4926	#define EXTI_RTSR_TR21 0x00200000U /!< Rising trigger event configuration bit of line 21 /
Kojto	122:f9eeca106725	4927	#define EXTI_RTSR_TR22 0x00400000U /!< Rising trigger event configuration bit of line 22 /
Kojto	110:165afa46840b	4928
Kojto	110:165afa46840b	4929	/**************** Bit definition for EXTI_FTSR register *****************/
Kojto	122:f9eeca106725	4930	#define EXTI_FTSR_TR0 0x00000001U /!< Falling trigger event configuration bit of line 0 /
Kojto	122:f9eeca106725	4931	#define EXTI_FTSR_TR1 0x00000002U /!< Falling trigger event configuration bit of line 1 /
Kojto	122:f9eeca106725	4932	#define EXTI_FTSR_TR2 0x00000004U /!< Falling trigger event configuration bit of line 2 /
Kojto	122:f9eeca106725	4933	#define EXTI_FTSR_TR3 0x00000008U /!< Falling trigger event configuration bit of line 3 /
Kojto	122:f9eeca106725	4934	#define EXTI_FTSR_TR4 0x00000010U /!< Falling trigger event configuration bit of line 4 /
Kojto	122:f9eeca106725	4935	#define EXTI_FTSR_TR5 0x00000020U /!< Falling trigger event configuration bit of line 5 /
Kojto	122:f9eeca106725	4936	#define EXTI_FTSR_TR6 0x00000040U /!< Falling trigger event configuration bit of line 6 /
Kojto	122:f9eeca106725	4937	#define EXTI_FTSR_TR7 0x00000080U /!< Falling trigger event configuration bit of line 7 /
Kojto	122:f9eeca106725	4938	#define EXTI_FTSR_TR8 0x00000100U /!< Falling trigger event configuration bit of line 8 /
Kojto	122:f9eeca106725	4939	#define EXTI_FTSR_TR9 0x00000200U /!< Falling trigger event configuration bit of line 9 /
Kojto	122:f9eeca106725	4940	#define EXTI_FTSR_TR10 0x00000400U /!< Falling trigger event configuration bit of line 10 /
Kojto	122:f9eeca106725	4941	#define EXTI_FTSR_TR11 0x00000800U /!< Falling trigger event configuration bit of line 11 /
Kojto	122:f9eeca106725	4942	#define EXTI_FTSR_TR12 0x00001000U /!< Falling trigger event configuration bit of line 12 /
Kojto	122:f9eeca106725	4943	#define EXTI_FTSR_TR13 0x00002000U /!< Falling trigger event configuration bit of line 13 /
Kojto	122:f9eeca106725	4944	#define EXTI_FTSR_TR14 0x00004000U /!< Falling trigger event configuration bit of line 14 /
Kojto	122:f9eeca106725	4945	#define EXTI_FTSR_TR15 0x00008000U /!< Falling trigger event configuration bit of line 15 /
Kojto	122:f9eeca106725	4946	#define EXTI_FTSR_TR16 0x00010000U /!< Falling trigger event configuration bit of line 16 /
Kojto	122:f9eeca106725	4947	#define EXTI_FTSR_TR17 0x00020000U /!< Falling trigger event configuration bit of line 17 /
Kojto	122:f9eeca106725	4948	#define EXTI_FTSR_TR18 0x00040000U /!< Falling trigger event configuration bit of line 18 /
Kojto	122:f9eeca106725	4949	#define EXTI_FTSR_TR19 0x00080000U /!< Falling trigger event configuration bit of line 19 /
Kojto	122:f9eeca106725	4950	#define EXTI_FTSR_TR20 0x00100000U /!< Falling trigger event configuration bit of line 20 /
Kojto	122:f9eeca106725	4951	#define EXTI_FTSR_TR21 0x00200000U /!< Falling trigger event configuration bit of line 21 /
Kojto	122:f9eeca106725	4952	#define EXTI_FTSR_TR22 0x00400000U /!< Falling trigger event configuration bit of line 22 /
Kojto	110:165afa46840b	4953
Kojto	110:165afa46840b	4954	/**************** Bit definition for EXTI_SWIER register ****************/
Kojto	122:f9eeca106725	4955	#define EXTI_SWIER_SWIER0 0x00000001U /!< Software Interrupt on line 0 /
Kojto	122:f9eeca106725	4956	#define EXTI_SWIER_SWIER1 0x00000002U /!< Software Interrupt on line 1 /
Kojto	122:f9eeca106725	4957	#define EXTI_SWIER_SWIER2 0x00000004U /!< Software Interrupt on line 2 /
Kojto	122:f9eeca106725	4958	#define EXTI_SWIER_SWIER3 0x00000008U /!< Software Interrupt on line 3 /
Kojto	122:f9eeca106725	4959	#define EXTI_SWIER_SWIER4 0x00000010U /!< Software Interrupt on line 4 /
Kojto	122:f9eeca106725	4960	#define EXTI_SWIER_SWIER5 0x00000020U /!< Software Interrupt on line 5 /
Kojto	122:f9eeca106725	4961	#define EXTI_SWIER_SWIER6 0x00000040U /!< Software Interrupt on line 6 /
Kojto	122:f9eeca106725	4962	#define EXTI_SWIER_SWIER7 0x00000080U /!< Software Interrupt on line 7 /
Kojto	122:f9eeca106725	4963	#define EXTI_SWIER_SWIER8 0x00000100U /!< Software Interrupt on line 8 /
Kojto	122:f9eeca106725	4964	#define EXTI_SWIER_SWIER9 0x00000200U /!< Software Interrupt on line 9 /
Kojto	122:f9eeca106725	4965	#define EXTI_SWIER_SWIER10 0x00000400U /!< Software Interrupt on line 10 /
Kojto	122:f9eeca106725	4966	#define EXTI_SWIER_SWIER11 0x00000800U /!< Software Interrupt on line 11 /
Kojto	122:f9eeca106725	4967	#define EXTI_SWIER_SWIER12 0x00001000U /!< Software Interrupt on line 12 /
Kojto	122:f9eeca106725	4968	#define EXTI_SWIER_SWIER13 0x00002000U /!< Software Interrupt on line 13 /
Kojto	122:f9eeca106725	4969	#define EXTI_SWIER_SWIER14 0x00004000U /!< Software Interrupt on line 14 /
Kojto	122:f9eeca106725	4970	#define EXTI_SWIER_SWIER15 0x00008000U /!< Software Interrupt on line 15 /
Kojto	122:f9eeca106725	4971	#define EXTI_SWIER_SWIER16 0x00010000U /!< Software Interrupt on line 16 /
Kojto	122:f9eeca106725	4972	#define EXTI_SWIER_SWIER17 0x00020000U /!< Software Interrupt on line 17 /
Kojto	122:f9eeca106725	4973	#define EXTI_SWIER_SWIER18 0x00040000U /!< Software Interrupt on line 18 /
Kojto	122:f9eeca106725	4974	#define EXTI_SWIER_SWIER19 0x00080000U /!< Software Interrupt on line 19 /
Kojto	122:f9eeca106725	4975	#define EXTI_SWIER_SWIER20 0x00100000U /!< Software Interrupt on line 20 /
Kojto	122:f9eeca106725	4976	#define EXTI_SWIER_SWIER21 0x00200000U /!< Software Interrupt on line 21 /
Kojto	122:f9eeca106725	4977	#define EXTI_SWIER_SWIER22 0x00400000U /!< Software Interrupt on line 22 /
Kojto	110:165afa46840b	4978
Kojto	110:165afa46840b	4979	/***************** Bit definition for EXTI_PR register ******************/
Kojto	122:f9eeca106725	4980	#define EXTI_PR_PR0 0x00000001U /!< Pending bit for line 0 /
Kojto	122:f9eeca106725	4981	#define EXTI_PR_PR1 0x00000002U /!< Pending bit for line 1 /
Kojto	122:f9eeca106725	4982	#define EXTI_PR_PR2 0x00000004U /!< Pending bit for line 2 /
Kojto	122:f9eeca106725	4983	#define EXTI_PR_PR3 0x00000008U /!< Pending bit for line 3 /
Kojto	122:f9eeca106725	4984	#define EXTI_PR_PR4 0x00000010U /!< Pending bit for line 4 /
Kojto	122:f9eeca106725	4985	#define EXTI_PR_PR5 0x00000020U /!< Pending bit for line 5 /
Kojto	122:f9eeca106725	4986	#define EXTI_PR_PR6 0x00000040U /!< Pending bit for line 6 /
Kojto	122:f9eeca106725	4987	#define EXTI_PR_PR7 0x00000080U /!< Pending bit for line 7 /
Kojto	122:f9eeca106725	4988	#define EXTI_PR_PR8 0x00000100U /!< Pending bit for line 8 /
Kojto	122:f9eeca106725	4989	#define EXTI_PR_PR9 0x00000200U /!< Pending bit for line 9 /
Kojto	122:f9eeca106725	4990	#define EXTI_PR_PR10 0x00000400U /!< Pending bit for line 10 /
Kojto	122:f9eeca106725	4991	#define EXTI_PR_PR11 0x00000800U /!< Pending bit for line 11 /
Kojto	122:f9eeca106725	4992	#define EXTI_PR_PR12 0x00001000U /!< Pending bit for line 12 /
Kojto	122:f9eeca106725	4993	#define EXTI_PR_PR13 0x00002000U /!< Pending bit for line 13 /
Kojto	122:f9eeca106725	4994	#define EXTI_PR_PR14 0x00004000U /!< Pending bit for line 14 /
Kojto	122:f9eeca106725	4995	#define EXTI_PR_PR15 0x00008000U /!< Pending bit for line 15 /
Kojto	122:f9eeca106725	4996	#define EXTI_PR_PR16 0x00010000U /!< Pending bit for line 16 /
Kojto	122:f9eeca106725	4997	#define EXTI_PR_PR17 0x00020000U /!< Pending bit for line 17 /
Kojto	122:f9eeca106725	4998	#define EXTI_PR_PR18 0x00040000U /!< Pending bit for line 18 /
Kojto	122:f9eeca106725	4999	#define EXTI_PR_PR19 0x00080000U /!< Pending bit for line 19 /
Kojto	122:f9eeca106725	5000	#define EXTI_PR_PR20 0x00100000U /!< Pending bit for line 20 /
Kojto	122:f9eeca106725	5001	#define EXTI_PR_PR21 0x00200000U /!< Pending bit for line 21 /
Kojto	122:f9eeca106725	5002	#define EXTI_PR_PR22 0x00400000U /!< Pending bit for line 22 /
Kojto	110:165afa46840b	5003
Kojto	110:165afa46840b	5004	/******************************************************************************/
Kojto	110:165afa46840b	5005	/* */
Kojto	110:165afa46840b	5006	/* FLASH */
Kojto	110:165afa46840b	5007	/* */
Kojto	110:165afa46840b	5008	/******************************************************************************/
Kojto	110:165afa46840b	5009	/***************** Bits definition for FLASH_ACR register ***************/
Kojto	122:f9eeca106725	5010	#define FLASH_ACR_LATENCY 0x0000000FU
Kojto	122:f9eeca106725	5011	#define FLASH_ACR_LATENCY_0WS 0x00000000U
Kojto	122:f9eeca106725	5012	#define FLASH_ACR_LATENCY_1WS 0x00000001U
Kojto	122:f9eeca106725	5013	#define FLASH_ACR_LATENCY_2WS 0x00000002U
Kojto	122:f9eeca106725	5014	#define FLASH_ACR_LATENCY_3WS 0x00000003U
Kojto	122:f9eeca106725	5015	#define FLASH_ACR_LATENCY_4WS 0x00000004U
Kojto	122:f9eeca106725	5016	#define FLASH_ACR_LATENCY_5WS 0x00000005U
Kojto	122:f9eeca106725	5017	#define FLASH_ACR_LATENCY_6WS 0x00000006U
Kojto	122:f9eeca106725	5018	#define FLASH_ACR_LATENCY_7WS 0x00000007U
Kojto	122:f9eeca106725	5019	#define FLASH_ACR_LATENCY_8WS 0x00000008U
Kojto	122:f9eeca106725	5020	#define FLASH_ACR_LATENCY_9WS 0x00000009U
Kojto	122:f9eeca106725	5021	#define FLASH_ACR_LATENCY_10WS 0x0000000AU
Kojto	122:f9eeca106725	5022	#define FLASH_ACR_LATENCY_11WS 0x0000000BU
Kojto	122:f9eeca106725	5023	#define FLASH_ACR_LATENCY_12WS 0x0000000CU
Kojto	122:f9eeca106725	5024	#define FLASH_ACR_LATENCY_13WS 0x0000000DU
Kojto	122:f9eeca106725	5025	#define FLASH_ACR_LATENCY_14WS 0x0000000EU
Kojto	122:f9eeca106725	5026	#define FLASH_ACR_LATENCY_15WS 0x0000000FU
Kojto	122:f9eeca106725	5027	#define FLASH_ACR_PRFTEN 0x00000100U
Kojto	122:f9eeca106725	5028	#define FLASH_ACR_ICEN 0x00000200U
Kojto	122:f9eeca106725	5029	#define FLASH_ACR_DCEN 0x00000400U
Kojto	122:f9eeca106725	5030	#define FLASH_ACR_ICRST 0x00000800U
Kojto	122:f9eeca106725	5031	#define FLASH_ACR_DCRST 0x00001000U
Kojto	122:f9eeca106725	5032	#define FLASH_ACR_BYTE0_ADDRESS 0x40023C00U
Kojto	122:f9eeca106725	5033	#define FLASH_ACR_BYTE2_ADDRESS 0x40023C03U
Kojto	110:165afa46840b	5034
Kojto	110:165afa46840b	5035	/***************** Bits definition for FLASH_SR register ****************/
Kojto	122:f9eeca106725	5036	#define FLASH_SR_EOP 0x00000001U
Kojto	122:f9eeca106725	5037	#define FLASH_SR_SOP 0x00000002U
Kojto	122:f9eeca106725	5038	#define FLASH_SR_WRPERR 0x00000010U
Kojto	122:f9eeca106725	5039	#define FLASH_SR_PGAERR 0x00000020U
Kojto	122:f9eeca106725	5040	#define FLASH_SR_PGPERR 0x00000040U
Kojto	122:f9eeca106725	5041	#define FLASH_SR_PGSERR 0x00000080U
Kojto	122:f9eeca106725	5042	#define FLASH_SR_BSY 0x00010000U
Kojto	110:165afa46840b	5043
Kojto	110:165afa46840b	5044	/***************** Bits definition for FLASH_CR register ****************/
Kojto	122:f9eeca106725	5045	#define FLASH_CR_PG 0x00000001U
Kojto	122:f9eeca106725	5046	#define FLASH_CR_SER 0x00000002U
Kojto	122:f9eeca106725	5047	#define FLASH_CR_MER 0x00000004U
Kojto	110:165afa46840b	5048	#define FLASH_CR_MER1 FLASH_CR_MER
Kojto	122:f9eeca106725	5049	#define FLASH_CR_SNB 0x000000F8U
Kojto	122:f9eeca106725	5050	#define FLASH_CR_SNB_0 0x00000008U
Kojto	122:f9eeca106725	5051	#define FLASH_CR_SNB_1 0x00000010U
Kojto	122:f9eeca106725	5052	#define FLASH_CR_SNB_2 0x00000020U
Kojto	122:f9eeca106725	5053	#define FLASH_CR_SNB_3 0x00000040U
Kojto	122:f9eeca106725	5054	#define FLASH_CR_SNB_4 0x00000080U
Kojto	122:f9eeca106725	5055	#define FLASH_CR_PSIZE 0x00000300U
Kojto	122:f9eeca106725	5056	#define FLASH_CR_PSIZE_0 0x00000100U
Kojto	122:f9eeca106725	5057	#define FLASH_CR_PSIZE_1 0x00000200U
Kojto	122:f9eeca106725	5058	#define FLASH_CR_MER2 0x00008000U
Kojto	122:f9eeca106725	5059	#define FLASH_CR_STRT 0x00010000U
Kojto	122:f9eeca106725	5060	#define FLASH_CR_EOPIE 0x01000000U
Kojto	122:f9eeca106725	5061	#define FLASH_CR_LOCK 0x80000000U
Kojto	110:165afa46840b	5062
Kojto	110:165afa46840b	5063	/***************** Bits definition for FLASH_OPTCR register *************/
Kojto	122:f9eeca106725	5064	#define FLASH_OPTCR_OPTLOCK 0x00000001U
Kojto	122:f9eeca106725	5065	#define FLASH_OPTCR_OPTSTRT 0x00000002U
Kojto	122:f9eeca106725	5066	#define FLASH_OPTCR_BOR_LEV_0 0x00000004U
Kojto	122:f9eeca106725	5067	#define FLASH_OPTCR_BOR_LEV_1 0x00000008U
Kojto	122:f9eeca106725	5068	#define FLASH_OPTCR_BOR_LEV 0x0000000CU
Kojto	122:f9eeca106725	5069	#define FLASH_OPTCR_BFB2 0x00000010U
Kojto	122:f9eeca106725	5070	#define FLASH_OPTCR_WDG_SW 0x00000020U
Kojto	122:f9eeca106725	5071	#define FLASH_OPTCR_nRST_STOP 0x00000040U
Kojto	122:f9eeca106725	5072	#define FLASH_OPTCR_nRST_STDBY 0x00000080U
Kojto	122:f9eeca106725	5073	#define FLASH_OPTCR_RDP 0x0000FF00U
Kojto	122:f9eeca106725	5074	#define FLASH_OPTCR_RDP_0 0x00000100U
Kojto	122:f9eeca106725	5075	#define FLASH_OPTCR_RDP_1 0x00000200U
Kojto	122:f9eeca106725	5076	#define FLASH_OPTCR_RDP_2 0x00000400U
Kojto	122:f9eeca106725	5077	#define FLASH_OPTCR_RDP_3 0x00000800U
Kojto	122:f9eeca106725	5078	#define FLASH_OPTCR_RDP_4 0x00001000U
Kojto	122:f9eeca106725	5079	#define FLASH_OPTCR_RDP_5 0x00002000U
Kojto	122:f9eeca106725	5080	#define FLASH_OPTCR_RDP_6 0x00004000U
Kojto	122:f9eeca106725	5081	#define FLASH_OPTCR_RDP_7 0x00008000U
Kojto	122:f9eeca106725	5082	#define FLASH_OPTCR_nWRP 0x0FFF0000U
Kojto	122:f9eeca106725	5083	#define FLASH_OPTCR_nWRP_0 0x00010000U
Kojto	122:f9eeca106725	5084	#define FLASH_OPTCR_nWRP_1 0x00020000U
Kojto	122:f9eeca106725	5085	#define FLASH_OPTCR_nWRP_2 0x00040000U
Kojto	122:f9eeca106725	5086	#define FLASH_OPTCR_nWRP_3 0x00080000U
Kojto	122:f9eeca106725	5087	#define FLASH_OPTCR_nWRP_4 0x00100000U
Kojto	122:f9eeca106725	5088	#define FLASH_OPTCR_nWRP_5 0x00200000U
Kojto	122:f9eeca106725	5089	#define FLASH_OPTCR_nWRP_6 0x00400000U
Kojto	122:f9eeca106725	5090	#define FLASH_OPTCR_nWRP_7 0x00800000U
Kojto	122:f9eeca106725	5091	#define FLASH_OPTCR_nWRP_8 0x01000000U
Kojto	122:f9eeca106725	5092	#define FLASH_OPTCR_nWRP_9 0x02000000U
Kojto	122:f9eeca106725	5093	#define FLASH_OPTCR_nWRP_10 0x04000000U
Kojto	122:f9eeca106725	5094	#define FLASH_OPTCR_nWRP_11 0x08000000U
Kojto	122:f9eeca106725	5095	#define FLASH_OPTCR_DB1M 0x40000000U
Kojto	122:f9eeca106725	5096	#define FLASH_OPTCR_SPRMOD 0x80000000U
Kojto	110:165afa46840b	5097
Kojto	110:165afa46840b	5098	/**************** Bits definition for FLASH_OPTCR1 register *************/
Kojto	122:f9eeca106725	5099	#define FLASH_OPTCR1_nWRP 0x0FFF0000U
Kojto	122:f9eeca106725	5100	#define FLASH_OPTCR1_nWRP_0 0x00010000U
Kojto	122:f9eeca106725	5101	#define FLASH_OPTCR1_nWRP_1 0x00020000U
Kojto	122:f9eeca106725	5102	#define FLASH_OPTCR1_nWRP_2 0x00040000U
Kojto	122:f9eeca106725	5103	#define FLASH_OPTCR1_nWRP_3 0x00080000U
Kojto	122:f9eeca106725	5104	#define FLASH_OPTCR1_nWRP_4 0x00100000U
Kojto	122:f9eeca106725	5105	#define FLASH_OPTCR1_nWRP_5 0x00200000U
Kojto	122:f9eeca106725	5106	#define FLASH_OPTCR1_nWRP_6 0x00400000U
Kojto	122:f9eeca106725	5107	#define FLASH_OPTCR1_nWRP_7 0x00800000U
Kojto	122:f9eeca106725	5108	#define FLASH_OPTCR1_nWRP_8 0x01000000U
Kojto	122:f9eeca106725	5109	#define FLASH_OPTCR1_nWRP_9 0x02000000U
Kojto	122:f9eeca106725	5110	#define FLASH_OPTCR1_nWRP_10 0x04000000U
Kojto	122:f9eeca106725	5111	#define FLASH_OPTCR1_nWRP_11 0x08000000U
Kojto	110:165afa46840b	5112
Kojto	110:165afa46840b	5113	/******************************************************************************/
Kojto	110:165afa46840b	5114	/* */
Kojto	110:165afa46840b	5115	/* Flexible Memory Controller */
Kojto	110:165afa46840b	5116	/* */
Kojto	110:165afa46840b	5117	/******************************************************************************/
Kojto	110:165afa46840b	5118	/**************** Bit definition for FMC_BCR1 register *****************/
Kojto	122:f9eeca106725	5119	#define FMC_BCR1_MBKEN 0x00000001U /!<Memory bank enable bit /
Kojto	122:f9eeca106725	5120	#define FMC_BCR1_MUXEN 0x00000002U /!<Address/data multiplexing enable bit /
Kojto	122:f9eeca106725	5121
Kojto	122:f9eeca106725	5122	#define FMC_BCR1_MTYP 0x0000000CU /!<MTYP[1:0] bits (Memory type) /
Kojto	122:f9eeca106725	5123	#define FMC_BCR1_MTYP_0 0x00000004U /!<Bit 0 /
Kojto	122:f9eeca106725	5124	#define FMC_BCR1_MTYP_1 0x00000008U /!<Bit 1 /
Kojto	122:f9eeca106725	5125
Kojto	122:f9eeca106725	5126	#define FMC_BCR1_MWID 0x00000030U /!<MWID[1:0] bits (Memory data bus width) /
Kojto	122:f9eeca106725	5127	#define FMC_BCR1_MWID_0 0x00000010U /!<Bit 0 /
Kojto	122:f9eeca106725	5128	#define FMC_BCR1_MWID_1 0x00000020U /!<Bit 1 /
Kojto	122:f9eeca106725	5129
Kojto	122:f9eeca106725	5130	#define FMC_BCR1_FACCEN 0x00000040U /!<Flash access enable /
Kojto	122:f9eeca106725	5131	#define FMC_BCR1_BURSTEN 0x00000100U /!<Burst enable bit /
Kojto	122:f9eeca106725	5132	#define FMC_BCR1_WAITPOL 0x00000200U /!<Wait signal polarity bit /
Kojto	122:f9eeca106725	5133	#define FMC_BCR1_WAITCFG 0x00000800U /!<Wait timing configuration /
Kojto	122:f9eeca106725	5134	#define FMC_BCR1_WREN 0x00001000U /!<Write enable bit /
Kojto	122:f9eeca106725	5135	#define FMC_BCR1_WAITEN 0x00002000U /!<Wait enable bit /
Kojto	122:f9eeca106725	5136	#define FMC_BCR1_EXTMOD 0x00004000U /!<Extended mode enable /
Kojto	122:f9eeca106725	5137	#define FMC_BCR1_ASYNCWAIT 0x00008000U /!<Asynchronous wait /
Kojto	122:f9eeca106725	5138	#define FMC_BCR1_CPSIZE 0x00070000U /!<CRAM page size /
Kojto	122:f9eeca106725	5139	#define FMC_BCR1_CPSIZE_0 0x00010000U /!<Bit 0 /
Kojto	122:f9eeca106725	5140	#define FMC_BCR1_CPSIZE_1 0x00020000U /!<Bit 1 /
Kojto	122:f9eeca106725	5141	#define FMC_BCR1_CPSIZE_2 0x00040000U /!<Bit 2 /
Kojto	122:f9eeca106725	5142	#define FMC_BCR1_CBURSTRW 0x00080000U /!<Write burst enable /
Kojto	122:f9eeca106725	5143	#define FMC_BCR1_CCLKEN 0x00100000U /!<Continous clock enable /
Kojto	122:f9eeca106725	5144	#define FMC_BCR1_WFDIS 0x00200000U /!<Write FIFO Disable /
Kojto	110:165afa46840b	5145
Kojto	110:165afa46840b	5146	/**************** Bit definition for FMC_BCR2 register *****************/
Kojto	122:f9eeca106725	5147	#define FMC_BCR2_MBKEN 0x00000001U /!<Memory bank enable bit /
Kojto	122:f9eeca106725	5148	#define FMC_BCR2_MUXEN 0x00000002U /!<Address/data multiplexing enable bit /
Kojto	122:f9eeca106725	5149
Kojto	122:f9eeca106725	5150	#define FMC_BCR2_MTYP 0x0000000CU /!<MTYP[1:0] bits (Memory type) /
Kojto	122:f9eeca106725	5151	#define FMC_BCR2_MTYP_0 0x00000004U /!<Bit 0 /
Kojto	122:f9eeca106725	5152	#define FMC_BCR2_MTYP_1 0x00000008U /!<Bit 1 /
Kojto	122:f9eeca106725	5153
Kojto	122:f9eeca106725	5154	#define FMC_BCR2_MWID 0x00000030U /!<MWID[1:0] bits (Memory data bus width) /
Kojto	122:f9eeca106725	5155	#define FMC_BCR2_MWID_0 0x00000010U /!<Bit 0 /
Kojto	122:f9eeca106725	5156	#define FMC_BCR2_MWID_1 0x00000020U /!<Bit 1 /
Kojto	122:f9eeca106725	5157
Kojto	122:f9eeca106725	5158	#define FMC_BCR2_FACCEN 0x00000040U /!<Flash access enable /
Kojto	122:f9eeca106725	5159	#define FMC_BCR2_BURSTEN 0x00000100U /!<Burst enable bit /
Kojto	122:f9eeca106725	5160	#define FMC_BCR2_WAITPOL 0x00000200U /!<Wait signal polarity bit /
Kojto	122:f9eeca106725	5161	#define FMC_BCR2_WAITCFG 0x00000800U /!<Wait timing configuration /
Kojto	122:f9eeca106725	5162	#define FMC_BCR2_WREN 0x00001000U /!<Write enable bit /
Kojto	122:f9eeca106725	5163	#define FMC_BCR2_WAITEN 0x00002000U /!<Wait enable bit /
Kojto	122:f9eeca106725	5164	#define FMC_BCR2_EXTMOD 0x00004000U /!<Extended mode enable /
Kojto	122:f9eeca106725	5165	#define FMC_BCR2_ASYNCWAIT 0x00008000U /!<Asynchronous wait /
Kojto	122:f9eeca106725	5166	#define FMC_BCR2_CBURSTRW 0x00080000U /!<Write burst enable /
Kojto	110:165afa46840b	5167
Kojto	110:165afa46840b	5168	/**************** Bit definition for FMC_BCR3 register *****************/
Kojto	122:f9eeca106725	5169	#define FMC_BCR3_MBKEN 0x00000001U /!<Memory bank enable bit /
Kojto	122:f9eeca106725	5170	#define FMC_BCR3_MUXEN 0x00000002U /!<Address/data multiplexing enable bit /
Kojto	122:f9eeca106725	5171
Kojto	122:f9eeca106725	5172	#define FMC_BCR3_MTYP 0x0000000CU /!<MTYP[1:0] bits (Memory type) /
Kojto	122:f9eeca106725	5173	#define FMC_BCR3_MTYP_0 0x00000004U /!<Bit 0 /
Kojto	122:f9eeca106725	5174	#define FMC_BCR3_MTYP_1 0x00000008U /!<Bit 1 /
Kojto	122:f9eeca106725	5175
Kojto	122:f9eeca106725	5176	#define FMC_BCR3_MWID 0x00000030U /!<MWID[1:0] bits (Memory data bus width) /
Kojto	122:f9eeca106725	5177	#define FMC_BCR3_MWID_0 0x00000010U /!<Bit 0 /
Kojto	122:f9eeca106725	5178	#define FMC_BCR3_MWID_1 0x00000020U /!<Bit 1 /
Kojto	122:f9eeca106725	5179
Kojto	122:f9eeca106725	5180	#define FMC_BCR3_FACCEN 0x00000040U /!<Flash access enable /
Kojto	122:f9eeca106725	5181	#define FMC_BCR3_BURSTEN 0x00000100U /!<Burst enable bit /
Kojto	122:f9eeca106725	5182	#define FMC_BCR3_WAITPOL 0x00000200U /!<Wait signal polarity bit /
Kojto	122:f9eeca106725	5183	#define FMC_BCR3_WAITCFG 0x00000800U /!<Wait timing configuration /
Kojto	122:f9eeca106725	5184	#define FMC_BCR3_WREN 0x00001000U /!<Write enable bit /
Kojto	122:f9eeca106725	5185	#define FMC_BCR3_WAITEN 0x00002000U /!<Wait enable bit /
Kojto	122:f9eeca106725	5186	#define FMC_BCR3_EXTMOD 0x00004000U /!<Extended mode enable /
Kojto	122:f9eeca106725	5187	#define FMC_BCR3_ASYNCWAIT 0x00008000U /!<Asynchronous wait /
Kojto	122:f9eeca106725	5188	#define FMC_BCR3_CBURSTRW 0x00080000U /!<Write burst enable /
Kojto	110:165afa46840b	5189
Kojto	110:165afa46840b	5190	/**************** Bit definition for FMC_BCR4 register *****************/
Kojto	122:f9eeca106725	5191	#define FMC_BCR4_MBKEN 0x00000001U /!<Memory bank enable bit /
Kojto	122:f9eeca106725	5192	#define FMC_BCR4_MUXEN 0x00000002U /!<Address/data multiplexing enable bit /
Kojto	122:f9eeca106725	5193
Kojto	122:f9eeca106725	5194	#define FMC_BCR4_MTYP 0x0000000CU /!<MTYP[1:0] bits (Memory type) /
Kojto	122:f9eeca106725	5195	#define FMC_BCR4_MTYP_0 0x00000004U /!<Bit 0 /
Kojto	122:f9eeca106725	5196	#define FMC_BCR4_MTYP_1 0x00000008U /!<Bit 1 /
Kojto	122:f9eeca106725	5197
Kojto	122:f9eeca106725	5198	#define FMC_BCR4_MWID 0x00000030U /!<MWID[1:0] bits (Memory data bus width) /
Kojto	122:f9eeca106725	5199	#define FMC_BCR4_MWID_0 0x00000010U /!<Bit 0 /
Kojto	122:f9eeca106725	5200	#define FMC_BCR4_MWID_1 0x00000020U /!<Bit 1 /
Kojto	122:f9eeca106725	5201
Kojto	122:f9eeca106725	5202	#define FMC_BCR4_FACCEN 0x00000040U /!<Flash access enable /
Kojto	122:f9eeca106725	5203	#define FMC_BCR4_BURSTEN 0x00000100U /!<Burst enable bit /
Kojto	122:f9eeca106725	5204	#define FMC_BCR4_WAITPOL 0x00000200U /!<Wait signal polarity bit /
Kojto	122:f9eeca106725	5205	#define FMC_BCR4_WAITCFG 0x00000800U /!<Wait timing configuration /
Kojto	122:f9eeca106725	5206	#define FMC_BCR4_WREN 0x00001000U /!<Write enable bit /
Kojto	122:f9eeca106725	5207	#define FMC_BCR4_WAITEN 0x00002000U /!<Wait enable bit /
Kojto	122:f9eeca106725	5208	#define FMC_BCR4_EXTMOD 0x00004000U /!<Extended mode enable /
Kojto	122:f9eeca106725	5209	#define FMC_BCR4_ASYNCWAIT 0x00008000U /!<Asynchronous wait /
Kojto	122:f9eeca106725	5210	#define FMC_BCR4_CBURSTRW 0x00080000U /!<Write burst enable /
Kojto	110:165afa46840b	5211
Kojto	110:165afa46840b	5212	/**************** Bit definition for FMC_BTR1 register ****************/
Kojto	122:f9eeca106725	5213	#define FMC_BTR1_ADDSET 0x0000000FU /!<ADDSET[3:0] bits (Address setup phase duration) /
Kojto	122:f9eeca106725	5214	#define FMC_BTR1_ADDSET_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	5215	#define FMC_BTR1_ADDSET_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	5216	#define FMC_BTR1_ADDSET_2 0x00000004U /!<Bit 2 /
Kojto	122:f9eeca106725	5217	#define FMC_BTR1_ADDSET_3 0x00000008U /!<Bit 3 /
Kojto	122:f9eeca106725	5218
Kojto	122:f9eeca106725	5219	#define FMC_BTR1_ADDHLD 0x000000F0U /!<ADDHLD[3:0] bits (Address-hold phase duration) /
Kojto	122:f9eeca106725	5220	#define FMC_BTR1_ADDHLD_0 0x00000010U /!<Bit 0 /
Kojto	122:f9eeca106725	5221	#define FMC_BTR1_ADDHLD_1 0x00000020U /!<Bit 1 /
Kojto	122:f9eeca106725	5222	#define FMC_BTR1_ADDHLD_2 0x00000040U /!<Bit 2 /
Kojto	122:f9eeca106725	5223	#define FMC_BTR1_ADDHLD_3 0x00000080U /!<Bit 3 /
Kojto	122:f9eeca106725	5224
Kojto	122:f9eeca106725	5225	#define FMC_BTR1_DATAST 0x0000FF00U /!<DATAST [3:0] bits (Data-phase duration) /
Kojto	122:f9eeca106725	5226	#define FMC_BTR1_DATAST_0 0x00000100U /!<Bit 0 /
Kojto	122:f9eeca106725	5227	#define FMC_BTR1_DATAST_1 0x00000200U /!<Bit 1 /
Kojto	122:f9eeca106725	5228	#define FMC_BTR1_DATAST_2 0x00000400U /!<Bit 2 /
Kojto	122:f9eeca106725	5229	#define FMC_BTR1_DATAST_3 0x00000800U /!<Bit 3 /
Kojto	122:f9eeca106725	5230	#define FMC_BTR1_DATAST_4 0x00001000U /!<Bit 4 /
Kojto	122:f9eeca106725	5231	#define FMC_BTR1_DATAST_5 0x00002000U /!<Bit 5 /
Kojto	122:f9eeca106725	5232	#define FMC_BTR1_DATAST_6 0x00004000U /!<Bit 6 /
Kojto	122:f9eeca106725	5233	#define FMC_BTR1_DATAST_7 0x00008000U /!<Bit 7 /
Kojto	122:f9eeca106725	5234
Kojto	122:f9eeca106725	5235	#define FMC_BTR1_BUSTURN 0x000F0000U /!<BUSTURN[3:0] bits (Bus turnaround phase duration) /
Kojto	122:f9eeca106725	5236	#define FMC_BTR1_BUSTURN_0 0x00010000U /!<Bit 0 /
Kojto	122:f9eeca106725	5237	#define FMC_BTR1_BUSTURN_1 0x00020000U /!<Bit 1 /
Kojto	122:f9eeca106725	5238	#define FMC_BTR1_BUSTURN_2 0x00040000U /!<Bit 2 /
Kojto	122:f9eeca106725	5239	#define FMC_BTR1_BUSTURN_3 0x00080000U /!<Bit 3 /
Kojto	122:f9eeca106725	5240
Kojto	122:f9eeca106725	5241	#define FMC_BTR1_CLKDIV 0x00F00000U /!<CLKDIV[3:0] bits (Clock divide ratio) /
Kojto	122:f9eeca106725	5242	#define FMC_BTR1_CLKDIV_0 0x00100000U /!<Bit 0 /
Kojto	122:f9eeca106725	5243	#define FMC_BTR1_CLKDIV_1 0x00200000U /!<Bit 1 /
Kojto	122:f9eeca106725	5244	#define FMC_BTR1_CLKDIV_2 0x00400000U /!<Bit 2 /
Kojto	122:f9eeca106725	5245	#define FMC_BTR1_CLKDIV_3 0x00800000U /!<Bit 3 /
Kojto	122:f9eeca106725	5246
Kojto	122:f9eeca106725	5247	#define FMC_BTR1_DATLAT 0x0F000000U /!<DATLA[3:0] bits (Data latency) /
Kojto	122:f9eeca106725	5248	#define FMC_BTR1_DATLAT_0 0x01000000U /!<Bit 0 /
Kojto	122:f9eeca106725	5249	#define FMC_BTR1_DATLAT_1 0x02000000U /!<Bit 1 /
Kojto	122:f9eeca106725	5250	#define FMC_BTR1_DATLAT_2 0x04000000U /!<Bit 2 /
Kojto	122:f9eeca106725	5251	#define FMC_BTR1_DATLAT_3 0x08000000U /!<Bit 3 /
Kojto	122:f9eeca106725	5252
Kojto	122:f9eeca106725	5253	#define FMC_BTR1_ACCMOD 0x30000000U /!<ACCMOD[1:0] bits (Access mode) /
Kojto	122:f9eeca106725	5254	#define FMC_BTR1_ACCMOD_0 0x10000000U /!<Bit 0 /
Kojto	122:f9eeca106725	5255	#define FMC_BTR1_ACCMOD_1 0x20000000U /!<Bit 1 /
Kojto	110:165afa46840b	5256
Kojto	110:165afa46840b	5257	/**************** Bit definition for FMC_BTR2 register *****************/
Kojto	122:f9eeca106725	5258	#define FMC_BTR2_ADDSET 0x0000000FU /!<ADDSET[3:0] bits (Address setup phase duration) /
Kojto	122:f9eeca106725	5259	#define FMC_BTR2_ADDSET_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	5260	#define FMC_BTR2_ADDSET_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	5261	#define FMC_BTR2_ADDSET_2 0x00000004U /!<Bit 2 /
Kojto	122:f9eeca106725	5262	#define FMC_BTR2_ADDSET_3 0x00000008U /!<Bit 3 /
Kojto	122:f9eeca106725	5263
Kojto	122:f9eeca106725	5264	#define FMC_BTR2_ADDHLD 0x000000F0U /!<ADDHLD[3:0] bits (Address-hold phase duration) /
Kojto	122:f9eeca106725	5265	#define FMC_BTR2_ADDHLD_0 0x00000010U /!<Bit 0 /
Kojto	122:f9eeca106725	5266	#define FMC_BTR2_ADDHLD_1 0x00000020U /!<Bit 1 /
Kojto	122:f9eeca106725	5267	#define FMC_BTR2_ADDHLD_2 0x00000040U /!<Bit 2 /
Kojto	122:f9eeca106725	5268	#define FMC_BTR2_ADDHLD_3 0x00000080U /!<Bit 3 /
Kojto	122:f9eeca106725	5269
Kojto	122:f9eeca106725	5270	#define FMC_BTR2_DATAST 0x0000FF00U /!<DATAST [3:0] bits (Data-phase duration) /
Kojto	122:f9eeca106725	5271	#define FMC_BTR2_DATAST_0 0x00000100U /!<Bit 0 /
Kojto	122:f9eeca106725	5272	#define FMC_BTR2_DATAST_1 0x00000200U /!<Bit 1 /
Kojto	122:f9eeca106725	5273	#define FMC_BTR2_DATAST_2 0x00000400U /!<Bit 2 /
Kojto	122:f9eeca106725	5274	#define FMC_BTR2_DATAST_3 0x00000800U /!<Bit 3 /
Kojto	122:f9eeca106725	5275	#define FMC_BTR2_DATAST_4 0x00001000U /!<Bit 4 /
Kojto	122:f9eeca106725	5276	#define FMC_BTR2_DATAST_5 0x00002000U /!<Bit 5 /
Kojto	122:f9eeca106725	5277	#define FMC_BTR2_DATAST_6 0x00004000U /!<Bit 6 /
Kojto	122:f9eeca106725	5278	#define FMC_BTR2_DATAST_7 0x00008000U /!<Bit 7 /
Kojto	122:f9eeca106725	5279
Kojto	122:f9eeca106725	5280	#define FMC_BTR2_BUSTURN 0x000F0000U /!<BUSTURN[3:0] bits (Bus turnaround phase duration) /
Kojto	122:f9eeca106725	5281	#define FMC_BTR2_BUSTURN_0 0x00010000U /!<Bit 0 /
Kojto	122:f9eeca106725	5282	#define FMC_BTR2_BUSTURN_1 0x00020000U /!<Bit 1 /
Kojto	122:f9eeca106725	5283	#define FMC_BTR2_BUSTURN_2 0x00040000U /!<Bit 2 /
Kojto	122:f9eeca106725	5284	#define FMC_BTR2_BUSTURN_3 0x00080000U /!<Bit 3 /
Kojto	122:f9eeca106725	5285
Kojto	122:f9eeca106725	5286	#define FMC_BTR2_CLKDIV 0x00F00000U /!<CLKDIV[3:0] bits (Clock divide ratio) /
Kojto	122:f9eeca106725	5287	#define FMC_BTR2_CLKDIV_0 0x00100000U /!<Bit 0 /
Kojto	122:f9eeca106725	5288	#define FMC_BTR2_CLKDIV_1 0x00200000U /!<Bit 1 /
Kojto	122:f9eeca106725	5289	#define FMC_BTR2_CLKDIV_2 0x00400000U /!<Bit 2 /
Kojto	122:f9eeca106725	5290	#define FMC_BTR2_CLKDIV_3 0x00800000U /!<Bit 3 /
Kojto	122:f9eeca106725	5291
Kojto	122:f9eeca106725	5292	#define FMC_BTR2_DATLAT 0x0F000000U /!<DATLA[3:0] bits (Data latency) /
Kojto	122:f9eeca106725	5293	#define FMC_BTR2_DATLAT_0 0x01000000U /!<Bit 0 /
Kojto	122:f9eeca106725	5294	#define FMC_BTR2_DATLAT_1 0x02000000U /!<Bit 1 /
Kojto	122:f9eeca106725	5295	#define FMC_BTR2_DATLAT_2 0x04000000U /!<Bit 2 /
Kojto	122:f9eeca106725	5296	#define FMC_BTR2_DATLAT_3 0x08000000U /!<Bit 3 /
Kojto	122:f9eeca106725	5297
Kojto	122:f9eeca106725	5298	#define FMC_BTR2_ACCMOD 0x30000000U /!<ACCMOD[1:0] bits (Access mode) /
Kojto	122:f9eeca106725	5299	#define FMC_BTR2_ACCMOD_0 0x10000000U /!<Bit 0 /
Kojto	122:f9eeca106725	5300	#define FMC_BTR2_ACCMOD_1 0x20000000U /!<Bit 1 /
Kojto	110:165afa46840b	5301
Kojto	110:165afa46840b	5302	/***************** Bit definition for FMC_BTR3 register *****************/
Kojto	122:f9eeca106725	5303	#define FMC_BTR3_ADDSET 0x0000000FU /!<ADDSET[3:0] bits (Address setup phase duration) /
Kojto	122:f9eeca106725	5304	#define FMC_BTR3_ADDSET_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	5305	#define FMC_BTR3_ADDSET_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	5306	#define FMC_BTR3_ADDSET_2 0x00000004U /!<Bit 2 /
Kojto	122:f9eeca106725	5307	#define FMC_BTR3_ADDSET_3 0x00000008U /!<Bit 3 /
Kojto	122:f9eeca106725	5308
Kojto	122:f9eeca106725	5309	#define FMC_BTR3_ADDHLD 0x000000F0U /!<ADDHLD[3:0] bits (Address-hold phase duration) /
Kojto	122:f9eeca106725	5310	#define FMC_BTR3_ADDHLD_0 0x00000010U /!<Bit 0 /
Kojto	122:f9eeca106725	5311	#define FMC_BTR3_ADDHLD_1 0x00000020U /!<Bit 1 /
Kojto	122:f9eeca106725	5312	#define FMC_BTR3_ADDHLD_2 0x00000040U /!<Bit 2 /
Kojto	122:f9eeca106725	5313	#define FMC_BTR3_ADDHLD_3 0x00000080U /!<Bit 3 /
Kojto	122:f9eeca106725	5314
Kojto	122:f9eeca106725	5315	#define FMC_BTR3_DATAST 0x0000FF00U /!<DATAST [3:0] bits (Data-phase duration) /
Kojto	122:f9eeca106725	5316	#define FMC_BTR3_DATAST_0 0x00000100U /!<Bit 0 /
Kojto	122:f9eeca106725	5317	#define FMC_BTR3_DATAST_1 0x00000200U /!<Bit 1 /
Kojto	122:f9eeca106725	5318	#define FMC_BTR3_DATAST_2 0x00000400U /!<Bit 2 /
Kojto	122:f9eeca106725	5319	#define FMC_BTR3_DATAST_3 0x00000800U /!<Bit 3 /
Kojto	122:f9eeca106725	5320	#define FMC_BTR3_DATAST_4 0x00001000U /!<Bit 4 /
Kojto	122:f9eeca106725	5321	#define FMC_BTR3_DATAST_5 0x00002000U /!<Bit 5 /
Kojto	122:f9eeca106725	5322	#define FMC_BTR3_DATAST_6 0x00004000U /!<Bit 6 /
Kojto	122:f9eeca106725	5323	#define FMC_BTR3_DATAST_7 0x00008000U /!<Bit 7 /
Kojto	122:f9eeca106725	5324
Kojto	122:f9eeca106725	5325	#define FMC_BTR3_BUSTURN 0x000F0000U /!<BUSTURN[3:0] bits (Bus turnaround phase duration) /
Kojto	122:f9eeca106725	5326	#define FMC_BTR3_BUSTURN_0 0x00010000U /!<Bit 0 /
Kojto	122:f9eeca106725	5327	#define FMC_BTR3_BUSTURN_1 0x00020000U /!<Bit 1 /
Kojto	122:f9eeca106725	5328	#define FMC_BTR3_BUSTURN_2 0x00040000U /!<Bit 2 /
Kojto	122:f9eeca106725	5329	#define FMC_BTR3_BUSTURN_3 0x00080000U /!<Bit 3 /
Kojto	122:f9eeca106725	5330
Kojto	122:f9eeca106725	5331	#define FMC_BTR3_CLKDIV 0x00F00000U /!<CLKDIV[3:0] bits (Clock divide ratio) /
Kojto	122:f9eeca106725	5332	#define FMC_BTR3_CLKDIV_0 0x00100000U /!<Bit 0 /
Kojto	122:f9eeca106725	5333	#define FMC_BTR3_CLKDIV_1 0x00200000U /!<Bit 1 /
Kojto	122:f9eeca106725	5334	#define FMC_BTR3_CLKDIV_2 0x00400000U /!<Bit 2 /
Kojto	122:f9eeca106725	5335	#define FMC_BTR3_CLKDIV_3 0x00800000U /!<Bit 3 /
Kojto	122:f9eeca106725	5336
Kojto	122:f9eeca106725	5337	#define FMC_BTR3_DATLAT 0x0F000000U /!<DATLA[3:0] bits (Data latency) /
Kojto	122:f9eeca106725	5338	#define FMC_BTR3_DATLAT_0 0x01000000U /!<Bit 0 /
Kojto	122:f9eeca106725	5339	#define FMC_BTR3_DATLAT_1 0x02000000U /!<Bit 1 /
Kojto	122:f9eeca106725	5340	#define FMC_BTR3_DATLAT_2 0x04000000U /!<Bit 2 /
Kojto	122:f9eeca106725	5341	#define FMC_BTR3_DATLAT_3 0x08000000U /!<Bit 3 /
Kojto	122:f9eeca106725	5342
Kojto	122:f9eeca106725	5343	#define FMC_BTR3_ACCMOD 0x30000000U /!<ACCMOD[1:0] bits (Access mode) /
Kojto	122:f9eeca106725	5344	#define FMC_BTR3_ACCMOD_0 0x10000000U /!<Bit 0 /
Kojto	122:f9eeca106725	5345	#define FMC_BTR3_ACCMOD_1 0x20000000U /!<Bit 1 /
Kojto	110:165afa46840b	5346
Kojto	110:165afa46840b	5347	/**************** Bit definition for FMC_BTR4 register *****************/
Kojto	122:f9eeca106725	5348	#define FMC_BTR4_ADDSET 0x0000000FU /!<ADDSET[3:0] bits (Address setup phase duration) /
Kojto	122:f9eeca106725	5349	#define FMC_BTR4_ADDSET_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	5350	#define FMC_BTR4_ADDSET_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	5351	#define FMC_BTR4_ADDSET_2 0x00000004U /!<Bit 2 /
Kojto	122:f9eeca106725	5352	#define FMC_BTR4_ADDSET_3 0x00000008U /!<Bit 3 /
Kojto	122:f9eeca106725	5353
Kojto	122:f9eeca106725	5354	#define FMC_BTR4_ADDHLD 0x000000F0U /!<ADDHLD[3:0] bits (Address-hold phase duration) /
Kojto	122:f9eeca106725	5355	#define FMC_BTR4_ADDHLD_0 0x00000010U /!<Bit 0 /
Kojto	122:f9eeca106725	5356	#define FMC_BTR4_ADDHLD_1 0x00000020U /!<Bit 1 /
Kojto	122:f9eeca106725	5357	#define FMC_BTR4_ADDHLD_2 0x00000040U /!<Bit 2 /
Kojto	122:f9eeca106725	5358	#define FMC_BTR4_ADDHLD_3 0x00000080U /!<Bit 3 /
Kojto	122:f9eeca106725	5359
Kojto	122:f9eeca106725	5360	#define FMC_BTR4_DATAST 0x0000FF00U /!<DATAST [3:0] bits (Data-phase duration) /
Kojto	122:f9eeca106725	5361	#define FMC_BTR4_DATAST_0 0x00000100U /!<Bit 0 /
Kojto	122:f9eeca106725	5362	#define FMC_BTR4_DATAST_1 0x00000200U /!<Bit 1 /
Kojto	122:f9eeca106725	5363	#define FMC_BTR4_DATAST_2 0x00000400U /!<Bit 2 /
Kojto	122:f9eeca106725	5364	#define FMC_BTR4_DATAST_3 0x00000800U /!<Bit 3 /
Kojto	122:f9eeca106725	5365	#define FMC_BTR4_DATAST_4 0x00001000U /!<Bit 4 /
Kojto	122:f9eeca106725	5366	#define FMC_BTR4_DATAST_5 0x00002000U /!<Bit 5 /
Kojto	122:f9eeca106725	5367	#define FMC_BTR4_DATAST_6 0x00004000U /!<Bit 6 /
Kojto	122:f9eeca106725	5368	#define FMC_BTR4_DATAST_7 0x00008000U /!<Bit 7 /
Kojto	122:f9eeca106725	5369
Kojto	122:f9eeca106725	5370	#define FMC_BTR4_BUSTURN 0x000F0000U /!<BUSTURN[3:0] bits (Bus turnaround phase duration) /
Kojto	122:f9eeca106725	5371	#define FMC_BTR4_BUSTURN_0 0x00010000U /!<Bit 0 /
Kojto	122:f9eeca106725	5372	#define FMC_BTR4_BUSTURN_1 0x00020000U /!<Bit 1 /
Kojto	122:f9eeca106725	5373	#define FMC_BTR4_BUSTURN_2 0x00040000U /!<Bit 2 /
Kojto	122:f9eeca106725	5374	#define FMC_BTR4_BUSTURN_3 0x00080000U /!<Bit 3 /
Kojto	122:f9eeca106725	5375
Kojto	122:f9eeca106725	5376	#define FMC_BTR4_CLKDIV 0x00F00000U /!<CLKDIV[3:0] bits (Clock divide ratio) /
Kojto	122:f9eeca106725	5377	#define FMC_BTR4_CLKDIV_0 0x00100000U /!<Bit 0 /
Kojto	122:f9eeca106725	5378	#define FMC_BTR4_CLKDIV_1 0x00200000U /!<Bit 1 /
Kojto	122:f9eeca106725	5379	#define FMC_BTR4_CLKDIV_2 0x00400000U /!<Bit 2 /
Kojto	122:f9eeca106725	5380	#define FMC_BTR4_CLKDIV_3 0x00800000U /!<Bit 3 /
Kojto	122:f9eeca106725	5381
Kojto	122:f9eeca106725	5382	#define FMC_BTR4_DATLAT 0x0F000000U /!<DATLA[3:0] bits (Data latency) /
Kojto	122:f9eeca106725	5383	#define FMC_BTR4_DATLAT_0 0x01000000U /!<Bit 0 /
Kojto	122:f9eeca106725	5384	#define FMC_BTR4_DATLAT_1 0x02000000U /!<Bit 1 /
Kojto	122:f9eeca106725	5385	#define FMC_BTR4_DATLAT_2 0x04000000U /!<Bit 2 /
Kojto	122:f9eeca106725	5386	#define FMC_BTR4_DATLAT_3 0x08000000U /!<Bit 3 /
Kojto	122:f9eeca106725	5387
Kojto	122:f9eeca106725	5388	#define FMC_BTR4_ACCMOD 0x30000000U /!<ACCMOD[1:0] bits (Access mode) /
Kojto	122:f9eeca106725	5389	#define FMC_BTR4_ACCMOD_0 0x10000000U /!<Bit 0 /
Kojto	122:f9eeca106725	5390	#define FMC_BTR4_ACCMOD_1 0x20000000U /!<Bit 1 /
Kojto	110:165afa46840b	5391
Kojto	110:165afa46840b	5392	/**************** Bit definition for FMC_BWTR1 register ****************/
Kojto	122:f9eeca106725	5393	#define FMC_BWTR1_ADDSET 0x0000000FU /!<ADDSET[3:0] bits (Address setup phase duration) /
Kojto	122:f9eeca106725	5394	#define FMC_BWTR1_ADDSET_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	5395	#define FMC_BWTR1_ADDSET_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	5396	#define FMC_BWTR1_ADDSET_2 0x00000004U /!<Bit 2 /
Kojto	122:f9eeca106725	5397	#define FMC_BWTR1_ADDSET_3 0x00000008U /!<Bit 3 /
Kojto	122:f9eeca106725	5398
Kojto	122:f9eeca106725	5399	#define FMC_BWTR1_ADDHLD 0x000000F0U /!<ADDHLD[3:0] bits (Address-hold phase duration) /
Kojto	122:f9eeca106725	5400	#define FMC_BWTR1_ADDHLD_0 0x00000010U /!<Bit 0 /
Kojto	122:f9eeca106725	5401	#define FMC_BWTR1_ADDHLD_1 0x00000020U /!<Bit 1 /
Kojto	122:f9eeca106725	5402	#define FMC_BWTR1_ADDHLD_2 0x00000040U /!<Bit 2 /
Kojto	122:f9eeca106725	5403	#define FMC_BWTR1_ADDHLD_3 0x00000080U /!<Bit 3 /
Kojto	122:f9eeca106725	5404
Kojto	122:f9eeca106725	5405	#define FMC_BWTR1_DATAST 0x0000FF00U /!<DATAST [3:0] bits (Data-phase duration) /
Kojto	122:f9eeca106725	5406	#define FMC_BWTR1_DATAST_0 0x00000100U /!<Bit 0 /
Kojto	122:f9eeca106725	5407	#define FMC_BWTR1_DATAST_1 0x00000200U /!<Bit 1 /
Kojto	122:f9eeca106725	5408	#define FMC_BWTR1_DATAST_2 0x00000400U /!<Bit 2 /
Kojto	122:f9eeca106725	5409	#define FMC_BWTR1_DATAST_3 0x00000800U /!<Bit 3 /
Kojto	122:f9eeca106725	5410	#define FMC_BWTR1_DATAST_4 0x00001000U /!<Bit 4 /
Kojto	122:f9eeca106725	5411	#define FMC_BWTR1_DATAST_5 0x00002000U /!<Bit 5 /
Kojto	122:f9eeca106725	5412	#define FMC_BWTR1_DATAST_6 0x00004000U /!<Bit 6 /
Kojto	122:f9eeca106725	5413	#define FMC_BWTR1_DATAST_7 0x00008000U /!<Bit 7 /
Kojto	122:f9eeca106725	5414
Kojto	122:f9eeca106725	5415	#define FMC_BWTR1_BUSTURN 0x000F0000U /!<BUSTURN[3:0] bits (Bus turnaround duration) /
Kojto	122:f9eeca106725	5416	#define FMC_BWTR1_BUSTURN_0 0x00010000U /!<Bit 0 /
Kojto	122:f9eeca106725	5417	#define FMC_BWTR1_BUSTURN_1 0x00020000U /!<Bit 1 /
Kojto	122:f9eeca106725	5418	#define FMC_BWTR1_BUSTURN_2 0x00040000U /!<Bit 2 /
Kojto	122:f9eeca106725	5419	#define FMC_BWTR1_BUSTURN_3 0x00080000U /!<Bit 3 /
Kojto	122:f9eeca106725	5420
Kojto	122:f9eeca106725	5421	#define FMC_BWTR1_ACCMOD 0x30000000U /!<ACCMOD[1:0] bits (Access mode) /
Kojto	122:f9eeca106725	5422	#define FMC_BWTR1_ACCMOD_0 0x10000000U /!<Bit 0 /
Kojto	122:f9eeca106725	5423	#define FMC_BWTR1_ACCMOD_1 0x20000000U /!<Bit 1 /
Kojto	110:165afa46840b	5424
Kojto	110:165afa46840b	5425	/**************** Bit definition for FMC_BWTR2 register ****************/
Kojto	122:f9eeca106725	5426	#define FMC_BWTR2_ADDSET 0x0000000FU /!<ADDSET[3:0] bits (Address setup phase duration) /
Kojto	122:f9eeca106725	5427	#define FMC_BWTR2_ADDSET_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	5428	#define FMC_BWTR2_ADDSET_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	5429	#define FMC_BWTR2_ADDSET_2 0x00000004U /!<Bit 2 /
Kojto	122:f9eeca106725	5430	#define FMC_BWTR2_ADDSET_3 0x00000008U /!<Bit 3 /
Kojto	122:f9eeca106725	5431
Kojto	122:f9eeca106725	5432	#define FMC_BWTR2_ADDHLD 0x000000F0U /!<ADDHLD[3:0] bits (Address-hold phase duration) /
Kojto	122:f9eeca106725	5433	#define FMC_BWTR2_ADDHLD_0 0x00000010U /!<Bit 0 /
Kojto	122:f9eeca106725	5434	#define FMC_BWTR2_ADDHLD_1 0x00000020U /!<Bit 1 /
Kojto	122:f9eeca106725	5435	#define FMC_BWTR2_ADDHLD_2 0x00000040U /!<Bit 2 /
Kojto	122:f9eeca106725	5436	#define FMC_BWTR2_ADDHLD_3 0x00000080U /!<Bit 3 /
Kojto	122:f9eeca106725	5437
Kojto	122:f9eeca106725	5438	#define FMC_BWTR2_DATAST 0x0000FF00U /!<DATAST [3:0] bits (Data-phase duration) /
Kojto	122:f9eeca106725	5439	#define FMC_BWTR2_DATAST_0 0x00000100U /!<Bit 0 /
Kojto	122:f9eeca106725	5440	#define FMC_BWTR2_DATAST_1 0x00000200U /!<Bit 1 /
Kojto	122:f9eeca106725	5441	#define FMC_BWTR2_DATAST_2 0x00000400U /!<Bit 2 /
Kojto	122:f9eeca106725	5442	#define FMC_BWTR2_DATAST_3 0x00000800U /!<Bit 3 /
Kojto	122:f9eeca106725	5443	#define FMC_BWTR2_DATAST_4 0x00001000U /!<Bit 4 /
Kojto	122:f9eeca106725	5444	#define FMC_BWTR2_DATAST_5 0x00002000U /!<Bit 5 /
Kojto	122:f9eeca106725	5445	#define FMC_BWTR2_DATAST_6 0x00004000U /!<Bit 6 /
Kojto	122:f9eeca106725	5446	#define FMC_BWTR2_DATAST_7 0x00008000U /!<Bit 7 /
Kojto	122:f9eeca106725	5447
Kojto	122:f9eeca106725	5448	#define FMC_BWTR2_BUSTURN 0x000F0000U /!<BUSTURN[3:0] bits (Bus turnaround duration) /
Kojto	122:f9eeca106725	5449	#define FMC_BWTR2_BUSTURN_0 0x00010000U /!<Bit 0 /
Kojto	122:f9eeca106725	5450	#define FMC_BWTR2_BUSTURN_1 0x00020000U /!<Bit 1 /
Kojto	122:f9eeca106725	5451	#define FMC_BWTR2_BUSTURN_2 0x00040000U /!<Bit 2 /
Kojto	122:f9eeca106725	5452	#define FMC_BWTR2_BUSTURN_3 0x00080000U /!<Bit 3 /
Kojto	122:f9eeca106725	5453
Kojto	122:f9eeca106725	5454	#define FMC_BWTR2_ACCMOD 0x30000000U /!<ACCMOD[1:0] bits (Access mode) /
Kojto	122:f9eeca106725	5455	#define FMC_BWTR2_ACCMOD_0 0x10000000U /!<Bit 0 /
Kojto	122:f9eeca106725	5456	#define FMC_BWTR2_ACCMOD_1 0x20000000U /!<Bit 1 /
Kojto	110:165afa46840b	5457
Kojto	110:165afa46840b	5458	/**************** Bit definition for FMC_BWTR3 register ****************/
Kojto	122:f9eeca106725	5459	#define FMC_BWTR3_ADDSET 0x0000000FU /!<ADDSET[3:0] bits (Address setup phase duration) /
Kojto	122:f9eeca106725	5460	#define FMC_BWTR3_ADDSET_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	5461	#define FMC_BWTR3_ADDSET_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	5462	#define FMC_BWTR3_ADDSET_2 0x00000004U /!<Bit 2 /
Kojto	122:f9eeca106725	5463	#define FMC_BWTR3_ADDSET_3 0x00000008U /!<Bit 3 /
Kojto	122:f9eeca106725	5464
Kojto	122:f9eeca106725	5465	#define FMC_BWTR3_ADDHLD 0x000000F0U /!<ADDHLD[3:0] bits (Address-hold phase duration) /
Kojto	122:f9eeca106725	5466	#define FMC_BWTR3_ADDHLD_0 0x00000010U /!<Bit 0 /
Kojto	122:f9eeca106725	5467	#define FMC_BWTR3_ADDHLD_1 0x00000020U /!<Bit 1 /
Kojto	122:f9eeca106725	5468	#define FMC_BWTR3_ADDHLD_2 0x00000040U /!<Bit 2 /
Kojto	122:f9eeca106725	5469	#define FMC_BWTR3_ADDHLD_3 0x00000080U /!<Bit 3 /
Kojto	122:f9eeca106725	5470
Kojto	122:f9eeca106725	5471	#define FMC_BWTR3_DATAST 0x0000FF00U /!<DATAST [3:0] bits (Data-phase duration) /
Kojto	122:f9eeca106725	5472	#define FMC_BWTR3_DATAST_0 0x00000100U /!<Bit 0 /
Kojto	122:f9eeca106725	5473	#define FMC_BWTR3_DATAST_1 0x00000200U /!<Bit 1 /
Kojto	122:f9eeca106725	5474	#define FMC_BWTR3_DATAST_2 0x00000400U /!<Bit 2 /
Kojto	122:f9eeca106725	5475	#define FMC_BWTR3_DATAST_3 0x00000800U /!<Bit 3 /
Kojto	122:f9eeca106725	5476	#define FMC_BWTR3_DATAST_4 0x00001000U /!<Bit 4 /
Kojto	122:f9eeca106725	5477	#define FMC_BWTR3_DATAST_5 0x00002000U /!<Bit 5 /
Kojto	122:f9eeca106725	5478	#define FMC_BWTR3_DATAST_6 0x00004000U /!<Bit 6 /
Kojto	122:f9eeca106725	5479	#define FMC_BWTR3_DATAST_7 0x00008000U /!<Bit 7 /
Kojto	122:f9eeca106725	5480
Kojto	122:f9eeca106725	5481	#define FMC_BWTR3_BUSTURN 0x000F0000U /!<BUSTURN[3:0] bits (Bus turnaround duration) /
Kojto	122:f9eeca106725	5482	#define FMC_BWTR3_BUSTURN_0 0x00010000U /!<Bit 0 /
Kojto	122:f9eeca106725	5483	#define FMC_BWTR3_BUSTURN_1 0x00020000U /!<Bit 1 /
Kojto	122:f9eeca106725	5484	#define FMC_BWTR3_BUSTURN_2 0x00040000U /!<Bit 2 /
Kojto	122:f9eeca106725	5485	#define FMC_BWTR3_BUSTURN_3 0x00080000U /!<Bit 3 /
Kojto	122:f9eeca106725	5486
Kojto	122:f9eeca106725	5487	#define FMC_BWTR3_ACCMOD 0x30000000U /!<ACCMOD[1:0] bits (Access mode) /
Kojto	122:f9eeca106725	5488	#define FMC_BWTR3_ACCMOD_0 0x10000000U /!<Bit 0 /
Kojto	122:f9eeca106725	5489	#define FMC_BWTR3_ACCMOD_1 0x20000000U /!<Bit 1 /
Kojto	110:165afa46840b	5490
Kojto	110:165afa46840b	5491	/**************** Bit definition for FMC_BWTR4 register ****************/
Kojto	122:f9eeca106725	5492	#define FMC_BWTR4_ADDSET 0x0000000FU /!<ADDSET[3:0] bits (Address setup phase duration) /
Kojto	122:f9eeca106725	5493	#define FMC_BWTR4_ADDSET_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	5494	#define FMC_BWTR4_ADDSET_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	5495	#define FMC_BWTR4_ADDSET_2 0x00000004U /!<Bit 2 /
Kojto	122:f9eeca106725	5496	#define FMC_BWTR4_ADDSET_3 0x00000008U /!<Bit 3 /
Kojto	122:f9eeca106725	5497
Kojto	122:f9eeca106725	5498	#define FMC_BWTR4_ADDHLD 0x000000F0U /!<ADDHLD[3:0] bits (Address-hold phase duration) /
Kojto	122:f9eeca106725	5499	#define FMC_BWTR4_ADDHLD_0 0x00000010U /!<Bit 0 /
Kojto	122:f9eeca106725	5500	#define FMC_BWTR4_ADDHLD_1 0x00000020U /!<Bit 1 /
Kojto	122:f9eeca106725	5501	#define FMC_BWTR4_ADDHLD_2 0x00000040U /!<Bit 2 /
Kojto	122:f9eeca106725	5502	#define FMC_BWTR4_ADDHLD_3 0x00000080U /!<Bit 3 /
Kojto	122:f9eeca106725	5503
Kojto	122:f9eeca106725	5504	#define FMC_BWTR4_DATAST 0x0000FF00U /!<DATAST [3:0] bits (Data-phase duration) /
Kojto	122:f9eeca106725	5505	#define FMC_BWTR4_DATAST_0 0x00000100U /!<Bit 0 /
Kojto	122:f9eeca106725	5506	#define FMC_BWTR4_DATAST_1 0x00000200U /!<Bit 1 /
Kojto	122:f9eeca106725	5507	#define FMC_BWTR4_DATAST_2 0x00000400U /!<Bit 2 /
Kojto	122:f9eeca106725	5508	#define FMC_BWTR4_DATAST_3 0x00000800U /!<Bit 3 /
Kojto	122:f9eeca106725	5509	#define FMC_BWTR4_DATAST_4 0x00001000U /!<Bit 4 /
Kojto	122:f9eeca106725	5510	#define FMC_BWTR4_DATAST_5 0x00002000U /!<Bit 5 /
Kojto	122:f9eeca106725	5511	#define FMC_BWTR4_DATAST_6 0x00004000U /!<Bit 6 /
Kojto	122:f9eeca106725	5512	#define FMC_BWTR4_DATAST_7 0x00008000U /!<Bit 7 /
Kojto	122:f9eeca106725	5513
Kojto	122:f9eeca106725	5514	#define FMC_BWTR4_BUSTURN 0x000F0000U /!<BUSTURN[3:0] bits (Bus turnaround duration) /
Kojto	122:f9eeca106725	5515	#define FMC_BWTR4_BUSTURN_0 0x00010000U /!<Bit 0 /
Kojto	122:f9eeca106725	5516	#define FMC_BWTR4_BUSTURN_1 0x00020000U /!<Bit 1 /
Kojto	122:f9eeca106725	5517	#define FMC_BWTR4_BUSTURN_2 0x00040000U /!<Bit 2 /
Kojto	122:f9eeca106725	5518	#define FMC_BWTR4_BUSTURN_3 0x00080000U /!<Bit 3 /
Kojto	122:f9eeca106725	5519
Kojto	122:f9eeca106725	5520	#define FMC_BWTR4_ACCMOD 0x30000000U /!<ACCMOD[1:0] bits (Access mode) /
Kojto	122:f9eeca106725	5521	#define FMC_BWTR4_ACCMOD_0 0x10000000U /!<Bit 0 /
Kojto	122:f9eeca106725	5522	#define FMC_BWTR4_ACCMOD_1 0x20000000U /!<Bit 1 /
Kojto	110:165afa46840b	5523
Kojto	110:165afa46840b	5524	/**************** Bit definition for FMC_PCR register *****************/
Kojto	122:f9eeca106725	5525	#define FMC_PCR_PWAITEN 0x00000002U /!<Wait feature enable bit /
Kojto	122:f9eeca106725	5526	#define FMC_PCR_PBKEN 0x00000004U /!<PC Card/NAND Flash memory bank enable bit /
Kojto	122:f9eeca106725	5527	#define FMC_PCR_PTYP 0x00000008U /!<Memory type /
Kojto	122:f9eeca106725	5528
Kojto	122:f9eeca106725	5529	#define FMC_PCR_PWID 0x00000030U /!<PWID[1:0] bits (NAND Flash databus width) /
Kojto	122:f9eeca106725	5530	#define FMC_PCR_PWID_0 0x00000010U /!<Bit 0 /
Kojto	122:f9eeca106725	5531	#define FMC_PCR_PWID_1 0x00000020U /!<Bit 1 /
Kojto	122:f9eeca106725	5532
Kojto	122:f9eeca106725	5533	#define FMC_PCR_ECCEN 0x00000040U /!<ECC computation logic enable bit /
Kojto	122:f9eeca106725	5534
Kojto	122:f9eeca106725	5535	#define FMC_PCR_TCLR 0x00001E00U /!<TCLR[3:0] bits (CLE to RE delay) /
Kojto	122:f9eeca106725	5536	#define FMC_PCR_TCLR_0 0x00000200U /!<Bit 0 /
Kojto	122:f9eeca106725	5537	#define FMC_PCR_TCLR_1 0x00000400U /!<Bit 1 /
Kojto	122:f9eeca106725	5538	#define FMC_PCR_TCLR_2 0x00000800U /!<Bit 2 /
Kojto	122:f9eeca106725	5539	#define FMC_PCR_TCLR_3 0x00001000U /!<Bit 3 /
Kojto	122:f9eeca106725	5540
Kojto	122:f9eeca106725	5541	#define FMC_PCR_TAR 0x0001E000U /!<TAR[3:0] bits (ALE to RE delay) /
Kojto	122:f9eeca106725	5542	#define FMC_PCR_TAR_0 0x00002000U /!<Bit 0 /
Kojto	122:f9eeca106725	5543	#define FMC_PCR_TAR_1 0x00004000U /!<Bit 1 /
Kojto	122:f9eeca106725	5544	#define FMC_PCR_TAR_2 0x00008000U /!<Bit 2 /
Kojto	122:f9eeca106725	5545	#define FMC_PCR_TAR_3 0x00010000U /!<Bit 3 /
Kojto	122:f9eeca106725	5546
Kojto	122:f9eeca106725	5547	#define FMC_PCR_ECCPS 0x000E0000U /!<ECCPS[1:0] bits (ECC page size) /
Kojto	122:f9eeca106725	5548	#define FMC_PCR_ECCPS_0 0x00020000U /!<Bit 0 /
Kojto	122:f9eeca106725	5549	#define FMC_PCR_ECCPS_1 0x00040000U /!<Bit 1 /
Kojto	122:f9eeca106725	5550	#define FMC_PCR_ECCPS_2 0x00080000U /!<Bit 2 /
Kojto	110:165afa46840b	5551
Kojto	110:165afa46840b	5552	/***************** Bit definition for FMC_SR register *****************/
Kojto	122:f9eeca106725	5553	#define FMC_SR_IRS 0x01U /!<Interrupt Rising Edge status /
Kojto	122:f9eeca106725	5554	#define FMC_SR_ILS 0x02U /!<Interrupt Level status /
Kojto	122:f9eeca106725	5555	#define FMC_SR_IFS 0x04U /!<Interrupt Falling Edge status /
Kojto	122:f9eeca106725	5556	#define FMC_SR_IREN 0x08U /!<Interrupt Rising Edge detection Enable bit /
Kojto	122:f9eeca106725	5557	#define FMC_SR_ILEN 0x10U /!<Interrupt Level detection Enable bit /
Kojto	122:f9eeca106725	5558	#define FMC_SR_IFEN 0x20U /!<Interrupt Falling Edge detection Enable bit /
Kojto	122:f9eeca106725	5559	#define FMC_SR_FEMPT 0x40U /!<FIFO empty /
Kojto	110:165afa46840b	5560
Kojto	110:165afa46840b	5561	/**************** Bit definition for FMC_PMEM register ****************/
Kojto	122:f9eeca106725	5562	#define FMC_PMEM_MEMSET2 0x000000FFU /!<MEMSET2[7:0] bits (Common memory 2 setup time) /
Kojto	122:f9eeca106725	5563	#define FMC_PMEM_MEMSET2_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	5564	#define FMC_PMEM_MEMSET2_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	5565	#define FMC_PMEM_MEMSET2_2 0x00000004U /!<Bit 2 /
Kojto	122:f9eeca106725	5566	#define FMC_PMEM_MEMSET2_3 0x00000008U /!<Bit 3 /
Kojto	122:f9eeca106725	5567	#define FMC_PMEM_MEMSET2_4 0x00000010U /!<Bit 4 /
Kojto	122:f9eeca106725	5568	#define FMC_PMEM_MEMSET2_5 0x00000020U /!<Bit 5 /
Kojto	122:f9eeca106725	5569	#define FMC_PMEM_MEMSET2_6 0x00000040U /!<Bit 6 /
Kojto	122:f9eeca106725	5570	#define FMC_PMEM_MEMSET2_7 0x00000080U /!<Bit 7 /
Kojto	122:f9eeca106725	5571
Kojto	122:f9eeca106725	5572	#define FMC_PMEM_MEMWAIT2 0x0000FF00U /!<MEMWAIT2[7:0] bits (Common memory 2 wait time) /
Kojto	122:f9eeca106725	5573	#define FMC_PMEM_MEMWAIT2_0 0x00000100U /!<Bit 0 /
Kojto	122:f9eeca106725	5574	#define FMC_PMEM_MEMWAIT2_1 0x00000200U /!<Bit 1 /
Kojto	122:f9eeca106725	5575	#define FMC_PMEM_MEMWAIT2_2 0x00000400U /!<Bit 2 /
Kojto	122:f9eeca106725	5576	#define FMC_PMEM_MEMWAIT2_3 0x00000800U /!<Bit 3 /
Kojto	122:f9eeca106725	5577	#define FMC_PMEM_MEMWAIT2_4 0x00001000U /!<Bit 4 /
Kojto	122:f9eeca106725	5578	#define FMC_PMEM_MEMWAIT2_5 0x00002000U /!<Bit 5 /
Kojto	122:f9eeca106725	5579	#define FMC_PMEM_MEMWAIT2_6 0x00004000U /!<Bit 6 /
Kojto	122:f9eeca106725	5580	#define FMC_PMEM_MEMWAIT2_7 0x00008000U /!<Bit 7 /
Kojto	122:f9eeca106725	5581
Kojto	122:f9eeca106725	5582	#define FMC_PMEM_MEMHOLD2 0x00FF0000U /!<MEMHOLD2[7:0] bits (Common memory 2 hold time) /
Kojto	122:f9eeca106725	5583	#define FMC_PMEM_MEMHOLD2_0 0x00010000U /!<Bit 0 /
Kojto	122:f9eeca106725	5584	#define FMC_PMEM_MEMHOLD2_1 0x00020000U /!<Bit 1 /
Kojto	122:f9eeca106725	5585	#define FMC_PMEM_MEMHOLD2_2 0x00040000U /!<Bit 2 /
Kojto	122:f9eeca106725	5586	#define FMC_PMEM_MEMHOLD2_3 0x00080000U /!<Bit 3 /
Kojto	122:f9eeca106725	5587	#define FMC_PMEM_MEMHOLD2_4 0x00100000U /!<Bit 4 /
Kojto	122:f9eeca106725	5588	#define FMC_PMEM_MEMHOLD2_5 0x00200000U /!<Bit 5 /
Kojto	122:f9eeca106725	5589	#define FMC_PMEM_MEMHOLD2_6 0x00400000U /!<Bit 6 /
Kojto	122:f9eeca106725	5590	#define FMC_PMEM_MEMHOLD2_7 0x00800000U /!<Bit 7 /
Kojto	122:f9eeca106725	5591
Kojto	122:f9eeca106725	5592	#define FMC_PMEM_MEMHIZ2 0xFF000000U /!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) /
Kojto	122:f9eeca106725	5593	#define FMC_PMEM_MEMHIZ2_0 0x01000000U /!<Bit 0 /
Kojto	122:f9eeca106725	5594	#define FMC_PMEM_MEMHIZ2_1 0x02000000U /!<Bit 1 /
Kojto	122:f9eeca106725	5595	#define FMC_PMEM_MEMHIZ2_2 0x04000000U /!<Bit 2 /
Kojto	122:f9eeca106725	5596	#define FMC_PMEM_MEMHIZ2_3 0x08000000U /!<Bit 3 /
Kojto	122:f9eeca106725	5597	#define FMC_PMEM_MEMHIZ2_4 0x10000000U /!<Bit 4 /
Kojto	122:f9eeca106725	5598	#define FMC_PMEM_MEMHIZ2_5 0x20000000U /!<Bit 5 /
Kojto	122:f9eeca106725	5599	#define FMC_PMEM_MEMHIZ2_6 0x40000000U /!<Bit 6 /
Kojto	122:f9eeca106725	5600	#define FMC_PMEM_MEMHIZ2_7 0x80000000U /!<Bit 7 /
Kojto	110:165afa46840b	5601
Kojto	110:165afa46840b	5602	/**************** Bit definition for FMC_PATT register ****************/
Kojto	122:f9eeca106725	5603	#define FMC_PATT_ATTSET2 0x000000FFU /!<ATTSET2[7:0] bits (Attribute memory 2 setup time) /
Kojto	122:f9eeca106725	5604	#define FMC_PATT_ATTSET2_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	5605	#define FMC_PATT_ATTSET2_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	5606	#define FMC_PATT_ATTSET2_2 0x00000004U /!<Bit 2 /
Kojto	122:f9eeca106725	5607	#define FMC_PATT_ATTSET2_3 0x00000008U /!<Bit 3 /
Kojto	122:f9eeca106725	5608	#define FMC_PATT_ATTSET2_4 0x00000010U /!<Bit 4 /
Kojto	122:f9eeca106725	5609	#define FMC_PATT_ATTSET2_5 0x00000020U /!<Bit 5 /
Kojto	122:f9eeca106725	5610	#define FMC_PATT_ATTSET2_6 0x00000040U /!<Bit 6 /
Kojto	122:f9eeca106725	5611	#define FMC_PATT_ATTSET2_7 0x00000080U /!<Bit 7 /
Kojto	122:f9eeca106725	5612
Kojto	122:f9eeca106725	5613	#define FMC_PATT_ATTWAIT2 0x0000FF00U /!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) /
Kojto	122:f9eeca106725	5614	#define FMC_PATT_ATTWAIT2_0 0x00000100U /!<Bit 0 /
Kojto	122:f9eeca106725	5615	#define FMC_PATT_ATTWAIT2_1 0x00000200U /!<Bit 1 /
Kojto	122:f9eeca106725	5616	#define FMC_PATT_ATTWAIT2_2 0x00000400U /!<Bit 2 /
Kojto	122:f9eeca106725	5617	#define FMC_PATT_ATTWAIT2_3 0x00000800U /!<Bit 3 /
Kojto	122:f9eeca106725	5618	#define FMC_PATT_ATTWAIT2_4 0x00001000U /!<Bit 4 /
Kojto	122:f9eeca106725	5619	#define FMC_PATT_ATTWAIT2_5 0x00002000U /!<Bit 5 /
Kojto	122:f9eeca106725	5620	#define FMC_PATT_ATTWAIT2_6 0x00004000U /!<Bit 6 /
Kojto	122:f9eeca106725	5621	#define FMC_PATT_ATTWAIT2_7 0x00008000U /!<Bit 7 /
Kojto	122:f9eeca106725	5622
Kojto	122:f9eeca106725	5623	#define FMC_PATT_ATTHOLD2 0x00FF0000U /!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) /
Kojto	122:f9eeca106725	5624	#define FMC_PATT_ATTHOLD2_0 0x00010000U /!<Bit 0 /
Kojto	122:f9eeca106725	5625	#define FMC_PATT_ATTHOLD2_1 0x00020000U /!<Bit 1 /
Kojto	122:f9eeca106725	5626	#define FMC_PATT_ATTHOLD2_2 0x00040000U /!<Bit 2 /
Kojto	122:f9eeca106725	5627	#define FMC_PATT_ATTHOLD2_3 0x00080000U /!<Bit 3 /
Kojto	122:f9eeca106725	5628	#define FMC_PATT_ATTHOLD2_4 0x00100000U /!<Bit 4 /
Kojto	122:f9eeca106725	5629	#define FMC_PATT_ATTHOLD2_5 0x00200000U /!<Bit 5 /
Kojto	122:f9eeca106725	5630	#define FMC_PATT_ATTHOLD2_6 0x00400000U /!<Bit 6 /
Kojto	122:f9eeca106725	5631	#define FMC_PATT_ATTHOLD2_7 0x00800000U /!<Bit 7 /
Kojto	122:f9eeca106725	5632
Kojto	122:f9eeca106725	5633	#define FMC_PATT_ATTHIZ2 0xFF000000U /!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) /
Kojto	122:f9eeca106725	5634	#define FMC_PATT_ATTHIZ2_0 0x01000000U /!<Bit 0 /
Kojto	122:f9eeca106725	5635	#define FMC_PATT_ATTHIZ2_1 0x02000000U /!<Bit 1 /
Kojto	122:f9eeca106725	5636	#define FMC_PATT_ATTHIZ2_2 0x04000000U /!<Bit 2 /
Kojto	122:f9eeca106725	5637	#define FMC_PATT_ATTHIZ2_3 0x08000000U /!<Bit 3 /
Kojto	122:f9eeca106725	5638	#define FMC_PATT_ATTHIZ2_4 0x10000000U /!<Bit 4 /
Kojto	122:f9eeca106725	5639	#define FMC_PATT_ATTHIZ2_5 0x20000000U /!<Bit 5 /
Kojto	122:f9eeca106725	5640	#define FMC_PATT_ATTHIZ2_6 0x40000000U /!<Bit 6 /
Kojto	122:f9eeca106725	5641	#define FMC_PATT_ATTHIZ2_7 0x80000000U /!<Bit 7 /
Kojto	110:165afa46840b	5642
Kojto	110:165afa46840b	5643	/**************** Bit definition for FMC_ECCR register ****************/
Kojto	122:f9eeca106725	5644	#define FMC_ECCR_ECC2 0xFFFFFFFFU /!<ECC result /
Kojto	110:165afa46840b	5645
Kojto	110:165afa46840b	5646	/**************** Bit definition for FMC_SDCR1 register ****************/
Kojto	122:f9eeca106725	5647	#define FMC_SDCR1_NC 0x00000003U /!<NC[1:0] bits (Number of column bits) /
Kojto	122:f9eeca106725	5648	#define FMC_SDCR1_NC_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	5649	#define FMC_SDCR1_NC_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	5650
Kojto	122:f9eeca106725	5651	#define FMC_SDCR1_NR 0x0000000CU /!<NR[1:0] bits (Number of row bits) /
Kojto	122:f9eeca106725	5652	#define FMC_SDCR1_NR_0 0x00000004U /!<Bit 0 /
Kojto	122:f9eeca106725	5653	#define FMC_SDCR1_NR_1 0x00000008U /!<Bit 1 /
Kojto	122:f9eeca106725	5654
Kojto	122:f9eeca106725	5655	#define FMC_SDCR1_MWID 0x00000030U /!<NR[1:0] bits (Number of row bits) /
Kojto	122:f9eeca106725	5656	#define FMC_SDCR1_MWID_0 0x00000010U /!<Bit 0 /
Kojto	122:f9eeca106725	5657	#define FMC_SDCR1_MWID_1 0x00000020U /!<Bit 1 /
Kojto	122:f9eeca106725	5658
Kojto	122:f9eeca106725	5659	#define FMC_SDCR1_NB 0x00000040U /!<Number of internal bank /
Kojto	122:f9eeca106725	5660
Kojto	122:f9eeca106725	5661	#define FMC_SDCR1_CAS 0x00000180U /!<CAS[1:0] bits (CAS latency) /
Kojto	122:f9eeca106725	5662	#define FMC_SDCR1_CAS_0 0x00000080U /!<Bit 0 /
Kojto	122:f9eeca106725	5663	#define FMC_SDCR1_CAS_1 0x00000100U /!<Bit 1 /
Kojto	122:f9eeca106725	5664
Kojto	122:f9eeca106725	5665	#define FMC_SDCR1_WP 0x00000200U /!<Write protection /
Kojto	122:f9eeca106725	5666
Kojto	122:f9eeca106725	5667	#define FMC_SDCR1_SDCLK 0x00000C00U /!<SDRAM clock configuration /
Kojto	122:f9eeca106725	5668	#define FMC_SDCR1_SDCLK_0 0x00000400U /!<Bit 0 /
Kojto	122:f9eeca106725	5669	#define FMC_SDCR1_SDCLK_1 0x00000800U /!<Bit 1 /
Kojto	122:f9eeca106725	5670
Kojto	122:f9eeca106725	5671	#define FMC_SDCR1_RBURST 0x00001000U /!<Read burst /
Kojto	122:f9eeca106725	5672
Kojto	122:f9eeca106725	5673	#define FMC_SDCR1_RPIPE 0x00006000U /!<Write protection /
Kojto	122:f9eeca106725	5674	#define FMC_SDCR1_RPIPE_0 0x00002000U /!<Bit 0 /
Kojto	122:f9eeca106725	5675	#define FMC_SDCR1_RPIPE_1 0x00004000U /!<Bit 1 /
Kojto	110:165afa46840b	5676
Kojto	110:165afa46840b	5677	/**************** Bit definition for FMC_SDCR2 register ****************/
Kojto	122:f9eeca106725	5678	#define FMC_SDCR2_NC 0x00000003U /!<NC[1:0] bits (Number of column bits) /
Kojto	122:f9eeca106725	5679	#define FMC_SDCR2_NC_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	5680	#define FMC_SDCR2_NC_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	5681
Kojto	122:f9eeca106725	5682	#define FMC_SDCR2_NR 0x0000000CU /!<NR[1:0] bits (Number of row bits) /
Kojto	122:f9eeca106725	5683	#define FMC_SDCR2_NR_0 0x00000004U /!<Bit 0 /
Kojto	122:f9eeca106725	5684	#define FMC_SDCR2_NR_1 0x00000008U /!<Bit 1 /
Kojto	122:f9eeca106725	5685
Kojto	122:f9eeca106725	5686	#define FMC_SDCR2_MWID 0x00000030U /!<NR[1:0] bits (Number of row bits) /
Kojto	122:f9eeca106725	5687	#define FMC_SDCR2_MWID_0 0x00000010U /!<Bit 0 /
Kojto	122:f9eeca106725	5688	#define FMC_SDCR2_MWID_1 0x00000020U /!<Bit 1 /
Kojto	122:f9eeca106725	5689
Kojto	122:f9eeca106725	5690	#define FMC_SDCR2_NB 0x00000040U /!<Number of internal bank /
Kojto	122:f9eeca106725	5691
Kojto	122:f9eeca106725	5692	#define FMC_SDCR2_CAS 0x00000180U /!<CAS[1:0] bits (CAS latency) /
Kojto	122:f9eeca106725	5693	#define FMC_SDCR2_CAS_0 0x00000080U /!<Bit 0 /
Kojto	122:f9eeca106725	5694	#define FMC_SDCR2_CAS_1 0x00000100U /!<Bit 1 /
Kojto	122:f9eeca106725	5695
Kojto	122:f9eeca106725	5696	#define FMC_SDCR2_WP 0x00000200U /!<Write protection /
Kojto	122:f9eeca106725	5697
Kojto	122:f9eeca106725	5698	#define FMC_SDCR2_SDCLK 0x00000C00U /!<SDCLK[1:0] (SDRAM clock configuration) /
Kojto	122:f9eeca106725	5699	#define FMC_SDCR2_SDCLK_0 0x00000400U /!<Bit 0 /
Kojto	122:f9eeca106725	5700	#define FMC_SDCR2_SDCLK_1 0x00000800U /!<Bit 1 /
Kojto	122:f9eeca106725	5701
Kojto	122:f9eeca106725	5702	#define FMC_SDCR2_RBURST 0x00001000U /!<Read burst /
Kojto	122:f9eeca106725	5703
Kojto	122:f9eeca106725	5704	#define FMC_SDCR2_RPIPE 0x00006000U /!<RPIPE[1:0](Read pipe) /
Kojto	122:f9eeca106725	5705	#define FMC_SDCR2_RPIPE_0 0x00002000U /!<Bit 0 /
Kojto	122:f9eeca106725	5706	#define FMC_SDCR2_RPIPE_1 0x00004000U /!<Bit 1 /
Kojto	110:165afa46840b	5707
Kojto	110:165afa46840b	5708	/**************** Bit definition for FMC_SDTR1 register ****************/
Kojto	122:f9eeca106725	5709	#define FMC_SDTR1_TMRD 0x0000000FU /!<TMRD[3:0] bits (Load mode register to active) /
Kojto	122:f9eeca106725	5710	#define FMC_SDTR1_TMRD_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	5711	#define FMC_SDTR1_TMRD_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	5712	#define FMC_SDTR1_TMRD_2 0x00000004U /!<Bit 2 /
Kojto	122:f9eeca106725	5713	#define FMC_SDTR1_TMRD_3 0x00000008U /!<Bit 3 /
Kojto	110:165afa46840b	5714
Kojto	122:f9eeca106725	5715	#define FMC_SDTR1_TXSR 0x000000F0U /!<TXSR[3:0] bits (Exit self refresh) /
Kojto	122:f9eeca106725	5716	#define FMC_SDTR1_TXSR_0 0x00000010U /!<Bit 0 /
Kojto	122:f9eeca106725	5717	#define FMC_SDTR1_TXSR_1 0x00000020U /!<Bit 1 /
Kojto	122:f9eeca106725	5718	#define FMC_SDTR1_TXSR_2 0x00000040U /!<Bit 2 /
Kojto	122:f9eeca106725	5719	#define FMC_SDTR1_TXSR_3 0x00000080U /!<Bit 3 /
Kojto	122:f9eeca106725	5720
Kojto	122:f9eeca106725	5721	#define FMC_SDTR1_TRAS 0x00000F00U /!<TRAS[3:0] bits (Self refresh time) /
Kojto	122:f9eeca106725	5722	#define FMC_SDTR1_TRAS_0 0x00000100U /!<Bit 0 /
Kojto	122:f9eeca106725	5723	#define FMC_SDTR1_TRAS_1 0x00000200U /!<Bit 1 /
Kojto	122:f9eeca106725	5724	#define FMC_SDTR1_TRAS_2 0x00000400U /!<Bit 2 /
Kojto	122:f9eeca106725	5725	#define FMC_SDTR1_TRAS_3 0x00000800U /!<Bit 3 /
Kojto	122:f9eeca106725	5726
Kojto	122:f9eeca106725	5727	#define FMC_SDTR1_TRC 0x0000F000U /!<TRC[2:0] bits (Row cycle delay) /
Kojto	122:f9eeca106725	5728	#define FMC_SDTR1_TRC_0 0x00001000U /!<Bit 0 /
Kojto	122:f9eeca106725	5729	#define FMC_SDTR1_TRC_1 0x00002000U /!<Bit 1 /
Kojto	122:f9eeca106725	5730	#define FMC_SDTR1_TRC_2 0x00004000U /!<Bit 2 /
Kojto	122:f9eeca106725	5731
Kojto	122:f9eeca106725	5732	#define FMC_SDTR1_TWR 0x000F0000U /!<TRC[2:0] bits (Write recovery delay) /
Kojto	122:f9eeca106725	5733	#define FMC_SDTR1_TWR_0 0x00010000U /!<Bit 0 /
Kojto	122:f9eeca106725	5734	#define FMC_SDTR1_TWR_1 0x00020000U /!<Bit 1 /
Kojto	122:f9eeca106725	5735	#define FMC_SDTR1_TWR_2 0x00040000U /!<Bit 2 /
Kojto	122:f9eeca106725	5736
Kojto	122:f9eeca106725	5737	#define FMC_SDTR1_TRP 0x00F00000U /!<TRP[2:0] bits (Row precharge delay) /
Kojto	122:f9eeca106725	5738	#define FMC_SDTR1_TRP_0 0x00100000U /!<Bit 0 /
Kojto	122:f9eeca106725	5739	#define FMC_SDTR1_TRP_1 0x00200000U /!<Bit 1 /
Kojto	122:f9eeca106725	5740	#define FMC_SDTR1_TRP_2 0x00400000U /!<Bit 2 /
Kojto	122:f9eeca106725	5741
Kojto	122:f9eeca106725	5742	#define FMC_SDTR1_TRCD 0x0F000000U /!<TRP[2:0] bits (Row to column delay) /
Kojto	122:f9eeca106725	5743	#define FMC_SDTR1_TRCD_0 0x01000000U /!<Bit 0 /
Kojto	122:f9eeca106725	5744	#define FMC_SDTR1_TRCD_1 0x02000000U /!<Bit 1 /
Kojto	122:f9eeca106725	5745	#define FMC_SDTR1_TRCD_2 0x04000000U /!<Bit 2 /
Kojto	110:165afa46840b	5746
Kojto	110:165afa46840b	5747	/**************** Bit definition for FMC_SDTR2 register ****************/
Kojto	122:f9eeca106725	5748	#define FMC_SDTR2_TMRD 0x0000000FU /!<TMRD[3:0] bits (Load mode register to active) /
Kojto	122:f9eeca106725	5749	#define FMC_SDTR2_TMRD_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	5750	#define FMC_SDTR2_TMRD_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	5751	#define FMC_SDTR2_TMRD_2 0x00000004U /!<Bit 2 /
Kojto	122:f9eeca106725	5752	#define FMC_SDTR2_TMRD_3 0x00000008U /!<Bit 3 /
Kojto	110:165afa46840b	5753
Kojto	122:f9eeca106725	5754	#define FMC_SDTR2_TXSR 0x000000F0U /!<TXSR[3:0] bits (Exit self refresh) /
Kojto	122:f9eeca106725	5755	#define FMC_SDTR2_TXSR_0 0x00000010U /!<Bit 0 /
Kojto	122:f9eeca106725	5756	#define FMC_SDTR2_TXSR_1 0x00000020U /!<Bit 1 /
Kojto	122:f9eeca106725	5757	#define FMC_SDTR2_TXSR_2 0x00000040U /!<Bit 2 /
Kojto	122:f9eeca106725	5758	#define FMC_SDTR2_TXSR_3 0x00000080U /!<Bit 3 /
Kojto	122:f9eeca106725	5759
Kojto	122:f9eeca106725	5760	#define FMC_SDTR2_TRAS 0x00000F00U /!<TRAS[3:0] bits (Self refresh time) /
Kojto	122:f9eeca106725	5761	#define FMC_SDTR2_TRAS_0 0x00000100U /!<Bit 0 /
Kojto	122:f9eeca106725	5762	#define FMC_SDTR2_TRAS_1 0x00000200U /!<Bit 1 /
Kojto	122:f9eeca106725	5763	#define FMC_SDTR2_TRAS_2 0x00000400U /!<Bit 2 /
Kojto	122:f9eeca106725	5764	#define FMC_SDTR2_TRAS_3 0x00000800U /!<Bit 3 /
Kojto	122:f9eeca106725	5765
Kojto	122:f9eeca106725	5766	#define FMC_SDTR2_TRC 0x0000F000U /!<TRC[2:0] bits (Row cycle delay) /
Kojto	122:f9eeca106725	5767	#define FMC_SDTR2_TRC_0 0x00001000U /!<Bit 0 /
Kojto	122:f9eeca106725	5768	#define FMC_SDTR2_TRC_1 0x00002000U /!<Bit 1 /
Kojto	122:f9eeca106725	5769	#define FMC_SDTR2_TRC_2 0x00004000U /!<Bit 2 /
Kojto	122:f9eeca106725	5770
Kojto	122:f9eeca106725	5771	#define FMC_SDTR2_TWR 0x000F0000U /!<TRC[2:0] bits (Write recovery delay) /
Kojto	122:f9eeca106725	5772	#define FMC_SDTR2_TWR_0 0x00010000U /!<Bit 0 /
Kojto	122:f9eeca106725	5773	#define FMC_SDTR2_TWR_1 0x00020000U /!<Bit 1 /
Kojto	122:f9eeca106725	5774	#define FMC_SDTR2_TWR_2 0x00040000U /!<Bit 2 /
Kojto	122:f9eeca106725	5775
Kojto	122:f9eeca106725	5776	#define FMC_SDTR2_TRP 0x00F00000U /!<TRP[2:0] bits (Row precharge delay) /
Kojto	122:f9eeca106725	5777	#define FMC_SDTR2_TRP_0 0x00100000U /!<Bit 0 /
Kojto	122:f9eeca106725	5778	#define FMC_SDTR2_TRP_1 0x00200000U /!<Bit 1 /
Kojto	122:f9eeca106725	5779	#define FMC_SDTR2_TRP_2 0x00400000U /!<Bit 2 /
Kojto	122:f9eeca106725	5780
Kojto	122:f9eeca106725	5781	#define FMC_SDTR2_TRCD 0x0F000000U /!<TRP[2:0] bits (Row to column delay) /
Kojto	122:f9eeca106725	5782	#define FMC_SDTR2_TRCD_0 0x01000000U /!<Bit 0 /
Kojto	122:f9eeca106725	5783	#define FMC_SDTR2_TRCD_1 0x02000000U /!<Bit 1 /
Kojto	122:f9eeca106725	5784	#define FMC_SDTR2_TRCD_2 0x04000000U /!<Bit 2 /
Kojto	110:165afa46840b	5785
Kojto	110:165afa46840b	5786	/**************** Bit definition for FMC_SDCMR register ****************/
Kojto	122:f9eeca106725	5787	#define FMC_SDCMR_MODE 0x00000007U /!<MODE[2:0] bits (Command mode) /
Kojto	122:f9eeca106725	5788	#define FMC_SDCMR_MODE_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	5789	#define FMC_SDCMR_MODE_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	5790	#define FMC_SDCMR_MODE_2 0x00000004U /!<Bit 2 /
Kojto	110:165afa46840b	5791
Kojto	122:f9eeca106725	5792	#define FMC_SDCMR_CTB2 0x00000008U /!<Command target 2 /
Kojto	122:f9eeca106725	5793
Kojto	122:f9eeca106725	5794	#define FMC_SDCMR_CTB1 0x00000010U /!<Command target 1 /
Kojto	122:f9eeca106725	5795
Kojto	122:f9eeca106725	5796	#define FMC_SDCMR_NRFS 0x000001E0U /!<NRFS[3:0] bits (Number of auto-refresh) /
Kojto	122:f9eeca106725	5797	#define FMC_SDCMR_NRFS_0 0x00000020U /!<Bit 0 /
Kojto	122:f9eeca106725	5798	#define FMC_SDCMR_NRFS_1 0x00000040U /!<Bit 1 /
Kojto	122:f9eeca106725	5799	#define FMC_SDCMR_NRFS_2 0x00000080U /!<Bit 2 /
Kojto	122:f9eeca106725	5800	#define FMC_SDCMR_NRFS_3 0x00000100U /!<Bit 3 /
Kojto	122:f9eeca106725	5801
Kojto	122:f9eeca106725	5802	#define FMC_SDCMR_MRD 0x003FFE00U /!<MRD[12:0] bits (Mode register definition) /
Kojto	110:165afa46840b	5803
Kojto	110:165afa46840b	5804	/**************** Bit definition for FMC_SDRTR register ****************/
Kojto	122:f9eeca106725	5805	#define FMC_SDRTR_CRE 0x00000001U /!<Clear refresh error flag /
Kojto	122:f9eeca106725	5806
Kojto	122:f9eeca106725	5807	#define FMC_SDRTR_COUNT 0x00003FFEU /!<COUNT[12:0] bits (Refresh timer count) /
Kojto	122:f9eeca106725	5808
Kojto	122:f9eeca106725	5809	#define FMC_SDRTR_REIE 0x00004000U /!<RES interupt enable /
Kojto	110:165afa46840b	5810
Kojto	110:165afa46840b	5811	/**************** Bit definition for FMC_SDSR register ****************/
Kojto	122:f9eeca106725	5812	#define FMC_SDSR_RE 0x00000001U /!<Refresh error flag /
Kojto	122:f9eeca106725	5813
Kojto	122:f9eeca106725	5814	#define FMC_SDSR_MODES1 0x00000006U /!<MODES1[1:0]bits (Status mode for bank 1) /
Kojto	122:f9eeca106725	5815	#define FMC_SDSR_MODES1_0 0x00000002U /!<Bit 0 /
Kojto	122:f9eeca106725	5816	#define FMC_SDSR_MODES1_1 0x00000004U /!<Bit 1 /
Kojto	122:f9eeca106725	5817
Kojto	122:f9eeca106725	5818	#define FMC_SDSR_MODES2 0x00000018U /!<MODES2[1:0]bits (Status mode for bank 2) /
Kojto	122:f9eeca106725	5819	#define FMC_SDSR_MODES2_0 0x00000008U /!<Bit 0 /
Kojto	122:f9eeca106725	5820	#define FMC_SDSR_MODES2_1 0x00000010U /!<Bit 1 /
Kojto	122:f9eeca106725	5821	#define FMC_SDSR_BUSY 0x00000020U /!<Busy status /
Kojto	110:165afa46840b	5822
Kojto	110:165afa46840b	5823	/******************************************************************************/
Kojto	110:165afa46840b	5824	/* */
Kojto	110:165afa46840b	5825	/* General Purpose I/O */
Kojto	110:165afa46840b	5826	/* */
Kojto	110:165afa46840b	5827	/******************************************************************************/
Kojto	110:165afa46840b	5828	/**************** Bits definition for GPIO_MODER register ***************/
Kojto	122:f9eeca106725	5829	#define GPIO_MODER_MODER0 0x00000003U
Kojto	122:f9eeca106725	5830	#define GPIO_MODER_MODER0_0 0x00000001U
Kojto	122:f9eeca106725	5831	#define GPIO_MODER_MODER0_1 0x00000002U
Kojto	122:f9eeca106725	5832
Kojto	122:f9eeca106725	5833	#define GPIO_MODER_MODER1 0x0000000CU
Kojto	122:f9eeca106725	5834	#define GPIO_MODER_MODER1_0 0x00000004U
Kojto	122:f9eeca106725	5835	#define GPIO_MODER_MODER1_1 0x00000008U
Kojto	122:f9eeca106725	5836
Kojto	122:f9eeca106725	5837	#define GPIO_MODER_MODER2 0x00000030U
Kojto	122:f9eeca106725	5838	#define GPIO_MODER_MODER2_0 0x00000010U
Kojto	122:f9eeca106725	5839	#define GPIO_MODER_MODER2_1 0x00000020U
Kojto	122:f9eeca106725	5840
Kojto	122:f9eeca106725	5841	#define GPIO_MODER_MODER3 0x000000C0U
Kojto	122:f9eeca106725	5842	#define GPIO_MODER_MODER3_0 0x00000040U
Kojto	122:f9eeca106725	5843	#define GPIO_MODER_MODER3_1 0x00000080U
Kojto	122:f9eeca106725	5844
Kojto	122:f9eeca106725	5845	#define GPIO_MODER_MODER4 0x00000300U
Kojto	122:f9eeca106725	5846	#define GPIO_MODER_MODER4_0 0x00000100U
Kojto	122:f9eeca106725	5847	#define GPIO_MODER_MODER4_1 0x00000200U
Kojto	122:f9eeca106725	5848
Kojto	122:f9eeca106725	5849	#define GPIO_MODER_MODER5 0x00000C00U
Kojto	122:f9eeca106725	5850	#define GPIO_MODER_MODER5_0 0x00000400U
Kojto	122:f9eeca106725	5851	#define GPIO_MODER_MODER5_1 0x00000800U
Kojto	122:f9eeca106725	5852
Kojto	122:f9eeca106725	5853	#define GPIO_MODER_MODER6 0x00003000U
Kojto	122:f9eeca106725	5854	#define GPIO_MODER_MODER6_0 0x00001000U
Kojto	122:f9eeca106725	5855	#define GPIO_MODER_MODER6_1 0x00002000U
Kojto	122:f9eeca106725	5856
Kojto	122:f9eeca106725	5857	#define GPIO_MODER_MODER7 0x0000C000U
Kojto	122:f9eeca106725	5858	#define GPIO_MODER_MODER7_0 0x00004000U
Kojto	122:f9eeca106725	5859	#define GPIO_MODER_MODER7_1 0x00008000U
Kojto	122:f9eeca106725	5860
Kojto	122:f9eeca106725	5861	#define GPIO_MODER_MODER8 0x00030000U
Kojto	122:f9eeca106725	5862	#define GPIO_MODER_MODER8_0 0x00010000U
Kojto	122:f9eeca106725	5863	#define GPIO_MODER_MODER8_1 0x00020000U
Kojto	122:f9eeca106725	5864
Kojto	122:f9eeca106725	5865	#define GPIO_MODER_MODER9 0x000C0000U
Kojto	122:f9eeca106725	5866	#define GPIO_MODER_MODER9_0 0x00040000U
Kojto	122:f9eeca106725	5867	#define GPIO_MODER_MODER9_1 0x00080000U
Kojto	122:f9eeca106725	5868
Kojto	122:f9eeca106725	5869	#define GPIO_MODER_MODER10 0x00300000U
Kojto	122:f9eeca106725	5870	#define GPIO_MODER_MODER10_0 0x00100000U
Kojto	122:f9eeca106725	5871	#define GPIO_MODER_MODER10_1 0x00200000U
Kojto	122:f9eeca106725	5872
Kojto	122:f9eeca106725	5873	#define GPIO_MODER_MODER11 0x00C00000U
Kojto	122:f9eeca106725	5874	#define GPIO_MODER_MODER11_0 0x00400000U
Kojto	122:f9eeca106725	5875	#define GPIO_MODER_MODER11_1 0x00800000U
Kojto	122:f9eeca106725	5876
Kojto	122:f9eeca106725	5877	#define GPIO_MODER_MODER12 0x03000000U
Kojto	122:f9eeca106725	5878	#define GPIO_MODER_MODER12_0 0x01000000U
Kojto	122:f9eeca106725	5879	#define GPIO_MODER_MODER12_1 0x02000000U
Kojto	122:f9eeca106725	5880
Kojto	122:f9eeca106725	5881	#define GPIO_MODER_MODER13 0x0C000000U
Kojto	122:f9eeca106725	5882	#define GPIO_MODER_MODER13_0 0x04000000U
Kojto	122:f9eeca106725	5883	#define GPIO_MODER_MODER13_1 0x08000000U
Kojto	122:f9eeca106725	5884
Kojto	122:f9eeca106725	5885	#define GPIO_MODER_MODER14 0x30000000U
Kojto	122:f9eeca106725	5886	#define GPIO_MODER_MODER14_0 0x10000000U
Kojto	122:f9eeca106725	5887	#define GPIO_MODER_MODER14_1 0x20000000U
Kojto	122:f9eeca106725	5888
Kojto	122:f9eeca106725	5889	#define GPIO_MODER_MODER15 0xC0000000U
Kojto	122:f9eeca106725	5890	#define GPIO_MODER_MODER15_0 0x40000000U
Kojto	122:f9eeca106725	5891	#define GPIO_MODER_MODER15_1 0x80000000U
Kojto	110:165afa46840b	5892
Kojto	110:165afa46840b	5893	/**************** Bits definition for GPIO_OTYPER register **************/
Kojto	122:f9eeca106725	5894	#define GPIO_OTYPER_OT_0 0x00000001U
Kojto	122:f9eeca106725	5895	#define GPIO_OTYPER_OT_1 0x00000002U
Kojto	122:f9eeca106725	5896	#define GPIO_OTYPER_OT_2 0x00000004U
Kojto	122:f9eeca106725	5897	#define GPIO_OTYPER_OT_3 0x00000008U
Kojto	122:f9eeca106725	5898	#define GPIO_OTYPER_OT_4 0x00000010U
Kojto	122:f9eeca106725	5899	#define GPIO_OTYPER_OT_5 0x00000020U
Kojto	122:f9eeca106725	5900	#define GPIO_OTYPER_OT_6 0x00000040U
Kojto	122:f9eeca106725	5901	#define GPIO_OTYPER_OT_7 0x00000080U
Kojto	122:f9eeca106725	5902	#define GPIO_OTYPER_OT_8 0x00000100U
Kojto	122:f9eeca106725	5903	#define GPIO_OTYPER_OT_9 0x00000200U
Kojto	122:f9eeca106725	5904	#define GPIO_OTYPER_OT_10 0x00000400U
Kojto	122:f9eeca106725	5905	#define GPIO_OTYPER_OT_11 0x00000800U
Kojto	122:f9eeca106725	5906	#define GPIO_OTYPER_OT_12 0x00001000U
Kojto	122:f9eeca106725	5907	#define GPIO_OTYPER_OT_13 0x00002000U
Kojto	122:f9eeca106725	5908	#define GPIO_OTYPER_OT_14 0x00004000U
Kojto	122:f9eeca106725	5909	#define GPIO_OTYPER_OT_15 0x00008000U
Kojto	110:165afa46840b	5910
Kojto	110:165afa46840b	5911	/**************** Bits definition for GPIO_OSPEEDR register *************/
Kojto	122:f9eeca106725	5912	#define GPIO_OSPEEDER_OSPEEDR0 0x00000003U
Kojto	122:f9eeca106725	5913	#define GPIO_OSPEEDER_OSPEEDR0_0 0x00000001U
Kojto	122:f9eeca106725	5914	#define GPIO_OSPEEDER_OSPEEDR0_1 0x00000002U
Kojto	122:f9eeca106725	5915
Kojto	122:f9eeca106725	5916	#define GPIO_OSPEEDER_OSPEEDR1 0x0000000CU
Kojto	122:f9eeca106725	5917	#define GPIO_OSPEEDER_OSPEEDR1_0 0x00000004U
Kojto	122:f9eeca106725	5918	#define GPIO_OSPEEDER_OSPEEDR1_1 0x00000008U
Kojto	122:f9eeca106725	5919
Kojto	122:f9eeca106725	5920	#define GPIO_OSPEEDER_OSPEEDR2 0x00000030U
Kojto	122:f9eeca106725	5921	#define GPIO_OSPEEDER_OSPEEDR2_0 0x00000010U
Kojto	122:f9eeca106725	5922	#define GPIO_OSPEEDER_OSPEEDR2_1 0x00000020U
Kojto	122:f9eeca106725	5923
Kojto	122:f9eeca106725	5924	#define GPIO_OSPEEDER_OSPEEDR3 0x000000C0U
Kojto	122:f9eeca106725	5925	#define GPIO_OSPEEDER_OSPEEDR3_0 0x00000040U
Kojto	122:f9eeca106725	5926	#define GPIO_OSPEEDER_OSPEEDR3_1 0x00000080U
Kojto	122:f9eeca106725	5927
Kojto	122:f9eeca106725	5928	#define GPIO_OSPEEDER_OSPEEDR4 0x00000300U
Kojto	122:f9eeca106725	5929	#define GPIO_OSPEEDER_OSPEEDR4_0 0x00000100U
Kojto	122:f9eeca106725	5930	#define GPIO_OSPEEDER_OSPEEDR4_1 0x00000200U
Kojto	122:f9eeca106725	5931
Kojto	122:f9eeca106725	5932	#define GPIO_OSPEEDER_OSPEEDR5 0x00000C00U
Kojto	122:f9eeca106725	5933	#define GPIO_OSPEEDER_OSPEEDR5_0 0x00000400U
Kojto	122:f9eeca106725	5934	#define GPIO_OSPEEDER_OSPEEDR5_1 0x00000800U
Kojto	122:f9eeca106725	5935
Kojto	122:f9eeca106725	5936	#define GPIO_OSPEEDER_OSPEEDR6 0x00003000U
Kojto	122:f9eeca106725	5937	#define GPIO_OSPEEDER_OSPEEDR6_0 0x00001000U
Kojto	122:f9eeca106725	5938	#define GPIO_OSPEEDER_OSPEEDR6_1 0x00002000U
Kojto	122:f9eeca106725	5939
Kojto	122:f9eeca106725	5940	#define GPIO_OSPEEDER_OSPEEDR7 0x0000C000U
Kojto	122:f9eeca106725	5941	#define GPIO_OSPEEDER_OSPEEDR7_0 0x00004000U
Kojto	122:f9eeca106725	5942	#define GPIO_OSPEEDER_OSPEEDR7_1 0x00008000U
Kojto	122:f9eeca106725	5943
Kojto	122:f9eeca106725	5944	#define GPIO_OSPEEDER_OSPEEDR8 0x00030000U
Kojto	122:f9eeca106725	5945	#define GPIO_OSPEEDER_OSPEEDR8_0 0x00010000U
Kojto	122:f9eeca106725	5946	#define GPIO_OSPEEDER_OSPEEDR8_1 0x00020000U
Kojto	122:f9eeca106725	5947
Kojto	122:f9eeca106725	5948	#define GPIO_OSPEEDER_OSPEEDR9 0x000C0000U
Kojto	122:f9eeca106725	5949	#define GPIO_OSPEEDER_OSPEEDR9_0 0x00040000U
Kojto	122:f9eeca106725	5950	#define GPIO_OSPEEDER_OSPEEDR9_1 0x00080000U
Kojto	122:f9eeca106725	5951
Kojto	122:f9eeca106725	5952	#define GPIO_OSPEEDER_OSPEEDR10 0x00300000U
Kojto	122:f9eeca106725	5953	#define GPIO_OSPEEDER_OSPEEDR10_0 0x00100000U
Kojto	122:f9eeca106725	5954	#define GPIO_OSPEEDER_OSPEEDR10_1 0x00200000U
Kojto	122:f9eeca106725	5955
Kojto	122:f9eeca106725	5956	#define GPIO_OSPEEDER_OSPEEDR11 0x00C00000U
Kojto	122:f9eeca106725	5957	#define GPIO_OSPEEDER_OSPEEDR11_0 0x00400000U
Kojto	122:f9eeca106725	5958	#define GPIO_OSPEEDER_OSPEEDR11_1 0x00800000U
Kojto	122:f9eeca106725	5959
Kojto	122:f9eeca106725	5960	#define GPIO_OSPEEDER_OSPEEDR12 0x03000000U
Kojto	122:f9eeca106725	5961	#define GPIO_OSPEEDER_OSPEEDR12_0 0x01000000U
Kojto	122:f9eeca106725	5962	#define GPIO_OSPEEDER_OSPEEDR12_1 0x02000000U
Kojto	122:f9eeca106725	5963
Kojto	122:f9eeca106725	5964	#define GPIO_OSPEEDER_OSPEEDR13 0x0C000000U
Kojto	122:f9eeca106725	5965	#define GPIO_OSPEEDER_OSPEEDR13_0 0x04000000U
Kojto	122:f9eeca106725	5966	#define GPIO_OSPEEDER_OSPEEDR13_1 0x08000000U
Kojto	122:f9eeca106725	5967
Kojto	122:f9eeca106725	5968	#define GPIO_OSPEEDER_OSPEEDR14 0x30000000U
Kojto	122:f9eeca106725	5969	#define GPIO_OSPEEDER_OSPEEDR14_0 0x10000000U
Kojto	122:f9eeca106725	5970	#define GPIO_OSPEEDER_OSPEEDR14_1 0x20000000U
Kojto	122:f9eeca106725	5971
Kojto	122:f9eeca106725	5972	#define GPIO_OSPEEDER_OSPEEDR15 0xC0000000U
Kojto	122:f9eeca106725	5973	#define GPIO_OSPEEDER_OSPEEDR15_0 0x40000000U
Kojto	122:f9eeca106725	5974	#define GPIO_OSPEEDER_OSPEEDR15_1 0x80000000U
Kojto	110:165afa46840b	5975
Kojto	110:165afa46840b	5976	/**************** Bits definition for GPIO_PUPDR register ***************/
Kojto	122:f9eeca106725	5977	#define GPIO_PUPDR_PUPDR0 0x00000003U
Kojto	122:f9eeca106725	5978	#define GPIO_PUPDR_PUPDR0_0 0x00000001U
Kojto	122:f9eeca106725	5979	#define GPIO_PUPDR_PUPDR0_1 0x00000002U
Kojto	122:f9eeca106725	5980
Kojto	122:f9eeca106725	5981	#define GPIO_PUPDR_PUPDR1 0x0000000CU
Kojto	122:f9eeca106725	5982	#define GPIO_PUPDR_PUPDR1_0 0x00000004U
Kojto	122:f9eeca106725	5983	#define GPIO_PUPDR_PUPDR1_1 0x00000008U
Kojto	122:f9eeca106725	5984
Kojto	122:f9eeca106725	5985	#define GPIO_PUPDR_PUPDR2 0x00000030U
Kojto	122:f9eeca106725	5986	#define GPIO_PUPDR_PUPDR2_0 0x00000010U
Kojto	122:f9eeca106725	5987	#define GPIO_PUPDR_PUPDR2_1 0x00000020U
Kojto	122:f9eeca106725	5988
Kojto	122:f9eeca106725	5989	#define GPIO_PUPDR_PUPDR3 0x000000C0U
Kojto	122:f9eeca106725	5990	#define GPIO_PUPDR_PUPDR3_0 0x00000040U
Kojto	122:f9eeca106725	5991	#define GPIO_PUPDR_PUPDR3_1 0x00000080U
Kojto	122:f9eeca106725	5992
Kojto	122:f9eeca106725	5993	#define GPIO_PUPDR_PUPDR4 0x00000300U
Kojto	122:f9eeca106725	5994	#define GPIO_PUPDR_PUPDR4_0 0x00000100U
Kojto	122:f9eeca106725	5995	#define GPIO_PUPDR_PUPDR4_1 0x00000200U
Kojto	122:f9eeca106725	5996
Kojto	122:f9eeca106725	5997	#define GPIO_PUPDR_PUPDR5 0x00000C00U
Kojto	122:f9eeca106725	5998	#define GPIO_PUPDR_PUPDR5_0 0x00000400U
Kojto	122:f9eeca106725	5999	#define GPIO_PUPDR_PUPDR5_1 0x00000800U
Kojto	122:f9eeca106725	6000
Kojto	122:f9eeca106725	6001	#define GPIO_PUPDR_PUPDR6 0x00003000U
Kojto	122:f9eeca106725	6002	#define GPIO_PUPDR_PUPDR6_0 0x00001000U
Kojto	122:f9eeca106725	6003	#define GPIO_PUPDR_PUPDR6_1 0x00002000U
Kojto	122:f9eeca106725	6004
Kojto	122:f9eeca106725	6005	#define GPIO_PUPDR_PUPDR7 0x0000C000U
Kojto	122:f9eeca106725	6006	#define GPIO_PUPDR_PUPDR7_0 0x00004000U
Kojto	122:f9eeca106725	6007	#define GPIO_PUPDR_PUPDR7_1 0x00008000U
Kojto	122:f9eeca106725	6008
Kojto	122:f9eeca106725	6009	#define GPIO_PUPDR_PUPDR8 0x00030000U
Kojto	122:f9eeca106725	6010	#define GPIO_PUPDR_PUPDR8_0 0x00010000U
Kojto	122:f9eeca106725	6011	#define GPIO_PUPDR_PUPDR8_1 0x00020000U
Kojto	122:f9eeca106725	6012
Kojto	122:f9eeca106725	6013	#define GPIO_PUPDR_PUPDR9 0x000C0000U
Kojto	122:f9eeca106725	6014	#define GPIO_PUPDR_PUPDR9_0 0x00040000U
Kojto	122:f9eeca106725	6015	#define GPIO_PUPDR_PUPDR9_1 0x00080000U
Kojto	122:f9eeca106725	6016
Kojto	122:f9eeca106725	6017	#define GPIO_PUPDR_PUPDR10 0x00300000U
Kojto	122:f9eeca106725	6018	#define GPIO_PUPDR_PUPDR10_0 0x00100000U
Kojto	122:f9eeca106725	6019	#define GPIO_PUPDR_PUPDR10_1 0x00200000U
Kojto	122:f9eeca106725	6020
Kojto	122:f9eeca106725	6021	#define GPIO_PUPDR_PUPDR11 0x00C00000U
Kojto	122:f9eeca106725	6022	#define GPIO_PUPDR_PUPDR11_0 0x00400000U
Kojto	122:f9eeca106725	6023	#define GPIO_PUPDR_PUPDR11_1 0x00800000U
Kojto	122:f9eeca106725	6024
Kojto	122:f9eeca106725	6025	#define GPIO_PUPDR_PUPDR12 0x03000000U
Kojto	122:f9eeca106725	6026	#define GPIO_PUPDR_PUPDR12_0 0x01000000U
Kojto	122:f9eeca106725	6027	#define GPIO_PUPDR_PUPDR12_1 0x02000000U
Kojto	122:f9eeca106725	6028
Kojto	122:f9eeca106725	6029	#define GPIO_PUPDR_PUPDR13 0x0C000000U
Kojto	122:f9eeca106725	6030	#define GPIO_PUPDR_PUPDR13_0 0x04000000U
Kojto	122:f9eeca106725	6031	#define GPIO_PUPDR_PUPDR13_1 0x08000000U
Kojto	122:f9eeca106725	6032
Kojto	122:f9eeca106725	6033	#define GPIO_PUPDR_PUPDR14 0x30000000U
Kojto	122:f9eeca106725	6034	#define GPIO_PUPDR_PUPDR14_0 0x10000000U
Kojto	122:f9eeca106725	6035	#define GPIO_PUPDR_PUPDR14_1 0x20000000U
Kojto	122:f9eeca106725	6036
Kojto	122:f9eeca106725	6037	#define GPIO_PUPDR_PUPDR15 0xC0000000U
Kojto	122:f9eeca106725	6038	#define GPIO_PUPDR_PUPDR15_0 0x40000000U
Kojto	122:f9eeca106725	6039	#define GPIO_PUPDR_PUPDR15_1 0x80000000U
Kojto	110:165afa46840b	6040
Kojto	110:165afa46840b	6041	/**************** Bits definition for GPIO_IDR register *****************/
Kojto	122:f9eeca106725	6042	#define GPIO_IDR_IDR_0 0x00000001U
Kojto	122:f9eeca106725	6043	#define GPIO_IDR_IDR_1 0x00000002U
Kojto	122:f9eeca106725	6044	#define GPIO_IDR_IDR_2 0x00000004U
Kojto	122:f9eeca106725	6045	#define GPIO_IDR_IDR_3 0x00000008U
Kojto	122:f9eeca106725	6046	#define GPIO_IDR_IDR_4 0x00000010U
Kojto	122:f9eeca106725	6047	#define GPIO_IDR_IDR_5 0x00000020U
Kojto	122:f9eeca106725	6048	#define GPIO_IDR_IDR_6 0x00000040U
Kojto	122:f9eeca106725	6049	#define GPIO_IDR_IDR_7 0x00000080U
Kojto	122:f9eeca106725	6050	#define GPIO_IDR_IDR_8 0x00000100U
Kojto	122:f9eeca106725	6051	#define GPIO_IDR_IDR_9 0x00000200U
Kojto	122:f9eeca106725	6052	#define GPIO_IDR_IDR_10 0x00000400U
Kojto	122:f9eeca106725	6053	#define GPIO_IDR_IDR_11 0x00000800U
Kojto	122:f9eeca106725	6054	#define GPIO_IDR_IDR_12 0x00001000U
Kojto	122:f9eeca106725	6055	#define GPIO_IDR_IDR_13 0x00002000U
Kojto	122:f9eeca106725	6056	#define GPIO_IDR_IDR_14 0x00004000U
Kojto	122:f9eeca106725	6057	#define GPIO_IDR_IDR_15 0x00008000U
Kojto	110:165afa46840b	6058	/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
Kojto	110:165afa46840b	6059	#define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
Kojto	110:165afa46840b	6060	#define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
Kojto	110:165afa46840b	6061	#define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
Kojto	110:165afa46840b	6062	#define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
Kojto	110:165afa46840b	6063	#define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
Kojto	110:165afa46840b	6064	#define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
Kojto	110:165afa46840b	6065	#define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
Kojto	110:165afa46840b	6066	#define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
Kojto	110:165afa46840b	6067	#define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
Kojto	110:165afa46840b	6068	#define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
Kojto	110:165afa46840b	6069	#define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
Kojto	110:165afa46840b	6070	#define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
Kojto	110:165afa46840b	6071	#define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
Kojto	110:165afa46840b	6072	#define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
Kojto	110:165afa46840b	6073	#define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
Kojto	110:165afa46840b	6074	#define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
Kojto	110:165afa46840b	6075
Kojto	110:165afa46840b	6076	/**************** Bits definition for GPIO_ODR register *****************/
Kojto	122:f9eeca106725	6077	#define GPIO_ODR_ODR_0 0x00000001U
Kojto	122:f9eeca106725	6078	#define GPIO_ODR_ODR_1 0x00000002U
Kojto	122:f9eeca106725	6079	#define GPIO_ODR_ODR_2 0x00000004U
Kojto	122:f9eeca106725	6080	#define GPIO_ODR_ODR_3 0x00000008U
Kojto	122:f9eeca106725	6081	#define GPIO_ODR_ODR_4 0x00000010U
Kojto	122:f9eeca106725	6082	#define GPIO_ODR_ODR_5 0x00000020U
Kojto	122:f9eeca106725	6083	#define GPIO_ODR_ODR_6 0x00000040U
Kojto	122:f9eeca106725	6084	#define GPIO_ODR_ODR_7 0x00000080U
Kojto	122:f9eeca106725	6085	#define GPIO_ODR_ODR_8 0x00000100U
Kojto	122:f9eeca106725	6086	#define GPIO_ODR_ODR_9 0x00000200U
Kojto	122:f9eeca106725	6087	#define GPIO_ODR_ODR_10 0x00000400U
Kojto	122:f9eeca106725	6088	#define GPIO_ODR_ODR_11 0x00000800U
Kojto	122:f9eeca106725	6089	#define GPIO_ODR_ODR_12 0x00001000U
Kojto	122:f9eeca106725	6090	#define GPIO_ODR_ODR_13 0x00002000U
Kojto	122:f9eeca106725	6091	#define GPIO_ODR_ODR_14 0x00004000U
Kojto	122:f9eeca106725	6092	#define GPIO_ODR_ODR_15 0x00008000U
Kojto	110:165afa46840b	6093	/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
Kojto	110:165afa46840b	6094	#define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
Kojto	110:165afa46840b	6095	#define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
Kojto	110:165afa46840b	6096	#define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
Kojto	110:165afa46840b	6097	#define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
Kojto	110:165afa46840b	6098	#define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
Kojto	110:165afa46840b	6099	#define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
Kojto	110:165afa46840b	6100	#define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
Kojto	110:165afa46840b	6101	#define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
Kojto	110:165afa46840b	6102	#define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
Kojto	110:165afa46840b	6103	#define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
Kojto	110:165afa46840b	6104	#define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
Kojto	110:165afa46840b	6105	#define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
Kojto	110:165afa46840b	6106	#define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
Kojto	110:165afa46840b	6107	#define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
Kojto	110:165afa46840b	6108	#define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
Kojto	110:165afa46840b	6109	#define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
Kojto	110:165afa46840b	6110
Kojto	110:165afa46840b	6111	/**************** Bits definition for GPIO_BSRR register ****************/
Kojto	122:f9eeca106725	6112	#define GPIO_BSRR_BS_0 0x00000001U
Kojto	122:f9eeca106725	6113	#define GPIO_BSRR_BS_1 0x00000002U
Kojto	122:f9eeca106725	6114	#define GPIO_BSRR_BS_2 0x00000004U
Kojto	122:f9eeca106725	6115	#define GPIO_BSRR_BS_3 0x00000008U
Kojto	122:f9eeca106725	6116	#define GPIO_BSRR_BS_4 0x00000010U
Kojto	122:f9eeca106725	6117	#define GPIO_BSRR_BS_5 0x00000020U
Kojto	122:f9eeca106725	6118	#define GPIO_BSRR_BS_6 0x00000040U
Kojto	122:f9eeca106725	6119	#define GPIO_BSRR_BS_7 0x00000080U
Kojto	122:f9eeca106725	6120	#define GPIO_BSRR_BS_8 0x00000100U
Kojto	122:f9eeca106725	6121	#define GPIO_BSRR_BS_9 0x00000200U
Kojto	122:f9eeca106725	6122	#define GPIO_BSRR_BS_10 0x00000400U
Kojto	122:f9eeca106725	6123	#define GPIO_BSRR_BS_11 0x00000800U
Kojto	122:f9eeca106725	6124	#define GPIO_BSRR_BS_12 0x00001000U
Kojto	122:f9eeca106725	6125	#define GPIO_BSRR_BS_13 0x00002000U
Kojto	122:f9eeca106725	6126	#define GPIO_BSRR_BS_14 0x00004000U
Kojto	122:f9eeca106725	6127	#define GPIO_BSRR_BS_15 0x00008000U
Kojto	122:f9eeca106725	6128	#define GPIO_BSRR_BR_0 0x00010000U
Kojto	122:f9eeca106725	6129	#define GPIO_BSRR_BR_1 0x00020000U
Kojto	122:f9eeca106725	6130	#define GPIO_BSRR_BR_2 0x00040000U
Kojto	122:f9eeca106725	6131	#define GPIO_BSRR_BR_3 0x00080000U
Kojto	122:f9eeca106725	6132	#define GPIO_BSRR_BR_4 0x00100000U
Kojto	122:f9eeca106725	6133	#define GPIO_BSRR_BR_5 0x00200000U
Kojto	122:f9eeca106725	6134	#define GPIO_BSRR_BR_6 0x00400000U
Kojto	122:f9eeca106725	6135	#define GPIO_BSRR_BR_7 0x00800000U
Kojto	122:f9eeca106725	6136	#define GPIO_BSRR_BR_8 0x01000000U
Kojto	122:f9eeca106725	6137	#define GPIO_BSRR_BR_9 0x02000000U
Kojto	122:f9eeca106725	6138	#define GPIO_BSRR_BR_10 0x04000000U
Kojto	122:f9eeca106725	6139	#define GPIO_BSRR_BR_11 0x08000000U
Kojto	122:f9eeca106725	6140	#define GPIO_BSRR_BR_12 0x10000000U
Kojto	122:f9eeca106725	6141	#define GPIO_BSRR_BR_13 0x20000000U
Kojto	122:f9eeca106725	6142	#define GPIO_BSRR_BR_14 0x40000000U
Kojto	122:f9eeca106725	6143	#define GPIO_BSRR_BR_15 0x80000000U
Kojto	110:165afa46840b	6144
Kojto	110:165afa46840b	6145	/**************** Bit definition for GPIO_LCKR register *******************/
Kojto	122:f9eeca106725	6146	#define GPIO_LCKR_LCK0 0x00000001U
Kojto	122:f9eeca106725	6147	#define GPIO_LCKR_LCK1 0x00000002U
Kojto	122:f9eeca106725	6148	#define GPIO_LCKR_LCK2 0x00000004U
Kojto	122:f9eeca106725	6149	#define GPIO_LCKR_LCK3 0x00000008U
Kojto	122:f9eeca106725	6150	#define GPIO_LCKR_LCK4 0x00000010U
Kojto	122:f9eeca106725	6151	#define GPIO_LCKR_LCK5 0x00000020U
Kojto	122:f9eeca106725	6152	#define GPIO_LCKR_LCK6 0x00000040U
Kojto	122:f9eeca106725	6153	#define GPIO_LCKR_LCK7 0x00000080U
Kojto	122:f9eeca106725	6154	#define GPIO_LCKR_LCK8 0x00000100U
Kojto	122:f9eeca106725	6155	#define GPIO_LCKR_LCK9 0x00000200U
Kojto	122:f9eeca106725	6156	#define GPIO_LCKR_LCK10 0x00000400U
Kojto	122:f9eeca106725	6157	#define GPIO_LCKR_LCK11 0x00000800U
Kojto	122:f9eeca106725	6158	#define GPIO_LCKR_LCK12 0x00001000U
Kojto	122:f9eeca106725	6159	#define GPIO_LCKR_LCK13 0x00002000U
Kojto	122:f9eeca106725	6160	#define GPIO_LCKR_LCK14 0x00004000U
Kojto	122:f9eeca106725	6161	#define GPIO_LCKR_LCK15 0x00008000U
Kojto	122:f9eeca106725	6162	#define GPIO_LCKR_LCKK 0x00010000U
Kojto	110:165afa46840b	6163
Kojto	110:165afa46840b	6164	/******************************************************************************/
Kojto	110:165afa46840b	6165	/* */
Kojto	110:165afa46840b	6166	/* Inter-integrated Circuit Interface */
Kojto	110:165afa46840b	6167	/* */
Kojto	110:165afa46840b	6168	/******************************************************************************/
Kojto	110:165afa46840b	6169	/***************** Bit definition for I2C_CR1 register ******************/
Kojto	122:f9eeca106725	6170	#define I2C_CR1_PE 0x00000001U /!<Peripheral Enable /
Kojto	122:f9eeca106725	6171	#define I2C_CR1_SMBUS 0x00000002U /!<SMBus Mode /
Kojto	122:f9eeca106725	6172	#define I2C_CR1_SMBTYPE 0x00000008U /!<SMBus Type /
Kojto	122:f9eeca106725	6173	#define I2C_CR1_ENARP 0x00000010U /!<ARP Enable /
Kojto	122:f9eeca106725	6174	#define I2C_CR1_ENPEC 0x00000020U /!<PEC Enable /
Kojto	122:f9eeca106725	6175	#define I2C_CR1_ENGC 0x00000040U /!<General Call Enable /
Kojto	122:f9eeca106725	6176	#define I2C_CR1_NOSTRETCH 0x00000080U /!<Clock Stretching Disable (Slave mode) /
Kojto	122:f9eeca106725	6177	#define I2C_CR1_START 0x00000100U /!<Start Generation /
Kojto	122:f9eeca106725	6178	#define I2C_CR1_STOP 0x00000200U /!<Stop Generation /
Kojto	122:f9eeca106725	6179	#define I2C_CR1_ACK 0x00000400U /!<Acknowledge Enable /
Kojto	122:f9eeca106725	6180	#define I2C_CR1_POS 0x00000800U /!<Acknowledge/PEC Position (for data reception) /
Kojto	122:f9eeca106725	6181	#define I2C_CR1_PEC 0x00001000U /!<Packet Error Checking /
Kojto	122:f9eeca106725	6182	#define I2C_CR1_ALERT 0x00002000U /!<SMBus Alert /
Kojto	122:f9eeca106725	6183	#define I2C_CR1_SWRST 0x00008000U /!<Software Reset /
Kojto	110:165afa46840b	6184
Kojto	110:165afa46840b	6185	/***************** Bit definition for I2C_CR2 register ******************/
Kojto	122:f9eeca106725	6186	#define I2C_CR2_FREQ 0x0000003FU /!<FREQ[5:0] bits (Peripheral Clock Frequency) /
Kojto	122:f9eeca106725	6187	#define I2C_CR2_FREQ_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	6188	#define I2C_CR2_FREQ_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	6189	#define I2C_CR2_FREQ_2 0x00000004U /!<Bit 2 /
Kojto	122:f9eeca106725	6190	#define I2C_CR2_FREQ_3 0x00000008U /!<Bit 3 /
Kojto	122:f9eeca106725	6191	#define I2C_CR2_FREQ_4 0x00000010U /!<Bit 4 /
Kojto	122:f9eeca106725	6192	#define I2C_CR2_FREQ_5 0x00000020U /!<Bit 5 /
Kojto	122:f9eeca106725	6193
Kojto	122:f9eeca106725	6194	#define I2C_CR2_ITERREN 0x00000100U /!<Error Interrupt Enable /
Kojto	122:f9eeca106725	6195	#define I2C_CR2_ITEVTEN 0x00000200U /!<Event Interrupt Enable /
Kojto	122:f9eeca106725	6196	#define I2C_CR2_ITBUFEN 0x00000400U /!<Buffer Interrupt Enable /
Kojto	122:f9eeca106725	6197	#define I2C_CR2_DMAEN 0x00000800U /!<DMA Requests Enable /
Kojto	122:f9eeca106725	6198	#define I2C_CR2_LAST 0x00001000U /!<DMA Last Transfer /
Kojto	110:165afa46840b	6199
Kojto	110:165afa46840b	6200	/***************** Bit definition for I2C_OAR1 register *****************/
Kojto	122:f9eeca106725	6201	#define I2C_OAR1_ADD1_7 0x000000FEU /!<Interface Address /
Kojto	122:f9eeca106725	6202	#define I2C_OAR1_ADD8_9 0x00000300U /!<Interface Address /
Kojto	122:f9eeca106725	6203
Kojto	122:f9eeca106725	6204	#define I2C_OAR1_ADD0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	6205	#define I2C_OAR1_ADD1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	6206	#define I2C_OAR1_ADD2 0x00000004U /!<Bit 2 /
Kojto	122:f9eeca106725	6207	#define I2C_OAR1_ADD3 0x00000008U /!<Bit 3 /
Kojto	122:f9eeca106725	6208	#define I2C_OAR1_ADD4 0x00000010U /!<Bit 4 /
Kojto	122:f9eeca106725	6209	#define I2C_OAR1_ADD5 0x00000020U /!<Bit 5 /
Kojto	122:f9eeca106725	6210	#define I2C_OAR1_ADD6 0x00000040U /!<Bit 6 /
Kojto	122:f9eeca106725	6211	#define I2C_OAR1_ADD7 0x00000080U /!<Bit 7 /
Kojto	122:f9eeca106725	6212	#define I2C_OAR1_ADD8 0x00000100U /!<Bit 8 /
Kojto	122:f9eeca106725	6213	#define I2C_OAR1_ADD9 0x00000200U /!<Bit 9 /
Kojto	122:f9eeca106725	6214
Kojto	122:f9eeca106725	6215	#define I2C_OAR1_ADDMODE 0x00008000U /!<Addressing Mode (Slave mode) /
Kojto	110:165afa46840b	6216
Kojto	110:165afa46840b	6217	/***************** Bit definition for I2C_OAR2 register *****************/
Kojto	122:f9eeca106725	6218	#define I2C_OAR2_ENDUAL 0x00000001U /!<Dual addressing mode enable /
Kojto	122:f9eeca106725	6219	#define I2C_OAR2_ADD2 0x000000FEU /!<Interface address /
Kojto	110:165afa46840b	6220
Kojto	110:165afa46840b	6221	/****************** Bit definition for I2C_DR register ******************/
Kojto	122:f9eeca106725	6222	#define I2C_DR_DR 0x000000FFU /!<8-bit Data Register /
Kojto	110:165afa46840b	6223
Kojto	110:165afa46840b	6224	/***************** Bit definition for I2C_SR1 register ******************/
Kojto	122:f9eeca106725	6225	#define I2C_SR1_SB 0x00000001U /!<Start Bit (Master mode) /
Kojto	122:f9eeca106725	6226	#define I2C_SR1_ADDR 0x00000002U /!<Address sent (master mode)/matched (slave mode) /
Kojto	122:f9eeca106725	6227	#define I2C_SR1_BTF 0x00000004U /!<Byte Transfer Finished /
Kojto	122:f9eeca106725	6228	#define I2C_SR1_ADD10 0x00000008U /!<10-bit header sent (Master mode) /
Kojto	122:f9eeca106725	6229	#define I2C_SR1_STOPF 0x00000010U /!<Stop detection (Slave mode) /
Kojto	122:f9eeca106725	6230	#define I2C_SR1_RXNE 0x00000040U /!<Data Register not Empty (receivers) /
Kojto	122:f9eeca106725	6231	#define I2C_SR1_TXE 0x00000080U /!<Data Register Empty (transmitters) /
Kojto	122:f9eeca106725	6232	#define I2C_SR1_BERR 0x00000100U /!<Bus Error /
Kojto	122:f9eeca106725	6233	#define I2C_SR1_ARLO 0x00000200U /!<Arbitration Lost (master mode) /
Kojto	122:f9eeca106725	6234	#define I2C_SR1_AF 0x00000400U /!<Acknowledge Failure /
Kojto	122:f9eeca106725	6235	#define I2C_SR1_OVR 0x00000800U /!<Overrun/Underrun /
Kojto	122:f9eeca106725	6236	#define I2C_SR1_PECERR 0x00001000U /!<PEC Error in reception /
Kojto	122:f9eeca106725	6237	#define I2C_SR1_TIMEOUT 0x00004000U /!<Timeout or Tlow Error /
Kojto	122:f9eeca106725	6238	#define I2C_SR1_SMBALERT 0x00008000U /!<SMBus Alert /
Kojto	110:165afa46840b	6239
Kojto	110:165afa46840b	6240	/***************** Bit definition for I2C_SR2 register ******************/
Kojto	122:f9eeca106725	6241	#define I2C_SR2_MSL 0x00000001U /!<Master/Slave /
Kojto	122:f9eeca106725	6242	#define I2C_SR2_BUSY 0x00000002U /!<Bus Busy /
Kojto	122:f9eeca106725	6243	#define I2C_SR2_TRA 0x00000004U /!<Transmitter/Receiver /
Kojto	122:f9eeca106725	6244	#define I2C_SR2_GENCALL 0x00000010U /!<General Call Address (Slave mode) /
Kojto	122:f9eeca106725	6245	#define I2C_SR2_SMBDEFAULT 0x00000020U /!<SMBus Device Default Address (Slave mode) /
Kojto	122:f9eeca106725	6246	#define I2C_SR2_SMBHOST 0x00000040U /!<SMBus Host Header (Slave mode) /
Kojto	122:f9eeca106725	6247	#define I2C_SR2_DUALF 0x00000080U /!<Dual Flag (Slave mode) /
Kojto	122:f9eeca106725	6248	#define I2C_SR2_PEC 0x0000FF00U /!<Packet Error Checking Register /
Kojto	110:165afa46840b	6249
Kojto	110:165afa46840b	6250	/***************** Bit definition for I2C_CCR register ******************/
Kojto	122:f9eeca106725	6251	#define I2C_CCR_CCR 0x00000FFFU /!<Clock Control Register in Fast/Standard mode (Master mode) /
Kojto	122:f9eeca106725	6252	#define I2C_CCR_DUTY 0x00004000U /!<Fast Mode Duty Cycle /
Kojto	122:f9eeca106725	6253	#define I2C_CCR_FS 0x00008000U /!<I2C Master Mode Selection /
Kojto	110:165afa46840b	6254
Kojto	110:165afa46840b	6255	/**************** Bit definition for I2C_TRISE register *****************/
Kojto	122:f9eeca106725	6256	#define I2C_TRISE_TRISE 0x0000003FU /!<Maximum Rise Time in Fast/Standard mode (Master mode) /
Kojto	110:165afa46840b	6257
Kojto	110:165afa46840b	6258	/**************** Bit definition for I2C_FLTR register *****************/
Kojto	122:f9eeca106725	6259	#define I2C_FLTR_DNF 0x0000000FU /!<Digital Noise Filter /
Kojto	122:f9eeca106725	6260	#define I2C_FLTR_ANOFF 0x00000010U /!<Analog Noise Filter OFF /
Kojto	110:165afa46840b	6261
Kojto	110:165afa46840b	6262	/******************************************************************************/
Kojto	110:165afa46840b	6263	/* */
Kojto	110:165afa46840b	6264	/* Independent WATCHDOG */
Kojto	110:165afa46840b	6265	/* */
Kojto	110:165afa46840b	6266	/******************************************************************************/
Kojto	110:165afa46840b	6267	/***************** Bit definition for IWDG_KR register ******************/
Kojto	122:f9eeca106725	6268	#define IWDG_KR_KEY 0xFFFFU /!<Key value (write only, read 0000h) /
Kojto	110:165afa46840b	6269
Kojto	110:165afa46840b	6270	/***************** Bit definition for IWDG_PR register ******************/
Kojto	122:f9eeca106725	6271	#define IWDG_PR_PR 0x07U /!<PR[2:0] (Prescaler divider) /
Kojto	122:f9eeca106725	6272	#define IWDG_PR_PR_0 0x01U /!<Bit 0 /
Kojto	122:f9eeca106725	6273	#define IWDG_PR_PR_1 0x02U /!<Bit 1 /
Kojto	122:f9eeca106725	6274	#define IWDG_PR_PR_2 0x04U /!<Bit 2 /
Kojto	110:165afa46840b	6275
Kojto	110:165afa46840b	6276	/***************** Bit definition for IWDG_RLR register *****************/
Kojto	122:f9eeca106725	6277	#define IWDG_RLR_RL 0x0FFFU /!<Watchdog counter reload value /
Kojto	110:165afa46840b	6278
Kojto	110:165afa46840b	6279	/***************** Bit definition for IWDG_SR register ******************/
Kojto	122:f9eeca106725	6280	#define IWDG_SR_PVU 0x01U /!<Watchdog prescaler value update /
Kojto	122:f9eeca106725	6281	#define IWDG_SR_RVU 0x02U /!<Watchdog counter reload value update /
Kojto	110:165afa46840b	6282
Kojto	110:165afa46840b	6283
Kojto	110:165afa46840b	6284	/******************************************************************************/
Kojto	110:165afa46840b	6285	/* */
Kojto	110:165afa46840b	6286	/* LCD-TFT Display Controller (LTDC) */
Kojto	110:165afa46840b	6287	/* */
Kojto	110:165afa46840b	6288	/******************************************************************************/
Kojto	110:165afa46840b	6289
Kojto	110:165afa46840b	6290	/****************** Bit definition for LTDC_SSCR register ***************/
Kojto	110:165afa46840b	6291
Kojto	122:f9eeca106725	6292	#define LTDC_SSCR_VSH 0x000007FFU /!< Vertical Synchronization Height /
Kojto	122:f9eeca106725	6293	#define LTDC_SSCR_HSW 0x0FFF0000U /!< Horizontal Synchronization Width /
Kojto	110:165afa46840b	6294
Kojto	110:165afa46840b	6295	/****************** Bit definition for LTDC_BPCR register ***************/
Kojto	110:165afa46840b	6296
Kojto	122:f9eeca106725	6297	#define LTDC_BPCR_AVBP 0x000007FFU /!< Accumulated Vertical Back Porch /
Kojto	122:f9eeca106725	6298	#define LTDC_BPCR_AHBP 0x0FFF0000U /!< Accumulated Horizontal Back Porch /
Kojto	110:165afa46840b	6299
Kojto	110:165afa46840b	6300	/****************** Bit definition for LTDC_AWCR register ***************/
Kojto	110:165afa46840b	6301
Kojto	122:f9eeca106725	6302	#define LTDC_AWCR_AAH 0x000007FFU /!< Accumulated Active heigh /
Kojto	122:f9eeca106725	6303	#define LTDC_AWCR_AAW 0x0FFF0000U /!< Accumulated Active Width /
Kojto	110:165afa46840b	6304
Kojto	110:165afa46840b	6305	/****************** Bit definition for LTDC_TWCR register ***************/
Kojto	110:165afa46840b	6306
Kojto	122:f9eeca106725	6307	#define LTDC_TWCR_TOTALH 0x000007FFU /!< Total Heigh /
Kojto	122:f9eeca106725	6308	#define LTDC_TWCR_TOTALW 0x0FFF0000U /!< Total Width /
Kojto	110:165afa46840b	6309
Kojto	110:165afa46840b	6310	/****************** Bit definition for LTDC_GCR register ****************/
Kojto	110:165afa46840b	6311
Kojto	122:f9eeca106725	6312	#define LTDC_GCR_LTDCEN 0x00000001U /!< LCD-TFT controller enable bit /
Kojto	122:f9eeca106725	6313	#define LTDC_GCR_DBW 0x00000070U /!< Dither Blue Width /
Kojto	122:f9eeca106725	6314	#define LTDC_GCR_DGW 0x00000700U /!< Dither Green Width /
Kojto	122:f9eeca106725	6315	#define LTDC_GCR_DRW 0x00007000U /!< Dither Red Width /
Kojto	122:f9eeca106725	6316	#define LTDC_GCR_DEN 0x00010000U /!< Dither Enable /
Kojto	122:f9eeca106725	6317	#define LTDC_GCR_PCPOL 0x10000000U /!< Pixel Clock Polarity /
Kojto	122:f9eeca106725	6318	#define LTDC_GCR_DEPOL 0x20000000U /!< Data Enable Polarity /
Kojto	122:f9eeca106725	6319	#define LTDC_GCR_VSPOL 0x40000000U /!< Vertical Synchronization Polarity /
Kojto	122:f9eeca106725	6320	#define LTDC_GCR_HSPOL 0x80000000U /!< Horizontal Synchronization Polarity /
Kojto	122:f9eeca106725	6321
Kojto	122:f9eeca106725	6322	/* Legacy defines */
Kojto	122:f9eeca106725	6323	#define LTDC_GCR_DTEN LTDC_GCR_DEN
Kojto	110:165afa46840b	6324
Kojto	110:165afa46840b	6325	/****************** Bit definition for LTDC_SRCR register ***************/
Kojto	110:165afa46840b	6326
Kojto	122:f9eeca106725	6327	#define LTDC_SRCR_IMR 0x00000001U /!< Immediate Reload /
Kojto	122:f9eeca106725	6328	#define LTDC_SRCR_VBR 0x00000002U /!< Vertical Blanking Reload /
Kojto	110:165afa46840b	6329
Kojto	110:165afa46840b	6330	/****************** Bit definition for LTDC_BCCR register ***************/
Kojto	110:165afa46840b	6331
Kojto	122:f9eeca106725	6332	#define LTDC_BCCR_BCBLUE 0x000000FFU /!< Background Blue value /
Kojto	122:f9eeca106725	6333	#define LTDC_BCCR_BCGREEN 0x0000FF00U /!< Background Green value /
Kojto	122:f9eeca106725	6334	#define LTDC_BCCR_BCRED 0x00FF0000U /!< Background Red value /
Kojto	110:165afa46840b	6335
Kojto	110:165afa46840b	6336	/****************** Bit definition for LTDC_IER register ****************/
Kojto	110:165afa46840b	6337
Kojto	122:f9eeca106725	6338	#define LTDC_IER_LIE 0x00000001U /!< Line Interrupt Enable /
Kojto	122:f9eeca106725	6339	#define LTDC_IER_FUIE 0x00000002U /!< FIFO Underrun Interrupt Enable /
Kojto	122:f9eeca106725	6340	#define LTDC_IER_TERRIE 0x00000004U /!< Transfer Error Interrupt Enable /
Kojto	122:f9eeca106725	6341	#define LTDC_IER_RRIE 0x00000008U /!< Register Reload interrupt enable /
Kojto	110:165afa46840b	6342
Kojto	110:165afa46840b	6343	/****************** Bit definition for LTDC_ISR register ****************/
Kojto	110:165afa46840b	6344
Kojto	122:f9eeca106725	6345	#define LTDC_ISR_LIF 0x00000001U /!< Line Interrupt Flag /
Kojto	122:f9eeca106725	6346	#define LTDC_ISR_FUIF 0x00000002U /!< FIFO Underrun Interrupt Flag /
Kojto	122:f9eeca106725	6347	#define LTDC_ISR_TERRIF 0x00000004U /!< Transfer Error Interrupt Flag /
Kojto	122:f9eeca106725	6348	#define LTDC_ISR_RRIF 0x00000008U /!< Register Reload interrupt Flag /
Kojto	110:165afa46840b	6349
Kojto	110:165afa46840b	6350	/****************** Bit definition for LTDC_ICR register ****************/
Kojto	110:165afa46840b	6351
Kojto	122:f9eeca106725	6352	#define LTDC_ICR_CLIF 0x00000001U /!< Clears the Line Interrupt Flag /
Kojto	122:f9eeca106725	6353	#define LTDC_ICR_CFUIF 0x00000002U /!< Clears the FIFO Underrun Interrupt Flag /
Kojto	122:f9eeca106725	6354	#define LTDC_ICR_CTERRIF 0x00000004U /!< Clears the Transfer Error Interrupt Flag /
Kojto	122:f9eeca106725	6355	#define LTDC_ICR_CRRIF 0x00000008U /!< Clears Register Reload interrupt Flag /
Kojto	110:165afa46840b	6356
Kojto	110:165afa46840b	6357	/****************** Bit definition for LTDC_LIPCR register **************/
Kojto	110:165afa46840b	6358
Kojto	122:f9eeca106725	6359	#define LTDC_LIPCR_LIPOS 0x000007FFU /!< Line Interrupt Position /
Kojto	110:165afa46840b	6360
Kojto	110:165afa46840b	6361	/****************** Bit definition for LTDC_CPSR register ***************/
Kojto	110:165afa46840b	6362
Kojto	122:f9eeca106725	6363	#define LTDC_CPSR_CYPOS 0x0000FFFFU /!< Current Y Position /
Kojto	122:f9eeca106725	6364	#define LTDC_CPSR_CXPOS 0xFFFF0000U /!< Current X Position /
Kojto	110:165afa46840b	6365
Kojto	110:165afa46840b	6366	/****************** Bit definition for LTDC_CDSR register ***************/
Kojto	110:165afa46840b	6367
Kojto	122:f9eeca106725	6368	#define LTDC_CDSR_VDES 0x00000001U /!< Vertical Data Enable Status /
Kojto	122:f9eeca106725	6369	#define LTDC_CDSR_HDES 0x00000002U /!< Horizontal Data Enable Status /
Kojto	122:f9eeca106725	6370	#define LTDC_CDSR_VSYNCS 0x00000004U /!< Vertical Synchronization Status /
Kojto	122:f9eeca106725	6371	#define LTDC_CDSR_HSYNCS 0x00000008U /!< Horizontal Synchronization Status /
Kojto	110:165afa46840b	6372
Kojto	110:165afa46840b	6373	/****************** Bit definition for LTDC_LxCR register ***************/
Kojto	110:165afa46840b	6374
Kojto	122:f9eeca106725	6375	#define LTDC_LxCR_LEN 0x00000001U /!< Layer Enable /
Kojto	122:f9eeca106725	6376	#define LTDC_LxCR_COLKEN 0x00000002U /!< Color Keying Enable /
Kojto	122:f9eeca106725	6377	#define LTDC_LxCR_CLUTEN 0x00000010U /!< Color Lockup Table Enable /
Kojto	110:165afa46840b	6378
Kojto	110:165afa46840b	6379	/****************** Bit definition for LTDC_LxWHPCR register ************/
Kojto	110:165afa46840b	6380
Kojto	122:f9eeca106725	6381	#define LTDC_LxWHPCR_WHSTPOS 0x00000FFFU /!< Window Horizontal Start Position /
Kojto	122:f9eeca106725	6382	#define LTDC_LxWHPCR_WHSPPOS 0xFFFF0000U /!< Window Horizontal Stop Position /
Kojto	110:165afa46840b	6383
Kojto	110:165afa46840b	6384	/****************** Bit definition for LTDC_LxWVPCR register ************/
Kojto	110:165afa46840b	6385
Kojto	122:f9eeca106725	6386	#define LTDC_LxWVPCR_WVSTPOS 0x00000FFFU /!< Window Vertical Start Position /
Kojto	122:f9eeca106725	6387	#define LTDC_LxWVPCR_WVSPPOS 0xFFFF0000U /!< Window Vertical Stop Position /
Kojto	110:165afa46840b	6388
Kojto	110:165afa46840b	6389	/****************** Bit definition for LTDC_LxCKCR register *************/
Kojto	110:165afa46840b	6390
Kojto	122:f9eeca106725	6391	#define LTDC_LxCKCR_CKBLUE 0x000000FFU /!< Color Key Blue value /
Kojto	122:f9eeca106725	6392	#define LTDC_LxCKCR_CKGREEN 0x0000FF00U /!< Color Key Green value /
Kojto	122:f9eeca106725	6393	#define LTDC_LxCKCR_CKRED 0x00FF0000U /!< Color Key Red value /
Kojto	110:165afa46840b	6394
Kojto	110:165afa46840b	6395	/****************** Bit definition for LTDC_LxPFCR register *************/
Kojto	110:165afa46840b	6396
Kojto	122:f9eeca106725	6397	#define LTDC_LxPFCR_PF 0x00000007U /!< Pixel Format /
Kojto	110:165afa46840b	6398
Kojto	110:165afa46840b	6399	/****************** Bit definition for LTDC_LxCACR register *************/
Kojto	110:165afa46840b	6400
Kojto	122:f9eeca106725	6401	#define LTDC_LxCACR_CONSTA 0x000000FFU /!< Constant Alpha /
Kojto	110:165afa46840b	6402
Kojto	110:165afa46840b	6403	/****************** Bit definition for LTDC_LxDCCR register *************/
Kojto	110:165afa46840b	6404
Kojto	122:f9eeca106725	6405	#define LTDC_LxDCCR_DCBLUE 0x000000FFU /!< Default Color Blue /
Kojto	122:f9eeca106725	6406	#define LTDC_LxDCCR_DCGREEN 0x0000FF00U /!< Default Color Green /
Kojto	122:f9eeca106725	6407	#define LTDC_LxDCCR_DCRED 0x00FF0000U /!< Default Color Red /
Kojto	122:f9eeca106725	6408	#define LTDC_LxDCCR_DCALPHA 0xFF000000U /!< Default Color Alpha /
Kojto	110:165afa46840b	6409
Kojto	110:165afa46840b	6410	/****************** Bit definition for LTDC_LxBFCR register *************/
Kojto	110:165afa46840b	6411
Kojto	122:f9eeca106725	6412	#define LTDC_LxBFCR_BF2 0x00000007U /!< Blending Factor 2 /
Kojto	122:f9eeca106725	6413	#define LTDC_LxBFCR_BF1 0x00000700U /!< Blending Factor 1 /
Kojto	110:165afa46840b	6414
Kojto	110:165afa46840b	6415	/****************** Bit definition for LTDC_LxCFBAR register ************/
Kojto	110:165afa46840b	6416
Kojto	122:f9eeca106725	6417	#define LTDC_LxCFBAR_CFBADD 0xFFFFFFFFU /!< Color Frame Buffer Start Address /
Kojto	110:165afa46840b	6418
Kojto	110:165afa46840b	6419	/****************** Bit definition for LTDC_LxCFBLR register ************/
Kojto	110:165afa46840b	6420
Kojto	122:f9eeca106725	6421	#define LTDC_LxCFBLR_CFBLL 0x00001FFFU /!< Color Frame Buffer Line Length /
Kojto	122:f9eeca106725	6422	#define LTDC_LxCFBLR_CFBP 0x1FFF0000U /!< Color Frame Buffer Pitch in bytes /
Kojto	110:165afa46840b	6423
Kojto	110:165afa46840b	6424	/****************** Bit definition for LTDC_LxCFBLNR register ***********/
Kojto	110:165afa46840b	6425
Kojto	122:f9eeca106725	6426	#define LTDC_LxCFBLNR_CFBLNBR 0x000007FFU /!< Frame Buffer Line Number /
Kojto	110:165afa46840b	6427
Kojto	110:165afa46840b	6428	/****************** Bit definition for LTDC_LxCLUTWR register ***********/
Kojto	110:165afa46840b	6429
Kojto	122:f9eeca106725	6430	#define LTDC_LxCLUTWR_BLUE 0x000000FFU /!< Blue value /
Kojto	122:f9eeca106725	6431	#define LTDC_LxCLUTWR_GREEN 0x0000FF00U /!< Green value /
Kojto	122:f9eeca106725	6432	#define LTDC_LxCLUTWR_RED 0x00FF0000U /!< Red value /
Kojto	122:f9eeca106725	6433	#define LTDC_LxCLUTWR_CLUTADD 0xFF000000U /!< CLUT address /
Kojto	110:165afa46840b	6434
Kojto	110:165afa46840b	6435
Kojto	110:165afa46840b	6436	/******************************************************************************/
Kojto	110:165afa46840b	6437	/* */
Kojto	110:165afa46840b	6438	/* Power Control */
Kojto	110:165afa46840b	6439	/* */
Kojto	110:165afa46840b	6440	/******************************************************************************/
Kojto	110:165afa46840b	6441	/****************** Bit definition for PWR_CR register ******************/
Kojto	122:f9eeca106725	6442	#define PWR_CR_LPDS 0x00000001U /!< Low-Power Deepsleep /
Kojto	122:f9eeca106725	6443	#define PWR_CR_PDDS 0x00000002U /!< Power Down Deepsleep /
Kojto	122:f9eeca106725	6444	#define PWR_CR_CWUF 0x00000004U /!< Clear Wakeup Flag /
Kojto	122:f9eeca106725	6445	#define PWR_CR_CSBF 0x00000008U /!< Clear Standby Flag /
Kojto	122:f9eeca106725	6446	#define PWR_CR_PVDE 0x00000010U /!< Power Voltage Detector Enable /
Kojto	122:f9eeca106725	6447
Kojto	122:f9eeca106725	6448	#define PWR_CR_PLS 0x000000E0U /!< PLS[2:0] bits (PVD Level Selection) /
Kojto	122:f9eeca106725	6449	#define PWR_CR_PLS_0 0x00000020U /!< Bit 0 /
Kojto	122:f9eeca106725	6450	#define PWR_CR_PLS_1 0x00000040U /!< Bit 1 /
Kojto	122:f9eeca106725	6451	#define PWR_CR_PLS_2 0x00000080U /!< Bit 2 /
Kojto	110:165afa46840b	6452
Kojto	110:165afa46840b	6453	/!< PVD level configuration /
Kojto	122:f9eeca106725	6454	#define PWR_CR_PLS_LEV0 0x00000000U /!< PVD level 0 /
Kojto	122:f9eeca106725	6455	#define PWR_CR_PLS_LEV1 0x00000020U /!< PVD level 1 /
Kojto	122:f9eeca106725	6456	#define PWR_CR_PLS_LEV2 0x00000040U /!< PVD level 2 /
Kojto	122:f9eeca106725	6457	#define PWR_CR_PLS_LEV3 0x00000060U /!< PVD level 3 /
Kojto	122:f9eeca106725	6458	#define PWR_CR_PLS_LEV4 0x00000080U /!< PVD level 4 /
Kojto	122:f9eeca106725	6459	#define PWR_CR_PLS_LEV5 0x000000A0U /!< PVD level 5 /
Kojto	122:f9eeca106725	6460	#define PWR_CR_PLS_LEV6 0x000000C0U /!< PVD level 6 /
Kojto	122:f9eeca106725	6461	#define PWR_CR_PLS_LEV7 0x000000E0U /!< PVD level 7 /
Kojto	122:f9eeca106725	6462	#define PWR_CR_DBP 0x00000100U /!< Disable Backup Domain write protection /
Kojto	122:f9eeca106725	6463	#define PWR_CR_FPDS 0x00000200U /!< Flash power down in Stop mode /
Kojto	122:f9eeca106725	6464	#define PWR_CR_LPLVDS 0x00000400U /!< Low-Power Regulator Low Voltage Scaling in Stop mode /
Kojto	122:f9eeca106725	6465	#define PWR_CR_MRLVDS 0x00000800U /!< Main regulator Low Voltage Scaling in Stop mode /
Kojto	122:f9eeca106725	6466	#define PWR_CR_ADCDC1 0x00002000U /!< Refer to AN4073 on how to use this bit /
Kojto	122:f9eeca106725	6467	#define PWR_CR_VOS 0x0000C000U /!< VOS[1:0] bits (Regulator voltage scaling output selection) /
Kojto	122:f9eeca106725	6468	#define PWR_CR_VOS_0 0x00004000U /!< Bit 0 /
Kojto	122:f9eeca106725	6469	#define PWR_CR_VOS_1 0x00008000U /!< Bit 1 /
Kojto	122:f9eeca106725	6470	#define PWR_CR_ODEN 0x00010000U /!< Over Drive enable /
Kojto	122:f9eeca106725	6471	#define PWR_CR_ODSWEN 0x00020000U /!< Over Drive switch enabled /
Kojto	122:f9eeca106725	6472	#define PWR_CR_UDEN 0x000C0000U /!< Under Drive enable in stop mode /
Kojto	122:f9eeca106725	6473	#define PWR_CR_UDEN_0 0x00040000U /!< Bit 0 /
Kojto	122:f9eeca106725	6474	#define PWR_CR_UDEN_1 0x00080000U /!< Bit 1 /
Kojto	110:165afa46840b	6475
Kojto	110:165afa46840b	6476	/* Legacy define */
Kojto	110:165afa46840b	6477	#define PWR_CR_PMODE PWR_CR_VOS
Kojto	110:165afa46840b	6478	#define PWR_CR_LPUDS PWR_CR_LPLVDS /!< Low-Power Regulator in deepsleep under-drive mode /
Kojto	110:165afa46840b	6479	#define PWR_CR_MRUDS PWR_CR_MRLVDS /!< Main regulator in deepsleep under-drive mode /
Kojto	110:165afa46840b	6480
Kojto	110:165afa46840b	6481	/***************** Bit definition for PWR_CSR register ******************/
Kojto	122:f9eeca106725	6482	#define PWR_CSR_WUF 0x00000001U /!< Wakeup Flag /
Kojto	122:f9eeca106725	6483	#define PWR_CSR_SBF 0x00000002U /!< Standby Flag /
Kojto	122:f9eeca106725	6484	#define PWR_CSR_PVDO 0x00000004U /!< PVD Output /
Kojto	122:f9eeca106725	6485	#define PWR_CSR_BRR 0x00000008U /!< Backup regulator ready /
Kojto	122:f9eeca106725	6486	#define PWR_CSR_WUPP 0x00000080U /!< WKUP pin Polarity /
Kojto	122:f9eeca106725	6487	#define PWR_CSR_EWUP 0x00000100U /!< Enable WKUP pin /
Kojto	122:f9eeca106725	6488	#define PWR_CSR_BRE 0x00000200U /!< Backup regulator enable /
Kojto	122:f9eeca106725	6489	#define PWR_CSR_VOSRDY 0x00004000U /!< Regulator voltage scaling output selection ready /
Kojto	122:f9eeca106725	6490	#define PWR_CSR_ODRDY 0x00010000U /!< Over Drive generator ready /
Kojto	122:f9eeca106725	6491	#define PWR_CSR_ODSWRDY 0x00020000U /!< Over Drive Switch ready /
Kojto	122:f9eeca106725	6492	#define PWR_CSR_UDSWRDY 0x000C0000U /!< Under Drive ready /
Kojto	110:165afa46840b	6493
Kojto	110:165afa46840b	6494	/* Legacy define */
Kojto	110:165afa46840b	6495	#define PWR_CSR_REGRDY PWR_CSR_VOSRDY
Kojto	110:165afa46840b	6496
Kojto	110:165afa46840b	6497	/******************************************************************************/
Kojto	110:165afa46840b	6498	/* */
Kojto	110:165afa46840b	6499	/* QUADSPI */
Kojto	110:165afa46840b	6500	/* */
Kojto	110:165afa46840b	6501	/******************************************************************************/
Kojto	110:165afa46840b	6502	/*************** Bit definition for QUADSPI_CR register *****************/
Kojto	122:f9eeca106725	6503	#define QUADSPI_CR_EN 0x00000001U /!< Enable /
Kojto	122:f9eeca106725	6504	#define QUADSPI_CR_ABORT 0x00000002U /!< Abort request /
Kojto	122:f9eeca106725	6505	#define QUADSPI_CR_DMAEN 0x00000004U /!< DMA Enable /
Kojto	122:f9eeca106725	6506	#define QUADSPI_CR_TCEN 0x00000008U /!< Timeout Counter Enable /
Kojto	122:f9eeca106725	6507	#define QUADSPI_CR_SSHIFT 0x00000010U /!< SSHIFT Sample Shift /
Kojto	122:f9eeca106725	6508	#define QUADSPI_CR_DFM 0x00000040U /!< Dual Flash Mode /
Kojto	122:f9eeca106725	6509	#define QUADSPI_CR_FSEL 0x00000080U /!< Flash Select /
Kojto	122:f9eeca106725	6510	#define QUADSPI_CR_FTHRES 0x00001F00U /!< FTHRES[3:0] FIFO Level /
Kojto	122:f9eeca106725	6511	#define QUADSPI_CR_FTHRES_0 0x00000100U /!< Bit 0 /
Kojto	122:f9eeca106725	6512	#define QUADSPI_CR_FTHRES_1 0x00000200U /!< Bit 1 /
Kojto	122:f9eeca106725	6513	#define QUADSPI_CR_FTHRES_2 0x00000400U /!< Bit 2 /
Kojto	122:f9eeca106725	6514	#define QUADSPI_CR_FTHRES_3 0x00000800U /!< Bit 3 /
Kojto	122:f9eeca106725	6515	#define QUADSPI_CR_FTHRES_4 0x00001000U /!< Bit 4 /
Kojto	122:f9eeca106725	6516	#define QUADSPI_CR_TEIE 0x00010000U /!< Transfer Error Interrupt Enable /
Kojto	122:f9eeca106725	6517	#define QUADSPI_CR_TCIE 0x00020000U /!< Transfer Complete Interrupt Enable /
Kojto	122:f9eeca106725	6518	#define QUADSPI_CR_FTIE 0x00040000U /!< FIFO Threshold Interrupt Enable /
Kojto	122:f9eeca106725	6519	#define QUADSPI_CR_SMIE 0x00080000U /!< Status Match Interrupt Enable /
Kojto	122:f9eeca106725	6520	#define QUADSPI_CR_TOIE 0x00100000U /!< TimeOut Interrupt Enable /
Kojto	122:f9eeca106725	6521	#define QUADSPI_CR_APMS 0x00400000U /!< Bit 1 /
Kojto	122:f9eeca106725	6522	#define QUADSPI_CR_PMM 0x00800000U /!< Polling Match Mode /
Kojto	122:f9eeca106725	6523	#define QUADSPI_CR_PRESCALER 0xFF000000U /!< PRESCALER[7:0] Clock prescaler /
Kojto	122:f9eeca106725	6524	#define QUADSPI_CR_PRESCALER_0 0x01000000U /!< Bit 0 /
Kojto	122:f9eeca106725	6525	#define QUADSPI_CR_PRESCALER_1 0x02000000U /!< Bit 1 /
Kojto	122:f9eeca106725	6526	#define QUADSPI_CR_PRESCALER_2 0x04000000U /!< Bit 2 /
Kojto	122:f9eeca106725	6527	#define QUADSPI_CR_PRESCALER_3 0x08000000U /!< Bit 3 /
Kojto	122:f9eeca106725	6528	#define QUADSPI_CR_PRESCALER_4 0x10000000U /!< Bit 4 /
Kojto	122:f9eeca106725	6529	#define QUADSPI_CR_PRESCALER_5 0x20000000U /!< Bit 5 /
Kojto	122:f9eeca106725	6530	#define QUADSPI_CR_PRESCALER_6 0x40000000U /!< Bit 6 /
Kojto	122:f9eeca106725	6531	#define QUADSPI_CR_PRESCALER_7 0x80000000U /!< Bit 7 /
Kojto	110:165afa46840b	6532
Kojto	110:165afa46840b	6533	/*************** Bit definition for QUADSPI_DCR register ****************/
Kojto	122:f9eeca106725	6534	#define QUADSPI_DCR_CKMODE 0x00000001U /!< Mode 0 / Mode 3 /
Kojto	122:f9eeca106725	6535	#define QUADSPI_DCR_CSHT 0x00000700U /!< CSHT[2:0]: ChipSelect High Time /
Kojto	122:f9eeca106725	6536	#define QUADSPI_DCR_CSHT_0 0x00000100U /!< Bit 0 /
Kojto	122:f9eeca106725	6537	#define QUADSPI_DCR_CSHT_1 0x00000200U /!< Bit 1 /
Kojto	122:f9eeca106725	6538	#define QUADSPI_DCR_CSHT_2 0x00000400U /!< Bit 2 /
Kojto	122:f9eeca106725	6539	#define QUADSPI_DCR_FSIZE 0x001F0000U /!< FSIZE[4:0]: Flash Size /
Kojto	122:f9eeca106725	6540	#define QUADSPI_DCR_FSIZE_0 0x00010000U /!< Bit 0 /
Kojto	122:f9eeca106725	6541	#define QUADSPI_DCR_FSIZE_1 0x00020000U /!< Bit 1 /
Kojto	122:f9eeca106725	6542	#define QUADSPI_DCR_FSIZE_2 0x00040000U /!< Bit 2 /
Kojto	122:f9eeca106725	6543	#define QUADSPI_DCR_FSIZE_3 0x00080000U /!< Bit 3 /
Kojto	122:f9eeca106725	6544	#define QUADSPI_DCR_FSIZE_4 0x00100000U /!< Bit 4 /
Kojto	110:165afa46840b	6545
Kojto	110:165afa46840b	6546	/**************** Bit definition for QUADSPI_SR register *****************/
Kojto	122:f9eeca106725	6547	#define QUADSPI_SR_TEF 0x00000001U /!< Transfer Error Flag /
Kojto	122:f9eeca106725	6548	#define QUADSPI_SR_TCF 0x00000002U /!< Transfer Complete Flag /
Kojto	122:f9eeca106725	6549	#define QUADSPI_SR_FTF 0x00000004U /!< FIFO Threshlod Flag /
Kojto	122:f9eeca106725	6550	#define QUADSPI_SR_SMF 0x00000008U /!< Status Match Flag /
Kojto	122:f9eeca106725	6551	#define QUADSPI_SR_TOF 0x00000010U /!< Timeout Flag /
Kojto	122:f9eeca106725	6552	#define QUADSPI_SR_BUSY 0x00000020U /!< Busy /
Kojto	122:f9eeca106725	6553	#define QUADSPI_SR_FLEVEL 0x00003F00U /!< FIFO Threshlod Flag /
Kojto	122:f9eeca106725	6554	#define QUADSPI_SR_FLEVEL_0 0x00000100U /!< Bit 0 /
Kojto	122:f9eeca106725	6555	#define QUADSPI_SR_FLEVEL_1 0x00000200U /!< Bit 1 /
Kojto	122:f9eeca106725	6556	#define QUADSPI_SR_FLEVEL_2 0x00000400U /!< Bit 2 /
Kojto	122:f9eeca106725	6557	#define QUADSPI_SR_FLEVEL_3 0x00000800U /!< Bit 3 /
Kojto	122:f9eeca106725	6558	#define QUADSPI_SR_FLEVEL_4 0x00001000U /!< Bit 4 /
Kojto	122:f9eeca106725	6559	#define QUADSPI_SR_FLEVEL_5 0x00002000U /!< Bit 5 /
Kojto	110:165afa46840b	6560
Kojto	110:165afa46840b	6561	/**************** Bit definition for QUADSPI_FCR register ****************/
Kojto	122:f9eeca106725	6562	#define QUADSPI_FCR_CTEF 0x00000001U /!< Clear Transfer Error Flag /
Kojto	122:f9eeca106725	6563	#define QUADSPI_FCR_CTCF 0x00000002U /!< Clear Transfer Complete Flag /
Kojto	122:f9eeca106725	6564	#define QUADSPI_FCR_CSMF 0x00000008U /!< Clear Status Match Flag /
Kojto	122:f9eeca106725	6565	#define QUADSPI_FCR_CTOF 0x00000010U /!< Clear Timeout Flag /
Kojto	110:165afa46840b	6566
Kojto	110:165afa46840b	6567	/**************** Bit definition for QUADSPI_DLR register ****************/
Kojto	122:f9eeca106725	6568	#define QUADSPI_DLR_DL 0xFFFFFFFFU /!< DL[31:0]: Data Length /
Kojto	110:165afa46840b	6569
Kojto	110:165afa46840b	6570	/**************** Bit definition for QUADSPI_CCR register ****************/
Kojto	122:f9eeca106725	6571	#define QUADSPI_CCR_INSTRUCTION 0x000000FFU /!< INSTRUCTION[7:0]: Instruction /
Kojto	122:f9eeca106725	6572	#define QUADSPI_CCR_INSTRUCTION_0 0x00000001U /!< Bit 0 /
Kojto	122:f9eeca106725	6573	#define QUADSPI_CCR_INSTRUCTION_1 0x00000002U /!< Bit 1 /
Kojto	122:f9eeca106725	6574	#define QUADSPI_CCR_INSTRUCTION_2 0x00000004U /!< Bit 2 /
Kojto	122:f9eeca106725	6575	#define QUADSPI_CCR_INSTRUCTION_3 0x00000008U /!< Bit 3 /
Kojto	122:f9eeca106725	6576	#define QUADSPI_CCR_INSTRUCTION_4 0x00000010U /!< Bit 4 /
Kojto	122:f9eeca106725	6577	#define QUADSPI_CCR_INSTRUCTION_5 0x00000020U /!< Bit 5 /
Kojto	122:f9eeca106725	6578	#define QUADSPI_CCR_INSTRUCTION_6 0x00000040U /!< Bit 6 /
Kojto	122:f9eeca106725	6579	#define QUADSPI_CCR_INSTRUCTION_7 0x00000080U /!< Bit 7 /
Kojto	122:f9eeca106725	6580	#define QUADSPI_CCR_IMODE 0x00000300U /!< IMODE[1:0]: Instruction Mode /
Kojto	122:f9eeca106725	6581	#define QUADSPI_CCR_IMODE_0 0x00000100U /!< Bit 0 /
Kojto	122:f9eeca106725	6582	#define QUADSPI_CCR_IMODE_1 0x00000200U /!< Bit 1 /
Kojto	122:f9eeca106725	6583	#define QUADSPI_CCR_ADMODE 0x00000C00U /!< ADMODE[1:0]: Address Mode /
Kojto	122:f9eeca106725	6584	#define QUADSPI_CCR_ADMODE_0 0x00000400U /!< Bit 0 /
Kojto	122:f9eeca106725	6585	#define QUADSPI_CCR_ADMODE_1 0x00000800U /!< Bit 1 /
Kojto	122:f9eeca106725	6586	#define QUADSPI_CCR_ADSIZE 0x00003000U /!< ADSIZE[1:0]: Address Size /
Kojto	122:f9eeca106725	6587	#define QUADSPI_CCR_ADSIZE_0 0x00001000U /!< Bit 0 /
Kojto	122:f9eeca106725	6588	#define QUADSPI_CCR_ADSIZE_1 0x00002000U /!< Bit 1 /
Kojto	122:f9eeca106725	6589	#define QUADSPI_CCR_ABMODE 0x0000C000U /!< ABMODE[1:0]: Alternate Bytes Mode /
Kojto	122:f9eeca106725	6590	#define QUADSPI_CCR_ABMODE_0 0x00004000U /!< Bit 0 /
Kojto	122:f9eeca106725	6591	#define QUADSPI_CCR_ABMODE_1 0x00008000U /!< Bit 1 /
Kojto	122:f9eeca106725	6592	#define QUADSPI_CCR_ABSIZE 0x00030000U /!< ABSIZE[1:0]: Instruction Mode /
Kojto	122:f9eeca106725	6593	#define QUADSPI_CCR_ABSIZE_0 0x00010000U /!< Bit 0 /
Kojto	122:f9eeca106725	6594	#define QUADSPI_CCR_ABSIZE_1 0x00020000U /!< Bit 1 /
Kojto	122:f9eeca106725	6595	#define QUADSPI_CCR_DCYC 0x007C0000U /!< DCYC[4:0]: Dummy Cycles /
Kojto	122:f9eeca106725	6596	#define QUADSPI_CCR_DCYC_0 0x00040000U /!< Bit 0 /
Kojto	122:f9eeca106725	6597	#define QUADSPI_CCR_DCYC_1 0x00080000U /!< Bit 1 /
Kojto	122:f9eeca106725	6598	#define QUADSPI_CCR_DCYC_2 0x00100000U /!< Bit 2 /
Kojto	122:f9eeca106725	6599	#define QUADSPI_CCR_DCYC_3 0x00200000U /!< Bit 3 /
Kojto	122:f9eeca106725	6600	#define QUADSPI_CCR_DCYC_4 0x00400000U /!< Bit 4 /
Kojto	122:f9eeca106725	6601	#define QUADSPI_CCR_DMODE 0x03000000U /!< DMODE[1:0]: Data Mode /
Kojto	122:f9eeca106725	6602	#define QUADSPI_CCR_DMODE_0 0x01000000U /!< Bit 0 /
Kojto	122:f9eeca106725	6603	#define QUADSPI_CCR_DMODE_1 0x02000000U /!< Bit 1 /
Kojto	122:f9eeca106725	6604	#define QUADSPI_CCR_FMODE 0x0C000000U /!< FMODE[1:0]: Functional Mode /
Kojto	122:f9eeca106725	6605	#define QUADSPI_CCR_FMODE_0 0x04000000U /!< Bit 0 /
Kojto	122:f9eeca106725	6606	#define QUADSPI_CCR_FMODE_1 0x08000000U /!< Bit 1 /
Kojto	122:f9eeca106725	6607	#define QUADSPI_CCR_SIOO 0x10000000U /!< SIOO: Send Instruction Only Once Mode /
Kojto	122:f9eeca106725	6608	#define QUADSPI_CCR_DHHC 0x40000000U /!< DHHC: Delay Half Hclk Cycle /
Kojto	122:f9eeca106725	6609	#define QUADSPI_CCR_DDRM 0x80000000U /!< DDRM: Double Data Rate Mode /
Kojto	110:165afa46840b	6610	/**************** Bit definition for QUADSPI_AR register *****************/
Kojto	122:f9eeca106725	6611	#define QUADSPI_AR_ADDRESS 0xFFFFFFFFU /!< ADDRESS[31:0]: Address /
Kojto	110:165afa46840b	6612
Kojto	110:165afa46840b	6613	/**************** Bit definition for QUADSPI_ABR register ****************/
Kojto	122:f9eeca106725	6614	#define QUADSPI_ABR_ALTERNATE 0xFFFFFFFFU /!< ALTERNATE[31:0]: Alternate Bytes /
Kojto	110:165afa46840b	6615
Kojto	110:165afa46840b	6616	/**************** Bit definition for QUADSPI_DR register *****************/
Kojto	122:f9eeca106725	6617	#define QUADSPI_DR_DATA 0xFFFFFFFFU /!< DATA[31:0]: Data /
Kojto	110:165afa46840b	6618
Kojto	110:165afa46840b	6619	/**************** Bit definition for QUADSPI_PSMKR register **************/
Kojto	122:f9eeca106725	6620	#define QUADSPI_PSMKR_MASK 0xFFFFFFFFU /!< MASK[31:0]: Status Mask /
Kojto	110:165afa46840b	6621
Kojto	110:165afa46840b	6622	/**************** Bit definition for QUADSPI_PSMAR register **************/
Kojto	122:f9eeca106725	6623	#define QUADSPI_PSMAR_MATCH 0xFFFFFFFFU /!< MATCH[31:0]: Status Match /
Kojto	110:165afa46840b	6624
Kojto	110:165afa46840b	6625	/**************** Bit definition for QUADSPI_PIR register ***************/
Kojto	122:f9eeca106725	6626	#define QUADSPI_PIR_INTERVAL 0x0000FFFFU /!< INTERVAL[15:0]: Polling Interval /
Kojto	110:165afa46840b	6627
Kojto	110:165afa46840b	6628	/**************** Bit definition for QUADSPI_LPTR register ***************/
Kojto	122:f9eeca106725	6629	#define QUADSPI_LPTR_TIMEOUT 0x0000FFFFU /!< TIMEOUT[15:0]: Timeout period /
Kojto	110:165afa46840b	6630
Kojto	110:165afa46840b	6631	/******************************************************************************/
Kojto	110:165afa46840b	6632	/* */
Kojto	110:165afa46840b	6633	/* Reset and Clock Control */
Kojto	110:165afa46840b	6634	/* */
Kojto	110:165afa46840b	6635	/******************************************************************************/
Kojto	110:165afa46840b	6636	/****************** Bit definition for RCC_CR register ******************/
Kojto	122:f9eeca106725	6637	#define RCC_CR_HSION 0x00000001U
Kojto	122:f9eeca106725	6638	#define RCC_CR_HSIRDY 0x00000002U
Kojto	122:f9eeca106725	6639
Kojto	122:f9eeca106725	6640	#define RCC_CR_HSITRIM 0x000000F8U
Kojto	122:f9eeca106725	6641	#define RCC_CR_HSITRIM_0 0x00000008U/!<Bit 0 /
Kojto	122:f9eeca106725	6642	#define RCC_CR_HSITRIM_1 0x00000010U/!<Bit 1 /
Kojto	122:f9eeca106725	6643	#define RCC_CR_HSITRIM_2 0x00000020U/!<Bit 2 /
Kojto	122:f9eeca106725	6644	#define RCC_CR_HSITRIM_3 0x00000040U/!<Bit 3 /
Kojto	122:f9eeca106725	6645	#define RCC_CR_HSITRIM_4 0x00000080U/!<Bit 4 /
Kojto	122:f9eeca106725	6646
Kojto	122:f9eeca106725	6647	#define RCC_CR_HSICAL 0x0000FF00U
Kojto	122:f9eeca106725	6648	#define RCC_CR_HSICAL_0 0x00000100U/!<Bit 0 /
Kojto	122:f9eeca106725	6649	#define RCC_CR_HSICAL_1 0x00000200U/!<Bit 1 /
Kojto	122:f9eeca106725	6650	#define RCC_CR_HSICAL_2 0x00000400U/!<Bit 2 /
Kojto	122:f9eeca106725	6651	#define RCC_CR_HSICAL_3 0x00000800U/!<Bit 3 /
Kojto	122:f9eeca106725	6652	#define RCC_CR_HSICAL_4 0x00001000U/!<Bit 4 /
Kojto	122:f9eeca106725	6653	#define RCC_CR_HSICAL_5 0x00002000U/!<Bit 5 /
Kojto	122:f9eeca106725	6654	#define RCC_CR_HSICAL_6 0x00004000U/!<Bit 6 /
Kojto	122:f9eeca106725	6655	#define RCC_CR_HSICAL_7 0x00008000U/!<Bit 7 /
Kojto	122:f9eeca106725	6656
Kojto	122:f9eeca106725	6657	#define RCC_CR_HSEON 0x00010000U
Kojto	122:f9eeca106725	6658	#define RCC_CR_HSERDY 0x00020000U
Kojto	122:f9eeca106725	6659	#define RCC_CR_HSEBYP 0x00040000U
Kojto	122:f9eeca106725	6660	#define RCC_CR_CSSON 0x00080000U
Kojto	122:f9eeca106725	6661	#define RCC_CR_PLLON 0x01000000U
Kojto	122:f9eeca106725	6662	#define RCC_CR_PLLRDY 0x02000000U
Kojto	122:f9eeca106725	6663	#define RCC_CR_PLLI2SON 0x04000000U
Kojto	122:f9eeca106725	6664	#define RCC_CR_PLLI2SRDY 0x08000000U
Kojto	122:f9eeca106725	6665	#define RCC_CR_PLLSAION 0x10000000U
Kojto	122:f9eeca106725	6666	#define RCC_CR_PLLSAIRDY 0x20000000U
Kojto	110:165afa46840b	6667
Kojto	110:165afa46840b	6668	/****************** Bit definition for RCC_PLLCFGR register *************/
Kojto	122:f9eeca106725	6669	#define RCC_PLLCFGR_PLLM 0x0000003FU
Kojto	122:f9eeca106725	6670	#define RCC_PLLCFGR_PLLM_0 0x00000001U
Kojto	122:f9eeca106725	6671	#define RCC_PLLCFGR_PLLM_1 0x00000002U
Kojto	122:f9eeca106725	6672	#define RCC_PLLCFGR_PLLM_2 0x00000004U
Kojto	122:f9eeca106725	6673	#define RCC_PLLCFGR_PLLM_3 0x00000008U
Kojto	122:f9eeca106725	6674	#define RCC_PLLCFGR_PLLM_4 0x00000010U
Kojto	122:f9eeca106725	6675	#define RCC_PLLCFGR_PLLM_5 0x00000020U
Kojto	122:f9eeca106725	6676
Kojto	122:f9eeca106725	6677	#define RCC_PLLCFGR_PLLN 0x00007FC0U
Kojto	122:f9eeca106725	6678	#define RCC_PLLCFGR_PLLN_0 0x00000040U
Kojto	122:f9eeca106725	6679	#define RCC_PLLCFGR_PLLN_1 0x00000080U
Kojto	122:f9eeca106725	6680	#define RCC_PLLCFGR_PLLN_2 0x00000100U
Kojto	122:f9eeca106725	6681	#define RCC_PLLCFGR_PLLN_3 0x00000200U
Kojto	122:f9eeca106725	6682	#define RCC_PLLCFGR_PLLN_4 0x00000400U
Kojto	122:f9eeca106725	6683	#define RCC_PLLCFGR_PLLN_5 0x00000800U
Kojto	122:f9eeca106725	6684	#define RCC_PLLCFGR_PLLN_6 0x00001000U
Kojto	122:f9eeca106725	6685	#define RCC_PLLCFGR_PLLN_7 0x00002000U
Kojto	122:f9eeca106725	6686	#define RCC_PLLCFGR_PLLN_8 0x00004000U
Kojto	122:f9eeca106725	6687
Kojto	122:f9eeca106725	6688	#define RCC_PLLCFGR_PLLP 0x00030000U
Kojto	122:f9eeca106725	6689	#define RCC_PLLCFGR_PLLP_0 0x00010000U
Kojto	122:f9eeca106725	6690	#define RCC_PLLCFGR_PLLP_1 0x00020000U
Kojto	122:f9eeca106725	6691
Kojto	122:f9eeca106725	6692	#define RCC_PLLCFGR_PLLSRC 0x00400000U
Kojto	122:f9eeca106725	6693	#define RCC_PLLCFGR_PLLSRC_HSE 0x00400000U
Kojto	122:f9eeca106725	6694	#define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
Kojto	122:f9eeca106725	6695
Kojto	122:f9eeca106725	6696	#define RCC_PLLCFGR_PLLQ 0x0F000000U
Kojto	122:f9eeca106725	6697	#define RCC_PLLCFGR_PLLQ_0 0x01000000U
Kojto	122:f9eeca106725	6698	#define RCC_PLLCFGR_PLLQ_1 0x02000000U
Kojto	122:f9eeca106725	6699	#define RCC_PLLCFGR_PLLQ_2 0x04000000U
Kojto	122:f9eeca106725	6700	#define RCC_PLLCFGR_PLLQ_3 0x08000000U
Kojto	122:f9eeca106725	6701
Kojto	122:f9eeca106725	6702	#define RCC_PLLCFGR_PLLR 0x70000000U
Kojto	122:f9eeca106725	6703	#define RCC_PLLCFGR_PLLR_0 0x10000000U
Kojto	122:f9eeca106725	6704	#define RCC_PLLCFGR_PLLR_1 0x20000000U
Kojto	122:f9eeca106725	6705	#define RCC_PLLCFGR_PLLR_2 0x40000000U
Kojto	110:165afa46840b	6706
Kojto	110:165afa46840b	6707
Kojto	110:165afa46840b	6708	/****************** Bit definition for RCC_CFGR register ****************/
Kojto	110:165afa46840b	6709	/!< SW configuration /
Kojto	122:f9eeca106725	6710	#define RCC_CFGR_SW 0x00000003U /!< SW[1:0] bits (System clock Switch) /
Kojto	122:f9eeca106725	6711	#define RCC_CFGR_SW_0 0x00000001U /!< Bit 0 /
Kojto	122:f9eeca106725	6712	#define RCC_CFGR_SW_1 0x00000002U /!< Bit 1 /
Kojto	122:f9eeca106725	6713
Kojto	122:f9eeca106725	6714	#define RCC_CFGR_SW_HSI 0x00000000U /!< HSI selected as system clock /
Kojto	122:f9eeca106725	6715	#define RCC_CFGR_SW_HSE 0x00000001U /!< HSE selected as system clock /
Kojto	122:f9eeca106725	6716	#define RCC_CFGR_SW_PLL 0x00000002U /!< PLL selected as system clock /
Kojto	110:165afa46840b	6717
Kojto	110:165afa46840b	6718	/!< SWS configuration /
Kojto	122:f9eeca106725	6719	#define RCC_CFGR_SWS 0x0000000CU /!< SWS[1:0] bits (System Clock Switch Status) /
Kojto	122:f9eeca106725	6720	#define RCC_CFGR_SWS_0 0x00000004U /!< Bit 0 /
Kojto	122:f9eeca106725	6721	#define RCC_CFGR_SWS_1 0x00000008U /!< Bit 1 /
Kojto	122:f9eeca106725	6722
Kojto	122:f9eeca106725	6723	#define RCC_CFGR_SWS_HSI 0x00000000U /!< HSI oscillator used as system clock /
Kojto	122:f9eeca106725	6724	#define RCC_CFGR_SWS_HSE 0x00000004U /!< HSE oscillator used as system clock /
Kojto	122:f9eeca106725	6725	#define RCC_CFGR_SWS_PLL 0x00000008U /!< PLL used as system clock /
Kojto	110:165afa46840b	6726
Kojto	110:165afa46840b	6727	/!< HPRE configuration /
Kojto	122:f9eeca106725	6728	#define RCC_CFGR_HPRE 0x000000F0U /!< HPRE[3:0] bits (AHB prescaler) /
Kojto	122:f9eeca106725	6729	#define RCC_CFGR_HPRE_0 0x00000010U /!< Bit 0 /
Kojto	122:f9eeca106725	6730	#define RCC_CFGR_HPRE_1 0x00000020U /!< Bit 1 /
Kojto	122:f9eeca106725	6731	#define RCC_CFGR_HPRE_2 0x00000040U /!< Bit 2 /
Kojto	122:f9eeca106725	6732	#define RCC_CFGR_HPRE_3 0x00000080U /!< Bit 3 /
Kojto	122:f9eeca106725	6733
Kojto	122:f9eeca106725	6734	#define RCC_CFGR_HPRE_DIV1 0x00000000U /!< SYSCLK not divided /
Kojto	122:f9eeca106725	6735	#define RCC_CFGR_HPRE_DIV2 0x00000080U /!< SYSCLK divided by 2 /
Kojto	122:f9eeca106725	6736	#define RCC_CFGR_HPRE_DIV4 0x00000090U /!< SYSCLK divided by 4 /
Kojto	122:f9eeca106725	6737	#define RCC_CFGR_HPRE_DIV8 0x000000A0U /!< SYSCLK divided by 8 /
Kojto	122:f9eeca106725	6738	#define RCC_CFGR_HPRE_DIV16 0x000000B0U /!< SYSCLK divided by 16 /
Kojto	122:f9eeca106725	6739	#define RCC_CFGR_HPRE_DIV64 0x000000C0U /!< SYSCLK divided by 64 /
Kojto	122:f9eeca106725	6740	#define RCC_CFGR_HPRE_DIV128 0x000000D0U /!< SYSCLK divided by 128 /
Kojto	122:f9eeca106725	6741	#define RCC_CFGR_HPRE_DIV256 0x000000E0U /!< SYSCLK divided by 256 /
Kojto	122:f9eeca106725	6742	#define RCC_CFGR_HPRE_DIV512 0x000000F0U /!< SYSCLK divided by 512 /
Kojto	110:165afa46840b	6743
Kojto	110:165afa46840b	6744	/!< PPRE1 configuration /
Kojto	122:f9eeca106725	6745	#define RCC_CFGR_PPRE1 0x00001C00U /!< PRE1[2:0] bits (APB1 prescaler) /
Kojto	122:f9eeca106725	6746	#define RCC_CFGR_PPRE1_0 0x00000400U /!< Bit 0 /
Kojto	122:f9eeca106725	6747	#define RCC_CFGR_PPRE1_1 0x00000800U /!< Bit 1 /
Kojto	122:f9eeca106725	6748	#define RCC_CFGR_PPRE1_2 0x00001000U /!< Bit 2 /
Kojto	122:f9eeca106725	6749
Kojto	122:f9eeca106725	6750	#define RCC_CFGR_PPRE1_DIV1 0x00000000U /!< HCLK not divided /
Kojto	122:f9eeca106725	6751	#define RCC_CFGR_PPRE1_DIV2 0x00001000U /!< HCLK divided by 2 /
Kojto	122:f9eeca106725	6752	#define RCC_CFGR_PPRE1_DIV4 0x00001400U /!< HCLK divided by 4 /
Kojto	122:f9eeca106725	6753	#define RCC_CFGR_PPRE1_DIV8 0x00001800U /!< HCLK divided by 8 /
Kojto	122:f9eeca106725	6754	#define RCC_CFGR_PPRE1_DIV16 0x00001C00U /!< HCLK divided by 16 /
Kojto	110:165afa46840b	6755
Kojto	110:165afa46840b	6756	/!< PPRE2 configuration /
Kojto	122:f9eeca106725	6757	#define RCC_CFGR_PPRE2 0x0000E000U /!< PRE2[2:0] bits (APB2 prescaler) /
Kojto	122:f9eeca106725	6758	#define RCC_CFGR_PPRE2_0 0x00002000U /!< Bit 0 /
Kojto	122:f9eeca106725	6759	#define RCC_CFGR_PPRE2_1 0x00004000U /!< Bit 1 /
Kojto	122:f9eeca106725	6760	#define RCC_CFGR_PPRE2_2 0x00008000U /!< Bit 2 /
Kojto	122:f9eeca106725	6761
Kojto	122:f9eeca106725	6762	#define RCC_CFGR_PPRE2_DIV1 0x00000000U /!< HCLK not divided /
Kojto	122:f9eeca106725	6763	#define RCC_CFGR_PPRE2_DIV2 0x00008000U /!< HCLK divided by 2 /
Kojto	122:f9eeca106725	6764	#define RCC_CFGR_PPRE2_DIV4 0x0000A000U /!< HCLK divided by 4 /
Kojto	122:f9eeca106725	6765	#define RCC_CFGR_PPRE2_DIV8 0x0000C000U /!< HCLK divided by 8 /
Kojto	122:f9eeca106725	6766	#define RCC_CFGR_PPRE2_DIV16 0x0000E000U /!< HCLK divided by 16 /
Kojto	110:165afa46840b	6767
Kojto	110:165afa46840b	6768	/!< RTCPRE configuration /
Kojto	122:f9eeca106725	6769	#define RCC_CFGR_RTCPRE 0x001F0000U
Kojto	122:f9eeca106725	6770	#define RCC_CFGR_RTCPRE_0 0x00010000U
Kojto	122:f9eeca106725	6771	#define RCC_CFGR_RTCPRE_1 0x00020000U
Kojto	122:f9eeca106725	6772	#define RCC_CFGR_RTCPRE_2 0x00040000U
Kojto	122:f9eeca106725	6773	#define RCC_CFGR_RTCPRE_3 0x00080000U
Kojto	122:f9eeca106725	6774	#define RCC_CFGR_RTCPRE_4 0x00100000U
Kojto	110:165afa46840b	6775
Kojto	110:165afa46840b	6776	/!< MCO1 configuration /
Kojto	122:f9eeca106725	6777	#define RCC_CFGR_MCO1 0x00600000U
Kojto	122:f9eeca106725	6778	#define RCC_CFGR_MCO1_0 0x00200000U
Kojto	122:f9eeca106725	6779	#define RCC_CFGR_MCO1_1 0x00400000U
Kojto	122:f9eeca106725	6780
Kojto	122:f9eeca106725	6781	#define RCC_CFGR_I2SSRC 0x00800000U
Kojto	122:f9eeca106725	6782
Kojto	122:f9eeca106725	6783	#define RCC_CFGR_MCO1PRE 0x07000000U
Kojto	122:f9eeca106725	6784	#define RCC_CFGR_MCO1PRE_0 0x01000000U
Kojto	122:f9eeca106725	6785	#define RCC_CFGR_MCO1PRE_1 0x02000000U
Kojto	122:f9eeca106725	6786	#define RCC_CFGR_MCO1PRE_2 0x04000000U
Kojto	122:f9eeca106725	6787
Kojto	122:f9eeca106725	6788	#define RCC_CFGR_MCO2PRE 0x38000000U
Kojto	122:f9eeca106725	6789	#define RCC_CFGR_MCO2PRE_0 0x08000000U
Kojto	122:f9eeca106725	6790	#define RCC_CFGR_MCO2PRE_1 0x10000000U
Kojto	122:f9eeca106725	6791	#define RCC_CFGR_MCO2PRE_2 0x20000000U
Kojto	122:f9eeca106725	6792
Kojto	122:f9eeca106725	6793	#define RCC_CFGR_MCO2 0xC0000000U
Kojto	122:f9eeca106725	6794	#define RCC_CFGR_MCO2_0 0x40000000U
Kojto	122:f9eeca106725	6795	#define RCC_CFGR_MCO2_1 0x80000000U
Kojto	110:165afa46840b	6796
Kojto	110:165afa46840b	6797	/****************** Bit definition for RCC_CIR register *****************/
Kojto	122:f9eeca106725	6798	#define RCC_CIR_LSIRDYF 0x00000001U
Kojto	122:f9eeca106725	6799	#define RCC_CIR_LSERDYF 0x00000002U
Kojto	122:f9eeca106725	6800	#define RCC_CIR_HSIRDYF 0x00000004U
Kojto	122:f9eeca106725	6801	#define RCC_CIR_HSERDYF 0x00000008U
Kojto	122:f9eeca106725	6802	#define RCC_CIR_PLLRDYF 0x00000010U
Kojto	122:f9eeca106725	6803	#define RCC_CIR_PLLI2SRDYF 0x00000020U
Kojto	122:f9eeca106725	6804	#define RCC_CIR_PLLSAIRDYF 0x00000040U
Kojto	122:f9eeca106725	6805	#define RCC_CIR_CSSF 0x00000080U
Kojto	122:f9eeca106725	6806	#define RCC_CIR_LSIRDYIE 0x00000100U
Kojto	122:f9eeca106725	6807	#define RCC_CIR_LSERDYIE 0x00000200U
Kojto	122:f9eeca106725	6808	#define RCC_CIR_HSIRDYIE 0x00000400U
Kojto	122:f9eeca106725	6809	#define RCC_CIR_HSERDYIE 0x00000800U
Kojto	122:f9eeca106725	6810	#define RCC_CIR_PLLRDYIE 0x00001000U
Kojto	122:f9eeca106725	6811	#define RCC_CIR_PLLI2SRDYIE 0x00002000U
Kojto	122:f9eeca106725	6812	#define RCC_CIR_PLLSAIRDYIE 0x00004000U
Kojto	122:f9eeca106725	6813	#define RCC_CIR_LSIRDYC 0x00010000U
Kojto	122:f9eeca106725	6814	#define RCC_CIR_LSERDYC 0x00020000U
Kojto	122:f9eeca106725	6815	#define RCC_CIR_HSIRDYC 0x00040000U
Kojto	122:f9eeca106725	6816	#define RCC_CIR_HSERDYC 0x00080000U
Kojto	122:f9eeca106725	6817	#define RCC_CIR_PLLRDYC 0x00100000U
Kojto	122:f9eeca106725	6818	#define RCC_CIR_PLLI2SRDYC 0x00200000U
Kojto	122:f9eeca106725	6819	#define RCC_CIR_PLLSAIRDYC 0x00400000U
Kojto	122:f9eeca106725	6820	#define RCC_CIR_CSSC 0x00800000U
Kojto	110:165afa46840b	6821
Kojto	110:165afa46840b	6822	/****************** Bit definition for RCC_AHB1RSTR register ************/
Kojto	122:f9eeca106725	6823	#define RCC_AHB1RSTR_GPIOARST 0x00000001U
Kojto	122:f9eeca106725	6824	#define RCC_AHB1RSTR_GPIOBRST 0x00000002U
Kojto	122:f9eeca106725	6825	#define RCC_AHB1RSTR_GPIOCRST 0x00000004U
Kojto	122:f9eeca106725	6826	#define RCC_AHB1RSTR_GPIODRST 0x00000008U
Kojto	122:f9eeca106725	6827	#define RCC_AHB1RSTR_GPIOERST 0x00000010U
Kojto	122:f9eeca106725	6828	#define RCC_AHB1RSTR_GPIOFRST 0x00000020U
Kojto	122:f9eeca106725	6829	#define RCC_AHB1RSTR_GPIOGRST 0x00000040U
Kojto	122:f9eeca106725	6830	#define RCC_AHB1RSTR_GPIOHRST 0x00000080U
Kojto	122:f9eeca106725	6831	#define RCC_AHB1RSTR_GPIOIRST 0x00000100U
Kojto	122:f9eeca106725	6832	#define RCC_AHB1RSTR_GPIOJRST 0x00000200U
Kojto	122:f9eeca106725	6833	#define RCC_AHB1RSTR_GPIOKRST 0x00000400U
Kojto	122:f9eeca106725	6834	#define RCC_AHB1RSTR_CRCRST 0x00001000U
Kojto	122:f9eeca106725	6835	#define RCC_AHB1RSTR_DMA1RST 0x00200000U
Kojto	122:f9eeca106725	6836	#define RCC_AHB1RSTR_DMA2RST 0x00400000U
Kojto	122:f9eeca106725	6837	#define RCC_AHB1RSTR_DMA2DRST 0x00800000U
Kojto	122:f9eeca106725	6838	#define RCC_AHB1RSTR_ETHMACRST 0x02000000U
Kojto	122:f9eeca106725	6839	#define RCC_AHB1RSTR_OTGHRST 0x20000000U
Kojto	110:165afa46840b	6840
Kojto	110:165afa46840b	6841	/****************** Bit definition for RCC_AHB2RSTR register ************/
Kojto	122:f9eeca106725	6842	#define RCC_AHB2RSTR_DCMIRST 0x00000001U
Kojto	122:f9eeca106725	6843	#define RCC_AHB2RSTR_RNGRST 0x00000040U
Kojto	122:f9eeca106725	6844	#define RCC_AHB2RSTR_OTGFSRST 0x00000080U
Kojto	110:165afa46840b	6845
Kojto	110:165afa46840b	6846	/****************** Bit definition for RCC_AHB3RSTR register ************/
Kojto	122:f9eeca106725	6847	#define RCC_AHB3RSTR_FMCRST 0x00000001U
Kojto	122:f9eeca106725	6848	#define RCC_AHB3RSTR_QSPIRST 0x00000002U
Kojto	110:165afa46840b	6849
Kojto	110:165afa46840b	6850	/****************** Bit definition for RCC_APB1RSTR register ************/
Kojto	122:f9eeca106725	6851	#define RCC_APB1RSTR_TIM2RST 0x00000001U
Kojto	122:f9eeca106725	6852	#define RCC_APB1RSTR_TIM3RST 0x00000002U
Kojto	122:f9eeca106725	6853	#define RCC_APB1RSTR_TIM4RST 0x00000004U
Kojto	122:f9eeca106725	6854	#define RCC_APB1RSTR_TIM5RST 0x00000008U
Kojto	122:f9eeca106725	6855	#define RCC_APB1RSTR_TIM6RST 0x00000010U
Kojto	122:f9eeca106725	6856	#define RCC_APB1RSTR_TIM7RST 0x00000020U
Kojto	122:f9eeca106725	6857	#define RCC_APB1RSTR_TIM12RST 0x00000040U
Kojto	122:f9eeca106725	6858	#define RCC_APB1RSTR_TIM13RST 0x00000080U
Kojto	122:f9eeca106725	6859	#define RCC_APB1RSTR_TIM14RST 0x00000100U
Kojto	122:f9eeca106725	6860	#define RCC_APB1RSTR_WWDGRST 0x00000800U
Kojto	122:f9eeca106725	6861	#define RCC_APB1RSTR_SPI2RST 0x00004000U
Kojto	122:f9eeca106725	6862	#define RCC_APB1RSTR_SPI3RST 0x00008000U
Kojto	122:f9eeca106725	6863	#define RCC_APB1RSTR_USART2RST 0x00020000U
Kojto	122:f9eeca106725	6864	#define RCC_APB1RSTR_USART3RST 0x00040000U
Kojto	122:f9eeca106725	6865	#define RCC_APB1RSTR_UART4RST 0x00080000U
Kojto	122:f9eeca106725	6866	#define RCC_APB1RSTR_UART5RST 0x00100000U
Kojto	122:f9eeca106725	6867	#define RCC_APB1RSTR_I2C1RST 0x00200000U
Kojto	122:f9eeca106725	6868	#define RCC_APB1RSTR_I2C2RST 0x00400000U
Kojto	122:f9eeca106725	6869	#define RCC_APB1RSTR_I2C3RST 0x00800000U
Kojto	122:f9eeca106725	6870	#define RCC_APB1RSTR_CAN1RST 0x02000000U
Kojto	122:f9eeca106725	6871	#define RCC_APB1RSTR_CAN2RST 0x04000000U
Kojto	122:f9eeca106725	6872	#define RCC_APB1RSTR_PWRRST 0x10000000U
Kojto	122:f9eeca106725	6873	#define RCC_APB1RSTR_DACRST 0x20000000U
Kojto	122:f9eeca106725	6874	#define RCC_APB1RSTR_UART7RST 0x40000000U
Kojto	122:f9eeca106725	6875	#define RCC_APB1RSTR_UART8RST 0x80000000U
Kojto	110:165afa46840b	6876
Kojto	110:165afa46840b	6877	/****************** Bit definition for RCC_APB2RSTR register ************/
Kojto	122:f9eeca106725	6878	#define RCC_APB2RSTR_TIM1RST 0x00000001U
Kojto	122:f9eeca106725	6879	#define RCC_APB2RSTR_TIM8RST 0x00000002U
Kojto	122:f9eeca106725	6880	#define RCC_APB2RSTR_USART1RST 0x00000010U
Kojto	122:f9eeca106725	6881	#define RCC_APB2RSTR_USART6RST 0x00000020U
Kojto	122:f9eeca106725	6882	#define RCC_APB2RSTR_ADCRST 0x00000100U
Kojto	122:f9eeca106725	6883	#define RCC_APB2RSTR_SDIORST 0x00000800U
Kojto	122:f9eeca106725	6884	#define RCC_APB2RSTR_SPI1RST 0x00001000U
Kojto	122:f9eeca106725	6885	#define RCC_APB2RSTR_SPI4RST 0x00002000U
Kojto	122:f9eeca106725	6886	#define RCC_APB2RSTR_SYSCFGRST 0x00004000U
Kojto	122:f9eeca106725	6887	#define RCC_APB2RSTR_TIM9RST 0x00010000U
Kojto	122:f9eeca106725	6888	#define RCC_APB2RSTR_TIM10RST 0x00020000U
Kojto	122:f9eeca106725	6889	#define RCC_APB2RSTR_TIM11RST 0x00040000U
Kojto	122:f9eeca106725	6890	#define RCC_APB2RSTR_SPI5RST 0x00100000U
Kojto	122:f9eeca106725	6891	#define RCC_APB2RSTR_SPI6RST 0x00200000U
Kojto	122:f9eeca106725	6892	#define RCC_APB2RSTR_SAI1RST 0x00400000U
Kojto	122:f9eeca106725	6893	#define RCC_APB2RSTR_LTDCRST 0x04000000U
Kojto	122:f9eeca106725	6894	#define RCC_APB2RSTR_DSIRST 0x08000000U
Kojto	110:165afa46840b	6895
Kojto	110:165afa46840b	6896	/* Old SPI1RST bit definition, maintained for legacy purpose */
Kojto	110:165afa46840b	6897	#define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
Kojto	110:165afa46840b	6898
Kojto	110:165afa46840b	6899	/****************** Bit definition for RCC_AHB1ENR register *************/
Kojto	122:f9eeca106725	6900	#define RCC_AHB1ENR_GPIOAEN 0x00000001U
Kojto	122:f9eeca106725	6901	#define RCC_AHB1ENR_GPIOBEN 0x00000002U
Kojto	122:f9eeca106725	6902	#define RCC_AHB1ENR_GPIOCEN 0x00000004U
Kojto	122:f9eeca106725	6903	#define RCC_AHB1ENR_GPIODEN 0x00000008U
Kojto	122:f9eeca106725	6904	#define RCC_AHB1ENR_GPIOEEN 0x00000010U
Kojto	122:f9eeca106725	6905	#define RCC_AHB1ENR_GPIOFEN 0x00000020U
Kojto	122:f9eeca106725	6906	#define RCC_AHB1ENR_GPIOGEN 0x00000040U
Kojto	122:f9eeca106725	6907	#define RCC_AHB1ENR_GPIOHEN 0x00000080U
Kojto	122:f9eeca106725	6908	#define RCC_AHB1ENR_GPIOIEN 0x00000100U
Kojto	122:f9eeca106725	6909	#define RCC_AHB1ENR_GPIOJEN 0x00000200U
Kojto	122:f9eeca106725	6910	#define RCC_AHB1ENR_GPIOKEN 0x00000400U
Kojto	122:f9eeca106725	6911
Kojto	122:f9eeca106725	6912	#define RCC_AHB1ENR_CRCEN 0x00001000U
Kojto	122:f9eeca106725	6913	#define RCC_AHB1ENR_BKPSRAMEN 0x00040000U
Kojto	122:f9eeca106725	6914	#define RCC_AHB1ENR_CCMDATARAMEN 0x00100000U
Kojto	122:f9eeca106725	6915	#define RCC_AHB1ENR_DMA1EN 0x00200000U
Kojto	122:f9eeca106725	6916	#define RCC_AHB1ENR_DMA2EN 0x00400000U
Kojto	122:f9eeca106725	6917	#define RCC_AHB1ENR_DMA2DEN 0x00800000U
Kojto	122:f9eeca106725	6918
Kojto	122:f9eeca106725	6919	#define RCC_AHB1ENR_ETHMACEN 0x02000000U
Kojto	122:f9eeca106725	6920	#define RCC_AHB1ENR_ETHMACTXEN 0x04000000U
Kojto	122:f9eeca106725	6921	#define RCC_AHB1ENR_ETHMACRXEN 0x08000000U
Kojto	122:f9eeca106725	6922	#define RCC_AHB1ENR_ETHMACPTPEN 0x10000000U
Kojto	122:f9eeca106725	6923	#define RCC_AHB1ENR_OTGHSEN 0x20000000U
Kojto	122:f9eeca106725	6924	#define RCC_AHB1ENR_OTGHSULPIEN 0x40000000U
Kojto	110:165afa46840b	6925
Kojto	110:165afa46840b	6926	/****************** Bit definition for RCC_AHB2ENR register *************/
Kojto	122:f9eeca106725	6927	#define RCC_AHB2ENR_DCMIEN 0x00000001U
Kojto	122:f9eeca106725	6928	#define RCC_AHB2ENR_RNGEN 0x00000040U
Kojto	122:f9eeca106725	6929	#define RCC_AHB2ENR_OTGFSEN 0x00000080U
Kojto	110:165afa46840b	6930
Kojto	110:165afa46840b	6931	/****************** Bit definition for RCC_AHB3ENR register *************/
Kojto	122:f9eeca106725	6932	#define RCC_AHB3ENR_FMCEN 0x00000001U
Kojto	122:f9eeca106725	6933	#define RCC_AHB3ENR_QSPIEN 0x00000002U
Kojto	110:165afa46840b	6934
Kojto	110:165afa46840b	6935	/****************** Bit definition for RCC_APB1ENR register *************/
Kojto	122:f9eeca106725	6936	#define RCC_APB1ENR_TIM2EN 0x00000001U
Kojto	122:f9eeca106725	6937	#define RCC_APB1ENR_TIM3EN 0x00000002U
Kojto	122:f9eeca106725	6938	#define RCC_APB1ENR_TIM4EN 0x00000004U
Kojto	122:f9eeca106725	6939	#define RCC_APB1ENR_TIM5EN 0x00000008U
Kojto	122:f9eeca106725	6940	#define RCC_APB1ENR_TIM6EN 0x00000010U
Kojto	122:f9eeca106725	6941	#define RCC_APB1ENR_TIM7EN 0x00000020U
Kojto	122:f9eeca106725	6942	#define RCC_APB1ENR_TIM12EN 0x00000040U
Kojto	122:f9eeca106725	6943	#define RCC_APB1ENR_TIM13EN 0x00000080U
Kojto	122:f9eeca106725	6944	#define RCC_APB1ENR_TIM14EN 0x00000100U
Kojto	122:f9eeca106725	6945	#define RCC_APB1ENR_WWDGEN 0x00000800U
Kojto	122:f9eeca106725	6946	#define RCC_APB1ENR_SPI2EN 0x00004000U
Kojto	122:f9eeca106725	6947	#define RCC_APB1ENR_SPI3EN 0x00008000U
Kojto	122:f9eeca106725	6948	#define RCC_APB1ENR_USART2EN 0x00020000U
Kojto	122:f9eeca106725	6949	#define RCC_APB1ENR_USART3EN 0x00040000U
Kojto	122:f9eeca106725	6950	#define RCC_APB1ENR_UART4EN 0x00080000U
Kojto	122:f9eeca106725	6951	#define RCC_APB1ENR_UART5EN 0x00100000U
Kojto	122:f9eeca106725	6952	#define RCC_APB1ENR_I2C1EN 0x00200000U
Kojto	122:f9eeca106725	6953	#define RCC_APB1ENR_I2C2EN 0x00400000U
Kojto	122:f9eeca106725	6954	#define RCC_APB1ENR_I2C3EN 0x00800000U
Kojto	122:f9eeca106725	6955	#define RCC_APB1ENR_CAN1EN 0x02000000U
Kojto	122:f9eeca106725	6956	#define RCC_APB1ENR_CAN2EN 0x04000000U
Kojto	122:f9eeca106725	6957	#define RCC_APB1ENR_PWREN 0x10000000U
Kojto	122:f9eeca106725	6958	#define RCC_APB1ENR_DACEN 0x20000000U
Kojto	122:f9eeca106725	6959	#define RCC_APB1ENR_UART7EN 0x40000000U
Kojto	122:f9eeca106725	6960	#define RCC_APB1ENR_UART8EN 0x80000000U
Kojto	110:165afa46840b	6961
Kojto	110:165afa46840b	6962	/****************** Bit definition for RCC_APB2ENR register *************/
Kojto	122:f9eeca106725	6963	#define RCC_APB2ENR_TIM1EN 0x00000001U
Kojto	122:f9eeca106725	6964	#define RCC_APB2ENR_TIM8EN 0x00000002U
Kojto	122:f9eeca106725	6965	#define RCC_APB2ENR_USART1EN 0x00000010U
Kojto	122:f9eeca106725	6966	#define RCC_APB2ENR_USART6EN 0x00000020U
Kojto	122:f9eeca106725	6967	#define RCC_APB2ENR_ADC1EN 0x00000100U
Kojto	122:f9eeca106725	6968	#define RCC_APB2ENR_ADC2EN 0x00000200U
Kojto	122:f9eeca106725	6969	#define RCC_APB2ENR_ADC3EN 0x00000400U
Kojto	122:f9eeca106725	6970	#define RCC_APB2ENR_SDIOEN 0x00000800U
Kojto	122:f9eeca106725	6971	#define RCC_APB2ENR_SPI1EN 0x00001000U
Kojto	122:f9eeca106725	6972	#define RCC_APB2ENR_SPI4EN 0x00002000U
Kojto	122:f9eeca106725	6973	#define RCC_APB2ENR_SYSCFGEN 0x00004000U
Kojto	122:f9eeca106725	6974	#define RCC_APB2ENR_TIM9EN 0x00010000U
Kojto	122:f9eeca106725	6975	#define RCC_APB2ENR_TIM10EN 0x00020000U
Kojto	122:f9eeca106725	6976	#define RCC_APB2ENR_TIM11EN 0x00040000U
Kojto	122:f9eeca106725	6977	#define RCC_APB2ENR_SPI5EN 0x00100000U
Kojto	122:f9eeca106725	6978	#define RCC_APB2ENR_SPI6EN 0x00200000U
Kojto	122:f9eeca106725	6979	#define RCC_APB2ENR_SAI1EN 0x00400000U
Kojto	122:f9eeca106725	6980	#define RCC_APB2ENR_LTDCEN 0x04000000U
Kojto	122:f9eeca106725	6981	#define RCC_APB2ENR_DSIEN 0x08000000U
Kojto	110:165afa46840b	6982
Kojto	110:165afa46840b	6983	/****************** Bit definition for RCC_AHB1LPENR register ***********/
Kojto	122:f9eeca106725	6984	#define RCC_AHB1LPENR_GPIOALPEN 0x00000001U
Kojto	122:f9eeca106725	6985	#define RCC_AHB1LPENR_GPIOBLPEN 0x00000002U
Kojto	122:f9eeca106725	6986	#define RCC_AHB1LPENR_GPIOCLPEN 0x00000004U
Kojto	122:f9eeca106725	6987	#define RCC_AHB1LPENR_GPIODLPEN 0x00000008U
Kojto	122:f9eeca106725	6988	#define RCC_AHB1LPENR_GPIOELPEN 0x00000010U
Kojto	122:f9eeca106725	6989	#define RCC_AHB1LPENR_GPIOFLPEN 0x00000020U
Kojto	122:f9eeca106725	6990	#define RCC_AHB1LPENR_GPIOGLPEN 0x00000040U
Kojto	122:f9eeca106725	6991	#define RCC_AHB1LPENR_GPIOHLPEN 0x00000080U
Kojto	122:f9eeca106725	6992	#define RCC_AHB1LPENR_GPIOILPEN 0x00000100U
Kojto	122:f9eeca106725	6993	#define RCC_AHB1LPENR_GPIOJLPEN 0x00000200U
Kojto	122:f9eeca106725	6994	#define RCC_AHB1LPENR_GPIOKLPEN 0x00000400U
Kojto	122:f9eeca106725	6995
Kojto	122:f9eeca106725	6996	#define RCC_AHB1LPENR_CRCLPEN 0x00001000U
Kojto	122:f9eeca106725	6997	#define RCC_AHB1LPENR_FLITFLPEN 0x00008000U
Kojto	122:f9eeca106725	6998	#define RCC_AHB1LPENR_SRAM1LPEN 0x00010000U
Kojto	122:f9eeca106725	6999	#define RCC_AHB1LPENR_SRAM2LPEN 0x00020000U
Kojto	122:f9eeca106725	7000	#define RCC_AHB1LPENR_BKPSRAMLPEN 0x00040000U
Kojto	122:f9eeca106725	7001	#define RCC_AHB1LPENR_SRAM3LPEN 0x00080000U
Kojto	122:f9eeca106725	7002	#define RCC_AHB1LPENR_DMA1LPEN 0x00200000U
Kojto	122:f9eeca106725	7003	#define RCC_AHB1LPENR_DMA2LPEN 0x00400000U
Kojto	122:f9eeca106725	7004	#define RCC_AHB1LPENR_DMA2DLPEN 0x00800000U
Kojto	122:f9eeca106725	7005
Kojto	122:f9eeca106725	7006	#define RCC_AHB1LPENR_ETHMACLPEN 0x02000000U
Kojto	122:f9eeca106725	7007	#define RCC_AHB1LPENR_ETHMACTXLPEN 0x04000000U
Kojto	122:f9eeca106725	7008	#define RCC_AHB1LPENR_ETHMACRXLPEN 0x08000000U
Kojto	122:f9eeca106725	7009	#define RCC_AHB1LPENR_ETHMACPTPLPEN 0x10000000U
Kojto	122:f9eeca106725	7010	#define RCC_AHB1LPENR_OTGHSLPEN 0x20000000U
Kojto	122:f9eeca106725	7011	#define RCC_AHB1LPENR_OTGHSULPILPEN 0x40000000U
Kojto	110:165afa46840b	7012
Kojto	110:165afa46840b	7013	/****************** Bit definition for RCC_AHB2LPENR register ***********/
Kojto	122:f9eeca106725	7014	#define RCC_AHB2LPENR_DCMILPEN 0x00000001U
Kojto	122:f9eeca106725	7015	#define RCC_AHB2LPENR_RNGLPEN 0x00000040U
Kojto	122:f9eeca106725	7016	#define RCC_AHB2LPENR_OTGFSLPEN 0x00000080U
Kojto	110:165afa46840b	7017
Kojto	110:165afa46840b	7018	/****************** Bit definition for RCC_AHB3LPENR register ***********/
Kojto	122:f9eeca106725	7019	#define RCC_AHB3LPENR_FMCLPEN 0x00000001U
Kojto	122:f9eeca106725	7020	#define RCC_AHB3LPENR_QSPILPEN 0x00000002U
Kojto	110:165afa46840b	7021
Kojto	110:165afa46840b	7022	/****************** Bit definition for RCC_APB1LPENR register ***********/
Kojto	122:f9eeca106725	7023	#define RCC_APB1LPENR_TIM2LPEN 0x00000001U
Kojto	122:f9eeca106725	7024	#define RCC_APB1LPENR_TIM3LPEN 0x00000002U
Kojto	122:f9eeca106725	7025	#define RCC_APB1LPENR_TIM4LPEN 0x00000004U
Kojto	122:f9eeca106725	7026	#define RCC_APB1LPENR_TIM5LPEN 0x00000008U
Kojto	122:f9eeca106725	7027	#define RCC_APB1LPENR_TIM6LPEN 0x00000010U
Kojto	122:f9eeca106725	7028	#define RCC_APB1LPENR_TIM7LPEN 0x00000020U
Kojto	122:f9eeca106725	7029	#define RCC_APB1LPENR_TIM12LPEN 0x00000040U
Kojto	122:f9eeca106725	7030	#define RCC_APB1LPENR_TIM13LPEN 0x00000080U
Kojto	122:f9eeca106725	7031	#define RCC_APB1LPENR_TIM14LPEN 0x00000100U
Kojto	122:f9eeca106725	7032	#define RCC_APB1LPENR_WWDGLPEN 0x00000800U
Kojto	122:f9eeca106725	7033	#define RCC_APB1LPENR_SPI2LPEN 0x00004000U
Kojto	122:f9eeca106725	7034	#define RCC_APB1LPENR_SPI3LPEN 0x00008000U
Kojto	122:f9eeca106725	7035	#define RCC_APB1LPENR_USART2LPEN 0x00020000U
Kojto	122:f9eeca106725	7036	#define RCC_APB1LPENR_USART3LPEN 0x00040000U
Kojto	122:f9eeca106725	7037	#define RCC_APB1LPENR_UART4LPEN 0x00080000U
Kojto	122:f9eeca106725	7038	#define RCC_APB1LPENR_UART5LPEN 0x00100000U
Kojto	122:f9eeca106725	7039	#define RCC_APB1LPENR_I2C1LPEN 0x00200000U
Kojto	122:f9eeca106725	7040	#define RCC_APB1LPENR_I2C2LPEN 0x00400000U
Kojto	122:f9eeca106725	7041	#define RCC_APB1LPENR_I2C3LPEN 0x00800000U
Kojto	122:f9eeca106725	7042	#define RCC_APB1LPENR_CAN1LPEN 0x02000000U
Kojto	122:f9eeca106725	7043	#define RCC_APB1LPENR_CAN2LPEN 0x04000000U
Kojto	122:f9eeca106725	7044	#define RCC_APB1LPENR_PWRLPEN 0x10000000U
Kojto	122:f9eeca106725	7045	#define RCC_APB1LPENR_DACLPEN 0x20000000U
Kojto	122:f9eeca106725	7046	#define RCC_APB1LPENR_UART7LPEN 0x40000000U
Kojto	122:f9eeca106725	7047	#define RCC_APB1LPENR_UART8LPEN 0x80000000U
Kojto	110:165afa46840b	7048
Kojto	110:165afa46840b	7049	/****************** Bit definition for RCC_APB2LPENR register ***********/
Kojto	122:f9eeca106725	7050	#define RCC_APB2LPENR_TIM1LPEN 0x00000001U
Kojto	122:f9eeca106725	7051	#define RCC_APB2LPENR_TIM8LPEN 0x00000002U
Kojto	122:f9eeca106725	7052	#define RCC_APB2LPENR_USART1LPEN 0x00000010U
Kojto	122:f9eeca106725	7053	#define RCC_APB2LPENR_USART6LPEN 0x00000020U
Kojto	122:f9eeca106725	7054	#define RCC_APB2LPENR_ADC1LPEN 0x00000100U
Kojto	122:f9eeca106725	7055	#define RCC_APB2LPENR_ADC2LPEN 0x00000200U
Kojto	122:f9eeca106725	7056	#define RCC_APB2LPENR_ADC3LPEN 0x00000400U
Kojto	122:f9eeca106725	7057	#define RCC_APB2LPENR_SDIOLPEN 0x00000800U
Kojto	122:f9eeca106725	7058	#define RCC_APB2LPENR_SPI1LPEN 0x00001000U
Kojto	122:f9eeca106725	7059	#define RCC_APB2LPENR_SPI4LPEN 0x00002000U
Kojto	122:f9eeca106725	7060	#define RCC_APB2LPENR_SYSCFGLPEN 0x00004000U
Kojto	122:f9eeca106725	7061	#define RCC_APB2LPENR_TIM9LPEN 0x00010000U
Kojto	122:f9eeca106725	7062	#define RCC_APB2LPENR_TIM10LPEN 0x00020000U
Kojto	122:f9eeca106725	7063	#define RCC_APB2LPENR_TIM11LPEN 0x00040000U
Kojto	122:f9eeca106725	7064	#define RCC_APB2LPENR_SPI5LPEN 0x00100000U
Kojto	122:f9eeca106725	7065	#define RCC_APB2LPENR_SPI6LPEN 0x00200000U
Kojto	122:f9eeca106725	7066	#define RCC_APB2LPENR_SAI1LPEN 0x00400000U
Kojto	122:f9eeca106725	7067	#define RCC_APB2LPENR_LTDCLPEN 0x04000000U
Kojto	122:f9eeca106725	7068	#define RCC_APB2LPENR_DSILPEN 0x08000000U
Kojto	110:165afa46840b	7069
Kojto	110:165afa46840b	7070	/****************** Bit definition for RCC_BDCR register ****************/
Kojto	122:f9eeca106725	7071	#define RCC_BDCR_LSEON 0x00000001U
Kojto	122:f9eeca106725	7072	#define RCC_BDCR_LSERDY 0x00000002U
Kojto	122:f9eeca106725	7073	#define RCC_BDCR_LSEBYP 0x00000004U
Kojto	122:f9eeca106725	7074	#define RCC_BDCR_LSEMOD 0x00000008U
Kojto	122:f9eeca106725	7075
Kojto	122:f9eeca106725	7076	#define RCC_BDCR_RTCSEL 0x00000300U
Kojto	122:f9eeca106725	7077	#define RCC_BDCR_RTCSEL_0 0x00000100U
Kojto	122:f9eeca106725	7078	#define RCC_BDCR_RTCSEL_1 0x00000200U
Kojto	122:f9eeca106725	7079
Kojto	122:f9eeca106725	7080	#define RCC_BDCR_RTCEN 0x00008000U
Kojto	122:f9eeca106725	7081	#define RCC_BDCR_BDRST 0x00010000U
Kojto	110:165afa46840b	7082
Kojto	110:165afa46840b	7083	/****************** Bit definition for RCC_CSR register *****************/
Kojto	122:f9eeca106725	7084	#define RCC_CSR_LSION 0x00000001U
Kojto	122:f9eeca106725	7085	#define RCC_CSR_LSIRDY 0x00000002U
Kojto	122:f9eeca106725	7086	#define RCC_CSR_RMVF 0x01000000U
Kojto	122:f9eeca106725	7087	#define RCC_CSR_BORRSTF 0x02000000U
Kojto	122:f9eeca106725	7088	#define RCC_CSR_PADRSTF 0x04000000U
Kojto	122:f9eeca106725	7089	#define RCC_CSR_PORRSTF 0x08000000U
Kojto	122:f9eeca106725	7090	#define RCC_CSR_SFTRSTF 0x10000000U
Kojto	122:f9eeca106725	7091	#define RCC_CSR_WDGRSTF 0x20000000U
Kojto	122:f9eeca106725	7092	#define RCC_CSR_WWDGRSTF 0x40000000U
Kojto	122:f9eeca106725	7093	#define RCC_CSR_LPWRRSTF 0x80000000U
Kojto	110:165afa46840b	7094
Kojto	110:165afa46840b	7095	/****************** Bit definition for RCC_SSCGR register ***************/
Kojto	122:f9eeca106725	7096	#define RCC_SSCGR_MODPER 0x00001FFFU
Kojto	122:f9eeca106725	7097	#define RCC_SSCGR_INCSTEP 0x0FFFE000U
Kojto	122:f9eeca106725	7098	#define RCC_SSCGR_SPREADSEL 0x40000000U
Kojto	122:f9eeca106725	7099	#define RCC_SSCGR_SSCGEN 0x80000000U
Kojto	110:165afa46840b	7100
Kojto	110:165afa46840b	7101	/****************** Bit definition for RCC_PLLI2SCFGR register **********/
Kojto	122:f9eeca106725	7102	#define RCC_PLLI2SCFGR_PLLI2SN 0x00007FC0U
Kojto	122:f9eeca106725	7103	#define RCC_PLLI2SCFGR_PLLI2SN_0 0x00000040U
Kojto	122:f9eeca106725	7104	#define RCC_PLLI2SCFGR_PLLI2SN_1 0x00000080U
Kojto	122:f9eeca106725	7105	#define RCC_PLLI2SCFGR_PLLI2SN_2 0x00000100U
Kojto	122:f9eeca106725	7106	#define RCC_PLLI2SCFGR_PLLI2SN_3 0x00000200U
Kojto	122:f9eeca106725	7107	#define RCC_PLLI2SCFGR_PLLI2SN_4 0x00000400U
Kojto	122:f9eeca106725	7108	#define RCC_PLLI2SCFGR_PLLI2SN_5 0x00000800U
Kojto	122:f9eeca106725	7109	#define RCC_PLLI2SCFGR_PLLI2SN_6 0x00001000U
Kojto	122:f9eeca106725	7110	#define RCC_PLLI2SCFGR_PLLI2SN_7 0x00002000U
Kojto	122:f9eeca106725	7111	#define RCC_PLLI2SCFGR_PLLI2SN_8 0x00004000U
Kojto	122:f9eeca106725	7112
Kojto	122:f9eeca106725	7113	#define RCC_PLLI2SCFGR_PLLI2SQ 0x0F000000U
Kojto	122:f9eeca106725	7114	#define RCC_PLLI2SCFGR_PLLI2SQ_0 0x01000000U
Kojto	122:f9eeca106725	7115	#define RCC_PLLI2SCFGR_PLLI2SQ_1 0x02000000U
Kojto	122:f9eeca106725	7116	#define RCC_PLLI2SCFGR_PLLI2SQ_2 0x04000000U
Kojto	122:f9eeca106725	7117	#define RCC_PLLI2SCFGR_PLLI2SQ_3 0x08000000U
Kojto	122:f9eeca106725	7118
Kojto	122:f9eeca106725	7119	#define RCC_PLLI2SCFGR_PLLI2SR 0x70000000U
Kojto	122:f9eeca106725	7120	#define RCC_PLLI2SCFGR_PLLI2SR_0 0x10000000U
Kojto	122:f9eeca106725	7121	#define RCC_PLLI2SCFGR_PLLI2SR_1 0x20000000U
Kojto	122:f9eeca106725	7122	#define RCC_PLLI2SCFGR_PLLI2SR_2 0x40000000U
Kojto	110:165afa46840b	7123
Kojto	110:165afa46840b	7124
Kojto	110:165afa46840b	7125	/****************** Bit definition for RCC_PLLSAICFGR register **********/
Kojto	122:f9eeca106725	7126	#define RCC_PLLSAICFGR_PLLSAIN 0x00007FC0U
Kojto	122:f9eeca106725	7127	#define RCC_PLLSAICFGR_PLLSAIN_0 0x00000040U
Kojto	122:f9eeca106725	7128	#define RCC_PLLSAICFGR_PLLSAIN_1 0x00000080U
Kojto	122:f9eeca106725	7129	#define RCC_PLLSAICFGR_PLLSAIN_2 0x00000100U
Kojto	122:f9eeca106725	7130	#define RCC_PLLSAICFGR_PLLSAIN_3 0x00000200U
Kojto	122:f9eeca106725	7131	#define RCC_PLLSAICFGR_PLLSAIN_4 0x00000400U
Kojto	122:f9eeca106725	7132	#define RCC_PLLSAICFGR_PLLSAIN_5 0x00000800U
Kojto	122:f9eeca106725	7133	#define RCC_PLLSAICFGR_PLLSAIN_6 0x00001000U
Kojto	122:f9eeca106725	7134	#define RCC_PLLSAICFGR_PLLSAIN_7 0x00002000U
Kojto	122:f9eeca106725	7135	#define RCC_PLLSAICFGR_PLLSAIN_8 0x00004000U
Kojto	122:f9eeca106725	7136
Kojto	122:f9eeca106725	7137	#define RCC_PLLSAICFGR_PLLSAIP 0x00030000U
Kojto	122:f9eeca106725	7138	#define RCC_PLLSAICFGR_PLLSAIP_0 0x00010000U
Kojto	122:f9eeca106725	7139	#define RCC_PLLSAICFGR_PLLSAIP_1 0x00020000U
Kojto	122:f9eeca106725	7140
Kojto	122:f9eeca106725	7141	#define RCC_PLLSAICFGR_PLLSAIQ 0x0F000000U
Kojto	122:f9eeca106725	7142	#define RCC_PLLSAICFGR_PLLSAIQ_0 0x01000000U
Kojto	122:f9eeca106725	7143	#define RCC_PLLSAICFGR_PLLSAIQ_1 0x02000000U
Kojto	122:f9eeca106725	7144	#define RCC_PLLSAICFGR_PLLSAIQ_2 0x04000000U
Kojto	122:f9eeca106725	7145	#define RCC_PLLSAICFGR_PLLSAIQ_3 0x08000000U
Kojto	122:f9eeca106725	7146
Kojto	122:f9eeca106725	7147	#define RCC_PLLSAICFGR_PLLSAIR 0x70000000U
Kojto	122:f9eeca106725	7148	#define RCC_PLLSAICFGR_PLLSAIR_0 0x10000000U
Kojto	122:f9eeca106725	7149	#define RCC_PLLSAICFGR_PLLSAIR_1 0x20000000U
Kojto	122:f9eeca106725	7150	#define RCC_PLLSAICFGR_PLLSAIR_2 0x40000000U
Kojto	110:165afa46840b	7151
Kojto	110:165afa46840b	7152	/****************** Bit definition for RCC_DCKCFGR register *************/
Kojto	122:f9eeca106725	7153	#define RCC_DCKCFGR_PLLI2SDIVQ 0x0000001FU
Kojto	122:f9eeca106725	7154	#define RCC_DCKCFGR_PLLSAIDIVQ 0x00001F00U
Kojto	122:f9eeca106725	7155	#define RCC_DCKCFGR_PLLSAIDIVR 0x00030000U
Kojto	122:f9eeca106725	7156	#define RCC_DCKCFGR_SAI1ASRC 0x00300000U
Kojto	122:f9eeca106725	7157	#define RCC_DCKCFGR_SAI1ASRC_0 0x00100000U
Kojto	122:f9eeca106725	7158	#define RCC_DCKCFGR_SAI1ASRC_1 0x00200000U
Kojto	122:f9eeca106725	7159	#define RCC_DCKCFGR_SAI1BSRC 0x00C00000U
Kojto	122:f9eeca106725	7160	#define RCC_DCKCFGR_SAI1BSRC_0 0x00400000U
Kojto	122:f9eeca106725	7161	#define RCC_DCKCFGR_SAI1BSRC_1 0x00800000U
Kojto	122:f9eeca106725	7162	#define RCC_DCKCFGR_TIMPRE 0x01000000U
Kojto	122:f9eeca106725	7163	#define RCC_DCKCFGR_CK48MSEL 0x08000000U
Kojto	122:f9eeca106725	7164	#define RCC_DCKCFGR_SDIOSEL 0x10000000U
Kojto	122:f9eeca106725	7165	#define RCC_DCKCFGR_DSISEL 0x20000000U
Kojto	110:165afa46840b	7166
Kojto	110:165afa46840b	7167	/******************************************************************************/
Kojto	110:165afa46840b	7168	/* */
Kojto	110:165afa46840b	7169	/* RNG */
Kojto	110:165afa46840b	7170	/* */
Kojto	110:165afa46840b	7171	/******************************************************************************/
Kojto	110:165afa46840b	7172	/****************** Bits definition for RNG_CR register *****************/
Kojto	122:f9eeca106725	7173	#define RNG_CR_RNGEN 0x00000004U
Kojto	122:f9eeca106725	7174	#define RNG_CR_IE 0x00000008U
Kojto	110:165afa46840b	7175
Kojto	110:165afa46840b	7176	/****************** Bits definition for RNG_SR register *****************/
Kojto	122:f9eeca106725	7177	#define RNG_SR_DRDY 0x00000001U
Kojto	122:f9eeca106725	7178	#define RNG_SR_CECS 0x00000002U
Kojto	122:f9eeca106725	7179	#define RNG_SR_SECS 0x00000004U
Kojto	122:f9eeca106725	7180	#define RNG_SR_CEIS 0x00000020U
Kojto	122:f9eeca106725	7181	#define RNG_SR_SEIS 0x00000040U
Kojto	110:165afa46840b	7182
Kojto	110:165afa46840b	7183	/******************************************************************************/
Kojto	110:165afa46840b	7184	/* */
Kojto	110:165afa46840b	7185	/* Real-Time Clock (RTC) */
Kojto	110:165afa46840b	7186	/* */
Kojto	110:165afa46840b	7187	/******************************************************************************/
Kojto	110:165afa46840b	7188	/****************** Bits definition for RTC_TR register *****************/
Kojto	122:f9eeca106725	7189	#define RTC_TR_PM 0x00400000U
Kojto	122:f9eeca106725	7190	#define RTC_TR_HT 0x00300000U
Kojto	122:f9eeca106725	7191	#define RTC_TR_HT_0 0x00100000U
Kojto	122:f9eeca106725	7192	#define RTC_TR_HT_1 0x00200000U
Kojto	122:f9eeca106725	7193	#define RTC_TR_HU 0x000F0000U
Kojto	122:f9eeca106725	7194	#define RTC_TR_HU_0 0x00010000U
Kojto	122:f9eeca106725	7195	#define RTC_TR_HU_1 0x00020000U
Kojto	122:f9eeca106725	7196	#define RTC_TR_HU_2 0x00040000U
Kojto	122:f9eeca106725	7197	#define RTC_TR_HU_3 0x00080000U
Kojto	122:f9eeca106725	7198	#define RTC_TR_MNT 0x00007000U
Kojto	122:f9eeca106725	7199	#define RTC_TR_MNT_0 0x00001000U
Kojto	122:f9eeca106725	7200	#define RTC_TR_MNT_1 0x00002000U
Kojto	122:f9eeca106725	7201	#define RTC_TR_MNT_2 0x00004000U
Kojto	122:f9eeca106725	7202	#define RTC_TR_MNU 0x00000F00U
Kojto	122:f9eeca106725	7203	#define RTC_TR_MNU_0 0x00000100U
Kojto	122:f9eeca106725	7204	#define RTC_TR_MNU_1 0x00000200U
Kojto	122:f9eeca106725	7205	#define RTC_TR_MNU_2 0x00000400U
Kojto	122:f9eeca106725	7206	#define RTC_TR_MNU_3 0x00000800U
Kojto	122:f9eeca106725	7207	#define RTC_TR_ST 0x00000070U
Kojto	122:f9eeca106725	7208	#define RTC_TR_ST_0 0x00000010U
Kojto	122:f9eeca106725	7209	#define RTC_TR_ST_1 0x00000020U
Kojto	122:f9eeca106725	7210	#define RTC_TR_ST_2 0x00000040U
Kojto	122:f9eeca106725	7211	#define RTC_TR_SU 0x0000000FU
Kojto	122:f9eeca106725	7212	#define RTC_TR_SU_0 0x00000001U
Kojto	122:f9eeca106725	7213	#define RTC_TR_SU_1 0x00000002U
Kojto	122:f9eeca106725	7214	#define RTC_TR_SU_2 0x00000004U
Kojto	122:f9eeca106725	7215	#define RTC_TR_SU_3 0x00000008U
Kojto	110:165afa46840b	7216
Kojto	110:165afa46840b	7217	/****************** Bits definition for RTC_DR register *****************/
Kojto	122:f9eeca106725	7218	#define RTC_DR_YT 0x00F00000U
Kojto	122:f9eeca106725	7219	#define RTC_DR_YT_0 0x00100000U
Kojto	122:f9eeca106725	7220	#define RTC_DR_YT_1 0x00200000U
Kojto	122:f9eeca106725	7221	#define RTC_DR_YT_2 0x00400000U
Kojto	122:f9eeca106725	7222	#define RTC_DR_YT_3 0x00800000U
Kojto	122:f9eeca106725	7223	#define RTC_DR_YU 0x000F0000U
Kojto	122:f9eeca106725	7224	#define RTC_DR_YU_0 0x00010000U
Kojto	122:f9eeca106725	7225	#define RTC_DR_YU_1 0x00020000U
Kojto	122:f9eeca106725	7226	#define RTC_DR_YU_2 0x00040000U
Kojto	122:f9eeca106725	7227	#define RTC_DR_YU_3 0x00080000U
Kojto	122:f9eeca106725	7228	#define RTC_DR_WDU 0x0000E000U
Kojto	122:f9eeca106725	7229	#define RTC_DR_WDU_0 0x00002000U
Kojto	122:f9eeca106725	7230	#define RTC_DR_WDU_1 0x00004000U
Kojto	122:f9eeca106725	7231	#define RTC_DR_WDU_2 0x00008000U
Kojto	122:f9eeca106725	7232	#define RTC_DR_MT 0x00001000U
Kojto	122:f9eeca106725	7233	#define RTC_DR_MU 0x00000F00U
Kojto	122:f9eeca106725	7234	#define RTC_DR_MU_0 0x00000100U
Kojto	122:f9eeca106725	7235	#define RTC_DR_MU_1 0x00000200U
Kojto	122:f9eeca106725	7236	#define RTC_DR_MU_2 0x00000400U
Kojto	122:f9eeca106725	7237	#define RTC_DR_MU_3 0x00000800U
Kojto	122:f9eeca106725	7238	#define RTC_DR_DT 0x00000030U
Kojto	122:f9eeca106725	7239	#define RTC_DR_DT_0 0x00000010U
Kojto	122:f9eeca106725	7240	#define RTC_DR_DT_1 0x00000020U
Kojto	122:f9eeca106725	7241	#define RTC_DR_DU 0x0000000FU
Kojto	122:f9eeca106725	7242	#define RTC_DR_DU_0 0x00000001U
Kojto	122:f9eeca106725	7243	#define RTC_DR_DU_1 0x00000002U
Kojto	122:f9eeca106725	7244	#define RTC_DR_DU_2 0x00000004U
Kojto	122:f9eeca106725	7245	#define RTC_DR_DU_3 0x00000008U
Kojto	110:165afa46840b	7246
Kojto	110:165afa46840b	7247	/****************** Bits definition for RTC_CR register *****************/
Kojto	122:f9eeca106725	7248	#define RTC_CR_COE 0x00800000U
Kojto	122:f9eeca106725	7249	#define RTC_CR_OSEL 0x00600000U
Kojto	122:f9eeca106725	7250	#define RTC_CR_OSEL_0 0x00200000U
Kojto	122:f9eeca106725	7251	#define RTC_CR_OSEL_1 0x00400000U
Kojto	122:f9eeca106725	7252	#define RTC_CR_POL 0x00100000U
Kojto	122:f9eeca106725	7253	#define RTC_CR_COSEL 0x00080000U
Kojto	122:f9eeca106725	7254	#define RTC_CR_BCK 0x00040000U
Kojto	122:f9eeca106725	7255	#define RTC_CR_SUB1H 0x00020000U
Kojto	122:f9eeca106725	7256	#define RTC_CR_ADD1H 0x00010000U
Kojto	122:f9eeca106725	7257	#define RTC_CR_TSIE 0x00008000U
Kojto	122:f9eeca106725	7258	#define RTC_CR_WUTIE 0x00004000U
Kojto	122:f9eeca106725	7259	#define RTC_CR_ALRBIE 0x00002000U
Kojto	122:f9eeca106725	7260	#define RTC_CR_ALRAIE 0x00001000U
Kojto	122:f9eeca106725	7261	#define RTC_CR_TSE 0x00000800U
Kojto	122:f9eeca106725	7262	#define RTC_CR_WUTE 0x00000400U
Kojto	122:f9eeca106725	7263	#define RTC_CR_ALRBE 0x00000200U
Kojto	122:f9eeca106725	7264	#define RTC_CR_ALRAE 0x00000100U
Kojto	122:f9eeca106725	7265	#define RTC_CR_DCE 0x00000080U
Kojto	122:f9eeca106725	7266	#define RTC_CR_FMT 0x00000040U
Kojto	122:f9eeca106725	7267	#define RTC_CR_BYPSHAD 0x00000020U
Kojto	122:f9eeca106725	7268	#define RTC_CR_REFCKON 0x00000010U
Kojto	122:f9eeca106725	7269	#define RTC_CR_TSEDGE 0x00000008U
Kojto	122:f9eeca106725	7270	#define RTC_CR_WUCKSEL 0x00000007U
Kojto	122:f9eeca106725	7271	#define RTC_CR_WUCKSEL_0 0x00000001U
Kojto	122:f9eeca106725	7272	#define RTC_CR_WUCKSEL_1 0x00000002U
Kojto	122:f9eeca106725	7273	#define RTC_CR_WUCKSEL_2 0x00000004U
Kojto	110:165afa46840b	7274
Kojto	110:165afa46840b	7275	/****************** Bits definition for RTC_ISR register ****************/
Kojto	122:f9eeca106725	7276	#define RTC_ISR_RECALPF 0x00010000U
Kojto	122:f9eeca106725	7277	#define RTC_ISR_TAMP1F 0x00002000U
Kojto	122:f9eeca106725	7278	#define RTC_ISR_TAMP2F 0x00004000U
Kojto	122:f9eeca106725	7279	#define RTC_ISR_TSOVF 0x00001000U
Kojto	122:f9eeca106725	7280	#define RTC_ISR_TSF 0x00000800U
Kojto	122:f9eeca106725	7281	#define RTC_ISR_WUTF 0x00000400U
Kojto	122:f9eeca106725	7282	#define RTC_ISR_ALRBF 0x00000200U
Kojto	122:f9eeca106725	7283	#define RTC_ISR_ALRAF 0x00000100U
Kojto	122:f9eeca106725	7284	#define RTC_ISR_INIT 0x00000080U
Kojto	122:f9eeca106725	7285	#define RTC_ISR_INITF 0x00000040U
Kojto	122:f9eeca106725	7286	#define RTC_ISR_RSF 0x00000020U
Kojto	122:f9eeca106725	7287	#define RTC_ISR_INITS 0x00000010U
Kojto	122:f9eeca106725	7288	#define RTC_ISR_SHPF 0x00000008U
Kojto	122:f9eeca106725	7289	#define RTC_ISR_WUTWF 0x00000004U
Kojto	122:f9eeca106725	7290	#define RTC_ISR_ALRBWF 0x00000002U
Kojto	122:f9eeca106725	7291	#define RTC_ISR_ALRAWF 0x00000001U
Kojto	110:165afa46840b	7292
Kojto	110:165afa46840b	7293	/****************** Bits definition for RTC_PRER register ***************/
Kojto	122:f9eeca106725	7294	#define RTC_PRER_PREDIV_A 0x007F0000U
Kojto	122:f9eeca106725	7295	#define RTC_PRER_PREDIV_S 0x00007FFFU
Kojto	110:165afa46840b	7296
Kojto	110:165afa46840b	7297	/****************** Bits definition for RTC_WUTR register ***************/
Kojto	122:f9eeca106725	7298	#define RTC_WUTR_WUT 0x0000FFFFU
Kojto	110:165afa46840b	7299
Kojto	110:165afa46840b	7300	/****************** Bits definition for RTC_CALIBR register *************/
Kojto	122:f9eeca106725	7301	#define RTC_CALIBR_DCS 0x00000080U
Kojto	122:f9eeca106725	7302	#define RTC_CALIBR_DC 0x0000001FU
Kojto	110:165afa46840b	7303
Kojto	110:165afa46840b	7304	/****************** Bits definition for RTC_ALRMAR register *************/
Kojto	122:f9eeca106725	7305	#define RTC_ALRMAR_MSK4 0x80000000U
Kojto	122:f9eeca106725	7306	#define RTC_ALRMAR_WDSEL 0x40000000U
Kojto	122:f9eeca106725	7307	#define RTC_ALRMAR_DT 0x30000000U
Kojto	122:f9eeca106725	7308	#define RTC_ALRMAR_DT_0 0x10000000U
Kojto	122:f9eeca106725	7309	#define RTC_ALRMAR_DT_1 0x20000000U
Kojto	122:f9eeca106725	7310	#define RTC_ALRMAR_DU 0x0F000000U
Kojto	122:f9eeca106725	7311	#define RTC_ALRMAR_DU_0 0x01000000U
Kojto	122:f9eeca106725	7312	#define RTC_ALRMAR_DU_1 0x02000000U
Kojto	122:f9eeca106725	7313	#define RTC_ALRMAR_DU_2 0x04000000U
Kojto	122:f9eeca106725	7314	#define RTC_ALRMAR_DU_3 0x08000000U
Kojto	122:f9eeca106725	7315	#define RTC_ALRMAR_MSK3 0x00800000U
Kojto	122:f9eeca106725	7316	#define RTC_ALRMAR_PM 0x00400000U
Kojto	122:f9eeca106725	7317	#define RTC_ALRMAR_HT 0x00300000U
Kojto	122:f9eeca106725	7318	#define RTC_ALRMAR_HT_0 0x00100000U
Kojto	122:f9eeca106725	7319	#define RTC_ALRMAR_HT_1 0x00200000U
Kojto	122:f9eeca106725	7320	#define RTC_ALRMAR_HU 0x000F0000U
Kojto	122:f9eeca106725	7321	#define RTC_ALRMAR_HU_0 0x00010000U
Kojto	122:f9eeca106725	7322	#define RTC_ALRMAR_HU_1 0x00020000U
Kojto	122:f9eeca106725	7323	#define RTC_ALRMAR_HU_2 0x00040000U
Kojto	122:f9eeca106725	7324	#define RTC_ALRMAR_HU_3 0x00080000U
Kojto	122:f9eeca106725	7325	#define RTC_ALRMAR_MSK2 0x00008000U
Kojto	122:f9eeca106725	7326	#define RTC_ALRMAR_MNT 0x00007000U
Kojto	122:f9eeca106725	7327	#define RTC_ALRMAR_MNT_0 0x00001000U
Kojto	122:f9eeca106725	7328	#define RTC_ALRMAR_MNT_1 0x00002000U
Kojto	122:f9eeca106725	7329	#define RTC_ALRMAR_MNT_2 0x00004000U
Kojto	122:f9eeca106725	7330	#define RTC_ALRMAR_MNU 0x00000F00U
Kojto	122:f9eeca106725	7331	#define RTC_ALRMAR_MNU_0 0x00000100U
Kojto	122:f9eeca106725	7332	#define RTC_ALRMAR_MNU_1 0x00000200U
Kojto	122:f9eeca106725	7333	#define RTC_ALRMAR_MNU_2 0x00000400U
Kojto	122:f9eeca106725	7334	#define RTC_ALRMAR_MNU_3 0x00000800U
Kojto	122:f9eeca106725	7335	#define RTC_ALRMAR_MSK1 0x00000080U
Kojto	122:f9eeca106725	7336	#define RTC_ALRMAR_ST 0x00000070U
Kojto	122:f9eeca106725	7337	#define RTC_ALRMAR_ST_0 0x00000010U
Kojto	122:f9eeca106725	7338	#define RTC_ALRMAR_ST_1 0x00000020U
Kojto	122:f9eeca106725	7339	#define RTC_ALRMAR_ST_2 0x00000040U
Kojto	122:f9eeca106725	7340	#define RTC_ALRMAR_SU 0x0000000FU
Kojto	122:f9eeca106725	7341	#define RTC_ALRMAR_SU_0 0x00000001U
Kojto	122:f9eeca106725	7342	#define RTC_ALRMAR_SU_1 0x00000002U
Kojto	122:f9eeca106725	7343	#define RTC_ALRMAR_SU_2 0x00000004U
Kojto	122:f9eeca106725	7344	#define RTC_ALRMAR_SU_3 0x00000008U
Kojto	110:165afa46840b	7345
Kojto	110:165afa46840b	7346	/****************** Bits definition for RTC_ALRMBR register *************/
Kojto	122:f9eeca106725	7347	#define RTC_ALRMBR_MSK4 0x80000000U
Kojto	122:f9eeca106725	7348	#define RTC_ALRMBR_WDSEL 0x40000000U
Kojto	122:f9eeca106725	7349	#define RTC_ALRMBR_DT 0x30000000U
Kojto	122:f9eeca106725	7350	#define RTC_ALRMBR_DT_0 0x10000000U
Kojto	122:f9eeca106725	7351	#define RTC_ALRMBR_DT_1 0x20000000U
Kojto	122:f9eeca106725	7352	#define RTC_ALRMBR_DU 0x0F000000U
Kojto	122:f9eeca106725	7353	#define RTC_ALRMBR_DU_0 0x01000000U
Kojto	122:f9eeca106725	7354	#define RTC_ALRMBR_DU_1 0x02000000U
Kojto	122:f9eeca106725	7355	#define RTC_ALRMBR_DU_2 0x04000000U
Kojto	122:f9eeca106725	7356	#define RTC_ALRMBR_DU_3 0x08000000U
Kojto	122:f9eeca106725	7357	#define RTC_ALRMBR_MSK3 0x00800000U
Kojto	122:f9eeca106725	7358	#define RTC_ALRMBR_PM 0x00400000U
Kojto	122:f9eeca106725	7359	#define RTC_ALRMBR_HT 0x00300000U
Kojto	122:f9eeca106725	7360	#define RTC_ALRMBR_HT_0 0x00100000U
Kojto	122:f9eeca106725	7361	#define RTC_ALRMBR_HT_1 0x00200000U
Kojto	122:f9eeca106725	7362	#define RTC_ALRMBR_HU 0x000F0000U
Kojto	122:f9eeca106725	7363	#define RTC_ALRMBR_HU_0 0x00010000U
Kojto	122:f9eeca106725	7364	#define RTC_ALRMBR_HU_1 0x00020000U
Kojto	122:f9eeca106725	7365	#define RTC_ALRMBR_HU_2 0x00040000U
Kojto	122:f9eeca106725	7366	#define RTC_ALRMBR_HU_3 0x00080000U
Kojto	122:f9eeca106725	7367	#define RTC_ALRMBR_MSK2 0x00008000U
Kojto	122:f9eeca106725	7368	#define RTC_ALRMBR_MNT 0x00007000U
Kojto	122:f9eeca106725	7369	#define RTC_ALRMBR_MNT_0 0x00001000U
Kojto	122:f9eeca106725	7370	#define RTC_ALRMBR_MNT_1 0x00002000U
Kojto	122:f9eeca106725	7371	#define RTC_ALRMBR_MNT_2 0x00004000U
Kojto	122:f9eeca106725	7372	#define RTC_ALRMBR_MNU 0x00000F00U
Kojto	122:f9eeca106725	7373	#define RTC_ALRMBR_MNU_0 0x00000100U
Kojto	122:f9eeca106725	7374	#define RTC_ALRMBR_MNU_1 0x00000200U
Kojto	122:f9eeca106725	7375	#define RTC_ALRMBR_MNU_2 0x00000400U
Kojto	122:f9eeca106725	7376	#define RTC_ALRMBR_MNU_3 0x00000800U
Kojto	122:f9eeca106725	7377	#define RTC_ALRMBR_MSK1 0x00000080U
Kojto	122:f9eeca106725	7378	#define RTC_ALRMBR_ST 0x00000070U
Kojto	122:f9eeca106725	7379	#define RTC_ALRMBR_ST_0 0x00000010U
Kojto	122:f9eeca106725	7380	#define RTC_ALRMBR_ST_1 0x00000020U
Kojto	122:f9eeca106725	7381	#define RTC_ALRMBR_ST_2 0x00000040U
Kojto	122:f9eeca106725	7382	#define RTC_ALRMBR_SU 0x0000000FU
Kojto	122:f9eeca106725	7383	#define RTC_ALRMBR_SU_0 0x00000001U
Kojto	122:f9eeca106725	7384	#define RTC_ALRMBR_SU_1 0x00000002U
Kojto	122:f9eeca106725	7385	#define RTC_ALRMBR_SU_2 0x00000004U
Kojto	122:f9eeca106725	7386	#define RTC_ALRMBR_SU_3 0x00000008U
Kojto	110:165afa46840b	7387
Kojto	110:165afa46840b	7388	/****************** Bits definition for RTC_WPR register ****************/
Kojto	122:f9eeca106725	7389	#define RTC_WPR_KEY 0x000000FFU
Kojto	110:165afa46840b	7390
Kojto	110:165afa46840b	7391	/****************** Bits definition for RTC_SSR register ****************/
Kojto	122:f9eeca106725	7392	#define RTC_SSR_SS 0x0000FFFFU
Kojto	110:165afa46840b	7393
Kojto	110:165afa46840b	7394	/****************** Bits definition for RTC_SHIFTR register *************/
Kojto	122:f9eeca106725	7395	#define RTC_SHIFTR_SUBFS 0x00007FFFU
Kojto	122:f9eeca106725	7396	#define RTC_SHIFTR_ADD1S 0x80000000U
Kojto	110:165afa46840b	7397
Kojto	110:165afa46840b	7398	/****************** Bits definition for RTC_TSTR register ***************/
Kojto	122:f9eeca106725	7399	#define RTC_TSTR_PM 0x00400000U
Kojto	122:f9eeca106725	7400	#define RTC_TSTR_HT 0x00300000U
Kojto	122:f9eeca106725	7401	#define RTC_TSTR_HT_0 0x00100000U
Kojto	122:f9eeca106725	7402	#define RTC_TSTR_HT_1 0x00200000U
Kojto	122:f9eeca106725	7403	#define RTC_TSTR_HU 0x000F0000U
Kojto	122:f9eeca106725	7404	#define RTC_TSTR_HU_0 0x00010000U
Kojto	122:f9eeca106725	7405	#define RTC_TSTR_HU_1 0x00020000U
Kojto	122:f9eeca106725	7406	#define RTC_TSTR_HU_2 0x00040000U
Kojto	122:f9eeca106725	7407	#define RTC_TSTR_HU_3 0x00080000U
Kojto	122:f9eeca106725	7408	#define RTC_TSTR_MNT 0x00007000U
Kojto	122:f9eeca106725	7409	#define RTC_TSTR_MNT_0 0x00001000U
Kojto	122:f9eeca106725	7410	#define RTC_TSTR_MNT_1 0x00002000U
Kojto	122:f9eeca106725	7411	#define RTC_TSTR_MNT_2 0x00004000U
Kojto	122:f9eeca106725	7412	#define RTC_TSTR_MNU 0x00000F00U
Kojto	122:f9eeca106725	7413	#define RTC_TSTR_MNU_0 0x00000100U
Kojto	122:f9eeca106725	7414	#define RTC_TSTR_MNU_1 0x00000200U
Kojto	122:f9eeca106725	7415	#define RTC_TSTR_MNU_2 0x00000400U
Kojto	122:f9eeca106725	7416	#define RTC_TSTR_MNU_3 0x00000800U
Kojto	122:f9eeca106725	7417	#define RTC_TSTR_ST 0x00000070U
Kojto	122:f9eeca106725	7418	#define RTC_TSTR_ST_0 0x00000010U
Kojto	122:f9eeca106725	7419	#define RTC_TSTR_ST_1 0x00000020U
Kojto	122:f9eeca106725	7420	#define RTC_TSTR_ST_2 0x00000040U
Kojto	122:f9eeca106725	7421	#define RTC_TSTR_SU 0x0000000FU
Kojto	122:f9eeca106725	7422	#define RTC_TSTR_SU_0 0x00000001U
Kojto	122:f9eeca106725	7423	#define RTC_TSTR_SU_1 0x00000002U
Kojto	122:f9eeca106725	7424	#define RTC_TSTR_SU_2 0x00000004U
Kojto	122:f9eeca106725	7425	#define RTC_TSTR_SU_3 0x00000008U
Kojto	110:165afa46840b	7426
Kojto	110:165afa46840b	7427	/****************** Bits definition for RTC_TSDR register ***************/
Kojto	122:f9eeca106725	7428	#define RTC_TSDR_WDU 0x0000E000U
Kojto	122:f9eeca106725	7429	#define RTC_TSDR_WDU_0 0x00002000U
Kojto	122:f9eeca106725	7430	#define RTC_TSDR_WDU_1 0x00004000U
Kojto	122:f9eeca106725	7431	#define RTC_TSDR_WDU_2 0x00008000U
Kojto	122:f9eeca106725	7432	#define RTC_TSDR_MT 0x00001000U
Kojto	122:f9eeca106725	7433	#define RTC_TSDR_MU 0x00000F00U
Kojto	122:f9eeca106725	7434	#define RTC_TSDR_MU_0 0x00000100U
Kojto	122:f9eeca106725	7435	#define RTC_TSDR_MU_1 0x00000200U
Kojto	122:f9eeca106725	7436	#define RTC_TSDR_MU_2 0x00000400U
Kojto	122:f9eeca106725	7437	#define RTC_TSDR_MU_3 0x00000800U
Kojto	122:f9eeca106725	7438	#define RTC_TSDR_DT 0x00000030U
Kojto	122:f9eeca106725	7439	#define RTC_TSDR_DT_0 0x00000010U
Kojto	122:f9eeca106725	7440	#define RTC_TSDR_DT_1 0x00000020U
Kojto	122:f9eeca106725	7441	#define RTC_TSDR_DU 0x0000000FU
Kojto	122:f9eeca106725	7442	#define RTC_TSDR_DU_0 0x00000001U
Kojto	122:f9eeca106725	7443	#define RTC_TSDR_DU_1 0x00000002U
Kojto	122:f9eeca106725	7444	#define RTC_TSDR_DU_2 0x00000004U
Kojto	122:f9eeca106725	7445	#define RTC_TSDR_DU_3 0x00000008U
Kojto	110:165afa46840b	7446
Kojto	110:165afa46840b	7447	/****************** Bits definition for RTC_TSSSR register **************/
Kojto	122:f9eeca106725	7448	#define RTC_TSSSR_SS 0x0000FFFFU
Kojto	110:165afa46840b	7449
Kojto	110:165afa46840b	7450	/****************** Bits definition for RTC_CAL register ***************/
Kojto	122:f9eeca106725	7451	#define RTC_CALR_CALP 0x00008000U
Kojto	122:f9eeca106725	7452	#define RTC_CALR_CALW8 0x00004000U
Kojto	122:f9eeca106725	7453	#define RTC_CALR_CALW16 0x00002000U
Kojto	122:f9eeca106725	7454	#define RTC_CALR_CALM 0x000001FFU
Kojto	122:f9eeca106725	7455	#define RTC_CALR_CALM_0 0x00000001U
Kojto	122:f9eeca106725	7456	#define RTC_CALR_CALM_1 0x00000002U
Kojto	122:f9eeca106725	7457	#define RTC_CALR_CALM_2 0x00000004U
Kojto	122:f9eeca106725	7458	#define RTC_CALR_CALM_3 0x00000008U
Kojto	122:f9eeca106725	7459	#define RTC_CALR_CALM_4 0x00000010U
Kojto	122:f9eeca106725	7460	#define RTC_CALR_CALM_5 0x00000020U
Kojto	122:f9eeca106725	7461	#define RTC_CALR_CALM_6 0x00000040U
Kojto	122:f9eeca106725	7462	#define RTC_CALR_CALM_7 0x00000080U
Kojto	122:f9eeca106725	7463	#define RTC_CALR_CALM_8 0x00000100U
Kojto	110:165afa46840b	7464
Kojto	110:165afa46840b	7465	/****************** Bits definition for RTC_TAFCR register **************/
Kojto	122:f9eeca106725	7466	#define RTC_TAFCR_ALARMOUTTYPE 0x00040000U
Kojto	122:f9eeca106725	7467	#define RTC_TAFCR_TSINSEL 0x00020000U
Kojto	122:f9eeca106725	7468	#define RTC_TAFCR_TAMPINSEL 0x00010000U
Kojto	122:f9eeca106725	7469	#define RTC_TAFCR_TAMPPUDIS 0x00008000U
Kojto	122:f9eeca106725	7470	#define RTC_TAFCR_TAMPPRCH 0x00006000U
Kojto	122:f9eeca106725	7471	#define RTC_TAFCR_TAMPPRCH_0 0x00002000U
Kojto	122:f9eeca106725	7472	#define RTC_TAFCR_TAMPPRCH_1 0x00004000U
Kojto	122:f9eeca106725	7473	#define RTC_TAFCR_TAMPFLT 0x00001800U
Kojto	122:f9eeca106725	7474	#define RTC_TAFCR_TAMPFLT_0 0x00000800U
Kojto	122:f9eeca106725	7475	#define RTC_TAFCR_TAMPFLT_1 0x00001000U
Kojto	122:f9eeca106725	7476	#define RTC_TAFCR_TAMPFREQ 0x00000700U
Kojto	122:f9eeca106725	7477	#define RTC_TAFCR_TAMPFREQ_0 0x00000100U
Kojto	122:f9eeca106725	7478	#define RTC_TAFCR_TAMPFREQ_1 0x00000200U
Kojto	122:f9eeca106725	7479	#define RTC_TAFCR_TAMPFREQ_2 0x00000400U
Kojto	122:f9eeca106725	7480	#define RTC_TAFCR_TAMPTS 0x00000080U
Kojto	122:f9eeca106725	7481	#define RTC_TAFCR_TAMP2TRG 0x00000010U
Kojto	122:f9eeca106725	7482	#define RTC_TAFCR_TAMP2E 0x00000008U
Kojto	122:f9eeca106725	7483	#define RTC_TAFCR_TAMPIE 0x00000004U
Kojto	122:f9eeca106725	7484	#define RTC_TAFCR_TAMP1TRG 0x00000002U
Kojto	122:f9eeca106725	7485	#define RTC_TAFCR_TAMP1E 0x00000001U
Kojto	110:165afa46840b	7486
Kojto	110:165afa46840b	7487	/****************** Bits definition for RTC_ALRMASSR register ***********/
Kojto	122:f9eeca106725	7488	#define RTC_ALRMASSR_MASKSS 0x0F000000U
Kojto	122:f9eeca106725	7489	#define RTC_ALRMASSR_MASKSS_0 0x01000000U
Kojto	122:f9eeca106725	7490	#define RTC_ALRMASSR_MASKSS_1 0x02000000U
Kojto	122:f9eeca106725	7491	#define RTC_ALRMASSR_MASKSS_2 0x04000000U
Kojto	122:f9eeca106725	7492	#define RTC_ALRMASSR_MASKSS_3 0x08000000U
Kojto	122:f9eeca106725	7493	#define RTC_ALRMASSR_SS 0x00007FFFU
Kojto	110:165afa46840b	7494
Kojto	110:165afa46840b	7495	/****************** Bits definition for RTC_ALRMBSSR register ***********/
Kojto	122:f9eeca106725	7496	#define RTC_ALRMBSSR_MASKSS 0x0F000000U
Kojto	122:f9eeca106725	7497	#define RTC_ALRMBSSR_MASKSS_0 0x01000000U
Kojto	122:f9eeca106725	7498	#define RTC_ALRMBSSR_MASKSS_1 0x02000000U
Kojto	122:f9eeca106725	7499	#define RTC_ALRMBSSR_MASKSS_2 0x04000000U
Kojto	122:f9eeca106725	7500	#define RTC_ALRMBSSR_MASKSS_3 0x08000000U
Kojto	122:f9eeca106725	7501	#define RTC_ALRMBSSR_SS 0x00007FFFU
Kojto	110:165afa46840b	7502
Kojto	110:165afa46840b	7503	/****************** Bits definition for RTC_BKP0R register **************/
Kojto	122:f9eeca106725	7504	#define RTC_BKP0R 0xFFFFFFFFU
Kojto	110:165afa46840b	7505
Kojto	110:165afa46840b	7506	/****************** Bits definition for RTC_BKP1R register **************/
Kojto	122:f9eeca106725	7507	#define RTC_BKP1R 0xFFFFFFFFU
Kojto	110:165afa46840b	7508
Kojto	110:165afa46840b	7509	/****************** Bits definition for RTC_BKP2R register **************/
Kojto	122:f9eeca106725	7510	#define RTC_BKP2R 0xFFFFFFFFU
Kojto	110:165afa46840b	7511
Kojto	110:165afa46840b	7512	/****************** Bits definition for RTC_BKP3R register **************/
Kojto	122:f9eeca106725	7513	#define RTC_BKP3R 0xFFFFFFFFU
Kojto	110:165afa46840b	7514
Kojto	110:165afa46840b	7515	/****************** Bits definition for RTC_BKP4R register **************/
Kojto	122:f9eeca106725	7516	#define RTC_BKP4R 0xFFFFFFFFU
Kojto	110:165afa46840b	7517
Kojto	110:165afa46840b	7518	/****************** Bits definition for RTC_BKP5R register **************/
Kojto	122:f9eeca106725	7519	#define RTC_BKP5R 0xFFFFFFFFU
Kojto	110:165afa46840b	7520
Kojto	110:165afa46840b	7521	/****************** Bits definition for RTC_BKP6R register **************/
Kojto	122:f9eeca106725	7522	#define RTC_BKP6R 0xFFFFFFFFU
Kojto	110:165afa46840b	7523
Kojto	110:165afa46840b	7524	/****************** Bits definition for RTC_BKP7R register **************/
Kojto	122:f9eeca106725	7525	#define RTC_BKP7R 0xFFFFFFFFU
Kojto	110:165afa46840b	7526
Kojto	110:165afa46840b	7527	/****************** Bits definition for RTC_BKP8R register **************/
Kojto	122:f9eeca106725	7528	#define RTC_BKP8R 0xFFFFFFFFU
Kojto	110:165afa46840b	7529
Kojto	110:165afa46840b	7530	/****************** Bits definition for RTC_BKP9R register **************/
Kojto	122:f9eeca106725	7531	#define RTC_BKP9R 0xFFFFFFFFU
Kojto	110:165afa46840b	7532
Kojto	110:165afa46840b	7533	/****************** Bits definition for RTC_BKP10R register *************/
Kojto	122:f9eeca106725	7534	#define RTC_BKP10R 0xFFFFFFFFU
Kojto	110:165afa46840b	7535
Kojto	110:165afa46840b	7536	/****************** Bits definition for RTC_BKP11R register *************/
Kojto	122:f9eeca106725	7537	#define RTC_BKP11R 0xFFFFFFFFU
Kojto	110:165afa46840b	7538
Kojto	110:165afa46840b	7539	/****************** Bits definition for RTC_BKP12R register *************/
Kojto	122:f9eeca106725	7540	#define RTC_BKP12R 0xFFFFFFFFU
Kojto	110:165afa46840b	7541
Kojto	110:165afa46840b	7542	/****************** Bits definition for RTC_BKP13R register *************/
Kojto	122:f9eeca106725	7543	#define RTC_BKP13R 0xFFFFFFFFU
Kojto	110:165afa46840b	7544
Kojto	110:165afa46840b	7545	/****************** Bits definition for RTC_BKP14R register *************/
Kojto	122:f9eeca106725	7546	#define RTC_BKP14R 0xFFFFFFFFU
Kojto	110:165afa46840b	7547
Kojto	110:165afa46840b	7548	/****************** Bits definition for RTC_BKP15R register *************/
Kojto	122:f9eeca106725	7549	#define RTC_BKP15R 0xFFFFFFFFU
Kojto	110:165afa46840b	7550
Kojto	110:165afa46840b	7551	/****************** Bits definition for RTC_BKP16R register *************/
Kojto	122:f9eeca106725	7552	#define RTC_BKP16R 0xFFFFFFFFU
Kojto	110:165afa46840b	7553
Kojto	110:165afa46840b	7554	/****************** Bits definition for RTC_BKP17R register *************/
Kojto	122:f9eeca106725	7555	#define RTC_BKP17R 0xFFFFFFFFU
Kojto	110:165afa46840b	7556
Kojto	110:165afa46840b	7557	/****************** Bits definition for RTC_BKP18R register *************/
Kojto	122:f9eeca106725	7558	#define RTC_BKP18R 0xFFFFFFFFU
Kojto	110:165afa46840b	7559
Kojto	110:165afa46840b	7560	/****************** Bits definition for RTC_BKP19R register *************/
Kojto	122:f9eeca106725	7561	#define RTC_BKP19R 0xFFFFFFFFU
Kojto	110:165afa46840b	7562
Kojto	110:165afa46840b	7563	/******************************************************************************/
Kojto	110:165afa46840b	7564	/* */
Kojto	110:165afa46840b	7565	/* Serial Audio Interface */
Kojto	110:165afa46840b	7566	/* */
Kojto	110:165afa46840b	7567	/******************************************************************************/
Kojto	110:165afa46840b	7568	/****************** Bit definition for SAI_GCR register *****************/
Kojto	122:f9eeca106725	7569	#define SAI_GCR_SYNCIN 0x00000003U /!<SYNCIN[1:0] bits (Synchronization Inputs) /
Kojto	122:f9eeca106725	7570	#define SAI_GCR_SYNCIN_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	7571	#define SAI_GCR_SYNCIN_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	7572
Kojto	122:f9eeca106725	7573	#define SAI_GCR_SYNCOUT 0x00000030U /!<SYNCOUT[1:0] bits (Synchronization Outputs) /
Kojto	122:f9eeca106725	7574	#define SAI_GCR_SYNCOUT_0 0x00000010U /!<Bit 0 /
Kojto	122:f9eeca106725	7575	#define SAI_GCR_SYNCOUT_1 0x00000020U /!<Bit 1 /
Kojto	110:165afa46840b	7576
Kojto	110:165afa46840b	7577	/***************** Bit definition for SAI_xCR1 register *****************/
Kojto	122:f9eeca106725	7578	#define SAI_xCR1_MODE 0x00000003U /!<MODE[1:0] bits (Audio Block Mode) /
Kojto	122:f9eeca106725	7579	#define SAI_xCR1_MODE_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	7580	#define SAI_xCR1_MODE_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	7581
Kojto	122:f9eeca106725	7582	#define SAI_xCR1_PRTCFG 0x0000000CU /!<PRTCFG[1:0] bits (Protocol Configuration) /
Kojto	122:f9eeca106725	7583	#define SAI_xCR1_PRTCFG_0 0x00000004U /!<Bit 0 /
Kojto	122:f9eeca106725	7584	#define SAI_xCR1_PRTCFG_1 0x00000008U /!<Bit 1 /
Kojto	122:f9eeca106725	7585
Kojto	122:f9eeca106725	7586	#define SAI_xCR1_DS 0x000000E0U /!<DS[1:0] bits (Data Size) /
Kojto	122:f9eeca106725	7587	#define SAI_xCR1_DS_0 0x00000020U /!<Bit 0 /
Kojto	122:f9eeca106725	7588	#define SAI_xCR1_DS_1 0x00000040U /!<Bit 1 /
Kojto	122:f9eeca106725	7589	#define SAI_xCR1_DS_2 0x00000080U /!<Bit 2 /
Kojto	122:f9eeca106725	7590
Kojto	122:f9eeca106725	7591	#define SAI_xCR1_LSBFIRST 0x00000100U /!<LSB First Configuration /
Kojto	122:f9eeca106725	7592	#define SAI_xCR1_CKSTR 0x00000200U /!<ClocK STRobing edge /
Kojto	122:f9eeca106725	7593
Kojto	122:f9eeca106725	7594	#define SAI_xCR1_SYNCEN 0x00000C00U /!<SYNCEN[1:0](SYNChronization ENable) /
Kojto	122:f9eeca106725	7595	#define SAI_xCR1_SYNCEN_0 0x00000400U /!<Bit 0 /
Kojto	122:f9eeca106725	7596	#define SAI_xCR1_SYNCEN_1 0x00000800U /!<Bit 1 /
Kojto	122:f9eeca106725	7597
Kojto	122:f9eeca106725	7598	#define SAI_xCR1_MONO 0x00001000U /!<Mono mode /
Kojto	122:f9eeca106725	7599	#define SAI_xCR1_OUTDRIV 0x00002000U /!<Output Drive /
Kojto	122:f9eeca106725	7600	#define SAI_xCR1_SAIEN 0x00010000U /!<Audio Block enable /
Kojto	122:f9eeca106725	7601	#define SAI_xCR1_DMAEN 0x00020000U /!<DMA enable /
Kojto	122:f9eeca106725	7602	#define SAI_xCR1_NODIV 0x00080000U /!<No Divider Configuration /
Kojto	122:f9eeca106725	7603
Kojto	122:f9eeca106725	7604	#define SAI_xCR1_MCKDIV 0x00F00000U /!<MCKDIV[3:0] (Master ClocK Divider) /
Kojto	122:f9eeca106725	7605	#define SAI_xCR1_MCKDIV_0 0x00100000U /!<Bit 0 /
Kojto	122:f9eeca106725	7606	#define SAI_xCR1_MCKDIV_1 0x00200000U /!<Bit 1 /
Kojto	122:f9eeca106725	7607	#define SAI_xCR1_MCKDIV_2 0x00400000U /!<Bit 2 /
Kojto	122:f9eeca106725	7608	#define SAI_xCR1_MCKDIV_3 0x00800000U /!<Bit 3 /
Kojto	110:165afa46840b	7609
Kojto	110:165afa46840b	7610	/***************** Bit definition for SAI_xCR2 register *****************/
Kojto	122:f9eeca106725	7611	#define SAI_xCR2_FTH 0x00000007U /!<FTH[2:0](Fifo THreshold) /
Kojto	122:f9eeca106725	7612	#define SAI_xCR2_FTH_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	7613	#define SAI_xCR2_FTH_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	7614	#define SAI_xCR2_FTH_2 0x00000004U /!<Bit 2 /
Kojto	122:f9eeca106725	7615
Kojto	122:f9eeca106725	7616	#define SAI_xCR2_FFLUSH 0x00000008U /!<Fifo FLUSH /
Kojto	122:f9eeca106725	7617	#define SAI_xCR2_TRIS 0x00000010U /!<TRIState Management on data line /
Kojto	122:f9eeca106725	7618	#define SAI_xCR2_MUTE 0x00000020U /!<Mute mode /
Kojto	122:f9eeca106725	7619	#define SAI_xCR2_MUTEVAL 0x00000040U /!<Muate value /
Kojto	122:f9eeca106725	7620
Kojto	122:f9eeca106725	7621	#define SAI_xCR2_MUTECNT 0x00001F80U /!<MUTECNT[5:0] (MUTE counter) /
Kojto	122:f9eeca106725	7622	#define SAI_xCR2_MUTECNT_0 0x00000080U /!<Bit 0 /
Kojto	122:f9eeca106725	7623	#define SAI_xCR2_MUTECNT_1 0x00000100U /!<Bit 1 /
Kojto	122:f9eeca106725	7624	#define SAI_xCR2_MUTECNT_2 0x00000200U /!<Bit 2 /
Kojto	122:f9eeca106725	7625	#define SAI_xCR2_MUTECNT_3 0x00000400U /!<Bit 3 /
Kojto	122:f9eeca106725	7626	#define SAI_xCR2_MUTECNT_4 0x00000800U /!<Bit 4 /
Kojto	122:f9eeca106725	7627	#define SAI_xCR2_MUTECNT_5 0x00001000U /!<Bit 5 /
Kojto	122:f9eeca106725	7628
Kojto	122:f9eeca106725	7629	#define SAI_xCR2_CPL 0x00002000U /!< Complement Bit /
Kojto	122:f9eeca106725	7630
Kojto	122:f9eeca106725	7631	#define SAI_xCR2_COMP 0x0000C000U /!<COMP[1:0] (Companding mode) /
Kojto	122:f9eeca106725	7632	#define SAI_xCR2_COMP_0 0x00004000U /!<Bit 0 /
Kojto	122:f9eeca106725	7633	#define SAI_xCR2_COMP_1 0x00008000U /!<Bit 1 /
Kojto	110:165afa46840b	7634
Kojto	110:165afa46840b	7635	/**************** Bit definition for SAI_xFRCR register *****************/
Kojto	122:f9eeca106725	7636	#define SAI_xFRCR_FRL 0x000000FFU /!<FRL[1:0](Frame length) /
Kojto	122:f9eeca106725	7637	#define SAI_xFRCR_FRL_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	7638	#define SAI_xFRCR_FRL_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	7639	#define SAI_xFRCR_FRL_2 0x00000004U /!<Bit 2 /
Kojto	122:f9eeca106725	7640	#define SAI_xFRCR_FRL_3 0x00000008U /!<Bit 3 /
Kojto	122:f9eeca106725	7641	#define SAI_xFRCR_FRL_4 0x00000010U /!<Bit 4 /
Kojto	122:f9eeca106725	7642	#define SAI_xFRCR_FRL_5 0x00000020U /!<Bit 5 /
Kojto	122:f9eeca106725	7643	#define SAI_xFRCR_FRL_6 0x00000040U /!<Bit 6 /
Kojto	122:f9eeca106725	7644	#define SAI_xFRCR_FRL_7 0x00000080U /!<Bit 7 /
Kojto	122:f9eeca106725	7645
Kojto	122:f9eeca106725	7646	#define SAI_xFRCR_FSALL 0x00007F00U /!<FRL[1:0] (Frame synchronization active level length) /
Kojto	122:f9eeca106725	7647	#define SAI_xFRCR_FSALL_0 0x00000100U /!<Bit 0 /
Kojto	122:f9eeca106725	7648	#define SAI_xFRCR_FSALL_1 0x00000200U /!<Bit 1 /
Kojto	122:f9eeca106725	7649	#define SAI_xFRCR_FSALL_2 0x00000400U /!<Bit 2 /
Kojto	122:f9eeca106725	7650	#define SAI_xFRCR_FSALL_3 0x00000800U /!<Bit 3 /
Kojto	122:f9eeca106725	7651	#define SAI_xFRCR_FSALL_4 0x00001000U /!<Bit 4 /
Kojto	122:f9eeca106725	7652	#define SAI_xFRCR_FSALL_5 0x00002000U /!<Bit 5 /
Kojto	122:f9eeca106725	7653	#define SAI_xFRCR_FSALL_6 0x00004000U /!<Bit 6 /
Kojto	122:f9eeca106725	7654
Kojto	122:f9eeca106725	7655	#define SAI_xFRCR_FSDEF 0x00010000U /!< Frame Synchronization Definition /
Kojto	122:f9eeca106725	7656	#define SAI_xFRCR_FSPOL 0x00020000U /!<Frame Synchronization POLarity /
Kojto	122:f9eeca106725	7657	#define SAI_xFRCR_FSOFF 0x00040000U /!<Frame Synchronization OFFset /
Kojto	122:f9eeca106725	7658	/* Legacy defines */
Kojto	122:f9eeca106725	7659	#define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
Kojto	110:165afa46840b	7660
Kojto	110:165afa46840b	7661	/**************** Bit definition for SAI_xSLOTR register *****************/
Kojto	122:f9eeca106725	7662	#define SAI_xSLOTR_FBOFF 0x0000001FU /!<FRL[4:0](First Bit Offset) /
Kojto	122:f9eeca106725	7663	#define SAI_xSLOTR_FBOFF_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	7664	#define SAI_xSLOTR_FBOFF_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	7665	#define SAI_xSLOTR_FBOFF_2 0x00000004U /!<Bit 2 /
Kojto	122:f9eeca106725	7666	#define SAI_xSLOTR_FBOFF_3 0x00000008U /!<Bit 3 /
Kojto	122:f9eeca106725	7667	#define SAI_xSLOTR_FBOFF_4 0x00000010U /!<Bit 4 /
Kojto	122:f9eeca106725	7668
Kojto	122:f9eeca106725	7669	#define SAI_xSLOTR_SLOTSZ 0x000000C0U /!<SLOTSZ[1:0] (Slot size) /
Kojto	122:f9eeca106725	7670	#define SAI_xSLOTR_SLOTSZ_0 0x00000040U /!<Bit 0 /
Kojto	122:f9eeca106725	7671	#define SAI_xSLOTR_SLOTSZ_1 0x00000080U /!<Bit 1 /
Kojto	122:f9eeca106725	7672
Kojto	122:f9eeca106725	7673	#define SAI_xSLOTR_NBSLOT 0x00000F00U /!<NBSLOT[3:0] (Number of Slot in audio Frame) /
Kojto	122:f9eeca106725	7674	#define SAI_xSLOTR_NBSLOT_0 0x00000100U /!<Bit 0 /
Kojto	122:f9eeca106725	7675	#define SAI_xSLOTR_NBSLOT_1 0x00000200U /!<Bit 1 /
Kojto	122:f9eeca106725	7676	#define SAI_xSLOTR_NBSLOT_2 0x00000400U /!<Bit 2 /
Kojto	122:f9eeca106725	7677	#define SAI_xSLOTR_NBSLOT_3 0x00000800U /!<Bit 3 /
Kojto	122:f9eeca106725	7678
Kojto	122:f9eeca106725	7679	#define SAI_xSLOTR_SLOTEN 0xFFFF0000U /!<SLOTEN[15:0] (Slot Enable) /
Kojto	110:165afa46840b	7680
Kojto	110:165afa46840b	7681	/***************** Bit definition for SAI_xIMR register *****************/
Kojto	122:f9eeca106725	7682	#define SAI_xIMR_OVRUDRIE 0x00000001U /!<Overrun underrun interrupt enable /
Kojto	122:f9eeca106725	7683	#define SAI_xIMR_MUTEDETIE 0x00000002U /!<Mute detection interrupt enable /
Kojto	122:f9eeca106725	7684	#define SAI_xIMR_WCKCFGIE 0x00000004U /!<Wrong Clock Configuration interrupt enable /
Kojto	122:f9eeca106725	7685	#define SAI_xIMR_FREQIE 0x00000008U /!<FIFO request interrupt enable /
Kojto	122:f9eeca106725	7686	#define SAI_xIMR_CNRDYIE 0x00000010U /!<Codec not ready interrupt enable /
Kojto	122:f9eeca106725	7687	#define SAI_xIMR_AFSDETIE 0x00000020U /!<Anticipated frame synchronization detection interrupt enable /
Kojto	122:f9eeca106725	7688	#define SAI_xIMR_LFSDETIE 0x00000040U /!<Late frame synchronization detection interrupt enable /
Kojto	110:165afa46840b	7689
Kojto	110:165afa46840b	7690	/****************** Bit definition for SAI_xSR register *****************/
Kojto	122:f9eeca106725	7691	#define SAI_xSR_OVRUDR 0x00000001U /!<Overrun underrun /
Kojto	122:f9eeca106725	7692	#define SAI_xSR_MUTEDET 0x00000002U /!<Mute detection /
Kojto	122:f9eeca106725	7693	#define SAI_xSR_WCKCFG 0x00000004U /!<Wrong Clock Configuration /
Kojto	122:f9eeca106725	7694	#define SAI_xSR_FREQ 0x00000008U /!<FIFO request /
Kojto	122:f9eeca106725	7695	#define SAI_xSR_CNRDY 0x00000010U /!<Codec not ready /
Kojto	122:f9eeca106725	7696	#define SAI_xSR_AFSDET 0x00000020U /!<Anticipated frame synchronization detection /
Kojto	122:f9eeca106725	7697	#define SAI_xSR_LFSDET 0x00000040U /!<Late frame synchronization detection /
Kojto	122:f9eeca106725	7698
Kojto	122:f9eeca106725	7699	#define SAI_xSR_FLVL 0x00070000U /!<FLVL[2:0] (FIFO Level Threshold) /
Kojto	122:f9eeca106725	7700	#define SAI_xSR_FLVL_0 0x00010000U /!<Bit 0 /
Kojto	122:f9eeca106725	7701	#define SAI_xSR_FLVL_1 0x00020000U /!<Bit 1 /
Kojto	122:f9eeca106725	7702	#define SAI_xSR_FLVL_2 0x00040000U /!<Bit 2 /
Kojto	110:165afa46840b	7703
Kojto	110:165afa46840b	7704	/**************** Bit definition for SAI_xCLRFR register ****************/
Kojto	122:f9eeca106725	7705	#define SAI_xCLRFR_COVRUDR 0x00000001U /!<Clear Overrun underrun /
Kojto	122:f9eeca106725	7706	#define SAI_xCLRFR_CMUTEDET 0x00000002U /!<Clear Mute detection /
Kojto	122:f9eeca106725	7707	#define SAI_xCLRFR_CWCKCFG 0x00000004U /!<Clear Wrong Clock Configuration /
Kojto	122:f9eeca106725	7708	#define SAI_xCLRFR_CFREQ 0x00000008U /!<Clear FIFO request /
Kojto	122:f9eeca106725	7709	#define SAI_xCLRFR_CCNRDY 0x00000010U /!<Clear Codec not ready /
Kojto	122:f9eeca106725	7710	#define SAI_xCLRFR_CAFSDET 0x00000020U /!<Clear Anticipated frame synchronization detection /
Kojto	122:f9eeca106725	7711	#define SAI_xCLRFR_CLFSDET 0x00000040U /!<Clear Late frame synchronization detection /
Kojto	110:165afa46840b	7712
Kojto	110:165afa46840b	7713	/**************** Bit definition for SAI_xDR register ****************/
Kojto	122:f9eeca106725	7714	#define SAI_xDR_DATA 0xFFFFFFFFU
Kojto	110:165afa46840b	7715
Kojto	110:165afa46840b	7716
Kojto	110:165afa46840b	7717	/******************************************************************************/
Kojto	110:165afa46840b	7718	/* */
Kojto	110:165afa46840b	7719	/* SD host Interface */
Kojto	110:165afa46840b	7720	/* */
Kojto	110:165afa46840b	7721	/******************************************************************************/
Kojto	110:165afa46840b	7722	/**************** Bit definition for SDIO_POWER register ****************/
Kojto	122:f9eeca106725	7723	#define SDIO_POWER_PWRCTRL 0x03U /!<PWRCTRL[1:0] bits (Power supply control bits) /
Kojto	122:f9eeca106725	7724	#define SDIO_POWER_PWRCTRL_0 0x01U /!<Bit 0 /
Kojto	122:f9eeca106725	7725	#define SDIO_POWER_PWRCTRL_1 0x02U /!<Bit 1 /
Kojto	110:165afa46840b	7726
Kojto	110:165afa46840b	7727	/**************** Bit definition for SDIO_CLKCR register ****************/
Kojto	122:f9eeca106725	7728	#define SDIO_CLKCR_CLKDIV 0x00FFU /!<Clock divide factor /
Kojto	122:f9eeca106725	7729	#define SDIO_CLKCR_CLKEN 0x0100U /!<Clock enable bit /
Kojto	122:f9eeca106725	7730	#define SDIO_CLKCR_PWRSAV 0x0200U /!<Power saving configuration bit /
Kojto	122:f9eeca106725	7731	#define SDIO_CLKCR_BYPASS 0x0400U /!<Clock divider bypass enable bit /
Kojto	122:f9eeca106725	7732
Kojto	122:f9eeca106725	7733	#define SDIO_CLKCR_WIDBUS 0x1800U /!<WIDBUS[1:0] bits (Wide bus mode enable bit) /
Kojto	122:f9eeca106725	7734	#define SDIO_CLKCR_WIDBUS_0 0x0800U /!<Bit 0 /
Kojto	122:f9eeca106725	7735	#define SDIO_CLKCR_WIDBUS_1 0x1000U /!<Bit 1 /
Kojto	122:f9eeca106725	7736
Kojto	122:f9eeca106725	7737	#define SDIO_CLKCR_NEGEDGE 0x2000U /!<SDIO_CK dephasing selection bit /
Kojto	122:f9eeca106725	7738	#define SDIO_CLKCR_HWFC_EN 0x4000U /!<HW Flow Control enable /
Kojto	110:165afa46840b	7739
Kojto	110:165afa46840b	7740	/***************** Bit definition for SDIO_ARG register *****************/
Kojto	122:f9eeca106725	7741	#define SDIO_ARG_CMDARG 0xFFFFFFFFU /!<Command argument /
Kojto	110:165afa46840b	7742
Kojto	110:165afa46840b	7743	/***************** Bit definition for SDIO_CMD register *****************/
Kojto	122:f9eeca106725	7744	#define SDIO_CMD_CMDINDEX 0x003FU /!<Command Index /
Kojto	122:f9eeca106725	7745
Kojto	122:f9eeca106725	7746	#define SDIO_CMD_WAITRESP 0x00C0U /!<WAITRESP[1:0] bits (Wait for response bits) /
Kojto	122:f9eeca106725	7747	#define SDIO_CMD_WAITRESP_0 0x0040U /!< Bit 0 /
Kojto	122:f9eeca106725	7748	#define SDIO_CMD_WAITRESP_1 0x0080U /!< Bit 1 /
Kojto	122:f9eeca106725	7749
Kojto	122:f9eeca106725	7750	#define SDIO_CMD_WAITINT 0x0100U /!<CPSM Waits for Interrupt Request /
Kojto	122:f9eeca106725	7751	#define SDIO_CMD_WAITPEND 0x0200U /!<CPSM Waits for ends of data transfer (CmdPend internal signal) /
Kojto	122:f9eeca106725	7752	#define SDIO_CMD_CPSMEN 0x0400U /!<Command path state machine (CPSM) Enable bit /
Kojto	122:f9eeca106725	7753	#define SDIO_CMD_SDIOSUSPEND 0x0800U /!<SD I/O suspend command /
Kojto	110:165afa46840b	7754
Kojto	110:165afa46840b	7755	/*************** Bit definition for SDIO_RESPCMD register ***************/
Kojto	122:f9eeca106725	7756	#define SDIO_RESPCMD_RESPCMD 0x3FU /!<Response command index /
Kojto	110:165afa46840b	7757
Kojto	110:165afa46840b	7758	/**************** Bit definition for SDIO_RESP0 register ****************/
Kojto	122:f9eeca106725	7759	#define SDIO_RESP0_CARDSTATUS0 0xFFFFFFFFU /!<Card Status /
Kojto	110:165afa46840b	7760
Kojto	110:165afa46840b	7761	/**************** Bit definition for SDIO_RESP1 register ****************/
Kojto	122:f9eeca106725	7762	#define SDIO_RESP1_CARDSTATUS1 0xFFFFFFFFU /!<Card Status /
Kojto	110:165afa46840b	7763
Kojto	110:165afa46840b	7764	/**************** Bit definition for SDIO_RESP2 register ****************/
Kojto	122:f9eeca106725	7765	#define SDIO_RESP2_CARDSTATUS2 0xFFFFFFFFU /!<Card Status /
Kojto	110:165afa46840b	7766
Kojto	110:165afa46840b	7767	/**************** Bit definition for SDIO_RESP3 register ****************/
Kojto	122:f9eeca106725	7768	#define SDIO_RESP3_CARDSTATUS3 0xFFFFFFFFU /!<Card Status /
Kojto	110:165afa46840b	7769
Kojto	110:165afa46840b	7770	/**************** Bit definition for SDIO_RESP4 register ****************/
Kojto	122:f9eeca106725	7771	#define SDIO_RESP4_CARDSTATUS4 0xFFFFFFFFU /!<Card Status /
Kojto	110:165afa46840b	7772
Kojto	110:165afa46840b	7773	/**************** Bit definition for SDIO_DTIMER register ***************/
Kojto	122:f9eeca106725	7774	#define SDIO_DTIMER_DATATIME 0xFFFFFFFFU /!<Data timeout period. /
Kojto	110:165afa46840b	7775
Kojto	110:165afa46840b	7776	/**************** Bit definition for SDIO_DLEN register *****************/
Kojto	122:f9eeca106725	7777	#define SDIO_DLEN_DATALENGTH 0x01FFFFFFU /!<Data length value /
Kojto	110:165afa46840b	7778
Kojto	110:165afa46840b	7779	/**************** Bit definition for SDIO_DCTRL register ****************/
Kojto	122:f9eeca106725	7780	#define SDIO_DCTRL_DTEN 0x0001U /!<Data transfer enabled bit /
Kojto	122:f9eeca106725	7781	#define SDIO_DCTRL_DTDIR 0x0002U /!<Data transfer direction selection /
Kojto	122:f9eeca106725	7782	#define SDIO_DCTRL_DTMODE 0x0004U /!<Data transfer mode selection /
Kojto	122:f9eeca106725	7783	#define SDIO_DCTRL_DMAEN 0x0008U /!<DMA enabled bit /
Kojto	122:f9eeca106725	7784
Kojto	122:f9eeca106725	7785	#define SDIO_DCTRL_DBLOCKSIZE 0x00F0U /!<DBLOCKSIZE[3:0] bits (Data block size) /
Kojto	122:f9eeca106725	7786	#define SDIO_DCTRL_DBLOCKSIZE_0 0x0010U /!<Bit 0 /
Kojto	122:f9eeca106725	7787	#define SDIO_DCTRL_DBLOCKSIZE_1 0x0020U /!<Bit 1 /
Kojto	122:f9eeca106725	7788	#define SDIO_DCTRL_DBLOCKSIZE_2 0x0040U /!<Bit 2 /
Kojto	122:f9eeca106725	7789	#define SDIO_DCTRL_DBLOCKSIZE_3 0x0080U /!<Bit 3 /
Kojto	122:f9eeca106725	7790
Kojto	122:f9eeca106725	7791	#define SDIO_DCTRL_RWSTART 0x0100U /!<Read wait start /
Kojto	122:f9eeca106725	7792	#define SDIO_DCTRL_RWSTOP 0x0200U /!<Read wait stop /
Kojto	122:f9eeca106725	7793	#define SDIO_DCTRL_RWMOD 0x0400U /!<Read wait mode /
Kojto	122:f9eeca106725	7794	#define SDIO_DCTRL_SDIOEN 0x0800U /!<SD I/O enable functions /
Kojto	110:165afa46840b	7795
Kojto	110:165afa46840b	7796	/**************** Bit definition for SDIO_DCOUNT register ***************/
Kojto	122:f9eeca106725	7797	#define SDIO_DCOUNT_DATACOUNT 0x01FFFFFFU /!<Data count value /
Kojto	110:165afa46840b	7798
Kojto	110:165afa46840b	7799	/**************** Bit definition for SDIO_STA register ******************/
Kojto	122:f9eeca106725	7800	#define SDIO_STA_CCRCFAIL 0x00000001U /!<Command response received (CRC check failed) /
Kojto	122:f9eeca106725	7801	#define SDIO_STA_DCRCFAIL 0x00000002U /!<Data block sent/received (CRC check failed) /
Kojto	122:f9eeca106725	7802	#define SDIO_STA_CTIMEOUT 0x00000004U /!<Command response timeout /
Kojto	122:f9eeca106725	7803	#define SDIO_STA_DTIMEOUT 0x00000008U /!<Data timeout /
Kojto	122:f9eeca106725	7804	#define SDIO_STA_TXUNDERR 0x00000010U /!<Transmit FIFO underrun error /
Kojto	122:f9eeca106725	7805	#define SDIO_STA_RXOVERR 0x00000020U /!<Received FIFO overrun error /
Kojto	122:f9eeca106725	7806	#define SDIO_STA_CMDREND 0x00000040U /!<Command response received (CRC check passed) /
Kojto	122:f9eeca106725	7807	#define SDIO_STA_CMDSENT 0x00000080U /!<Command sent (no response required) /
Kojto	122:f9eeca106725	7808	#define SDIO_STA_DATAEND 0x00000100U /!<Data end (data counter, SDIDCOUNT, is zero) /
Kojto	122:f9eeca106725	7809	#define SDIO_STA_DBCKEND 0x00000400U /!<Data block sent/received (CRC check passed) /
Kojto	122:f9eeca106725	7810	#define SDIO_STA_CMDACT 0x00000800U /!<Command transfer in progress /
Kojto	122:f9eeca106725	7811	#define SDIO_STA_TXACT 0x00001000U /!<Data transmit in progress /
Kojto	122:f9eeca106725	7812	#define SDIO_STA_RXACT 0x00002000U /!<Data receive in progress /
Kojto	122:f9eeca106725	7813	#define SDIO_STA_TXFIFOHE 0x00004000U /!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO /
Kojto	122:f9eeca106725	7814	#define SDIO_STA_RXFIFOHF 0x00008000U /!<Receive FIFO Half Full: there are at least 8 words in the FIFO /
Kojto	122:f9eeca106725	7815	#define SDIO_STA_TXFIFOF 0x00010000U /!<Transmit FIFO full /
Kojto	122:f9eeca106725	7816	#define SDIO_STA_RXFIFOF 0x00020000U /!<Receive FIFO full /
Kojto	122:f9eeca106725	7817	#define SDIO_STA_TXFIFOE 0x00040000U /!<Transmit FIFO empty /
Kojto	122:f9eeca106725	7818	#define SDIO_STA_RXFIFOE 0x00080000U /!<Receive FIFO empty /
Kojto	122:f9eeca106725	7819	#define SDIO_STA_TXDAVL 0x00100000U /!<Data available in transmit FIFO /
Kojto	122:f9eeca106725	7820	#define SDIO_STA_RXDAVL 0x00200000U /!<Data available in receive FIFO /
Kojto	122:f9eeca106725	7821	#define SDIO_STA_SDIOIT 0x00400000U /!<SDIO interrupt received /
Kojto	110:165afa46840b	7822
Kojto	110:165afa46840b	7823	/***************** Bit definition for SDIO_ICR register *****************/
Kojto	122:f9eeca106725	7824	#define SDIO_ICR_CCRCFAILC 0x00000001U /!<CCRCFAIL flag clear bit /
Kojto	122:f9eeca106725	7825	#define SDIO_ICR_DCRCFAILC 0x00000002U /!<DCRCFAIL flag clear bit /
Kojto	122:f9eeca106725	7826	#define SDIO_ICR_CTIMEOUTC 0x00000004U /!<CTIMEOUT flag clear bit /
Kojto	122:f9eeca106725	7827	#define SDIO_ICR_DTIMEOUTC 0x00000008U /!<DTIMEOUT flag clear bit /
Kojto	122:f9eeca106725	7828	#define SDIO_ICR_TXUNDERRC 0x00000010U /!<TXUNDERR flag clear bit /
Kojto	122:f9eeca106725	7829	#define SDIO_ICR_RXOVERRC 0x00000020U /!<RXOVERR flag clear bit /
Kojto	122:f9eeca106725	7830	#define SDIO_ICR_CMDRENDC 0x00000040U /!<CMDREND flag clear bit /
Kojto	122:f9eeca106725	7831	#define SDIO_ICR_CMDSENTC 0x00000080U /!<CMDSENT flag clear bit /
Kojto	122:f9eeca106725	7832	#define SDIO_ICR_DATAENDC 0x00000100U /!<DATAEND flag clear bit /
Kojto	122:f9eeca106725	7833	#define SDIO_ICR_DBCKENDC 0x00000400U /!<DBCKEND flag clear bit /
Kojto	122:f9eeca106725	7834	#define SDIO_ICR_SDIOITC 0x00400000U /!<SDIOIT flag clear bit /
Kojto	110:165afa46840b	7835
Kojto	110:165afa46840b	7836	/**************** Bit definition for SDIO_MASK register *****************/
Kojto	122:f9eeca106725	7837	#define SDIO_MASK_CCRCFAILIE 0x00000001U /!<Command CRC Fail Interrupt Enable /
Kojto	122:f9eeca106725	7838	#define SDIO_MASK_DCRCFAILIE 0x00000002U /!<Data CRC Fail Interrupt Enable /
Kojto	122:f9eeca106725	7839	#define SDIO_MASK_CTIMEOUTIE 0x00000004U /!<Command TimeOut Interrupt Enable /
Kojto	122:f9eeca106725	7840	#define SDIO_MASK_DTIMEOUTIE 0x00000008U /!<Data TimeOut Interrupt Enable /
Kojto	122:f9eeca106725	7841	#define SDIO_MASK_TXUNDERRIE 0x00000010U /!<Tx FIFO UnderRun Error Interrupt Enable /
Kojto	122:f9eeca106725	7842	#define SDIO_MASK_RXOVERRIE 0x00000020U /!<Rx FIFO OverRun Error Interrupt Enable /
Kojto	122:f9eeca106725	7843	#define SDIO_MASK_CMDRENDIE 0x00000040U /!<Command Response Received Interrupt Enable /
Kojto	122:f9eeca106725	7844	#define SDIO_MASK_CMDSENTIE 0x00000080U /!<Command Sent Interrupt Enable /
Kojto	122:f9eeca106725	7845	#define SDIO_MASK_DATAENDIE 0x00000100U /!<Data End Interrupt Enable /
Kojto	122:f9eeca106725	7846	#define SDIO_MASK_DBCKENDIE 0x00000400U /!<Data Block End Interrupt Enable /
Kojto	122:f9eeca106725	7847	#define SDIO_MASK_CMDACTIE 0x00000800U /!<CCommand Acting Interrupt Enable /
Kojto	122:f9eeca106725	7848	#define SDIO_MASK_TXACTIE 0x00001000U /!<Data Transmit Acting Interrupt Enable /
Kojto	122:f9eeca106725	7849	#define SDIO_MASK_RXACTIE 0x00002000U /!<Data receive acting interrupt enabled /
Kojto	122:f9eeca106725	7850	#define SDIO_MASK_TXFIFOHEIE 0x00004000U /!<Tx FIFO Half Empty interrupt Enable /
Kojto	122:f9eeca106725	7851	#define SDIO_MASK_RXFIFOHFIE 0x00008000U /!<Rx FIFO Half Full interrupt Enable /
Kojto	122:f9eeca106725	7852	#define SDIO_MASK_TXFIFOFIE 0x00010000U /!<Tx FIFO Full interrupt Enable /
Kojto	122:f9eeca106725	7853	#define SDIO_MASK_RXFIFOFIE 0x00020000U /!<Rx FIFO Full interrupt Enable /
Kojto	122:f9eeca106725	7854	#define SDIO_MASK_TXFIFOEIE 0x00040000U /!<Tx FIFO Empty interrupt Enable /
Kojto	122:f9eeca106725	7855	#define SDIO_MASK_RXFIFOEIE 0x00080000U /!<Rx FIFO Empty interrupt Enable /
Kojto	122:f9eeca106725	7856	#define SDIO_MASK_TXDAVLIE 0x00100000U /!<Data available in Tx FIFO interrupt Enable /
Kojto	122:f9eeca106725	7857	#define SDIO_MASK_RXDAVLIE 0x00200000U /!<Data available in Rx FIFO interrupt Enable /
Kojto	122:f9eeca106725	7858	#define SDIO_MASK_SDIOITIE 0x00400000U /!<SDIO Mode Interrupt Received interrupt Enable /
Kojto	110:165afa46840b	7859
Kojto	110:165afa46840b	7860	/*************** Bit definition for SDIO_FIFOCNT register ***************/
Kojto	122:f9eeca106725	7861	#define SDIO_FIFOCNT_FIFOCOUNT 0x00FFFFFFU /!<Remaining number of words to be written to or read from the FIFO /
Kojto	110:165afa46840b	7862
Kojto	110:165afa46840b	7863	/**************** Bit definition for SDIO_FIFO register *****************/
Kojto	122:f9eeca106725	7864	#define SDIO_FIFO_FIFODATA 0xFFFFFFFFU /!<Receive and transmit FIFO data /
Kojto	110:165afa46840b	7865
Kojto	110:165afa46840b	7866	/******************************************************************************/
Kojto	110:165afa46840b	7867	/* */
Kojto	110:165afa46840b	7868	/* Serial Peripheral Interface */
Kojto	110:165afa46840b	7869	/* */
Kojto	110:165afa46840b	7870	/******************************************************************************/
Kojto	110:165afa46840b	7871	/***************** Bit definition for SPI_CR1 register ******************/
Kojto	122:f9eeca106725	7872	#define SPI_CR1_CPHA 0x00000001U /!<Clock Phase /
Kojto	122:f9eeca106725	7873	#define SPI_CR1_CPOL 0x00000002U /!<Clock Polarity /
Kojto	122:f9eeca106725	7874	#define SPI_CR1_MSTR 0x00000004U /!<Master Selection /
Kojto	122:f9eeca106725	7875
Kojto	122:f9eeca106725	7876	#define SPI_CR1_BR 0x00000038U /!<BR[2:0] bits (Baud Rate Control) /
Kojto	122:f9eeca106725	7877	#define SPI_CR1_BR_0 0x00000008U /!<Bit 0 /
Kojto	122:f9eeca106725	7878	#define SPI_CR1_BR_1 0x00000010U /!<Bit 1 /
Kojto	122:f9eeca106725	7879	#define SPI_CR1_BR_2 0x00000020U /!<Bit 2 /
Kojto	122:f9eeca106725	7880
Kojto	122:f9eeca106725	7881	#define SPI_CR1_SPE 0x00000040U /!<SPI Enable /
Kojto	122:f9eeca106725	7882	#define SPI_CR1_LSBFIRST 0x00000080U /!<Frame Format /
Kojto	122:f9eeca106725	7883	#define SPI_CR1_SSI 0x00000100U /!<Internal slave select /
Kojto	122:f9eeca106725	7884	#define SPI_CR1_SSM 0x00000200U /!<Software slave management /
Kojto	122:f9eeca106725	7885	#define SPI_CR1_RXONLY 0x00000400U /!<Receive only /
Kojto	122:f9eeca106725	7886	#define SPI_CR1_DFF 0x00000800U /!<Data Frame Format /
Kojto	122:f9eeca106725	7887	#define SPI_CR1_CRCNEXT 0x00001000U /!<Transmit CRC next /
Kojto	122:f9eeca106725	7888	#define SPI_CR1_CRCEN 0x00002000U /!<Hardware CRC calculation enable /
Kojto	122:f9eeca106725	7889	#define SPI_CR1_BIDIOE 0x00004000U /!<Output enable in bidirectional mode /
Kojto	122:f9eeca106725	7890	#define SPI_CR1_BIDIMODE 0x00008000U /!<Bidirectional data mode enable /
Kojto	110:165afa46840b	7891
Kojto	110:165afa46840b	7892	/***************** Bit definition for SPI_CR2 register ******************/
Kojto	122:f9eeca106725	7893	#define SPI_CR2_RXDMAEN 0x00000001U /!<Rx Buffer DMA Enable /
Kojto	122:f9eeca106725	7894	#define SPI_CR2_TXDMAEN 0x00000002U /!<Tx Buffer DMA Enable /
Kojto	122:f9eeca106725	7895	#define SPI_CR2_SSOE 0x00000004U /!<SS Output Enable /
Kojto	122:f9eeca106725	7896	#define SPI_CR2_FRF 0x00000010U /!<Frame Format /
Kojto	122:f9eeca106725	7897	#define SPI_CR2_ERRIE 0x00000020U /!<Error Interrupt Enable /
Kojto	122:f9eeca106725	7898	#define SPI_CR2_RXNEIE 0x00000040U /!<RX buffer Not Empty Interrupt Enable /
Kojto	122:f9eeca106725	7899	#define SPI_CR2_TXEIE 0x00000080U /!<Tx buffer Empty Interrupt Enable /
Kojto	110:165afa46840b	7900
Kojto	110:165afa46840b	7901	/****************** Bit definition for SPI_SR register ******************/
Kojto	122:f9eeca106725	7902	#define SPI_SR_RXNE 0x00000001U /!<Receive buffer Not Empty /
Kojto	122:f9eeca106725	7903	#define SPI_SR_TXE 0x00000002U /!<Transmit buffer Empty /
Kojto	122:f9eeca106725	7904	#define SPI_SR_CHSIDE 0x00000004U /!<Channel side /
Kojto	122:f9eeca106725	7905	#define SPI_SR_UDR 0x00000008U /!<Underrun flag /
Kojto	122:f9eeca106725	7906	#define SPI_SR_CRCERR 0x00000010U /!<CRC Error flag /
Kojto	122:f9eeca106725	7907	#define SPI_SR_MODF 0x00000020U /!<Mode fault /
Kojto	122:f9eeca106725	7908	#define SPI_SR_OVR 0x00000040U /!<Overrun flag /
Kojto	122:f9eeca106725	7909	#define SPI_SR_BSY 0x00000080U /!<Busy flag /
Kojto	122:f9eeca106725	7910	#define SPI_SR_FRE 0x00000100U /!<Frame format error flag /
Kojto	110:165afa46840b	7911
Kojto	110:165afa46840b	7912	/****************** Bit definition for SPI_DR register ******************/
Kojto	122:f9eeca106725	7913	#define SPI_DR_DR 0x0000FFFFU /!<Data Register /
Kojto	110:165afa46840b	7914
Kojto	110:165afa46840b	7915	/***************** Bit definition for SPI_CRCPR register ****************/
Kojto	122:f9eeca106725	7916	#define SPI_CRCPR_CRCPOLY 0x0000FFFFU /!<CRC polynomial register /
Kojto	110:165afa46840b	7917
Kojto	110:165afa46840b	7918	/**************** Bit definition for SPI_RXCRCR register ****************/
Kojto	122:f9eeca106725	7919	#define SPI_RXCRCR_RXCRC 0x0000FFFFU /!<Rx CRC Register /
Kojto	110:165afa46840b	7920
Kojto	110:165afa46840b	7921	/**************** Bit definition for SPI_TXCRCR register ****************/
Kojto	122:f9eeca106725	7922	#define SPI_TXCRCR_TXCRC 0x0000FFFFU /!<Tx CRC Register /
Kojto	110:165afa46840b	7923
Kojto	110:165afa46840b	7924	/**************** Bit definition for SPI_I2SCFGR register ***************/
Kojto	122:f9eeca106725	7925	#define SPI_I2SCFGR_CHLEN 0x00000001U /!<Channel length (number of bits per audio channel) /
Kojto	122:f9eeca106725	7926
Kojto	122:f9eeca106725	7927	#define SPI_I2SCFGR_DATLEN 0x00000006U /!<DATLEN[1:0] bits (Data length to be transferred) /
Kojto	122:f9eeca106725	7928	#define SPI_I2SCFGR_DATLEN_0 0x00000002U /!<Bit 0 /
Kojto	122:f9eeca106725	7929	#define SPI_I2SCFGR_DATLEN_1 0x00000004U /!<Bit 1 /
Kojto	122:f9eeca106725	7930
Kojto	122:f9eeca106725	7931	#define SPI_I2SCFGR_CKPOL 0x00000008U /!<steady state clock polarity /
Kojto	122:f9eeca106725	7932
Kojto	122:f9eeca106725	7933	#define SPI_I2SCFGR_I2SSTD 0x00000030U /!<I2SSTD[1:0] bits (I2S standard selection) /
Kojto	122:f9eeca106725	7934	#define SPI_I2SCFGR_I2SSTD_0 0x00000010U /!<Bit 0 /
Kojto	122:f9eeca106725	7935	#define SPI_I2SCFGR_I2SSTD_1 0x00000020U /!<Bit 1 /
Kojto	122:f9eeca106725	7936
Kojto	122:f9eeca106725	7937	#define SPI_I2SCFGR_PCMSYNC 0x00000080U /!<PCM frame synchronization /
Kojto	122:f9eeca106725	7938
Kojto	122:f9eeca106725	7939	#define SPI_I2SCFGR_I2SCFG 0x00000300U /!<I2SCFG[1:0] bits (I2S configuration mode) /
Kojto	122:f9eeca106725	7940	#define SPI_I2SCFGR_I2SCFG_0 0x00000100U /!<Bit 0 /
Kojto	122:f9eeca106725	7941	#define SPI_I2SCFGR_I2SCFG_1 0x00000200U /!<Bit 1 /
Kojto	122:f9eeca106725	7942
Kojto	122:f9eeca106725	7943	#define SPI_I2SCFGR_I2SE 0x00000400U /!<I2S Enable /
Kojto	122:f9eeca106725	7944	#define SPI_I2SCFGR_I2SMOD 0x00000800U /!<I2S mode selection /
Kojto	122:f9eeca106725	7945	#define SPI_I2SCFGR_ASTRTEN 0x00001000U /!<Asynchronous start enable /
Kojto	110:165afa46840b	7946
Kojto	110:165afa46840b	7947	/**************** Bit definition for SPI_I2SPR register *****************/
Kojto	122:f9eeca106725	7948	#define SPI_I2SPR_I2SDIV 0x000000FFU /!<I2S Linear prescaler /
Kojto	122:f9eeca106725	7949	#define SPI_I2SPR_ODD 0x00000100U /!<Odd factor for the prescaler /
Kojto	122:f9eeca106725	7950	#define SPI_I2SPR_MCKOE 0x00000200U /!<Master Clock Output Enable /
Kojto	110:165afa46840b	7951
Kojto	110:165afa46840b	7952	/******************************************************************************/
Kojto	110:165afa46840b	7953	/* */
Kojto	110:165afa46840b	7954	/* SYSCFG */
Kojto	110:165afa46840b	7955	/* */
Kojto	110:165afa46840b	7956	/******************************************************************************/
Kojto	110:165afa46840b	7957	/**************** Bit definition for SYSCFG_MEMRMP register *************/
Kojto	122:f9eeca106725	7958	#define SYSCFG_MEMRMP_MEM_MODE 0x00000007U /!< SYSCFG_Memory Remap Config /
Kojto	122:f9eeca106725	7959	#define SYSCFG_MEMRMP_MEM_MODE_0 0x00000001U
Kojto	122:f9eeca106725	7960	#define SYSCFG_MEMRMP_MEM_MODE_1 0x00000002U
Kojto	122:f9eeca106725	7961	#define SYSCFG_MEMRMP_MEM_MODE_2 0x00000004U
Kojto	122:f9eeca106725	7962
Kojto	122:f9eeca106725	7963	#define SYSCFG_MEMRMP_UFB_MODE 0x00000100U /!< User Flash Bank mode /
Kojto	122:f9eeca106725	7964	#define SYSCFG_SWP_FMC 0x00000C00U /!< FMC memory mapping swap /
Kojto	110:165afa46840b	7965
Kojto	110:165afa46840b	7966	/**************** Bit definition for SYSCFG_PMC register ****************/
Kojto	122:f9eeca106725	7967	#define SYSCFG_PMC_ADCxDC2 0x00070000U /!< Refer to AN4073 on how to use this bit /
Kojto	122:f9eeca106725	7968	#define SYSCFG_PMC_ADC1DC2 0x00010000U /!< Refer to AN4073 on how to use this bit /
Kojto	122:f9eeca106725	7969	#define SYSCFG_PMC_ADC2DC2 0x00020000U /!< Refer to AN4073 on how to use this bit /
Kojto	122:f9eeca106725	7970	#define SYSCFG_PMC_ADC3DC2 0x00040000U /!< Refer to AN4073 on how to use this bit /
Kojto	122:f9eeca106725	7971
Kojto	122:f9eeca106725	7972	#define SYSCFG_PMC_MII_RMII_SEL 0x00800000U /!<Ethernet PHY interface selection /
Kojto	110:165afa46840b	7973
Kojto	110:165afa46840b	7974	/*************** Bit definition for SYSCFG_EXTICR1 register *************/
Kojto	122:f9eeca106725	7975	#define SYSCFG_EXTICR1_EXTI0 0x000FU /!<EXTI 0 configuration /
Kojto	122:f9eeca106725	7976	#define SYSCFG_EXTICR1_EXTI1 0x00F0U /!<EXTI 1 configuration /
Kojto	122:f9eeca106725	7977	#define SYSCFG_EXTICR1_EXTI2 0x0F00U /!<EXTI 2 configuration /
Kojto	122:f9eeca106725	7978	#define SYSCFG_EXTICR1_EXTI3 0xF000U /!<EXTI 3 configuration /
Kojto	110:165afa46840b	7979	/**
Kojto	110:165afa46840b	7980	* @brief EXTI0 configuration
Kojto	110:165afa46840b	7981	*/
Kojto	122:f9eeca106725	7982	#define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /!<PA[0] pin /
Kojto	122:f9eeca106725	7983	#define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /!<PB[0] pin /
Kojto	122:f9eeca106725	7984	#define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /!<PC[0] pin /
Kojto	122:f9eeca106725	7985	#define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /!<PD[0] pin /
Kojto	122:f9eeca106725	7986	#define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /!<PE[0] pin /
Kojto	122:f9eeca106725	7987	#define SYSCFG_EXTICR1_EXTI0_PF 0x0005U /!<PF[0] pin /
Kojto	122:f9eeca106725	7988	#define SYSCFG_EXTICR1_EXTI0_PG 0x0006U /!<PG[0] pin /
Kojto	122:f9eeca106725	7989	#define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /!<PH[0] pin /
Kojto	122:f9eeca106725	7990	#define SYSCFG_EXTICR1_EXTI0_PI 0x0008U /!<PI[0] pin /
Kojto	122:f9eeca106725	7991	#define SYSCFG_EXTICR1_EXTI0_PJ 0x0009U /!<PJ[0] pin /
Kojto	122:f9eeca106725	7992	#define SYSCFG_EXTICR1_EXTI0_PK 0x000AU /!<PK[0] pin /
Kojto	110:165afa46840b	7993
Kojto	110:165afa46840b	7994	/**
Kojto	110:165afa46840b	7995	* @brief EXTI1 configuration
Kojto	110:165afa46840b	7996	*/
Kojto	122:f9eeca106725	7997	#define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /!<PA[1] pin /
Kojto	122:f9eeca106725	7998	#define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /!<PB[1] pin /
Kojto	122:f9eeca106725	7999	#define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /!<PC[1] pin /
Kojto	122:f9eeca106725	8000	#define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /!<PD[1] pin /
Kojto	122:f9eeca106725	8001	#define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /!<PE[1] pin /
Kojto	122:f9eeca106725	8002	#define SYSCFG_EXTICR1_EXTI1_PF 0x0050U /!<PF[1] pin /
Kojto	122:f9eeca106725	8003	#define SYSCFG_EXTICR1_EXTI1_PG 0x0060U /!<PG[1] pin /
Kojto	122:f9eeca106725	8004	#define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /!<PH[1] pin /
Kojto	122:f9eeca106725	8005	#define SYSCFG_EXTICR1_EXTI1_PI 0x0080U /!<PI[1] pin /
Kojto	122:f9eeca106725	8006	#define SYSCFG_EXTICR1_EXTI1_PJ 0x0090U /!<PJ[1] pin /
Kojto	122:f9eeca106725	8007	#define SYSCFG_EXTICR1_EXTI1_PK 0x00A0U /!<PK[1] pin /
Kojto	110:165afa46840b	8008
Kojto	110:165afa46840b	8009
Kojto	110:165afa46840b	8010	/**
Kojto	110:165afa46840b	8011	* @brief EXTI2 configuration
Kojto	110:165afa46840b	8012	*/
Kojto	122:f9eeca106725	8013	#define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /!<PA[2] pin /
Kojto	122:f9eeca106725	8014	#define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /!<PB[2] pin /
Kojto	122:f9eeca106725	8015	#define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /!<PC[2] pin /
Kojto	122:f9eeca106725	8016	#define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /!<PD[2] pin /
Kojto	122:f9eeca106725	8017	#define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /!<PE[2] pin /
Kojto	122:f9eeca106725	8018	#define SYSCFG_EXTICR1_EXTI2_PF 0x0500U /!<PF[2] pin /
Kojto	122:f9eeca106725	8019	#define SYSCFG_EXTICR1_EXTI2_PG 0x0600U /!<PG[2] pin /
Kojto	122:f9eeca106725	8020	#define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /!<PH[2] pin /
Kojto	122:f9eeca106725	8021	#define SYSCFG_EXTICR1_EXTI2_PI 0x0800U /!<PI[2] pin /
Kojto	122:f9eeca106725	8022	#define SYSCFG_EXTICR1_EXTI2_PJ 0x0900U /!<PJ[2] pin /
Kojto	122:f9eeca106725	8023	#define SYSCFG_EXTICR1_EXTI2_PK 0x0A00U /!<PK[2] pin /
Kojto	110:165afa46840b	8024
Kojto	110:165afa46840b	8025
Kojto	110:165afa46840b	8026	/**
Kojto	110:165afa46840b	8027	* @brief EXTI3 configuration
Kojto	110:165afa46840b	8028	*/
Kojto	122:f9eeca106725	8029	#define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /!<PA[3] pin /
Kojto	122:f9eeca106725	8030	#define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /!<PB[3] pin /
Kojto	122:f9eeca106725	8031	#define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /!<PC[3] pin /
Kojto	122:f9eeca106725	8032	#define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /!<PD[3] pin /
Kojto	122:f9eeca106725	8033	#define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /!<PE[3] pin /
Kojto	122:f9eeca106725	8034	#define SYSCFG_EXTICR1_EXTI3_PF 0x5000U /!<PF[3] pin /
Kojto	122:f9eeca106725	8035	#define SYSCFG_EXTICR1_EXTI3_PG 0x6000U /!<PG[3] pin /
Kojto	122:f9eeca106725	8036	#define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /!<PH[3] pin /
Kojto	122:f9eeca106725	8037	#define SYSCFG_EXTICR1_EXTI3_PI 0x8000U /!<PI[3] pin /
Kojto	122:f9eeca106725	8038	#define SYSCFG_EXTICR1_EXTI3_PJ 0x9000U /!<PJ[3] pin /
Kojto	122:f9eeca106725	8039	#define SYSCFG_EXTICR1_EXTI3_PK 0xA000U /!<PK[3] pin /
Kojto	110:165afa46840b	8040
Kojto	110:165afa46840b	8041
Kojto	110:165afa46840b	8042	/*************** Bit definition for SYSCFG_EXTICR2 register *************/
Kojto	122:f9eeca106725	8043	#define SYSCFG_EXTICR2_EXTI4 0x000FU /!<EXTI 4 configuration /
Kojto	122:f9eeca106725	8044	#define SYSCFG_EXTICR2_EXTI5 0x00F0U /!<EXTI 5 configuration /
Kojto	122:f9eeca106725	8045	#define SYSCFG_EXTICR2_EXTI6 0x0F00U /!<EXTI 6 configuration /
Kojto	122:f9eeca106725	8046	#define SYSCFG_EXTICR2_EXTI7 0xF000U /!<EXTI 7 configuration /
Kojto	110:165afa46840b	8047	/**
Kojto	110:165afa46840b	8048	* @brief EXTI4 configuration
Kojto	110:165afa46840b	8049	*/
Kojto	122:f9eeca106725	8050	#define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /!<PA[4] pin /
Kojto	122:f9eeca106725	8051	#define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /!<PB[4] pin /
Kojto	122:f9eeca106725	8052	#define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /!<PC[4] pin /
Kojto	122:f9eeca106725	8053	#define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /!<PD[4] pin /
Kojto	122:f9eeca106725	8054	#define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /!<PE[4] pin /
Kojto	122:f9eeca106725	8055	#define SYSCFG_EXTICR2_EXTI4_PF 0x0005U /!<PF[4] pin /
Kojto	122:f9eeca106725	8056	#define SYSCFG_EXTICR2_EXTI4_PG 0x0006U /!<PG[4] pin /
Kojto	122:f9eeca106725	8057	#define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /!<PH[4] pin /
Kojto	122:f9eeca106725	8058	#define SYSCFG_EXTICR2_EXTI4_PI 0x0008U /!<PI[4] pin /
Kojto	122:f9eeca106725	8059	#define SYSCFG_EXTICR2_EXTI4_PJ 0x0009U /!<PJ[4] pin /
Kojto	122:f9eeca106725	8060	#define SYSCFG_EXTICR2_EXTI4_PK 0x000AU /!<PK[4] pin /
Kojto	110:165afa46840b	8061
Kojto	110:165afa46840b	8062	/**
Kojto	110:165afa46840b	8063	* @brief EXTI5 configuration
Kojto	110:165afa46840b	8064	*/
Kojto	122:f9eeca106725	8065	#define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /!<PA[5] pin /
Kojto	122:f9eeca106725	8066	#define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /!<PB[5] pin /
Kojto	122:f9eeca106725	8067	#define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /!<PC[5] pin /
Kojto	122:f9eeca106725	8068	#define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /!<PD[5] pin /
Kojto	122:f9eeca106725	8069	#define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /!<PE[5] pin /
Kojto	122:f9eeca106725	8070	#define SYSCFG_EXTICR2_EXTI5_PF 0x0050U /!<PF[5] pin /
Kojto	122:f9eeca106725	8071	#define SYSCFG_EXTICR2_EXTI5_PG 0x0060U /!<PG[5] pin /
Kojto	122:f9eeca106725	8072	#define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /!<PH[5] pin /
Kojto	122:f9eeca106725	8073	#define SYSCFG_EXTICR2_EXTI5_PI 0x0080U /!<PI[5] pin /
Kojto	122:f9eeca106725	8074	#define SYSCFG_EXTICR2_EXTI5_PJ 0x0090U /!<PJ[5] pin /
Kojto	122:f9eeca106725	8075	#define SYSCFG_EXTICR2_EXTI5_PK 0x00A0U /!<PK[5] pin /
Kojto	110:165afa46840b	8076
Kojto	110:165afa46840b	8077	/**
Kojto	110:165afa46840b	8078	* @brief EXTI6 configuration
Kojto	110:165afa46840b	8079	*/
Kojto	122:f9eeca106725	8080	#define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /!<PA[6] pin /
Kojto	122:f9eeca106725	8081	#define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /!<PB[6] pin /
Kojto	122:f9eeca106725	8082	#define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /!<PC[6] pin /
Kojto	122:f9eeca106725	8083	#define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /!<PD[6] pin /
Kojto	122:f9eeca106725	8084	#define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /!<PE[6] pin /
Kojto	122:f9eeca106725	8085	#define SYSCFG_EXTICR2_EXTI6_PF 0x0500U /!<PF[6] pin /
Kojto	122:f9eeca106725	8086	#define SYSCFG_EXTICR2_EXTI6_PG 0x0600U /!<PG[6] pin /
Kojto	122:f9eeca106725	8087	#define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /!<PH[6] pin /
Kojto	122:f9eeca106725	8088	#define SYSCFG_EXTICR2_EXTI6_PI 0x0800U /!<PI[6] pin /
Kojto	122:f9eeca106725	8089	#define SYSCFG_EXTICR2_EXTI6_PJ 0x0900U /!<PJ[6] pin /
Kojto	122:f9eeca106725	8090	#define SYSCFG_EXTICR2_EXTI6_PK 0x0A00U /!<PK[6] pin /
Kojto	110:165afa46840b	8091
Kojto	110:165afa46840b	8092
Kojto	110:165afa46840b	8093	/**
Kojto	110:165afa46840b	8094	* @brief EXTI7 configuration
Kojto	110:165afa46840b	8095	*/
Kojto	122:f9eeca106725	8096	#define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /!<PA[7] pin /
Kojto	122:f9eeca106725	8097	#define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /!<PB[7] pin /
Kojto	122:f9eeca106725	8098	#define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /!<PC[7] pin /
Kojto	122:f9eeca106725	8099	#define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /!<PD[7] pin /
Kojto	122:f9eeca106725	8100	#define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /!<PE[7] pin /
Kojto	122:f9eeca106725	8101	#define SYSCFG_EXTICR2_EXTI7_PF 0x5000U /!<PF[7] pin /
Kojto	122:f9eeca106725	8102	#define SYSCFG_EXTICR2_EXTI7_PG 0x6000U /!<PG[7] pin /
Kojto	122:f9eeca106725	8103	#define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /!<PH[7] pin /
Kojto	122:f9eeca106725	8104	#define SYSCFG_EXTICR2_EXTI7_PI 0x8000U /!<PI[7] pin /
Kojto	122:f9eeca106725	8105	#define SYSCFG_EXTICR2_EXTI7_PJ 0x9000U /!<PJ[7] pin /
Kojto	122:f9eeca106725	8106	#define SYSCFG_EXTICR2_EXTI7_PK 0xA000U /!<PK[7] pin /
Kojto	110:165afa46840b	8107
Kojto	110:165afa46840b	8108	/*************** Bit definition for SYSCFG_EXTICR3 register *************/
Kojto	122:f9eeca106725	8109	#define SYSCFG_EXTICR3_EXTI8 0x000FU /!<EXTI 8 configuration /
Kojto	122:f9eeca106725	8110	#define SYSCFG_EXTICR3_EXTI9 0x00F0U /!<EXTI 9 configuration /
Kojto	122:f9eeca106725	8111	#define SYSCFG_EXTICR3_EXTI10 0x0F00U /!<EXTI 10 configuration /
Kojto	122:f9eeca106725	8112	#define SYSCFG_EXTICR3_EXTI11 0xF000U /!<EXTI 11 configuration /
Kojto	110:165afa46840b	8113
Kojto	110:165afa46840b	8114	/**
Kojto	110:165afa46840b	8115	* @brief EXTI8 configuration
Kojto	110:165afa46840b	8116	*/
Kojto	122:f9eeca106725	8117	#define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /!<PA[8] pin /
Kojto	122:f9eeca106725	8118	#define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /!<PB[8] pin /
Kojto	122:f9eeca106725	8119	#define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /!<PC[8] pin /
Kojto	122:f9eeca106725	8120	#define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /!<PD[8] pin /
Kojto	122:f9eeca106725	8121	#define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /!<PE[8] pin /
Kojto	122:f9eeca106725	8122	#define SYSCFG_EXTICR3_EXTI8_PF 0x0005U /!<PF[8] pin /
Kojto	122:f9eeca106725	8123	#define SYSCFG_EXTICR3_EXTI8_PG 0x0006U /!<PG[8] pin /
Kojto	122:f9eeca106725	8124	#define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /!<PH[8] pin /
Kojto	122:f9eeca106725	8125	#define SYSCFG_EXTICR3_EXTI8_PI 0x0008U /!<PI[8] pin /
Kojto	122:f9eeca106725	8126	#define SYSCFG_EXTICR3_EXTI8_PJ 0x0009U /!<PJ[8] pin /
Kojto	110:165afa46840b	8127
Kojto	110:165afa46840b	8128	/**
Kojto	110:165afa46840b	8129	* @brief EXTI9 configuration
Kojto	110:165afa46840b	8130	*/
Kojto	122:f9eeca106725	8131	#define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /!<PA[9] pin /
Kojto	122:f9eeca106725	8132	#define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /!<PB[9] pin /
Kojto	122:f9eeca106725	8133	#define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /!<PC[9] pin /
Kojto	122:f9eeca106725	8134	#define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /!<PD[9] pin /
Kojto	122:f9eeca106725	8135	#define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /!<PE[9] pin /
Kojto	122:f9eeca106725	8136	#define SYSCFG_EXTICR3_EXTI9_PF 0x0050U /!<PF[9] pin /
Kojto	122:f9eeca106725	8137	#define SYSCFG_EXTICR3_EXTI9_PG 0x0060U /!<PG[9] pin /
Kojto	122:f9eeca106725	8138	#define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /!<PH[9] pin /
Kojto	122:f9eeca106725	8139	#define SYSCFG_EXTICR3_EXTI9_PI 0x0080U /!<PI[9] pin /
Kojto	122:f9eeca106725	8140	#define SYSCFG_EXTICR3_EXTI9_PJ 0x0090U /!<PJ[9] pin /
Kojto	110:165afa46840b	8141
Kojto	110:165afa46840b	8142
Kojto	110:165afa46840b	8143	/**
Kojto	110:165afa46840b	8144	* @brief EXTI10 configuration
Kojto	110:165afa46840b	8145	*/
Kojto	122:f9eeca106725	8146	#define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /!<PA[10] pin /
Kojto	122:f9eeca106725	8147	#define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /!<PB[10] pin /
Kojto	122:f9eeca106725	8148	#define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /!<PC[10] pin /
Kojto	122:f9eeca106725	8149	#define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /!<PD[10] pin /
Kojto	122:f9eeca106725	8150	#define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /!<PE[10] pin /
Kojto	122:f9eeca106725	8151	#define SYSCFG_EXTICR3_EXTI10_PF 0x0500U /!<PF[10] pin /
Kojto	122:f9eeca106725	8152	#define SYSCFG_EXTICR3_EXTI10_PG 0x0600U /!<PG[10] pin /
Kojto	122:f9eeca106725	8153	#define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /!<PH[10] pin /
Kojto	122:f9eeca106725	8154	#define SYSCFG_EXTICR3_EXTI10_PI 0x0800U /!<PI[10] pin /
Kojto	122:f9eeca106725	8155	#define SYSCFG_EXTICR3_EXTI10_PJ 0x0900U /!<PJ[10] pin /
Kojto	110:165afa46840b	8156
Kojto	110:165afa46840b	8157
Kojto	110:165afa46840b	8158	/**
Kojto	110:165afa46840b	8159	* @brief EXTI11 configuration
Kojto	110:165afa46840b	8160	*/
Kojto	122:f9eeca106725	8161	#define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /!<PA[11] pin /
Kojto	122:f9eeca106725	8162	#define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /!<PB[11] pin /
Kojto	122:f9eeca106725	8163	#define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /!<PC[11] pin /
Kojto	122:f9eeca106725	8164	#define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /!<PD[11] pin /
Kojto	122:f9eeca106725	8165	#define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /!<PE[11] pin /
Kojto	122:f9eeca106725	8166	#define SYSCFG_EXTICR3_EXTI11_PF 0x5000U /!<PF[11] pin /
Kojto	122:f9eeca106725	8167	#define SYSCFG_EXTICR3_EXTI11_PG 0x6000U /!<PG[11] pin /
Kojto	122:f9eeca106725	8168	#define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /!<PH[11] pin /
Kojto	122:f9eeca106725	8169	#define SYSCFG_EXTICR3_EXTI11_PI 0x8000U /!<PI[11] pin /
Kojto	122:f9eeca106725	8170	#define SYSCFG_EXTICR3_EXTI11_PJ 0x9000U /!<PJ[11] pin /
Kojto	110:165afa46840b	8171
Kojto	110:165afa46840b	8172
Kojto	110:165afa46840b	8173	/*************** Bit definition for SYSCFG_EXTICR4 register *************/
Kojto	122:f9eeca106725	8174	#define SYSCFG_EXTICR4_EXTI12 0x000FU /!<EXTI 12 configuration /
Kojto	122:f9eeca106725	8175	#define SYSCFG_EXTICR4_EXTI13 0x00F0U /!<EXTI 13 configuration /
Kojto	122:f9eeca106725	8176	#define SYSCFG_EXTICR4_EXTI14 0x0F00U /!<EXTI 14 configuration /
Kojto	122:f9eeca106725	8177	#define SYSCFG_EXTICR4_EXTI15 0xF000U /!<EXTI 15 configuration /
Kojto	110:165afa46840b	8178	/**
Kojto	110:165afa46840b	8179	* @brief EXTI12 configuration
Kojto	110:165afa46840b	8180	*/
Kojto	122:f9eeca106725	8181	#define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /!<PA[12] pin /
Kojto	122:f9eeca106725	8182	#define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /!<PB[12] pin /
Kojto	122:f9eeca106725	8183	#define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /!<PC[12] pin /
Kojto	122:f9eeca106725	8184	#define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /!<PD[12] pin /
Kojto	122:f9eeca106725	8185	#define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /!<PE[12] pin /
Kojto	122:f9eeca106725	8186	#define SYSCFG_EXTICR4_EXTI12_PF 0x0005U /!<PF[12] pin /
Kojto	122:f9eeca106725	8187	#define SYSCFG_EXTICR4_EXTI12_PG 0x0006U /!<PG[12] pin /
Kojto	122:f9eeca106725	8188	#define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /!<PH[12] pin /
Kojto	122:f9eeca106725	8189	#define SYSCFG_EXTICR4_EXTI12_PI 0x0008U /!<PI[12] pin /
Kojto	122:f9eeca106725	8190	#define SYSCFG_EXTICR4_EXTI12_PJ 0x0009U /!<PJ[12] pin /
Kojto	110:165afa46840b	8191
Kojto	110:165afa46840b	8192
Kojto	110:165afa46840b	8193	/**
Kojto	110:165afa46840b	8194	* @brief EXTI13 configuration
Kojto	110:165afa46840b	8195	*/
Kojto	122:f9eeca106725	8196	#define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /!<PA[13] pin /
Kojto	122:f9eeca106725	8197	#define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /!<PB[13] pin /
Kojto	122:f9eeca106725	8198	#define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /!<PC[13] pin /
Kojto	122:f9eeca106725	8199	#define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /!<PD[13] pin /
Kojto	122:f9eeca106725	8200	#define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /!<PE[13] pin /
Kojto	122:f9eeca106725	8201	#define SYSCFG_EXTICR4_EXTI13_PF 0x0050U /!<PF[13] pin /
Kojto	122:f9eeca106725	8202	#define SYSCFG_EXTICR4_EXTI13_PG 0x0060U /!<PG[13] pin /
Kojto	122:f9eeca106725	8203	#define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /!<PH[13] pin /
Kojto	122:f9eeca106725	8204	#define SYSCFG_EXTICR4_EXTI13_PI 0x0008U /!<PI[13] pin /
Kojto	122:f9eeca106725	8205	#define SYSCFG_EXTICR4_EXTI13_PJ 0x0009U /!<PJ[13] pin /
Kojto	110:165afa46840b	8206
Kojto	110:165afa46840b	8207
Kojto	110:165afa46840b	8208	/**
Kojto	110:165afa46840b	8209	* @brief EXTI14 configuration
Kojto	110:165afa46840b	8210	*/
Kojto	122:f9eeca106725	8211	#define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /!<PA[14] pin /
Kojto	122:f9eeca106725	8212	#define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /!<PB[14] pin /
Kojto	122:f9eeca106725	8213	#define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /!<PC[14] pin /
Kojto	122:f9eeca106725	8214	#define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /!<PD[14] pin /
Kojto	122:f9eeca106725	8215	#define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /!<PE[14] pin /
Kojto	122:f9eeca106725	8216	#define SYSCFG_EXTICR4_EXTI14_PF 0x0500U /!<PF[14] pin /
Kojto	122:f9eeca106725	8217	#define SYSCFG_EXTICR4_EXTI14_PG 0x0600U /!<PG[14] pin /
Kojto	122:f9eeca106725	8218	#define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /!<PH[14] pin /
Kojto	122:f9eeca106725	8219	#define SYSCFG_EXTICR4_EXTI14_PI 0x0800U /!<PI[14] pin /
Kojto	122:f9eeca106725	8220	#define SYSCFG_EXTICR4_EXTI14_PJ 0x0900U /!<PJ[14] pin /
Kojto	110:165afa46840b	8221
Kojto	110:165afa46840b	8222
Kojto	110:165afa46840b	8223	/**
Kojto	110:165afa46840b	8224	* @brief EXTI15 configuration
Kojto	110:165afa46840b	8225	*/
Kojto	122:f9eeca106725	8226	#define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /!<PA[15] pin /
Kojto	122:f9eeca106725	8227	#define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /!<PB[15] pin /
Kojto	122:f9eeca106725	8228	#define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /!<PC[15] pin /
Kojto	122:f9eeca106725	8229	#define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /!<PD[15] pin /
Kojto	122:f9eeca106725	8230	#define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /!<PE[15] pin /
Kojto	122:f9eeca106725	8231	#define SYSCFG_EXTICR4_EXTI15_PF 0x5000U /!<PF[15] pin /
Kojto	122:f9eeca106725	8232	#define SYSCFG_EXTICR4_EXTI15_PG 0x6000U /!<PG[15] pin /
Kojto	122:f9eeca106725	8233	#define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /!<PH[15] pin /
Kojto	122:f9eeca106725	8234	#define SYSCFG_EXTICR4_EXTI15_PI 0x8000U /!<PI[15] pin /
Kojto	122:f9eeca106725	8235	#define SYSCFG_EXTICR4_EXTI15_PJ 0x9000U /!<PJ[15] pin /
Kojto	110:165afa46840b	8236
Kojto	110:165afa46840b	8237	/**************** Bit definition for SYSCFG_CMPCR register **************/
Kojto	122:f9eeca106725	8238	#define SYSCFG_CMPCR_CMP_PD 0x00000001U /!<Compensation cell ready flag /
Kojto	122:f9eeca106725	8239	#define SYSCFG_CMPCR_READY 0x00000100U /!<Compensation cell power-down /
Kojto	110:165afa46840b	8240
Kojto	110:165afa46840b	8241	/******************************************************************************/
Kojto	110:165afa46840b	8242	/* */
Kojto	110:165afa46840b	8243	/* TIM */
Kojto	110:165afa46840b	8244	/* */
Kojto	110:165afa46840b	8245	/******************************************************************************/
Kojto	110:165afa46840b	8246	/***************** Bit definition for TIM_CR1 register ******************/
Kojto	122:f9eeca106725	8247	#define TIM_CR1_CEN 0x0001U /!<Counter enable /
Kojto	122:f9eeca106725	8248	#define TIM_CR1_UDIS 0x0002U /!<Update disable /
Kojto	122:f9eeca106725	8249	#define TIM_CR1_URS 0x0004U /!<Update request source /
Kojto	122:f9eeca106725	8250	#define TIM_CR1_OPM 0x0008U /!<One pulse mode /
Kojto	122:f9eeca106725	8251	#define TIM_CR1_DIR 0x0010U /!<Direction /
Kojto	122:f9eeca106725	8252
Kojto	122:f9eeca106725	8253	#define TIM_CR1_CMS 0x0060U /!<CMS[1:0] bits (Center-aligned mode selection) /
Kojto	122:f9eeca106725	8254	#define TIM_CR1_CMS_0 0x0020U /!<Bit 0 /
Kojto	122:f9eeca106725	8255	#define TIM_CR1_CMS_1 0x0040U /!<Bit 1 /
Kojto	122:f9eeca106725	8256
Kojto	122:f9eeca106725	8257	#define TIM_CR1_ARPE 0x0080U /!<Auto-reload preload enable /
Kojto	122:f9eeca106725	8258
Kojto	122:f9eeca106725	8259	#define TIM_CR1_CKD 0x0300U /!<CKD[1:0] bits (clock division) /
Kojto	122:f9eeca106725	8260	#define TIM_CR1_CKD_0 0x0100U /!<Bit 0 /
Kojto	122:f9eeca106725	8261	#define TIM_CR1_CKD_1 0x0200U /!<Bit 1 /
Kojto	110:165afa46840b	8262
Kojto	110:165afa46840b	8263	/***************** Bit definition for TIM_CR2 register ******************/
Kojto	122:f9eeca106725	8264	#define TIM_CR2_CCPC 0x0001U /!<Capture/Compare Preloaded Control /
Kojto	122:f9eeca106725	8265	#define TIM_CR2_CCUS 0x0004U /!<Capture/Compare Control Update Selection /
Kojto	122:f9eeca106725	8266	#define TIM_CR2_CCDS 0x0008U /!<Capture/Compare DMA Selection /
Kojto	122:f9eeca106725	8267
Kojto	122:f9eeca106725	8268	#define TIM_CR2_MMS 0x0070U /!<MMS[2:0] bits (Master Mode Selection) /
Kojto	122:f9eeca106725	8269	#define TIM_CR2_MMS_0 0x0010U /!<Bit 0 /
Kojto	122:f9eeca106725	8270	#define TIM_CR2_MMS_1 0x0020U /!<Bit 1 /
Kojto	122:f9eeca106725	8271	#define TIM_CR2_MMS_2 0x0040U /!<Bit 2 /
Kojto	122:f9eeca106725	8272
Kojto	122:f9eeca106725	8273	#define TIM_CR2_TI1S 0x0080U /!<TI1 Selection /
Kojto	122:f9eeca106725	8274	#define TIM_CR2_OIS1 0x0100U /!<Output Idle state 1 (OC1 output) /
Kojto	122:f9eeca106725	8275	#define TIM_CR2_OIS1N 0x0200U /!<Output Idle state 1 (OC1N output) /
Kojto	122:f9eeca106725	8276	#define TIM_CR2_OIS2 0x0400U /!<Output Idle state 2 (OC2 output) /
Kojto	122:f9eeca106725	8277	#define TIM_CR2_OIS2N 0x0800U /!<Output Idle state 2 (OC2N output) /
Kojto	122:f9eeca106725	8278	#define TIM_CR2_OIS3 0x1000U /!<Output Idle state 3 (OC3 output) /
Kojto	122:f9eeca106725	8279	#define TIM_CR2_OIS3N 0x2000U /!<Output Idle state 3 (OC3N output) /
Kojto	122:f9eeca106725	8280	#define TIM_CR2_OIS4 0x4000U /!<Output Idle state 4 (OC4 output) /
Kojto	110:165afa46840b	8281
Kojto	110:165afa46840b	8282	/***************** Bit definition for TIM_SMCR register *****************/
Kojto	122:f9eeca106725	8283	#define TIM_SMCR_SMS 0x0007U /!<SMS[2:0] bits (Slave mode selection) /
Kojto	122:f9eeca106725	8284	#define TIM_SMCR_SMS_0 0x0001U /!<Bit 0 /
Kojto	122:f9eeca106725	8285	#define TIM_SMCR_SMS_1 0x0002U /!<Bit 1 /
Kojto	122:f9eeca106725	8286	#define TIM_SMCR_SMS_2 0x0004U /!<Bit 2 /
Kojto	122:f9eeca106725	8287
Kojto	122:f9eeca106725	8288	#define TIM_SMCR_TS 0x0070U /!<TS[2:0] bits (Trigger selection) /
Kojto	122:f9eeca106725	8289	#define TIM_SMCR_TS_0 0x0010U /!<Bit 0 /
Kojto	122:f9eeca106725	8290	#define TIM_SMCR_TS_1 0x0020U /!<Bit 1 /
Kojto	122:f9eeca106725	8291	#define TIM_SMCR_TS_2 0x0040U /!<Bit 2 /
Kojto	122:f9eeca106725	8292
Kojto	122:f9eeca106725	8293	#define TIM_SMCR_MSM 0x0080U /!<Master/slave mode /
Kojto	122:f9eeca106725	8294
Kojto	122:f9eeca106725	8295	#define TIM_SMCR_ETF 0x0F00U /!<ETF[3:0] bits (External trigger filter) /
Kojto	122:f9eeca106725	8296	#define TIM_SMCR_ETF_0 0x0100U /!<Bit 0 /
Kojto	122:f9eeca106725	8297	#define TIM_SMCR_ETF_1 0x0200U /!<Bit 1 /
Kojto	122:f9eeca106725	8298	#define TIM_SMCR_ETF_2 0x0400U /!<Bit 2 /
Kojto	122:f9eeca106725	8299	#define TIM_SMCR_ETF_3 0x0800U /!<Bit 3 /
Kojto	122:f9eeca106725	8300
Kojto	122:f9eeca106725	8301	#define TIM_SMCR_ETPS 0x3000U /!<ETPS[1:0] bits (External trigger prescaler) /
Kojto	122:f9eeca106725	8302	#define TIM_SMCR_ETPS_0 0x1000U /!<Bit 0 /
Kojto	122:f9eeca106725	8303	#define TIM_SMCR_ETPS_1 0x2000U /!<Bit 1 /
Kojto	122:f9eeca106725	8304
Kojto	122:f9eeca106725	8305	#define TIM_SMCR_ECE 0x4000U /!<External clock enable /
Kojto	122:f9eeca106725	8306	#define TIM_SMCR_ETP 0x8000U /!<External trigger polarity /
Kojto	110:165afa46840b	8307
Kojto	110:165afa46840b	8308	/***************** Bit definition for TIM_DIER register *****************/
Kojto	122:f9eeca106725	8309	#define TIM_DIER_UIE 0x0001U /!<Update interrupt enable /
Kojto	122:f9eeca106725	8310	#define TIM_DIER_CC1IE 0x0002U /!<Capture/Compare 1 interrupt enable /
Kojto	122:f9eeca106725	8311	#define TIM_DIER_CC2IE 0x0004U /!<Capture/Compare 2 interrupt enable /
Kojto	122:f9eeca106725	8312	#define TIM_DIER_CC3IE 0x0008U /!<Capture/Compare 3 interrupt enable /
Kojto	122:f9eeca106725	8313	#define TIM_DIER_CC4IE 0x0010U /!<Capture/Compare 4 interrupt enable /
Kojto	122:f9eeca106725	8314	#define TIM_DIER_COMIE 0x0020U /!<COM interrupt enable /
Kojto	122:f9eeca106725	8315	#define TIM_DIER_TIE 0x0040U /!<Trigger interrupt enable /
Kojto	122:f9eeca106725	8316	#define TIM_DIER_BIE 0x0080U /!<Break interrupt enable /
Kojto	122:f9eeca106725	8317	#define TIM_DIER_UDE 0x0100U /!<Update DMA request enable /
Kojto	122:f9eeca106725	8318	#define TIM_DIER_CC1DE 0x0200U /!<Capture/Compare 1 DMA request enable /
Kojto	122:f9eeca106725	8319	#define TIM_DIER_CC2DE 0x0400U /!<Capture/Compare 2 DMA request enable /
Kojto	122:f9eeca106725	8320	#define TIM_DIER_CC3DE 0x0800U /!<Capture/Compare 3 DMA request enable /
Kojto	122:f9eeca106725	8321	#define TIM_DIER_CC4DE 0x1000U /!<Capture/Compare 4 DMA request enable /
Kojto	122:f9eeca106725	8322	#define TIM_DIER_COMDE 0x2000U /!<COM DMA request enable /
Kojto	122:f9eeca106725	8323	#define TIM_DIER_TDE 0x4000U /!<Trigger DMA request enable /
Kojto	110:165afa46840b	8324
Kojto	110:165afa46840b	8325	/****************** Bit definition for TIM_SR register ******************/
Kojto	122:f9eeca106725	8326	#define TIM_SR_UIF 0x0001U /!<Update interrupt Flag /
Kojto	122:f9eeca106725	8327	#define TIM_SR_CC1IF 0x0002U /!<Capture/Compare 1 interrupt Flag /
Kojto	122:f9eeca106725	8328	#define TIM_SR_CC2IF 0x0004U /!<Capture/Compare 2 interrupt Flag /
Kojto	122:f9eeca106725	8329	#define TIM_SR_CC3IF 0x0008U /!<Capture/Compare 3 interrupt Flag /
Kojto	122:f9eeca106725	8330	#define TIM_SR_CC4IF 0x0010U /!<Capture/Compare 4 interrupt Flag /
Kojto	122:f9eeca106725	8331	#define TIM_SR_COMIF 0x0020U /!<COM interrupt Flag /
Kojto	122:f9eeca106725	8332	#define TIM_SR_TIF 0x0040U /!<Trigger interrupt Flag /
Kojto	122:f9eeca106725	8333	#define TIM_SR_BIF 0x0080U /!<Break interrupt Flag /
Kojto	122:f9eeca106725	8334	#define TIM_SR_CC1OF 0x0200U /!<Capture/Compare 1 Overcapture Flag /
Kojto	122:f9eeca106725	8335	#define TIM_SR_CC2OF 0x0400U /!<Capture/Compare 2 Overcapture Flag /
Kojto	122:f9eeca106725	8336	#define TIM_SR_CC3OF 0x0800U /!<Capture/Compare 3 Overcapture Flag /
Kojto	122:f9eeca106725	8337	#define TIM_SR_CC4OF 0x1000U /!<Capture/Compare 4 Overcapture Flag /
Kojto	110:165afa46840b	8338
Kojto	110:165afa46840b	8339	/***************** Bit definition for TIM_EGR register ******************/
Kojto	122:f9eeca106725	8340	#define TIM_EGR_UG 0x01U /!<Update Generation /
Kojto	122:f9eeca106725	8341	#define TIM_EGR_CC1G 0x02U /!<Capture/Compare 1 Generation /
Kojto	122:f9eeca106725	8342	#define TIM_EGR_CC2G 0x04U /!<Capture/Compare 2 Generation /
Kojto	122:f9eeca106725	8343	#define TIM_EGR_CC3G 0x08U /!<Capture/Compare 3 Generation /
Kojto	122:f9eeca106725	8344	#define TIM_EGR_CC4G 0x10U /!<Capture/Compare 4 Generation /
Kojto	122:f9eeca106725	8345	#define TIM_EGR_COMG 0x20U /!<Capture/Compare Control Update Generation /
Kojto	122:f9eeca106725	8346	#define TIM_EGR_TG 0x40U /!<Trigger Generation /
Kojto	122:f9eeca106725	8347	#define TIM_EGR_BG 0x80U /!<Break Generation /
Kojto	110:165afa46840b	8348
Kojto	110:165afa46840b	8349	/**************** Bit definition for TIM_CCMR1 register *****************/
Kojto	122:f9eeca106725	8350	#define TIM_CCMR1_CC1S 0x0003U /!<CC1S[1:0] bits (Capture/Compare 1 Selection) /
Kojto	122:f9eeca106725	8351	#define TIM_CCMR1_CC1S_0 0x0001U /!<Bit 0 /
Kojto	122:f9eeca106725	8352	#define TIM_CCMR1_CC1S_1 0x0002U /!<Bit 1 /
Kojto	122:f9eeca106725	8353
Kojto	122:f9eeca106725	8354	#define TIM_CCMR1_OC1FE 0x0004U /!<Output Compare 1 Fast enable /
Kojto	122:f9eeca106725	8355	#define TIM_CCMR1_OC1PE 0x0008U /!<Output Compare 1 Preload enable /
Kojto	122:f9eeca106725	8356
Kojto	122:f9eeca106725	8357	#define TIM_CCMR1_OC1M 0x0070U /!<OC1M[2:0] bits (Output Compare 1 Mode) /
Kojto	122:f9eeca106725	8358	#define TIM_CCMR1_OC1M_0 0x0010U /!<Bit 0 /
Kojto	122:f9eeca106725	8359	#define TIM_CCMR1_OC1M_1 0x0020U /!<Bit 1 /
Kojto	122:f9eeca106725	8360	#define TIM_CCMR1_OC1M_2 0x0040U /!<Bit 2 /
Kojto	122:f9eeca106725	8361
Kojto	122:f9eeca106725	8362	#define TIM_CCMR1_OC1CE 0x0080U /!<Output Compare 1Clear Enable /
Kojto	122:f9eeca106725	8363
Kojto	122:f9eeca106725	8364	#define TIM_CCMR1_CC2S 0x0300U /!<CC2S[1:0] bits (Capture/Compare 2 Selection) /
Kojto	122:f9eeca106725	8365	#define TIM_CCMR1_CC2S_0 0x0100U /!<Bit 0 /
Kojto	122:f9eeca106725	8366	#define TIM_CCMR1_CC2S_1 0x0200U /!<Bit 1 /
Kojto	122:f9eeca106725	8367
Kojto	122:f9eeca106725	8368	#define TIM_CCMR1_OC2FE 0x0400U /!<Output Compare 2 Fast enable /
Kojto	122:f9eeca106725	8369	#define TIM_CCMR1_OC2PE 0x0800U /!<Output Compare 2 Preload enable /
Kojto	122:f9eeca106725	8370
Kojto	122:f9eeca106725	8371	#define TIM_CCMR1_OC2M 0x7000U /!<OC2M[2:0] bits (Output Compare 2 Mode) /
Kojto	122:f9eeca106725	8372	#define TIM_CCMR1_OC2M_0 0x1000U /!<Bit 0 /
Kojto	122:f9eeca106725	8373	#define TIM_CCMR1_OC2M_1 0x2000U /!<Bit 1 /
Kojto	122:f9eeca106725	8374	#define TIM_CCMR1_OC2M_2 0x4000U /!<Bit 2 /
Kojto	122:f9eeca106725	8375
Kojto	122:f9eeca106725	8376	#define TIM_CCMR1_OC2CE 0x8000U /!<Output Compare 2 Clear Enable /
Kojto	110:165afa46840b	8377
Kojto	110:165afa46840b	8378	/----------------------------------------------------------------------------/
Kojto	110:165afa46840b	8379
Kojto	122:f9eeca106725	8380	#define TIM_CCMR1_IC1PSC 0x000CU /!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) /
Kojto	122:f9eeca106725	8381	#define TIM_CCMR1_IC1PSC_0 0x0004U /!<Bit 0 /
Kojto	122:f9eeca106725	8382	#define TIM_CCMR1_IC1PSC_1 0x0008U /!<Bit 1 /
Kojto	122:f9eeca106725	8383
Kojto	122:f9eeca106725	8384	#define TIM_CCMR1_IC1F 0x00F0U /!<IC1F[3:0] bits (Input Capture 1 Filter) /
Kojto	122:f9eeca106725	8385	#define TIM_CCMR1_IC1F_0 0x0010U /!<Bit 0 /
Kojto	122:f9eeca106725	8386	#define TIM_CCMR1_IC1F_1 0x0020U /!<Bit 1 /
Kojto	122:f9eeca106725	8387	#define TIM_CCMR1_IC1F_2 0x0040U /!<Bit 2 /
Kojto	122:f9eeca106725	8388	#define TIM_CCMR1_IC1F_3 0x0080U /!<Bit 3 /
Kojto	122:f9eeca106725	8389
Kojto	122:f9eeca106725	8390	#define TIM_CCMR1_IC2PSC 0x0C00U /!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) /
Kojto	122:f9eeca106725	8391	#define TIM_CCMR1_IC2PSC_0 0x0400U /!<Bit 0 /
Kojto	122:f9eeca106725	8392	#define TIM_CCMR1_IC2PSC_1 0x0800U /!<Bit 1 /
Kojto	122:f9eeca106725	8393
Kojto	122:f9eeca106725	8394	#define TIM_CCMR1_IC2F 0xF000U /!<IC2F[3:0] bits (Input Capture 2 Filter) /
Kojto	122:f9eeca106725	8395	#define TIM_CCMR1_IC2F_0 0x1000U /!<Bit 0 /
Kojto	122:f9eeca106725	8396	#define TIM_CCMR1_IC2F_1 0x2000U /!<Bit 1 /
Kojto	122:f9eeca106725	8397	#define TIM_CCMR1_IC2F_2 0x4000U /!<Bit 2 /
Kojto	122:f9eeca106725	8398	#define TIM_CCMR1_IC2F_3 0x8000U /!<Bit 3 /
Kojto	110:165afa46840b	8399
Kojto	110:165afa46840b	8400	/**************** Bit definition for TIM_CCMR2 register *****************/
Kojto	122:f9eeca106725	8401	#define TIM_CCMR2_CC3S 0x0003U /!<CC3S[1:0] bits (Capture/Compare 3 Selection) /
Kojto	122:f9eeca106725	8402	#define TIM_CCMR2_CC3S_0 0x0001U /!<Bit 0 /
Kojto	122:f9eeca106725	8403	#define TIM_CCMR2_CC3S_1 0x0002U /!<Bit 1 /
Kojto	122:f9eeca106725	8404
Kojto	122:f9eeca106725	8405	#define TIM_CCMR2_OC3FE 0x0004U /!<Output Compare 3 Fast enable /
Kojto	122:f9eeca106725	8406	#define TIM_CCMR2_OC3PE 0x0008U /!<Output Compare 3 Preload enable /
Kojto	122:f9eeca106725	8407
Kojto	122:f9eeca106725	8408	#define TIM_CCMR2_OC3M 0x0070U /!<OC3M[2:0] bits (Output Compare 3 Mode) /
Kojto	122:f9eeca106725	8409	#define TIM_CCMR2_OC3M_0 0x0010U /!<Bit 0 /
Kojto	122:f9eeca106725	8410	#define TIM_CCMR2_OC3M_1 0x0020U /!<Bit 1 /
Kojto	122:f9eeca106725	8411	#define TIM_CCMR2_OC3M_2 0x0040U /!<Bit 2 /
Kojto	122:f9eeca106725	8412
Kojto	122:f9eeca106725	8413	#define TIM_CCMR2_OC3CE 0x0080U /!<Output Compare 3 Clear Enable /
Kojto	122:f9eeca106725	8414
Kojto	122:f9eeca106725	8415	#define TIM_CCMR2_CC4S 0x0300U /!<CC4S[1:0] bits (Capture/Compare 4 Selection) /
Kojto	122:f9eeca106725	8416	#define TIM_CCMR2_CC4S_0 0x0100U /!<Bit 0 /
Kojto	122:f9eeca106725	8417	#define TIM_CCMR2_CC4S_1 0x0200U /!<Bit 1 /
Kojto	122:f9eeca106725	8418
Kojto	122:f9eeca106725	8419	#define TIM_CCMR2_OC4FE 0x0400U /!<Output Compare 4 Fast enable /
Kojto	122:f9eeca106725	8420	#define TIM_CCMR2_OC4PE 0x0800U /!<Output Compare 4 Preload enable /
Kojto	122:f9eeca106725	8421
Kojto	122:f9eeca106725	8422	#define TIM_CCMR2_OC4M 0x7000U /!<OC4M[2:0] bits (Output Compare 4 Mode) /
Kojto	122:f9eeca106725	8423	#define TIM_CCMR2_OC4M_0 0x1000U /!<Bit 0 /
Kojto	122:f9eeca106725	8424	#define TIM_CCMR2_OC4M_1 0x2000U /!<Bit 1 /
Kojto	122:f9eeca106725	8425	#define TIM_CCMR2_OC4M_2 0x4000U /!<Bit 2 /
Kojto	122:f9eeca106725	8426
Kojto	122:f9eeca106725	8427	#define TIM_CCMR2_OC4CE 0x8000U /!<Output Compare 4 Clear Enable /
Kojto	110:165afa46840b	8428
Kojto	110:165afa46840b	8429	/----------------------------------------------------------------------------/
Kojto	110:165afa46840b	8430
Kojto	122:f9eeca106725	8431	#define TIM_CCMR2_IC3PSC 0x000CU /!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) /
Kojto	122:f9eeca106725	8432	#define TIM_CCMR2_IC3PSC_0 0x0004U /!<Bit 0 /
Kojto	122:f9eeca106725	8433	#define TIM_CCMR2_IC3PSC_1 0x0008U /!<Bit 1 /
Kojto	122:f9eeca106725	8434
Kojto	122:f9eeca106725	8435	#define TIM_CCMR2_IC3F 0x00F0U /!<IC3F[3:0] bits (Input Capture 3 Filter) /
Kojto	122:f9eeca106725	8436	#define TIM_CCMR2_IC3F_0 0x0010U /!<Bit 0 /
Kojto	122:f9eeca106725	8437	#define TIM_CCMR2_IC3F_1 0x0020U /!<Bit 1 /
Kojto	122:f9eeca106725	8438	#define TIM_CCMR2_IC3F_2 0x0040U /!<Bit 2 /
Kojto	122:f9eeca106725	8439	#define TIM_CCMR2_IC3F_3 0x0080U /!<Bit 3 /
Kojto	122:f9eeca106725	8440
Kojto	122:f9eeca106725	8441	#define TIM_CCMR2_IC4PSC 0x0C00U /!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) /
Kojto	122:f9eeca106725	8442	#define TIM_CCMR2_IC4PSC_0 0x0400U /!<Bit 0 /
Kojto	122:f9eeca106725	8443	#define TIM_CCMR2_IC4PSC_1 0x0800U /!<Bit 1 /
Kojto	122:f9eeca106725	8444
Kojto	122:f9eeca106725	8445	#define TIM_CCMR2_IC4F 0xF000U /!<IC4F[3:0] bits (Input Capture 4 Filter) /
Kojto	122:f9eeca106725	8446	#define TIM_CCMR2_IC4F_0 0x1000U /!<Bit 0 /
Kojto	122:f9eeca106725	8447	#define TIM_CCMR2_IC4F_1 0x2000U /!<Bit 1 /
Kojto	122:f9eeca106725	8448	#define TIM_CCMR2_IC4F_2 0x4000U /!<Bit 2 /
Kojto	122:f9eeca106725	8449	#define TIM_CCMR2_IC4F_3 0x8000U /!<Bit 3 /
Kojto	110:165afa46840b	8450
Kojto	110:165afa46840b	8451	/***************** Bit definition for TIM_CCER register *****************/
Kojto	122:f9eeca106725	8452	#define TIM_CCER_CC1E 0x0001U /!<Capture/Compare 1 output enable /
Kojto	122:f9eeca106725	8453	#define TIM_CCER_CC1P 0x0002U /!<Capture/Compare 1 output Polarity /
Kojto	122:f9eeca106725	8454	#define TIM_CCER_CC1NE 0x0004U /!<Capture/Compare 1 Complementary output enable /
Kojto	122:f9eeca106725	8455	#define TIM_CCER_CC1NP 0x0008U /!<Capture/Compare 1 Complementary output Polarity /
Kojto	122:f9eeca106725	8456	#define TIM_CCER_CC2E 0x0010U /!<Capture/Compare 2 output enable /
Kojto	122:f9eeca106725	8457	#define TIM_CCER_CC2P 0x0020U /!<Capture/Compare 2 output Polarity /
Kojto	122:f9eeca106725	8458	#define TIM_CCER_CC2NE 0x0040U /!<Capture/Compare 2 Complementary output enable /
Kojto	122:f9eeca106725	8459	#define TIM_CCER_CC2NP 0x0080U /!<Capture/Compare 2 Complementary output Polarity /
Kojto	122:f9eeca106725	8460	#define TIM_CCER_CC3E 0x0100U /!<Capture/Compare 3 output enable /
Kojto	122:f9eeca106725	8461	#define TIM_CCER_CC3P 0x0200U /!<Capture/Compare 3 output Polarity /
Kojto	122:f9eeca106725	8462	#define TIM_CCER_CC3NE 0x0400U /!<Capture/Compare 3 Complementary output enable /
Kojto	122:f9eeca106725	8463	#define TIM_CCER_CC3NP 0x0800U /!<Capture/Compare 3 Complementary output Polarity /
Kojto	122:f9eeca106725	8464	#define TIM_CCER_CC4E 0x1000U /!<Capture/Compare 4 output enable /
Kojto	122:f9eeca106725	8465	#define TIM_CCER_CC4P 0x2000U /!<Capture/Compare 4 output Polarity /
Kojto	122:f9eeca106725	8466	#define TIM_CCER_CC4NP 0x8000U /!<Capture/Compare 4 Complementary output Polarity /
Kojto	110:165afa46840b	8467
Kojto	110:165afa46840b	8468	/***************** Bit definition for TIM_CNT register ******************/
Kojto	122:f9eeca106725	8469	#define TIM_CNT_CNT 0xFFFFU /!<Counter Value /
Kojto	110:165afa46840b	8470
Kojto	110:165afa46840b	8471	/***************** Bit definition for TIM_PSC register ******************/
Kojto	122:f9eeca106725	8472	#define TIM_PSC_PSC 0xFFFFU /!<Prescaler Value /
Kojto	110:165afa46840b	8473
Kojto	110:165afa46840b	8474	/***************** Bit definition for TIM_ARR register ******************/
Kojto	122:f9eeca106725	8475	#define TIM_ARR_ARR 0xFFFFU /!<actual auto-reload Value /
Kojto	110:165afa46840b	8476
Kojto	110:165afa46840b	8477	/***************** Bit definition for TIM_RCR register ******************/
Kojto	122:f9eeca106725	8478	#define TIM_RCR_REP 0xFFU /!<Repetition Counter Value /
Kojto	110:165afa46840b	8479
Kojto	110:165afa46840b	8480	/***************** Bit definition for TIM_CCR1 register *****************/
Kojto	122:f9eeca106725	8481	#define TIM_CCR1_CCR1 0xFFFFU /!<Capture/Compare 1 Value /
Kojto	110:165afa46840b	8482
Kojto	110:165afa46840b	8483	/***************** Bit definition for TIM_CCR2 register *****************/
Kojto	122:f9eeca106725	8484	#define TIM_CCR2_CCR2 0xFFFFU /!<Capture/Compare 2 Value /
Kojto	110:165afa46840b	8485
Kojto	110:165afa46840b	8486	/***************** Bit definition for TIM_CCR3 register *****************/
Kojto	122:f9eeca106725	8487	#define TIM_CCR3_CCR3 0xFFFFU /!<Capture/Compare 3 Value /
Kojto	110:165afa46840b	8488
Kojto	110:165afa46840b	8489	/***************** Bit definition for TIM_CCR4 register *****************/
Kojto	122:f9eeca106725	8490	#define TIM_CCR4_CCR4 0xFFFFU /!<Capture/Compare 4 Value /
Kojto	110:165afa46840b	8491
Kojto	110:165afa46840b	8492	/***************** Bit definition for TIM_BDTR register *****************/
Kojto	122:f9eeca106725	8493	#define TIM_BDTR_DTG 0x00FFU /!<DTG[0:7] bits (Dead-Time Generator set-up) /
Kojto	122:f9eeca106725	8494	#define TIM_BDTR_DTG_0 0x0001U /!<Bit 0 /
Kojto	122:f9eeca106725	8495	#define TIM_BDTR_DTG_1 0x0002U /!<Bit 1 /
Kojto	122:f9eeca106725	8496	#define TIM_BDTR_DTG_2 0x0004U /!<Bit 2 /
Kojto	122:f9eeca106725	8497	#define TIM_BDTR_DTG_3 0x0008U /!<Bit 3 /
Kojto	122:f9eeca106725	8498	#define TIM_BDTR_DTG_4 0x0010U /!<Bit 4 /
Kojto	122:f9eeca106725	8499	#define TIM_BDTR_DTG_5 0x0020U /!<Bit 5 /
Kojto	122:f9eeca106725	8500	#define TIM_BDTR_DTG_6 0x0040U /!<Bit 6 /
Kojto	122:f9eeca106725	8501	#define TIM_BDTR_DTG_7 0x0080U /!<Bit 7 /
Kojto	122:f9eeca106725	8502
Kojto	122:f9eeca106725	8503	#define TIM_BDTR_LOCK 0x0300U /!<LOCK[1:0] bits (Lock Configuration) /
Kojto	122:f9eeca106725	8504	#define TIM_BDTR_LOCK_0 0x0100U /!<Bit 0 /
Kojto	122:f9eeca106725	8505	#define TIM_BDTR_LOCK_1 0x0200U /!<Bit 1 /
Kojto	122:f9eeca106725	8506
Kojto	122:f9eeca106725	8507	#define TIM_BDTR_OSSI 0x0400U /!<Off-State Selection for Idle mode /
Kojto	122:f9eeca106725	8508	#define TIM_BDTR_OSSR 0x0800U /!<Off-State Selection for Run mode /
Kojto	122:f9eeca106725	8509	#define TIM_BDTR_BKE 0x1000U /!<Break enable /
Kojto	122:f9eeca106725	8510	#define TIM_BDTR_BKP 0x2000U /!<Break Polarity /
Kojto	122:f9eeca106725	8511	#define TIM_BDTR_AOE 0x4000U /!<Automatic Output enable /
Kojto	122:f9eeca106725	8512	#define TIM_BDTR_MOE 0x8000U /!<Main Output enable /
Kojto	110:165afa46840b	8513
Kojto	110:165afa46840b	8514	/***************** Bit definition for TIM_DCR register ******************/
Kojto	122:f9eeca106725	8515	#define TIM_DCR_DBA 0x001FU /!<DBA[4:0] bits (DMA Base Address) /
Kojto	122:f9eeca106725	8516	#define TIM_DCR_DBA_0 0x0001U /!<Bit 0 /
Kojto	122:f9eeca106725	8517	#define TIM_DCR_DBA_1 0x0002U /!<Bit 1 /
Kojto	122:f9eeca106725	8518	#define TIM_DCR_DBA_2 0x0004U /!<Bit 2 /
Kojto	122:f9eeca106725	8519	#define TIM_DCR_DBA_3 0x0008U /!<Bit 3 /
Kojto	122:f9eeca106725	8520	#define TIM_DCR_DBA_4 0x0010U /!<Bit 4 /
Kojto	122:f9eeca106725	8521
Kojto	122:f9eeca106725	8522	#define TIM_DCR_DBL 0x1F00U /!<DBL[4:0] bits (DMA Burst Length) /
Kojto	122:f9eeca106725	8523	#define TIM_DCR_DBL_0 0x0100U /!<Bit 0 /
Kojto	122:f9eeca106725	8524	#define TIM_DCR_DBL_1 0x0200U /!<Bit 1 /
Kojto	122:f9eeca106725	8525	#define TIM_DCR_DBL_2 0x0400U /!<Bit 2 /
Kojto	122:f9eeca106725	8526	#define TIM_DCR_DBL_3 0x0800U /!<Bit 3 /
Kojto	122:f9eeca106725	8527	#define TIM_DCR_DBL_4 0x1000U /!<Bit 4 /
Kojto	110:165afa46840b	8528
Kojto	110:165afa46840b	8529	/***************** Bit definition for TIM_DMAR register *****************/
Kojto	122:f9eeca106725	8530	#define TIM_DMAR_DMAB 0xFFFFU /!<DMA register for burst accesses /
Kojto	110:165afa46840b	8531
Kojto	110:165afa46840b	8532	/***************** Bit definition for TIM_OR register *******************/
Kojto	122:f9eeca106725	8533	#define TIM_OR_TI4_RMP 0x00C0U /!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) /
Kojto	122:f9eeca106725	8534	#define TIM_OR_TI4_RMP_0 0x0040U /!<Bit 0 /
Kojto	122:f9eeca106725	8535	#define TIM_OR_TI4_RMP_1 0x0080U /!<Bit 1 /
Kojto	122:f9eeca106725	8536	#define TIM_OR_ITR1_RMP 0x0C00U /!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) /
Kojto	122:f9eeca106725	8537	#define TIM_OR_ITR1_RMP_0 0x0400U /!<Bit 0 /
Kojto	122:f9eeca106725	8538	#define TIM_OR_ITR1_RMP_1 0x0800U /!<Bit 1 /
Kojto	110:165afa46840b	8539
Kojto	110:165afa46840b	8540
Kojto	110:165afa46840b	8541	/******************************************************************************/
Kojto	110:165afa46840b	8542	/* */
Kojto	110:165afa46840b	8543	/* Universal Synchronous Asynchronous Receiver Transmitter */
Kojto	110:165afa46840b	8544	/* */
Kojto	110:165afa46840b	8545	/******************************************************************************/
Kojto	110:165afa46840b	8546	/***************** Bit definition for USART_SR register *****************/
Kojto	122:f9eeca106725	8547	#define USART_SR_PE 0x0001U /!<Parity Error /
Kojto	122:f9eeca106725	8548	#define USART_SR_FE 0x0002U /!<Framing Error /
Kojto	122:f9eeca106725	8549	#define USART_SR_NE 0x0004U /!<Noise Error Flag /
Kojto	122:f9eeca106725	8550	#define USART_SR_ORE 0x0008U /!<OverRun Error /
Kojto	122:f9eeca106725	8551	#define USART_SR_IDLE 0x0010U /!<IDLE line detected /
Kojto	122:f9eeca106725	8552	#define USART_SR_RXNE 0x0020U /!<Read Data Register Not Empty /
Kojto	122:f9eeca106725	8553	#define USART_SR_TC 0x0040U /!<Transmission Complete /
Kojto	122:f9eeca106725	8554	#define USART_SR_TXE 0x0080U /!<Transmit Data Register Empty /
Kojto	122:f9eeca106725	8555	#define USART_SR_LBD 0x0100U /!<LIN Break Detection Flag /
Kojto	122:f9eeca106725	8556	#define USART_SR_CTS 0x0200U /!<CTS Flag /
Kojto	110:165afa46840b	8557
Kojto	110:165afa46840b	8558	/***************** Bit definition for USART_DR register *****************/
Kojto	122:f9eeca106725	8559	#define USART_DR_DR 0x01FFU /!<Data value /
Kojto	110:165afa46840b	8560
Kojto	110:165afa46840b	8561	/**************** Bit definition for USART_BRR register *****************/
Kojto	122:f9eeca106725	8562	#define USART_BRR_DIV_Fraction 0x000FU /!<Fraction of USARTDIV /
Kojto	122:f9eeca106725	8563	#define USART_BRR_DIV_Mantissa 0xFFF0U /!<Mantissa of USARTDIV /
Kojto	110:165afa46840b	8564
Kojto	110:165afa46840b	8565	/**************** Bit definition for USART_CR1 register *****************/
Kojto	122:f9eeca106725	8566	#define USART_CR1_SBK 0x0001U /!<Send Break /
Kojto	122:f9eeca106725	8567	#define USART_CR1_RWU 0x0002U /!<Receiver wakeup /
Kojto	122:f9eeca106725	8568	#define USART_CR1_RE 0x0004U /!<Receiver Enable /
Kojto	122:f9eeca106725	8569	#define USART_CR1_TE 0x0008U /!<Transmitter Enable /
Kojto	122:f9eeca106725	8570	#define USART_CR1_IDLEIE 0x0010U /!<IDLE Interrupt Enable /
Kojto	122:f9eeca106725	8571	#define USART_CR1_RXNEIE 0x0020U /!<RXNE Interrupt Enable /
Kojto	122:f9eeca106725	8572	#define USART_CR1_TCIE 0x0040U /!<Transmission Complete Interrupt Enable /
Kojto	122:f9eeca106725	8573	#define USART_CR1_TXEIE 0x0080U /!<PE Interrupt Enable /
Kojto	122:f9eeca106725	8574	#define USART_CR1_PEIE 0x0100U /!<PE Interrupt Enable /
Kojto	122:f9eeca106725	8575	#define USART_CR1_PS 0x0200U /!<Parity Selection /
Kojto	122:f9eeca106725	8576	#define USART_CR1_PCE 0x0400U /!<Parity Control Enable /
Kojto	122:f9eeca106725	8577	#define USART_CR1_WAKE 0x0800U /!<Wakeup method /
Kojto	122:f9eeca106725	8578	#define USART_CR1_M 0x1000U /!<Word length /
Kojto	122:f9eeca106725	8579	#define USART_CR1_UE 0x2000U /!<USART Enable /
Kojto	122:f9eeca106725	8580	#define USART_CR1_OVER8 0x8000U /!<USART Oversampling by 8 enable /
Kojto	110:165afa46840b	8581
Kojto	110:165afa46840b	8582	/**************** Bit definition for USART_CR2 register *****************/
Kojto	122:f9eeca106725	8583	#define USART_CR2_ADD 0x000FU /!<Address of the USART node /
Kojto	122:f9eeca106725	8584	#define USART_CR2_LBDL 0x0020U /!<LIN Break Detection Length /
Kojto	122:f9eeca106725	8585	#define USART_CR2_LBDIE 0x0040U /!<LIN Break Detection Interrupt Enable /
Kojto	122:f9eeca106725	8586	#define USART_CR2_LBCL 0x0100U /!<Last Bit Clock pulse /
Kojto	122:f9eeca106725	8587	#define USART_CR2_CPHA 0x0200U /!<Clock Phase /
Kojto	122:f9eeca106725	8588	#define USART_CR2_CPOL 0x0400U /!<Clock Polarity /
Kojto	122:f9eeca106725	8589	#define USART_CR2_CLKEN 0x0800U /!<Clock Enable /
Kojto	122:f9eeca106725	8590
Kojto	122:f9eeca106725	8591	#define USART_CR2_STOP 0x3000U /!<STOP[1:0] bits (STOP bits) /
Kojto	122:f9eeca106725	8592	#define USART_CR2_STOP_0 0x1000U /!<Bit 0 /
Kojto	122:f9eeca106725	8593	#define USART_CR2_STOP_1 0x2000U /!<Bit 1 /
Kojto	122:f9eeca106725	8594
Kojto	122:f9eeca106725	8595	#define USART_CR2_LINEN 0x4000U /!<LIN mode enable /
Kojto	110:165afa46840b	8596
Kojto	110:165afa46840b	8597	/**************** Bit definition for USART_CR3 register *****************/
Kojto	122:f9eeca106725	8598	#define USART_CR3_EIE 0x0001U /!<Error Interrupt Enable /
Kojto	122:f9eeca106725	8599	#define USART_CR3_IREN 0x0002U /!<IrDA mode Enable /
Kojto	122:f9eeca106725	8600	#define USART_CR3_IRLP 0x0004U /!<IrDA Low-Power /
Kojto	122:f9eeca106725	8601	#define USART_CR3_HDSEL 0x0008U /!<Half-Duplex Selection /
Kojto	122:f9eeca106725	8602	#define USART_CR3_NACK 0x0010U /!<Smartcard NACK enable /
Kojto	122:f9eeca106725	8603	#define USART_CR3_SCEN 0x0020U /!<Smartcard mode enable /
Kojto	122:f9eeca106725	8604	#define USART_CR3_DMAR 0x0040U /!<DMA Enable Receiver /
Kojto	122:f9eeca106725	8605	#define USART_CR3_DMAT 0x0080U /!<DMA Enable Transmitter /
Kojto	122:f9eeca106725	8606	#define USART_CR3_RTSE 0x0100U /!<RTS Enable /
Kojto	122:f9eeca106725	8607	#define USART_CR3_CTSE 0x0200U /!<CTS Enable /
Kojto	122:f9eeca106725	8608	#define USART_CR3_CTSIE 0x0400U /!<CTS Interrupt Enable /
Kojto	122:f9eeca106725	8609	#define USART_CR3_ONEBIT 0x0800U /!<USART One bit method enable /
Kojto	110:165afa46840b	8610
Kojto	110:165afa46840b	8611	/**************** Bit definition for USART_GTPR register ****************/
Kojto	122:f9eeca106725	8612	#define USART_GTPR_PSC 0x00FFU /!<PSC[7:0] bits (Prescaler value) /
Kojto	122:f9eeca106725	8613	#define USART_GTPR_PSC_0 0x0001U /!<Bit 0 /
Kojto	122:f9eeca106725	8614	#define USART_GTPR_PSC_1 0x0002U /!<Bit 1 /
Kojto	122:f9eeca106725	8615	#define USART_GTPR_PSC_2 0x0004U /!<Bit 2 /
Kojto	122:f9eeca106725	8616	#define USART_GTPR_PSC_3 0x0008U /!<Bit 3 /
Kojto	122:f9eeca106725	8617	#define USART_GTPR_PSC_4 0x0010U /!<Bit 4 /
Kojto	122:f9eeca106725	8618	#define USART_GTPR_PSC_5 0x0020U /!<Bit 5 /
Kojto	122:f9eeca106725	8619	#define USART_GTPR_PSC_6 0x0040U /!<Bit 6 /
Kojto	122:f9eeca106725	8620	#define USART_GTPR_PSC_7 0x0080U /!<Bit 7 /
Kojto	122:f9eeca106725	8621
Kojto	122:f9eeca106725	8622	#define USART_GTPR_GT 0xFF00U /!<Guard time value /
Kojto	110:165afa46840b	8623
Kojto	110:165afa46840b	8624	/******************************************************************************/
Kojto	110:165afa46840b	8625	/* */
Kojto	110:165afa46840b	8626	/* Window WATCHDOG */
Kojto	110:165afa46840b	8627	/* */
Kojto	110:165afa46840b	8628	/******************************************************************************/
Kojto	110:165afa46840b	8629	/***************** Bit definition for WWDG_CR register ******************/
Kojto	122:f9eeca106725	8630	#define WWDG_CR_T 0x7FU /!<T[6:0] bits (7-Bit counter (MSB to LSB)) /
Kojto	122:f9eeca106725	8631	#define WWDG_CR_T_0 0x01U /!<Bit 0 /
Kojto	122:f9eeca106725	8632	#define WWDG_CR_T_1 0x02U /!<Bit 1 /
Kojto	122:f9eeca106725	8633	#define WWDG_CR_T_2 0x04U /!<Bit 2 /
Kojto	122:f9eeca106725	8634	#define WWDG_CR_T_3 0x08U /!<Bit 3 /
Kojto	122:f9eeca106725	8635	#define WWDG_CR_T_4 0x10U /!<Bit 4 /
Kojto	122:f9eeca106725	8636	#define WWDG_CR_T_5 0x20U /!<Bit 5 /
Kojto	122:f9eeca106725	8637	#define WWDG_CR_T_6 0x40U /!<Bit 6 /
Kojto	122:f9eeca106725	8638	/* Legacy defines */
Kojto	122:f9eeca106725	8639	#define WWDG_CR_T0 WWDG_CR_T_0
Kojto	122:f9eeca106725	8640	#define WWDG_CR_T1 WWDG_CR_T_1
Kojto	122:f9eeca106725	8641	#define WWDG_CR_T2 WWDG_CR_T_2
Kojto	122:f9eeca106725	8642	#define WWDG_CR_T3 WWDG_CR_T_3
Kojto	122:f9eeca106725	8643	#define WWDG_CR_T4 WWDG_CR_T_4
Kojto	122:f9eeca106725	8644	#define WWDG_CR_T5 WWDG_CR_T_5
Kojto	122:f9eeca106725	8645	#define WWDG_CR_T6 WWDG_CR_T_6
Kojto	122:f9eeca106725	8646
Kojto	122:f9eeca106725	8647	#define WWDG_CR_WDGA 0x80U /!<Activation bit /
Kojto	110:165afa46840b	8648
Kojto	110:165afa46840b	8649	/***************** Bit definition for WWDG_CFR register *****************/
Kojto	122:f9eeca106725	8650	#define WWDG_CFR_W 0x007FU /!<W[6:0] bits (7-bit window value) /
Kojto	122:f9eeca106725	8651	#define WWDG_CFR_W_0 0x0001U /!<Bit 0 /
Kojto	122:f9eeca106725	8652	#define WWDG_CFR_W_1 0x0002U /!<Bit 1 /
Kojto	122:f9eeca106725	8653	#define WWDG_CFR_W_2 0x0004U /!<Bit 2 /
Kojto	122:f9eeca106725	8654	#define WWDG_CFR_W_3 0x0008U /!<Bit 3 /
Kojto	122:f9eeca106725	8655	#define WWDG_CFR_W_4 0x0010U /!<Bit 4 /
Kojto	122:f9eeca106725	8656	#define WWDG_CFR_W_5 0x0020U /!<Bit 5 /
Kojto	122:f9eeca106725	8657	#define WWDG_CFR_W_6 0x0040U /!<Bit 6 /
Kojto	122:f9eeca106725	8658	/* Legacy defines */
Kojto	122:f9eeca106725	8659	#define WWDG_CFR_W0 WWDG_CFR_W_0
Kojto	122:f9eeca106725	8660	#define WWDG_CFR_W1 WWDG_CFR_W_1
Kojto	122:f9eeca106725	8661	#define WWDG_CFR_W2 WWDG_CFR_W_2
Kojto	122:f9eeca106725	8662	#define WWDG_CFR_W3 WWDG_CFR_W_3
Kojto	122:f9eeca106725	8663	#define WWDG_CFR_W4 WWDG_CFR_W_4
Kojto	122:f9eeca106725	8664	#define WWDG_CFR_W5 WWDG_CFR_W_5
Kojto	122:f9eeca106725	8665	#define WWDG_CFR_W6 WWDG_CFR_W_6
Kojto	122:f9eeca106725	8666
Kojto	122:f9eeca106725	8667	#define WWDG_CFR_WDGTB 0x0180U /!<WDGTB[1:0] bits (Timer Base) /
Kojto	122:f9eeca106725	8668	#define WWDG_CFR_WDGTB_0 0x0080U /!<Bit 0 /
Kojto	122:f9eeca106725	8669	#define WWDG_CFR_WDGTB_1 0x0100U /!<Bit 1 /
Kojto	122:f9eeca106725	8670	/* Legacy defines */
Kojto	122:f9eeca106725	8671	#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
Kojto	122:f9eeca106725	8672	#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
Kojto	122:f9eeca106725	8673
Kojto	122:f9eeca106725	8674	#define WWDG_CFR_EWI 0x0200U /!<Early Wakeup Interrupt /
Kojto	110:165afa46840b	8675
Kojto	110:165afa46840b	8676	/***************** Bit definition for WWDG_SR register ******************/
Kojto	122:f9eeca106725	8677	#define WWDG_SR_EWIF 0x01U /!<Early Wakeup Interrupt Flag /
Kojto	110:165afa46840b	8678
Kojto	110:165afa46840b	8679
Kojto	110:165afa46840b	8680	/******************************************************************************/
Kojto	110:165afa46840b	8681	/* */
Kojto	110:165afa46840b	8682	/* DBG */
Kojto	110:165afa46840b	8683	/* */
Kojto	110:165afa46840b	8684	/******************************************************************************/
Kojto	110:165afa46840b	8685	/****************** Bit definition for DBGMCU_IDCODE register ***********/
Kojto	122:f9eeca106725	8686	#define DBGMCU_IDCODE_DEV_ID 0x00000FFFU
Kojto	122:f9eeca106725	8687	#define DBGMCU_IDCODE_REV_ID 0xFFFF0000U
Kojto	110:165afa46840b	8688
Kojto	110:165afa46840b	8689	/****************** Bit definition for DBGMCU_CR register ***************/
Kojto	122:f9eeca106725	8690	#define DBGMCU_CR_DBG_SLEEP 0x00000001U
Kojto	122:f9eeca106725	8691	#define DBGMCU_CR_DBG_STOP 0x00000002U
Kojto	122:f9eeca106725	8692	#define DBGMCU_CR_DBG_STANDBY 0x00000004U
Kojto	122:f9eeca106725	8693	#define DBGMCU_CR_TRACE_IOEN 0x00000020U
Kojto	122:f9eeca106725	8694
Kojto	122:f9eeca106725	8695	#define DBGMCU_CR_TRACE_MODE 0x000000C0U
Kojto	122:f9eeca106725	8696	#define DBGMCU_CR_TRACE_MODE_0 0x00000040U/!<Bit 0 /
Kojto	122:f9eeca106725	8697	#define DBGMCU_CR_TRACE_MODE_1 0x00000080U/!<Bit 1 /
Kojto	110:165afa46840b	8698
Kojto	110:165afa46840b	8699	/****************** Bit definition for DBGMCU_APB1_FZ register **********/
Kojto	122:f9eeca106725	8700	#define DBGMCU_APB1_FZ_DBG_TIM2_STOP 0x00000001U
Kojto	122:f9eeca106725	8701	#define DBGMCU_APB1_FZ_DBG_TIM3_STOP 0x00000002U
Kojto	122:f9eeca106725	8702	#define DBGMCU_APB1_FZ_DBG_TIM4_STOP 0x00000004U
Kojto	122:f9eeca106725	8703	#define DBGMCU_APB1_FZ_DBG_TIM5_STOP 0x00000008U
Kojto	122:f9eeca106725	8704	#define DBGMCU_APB1_FZ_DBG_TIM6_STOP 0x00000010U
Kojto	122:f9eeca106725	8705	#define DBGMCU_APB1_FZ_DBG_TIM7_STOP 0x00000020U
Kojto	122:f9eeca106725	8706	#define DBGMCU_APB1_FZ_DBG_TIM12_STOP 0x00000040U
Kojto	122:f9eeca106725	8707	#define DBGMCU_APB1_FZ_DBG_TIM13_STOP 0x00000080U
Kojto	122:f9eeca106725	8708	#define DBGMCU_APB1_FZ_DBG_TIM14_STOP 0x00000100U
Kojto	122:f9eeca106725	8709	#define DBGMCU_APB1_FZ_DBG_RTC_STOP 0x00000400U
Kojto	122:f9eeca106725	8710	#define DBGMCU_APB1_FZ_DBG_WWDG_STOP 0x00000800U
Kojto	122:f9eeca106725	8711	#define DBGMCU_APB1_FZ_DBG_IWDG_STOP 0x00001000U
Kojto	122:f9eeca106725	8712	#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT 0x00200000U
Kojto	122:f9eeca106725	8713	#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT 0x00400000U
Kojto	122:f9eeca106725	8714	#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT 0x00800000U
Kojto	122:f9eeca106725	8715	#define DBGMCU_APB1_FZ_DBG_CAN1_STOP 0x02000000U
Kojto	122:f9eeca106725	8716	#define DBGMCU_APB1_FZ_DBG_CAN2_STOP 0x04000000U
Kojto	110:165afa46840b	8717	/* Old IWDGSTOP bit definition, maintained for legacy purpose */
Kojto	110:165afa46840b	8718	#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
Kojto	110:165afa46840b	8719
Kojto	110:165afa46840b	8720	/****************** Bit definition for DBGMCU_APB2_FZ register **********/
Kojto	122:f9eeca106725	8721	#define DBGMCU_APB2_FZ_DBG_TIM1_STOP 0x00000001U
Kojto	122:f9eeca106725	8722	#define DBGMCU_APB2_FZ_DBG_TIM8_STOP 0x00000002U
Kojto	122:f9eeca106725	8723	#define DBGMCU_APB2_FZ_DBG_TIM9_STOP 0x00010000U
Kojto	122:f9eeca106725	8724	#define DBGMCU_APB2_FZ_DBG_TIM10_STOP 0x00020000U
Kojto	122:f9eeca106725	8725	#define DBGMCU_APB2_FZ_DBG_TIM11_STOP 0x00040000U
Kojto	110:165afa46840b	8726
Kojto	110:165afa46840b	8727	/******************************************************************************/
Kojto	110:165afa46840b	8728	/* */
Kojto	110:165afa46840b	8729	/* Ethernet MAC Registers bits definitions */
Kojto	110:165afa46840b	8730	/* */
Kojto	110:165afa46840b	8731	/******************************************************************************/
Kojto	110:165afa46840b	8732	/* Bit definition for Ethernet MAC Control Register register */
Kojto	122:f9eeca106725	8733	#define ETH_MACCR_WD 0x00800000U /* Watchdog disable */
Kojto	122:f9eeca106725	8734	#define ETH_MACCR_JD 0x00400000U /* Jabber disable */
Kojto	122:f9eeca106725	8735	#define ETH_MACCR_IFG 0x000E0000U /* Inter-frame gap */
Kojto	122:f9eeca106725	8736	#define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */
Kojto	122:f9eeca106725	8737	#define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */
Kojto	122:f9eeca106725	8738	#define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */
Kojto	122:f9eeca106725	8739	#define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */
Kojto	122:f9eeca106725	8740	#define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */
Kojto	122:f9eeca106725	8741	#define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */
Kojto	122:f9eeca106725	8742	#define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */
Kojto	122:f9eeca106725	8743	#define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */
Kojto	122:f9eeca106725	8744	#define ETH_MACCR_CSD 0x00010000U /* Carrier sense disable (during transmission) */
Kojto	122:f9eeca106725	8745	#define ETH_MACCR_FES 0x00004000U /* Fast ethernet speed */
Kojto	122:f9eeca106725	8746	#define ETH_MACCR_ROD 0x00002000U /* Receive own disable */
Kojto	122:f9eeca106725	8747	#define ETH_MACCR_LM 0x00001000U /* loopback mode */
Kojto	122:f9eeca106725	8748	#define ETH_MACCR_DM 0x00000800U /* Duplex mode */
Kojto	122:f9eeca106725	8749	#define ETH_MACCR_IPCO 0x00000400U /* IP Checksum offload */
Kojto	122:f9eeca106725	8750	#define ETH_MACCR_RD 0x00000200U /* Retry disable */
Kojto	122:f9eeca106725	8751	#define ETH_MACCR_APCS 0x00000080U /* Automatic Pad/CRC stripping */
Kojto	122:f9eeca106725	8752	#define ETH_MACCR_BL 0x00000060U /* Back-off limit: random integer number (r) of slot time delays before rescheduling
Kojto	110:165afa46840b	8753	a transmission attempt during retries after a collision: 0 =< r <2^k */
Kojto	122:f9eeca106725	8754	#define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */
Kojto	122:f9eeca106725	8755	#define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */
Kojto	122:f9eeca106725	8756	#define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */
Kojto	122:f9eeca106725	8757	#define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */
Kojto	122:f9eeca106725	8758	#define ETH_MACCR_DC 0x00000010U /* Defferal check */
Kojto	122:f9eeca106725	8759	#define ETH_MACCR_TE 0x00000008U /* Transmitter enable */
Kojto	122:f9eeca106725	8760	#define ETH_MACCR_RE 0x00000004U /* Receiver enable */
Kojto	110:165afa46840b	8761
Kojto	110:165afa46840b	8762	/* Bit definition for Ethernet MAC Frame Filter Register */
Kojto	122:f9eeca106725	8763	#define ETH_MACFFR_RA 0x80000000U /* Receive all */
Kojto	122:f9eeca106725	8764	#define ETH_MACFFR_HPF 0x00000400U /* Hash or perfect filter */
Kojto	122:f9eeca106725	8765	#define ETH_MACFFR_SAF 0x00000200U /* Source address filter enable */
Kojto	122:f9eeca106725	8766	#define ETH_MACFFR_SAIF 0x00000100U /* SA inverse filtering */
Kojto	122:f9eeca106725	8767	#define ETH_MACFFR_PCF 0x000000C0U /* Pass control frames: 3 cases */
Kojto	122:f9eeca106725	8768	#define ETH_MACFFR_PCF_BlockAll 0x00000040U /* MAC filters all control frames from reaching the application */
Kojto	122:f9eeca106725	8769	#define ETH_MACFFR_PCF_ForwardAll 0x00000080U /* MAC forwards all control frames to application even if they fail the Address Filter */
Kojto	122:f9eeca106725	8770	#define ETH_MACFFR_PCF_ForwardPassedAddrFilter 0x000000C0U /* MAC forwards control frames that pass the Address Filter. */
Kojto	122:f9eeca106725	8771	#define ETH_MACFFR_BFD 0x00000020U /* Broadcast frame disable */
Kojto	122:f9eeca106725	8772	#define ETH_MACFFR_PAM 0x00000010U /* Pass all mutlicast */
Kojto	122:f9eeca106725	8773	#define ETH_MACFFR_DAIF 0x00000008U /* DA Inverse filtering */
Kojto	122:f9eeca106725	8774	#define ETH_MACFFR_HM 0x00000004U /* Hash multicast */
Kojto	122:f9eeca106725	8775	#define ETH_MACFFR_HU 0x00000002U /* Hash unicast */
Kojto	122:f9eeca106725	8776	#define ETH_MACFFR_PM 0x00000001U /* Promiscuous mode */
Kojto	110:165afa46840b	8777
Kojto	110:165afa46840b	8778	/* Bit definition for Ethernet MAC Hash Table High Register */
Kojto	122:f9eeca106725	8779	#define ETH_MACHTHR_HTH 0xFFFFFFFFU /* Hash table high */
Kojto	110:165afa46840b	8780
Kojto	110:165afa46840b	8781	/* Bit definition for Ethernet MAC Hash Table Low Register */
Kojto	122:f9eeca106725	8782	#define ETH_MACHTLR_HTL 0xFFFFFFFFU /* Hash table low */
Kojto	110:165afa46840b	8783
Kojto	110:165afa46840b	8784	/* Bit definition for Ethernet MAC MII Address Register */
Kojto	122:f9eeca106725	8785	#define ETH_MACMIIAR_PA 0x0000F800U /* Physical layer address */
Kojto	122:f9eeca106725	8786	#define ETH_MACMIIAR_MR 0x000007C0U /* MII register in the selected PHY */
Kojto	122:f9eeca106725	8787	#define ETH_MACMIIAR_CR 0x0000001CU /* CR clock range: 6 cases */
Kojto	122:f9eeca106725	8788	#define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
Kojto	122:f9eeca106725	8789	#define ETH_MACMIIAR_CR_Div62 0x00000004U /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
Kojto	122:f9eeca106725	8790	#define ETH_MACMIIAR_CR_Div16 0x00000008U /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
Kojto	122:f9eeca106725	8791	#define ETH_MACMIIAR_CR_Div26 0x0000000CU /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
Kojto	122:f9eeca106725	8792	#define ETH_MACMIIAR_CR_Div102 0x00000010U /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
Kojto	122:f9eeca106725	8793	#define ETH_MACMIIAR_MW 0x00000002U /* MII write */
Kojto	122:f9eeca106725	8794	#define ETH_MACMIIAR_MB 0x00000001U /* MII busy */
Kojto	110:165afa46840b	8795
Kojto	110:165afa46840b	8796	/* Bit definition for Ethernet MAC MII Data Register */
Kojto	122:f9eeca106725	8797	#define ETH_MACMIIDR_MD 0x0000FFFFU /* MII data: read/write data from/to PHY */
Kojto	110:165afa46840b	8798
Kojto	110:165afa46840b	8799	/* Bit definition for Ethernet MAC Flow Control Register */
Kojto	122:f9eeca106725	8800	#define ETH_MACFCR_PT 0xFFFF0000U /* Pause time */
Kojto	122:f9eeca106725	8801	#define ETH_MACFCR_ZQPD 0x00000080U /* Zero-quanta pause disable */
Kojto	122:f9eeca106725	8802	#define ETH_MACFCR_PLT 0x00000030U /* Pause low threshold: 4 cases */
Kojto	122:f9eeca106725	8803	#define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */
Kojto	122:f9eeca106725	8804	#define ETH_MACFCR_PLT_Minus28 0x00000010U /* Pause time minus 28 slot times */
Kojto	122:f9eeca106725	8805	#define ETH_MACFCR_PLT_Minus144 0x00000020U /* Pause time minus 144 slot times */
Kojto	122:f9eeca106725	8806	#define ETH_MACFCR_PLT_Minus256 0x00000030U /* Pause time minus 256 slot times */
Kojto	122:f9eeca106725	8807	#define ETH_MACFCR_UPFD 0x00000008U /* Unicast pause frame detect */
Kojto	122:f9eeca106725	8808	#define ETH_MACFCR_RFCE 0x00000004U /* Receive flow control enable */
Kojto	122:f9eeca106725	8809	#define ETH_MACFCR_TFCE 0x00000002U /* Transmit flow control enable */
Kojto	122:f9eeca106725	8810	#define ETH_MACFCR_FCBBPA 0x00000001U /* Flow control busy/backpressure activate */
Kojto	110:165afa46840b	8811
Kojto	110:165afa46840b	8812	/* Bit definition for Ethernet MAC VLAN Tag Register */
Kojto	122:f9eeca106725	8813	#define ETH_MACVLANTR_VLANTC 0x00010000U /* 12-bit VLAN tag comparison */
Kojto	122:f9eeca106725	8814	#define ETH_MACVLANTR_VLANTI 0x0000FFFFU /* VLAN tag identifier (for receive frames) */
Kojto	110:165afa46840b	8815
Kojto	110:165afa46840b	8816	/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
Kojto	122:f9eeca106725	8817	#define ETH_MACRWUFFR_D 0xFFFFFFFFU /* Wake-up frame filter register data */
Kojto	110:165afa46840b	8818	/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
Kojto	110:165afa46840b	8819	Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
Kojto	110:165afa46840b	8820	/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
Kojto	110:165afa46840b	8821	Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
Kojto	110:165afa46840b	8822	Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
Kojto	110:165afa46840b	8823	Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
Kojto	110:165afa46840b	8824	Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
Kojto	110:165afa46840b	8825	RSVD - Filter1 Command - RSVD - Filter0 Command
Kojto	110:165afa46840b	8826	Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
Kojto	110:165afa46840b	8827	Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
Kojto	110:165afa46840b	8828	Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
Kojto	110:165afa46840b	8829
Kojto	110:165afa46840b	8830	/* Bit definition for Ethernet MAC PMT Control and Status Register */
Kojto	122:f9eeca106725	8831	#define ETH_MACPMTCSR_WFFRPR 0x80000000U /* Wake-Up Frame Filter Register Pointer Reset */
Kojto	122:f9eeca106725	8832	#define ETH_MACPMTCSR_GU 0x00000200U /* Global Unicast */
Kojto	122:f9eeca106725	8833	#define ETH_MACPMTCSR_WFR 0x00000040U /* Wake-Up Frame Received */
Kojto	122:f9eeca106725	8834	#define ETH_MACPMTCSR_MPR 0x00000020U /* Magic Packet Received */
Kojto	122:f9eeca106725	8835	#define ETH_MACPMTCSR_WFE 0x00000004U /* Wake-Up Frame Enable */
Kojto	122:f9eeca106725	8836	#define ETH_MACPMTCSR_MPE 0x00000002U /* Magic Packet Enable */
Kojto	122:f9eeca106725	8837	#define ETH_MACPMTCSR_PD 0x00000001U /* Power Down */
Kojto	110:165afa46840b	8838
Kojto	110:165afa46840b	8839	/* Bit definition for Ethernet MAC Status Register */
Kojto	122:f9eeca106725	8840	#define ETH_MACSR_TSTS 0x00000200U /* Time stamp trigger status */
Kojto	122:f9eeca106725	8841	#define ETH_MACSR_MMCTS 0x00000040U /* MMC transmit status */
Kojto	122:f9eeca106725	8842	#define ETH_MACSR_MMMCRS 0x00000020U /* MMC receive status */
Kojto	122:f9eeca106725	8843	#define ETH_MACSR_MMCS 0x00000010U /* MMC status */
Kojto	122:f9eeca106725	8844	#define ETH_MACSR_PMTS 0x00000008U /* PMT status */
Kojto	110:165afa46840b	8845
Kojto	110:165afa46840b	8846	/* Bit definition for Ethernet MAC Interrupt Mask Register */
Kojto	122:f9eeca106725	8847	#define ETH_MACIMR_TSTIM 0x00000200U /* Time stamp trigger interrupt mask */
Kojto	122:f9eeca106725	8848	#define ETH_MACIMR_PMTIM 0x00000008U /* PMT interrupt mask */
Kojto	110:165afa46840b	8849
Kojto	110:165afa46840b	8850	/* Bit definition for Ethernet MAC Address0 High Register */
Kojto	122:f9eeca106725	8851	#define ETH_MACA0HR_MACA0H 0x0000FFFFU /* MAC address0 high */
Kojto	110:165afa46840b	8852
Kojto	110:165afa46840b	8853	/* Bit definition for Ethernet MAC Address0 Low Register */
Kojto	122:f9eeca106725	8854	#define ETH_MACA0LR_MACA0L 0xFFFFFFFFU /* MAC address0 low */
Kojto	110:165afa46840b	8855
Kojto	110:165afa46840b	8856	/* Bit definition for Ethernet MAC Address1 High Register */
Kojto	122:f9eeca106725	8857	#define ETH_MACA1HR_AE 0x80000000U /* Address enable */
Kojto	122:f9eeca106725	8858	#define ETH_MACA1HR_SA 0x40000000U /* Source address */
Kojto	122:f9eeca106725	8859	#define ETH_MACA1HR_MBC 0x3F000000U /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
Kojto	122:f9eeca106725	8860	#define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
Kojto	122:f9eeca106725	8861	#define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
Kojto	122:f9eeca106725	8862	#define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
Kojto	122:f9eeca106725	8863	#define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
Kojto	122:f9eeca106725	8864	#define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
Kojto	122:f9eeca106725	8865	#define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */
Kojto	122:f9eeca106725	8866	#define ETH_MACA1HR_MACA1H 0x0000FFFFU /* MAC address1 high */
Kojto	110:165afa46840b	8867
Kojto	110:165afa46840b	8868	/* Bit definition for Ethernet MAC Address1 Low Register */
Kojto	122:f9eeca106725	8869	#define ETH_MACA1LR_MACA1L 0xFFFFFFFFU /* MAC address1 low */
Kojto	110:165afa46840b	8870
Kojto	110:165afa46840b	8871	/* Bit definition for Ethernet MAC Address2 High Register */
Kojto	122:f9eeca106725	8872	#define ETH_MACA2HR_AE 0x80000000U /* Address enable */
Kojto	122:f9eeca106725	8873	#define ETH_MACA2HR_SA 0x40000000U /* Source address */
Kojto	122:f9eeca106725	8874	#define ETH_MACA2HR_MBC 0x3F000000U /* Mask byte control */
Kojto	122:f9eeca106725	8875	#define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
Kojto	122:f9eeca106725	8876	#define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
Kojto	122:f9eeca106725	8877	#define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
Kojto	122:f9eeca106725	8878	#define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
Kojto	122:f9eeca106725	8879	#define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
Kojto	122:f9eeca106725	8880	#define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
Kojto	122:f9eeca106725	8881	#define ETH_MACA2HR_MACA2H 0x0000FFFFU /* MAC address1 high */
Kojto	110:165afa46840b	8882
Kojto	110:165afa46840b	8883	/* Bit definition for Ethernet MAC Address2 Low Register */
Kojto	122:f9eeca106725	8884	#define ETH_MACA2LR_MACA2L 0xFFFFFFFFU /* MAC address2 low */
Kojto	110:165afa46840b	8885
Kojto	110:165afa46840b	8886	/* Bit definition for Ethernet MAC Address3 High Register */
Kojto	122:f9eeca106725	8887	#define ETH_MACA3HR_AE 0x80000000U /* Address enable */
Kojto	122:f9eeca106725	8888	#define ETH_MACA3HR_SA 0x40000000U /* Source address */
Kojto	122:f9eeca106725	8889	#define ETH_MACA3HR_MBC 0x3F000000U /* Mask byte control */
Kojto	122:f9eeca106725	8890	#define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
Kojto	122:f9eeca106725	8891	#define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
Kojto	122:f9eeca106725	8892	#define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
Kojto	122:f9eeca106725	8893	#define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
Kojto	122:f9eeca106725	8894	#define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
Kojto	122:f9eeca106725	8895	#define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
Kojto	122:f9eeca106725	8896	#define ETH_MACA3HR_MACA3H 0x0000FFFFU /* MAC address3 high */
Kojto	110:165afa46840b	8897
Kojto	110:165afa46840b	8898	/* Bit definition for Ethernet MAC Address3 Low Register */
Kojto	122:f9eeca106725	8899	#define ETH_MACA3LR_MACA3L 0xFFFFFFFFU /* MAC address3 low */
Kojto	110:165afa46840b	8900
Kojto	110:165afa46840b	8901	/******************************************************************************/
Kojto	110:165afa46840b	8902	/* Ethernet MMC Registers bits definition */
Kojto	110:165afa46840b	8903	/******************************************************************************/
Kojto	110:165afa46840b	8904
Kojto	110:165afa46840b	8905	/* Bit definition for Ethernet MMC Contol Register */
Kojto	122:f9eeca106725	8906	#define ETH_MMCCR_MCFHP 0x00000020U /* MMC counter Full-Half preset */
Kojto	122:f9eeca106725	8907	#define ETH_MMCCR_MCP 0x00000010U /* MMC counter preset */
Kojto	122:f9eeca106725	8908	#define ETH_MMCCR_MCF 0x00000008U /* MMC Counter Freeze */
Kojto	122:f9eeca106725	8909	#define ETH_MMCCR_ROR 0x00000004U /* Reset on Read */
Kojto	122:f9eeca106725	8910	#define ETH_MMCCR_CSR 0x00000002U /* Counter Stop Rollover */
Kojto	122:f9eeca106725	8911	#define ETH_MMCCR_CR 0x00000001U /* Counters Reset */
Kojto	110:165afa46840b	8912
Kojto	110:165afa46840b	8913	/* Bit definition for Ethernet MMC Receive Interrupt Register */
Kojto	122:f9eeca106725	8914	#define ETH_MMCRIR_RGUFS 0x00020000U /* Set when Rx good unicast frames counter reaches half the maximum value */
Kojto	122:f9eeca106725	8915	#define ETH_MMCRIR_RFAES 0x00000040U /* Set when Rx alignment error counter reaches half the maximum value */
Kojto	122:f9eeca106725	8916	#define ETH_MMCRIR_RFCES 0x00000020U /* Set when Rx crc error counter reaches half the maximum value */
Kojto	110:165afa46840b	8917
Kojto	110:165afa46840b	8918	/* Bit definition for Ethernet MMC Transmit Interrupt Register */
Kojto	122:f9eeca106725	8919	#define ETH_MMCTIR_TGFS 0x00200000U /* Set when Tx good frame count counter reaches half the maximum value */
Kojto	122:f9eeca106725	8920	#define ETH_MMCTIR_TGFMSCS 0x00008000U /* Set when Tx good multi col counter reaches half the maximum value */
Kojto	122:f9eeca106725	8921	#define ETH_MMCTIR_TGFSCS 0x00004000U /* Set when Tx good single col counter reaches half the maximum value */
Kojto	110:165afa46840b	8922
Kojto	110:165afa46840b	8923	/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
Kojto	122:f9eeca106725	8924	#define ETH_MMCRIMR_RGUFM 0x00020000U /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
Kojto	122:f9eeca106725	8925	#define ETH_MMCRIMR_RFAEM 0x00000040U /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
Kojto	122:f9eeca106725	8926	#define ETH_MMCRIMR_RFCEM 0x00000020U /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
Kojto	110:165afa46840b	8927
Kojto	110:165afa46840b	8928	/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
Kojto	122:f9eeca106725	8929	#define ETH_MMCTIMR_TGFM 0x00200000U /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
Kojto	122:f9eeca106725	8930	#define ETH_MMCTIMR_TGFMSCM 0x00008000U /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
Kojto	122:f9eeca106725	8931	#define ETH_MMCTIMR_TGFSCM 0x00004000U /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
Kojto	110:165afa46840b	8932
Kojto	110:165afa46840b	8933	/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
Kojto	122:f9eeca106725	8934	#define ETH_MMCTGFSCCR_TGFSCC 0xFFFFFFFFU /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
Kojto	110:165afa46840b	8935
Kojto	110:165afa46840b	8936	/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
Kojto	122:f9eeca106725	8937	#define ETH_MMCTGFMSCCR_TGFMSCC 0xFFFFFFFFU /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
Kojto	110:165afa46840b	8938
Kojto	110:165afa46840b	8939	/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
Kojto	122:f9eeca106725	8940	#define ETH_MMCTGFCR_TGFC 0xFFFFFFFFU /* Number of good frames transmitted. */
Kojto	110:165afa46840b	8941
Kojto	110:165afa46840b	8942	/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
Kojto	122:f9eeca106725	8943	#define ETH_MMCRFCECR_RFCEC 0xFFFFFFFFU /* Number of frames received with CRC error. */
Kojto	110:165afa46840b	8944
Kojto	110:165afa46840b	8945	/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
Kojto	122:f9eeca106725	8946	#define ETH_MMCRFAECR_RFAEC 0xFFFFFFFFU /* Number of frames received with alignment (dribble) error */
Kojto	110:165afa46840b	8947
Kojto	110:165afa46840b	8948	/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
Kojto	122:f9eeca106725	8949	#define ETH_MMCRGUFCR_RGUFC 0xFFFFFFFFU /* Number of good unicast frames received. */
Kojto	110:165afa46840b	8950
Kojto	110:165afa46840b	8951	/******************************************************************************/
Kojto	110:165afa46840b	8952	/* Ethernet PTP Registers bits definition */
Kojto	110:165afa46840b	8953	/******************************************************************************/
Kojto	110:165afa46840b	8954
Kojto	110:165afa46840b	8955	/* Bit definition for Ethernet PTP Time Stamp Contol Register */
Kojto	122:f9eeca106725	8956	#define ETH_PTPTSCR_TSCNT 0x00030000U /* Time stamp clock node type */
Kojto	122:f9eeca106725	8957	#define ETH_PTPTSSR_TSSMRME 0x00008000U /* Time stamp snapshot for message relevant to master enable */
Kojto	122:f9eeca106725	8958	#define ETH_PTPTSSR_TSSEME 0x00004000U /* Time stamp snapshot for event message enable */
Kojto	122:f9eeca106725	8959	#define ETH_PTPTSSR_TSSIPV4FE 0x00002000U /* Time stamp snapshot for IPv4 frames enable */
Kojto	122:f9eeca106725	8960	#define ETH_PTPTSSR_TSSIPV6FE 0x00001000U /* Time stamp snapshot for IPv6 frames enable */
Kojto	122:f9eeca106725	8961	#define ETH_PTPTSSR_TSSPTPOEFE 0x00000800U /* Time stamp snapshot for PTP over ethernet frames enable */
Kojto	122:f9eeca106725	8962	#define ETH_PTPTSSR_TSPTPPSV2E 0x00000400U /* Time stamp PTP packet snooping for version2 format enable */
Kojto	122:f9eeca106725	8963	#define ETH_PTPTSSR_TSSSR 0x00000200U /* Time stamp Sub-seconds rollover */
Kojto	122:f9eeca106725	8964	#define ETH_PTPTSSR_TSSARFE 0x00000100U /* Time stamp snapshot for all received frames enable */
Kojto	122:f9eeca106725	8965
Kojto	122:f9eeca106725	8966	#define ETH_PTPTSCR_TSARU 0x00000020U /* Addend register update */
Kojto	122:f9eeca106725	8967	#define ETH_PTPTSCR_TSITE 0x00000010U /* Time stamp interrupt trigger enable */
Kojto	122:f9eeca106725	8968	#define ETH_PTPTSCR_TSSTU 0x00000008U /* Time stamp update */
Kojto	122:f9eeca106725	8969	#define ETH_PTPTSCR_TSSTI 0x00000004U /* Time stamp initialize */
Kojto	122:f9eeca106725	8970	#define ETH_PTPTSCR_TSFCU 0x00000002U /* Time stamp fine or coarse update */
Kojto	122:f9eeca106725	8971	#define ETH_PTPTSCR_TSE 0x00000001U /* Time stamp enable */
Kojto	110:165afa46840b	8972
Kojto	110:165afa46840b	8973	/* Bit definition for Ethernet PTP Sub-Second Increment Register */
Kojto	122:f9eeca106725	8974	#define ETH_PTPSSIR_STSSI 0x000000FFU /* System time Sub-second increment value */
Kojto	110:165afa46840b	8975
Kojto	110:165afa46840b	8976	/* Bit definition for Ethernet PTP Time Stamp High Register */
Kojto	122:f9eeca106725	8977	#define ETH_PTPTSHR_STS 0xFFFFFFFFU /* System Time second */
Kojto	110:165afa46840b	8978
Kojto	110:165afa46840b	8979	/* Bit definition for Ethernet PTP Time Stamp Low Register */
Kojto	122:f9eeca106725	8980	#define ETH_PTPTSLR_STPNS 0x80000000U /* System Time Positive or negative time */
Kojto	122:f9eeca106725	8981	#define ETH_PTPTSLR_STSS 0x7FFFFFFFU /* System Time sub-seconds */
Kojto	110:165afa46840b	8982
Kojto	110:165afa46840b	8983	/* Bit definition for Ethernet PTP Time Stamp High Update Register */
Kojto	122:f9eeca106725	8984	#define ETH_PTPTSHUR_TSUS 0xFFFFFFFFU /* Time stamp update seconds */
Kojto	110:165afa46840b	8985
Kojto	110:165afa46840b	8986	/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
Kojto	122:f9eeca106725	8987	#define ETH_PTPTSLUR_TSUPNS 0x80000000U /* Time stamp update Positive or negative time */
Kojto	122:f9eeca106725	8988	#define ETH_PTPTSLUR_TSUSS 0x7FFFFFFFU /* Time stamp update sub-seconds */
Kojto	110:165afa46840b	8989
Kojto	110:165afa46840b	8990	/* Bit definition for Ethernet PTP Time Stamp Addend Register */
Kojto	122:f9eeca106725	8991	#define ETH_PTPTSAR_TSA 0xFFFFFFFFU /* Time stamp addend */
Kojto	110:165afa46840b	8992
Kojto	110:165afa46840b	8993	/* Bit definition for Ethernet PTP Target Time High Register */
Kojto	122:f9eeca106725	8994	#define ETH_PTPTTHR_TTSH 0xFFFFFFFFU /* Target time stamp high */
Kojto	110:165afa46840b	8995
Kojto	110:165afa46840b	8996	/* Bit definition for Ethernet PTP Target Time Low Register */
Kojto	122:f9eeca106725	8997	#define ETH_PTPTTLR_TTSL 0xFFFFFFFFU /* Target time stamp low */
Kojto	110:165afa46840b	8998
Kojto	110:165afa46840b	8999	/* Bit definition for Ethernet PTP Time Stamp Status Register */
Kojto	122:f9eeca106725	9000	#define ETH_PTPTSSR_TSTTR 0x00000020U /* Time stamp target time reached */
Kojto	122:f9eeca106725	9001	#define ETH_PTPTSSR_TSSO 0x00000010U /* Time stamp seconds overflow */
Kojto	110:165afa46840b	9002
Kojto	110:165afa46840b	9003	/******************************************************************************/
Kojto	110:165afa46840b	9004	/* Ethernet DMA Registers bits definition */
Kojto	110:165afa46840b	9005	/******************************************************************************/
Kojto	110:165afa46840b	9006
Kojto	110:165afa46840b	9007	/* Bit definition for Ethernet DMA Bus Mode Register */
Kojto	122:f9eeca106725	9008	#define ETH_DMABMR_AAB 0x02000000U /* Address-Aligned beats */
Kojto	122:f9eeca106725	9009	#define ETH_DMABMR_FPM 0x01000000U /* 4xPBL mode */
Kojto	122:f9eeca106725	9010	#define ETH_DMABMR_USP 0x00800000U /* Use separate PBL */
Kojto	122:f9eeca106725	9011	#define ETH_DMABMR_RDP 0x007E0000U /* RxDMA PBL */
Kojto	122:f9eeca106725	9012	#define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
Kojto	122:f9eeca106725	9013	#define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
Kojto	122:f9eeca106725	9014	#define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
Kojto	122:f9eeca106725	9015	#define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
Kojto	122:f9eeca106725	9016	#define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
Kojto	122:f9eeca106725	9017	#define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
Kojto	122:f9eeca106725	9018	#define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
Kojto	122:f9eeca106725	9019	#define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
Kojto	122:f9eeca106725	9020	#define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
Kojto	122:f9eeca106725	9021	#define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
Kojto	122:f9eeca106725	9022	#define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
Kojto	122:f9eeca106725	9023	#define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
Kojto	122:f9eeca106725	9024	#define ETH_DMABMR_FB 0x00010000U /* Fixed Burst */
Kojto	122:f9eeca106725	9025	#define ETH_DMABMR_RTPR 0x0000C000U /* Rx Tx priority ratio */
Kojto	122:f9eeca106725	9026	#define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */
Kojto	122:f9eeca106725	9027	#define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */
Kojto	122:f9eeca106725	9028	#define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */
Kojto	122:f9eeca106725	9029	#define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */
Kojto	122:f9eeca106725	9030	#define ETH_DMABMR_PBL 0x00003F00U /* Programmable burst length */
Kojto	122:f9eeca106725	9031	#define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
Kojto	122:f9eeca106725	9032	#define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
Kojto	122:f9eeca106725	9033	#define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
Kojto	122:f9eeca106725	9034	#define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
Kojto	122:f9eeca106725	9035	#define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
Kojto	122:f9eeca106725	9036	#define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
Kojto	122:f9eeca106725	9037	#define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
Kojto	122:f9eeca106725	9038	#define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
Kojto	122:f9eeca106725	9039	#define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
Kojto	122:f9eeca106725	9040	#define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
Kojto	122:f9eeca106725	9041	#define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
Kojto	122:f9eeca106725	9042	#define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
Kojto	122:f9eeca106725	9043	#define ETH_DMABMR_EDE 0x00000080U /* Enhanced Descriptor Enable */
Kojto	122:f9eeca106725	9044	#define ETH_DMABMR_DSL 0x0000007CU /* Descriptor Skip Length */
Kojto	122:f9eeca106725	9045	#define ETH_DMABMR_DA 0x00000002U /* DMA arbitration scheme */
Kojto	122:f9eeca106725	9046	#define ETH_DMABMR_SR 0x00000001U /* Software reset */
Kojto	110:165afa46840b	9047
Kojto	110:165afa46840b	9048	/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
Kojto	122:f9eeca106725	9049	#define ETH_DMATPDR_TPD 0xFFFFFFFFU /* Transmit poll demand */
Kojto	110:165afa46840b	9050
Kojto	110:165afa46840b	9051	/* Bit definition for Ethernet DMA Receive Poll Demand Register */
Kojto	122:f9eeca106725	9052	#define ETH_DMARPDR_RPD 0xFFFFFFFFU /* Receive poll demand */
Kojto	110:165afa46840b	9053
Kojto	110:165afa46840b	9054	/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
Kojto	122:f9eeca106725	9055	#define ETH_DMARDLAR_SRL 0xFFFFFFFFU /* Start of receive list */
Kojto	110:165afa46840b	9056
Kojto	110:165afa46840b	9057	/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
Kojto	122:f9eeca106725	9058	#define ETH_DMATDLAR_STL 0xFFFFFFFFU /* Start of transmit list */
Kojto	110:165afa46840b	9059
Kojto	110:165afa46840b	9060	/* Bit definition for Ethernet DMA Status Register */
Kojto	122:f9eeca106725	9061	#define ETH_DMASR_TSTS 0x20000000U /* Time-stamp trigger status */
Kojto	122:f9eeca106725	9062	#define ETH_DMASR_PMTS 0x10000000U /* PMT status */
Kojto	122:f9eeca106725	9063	#define ETH_DMASR_MMCS 0x08000000U /* MMC status */
Kojto	122:f9eeca106725	9064	#define ETH_DMASR_EBS 0x03800000U /* Error bits status */
Kojto	110:165afa46840b	9065	/* combination with EBS[2:0] for GetFlagStatus function */
Kojto	122:f9eeca106725	9066	#define ETH_DMASR_EBS_DescAccess 0x02000000U /* Error bits 0-data buffer, 1-desc. access */
Kojto	122:f9eeca106725	9067	#define ETH_DMASR_EBS_ReadTransf 0x01000000U /* Error bits 0-write trnsf, 1-read transfr */
Kojto	122:f9eeca106725	9068	#define ETH_DMASR_EBS_DataTransfTx 0x00800000U /* Error bits 0-Rx DMA, 1-Tx DMA */
Kojto	122:f9eeca106725	9069	#define ETH_DMASR_TPS 0x00700000U /* Transmit process state */
Kojto	122:f9eeca106725	9070	#define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */
Kojto	122:f9eeca106725	9071	#define ETH_DMASR_TPS_Fetching 0x00100000U /* Running - fetching the Tx descriptor */
Kojto	122:f9eeca106725	9072	#define ETH_DMASR_TPS_Waiting 0x00200000U /* Running - waiting for status */
Kojto	122:f9eeca106725	9073	#define ETH_DMASR_TPS_Reading 0x00300000U /* Running - reading the data from host memory */
Kojto	122:f9eeca106725	9074	#define ETH_DMASR_TPS_Suspended 0x00600000U /* Suspended - Tx Descriptor unavailabe */
Kojto	122:f9eeca106725	9075	#define ETH_DMASR_TPS_Closing 0x00700000U /* Running - closing Rx descriptor */
Kojto	122:f9eeca106725	9076	#define ETH_DMASR_RPS 0x000E0000U /* Receive process state */
Kojto	122:f9eeca106725	9077	#define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */
Kojto	122:f9eeca106725	9078	#define ETH_DMASR_RPS_Fetching 0x00020000U /* Running - fetching the Rx descriptor */
Kojto	122:f9eeca106725	9079	#define ETH_DMASR_RPS_Waiting 0x00060000U /* Running - waiting for packet */
Kojto	122:f9eeca106725	9080	#define ETH_DMASR_RPS_Suspended 0x00080000U /* Suspended - Rx Descriptor unavailable */
Kojto	122:f9eeca106725	9081	#define ETH_DMASR_RPS_Closing 0x000A0000U /* Running - closing descriptor */
Kojto	122:f9eeca106725	9082	#define ETH_DMASR_RPS_Queuing 0x000E0000U /* Running - queuing the recieve frame into host memory */
Kojto	122:f9eeca106725	9083	#define ETH_DMASR_NIS 0x00010000U /* Normal interrupt summary */
Kojto	122:f9eeca106725	9084	#define ETH_DMASR_AIS 0x00008000U /* Abnormal interrupt summary */
Kojto	122:f9eeca106725	9085	#define ETH_DMASR_ERS 0x00004000U /* Early receive status */
Kojto	122:f9eeca106725	9086	#define ETH_DMASR_FBES 0x00002000U /* Fatal bus error status */
Kojto	122:f9eeca106725	9087	#define ETH_DMASR_ETS 0x00000400U /* Early transmit status */
Kojto	122:f9eeca106725	9088	#define ETH_DMASR_RWTS 0x00000200U /* Receive watchdog timeout status */
Kojto	122:f9eeca106725	9089	#define ETH_DMASR_RPSS 0x00000100U /* Receive process stopped status */
Kojto	122:f9eeca106725	9090	#define ETH_DMASR_RBUS 0x00000080U /* Receive buffer unavailable status */
Kojto	122:f9eeca106725	9091	#define ETH_DMASR_RS 0x00000040U /* Receive status */
Kojto	122:f9eeca106725	9092	#define ETH_DMASR_TUS 0x00000020U /* Transmit underflow status */
Kojto	122:f9eeca106725	9093	#define ETH_DMASR_ROS 0x00000010U /* Receive overflow status */
Kojto	122:f9eeca106725	9094	#define ETH_DMASR_TJTS 0x00000008U /* Transmit jabber timeout status */
Kojto	122:f9eeca106725	9095	#define ETH_DMASR_TBUS 0x00000004U /* Transmit buffer unavailable status */
Kojto	122:f9eeca106725	9096	#define ETH_DMASR_TPSS 0x00000002U /* Transmit process stopped status */
Kojto	122:f9eeca106725	9097	#define ETH_DMASR_TS 0x00000001U /* Transmit status */
Kojto	110:165afa46840b	9098
Kojto	110:165afa46840b	9099	/* Bit definition for Ethernet DMA Operation Mode Register */
Kojto	122:f9eeca106725	9100	#define ETH_DMAOMR_DTCEFD 0x04000000U /* Disable Dropping of TCP/IP checksum error frames */
Kojto	122:f9eeca106725	9101	#define ETH_DMAOMR_RSF 0x02000000U /* Receive store and forward */
Kojto	122:f9eeca106725	9102	#define ETH_DMAOMR_DFRF 0x01000000U /* Disable flushing of received frames */
Kojto	122:f9eeca106725	9103	#define ETH_DMAOMR_TSF 0x00200000U /* Transmit store and forward */
Kojto	122:f9eeca106725	9104	#define ETH_DMAOMR_FTF 0x00100000U /* Flush transmit FIFO */
Kojto	122:f9eeca106725	9105	#define ETH_DMAOMR_TTC 0x0001C000U /* Transmit threshold control */
Kojto	122:f9eeca106725	9106	#define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */
Kojto	122:f9eeca106725	9107	#define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */
Kojto	122:f9eeca106725	9108	#define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */
Kojto	122:f9eeca106725	9109	#define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */
Kojto	122:f9eeca106725	9110	#define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */
Kojto	122:f9eeca106725	9111	#define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */
Kojto	122:f9eeca106725	9112	#define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */
Kojto	122:f9eeca106725	9113	#define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */
Kojto	122:f9eeca106725	9114	#define ETH_DMAOMR_ST 0x00002000U /* Start/stop transmission command */
Kojto	122:f9eeca106725	9115	#define ETH_DMAOMR_FEF 0x00000080U /* Forward error frames */
Kojto	122:f9eeca106725	9116	#define ETH_DMAOMR_FUGF 0x00000040U /* Forward undersized good frames */
Kojto	122:f9eeca106725	9117	#define ETH_DMAOMR_RTC 0x00000018U /* receive threshold control */
Kojto	122:f9eeca106725	9118	#define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */
Kojto	122:f9eeca106725	9119	#define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */
Kojto	122:f9eeca106725	9120	#define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */
Kojto	122:f9eeca106725	9121	#define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */
Kojto	122:f9eeca106725	9122	#define ETH_DMAOMR_OSF 0x00000004U /* operate on second frame */
Kojto	122:f9eeca106725	9123	#define ETH_DMAOMR_SR 0x00000002U /* Start/stop receive */
Kojto	110:165afa46840b	9124
Kojto	110:165afa46840b	9125	/* Bit definition for Ethernet DMA Interrupt Enable Register */
Kojto	122:f9eeca106725	9126	#define ETH_DMAIER_NISE 0x00010000U /* Normal interrupt summary enable */
Kojto	122:f9eeca106725	9127	#define ETH_DMAIER_AISE 0x00008000U /* Abnormal interrupt summary enable */
Kojto	122:f9eeca106725	9128	#define ETH_DMAIER_ERIE 0x00004000U /* Early receive interrupt enable */
Kojto	122:f9eeca106725	9129	#define ETH_DMAIER_FBEIE 0x00002000U /* Fatal bus error interrupt enable */
Kojto	122:f9eeca106725	9130	#define ETH_DMAIER_ETIE 0x00000400U /* Early transmit interrupt enable */
Kojto	122:f9eeca106725	9131	#define ETH_DMAIER_RWTIE 0x00000200U /* Receive watchdog timeout interrupt enable */
Kojto	122:f9eeca106725	9132	#define ETH_DMAIER_RPSIE 0x00000100U /* Receive process stopped interrupt enable */
Kojto	122:f9eeca106725	9133	#define ETH_DMAIER_RBUIE 0x00000080U /* Receive buffer unavailable interrupt enable */
Kojto	122:f9eeca106725	9134	#define ETH_DMAIER_RIE 0x00000040U /* Receive interrupt enable */
Kojto	122:f9eeca106725	9135	#define ETH_DMAIER_TUIE 0x00000020U /* Transmit Underflow interrupt enable */
Kojto	122:f9eeca106725	9136	#define ETH_DMAIER_ROIE 0x00000010U /* Receive Overflow interrupt enable */
Kojto	122:f9eeca106725	9137	#define ETH_DMAIER_TJTIE 0x00000008U /* Transmit jabber timeout interrupt enable */
Kojto	122:f9eeca106725	9138	#define ETH_DMAIER_TBUIE 0x00000004U /* Transmit buffer unavailable interrupt enable */
Kojto	122:f9eeca106725	9139	#define ETH_DMAIER_TPSIE 0x00000002U /* Transmit process stopped interrupt enable */
Kojto	122:f9eeca106725	9140	#define ETH_DMAIER_TIE 0x00000001U /* Transmit interrupt enable */
Kojto	110:165afa46840b	9141
Kojto	110:165afa46840b	9142	/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
Kojto	122:f9eeca106725	9143	#define ETH_DMAMFBOCR_OFOC 0x10000000U /* Overflow bit for FIFO overflow counter */
Kojto	122:f9eeca106725	9144	#define ETH_DMAMFBOCR_MFA 0x0FFE0000U /* Number of frames missed by the application */
Kojto	122:f9eeca106725	9145	#define ETH_DMAMFBOCR_OMFC 0x00010000U /* Overflow bit for missed frame counter */
Kojto	122:f9eeca106725	9146	#define ETH_DMAMFBOCR_MFC 0x0000FFFFU /* Number of frames missed by the controller */
Kojto	110:165afa46840b	9147
Kojto	110:165afa46840b	9148	/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
Kojto	122:f9eeca106725	9149	#define ETH_DMACHTDR_HTDAP 0xFFFFFFFFU /* Host transmit descriptor address pointer */
Kojto	110:165afa46840b	9150
Kojto	110:165afa46840b	9151	/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
Kojto	122:f9eeca106725	9152	#define ETH_DMACHRDR_HRDAP 0xFFFFFFFFU /* Host receive descriptor address pointer */
Kojto	110:165afa46840b	9153
Kojto	110:165afa46840b	9154	/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
Kojto	122:f9eeca106725	9155	#define ETH_DMACHTBAR_HTBAP 0xFFFFFFFFU /* Host transmit buffer address pointer */
Kojto	110:165afa46840b	9156
Kojto	110:165afa46840b	9157	/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
Kojto	122:f9eeca106725	9158	#define ETH_DMACHRBAR_HRBAP 0xFFFFFFFFU /* Host receive buffer address pointer */
Kojto	110:165afa46840b	9159
Kojto	110:165afa46840b	9160	/******************************************************************************/
Kojto	110:165afa46840b	9161	/* */
Kojto	110:165afa46840b	9162	/* USB_OTG */
Kojto	110:165afa46840b	9163	/* */
Kojto	110:165afa46840b	9164	/******************************************************************************/
Kojto	110:165afa46840b	9165	/****************** Bit definition forUSB_OTG_GOTGCTL register ******************/
Kojto	122:f9eeca106725	9166	#define USB_OTG_GOTGCTL_SRQSCS 0x00000001U /!< Session request success /
Kojto	122:f9eeca106725	9167	#define USB_OTG_GOTGCTL_SRQ 0x00000002U /!< Session request /
Kojto	122:f9eeca106725	9168	#define USB_OTG_GOTGCTL_VBVALOEN 0x00000004U /!< VBUS valid override enable /
Kojto	122:f9eeca106725	9169	#define USB_OTG_GOTGCTL_VBVALOVAL 0x00000008U /!< VBUS valid override value /
Kojto	122:f9eeca106725	9170	#define USB_OTG_GOTGCTL_AVALOEN 0x00000010U /!< A-peripheral session valid override enable /
Kojto	122:f9eeca106725	9171	#define USB_OTG_GOTGCTL_AVALOVAL 0x00000020U /!< A-peripheral session valid override value /
Kojto	122:f9eeca106725	9172	#define USB_OTG_GOTGCTL_BVALOEN 0x00000040U /!< B-peripheral session valid override enable /
Kojto	122:f9eeca106725	9173	#define USB_OTG_GOTGCTL_BVALOVAL 0x00000080U /!< B-peripheral session valid override value /
Kojto	122:f9eeca106725	9174	#define USB_OTG_GOTGCTL_HNGSCS 0x00000100U /!< Host set HNP enable /
Kojto	122:f9eeca106725	9175	#define USB_OTG_GOTGCTL_HNPRQ 0x00000200U /!< HNP request /
Kojto	122:f9eeca106725	9176	#define USB_OTG_GOTGCTL_HSHNPEN 0x00000400U /!< Host set HNP enable /
Kojto	122:f9eeca106725	9177	#define USB_OTG_GOTGCTL_DHNPEN 0x00000800U /!< Device HNP enabled /
Kojto	122:f9eeca106725	9178	#define USB_OTG_GOTGCTL_EHEN 0x00001000U /!< Embedded host enable /
Kojto	122:f9eeca106725	9179	#define USB_OTG_GOTGCTL_CIDSTS 0x00010000U /!< Connector ID status /
Kojto	122:f9eeca106725	9180	#define USB_OTG_GOTGCTL_DBCT 0x00020000U /!< Long/short debounce time /
Kojto	122:f9eeca106725	9181	#define USB_OTG_GOTGCTL_ASVLD 0x00040000U /!< A-session valid /
Kojto	122:f9eeca106725	9182	#define USB_OTG_GOTGCTL_BSESVLD 0x00080000U /!< B-session valid /
Kojto	122:f9eeca106725	9183	#define USB_OTG_GOTGCTL_OTGVER 0x00100000U /!< OTG version /
Kojto	110:165afa46840b	9184
Kojto	110:165afa46840b	9185	/****************** Bit definition forUSB_OTG_HCFG register ******************/
Kojto	110:165afa46840b	9186
Kojto	122:f9eeca106725	9187	#define USB_OTG_HCFG_FSLSPCS 0x00000003U /!< FS/LS PHY clock select /
Kojto	122:f9eeca106725	9188	#define USB_OTG_HCFG_FSLSPCS_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	9189	#define USB_OTG_HCFG_FSLSPCS_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	9190	#define USB_OTG_HCFG_FSLSS 0x00000004U /!< FS- and LS-only support /
Kojto	110:165afa46840b	9191
Kojto	110:165afa46840b	9192	/****************** Bit definition forUSB_OTG_DCFG register ******************/
Kojto	110:165afa46840b	9193
Kojto	122:f9eeca106725	9194	#define USB_OTG_DCFG_DSPD 0x00000003U /!< Device speed /
Kojto	122:f9eeca106725	9195	#define USB_OTG_DCFG_DSPD_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	9196	#define USB_OTG_DCFG_DSPD_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	9197	#define USB_OTG_DCFG_NZLSOHSK 0x00000004U /!< Nonzero-length status OUT handshake /
Kojto	122:f9eeca106725	9198
Kojto	122:f9eeca106725	9199	#define USB_OTG_DCFG_DAD 0x000007F0U /!< Device address /
Kojto	122:f9eeca106725	9200	#define USB_OTG_DCFG_DAD_0 0x00000010U /!<Bit 0 /
Kojto	122:f9eeca106725	9201	#define USB_OTG_DCFG_DAD_1 0x00000020U /!<Bit 1 /
Kojto	122:f9eeca106725	9202	#define USB_OTG_DCFG_DAD_2 0x00000040U /!<Bit 2 /
Kojto	122:f9eeca106725	9203	#define USB_OTG_DCFG_DAD_3 0x00000080U /!<Bit 3 /
Kojto	122:f9eeca106725	9204	#define USB_OTG_DCFG_DAD_4 0x00000100U /!<Bit 4 /
Kojto	122:f9eeca106725	9205	#define USB_OTG_DCFG_DAD_5 0x00000200U /!<Bit 5 /
Kojto	122:f9eeca106725	9206	#define USB_OTG_DCFG_DAD_6 0x00000400U /!<Bit 6 /
Kojto	122:f9eeca106725	9207
Kojto	122:f9eeca106725	9208	#define USB_OTG_DCFG_PFIVL 0x00001800U /!< Periodic (micro)frame interval /
Kojto	122:f9eeca106725	9209	#define USB_OTG_DCFG_PFIVL_0 0x00000800U /!<Bit 0 /
Kojto	122:f9eeca106725	9210	#define USB_OTG_DCFG_PFIVL_1 0x00001000U /!<Bit 1 /
Kojto	122:f9eeca106725	9211
Kojto	122:f9eeca106725	9212	#define USB_OTG_DCFG_PERSCHIVL 0x03000000U /!< Periodic scheduling interval /
Kojto	122:f9eeca106725	9213	#define USB_OTG_DCFG_PERSCHIVL_0 0x01000000U /!<Bit 0 /
Kojto	122:f9eeca106725	9214	#define USB_OTG_DCFG_PERSCHIVL_1 0x02000000U /!<Bit 1 /
Kojto	110:165afa46840b	9215
Kojto	110:165afa46840b	9216	/****************** Bit definition forUSB_OTG_PCGCR register ******************/
Kojto	122:f9eeca106725	9217	#define USB_OTG_PCGCR_STPPCLK 0x00000001U /!< Stop PHY clock /
Kojto	122:f9eeca106725	9218	#define USB_OTG_PCGCR_GATEHCLK 0x00000002U /!< Gate HCLK /
Kojto	122:f9eeca106725	9219	#define USB_OTG_PCGCR_PHYSUSP 0x00000010U /!< PHY suspended /
Kojto	110:165afa46840b	9220
Kojto	110:165afa46840b	9221	/****************** Bit definition forUSB_OTG_GOTGINT register ******************/
Kojto	122:f9eeca106725	9222	#define USB_OTG_GOTGINT_SEDET 0x00000004U /!< Session end detected /
Kojto	122:f9eeca106725	9223	#define USB_OTG_GOTGINT_SRSSCHG 0x00000100U /!< Session request success status change /
Kojto	122:f9eeca106725	9224	#define USB_OTG_GOTGINT_HNSSCHG 0x00000200U /!< Host negotiation success status change /
Kojto	122:f9eeca106725	9225	#define USB_OTG_GOTGINT_HNGDET 0x00020000U /!< Host negotiation detected /
Kojto	122:f9eeca106725	9226	#define USB_OTG_GOTGINT_ADTOCHG 0x00040000U /!< A-device timeout change /
Kojto	122:f9eeca106725	9227	#define USB_OTG_GOTGINT_DBCDNE 0x00080000U /!< Debounce done /
Kojto	122:f9eeca106725	9228	#define USB_OTG_GOTGINT_IDCHNG 0x00100000U /!< Change in ID pin input value /
Kojto	110:165afa46840b	9229
Kojto	110:165afa46840b	9230	/****************** Bit definition forUSB_OTG_DCTL register ******************/
Kojto	122:f9eeca106725	9231	#define USB_OTG_DCTL_RWUSIG 0x00000001U /!< Remote wakeup signaling /
Kojto	122:f9eeca106725	9232	#define USB_OTG_DCTL_SDIS 0x00000002U /!< Soft disconnect /
Kojto	122:f9eeca106725	9233	#define USB_OTG_DCTL_GINSTS 0x00000004U /!< Global IN NAK status /
Kojto	122:f9eeca106725	9234	#define USB_OTG_DCTL_GONSTS 0x00000008U /!< Global OUT NAK status /
Kojto	122:f9eeca106725	9235
Kojto	122:f9eeca106725	9236	#define USB_OTG_DCTL_TCTL 0x00000070U /!< Test control /
Kojto	122:f9eeca106725	9237	#define USB_OTG_DCTL_TCTL_0 0x00000010U /!<Bit 0 /
Kojto	122:f9eeca106725	9238	#define USB_OTG_DCTL_TCTL_1 0x00000020U /!<Bit 1 /
Kojto	122:f9eeca106725	9239	#define USB_OTG_DCTL_TCTL_2 0x00000040U /!<Bit 2 /
Kojto	122:f9eeca106725	9240	#define USB_OTG_DCTL_SGINAK 0x00000080U /!< Set global IN NAK /
Kojto	122:f9eeca106725	9241	#define USB_OTG_DCTL_CGINAK 0x00000100U /!< Clear global IN NAK /
Kojto	122:f9eeca106725	9242	#define USB_OTG_DCTL_SGONAK 0x00000200U /!< Set global OUT NAK /
Kojto	122:f9eeca106725	9243	#define USB_OTG_DCTL_CGONAK 0x00000400U /!< Clear global OUT NAK /
Kojto	122:f9eeca106725	9244	#define USB_OTG_DCTL_POPRGDNE 0x00000800U /!< Power-on programming done /
Kojto	110:165afa46840b	9245
Kojto	110:165afa46840b	9246	/****************** Bit definition forUSB_OTG_HFIR register ******************/
Kojto	122:f9eeca106725	9247	#define USB_OTG_HFIR_FRIVL 0x0000FFFFU /!< Frame interval /
Kojto	110:165afa46840b	9248
Kojto	110:165afa46840b	9249	/****************** Bit definition forUSB_OTG_HFNUM register ******************/
Kojto	122:f9eeca106725	9250	#define USB_OTG_HFNUM_FRNUM 0x0000FFFFU /!< Frame number /
Kojto	122:f9eeca106725	9251	#define USB_OTG_HFNUM_FTREM 0xFFFF0000U /!< Frame time remaining /
Kojto	110:165afa46840b	9252
Kojto	110:165afa46840b	9253	/****************** Bit definition forUSB_OTG_DSTS register ******************/
Kojto	122:f9eeca106725	9254	#define USB_OTG_DSTS_SUSPSTS 0x00000001U /!< Suspend status /
Kojto	122:f9eeca106725	9255
Kojto	122:f9eeca106725	9256	#define USB_OTG_DSTS_ENUMSPD 0x00000006U /!< Enumerated speed /
Kojto	122:f9eeca106725	9257	#define USB_OTG_DSTS_ENUMSPD_0 0x00000002U /!<Bit 0 /
Kojto	122:f9eeca106725	9258	#define USB_OTG_DSTS_ENUMSPD_1 0x00000004U /!<Bit 1 /
Kojto	122:f9eeca106725	9259	#define USB_OTG_DSTS_EERR 0x00000008U /!< Erratic error /
Kojto	122:f9eeca106725	9260	#define USB_OTG_DSTS_FNSOF 0x003FFF00U /!< Frame number of the received SOF /
Kojto	110:165afa46840b	9261
Kojto	110:165afa46840b	9262	/****************** Bit definition forUSB_OTG_GAHBCFG register ******************/
Kojto	122:f9eeca106725	9263	#define USB_OTG_GAHBCFG_GINT 0x00000001U /!< Global interrupt mask /
Kojto	122:f9eeca106725	9264	#define USB_OTG_GAHBCFG_HBSTLEN 0x0000001EU /!< Burst length/type /
Kojto	122:f9eeca106725	9265	#define USB_OTG_GAHBCFG_HBSTLEN_0 0x00000002U /!<Bit 0 /
Kojto	122:f9eeca106725	9266	#define USB_OTG_GAHBCFG_HBSTLEN_1 0x00000004U /!<Bit 1 /
Kojto	122:f9eeca106725	9267	#define USB_OTG_GAHBCFG_HBSTLEN_2 0x00000008U /!<Bit 2 /
Kojto	122:f9eeca106725	9268	#define USB_OTG_GAHBCFG_HBSTLEN_3 0x00000010U /!<Bit 3 /
Kojto	122:f9eeca106725	9269	#define USB_OTG_GAHBCFG_DMAEN 0x00000020U /!< DMA enable /
Kojto	122:f9eeca106725	9270	#define USB_OTG_GAHBCFG_TXFELVL 0x00000080U /!< TxFIFO empty level /
Kojto	122:f9eeca106725	9271	#define USB_OTG_GAHBCFG_PTXFELVL 0x00000100U /!< Periodic TxFIFO empty level /
Kojto	110:165afa46840b	9272
Kojto	110:165afa46840b	9273	/****************** Bit definition forUSB_OTG_GUSBCFG register ******************/
Kojto	110:165afa46840b	9274
Kojto	122:f9eeca106725	9275	#define USB_OTG_GUSBCFG_TOCAL 0x00000007U /!< FS timeout calibration /
Kojto	122:f9eeca106725	9276	#define USB_OTG_GUSBCFG_TOCAL_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	9277	#define USB_OTG_GUSBCFG_TOCAL_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	9278	#define USB_OTG_GUSBCFG_TOCAL_2 0x00000004U /!<Bit 2 /
Kojto	122:f9eeca106725	9279	#define USB_OTG_GUSBCFG_PHYSEL 0x00000040U /!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select /
Kojto	122:f9eeca106725	9280	#define USB_OTG_GUSBCFG_SRPCAP 0x00000100U /!< SRP-capable /
Kojto	122:f9eeca106725	9281	#define USB_OTG_GUSBCFG_HNPCAP 0x00000200U /!< HNP-capable /
Kojto	122:f9eeca106725	9282	#define USB_OTG_GUSBCFG_TRDT 0x00003C00U /!< USB turnaround time /
Kojto	122:f9eeca106725	9283	#define USB_OTG_GUSBCFG_TRDT_0 0x00000400U /!<Bit 0 /
Kojto	122:f9eeca106725	9284	#define USB_OTG_GUSBCFG_TRDT_1 0x00000800U /!<Bit 1 /
Kojto	122:f9eeca106725	9285	#define USB_OTG_GUSBCFG_TRDT_2 0x00001000U /!<Bit 2 /
Kojto	122:f9eeca106725	9286	#define USB_OTG_GUSBCFG_TRDT_3 0x00002000U /!<Bit 3 /
Kojto	122:f9eeca106725	9287	#define USB_OTG_GUSBCFG_PHYLPCS 0x00008000U /!< PHY Low-power clock select /
Kojto	122:f9eeca106725	9288	#define USB_OTG_GUSBCFG_ULPIFSLS 0x00020000U /!< ULPI FS/LS select /
Kojto	122:f9eeca106725	9289	#define USB_OTG_GUSBCFG_ULPIAR 0x00040000U /!< ULPI Auto-resume /
Kojto	122:f9eeca106725	9290	#define USB_OTG_GUSBCFG_ULPICSM 0x00080000U /!< ULPI Clock SuspendM /
Kojto	122:f9eeca106725	9291	#define USB_OTG_GUSBCFG_ULPIEVBUSD 0x00100000U /!< ULPI External VBUS Drive /
Kojto	122:f9eeca106725	9292	#define USB_OTG_GUSBCFG_ULPIEVBUSI 0x00200000U /!< ULPI external VBUS indicator /
Kojto	122:f9eeca106725	9293	#define USB_OTG_GUSBCFG_TSDPS 0x00400000U /!< TermSel DLine pulsing selection /
Kojto	122:f9eeca106725	9294	#define USB_OTG_GUSBCFG_PCCI 0x00800000U /!< Indicator complement /
Kojto	122:f9eeca106725	9295	#define USB_OTG_GUSBCFG_PTCI 0x01000000U /!< Indicator pass through /
Kojto	122:f9eeca106725	9296	#define USB_OTG_GUSBCFG_ULPIIPD 0x02000000U /!< ULPI interface protect disable /
Kojto	122:f9eeca106725	9297	#define USB_OTG_GUSBCFG_FHMOD 0x20000000U /!< Forced host mode /
Kojto	122:f9eeca106725	9298	#define USB_OTG_GUSBCFG_FDMOD 0x40000000U /!< Forced peripheral mode /
Kojto	122:f9eeca106725	9299	#define USB_OTG_GUSBCFG_CTXPKT 0x80000000U /!< Corrupt Tx packet /
Kojto	110:165afa46840b	9300
Kojto	110:165afa46840b	9301	/****************** Bit definition forUSB_OTG_GRSTCTL register ******************/
Kojto	122:f9eeca106725	9302	#define USB_OTG_GRSTCTL_CSRST 0x00000001U /!< Core soft reset /
Kojto	122:f9eeca106725	9303	#define USB_OTG_GRSTCTL_HSRST 0x00000002U /!< HCLK soft reset /
Kojto	122:f9eeca106725	9304	#define USB_OTG_GRSTCTL_FCRST 0x00000004U /!< Host frame counter reset /
Kojto	122:f9eeca106725	9305	#define USB_OTG_GRSTCTL_RXFFLSH 0x00000010U /!< RxFIFO flush /
Kojto	122:f9eeca106725	9306	#define USB_OTG_GRSTCTL_TXFFLSH 0x00000020U /!< TxFIFO flush /
Kojto	122:f9eeca106725	9307	#define USB_OTG_GRSTCTL_TXFNUM 0x000007C0U /!< TxFIFO number /
Kojto	122:f9eeca106725	9308	#define USB_OTG_GRSTCTL_TXFNUM_0 0x00000040U /!<Bit 0 /
Kojto	122:f9eeca106725	9309	#define USB_OTG_GRSTCTL_TXFNUM_1 0x00000080U /!<Bit 1 /
Kojto	122:f9eeca106725	9310	#define USB_OTG_GRSTCTL_TXFNUM_2 0x00000100U /!<Bit 2 /
Kojto	122:f9eeca106725	9311	#define USB_OTG_GRSTCTL_TXFNUM_3 0x00000200U /!<Bit 3 /
Kojto	122:f9eeca106725	9312	#define USB_OTG_GRSTCTL_TXFNUM_4 0x00000400U /!<Bit 4 /
Kojto	122:f9eeca106725	9313	#define USB_OTG_GRSTCTL_DMAREQ 0x40000000U /!< DMA request signal /
Kojto	122:f9eeca106725	9314	#define USB_OTG_GRSTCTL_AHBIDL 0x80000000U /!< AHB master idle /
Kojto	110:165afa46840b	9315
Kojto	110:165afa46840b	9316	/****************** Bit definition forUSB_OTG_DIEPMSK register ******************/
Kojto	122:f9eeca106725	9317	#define USB_OTG_DIEPMSK_XFRCM 0x00000001U /!< Transfer completed interrupt mask /
Kojto	122:f9eeca106725	9318	#define USB_OTG_DIEPMSK_EPDM 0x00000002U /!< Endpoint disabled interrupt mask /
Kojto	122:f9eeca106725	9319	#define USB_OTG_DIEPMSK_TOM 0x00000008U /!< Timeout condition mask (nonisochronous endpoints) /
Kojto	122:f9eeca106725	9320	#define USB_OTG_DIEPMSK_ITTXFEMSK 0x00000010U /!< IN token received when TxFIFO empty mask /
Kojto	122:f9eeca106725	9321	#define USB_OTG_DIEPMSK_INEPNMM 0x00000020U /!< IN token received with EP mismatch mask /
Kojto	122:f9eeca106725	9322	#define USB_OTG_DIEPMSK_INEPNEM 0x00000040U /!< IN endpoint NAK effective mask /
Kojto	122:f9eeca106725	9323	#define USB_OTG_DIEPMSK_TXFURM 0x00000100U /!< FIFO underrun mask /
Kojto	122:f9eeca106725	9324	#define USB_OTG_DIEPMSK_BIM 0x00000200U /!< BNA interrupt mask /
Kojto	110:165afa46840b	9325
Kojto	110:165afa46840b	9326	/****************** Bit definition forUSB_OTG_HPTXSTS register ******************/
Kojto	122:f9eeca106725	9327	#define USB_OTG_HPTXSTS_PTXFSAVL 0x0000FFFFU /!< Periodic transmit data FIFO space available /
Kojto	122:f9eeca106725	9328	#define USB_OTG_HPTXSTS_PTXQSAV 0x00FF0000U /!< Periodic transmit request queue space available /
Kojto	122:f9eeca106725	9329	#define USB_OTG_HPTXSTS_PTXQSAV_0 0x00010000U /!<Bit 0 /
Kojto	122:f9eeca106725	9330	#define USB_OTG_HPTXSTS_PTXQSAV_1 0x00020000U /!<Bit 1 /
Kojto	122:f9eeca106725	9331	#define USB_OTG_HPTXSTS_PTXQSAV_2 0x00040000U /!<Bit 2 /
Kojto	122:f9eeca106725	9332	#define USB_OTG_HPTXSTS_PTXQSAV_3 0x00080000U /!<Bit 3 /
Kojto	122:f9eeca106725	9333	#define USB_OTG_HPTXSTS_PTXQSAV_4 0x00100000U /!<Bit 4 /
Kojto	122:f9eeca106725	9334	#define USB_OTG_HPTXSTS_PTXQSAV_5 0x00200000U /!<Bit 5 /
Kojto	122:f9eeca106725	9335	#define USB_OTG_HPTXSTS_PTXQSAV_6 0x00400000U /!<Bit 6 /
Kojto	122:f9eeca106725	9336	#define USB_OTG_HPTXSTS_PTXQSAV_7 0x00800000U /!<Bit 7 /
Kojto	122:f9eeca106725	9337
Kojto	122:f9eeca106725	9338	#define USB_OTG_HPTXSTS_PTXQTOP 0xFF000000U /!< Top of the periodic transmit request queue /
Kojto	122:f9eeca106725	9339	#define USB_OTG_HPTXSTS_PTXQTOP_0 0x01000000U /!<Bit 0 /
Kojto	122:f9eeca106725	9340	#define USB_OTG_HPTXSTS_PTXQTOP_1 0x02000000U /!<Bit 1 /
Kojto	122:f9eeca106725	9341	#define USB_OTG_HPTXSTS_PTXQTOP_2 0x04000000U /!<Bit 2 /
Kojto	122:f9eeca106725	9342	#define USB_OTG_HPTXSTS_PTXQTOP_3 0x08000000U /!<Bit 3 /
Kojto	122:f9eeca106725	9343	#define USB_OTG_HPTXSTS_PTXQTOP_4 0x10000000U /!<Bit 4 /
Kojto	122:f9eeca106725	9344	#define USB_OTG_HPTXSTS_PTXQTOP_5 0x20000000U /!<Bit 5 /
Kojto	122:f9eeca106725	9345	#define USB_OTG_HPTXSTS_PTXQTOP_6 0x40000000U /!<Bit 6 /
Kojto	122:f9eeca106725	9346	#define USB_OTG_HPTXSTS_PTXQTOP_7 0x80000000U /!<Bit 7 /
Kojto	110:165afa46840b	9347
Kojto	110:165afa46840b	9348	/****************** Bit definition forUSB_OTG_HAINT register ******************/
Kojto	122:f9eeca106725	9349	#define USB_OTG_HAINT_HAINT 0x0000FFFFU /!< Channel interrupts /
Kojto	110:165afa46840b	9350
Kojto	110:165afa46840b	9351	/****************** Bit definition forUSB_OTG_DOEPMSK register ******************/
Kojto	122:f9eeca106725	9352	#define USB_OTG_DOEPMSK_XFRCM 0x00000001U /!< Transfer completed interrupt mask /
Kojto	122:f9eeca106725	9353	#define USB_OTG_DOEPMSK_EPDM 0x00000002U /!< Endpoint disabled interrupt mask /
Kojto	122:f9eeca106725	9354	#define USB_OTG_DOEPMSK_STUPM 0x00000008U /!< SETUP phase done mask /
Kojto	122:f9eeca106725	9355	#define USB_OTG_DOEPMSK_OTEPDM 0x00000010U /!< OUT token received when endpoint disabled mask /
Kojto	122:f9eeca106725	9356	#define USB_OTG_DOEPMSK_OTEPSPRM 0x00000020U /!< Status Phase Received mask /
Kojto	122:f9eeca106725	9357	#define USB_OTG_DOEPMSK_B2BSTUP 0x00000040U /!< Back-to-back SETUP packets received mask /
Kojto	122:f9eeca106725	9358	#define USB_OTG_DOEPMSK_OPEM 0x00000100U /!< OUT packet error mask /
Kojto	122:f9eeca106725	9359	#define USB_OTG_DOEPMSK_BOIM 0x00000200U /!< BNA interrupt mask /
Kojto	110:165afa46840b	9360
Kojto	110:165afa46840b	9361	/****************** Bit definition forUSB_OTG_GINTSTS register ******************/
Kojto	122:f9eeca106725	9362	#define USB_OTG_GINTSTS_CMOD 0x00000001U /!< Current mode of operation /
Kojto	122:f9eeca106725	9363	#define USB_OTG_GINTSTS_MMIS 0x00000002U /!< Mode mismatch interrupt /
Kojto	122:f9eeca106725	9364	#define USB_OTG_GINTSTS_OTGINT 0x00000004U /!< OTG interrupt /
Kojto	122:f9eeca106725	9365	#define USB_OTG_GINTSTS_SOF 0x00000008U /!< Start of frame /
Kojto	122:f9eeca106725	9366	#define USB_OTG_GINTSTS_RXFLVL 0x00000010U /!< RxFIFO nonempty /
Kojto	122:f9eeca106725	9367	#define USB_OTG_GINTSTS_NPTXFE 0x00000020U /!< Nonperiodic TxFIFO empty /
Kojto	122:f9eeca106725	9368	#define USB_OTG_GINTSTS_GINAKEFF 0x00000040U /!< Global IN nonperiodic NAK effective /
Kojto	122:f9eeca106725	9369	#define USB_OTG_GINTSTS_BOUTNAKEFF 0x00000080U /!< Global OUT NAK effective /
Kojto	122:f9eeca106725	9370	#define USB_OTG_GINTSTS_ESUSP 0x00000400U /!< Early suspend /
Kojto	122:f9eeca106725	9371	#define USB_OTG_GINTSTS_USBSUSP 0x00000800U /!< USB suspend /
Kojto	122:f9eeca106725	9372	#define USB_OTG_GINTSTS_USBRST 0x00001000U /!< USB reset /
Kojto	122:f9eeca106725	9373	#define USB_OTG_GINTSTS_ENUMDNE 0x00002000U /!< Enumeration done /
Kojto	122:f9eeca106725	9374	#define USB_OTG_GINTSTS_ISOODRP 0x00004000U /!< Isochronous OUT packet dropped interrupt /
Kojto	122:f9eeca106725	9375	#define USB_OTG_GINTSTS_EOPF 0x00008000U /!< End of periodic frame interrupt /
Kojto	122:f9eeca106725	9376	#define USB_OTG_GINTSTS_IEPINT 0x00040000U /!< IN endpoint interrupt /
Kojto	122:f9eeca106725	9377	#define USB_OTG_GINTSTS_OEPINT 0x00080000U /!< OUT endpoint interrupt /
Kojto	122:f9eeca106725	9378	#define USB_OTG_GINTSTS_IISOIXFR 0x00100000U /!< Incomplete isochronous IN transfer /
Kojto	122:f9eeca106725	9379	#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT 0x00200000U /!< Incomplete periodic transfer /
Kojto	122:f9eeca106725	9380	#define USB_OTG_GINTSTS_DATAFSUSP 0x00400000U /!< Data fetch suspended /
Kojto	122:f9eeca106725	9381	#define USB_OTG_GINTSTS_RSTDET 0x00800000U /!< Reset detected interrupt /
Kojto	122:f9eeca106725	9382	#define USB_OTG_GINTSTS_HPRTINT 0x01000000U /!< Host port interrupt /
Kojto	122:f9eeca106725	9383	#define USB_OTG_GINTSTS_HCINT 0x02000000U /!< Host channels interrupt /
Kojto	122:f9eeca106725	9384	#define USB_OTG_GINTSTS_PTXFE 0x04000000U /!< Periodic TxFIFO empty /
Kojto	122:f9eeca106725	9385	#define USB_OTG_GINTSTS_LPMINT 0x08000000U /!< LPM interrupt /
Kojto	122:f9eeca106725	9386	#define USB_OTG_GINTSTS_CIDSCHG 0x10000000U /!< Connector ID status change /
Kojto	122:f9eeca106725	9387	#define USB_OTG_GINTSTS_DISCINT 0x20000000U /!< Disconnect detected interrupt /
Kojto	122:f9eeca106725	9388	#define USB_OTG_GINTSTS_SRQINT 0x40000000U /!< Session request/new session detected interrupt /
Kojto	122:f9eeca106725	9389	#define USB_OTG_GINTSTS_WKUINT 0x80000000U /!< Resume/remote wakeup detected interrupt /
Kojto	110:165afa46840b	9390
Kojto	110:165afa46840b	9391	/****************** Bit definition forUSB_OTG_GINTMSK register ******************/
Kojto	122:f9eeca106725	9392	#define USB_OTG_GINTMSK_MMISM 0x00000002U /!< Mode mismatch interrupt mask /
Kojto	122:f9eeca106725	9393	#define USB_OTG_GINTMSK_OTGINT 0x00000004U /!< OTG interrupt mask /
Kojto	122:f9eeca106725	9394	#define USB_OTG_GINTMSK_SOFM 0x00000008U /!< Start of frame mask /
Kojto	122:f9eeca106725	9395	#define USB_OTG_GINTMSK_RXFLVLM 0x00000010U /!< Receive FIFO nonempty mask /
Kojto	122:f9eeca106725	9396	#define USB_OTG_GINTMSK_NPTXFEM 0x00000020U /!< Nonperiodic TxFIFO empty mask /
Kojto	122:f9eeca106725	9397	#define USB_OTG_GINTMSK_GINAKEFFM 0x00000040U /!< Global nonperiodic IN NAK effective mask /
Kojto	122:f9eeca106725	9398	#define USB_OTG_GINTMSK_GONAKEFFM 0x00000080U /!< Global OUT NAK effective mask /
Kojto	122:f9eeca106725	9399	#define USB_OTG_GINTMSK_ESUSPM 0x00000400U /!< Early suspend mask /
Kojto	122:f9eeca106725	9400	#define USB_OTG_GINTMSK_USBSUSPM 0x00000800U /!< USB suspend mask /
Kojto	122:f9eeca106725	9401	#define USB_OTG_GINTMSK_USBRST 0x00001000U /!< USB reset mask /
Kojto	122:f9eeca106725	9402	#define USB_OTG_GINTMSK_ENUMDNEM 0x00002000U /!< Enumeration done mask /
Kojto	122:f9eeca106725	9403	#define USB_OTG_GINTMSK_ISOODRPM 0x00004000U /!< Isochronous OUT packet dropped interrupt mask /
Kojto	122:f9eeca106725	9404	#define USB_OTG_GINTMSK_EOPFM 0x00008000U /!< End of periodic frame interrupt mask /
Kojto	122:f9eeca106725	9405	#define USB_OTG_GINTMSK_EPMISM 0x00020000U /!< Endpoint mismatch interrupt mask /
Kojto	122:f9eeca106725	9406	#define USB_OTG_GINTMSK_IEPINT 0x00040000U /!< IN endpoints interrupt mask /
Kojto	122:f9eeca106725	9407	#define USB_OTG_GINTMSK_OEPINT 0x00080000U /!< OUT endpoints interrupt mask /
Kojto	122:f9eeca106725	9408	#define USB_OTG_GINTMSK_IISOIXFRM 0x00100000U /!< Incomplete isochronous IN transfer mask /
Kojto	122:f9eeca106725	9409	#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM 0x00200000U /!< Incomplete periodic transfer mask /
Kojto	122:f9eeca106725	9410	#define USB_OTG_GINTMSK_FSUSPM 0x00400000U /!< Data fetch suspended mask /
Kojto	122:f9eeca106725	9411	#define USB_OTG_GINTMSK_RSTDEM 0x00800000U /!< Reset detected interrupt mask /
Kojto	122:f9eeca106725	9412	#define USB_OTG_GINTMSK_PRTIM 0x01000000U /!< Host port interrupt mask /
Kojto	122:f9eeca106725	9413	#define USB_OTG_GINTMSK_HCIM 0x02000000U /!< Host channels interrupt mask /
Kojto	122:f9eeca106725	9414	#define USB_OTG_GINTMSK_PTXFEM 0x04000000U /!< Periodic TxFIFO empty mask /
Kojto	122:f9eeca106725	9415	#define USB_OTG_GINTMSK_LPMINTM 0x08000000U /!< LPM interrupt Mask /
Kojto	122:f9eeca106725	9416	#define USB_OTG_GINTMSK_CIDSCHGM 0x10000000U /!< Connector ID status change mask /
Kojto	122:f9eeca106725	9417	#define USB_OTG_GINTMSK_DISCINT 0x20000000U /!< Disconnect detected interrupt mask /
Kojto	122:f9eeca106725	9418	#define USB_OTG_GINTMSK_SRQIM 0x40000000U /!< Session request/new session detected interrupt mask /
Kojto	122:f9eeca106725	9419	#define USB_OTG_GINTMSK_WUIM 0x80000000U /!< Resume/remote wakeup detected interrupt mask /
Kojto	110:165afa46840b	9420
Kojto	110:165afa46840b	9421	/****************** Bit definition forUSB_OTG_DAINT register ******************/
Kojto	122:f9eeca106725	9422	#define USB_OTG_DAINT_IEPINT 0x0000FFFFU /!< IN endpoint interrupt bits /
Kojto	122:f9eeca106725	9423	#define USB_OTG_DAINT_OEPINT 0xFFFF0000U /!< OUT endpoint interrupt bits /
Kojto	110:165afa46840b	9424
Kojto	110:165afa46840b	9425	/****************** Bit definition forUSB_OTG_HAINTMSK register ******************/
Kojto	122:f9eeca106725	9426	#define USB_OTG_HAINTMSK_HAINTM 0x0000FFFFU /!< Channel interrupt mask /
Kojto	110:165afa46840b	9427
Kojto	110:165afa46840b	9428	/****************** Bit definition for USB_OTG_GRXSTSP register ******************/
Kojto	122:f9eeca106725	9429	#define USB_OTG_GRXSTSP_EPNUM 0x0000000FU /!< IN EP interrupt mask bits /
Kojto	122:f9eeca106725	9430	#define USB_OTG_GRXSTSP_BCNT 0x00007FF0U /!< OUT EP interrupt mask bits /
Kojto	122:f9eeca106725	9431	#define USB_OTG_GRXSTSP_DPID 0x00018000U /!< OUT EP interrupt mask bits /
Kojto	122:f9eeca106725	9432	#define USB_OTG_GRXSTSP_PKTSTS 0x001E0000U /!< OUT EP interrupt mask bits /
Kojto	110:165afa46840b	9433
Kojto	110:165afa46840b	9434	/****************** Bit definition forUSB_OTG_DAINTMSK register ******************/
Kojto	122:f9eeca106725	9435	#define USB_OTG_DAINTMSK_IEPM 0x0000FFFFU /!< IN EP interrupt mask bits /
Kojto	122:f9eeca106725	9436	#define USB_OTG_DAINTMSK_OEPM 0xFFFF0000U /!< OUT EP interrupt mask bits /
Kojto	110:165afa46840b	9437
Kojto	110:165afa46840b	9438	/****************** Bit definition for OTG register ******************/
Kojto	110:165afa46840b	9439
Kojto	122:f9eeca106725	9440	#define USB_OTG_CHNUM 0x0000000FU /!< Channel number /
Kojto	122:f9eeca106725	9441	#define USB_OTG_CHNUM_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	9442	#define USB_OTG_CHNUM_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	9443	#define USB_OTG_CHNUM_2 0x00000004U /!<Bit 2 /
Kojto	122:f9eeca106725	9444	#define USB_OTG_CHNUM_3 0x00000008U /!<Bit 3 /
Kojto	122:f9eeca106725	9445	#define USB_OTG_BCNT 0x00007FF0U /!< Byte count /
Kojto	122:f9eeca106725	9446
Kojto	122:f9eeca106725	9447	#define USB_OTG_DPID 0x00018000U /!< Data PID /
Kojto	122:f9eeca106725	9448	#define USB_OTG_DPID_0 0x00008000U /!<Bit 0 /
Kojto	122:f9eeca106725	9449	#define USB_OTG_DPID_1 0x00010000U /!<Bit 1 /
Kojto	122:f9eeca106725	9450
Kojto	122:f9eeca106725	9451	#define USB_OTG_PKTSTS 0x001E0000U /!< Packet status /
Kojto	122:f9eeca106725	9452	#define USB_OTG_PKTSTS_0 0x00020000U /!<Bit 0 /
Kojto	122:f9eeca106725	9453	#define USB_OTG_PKTSTS_1 0x00040000U /!<Bit 1 /
Kojto	122:f9eeca106725	9454	#define USB_OTG_PKTSTS_2 0x00080000U /!<Bit 2 /
Kojto	122:f9eeca106725	9455	#define USB_OTG_PKTSTS_3 0x00100000U /!<Bit 3 /
Kojto	122:f9eeca106725	9456
Kojto	122:f9eeca106725	9457	#define USB_OTG_EPNUM 0x0000000FU /!< Endpoint number /
Kojto	122:f9eeca106725	9458	#define USB_OTG_EPNUM_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	9459	#define USB_OTG_EPNUM_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	9460	#define USB_OTG_EPNUM_2 0x00000004U /!<Bit 2 /
Kojto	122:f9eeca106725	9461	#define USB_OTG_EPNUM_3 0x00000008U /!<Bit 3 /
Kojto	122:f9eeca106725	9462
Kojto	122:f9eeca106725	9463	#define USB_OTG_FRMNUM 0x01E00000U /!< Frame number /
Kojto	122:f9eeca106725	9464	#define USB_OTG_FRMNUM_0 0x00200000U /!<Bit 0 /
Kojto	122:f9eeca106725	9465	#define USB_OTG_FRMNUM_1 0x00400000U /!<Bit 1 /
Kojto	122:f9eeca106725	9466	#define USB_OTG_FRMNUM_2 0x00800000U /!<Bit 2 /
Kojto	122:f9eeca106725	9467	#define USB_OTG_FRMNUM_3 0x01000000U /!<Bit 3 /
Kojto	110:165afa46840b	9468
Kojto	110:165afa46840b	9469	/****************** Bit definition for OTG register ******************/
Kojto	110:165afa46840b	9470
Kojto	122:f9eeca106725	9471	#define USB_OTG_CHNUM 0x0000000FU /!< Channel number /
Kojto	122:f9eeca106725	9472	#define USB_OTG_CHNUM_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	9473	#define USB_OTG_CHNUM_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	9474	#define USB_OTG_CHNUM_2 0x00000004U /!<Bit 2 /
Kojto	122:f9eeca106725	9475	#define USB_OTG_CHNUM_3 0x00000008U /!<Bit 3 /
Kojto	122:f9eeca106725	9476	#define USB_OTG_BCNT 0x00007FF0U /!< Byte count /
Kojto	122:f9eeca106725	9477
Kojto	122:f9eeca106725	9478	#define USB_OTG_DPID 0x00018000U /!< Data PID /
Kojto	122:f9eeca106725	9479	#define USB_OTG_DPID_0 0x00008000U /!<Bit 0 /
Kojto	122:f9eeca106725	9480	#define USB_OTG_DPID_1 0x00010000U /!<Bit 1 /
Kojto	122:f9eeca106725	9481
Kojto	122:f9eeca106725	9482	#define USB_OTG_PKTSTS 0x001E0000U /!< Packet status /
Kojto	122:f9eeca106725	9483	#define USB_OTG_PKTSTS_0 0x00020000U /!<Bit 0 /
Kojto	122:f9eeca106725	9484	#define USB_OTG_PKTSTS_1 0x00040000U /!<Bit 1 /
Kojto	122:f9eeca106725	9485	#define USB_OTG_PKTSTS_2 0x00080000U /!<Bit 2 /
Kojto	122:f9eeca106725	9486	#define USB_OTG_PKTSTS_3 0x00100000U /!<Bit 3 /
Kojto	122:f9eeca106725	9487
Kojto	122:f9eeca106725	9488	#define USB_OTG_EPNUM 0x0000000FU /!< Endpoint number /
Kojto	122:f9eeca106725	9489	#define USB_OTG_EPNUM_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	9490	#define USB_OTG_EPNUM_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	9491	#define USB_OTG_EPNUM_2 0x00000004U /!<Bit 2 /
Kojto	122:f9eeca106725	9492	#define USB_OTG_EPNUM_3 0x00000008U /!<Bit 3 /
Kojto	122:f9eeca106725	9493
Kojto	122:f9eeca106725	9494	#define USB_OTG_FRMNUM 0x01E00000U /!< Frame number /
Kojto	122:f9eeca106725	9495	#define USB_OTG_FRMNUM_0 0x00200000U /!<Bit 0 /
Kojto	122:f9eeca106725	9496	#define USB_OTG_FRMNUM_1 0x00400000U /!<Bit 1 /
Kojto	122:f9eeca106725	9497	#define USB_OTG_FRMNUM_2 0x00800000U /!<Bit 2 /
Kojto	122:f9eeca106725	9498	#define USB_OTG_FRMNUM_3 0x01000000U /!<Bit 3 /
Kojto	110:165afa46840b	9499
Kojto	110:165afa46840b	9500	/****************** Bit definition forUSB_OTG_GRXFSIZ register ******************/
Kojto	122:f9eeca106725	9501	#define USB_OTG_GRXFSIZ_RXFD 0x0000FFFFU /!< RxFIFO depth /
Kojto	110:165afa46840b	9502
Kojto	110:165afa46840b	9503	/****************** Bit definition forUSB_OTG_DVBUSDIS register ******************/
Kojto	122:f9eeca106725	9504	#define USB_OTG_DVBUSDIS_VBUSDT 0x0000FFFFU /!< Device VBUS discharge time /
Kojto	110:165afa46840b	9505
Kojto	110:165afa46840b	9506	/****************** Bit definition for OTG register ******************/
Kojto	122:f9eeca106725	9507	#define USB_OTG_NPTXFSA 0x0000FFFFU /!< Nonperiodic transmit RAM start address /
Kojto	122:f9eeca106725	9508	#define USB_OTG_NPTXFD 0xFFFF0000U /!< Nonperiodic TxFIFO depth /
Kojto	122:f9eeca106725	9509	#define USB_OTG_TX0FSA 0x0000FFFFU /!< Endpoint 0 transmit RAM start address /
Kojto	122:f9eeca106725	9510	#define USB_OTG_TX0FD 0xFFFF0000U /!< Endpoint 0 TxFIFO depth /
Kojto	110:165afa46840b	9511
Kojto	110:165afa46840b	9512	/****************** Bit definition forUSB_OTG_DVBUSPULSE register ******************/
Kojto	122:f9eeca106725	9513	#define USB_OTG_DVBUSPULSE_DVBUSP 0x00000FFFU /!< Device VBUS pulsing time /
Kojto	110:165afa46840b	9514
Kojto	110:165afa46840b	9515	/****************** Bit definition forUSB_OTG_GNPTXSTS register ******************/
Kojto	122:f9eeca106725	9516	#define USB_OTG_GNPTXSTS_NPTXFSAV 0x0000FFFFU /!< Nonperiodic TxFIFO space available /
Kojto	122:f9eeca106725	9517
Kojto	122:f9eeca106725	9518	#define USB_OTG_GNPTXSTS_NPTQXSAV 0x00FF0000U /!< Nonperiodic transmit request queue space available /
Kojto	122:f9eeca106725	9519	#define USB_OTG_GNPTXSTS_NPTQXSAV_0 0x00010000U /!<Bit 0 /
Kojto	122:f9eeca106725	9520	#define USB_OTG_GNPTXSTS_NPTQXSAV_1 0x00020000U /!<Bit 1 /
Kojto	122:f9eeca106725	9521	#define USB_OTG_GNPTXSTS_NPTQXSAV_2 0x00040000U /!<Bit 2 /
Kojto	122:f9eeca106725	9522	#define USB_OTG_GNPTXSTS_NPTQXSAV_3 0x00080000U /!<Bit 3 /
Kojto	122:f9eeca106725	9523	#define USB_OTG_GNPTXSTS_NPTQXSAV_4 0x00100000U /!<Bit 4 /
Kojto	122:f9eeca106725	9524	#define USB_OTG_GNPTXSTS_NPTQXSAV_5 0x00200000U /!<Bit 5 /
Kojto	122:f9eeca106725	9525	#define USB_OTG_GNPTXSTS_NPTQXSAV_6 0x00400000U /!<Bit 6 /
Kojto	122:f9eeca106725	9526	#define USB_OTG_GNPTXSTS_NPTQXSAV_7 0x00800000U /!<Bit 7 /
Kojto	122:f9eeca106725	9527
Kojto	122:f9eeca106725	9528	#define USB_OTG_GNPTXSTS_NPTXQTOP 0x7F000000U /!< Top of the nonperiodic transmit request queue /
Kojto	122:f9eeca106725	9529	#define USB_OTG_GNPTXSTS_NPTXQTOP_0 0x01000000U /!<Bit 0 /
Kojto	122:f9eeca106725	9530	#define USB_OTG_GNPTXSTS_NPTXQTOP_1 0x02000000U /!<Bit 1 /
Kojto	122:f9eeca106725	9531	#define USB_OTG_GNPTXSTS_NPTXQTOP_2 0x04000000U /!<Bit 2 /
Kojto	122:f9eeca106725	9532	#define USB_OTG_GNPTXSTS_NPTXQTOP_3 0x08000000U /!<Bit 3 /
Kojto	122:f9eeca106725	9533	#define USB_OTG_GNPTXSTS_NPTXQTOP_4 0x10000000U /!<Bit 4 /
Kojto	122:f9eeca106725	9534	#define USB_OTG_GNPTXSTS_NPTXQTOP_5 0x20000000U /!<Bit 5 /
Kojto	122:f9eeca106725	9535	#define USB_OTG_GNPTXSTS_NPTXQTOP_6 0x40000000U /!<Bit 6 /
Kojto	110:165afa46840b	9536
Kojto	110:165afa46840b	9537	/****************** Bit definition forUSB_OTG_DTHRCTL register ******************/
Kojto	122:f9eeca106725	9538	#define USB_OTG_DTHRCTL_NONISOTHREN 0x00000001U /!< Nonisochronous IN endpoints threshold enable /
Kojto	122:f9eeca106725	9539	#define USB_OTG_DTHRCTL_ISOTHREN 0x00000002U /!< ISO IN endpoint threshold enable /
Kojto	122:f9eeca106725	9540
Kojto	122:f9eeca106725	9541	#define USB_OTG_DTHRCTL_TXTHRLEN 0x000007FCU /!< Transmit threshold length /
Kojto	122:f9eeca106725	9542	#define USB_OTG_DTHRCTL_TXTHRLEN_0 0x00000004U /!<Bit 0 /
Kojto	122:f9eeca106725	9543	#define USB_OTG_DTHRCTL_TXTHRLEN_1 0x00000008U /!<Bit 1 /
Kojto	122:f9eeca106725	9544	#define USB_OTG_DTHRCTL_TXTHRLEN_2 0x00000010U /!<Bit 2 /
Kojto	122:f9eeca106725	9545	#define USB_OTG_DTHRCTL_TXTHRLEN_3 0x00000020U /!<Bit 3 /
Kojto	122:f9eeca106725	9546	#define USB_OTG_DTHRCTL_TXTHRLEN_4 0x00000040U /!<Bit 4 /
Kojto	122:f9eeca106725	9547	#define USB_OTG_DTHRCTL_TXTHRLEN_5 0x00000080U /!<Bit 5 /
Kojto	122:f9eeca106725	9548	#define USB_OTG_DTHRCTL_TXTHRLEN_6 0x00000100U /!<Bit 6 /
Kojto	122:f9eeca106725	9549	#define USB_OTG_DTHRCTL_TXTHRLEN_7 0x00000200U /!<Bit 7 /
Kojto	122:f9eeca106725	9550	#define USB_OTG_DTHRCTL_TXTHRLEN_8 0x00000400U /!<Bit 8 /
Kojto	122:f9eeca106725	9551	#define USB_OTG_DTHRCTL_RXTHREN 0x00010000U /!< Receive threshold enable /
Kojto	122:f9eeca106725	9552
Kojto	122:f9eeca106725	9553	#define USB_OTG_DTHRCTL_RXTHRLEN 0x03FE0000U /!< Receive threshold length /
Kojto	122:f9eeca106725	9554	#define USB_OTG_DTHRCTL_RXTHRLEN_0 0x00020000U /!<Bit 0 /
Kojto	122:f9eeca106725	9555	#define USB_OTG_DTHRCTL_RXTHRLEN_1 0x00040000U /!<Bit 1 /
Kojto	122:f9eeca106725	9556	#define USB_OTG_DTHRCTL_RXTHRLEN_2 0x00080000U /!<Bit 2 /
Kojto	122:f9eeca106725	9557	#define USB_OTG_DTHRCTL_RXTHRLEN_3 0x00100000U /!<Bit 3 /
Kojto	122:f9eeca106725	9558	#define USB_OTG_DTHRCTL_RXTHRLEN_4 0x00200000U /!<Bit 4 /
Kojto	122:f9eeca106725	9559	#define USB_OTG_DTHRCTL_RXTHRLEN_5 0x00400000U /!<Bit 5 /
Kojto	122:f9eeca106725	9560	#define USB_OTG_DTHRCTL_RXTHRLEN_6 0x00800000U /!<Bit 6 /
Kojto	122:f9eeca106725	9561	#define USB_OTG_DTHRCTL_RXTHRLEN_7 0x01000000U /!<Bit 7 /
Kojto	122:f9eeca106725	9562	#define USB_OTG_DTHRCTL_RXTHRLEN_8 0x02000000U /!<Bit 8 /
Kojto	122:f9eeca106725	9563	#define USB_OTG_DTHRCTL_ARPEN 0x08000000U /!< Arbiter parking enable /
Kojto	110:165afa46840b	9564
Kojto	110:165afa46840b	9565	/****************** Bit definition forUSB_OTG_DIEPEMPMSK register ******************/
Kojto	122:f9eeca106725	9566	#define USB_OTG_DIEPEMPMSK_INEPTXFEM 0x0000FFFFU /!< IN EP Tx FIFO empty interrupt mask bits /
Kojto	110:165afa46840b	9567
Kojto	110:165afa46840b	9568	/****************** Bit definition forUSB_OTG_DEACHINT register ******************/
Kojto	122:f9eeca106725	9569	#define USB_OTG_DEACHINT_IEP1INT 0x00000002U /!< IN endpoint 1interrupt bit /
Kojto	122:f9eeca106725	9570	#define USB_OTG_DEACHINT_OEP1INT 0x00020000U /!< OUT endpoint 1 interrupt bit /
Kojto	110:165afa46840b	9571
Kojto	110:165afa46840b	9572	/****************** Bit definition forUSB_OTG_GCCFG register ******************/
Kojto	122:f9eeca106725	9573	#define USB_OTG_GCCFG_PWRDWN 0x00010000U /!< Power down /
Kojto	122:f9eeca106725	9574	#define USB_OTG_GCCFG_VBDEN 0x00200000U /!< USB VBUS Detection Enable /
Kojto	110:165afa46840b	9575
Kojto	110:165afa46840b	9576	/****************** Bit definition forUSB_OTG_DEACHINTMSK register ******************/
Kojto	122:f9eeca106725	9577	#define USB_OTG_DEACHINTMSK_IEP1INTM 0x00000002U /!< IN Endpoint 1 interrupt mask bit /
Kojto	122:f9eeca106725	9578	#define USB_OTG_DEACHINTMSK_OEP1INTM 0x00020000U /!< OUT Endpoint 1 interrupt mask bit /
Kojto	110:165afa46840b	9579
Kojto	110:165afa46840b	9580	/****************** Bit definition forUSB_OTG_CID register ******************/
Kojto	122:f9eeca106725	9581	#define USB_OTG_CID_PRODUCT_ID 0xFFFFFFFFU /!< Product ID field /
Kojto	110:165afa46840b	9582
Kojto	110:165afa46840b	9583	/****************** Bit definition for USB_OTG_GLPMCFG register ******************/
Kojto	122:f9eeca106725	9584	#define USB_OTG_GLPMCFG_LPMEN 0x00000001U /!< LPM support enable /
Kojto	122:f9eeca106725	9585	#define USB_OTG_GLPMCFG_LPMACK 0x00000002U /!< LPM Token acknowledge enable /
Kojto	122:f9eeca106725	9586	#define USB_OTG_GLPMCFG_BESL 0x0000003CU /!< BESL value received with last ACKed LPM Token /
Kojto	122:f9eeca106725	9587	#define USB_OTG_GLPMCFG_REMWAKE 0x00000040U /!< bRemoteWake value received with last ACKed LPM Token /
Kojto	122:f9eeca106725	9588	#define USB_OTG_GLPMCFG_L1SSEN 0x00000080U /!< L1 shallow sleep enable /
Kojto	122:f9eeca106725	9589	#define USB_OTG_GLPMCFG_BESLTHRS 0x00000F00U /!< BESL threshold /
Kojto	122:f9eeca106725	9590	#define USB_OTG_GLPMCFG_L1DSEN 0x00001000U /!< L1 deep sleep enable /
Kojto	122:f9eeca106725	9591	#define USB_OTG_GLPMCFG_LPMRSP 0x00006000U /!< LPM response /
Kojto	122:f9eeca106725	9592	#define USB_OTG_GLPMCFG_SLPSTS 0x00008000U /!< Port sleep status /
Kojto	122:f9eeca106725	9593	#define USB_OTG_GLPMCFG_L1RSMOK 0x00010000U /!< Sleep State Resume OK /
Kojto	122:f9eeca106725	9594	#define USB_OTG_GLPMCFG_LPMCHIDX 0x001E0000U /!< LPM Channel Index /
Kojto	122:f9eeca106725	9595	#define USB_OTG_GLPMCFG_LPMRCNT 0x00E00000U /!< LPM retry count /
Kojto	122:f9eeca106725	9596	#define USB_OTG_GLPMCFG_SNDLPM 0x01000000U /!< Send LPM transaction /
Kojto	122:f9eeca106725	9597	#define USB_OTG_GLPMCFG_LPMRCNTSTS 0x0E000000U /!< LPM retry count status /
Kojto	122:f9eeca106725	9598	#define USB_OTG_GLPMCFG_ENBESL 0x10000000U /!< Enable best effort service latency /
Kojto	110:165afa46840b	9599
Kojto	110:165afa46840b	9600	/****************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ******************/
Kojto	122:f9eeca106725	9601	#define USB_OTG_DIEPEACHMSK1_XFRCM 0x00000001U /!< Transfer completed interrupt mask /
Kojto	122:f9eeca106725	9602	#define USB_OTG_DIEPEACHMSK1_EPDM 0x00000002U /!< Endpoint disabled interrupt mask /
Kojto	122:f9eeca106725	9603	#define USB_OTG_DIEPEACHMSK1_TOM 0x00000008U /!< Timeout condition mask (nonisochronous endpoints) /
Kojto	122:f9eeca106725	9604	#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK 0x00000010U /!< IN token received when TxFIFO empty mask /
Kojto	122:f9eeca106725	9605	#define USB_OTG_DIEPEACHMSK1_INEPNMM 0x00000020U /!< IN token received with EP mismatch mask /
Kojto	122:f9eeca106725	9606	#define USB_OTG_DIEPEACHMSK1_INEPNEM 0x00000040U /!< IN endpoint NAK effective mask /
Kojto	122:f9eeca106725	9607	#define USB_OTG_DIEPEACHMSK1_TXFURM 0x00000100U /!< FIFO underrun mask /
Kojto	122:f9eeca106725	9608	#define USB_OTG_DIEPEACHMSK1_BIM 0x00000200U /!< BNA interrupt mask /
Kojto	122:f9eeca106725	9609	#define USB_OTG_DIEPEACHMSK1_NAKM 0x00002000U /!< NAK interrupt mask /
Kojto	110:165afa46840b	9610
Kojto	110:165afa46840b	9611	/****************** Bit definition forUSB_OTG_HPRT register ******************/
Kojto	122:f9eeca106725	9612	#define USB_OTG_HPRT_PCSTS 0x00000001U /!< Port connect status /
Kojto	122:f9eeca106725	9613	#define USB_OTG_HPRT_PCDET 0x00000002U /!< Port connect detected /
Kojto	122:f9eeca106725	9614	#define USB_OTG_HPRT_PENA 0x00000004U /!< Port enable /
Kojto	122:f9eeca106725	9615	#define USB_OTG_HPRT_PENCHNG 0x00000008U /!< Port enable/disable change /
Kojto	122:f9eeca106725	9616	#define USB_OTG_HPRT_POCA 0x00000010U /!< Port overcurrent active /
Kojto	122:f9eeca106725	9617	#define USB_OTG_HPRT_POCCHNG 0x00000020U /!< Port overcurrent change /
Kojto	122:f9eeca106725	9618	#define USB_OTG_HPRT_PRES 0x00000040U /!< Port resume /
Kojto	122:f9eeca106725	9619	#define USB_OTG_HPRT_PSUSP 0x00000080U /!< Port suspend /
Kojto	122:f9eeca106725	9620	#define USB_OTG_HPRT_PRST 0x00000100U /!< Port reset /
Kojto	122:f9eeca106725	9621
Kojto	122:f9eeca106725	9622	#define USB_OTG_HPRT_PLSTS 0x00000C00U /!< Port line status /
Kojto	122:f9eeca106725	9623	#define USB_OTG_HPRT_PLSTS_0 0x00000400U /!<Bit 0 /
Kojto	122:f9eeca106725	9624	#define USB_OTG_HPRT_PLSTS_1 0x00000800U /!<Bit 1 /
Kojto	122:f9eeca106725	9625	#define USB_OTG_HPRT_PPWR 0x00001000U /!< Port power /
Kojto	122:f9eeca106725	9626
Kojto	122:f9eeca106725	9627	#define USB_OTG_HPRT_PTCTL 0x0001E000U /!< Port test control /
Kojto	122:f9eeca106725	9628	#define USB_OTG_HPRT_PTCTL_0 0x00002000U /!<Bit 0 /
Kojto	122:f9eeca106725	9629	#define USB_OTG_HPRT_PTCTL_1 0x00004000U /!<Bit 1 /
Kojto	122:f9eeca106725	9630	#define USB_OTG_HPRT_PTCTL_2 0x00008000U /!<Bit 2 /
Kojto	122:f9eeca106725	9631	#define USB_OTG_HPRT_PTCTL_3 0x00010000U /!<Bit 3 /
Kojto	122:f9eeca106725	9632
Kojto	122:f9eeca106725	9633	#define USB_OTG_HPRT_PSPD 0x00060000U /!< Port speed /
Kojto	122:f9eeca106725	9634	#define USB_OTG_HPRT_PSPD_0 0x00020000U /!<Bit 0 /
Kojto	122:f9eeca106725	9635	#define USB_OTG_HPRT_PSPD_1 0x00040000U /!<Bit 1 /
Kojto	110:165afa46840b	9636
Kojto	110:165afa46840b	9637	/****************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ******************/
Kojto	122:f9eeca106725	9638	#define USB_OTG_DOEPEACHMSK1_XFRCM 0x00000001U /!< Transfer completed interrupt mask /
Kojto	122:f9eeca106725	9639	#define USB_OTG_DOEPEACHMSK1_EPDM 0x00000002U /!< Endpoint disabled interrupt mask /
Kojto	122:f9eeca106725	9640	#define USB_OTG_DOEPEACHMSK1_TOM 0x00000008U /!< Timeout condition mask /
Kojto	122:f9eeca106725	9641	#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK 0x00000010U /!< IN token received when TxFIFO empty mask /
Kojto	122:f9eeca106725	9642	#define USB_OTG_DOEPEACHMSK1_INEPNMM 0x00000020U /!< IN token received with EP mismatch mask /
Kojto	122:f9eeca106725	9643	#define USB_OTG_DOEPEACHMSK1_INEPNEM 0x00000040U /!< IN endpoint NAK effective mask /
Kojto	122:f9eeca106725	9644	#define USB_OTG_DOEPEACHMSK1_TXFURM 0x00000100U /!< OUT packet error mask /
Kojto	122:f9eeca106725	9645	#define USB_OTG_DOEPEACHMSK1_BIM 0x00000200U /!< BNA interrupt mask /
Kojto	122:f9eeca106725	9646	#define USB_OTG_DOEPEACHMSK1_BERRM 0x00001000U /!< Bubble error interrupt mask /
Kojto	122:f9eeca106725	9647	#define USB_OTG_DOEPEACHMSK1_NAKM 0x00002000U /!< NAK interrupt mask /
Kojto	122:f9eeca106725	9648	#define USB_OTG_DOEPEACHMSK1_NYETM 0x00004000U /!< NYET interrupt mask /
Kojto	110:165afa46840b	9649
Kojto	110:165afa46840b	9650	/****************** Bit definition forUSB_OTG_HPTXFSIZ register ******************/
Kojto	122:f9eeca106725	9651	#define USB_OTG_HPTXFSIZ_PTXSA 0x0000FFFFU /!< Host periodic TxFIFO start address /
Kojto	122:f9eeca106725	9652	#define USB_OTG_HPTXFSIZ_PTXFD 0xFFFF0000U /!< Host periodic TxFIFO depth /
Kojto	110:165afa46840b	9653
Kojto	110:165afa46840b	9654	/****************** Bit definition forUSB_OTG_DIEPCTL register ******************/
Kojto	122:f9eeca106725	9655	#define USB_OTG_DIEPCTL_MPSIZ 0x000007FFU /!< Maximum packet size /
Kojto	122:f9eeca106725	9656	#define USB_OTG_DIEPCTL_USBAEP 0x00008000U /!< USB active endpoint /
Kojto	122:f9eeca106725	9657	#define USB_OTG_DIEPCTL_EONUM_DPID 0x00010000U /!< Even/odd frame /
Kojto	122:f9eeca106725	9658	#define USB_OTG_DIEPCTL_NAKSTS 0x00020000U /!< NAK status /
Kojto	122:f9eeca106725	9659
Kojto	122:f9eeca106725	9660	#define USB_OTG_DIEPCTL_EPTYP 0x000C0000U /!< Endpoint type /
Kojto	122:f9eeca106725	9661	#define USB_OTG_DIEPCTL_EPTYP_0 0x00040000U /!<Bit 0 /
Kojto	122:f9eeca106725	9662	#define USB_OTG_DIEPCTL_EPTYP_1 0x00080000U /!<Bit 1 /
Kojto	122:f9eeca106725	9663	#define USB_OTG_DIEPCTL_STALL 0x00200000U /!< STALL handshake /
Kojto	122:f9eeca106725	9664
Kojto	122:f9eeca106725	9665	#define USB_OTG_DIEPCTL_TXFNUM 0x03C00000U /!< TxFIFO number /
Kojto	122:f9eeca106725	9666	#define USB_OTG_DIEPCTL_TXFNUM_0 0x00400000U /!<Bit 0 /
Kojto	122:f9eeca106725	9667	#define USB_OTG_DIEPCTL_TXFNUM_1 0x00800000U /!<Bit 1 /
Kojto	122:f9eeca106725	9668	#define USB_OTG_DIEPCTL_TXFNUM_2 0x01000000U /!<Bit 2 /
Kojto	122:f9eeca106725	9669	#define USB_OTG_DIEPCTL_TXFNUM_3 0x02000000U /!<Bit 3 /
Kojto	122:f9eeca106725	9670	#define USB_OTG_DIEPCTL_CNAK 0x04000000U /!< Clear NAK /
Kojto	122:f9eeca106725	9671	#define USB_OTG_DIEPCTL_SNAK 0x08000000U /!< Set NAK /
Kojto	122:f9eeca106725	9672	#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM 0x10000000U /!< Set DATA0 PID /
Kojto	122:f9eeca106725	9673	#define USB_OTG_DIEPCTL_SODDFRM 0x20000000U /!< Set odd frame /
Kojto	122:f9eeca106725	9674	#define USB_OTG_DIEPCTL_EPDIS 0x40000000U /!< Endpoint disable /
Kojto	122:f9eeca106725	9675	#define USB_OTG_DIEPCTL_EPENA 0x80000000U /!< Endpoint enable /
Kojto	110:165afa46840b	9676
Kojto	110:165afa46840b	9677	/****************** Bit definition forUSB_OTG_HCCHAR register ******************/
Kojto	122:f9eeca106725	9678	#define USB_OTG_HCCHAR_MPSIZ 0x000007FFU /!< Maximum packet size /
Kojto	122:f9eeca106725	9679
Kojto	122:f9eeca106725	9680	#define USB_OTG_HCCHAR_EPNUM 0x00007800U /!< Endpoint number /
Kojto	122:f9eeca106725	9681	#define USB_OTG_HCCHAR_EPNUM_0 0x00000800U /!<Bit 0 /
Kojto	122:f9eeca106725	9682	#define USB_OTG_HCCHAR_EPNUM_1 0x00001000U /!<Bit 1 /
Kojto	122:f9eeca106725	9683	#define USB_OTG_HCCHAR_EPNUM_2 0x00002000U /!<Bit 2 /
Kojto	122:f9eeca106725	9684	#define USB_OTG_HCCHAR_EPNUM_3 0x00004000U /!<Bit 3 /
Kojto	122:f9eeca106725	9685	#define USB_OTG_HCCHAR_EPDIR 0x00008000U /!< Endpoint direction /
Kojto	122:f9eeca106725	9686	#define USB_OTG_HCCHAR_LSDEV 0x00020000U /!< Low-speed device /
Kojto	122:f9eeca106725	9687
Kojto	122:f9eeca106725	9688	#define USB_OTG_HCCHAR_EPTYP 0x000C0000U /!< Endpoint type /
Kojto	122:f9eeca106725	9689	#define USB_OTG_HCCHAR_EPTYP_0 0x00040000U /!<Bit 0 /
Kojto	122:f9eeca106725	9690	#define USB_OTG_HCCHAR_EPTYP_1 0x00080000U /!<Bit 1 /
Kojto	122:f9eeca106725	9691
Kojto	122:f9eeca106725	9692	#define USB_OTG_HCCHAR_MC 0x00300000U /!< Multi Count (MC) / Error Count (EC) /
Kojto	122:f9eeca106725	9693	#define USB_OTG_HCCHAR_MC_0 0x00100000U /!<Bit 0 /
Kojto	122:f9eeca106725	9694	#define USB_OTG_HCCHAR_MC_1 0x00200000U /!<Bit 1 /
Kojto	122:f9eeca106725	9695
Kojto	122:f9eeca106725	9696	#define USB_OTG_HCCHAR_DAD 0x1FC00000U /!< Device address /
Kojto	122:f9eeca106725	9697	#define USB_OTG_HCCHAR_DAD_0 0x00400000U /!<Bit 0 /
Kojto	122:f9eeca106725	9698	#define USB_OTG_HCCHAR_DAD_1 0x00800000U /!<Bit 1 /
Kojto	122:f9eeca106725	9699	#define USB_OTG_HCCHAR_DAD_2 0x01000000U /!<Bit 2 /
Kojto	122:f9eeca106725	9700	#define USB_OTG_HCCHAR_DAD_3 0x02000000U /!<Bit 3 /
Kojto	122:f9eeca106725	9701	#define USB_OTG_HCCHAR_DAD_4 0x04000000U /!<Bit 4 /
Kojto	122:f9eeca106725	9702	#define USB_OTG_HCCHAR_DAD_5 0x08000000U /!<Bit 5 /
Kojto	122:f9eeca106725	9703	#define USB_OTG_HCCHAR_DAD_6 0x10000000U /!<Bit 6 /
Kojto	122:f9eeca106725	9704	#define USB_OTG_HCCHAR_ODDFRM 0x20000000U /!< Odd frame /
Kojto	122:f9eeca106725	9705	#define USB_OTG_HCCHAR_CHDIS 0x40000000U /!< Channel disable /
Kojto	122:f9eeca106725	9706	#define USB_OTG_HCCHAR_CHENA 0x80000000U /!< Channel enable /
Kojto	110:165afa46840b	9707
Kojto	110:165afa46840b	9708	/****************** Bit definition forUSB_OTG_HCSPLT register ******************/
Kojto	110:165afa46840b	9709
Kojto	122:f9eeca106725	9710	#define USB_OTG_HCSPLT_PRTADDR 0x0000007FU /!< Port address /
Kojto	122:f9eeca106725	9711	#define USB_OTG_HCSPLT_PRTADDR_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	9712	#define USB_OTG_HCSPLT_PRTADDR_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	9713	#define USB_OTG_HCSPLT_PRTADDR_2 0x00000004U /!<Bit 2 /
Kojto	122:f9eeca106725	9714	#define USB_OTG_HCSPLT_PRTADDR_3 0x00000008U /!<Bit 3 /
Kojto	122:f9eeca106725	9715	#define USB_OTG_HCSPLT_PRTADDR_4 0x00000010U /!<Bit 4 /
Kojto	122:f9eeca106725	9716	#define USB_OTG_HCSPLT_PRTADDR_5 0x00000020U /!<Bit 5 /
Kojto	122:f9eeca106725	9717	#define USB_OTG_HCSPLT_PRTADDR_6 0x00000040U /!<Bit 6 /
Kojto	122:f9eeca106725	9718
Kojto	122:f9eeca106725	9719	#define USB_OTG_HCSPLT_HUBADDR 0x00003F80U /!< Hub address /
Kojto	122:f9eeca106725	9720	#define USB_OTG_HCSPLT_HUBADDR_0 0x00000080U /!<Bit 0 /
Kojto	122:f9eeca106725	9721	#define USB_OTG_HCSPLT_HUBADDR_1 0x00000100U /!<Bit 1 /
Kojto	122:f9eeca106725	9722	#define USB_OTG_HCSPLT_HUBADDR_2 0x00000200U /!<Bit 2 /
Kojto	122:f9eeca106725	9723	#define USB_OTG_HCSPLT_HUBADDR_3 0x00000400U /!<Bit 3 /
Kojto	122:f9eeca106725	9724	#define USB_OTG_HCSPLT_HUBADDR_4 0x00000800U /!<Bit 4 /
Kojto	122:f9eeca106725	9725	#define USB_OTG_HCSPLT_HUBADDR_5 0x00001000U /!<Bit 5 /
Kojto	122:f9eeca106725	9726	#define USB_OTG_HCSPLT_HUBADDR_6 0x00002000U /!<Bit 6 /
Kojto	122:f9eeca106725	9727
Kojto	122:f9eeca106725	9728	#define USB_OTG_HCSPLT_XACTPOS 0x0000C000U /!< XACTPOS /
Kojto	122:f9eeca106725	9729	#define USB_OTG_HCSPLT_XACTPOS_0 0x00004000U /!<Bit 0 /
Kojto	122:f9eeca106725	9730	#define USB_OTG_HCSPLT_XACTPOS_1 0x00008000U /!<Bit 1 /
Kojto	122:f9eeca106725	9731	#define USB_OTG_HCSPLT_COMPLSPLT 0x00010000U /!< Do complete split /
Kojto	122:f9eeca106725	9732	#define USB_OTG_HCSPLT_SPLITEN 0x80000000U /!< Split enable /
Kojto	110:165afa46840b	9733
Kojto	110:165afa46840b	9734	/****************** Bit definition forUSB_OTG_HCINT register ******************/
Kojto	122:f9eeca106725	9735	#define USB_OTG_HCINT_XFRC 0x00000001U /!< Transfer completed /
Kojto	122:f9eeca106725	9736	#define USB_OTG_HCINT_CHH 0x00000002U /!< Channel halted /
Kojto	122:f9eeca106725	9737	#define USB_OTG_HCINT_AHBERR 0x00000004U /!< AHB error /
Kojto	122:f9eeca106725	9738	#define USB_OTG_HCINT_STALL 0x00000008U /!< STALL response received interrupt /
Kojto	122:f9eeca106725	9739	#define USB_OTG_HCINT_NAK 0x00000010U /!< NAK response received interrupt /
Kojto	122:f9eeca106725	9740	#define USB_OTG_HCINT_ACK 0x00000020U /!< ACK response received/transmitted interrupt /
Kojto	122:f9eeca106725	9741	#define USB_OTG_HCINT_NYET 0x00000040U /!< Response received interrupt /
Kojto	122:f9eeca106725	9742	#define USB_OTG_HCINT_TXERR 0x00000080U /!< Transaction error /
Kojto	122:f9eeca106725	9743	#define USB_OTG_HCINT_BBERR 0x00000100U /!< Babble error /
Kojto	122:f9eeca106725	9744	#define USB_OTG_HCINT_FRMOR 0x00000200U /!< Frame overrun /
Kojto	122:f9eeca106725	9745	#define USB_OTG_HCINT_DTERR 0x00000400U /!< Data toggle error /
Kojto	110:165afa46840b	9746
Kojto	110:165afa46840b	9747	/****************** Bit definition forUSB_OTG_DIEPINT register ******************/
Kojto	122:f9eeca106725	9748	#define USB_OTG_DIEPINT_XFRC 0x00000001U /!< Transfer completed interrupt /
Kojto	122:f9eeca106725	9749	#define USB_OTG_DIEPINT_EPDISD 0x00000002U /!< Endpoint disabled interrupt /
Kojto	122:f9eeca106725	9750	#define USB_OTG_DIEPINT_TOC 0x00000008U /!< Timeout condition /
Kojto	122:f9eeca106725	9751	#define USB_OTG_DIEPINT_ITTXFE 0x00000010U /!< IN token received when TxFIFO is empty /
Kojto	122:f9eeca106725	9752	#define USB_OTG_DIEPINT_INEPNE 0x00000040U /!< IN endpoint NAK effective /
Kojto	122:f9eeca106725	9753	#define USB_OTG_DIEPINT_TXFE 0x00000080U /!< Transmit FIFO empty /
Kojto	122:f9eeca106725	9754	#define USB_OTG_DIEPINT_TXFIFOUDRN 0x00000100U /!< Transmit Fifo Underrun /
Kojto	122:f9eeca106725	9755	#define USB_OTG_DIEPINT_BNA 0x00000200U /!< Buffer not available interrupt /
Kojto	122:f9eeca106725	9756	#define USB_OTG_DIEPINT_PKTDRPSTS 0x00000800U /!< Packet dropped status /
Kojto	122:f9eeca106725	9757	#define USB_OTG_DIEPINT_BERR 0x00001000U /!< Babble error interrupt /
Kojto	122:f9eeca106725	9758	#define USB_OTG_DIEPINT_NAK 0x00002000U /!< NAK interrupt /
Kojto	110:165afa46840b	9759
Kojto	110:165afa46840b	9760	/****************** Bit definition forUSB_OTG_HCINTMSK register ******************/
Kojto	122:f9eeca106725	9761	#define USB_OTG_HCINTMSK_XFRCM 0x00000001U /!< Transfer completed mask /
Kojto	122:f9eeca106725	9762	#define USB_OTG_HCINTMSK_CHHM 0x00000002U /!< Channel halted mask /
Kojto	122:f9eeca106725	9763	#define USB_OTG_HCINTMSK_AHBERR 0x00000004U /!< AHB error /
Kojto	122:f9eeca106725	9764	#define USB_OTG_HCINTMSK_STALLM 0x00000008U /!< STALL response received interrupt mask /
Kojto	122:f9eeca106725	9765	#define USB_OTG_HCINTMSK_NAKM 0x00000010U /!< NAK response received interrupt mask /
Kojto	122:f9eeca106725	9766	#define USB_OTG_HCINTMSK_ACKM 0x00000020U /!< ACK response received/transmitted interrupt mask /
Kojto	122:f9eeca106725	9767	#define USB_OTG_HCINTMSK_NYET 0x00000040U /!< response received interrupt mask /
Kojto	122:f9eeca106725	9768	#define USB_OTG_HCINTMSK_TXERRM 0x00000080U /!< Transaction error mask /
Kojto	122:f9eeca106725	9769	#define USB_OTG_HCINTMSK_BBERRM 0x00000100U /!< Babble error mask /
Kojto	122:f9eeca106725	9770	#define USB_OTG_HCINTMSK_FRMORM 0x00000200U /!< Frame overrun mask /
Kojto	122:f9eeca106725	9771	#define USB_OTG_HCINTMSK_DTERRM 0x00000400U /!< Data toggle error mask /
Kojto	110:165afa46840b	9772
Kojto	110:165afa46840b	9773	/****************** Bit definition for USB_OTG_DIEPTSIZ register ******************/
Kojto	110:165afa46840b	9774
Kojto	122:f9eeca106725	9775	#define USB_OTG_DIEPTSIZ_XFRSIZ 0x0007FFFFU /!< Transfer size /
Kojto	122:f9eeca106725	9776	#define USB_OTG_DIEPTSIZ_PKTCNT 0x1FF80000U /!< Packet count /
Kojto	122:f9eeca106725	9777	#define USB_OTG_DIEPTSIZ_MULCNT 0x60000000U /!< Packet count /
Kojto	110:165afa46840b	9778	/****************** Bit definition forUSB_OTG_HCTSIZ register ******************/
Kojto	122:f9eeca106725	9779	#define USB_OTG_HCTSIZ_XFRSIZ 0x0007FFFFU /!< Transfer size /
Kojto	122:f9eeca106725	9780	#define USB_OTG_HCTSIZ_PKTCNT 0x1FF80000U /!< Packet count /
Kojto	122:f9eeca106725	9781	#define USB_OTG_HCTSIZ_DOPING 0x80000000U /!< Do PING /
Kojto	122:f9eeca106725	9782	#define USB_OTG_HCTSIZ_DPID 0x60000000U /!< Data PID /
Kojto	122:f9eeca106725	9783	#define USB_OTG_HCTSIZ_DPID_0 0x20000000U /!<Bit 0 /
Kojto	122:f9eeca106725	9784	#define USB_OTG_HCTSIZ_DPID_1 0x40000000U /!<Bit 1 /
Kojto	110:165afa46840b	9785
Kojto	110:165afa46840b	9786	/****************** Bit definition forUSB_OTG_DIEPDMA register ******************/
Kojto	122:f9eeca106725	9787	#define USB_OTG_DIEPDMA_DMAADDR 0xFFFFFFFFU /!< DMA address /
Kojto	110:165afa46840b	9788
Kojto	110:165afa46840b	9789	/****************** Bit definition forUSB_OTG_HCDMA register ******************/
Kojto	122:f9eeca106725	9790	#define USB_OTG_HCDMA_DMAADDR 0xFFFFFFFFU /!< DMA address /
Kojto	110:165afa46840b	9791
Kojto	110:165afa46840b	9792	/****************** Bit definition forUSB_OTG_DTXFSTS register ******************/
Kojto	122:f9eeca106725	9793	#define USB_OTG_DTXFSTS_INEPTFSAV 0x0000FFFFU /!< IN endpoint TxFIFO space available /
Kojto	110:165afa46840b	9794
Kojto	110:165afa46840b	9795	/****************** Bit definition forUSB_OTG_DIEPTXF register ******************/
Kojto	122:f9eeca106725	9796	#define USB_OTG_DIEPTXF_INEPTXSA 0x0000FFFFU /!< IN endpoint FIFOx transmit RAM start address /
Kojto	122:f9eeca106725	9797	#define USB_OTG_DIEPTXF_INEPTXFD 0xFFFF0000U /!< IN endpoint TxFIFO depth /
Kojto	110:165afa46840b	9798
Kojto	110:165afa46840b	9799	/****************** Bit definition forUSB_OTG_DOEPCTL register ******************/
Kojto	110:165afa46840b	9800
Kojto	122:f9eeca106725	9801	#define USB_OTG_DOEPCTL_MPSIZ 0x000007FFU /!< Maximum packet size / /!<Bit 1 /
Kojto	122:f9eeca106725	9802	#define USB_OTG_DOEPCTL_USBAEP 0x00008000U /!< USB active endpoint /
Kojto	122:f9eeca106725	9803	#define USB_OTG_DOEPCTL_NAKSTS 0x00020000U /!< NAK status /
Kojto	122:f9eeca106725	9804	#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM 0x10000000U /!< Set DATA0 PID /
Kojto	122:f9eeca106725	9805	#define USB_OTG_DOEPCTL_SODDFRM 0x20000000U /!< Set odd frame /
Kojto	122:f9eeca106725	9806	#define USB_OTG_DOEPCTL_EPTYP 0x000C0000U /!< Endpoint type /
Kojto	122:f9eeca106725	9807	#define USB_OTG_DOEPCTL_EPTYP_0 0x00040000U /!<Bit 0 /
Kojto	122:f9eeca106725	9808	#define USB_OTG_DOEPCTL_EPTYP_1 0x00080000U /!<Bit 1 /
Kojto	122:f9eeca106725	9809	#define USB_OTG_DOEPCTL_SNPM 0x00100000U /!< Snoop mode /
Kojto	122:f9eeca106725	9810	#define USB_OTG_DOEPCTL_STALL 0x00200000U /!< STALL handshake /
Kojto	122:f9eeca106725	9811	#define USB_OTG_DOEPCTL_CNAK 0x04000000U /!< Clear NAK /
Kojto	122:f9eeca106725	9812	#define USB_OTG_DOEPCTL_SNAK 0x08000000U /!< Set NAK /
Kojto	122:f9eeca106725	9813	#define USB_OTG_DOEPCTL_EPDIS 0x40000000U /!< Endpoint disable /
Kojto	122:f9eeca106725	9814	#define USB_OTG_DOEPCTL_EPENA 0x80000000U /!< Endpoint enable /
Kojto	110:165afa46840b	9815
Kojto	110:165afa46840b	9816	/****************** Bit definition forUSB_OTG_DOEPINT register ******************/
Kojto	122:f9eeca106725	9817	#define USB_OTG_DOEPINT_XFRC 0x00000001U /!< Transfer completed interrupt /
Kojto	122:f9eeca106725	9818	#define USB_OTG_DOEPINT_EPDISD 0x00000002U /!< Endpoint disabled interrupt /
Kojto	122:f9eeca106725	9819	#define USB_OTG_DOEPINT_STUP 0x00000008U /!< SETUP phase done /
Kojto	122:f9eeca106725	9820	#define USB_OTG_DOEPINT_OTEPDIS 0x00000010U /!< OUT token received when endpoint disabled /
Kojto	122:f9eeca106725	9821	#define USB_OTG_DOEPINT_OTEPSPR 0x00000020U /!< Status Phase Received For Control Write /
Kojto	122:f9eeca106725	9822	#define USB_OTG_DOEPINT_B2BSTUP 0x00000040U /!< Back-to-back SETUP packets received /
Kojto	122:f9eeca106725	9823	#define USB_OTG_DOEPINT_NYET 0x00004000U /!< NYET interrupt /
Kojto	110:165afa46840b	9824
Kojto	110:165afa46840b	9825	/****************** Bit definition forUSB_OTG_DOEPTSIZ register ******************/
Kojto	110:165afa46840b	9826
Kojto	122:f9eeca106725	9827	#define USB_OTG_DOEPTSIZ_XFRSIZ 0x0007FFFFU /!< Transfer size /
Kojto	122:f9eeca106725	9828	#define USB_OTG_DOEPTSIZ_PKTCNT 0x1FF80000U /!< Packet count /
Kojto	122:f9eeca106725	9829
Kojto	122:f9eeca106725	9830	#define USB_OTG_DOEPTSIZ_STUPCNT 0x60000000U /!< SETUP packet count /
Kojto	122:f9eeca106725	9831	#define USB_OTG_DOEPTSIZ_STUPCNT_0 0x20000000U /!<Bit 0 /
Kojto	122:f9eeca106725	9832	#define USB_OTG_DOEPTSIZ_STUPCNT_1 0x40000000U /!<Bit 1 /
Kojto	110:165afa46840b	9833
Kojto	110:165afa46840b	9834	/****************** Bit definition for PCGCCTL register ******************/
Kojto	122:f9eeca106725	9835	#define USB_OTG_PCGCCTL_STOPCLK 0x00000001U /!< SETUP packet count /
Kojto	122:f9eeca106725	9836	#define USB_OTG_PCGCCTL_GATECLK 0x00000002U /!<Bit 0 /
Kojto	122:f9eeca106725	9837	#define USB_OTG_PCGCCTL_PHYSUSP 0x00000010U /!<Bit 1 /
Kojto	110:165afa46840b	9838
Kojto	110:165afa46840b	9839
Kojto	110:165afa46840b	9840	/**
Kojto	110:165afa46840b	9841	* @}
Kojto	110:165afa46840b	9842	*/
Kojto	110:165afa46840b	9843
Kojto	110:165afa46840b	9844	/**
Kojto	110:165afa46840b	9845	* @}
Kojto	110:165afa46840b	9846	*/
Kojto	110:165afa46840b	9847
Kojto	110:165afa46840b	9848	/** @addtogroup Exported_macros
Kojto	110:165afa46840b	9849	* @{
Kojto	110:165afa46840b	9850	*/
Kojto	110:165afa46840b	9851
Kojto	110:165afa46840b	9852	/***************************** ADC Instances ******************************/
Kojto	110:165afa46840b	9853	#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) \|\| \
Kojto	110:165afa46840b	9854	((INSTANCE) == ADC2) \|\| \
Kojto	110:165afa46840b	9855	((INSTANCE) == ADC3))
Kojto	110:165afa46840b	9856
Kojto	110:165afa46840b	9857	/***************************** CAN Instances ******************************/
Kojto	110:165afa46840b	9858	#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) \|\| \
Kojto	110:165afa46840b	9859	((INSTANCE) == CAN2))
Kojto	110:165afa46840b	9860
Kojto	110:165afa46840b	9861	/***************************** CRC Instances ******************************/
Kojto	110:165afa46840b	9862	#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
Kojto	110:165afa46840b	9863
Kojto	110:165afa46840b	9864	/***************************** DAC Instances ******************************/
Kojto	110:165afa46840b	9865	#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
Kojto	110:165afa46840b	9866
Kojto	110:165afa46840b	9867	/***************************** DCMI Instances *****************************/
Kojto	110:165afa46840b	9868	#define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
Kojto	110:165afa46840b	9869
Kojto	110:165afa46840b	9870	/***************************** DMA2D Instances *****************************/
Kojto	110:165afa46840b	9871	#define IS_DMA2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA2D)
Kojto	110:165afa46840b	9872
Kojto	110:165afa46840b	9873	/****************************** DMA Instances *****************************/
Kojto	110:165afa46840b	9874	#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) \|\| \
Kojto	110:165afa46840b	9875	((INSTANCE) == DMA1_Stream1) \|\| \
Kojto	110:165afa46840b	9876	((INSTANCE) == DMA1_Stream2) \|\| \
Kojto	110:165afa46840b	9877	((INSTANCE) == DMA1_Stream3) \|\| \
Kojto	110:165afa46840b	9878	((INSTANCE) == DMA1_Stream4) \|\| \
Kojto	110:165afa46840b	9879	((INSTANCE) == DMA1_Stream5) \|\| \
Kojto	110:165afa46840b	9880	((INSTANCE) == DMA1_Stream6) \|\| \
Kojto	110:165afa46840b	9881	((INSTANCE) == DMA1_Stream7) \|\| \
Kojto	110:165afa46840b	9882	((INSTANCE) == DMA2_Stream0) \|\| \
Kojto	110:165afa46840b	9883	((INSTANCE) == DMA2_Stream1) \|\| \
Kojto	110:165afa46840b	9884	((INSTANCE) == DMA2_Stream2) \|\| \
Kojto	110:165afa46840b	9885	((INSTANCE) == DMA2_Stream3) \|\| \
Kojto	110:165afa46840b	9886	((INSTANCE) == DMA2_Stream4) \|\| \
Kojto	110:165afa46840b	9887	((INSTANCE) == DMA2_Stream5) \|\| \
Kojto	110:165afa46840b	9888	((INSTANCE) == DMA2_Stream6) \|\| \
Kojto	110:165afa46840b	9889	((INSTANCE) == DMA2_Stream7))
Kojto	110:165afa46840b	9890
Kojto	110:165afa46840b	9891	/***************************** GPIO Instances *****************************/
Kojto	110:165afa46840b	9892	#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) \|\| \
Kojto	110:165afa46840b	9893	((INSTANCE) == GPIOB) \|\| \
Kojto	110:165afa46840b	9894	((INSTANCE) == GPIOC) \|\| \
Kojto	110:165afa46840b	9895	((INSTANCE) == GPIOD) \|\| \
Kojto	110:165afa46840b	9896	((INSTANCE) == GPIOE) \|\| \
Kojto	110:165afa46840b	9897	((INSTANCE) == GPIOF) \|\| \
Kojto	110:165afa46840b	9898	((INSTANCE) == GPIOG) \|\| \
Kojto	110:165afa46840b	9899	((INSTANCE) == GPIOH) \|\| \
Kojto	110:165afa46840b	9900	((INSTANCE) == GPIOI) \|\| \
Kojto	110:165afa46840b	9901	((INSTANCE) == GPIOJ) \|\| \
Kojto	110:165afa46840b	9902	((INSTANCE) == GPIOK))
Kojto	110:165afa46840b	9903
Kojto	110:165afa46840b	9904	/****************************** I2C Instances *****************************/
Kojto	110:165afa46840b	9905	#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) \|\| \
Kojto	110:165afa46840b	9906	((INSTANCE) == I2C2) \|\| \
Kojto	110:165afa46840b	9907	((INSTANCE) == I2C3))
Kojto	110:165afa46840b	9908
Kojto	110:165afa46840b	9909	/****************************** I2S Instances *****************************/
Kojto	110:165afa46840b	9910	#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) \|\| \
Kojto	110:165afa46840b	9911	((INSTANCE) == SPI3))
Kojto	110:165afa46840b	9912
Kojto	110:165afa46840b	9913	/************************* I2S Extended Instances *************************/
Kojto	110:165afa46840b	9914	#define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) \|\| \
Kojto	110:165afa46840b	9915	((INSTANCE) == SPI3) \|\| \
Kojto	110:165afa46840b	9916	((INSTANCE) == I2S2ext) \|\| \
Kojto	110:165afa46840b	9917	((INSTANCE) == I2S3ext))
Kojto	110:165afa46840b	9918
Kojto	110:165afa46840b	9919	/**************************** LTDC Instances ******************************/
Kojto	110:165afa46840b	9920	#define IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC)
Kojto	110:165afa46840b	9921
Kojto	110:165afa46840b	9922	/***************************** RNG Instances ******************************/
Kojto	110:165afa46840b	9923	#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
Kojto	110:165afa46840b	9924
Kojto	110:165afa46840b	9925	/**************************** RTC Instances *******************************/
Kojto	110:165afa46840b	9926	#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
Kojto	110:165afa46840b	9927
Kojto	110:165afa46840b	9928	/***************************** SAI Instances ******************************/
Kojto	122:f9eeca106725	9929	#define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A) \|\| \
Kojto	110:165afa46840b	9930	((PERIPH) == SAI1_Block_B))
Kojto	122:f9eeca106725	9931	/* Legacy define */
Kojto	122:f9eeca106725	9932	#define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
Kojto	110:165afa46840b	9933
Kojto	110:165afa46840b	9934	/****************************** SPI Instances *****************************/
Kojto	110:165afa46840b	9935	#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) \|\| \
Kojto	110:165afa46840b	9936	((INSTANCE) == SPI2) \|\| \
Kojto	110:165afa46840b	9937	((INSTANCE) == SPI3) \|\| \
Kojto	110:165afa46840b	9938	((INSTANCE) == SPI4) \|\| \
Kojto	110:165afa46840b	9939	((INSTANCE) == SPI5) \|\| \
Kojto	110:165afa46840b	9940	((INSTANCE) == SPI6))
Kojto	110:165afa46840b	9941
Kojto	110:165afa46840b	9942	/************************* SPI Extended Instances *************************/
Kojto	110:165afa46840b	9943	#define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) \|\| \
Kojto	110:165afa46840b	9944	((INSTANCE) == SPI2) \|\| \
Kojto	110:165afa46840b	9945	((INSTANCE) == SPI3) \|\| \
Kojto	110:165afa46840b	9946	((INSTANCE) == SPI4) \|\| \
Kojto	110:165afa46840b	9947	((INSTANCE) == SPI5) \|\| \
Kojto	110:165afa46840b	9948	((INSTANCE) == SPI6) \|\| \
Kojto	110:165afa46840b	9949	((INSTANCE) == I2S2ext) \|\| \
Kojto	110:165afa46840b	9950	((INSTANCE) == I2S3ext))
Kojto	110:165afa46840b	9951
Kojto	110:165afa46840b	9952	/**************** TIM Instances : All supported instances *****************/
Kojto	110:165afa46840b	9953	#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
Kojto	110:165afa46840b	9954	((INSTANCE) == TIM2) \|\| \
Kojto	110:165afa46840b	9955	((INSTANCE) == TIM3) \|\| \
Kojto	110:165afa46840b	9956	((INSTANCE) == TIM4) \|\| \
Kojto	110:165afa46840b	9957	((INSTANCE) == TIM5) \|\| \
Kojto	110:165afa46840b	9958	((INSTANCE) == TIM6) \|\| \
Kojto	110:165afa46840b	9959	((INSTANCE) == TIM7) \|\| \
Kojto	110:165afa46840b	9960	((INSTANCE) == TIM8) \|\| \
Kojto	110:165afa46840b	9961	((INSTANCE) == TIM9) \|\| \
Kojto	110:165afa46840b	9962	((INSTANCE) == TIM10) \|\| \
Kojto	110:165afa46840b	9963	((INSTANCE) == TIM11) \|\| \
Kojto	110:165afa46840b	9964	((INSTANCE) == TIM12) \|\| \
Kojto	110:165afa46840b	9965	((INSTANCE) == TIM13) \|\| \
Kojto	110:165afa46840b	9966	((INSTANCE) == TIM14))
Kojto	110:165afa46840b	9967
Kojto	110:165afa46840b	9968	/*********** TIM Instances : at least 1 capture/compare channel ***********/
Kojto	110:165afa46840b	9969	#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
Kojto	110:165afa46840b	9970	((INSTANCE) == TIM2) \|\| \
Kojto	110:165afa46840b	9971	((INSTANCE) == TIM3) \|\| \
Kojto	110:165afa46840b	9972	((INSTANCE) == TIM4) \|\| \
Kojto	110:165afa46840b	9973	((INSTANCE) == TIM5) \|\| \
Kojto	110:165afa46840b	9974	((INSTANCE) == TIM8) \|\| \
Kojto	110:165afa46840b	9975	((INSTANCE) == TIM9) \|\| \
Kojto	110:165afa46840b	9976	((INSTANCE) == TIM10) \|\| \
Kojto	110:165afa46840b	9977	((INSTANCE) == TIM11) \|\| \
Kojto	110:165afa46840b	9978	((INSTANCE) == TIM12) \|\| \
Kojto	110:165afa46840b	9979	((INSTANCE) == TIM13) \|\| \
Kojto	110:165afa46840b	9980	((INSTANCE) == TIM14))
Kojto	110:165afa46840b	9981
Kojto	110:165afa46840b	9982	/********** TIM Instances : at least 2 capture/compare channels ***********/
Kojto	110:165afa46840b	9983	#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
Kojto	110:165afa46840b	9984	((INSTANCE) == TIM2) \|\| \
Kojto	110:165afa46840b	9985	((INSTANCE) == TIM3) \|\| \
Kojto	110:165afa46840b	9986	((INSTANCE) == TIM4) \|\| \
Kojto	110:165afa46840b	9987	((INSTANCE) == TIM5) \|\| \
Kojto	110:165afa46840b	9988	((INSTANCE) == TIM8) \|\| \
Kojto	110:165afa46840b	9989	((INSTANCE) == TIM9) \|\| \
Kojto	110:165afa46840b	9990	((INSTANCE) == TIM12))
Kojto	110:165afa46840b	9991
Kojto	110:165afa46840b	9992	/********** TIM Instances : at least 3 capture/compare channels ***********/
Kojto	110:165afa46840b	9993	#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
Kojto	110:165afa46840b	9994	((INSTANCE) == TIM2) \|\| \
Kojto	110:165afa46840b	9995	((INSTANCE) == TIM3) \|\| \
Kojto	110:165afa46840b	9996	((INSTANCE) == TIM4) \|\| \
Kojto	110:165afa46840b	9997	((INSTANCE) == TIM5) \|\| \
Kojto	110:165afa46840b	9998	((INSTANCE) == TIM8))
Kojto	110:165afa46840b	9999
Kojto	110:165afa46840b	10000	/********** TIM Instances : at least 4 capture/compare channels ***********/
Kojto	110:165afa46840b	10001	#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
Kojto	110:165afa46840b	10002	((INSTANCE) == TIM2) \|\| \
Kojto	110:165afa46840b	10003	((INSTANCE) == TIM3) \|\| \
Kojto	110:165afa46840b	10004	((INSTANCE) == TIM4) \|\| \
Kojto	110:165afa46840b	10005	((INSTANCE) == TIM5) \|\| \
Kojto	110:165afa46840b	10006	((INSTANCE) == TIM8))
Kojto	110:165afa46840b	10007
Kojto	110:165afa46840b	10008	/****************** TIM Instances : Advanced-control timers ***************/
Kojto	110:165afa46840b	10009	#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
Kojto	110:165afa46840b	10010	((INSTANCE) == TIM8))
Kojto	110:165afa46840b	10011
Kojto	110:165afa46840b	10012	/***************** TIM Instances : Timer input XOR function ***************/
Kojto	110:165afa46840b	10013	#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
Kojto	110:165afa46840b	10014	((INSTANCE) == TIM2) \|\| \
Kojto	110:165afa46840b	10015	((INSTANCE) == TIM3) \|\| \
Kojto	110:165afa46840b	10016	((INSTANCE) == TIM4) \|\| \
Kojto	110:165afa46840b	10017	((INSTANCE) == TIM5) \|\| \
Kojto	110:165afa46840b	10018	((INSTANCE) == TIM8))
Kojto	110:165afa46840b	10019
Kojto	110:165afa46840b	10020	/**************** TIM Instances : DMA requests generation (UDE) ***********/
Kojto	110:165afa46840b	10021	#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
Kojto	110:165afa46840b	10022	((INSTANCE) == TIM2) \|\| \
Kojto	110:165afa46840b	10023	((INSTANCE) == TIM3) \|\| \
Kojto	110:165afa46840b	10024	((INSTANCE) == TIM4) \|\| \
Kojto	110:165afa46840b	10025	((INSTANCE) == TIM5) \|\| \
Kojto	110:165afa46840b	10026	((INSTANCE) == TIM6) \|\| \
Kojto	110:165afa46840b	10027	((INSTANCE) == TIM7) \|\| \
Kojto	110:165afa46840b	10028	((INSTANCE) == TIM8))
Kojto	110:165afa46840b	10029
Kojto	110:165afa46840b	10030	/********** TIM Instances : DMA requests generation (CCxDE) ***************/
Kojto	110:165afa46840b	10031	#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
Kojto	110:165afa46840b	10032	((INSTANCE) == TIM2) \|\| \
Kojto	110:165afa46840b	10033	((INSTANCE) == TIM3) \|\| \
Kojto	110:165afa46840b	10034	((INSTANCE) == TIM4) \|\| \
Kojto	110:165afa46840b	10035	((INSTANCE) == TIM5) \|\| \
Kojto	110:165afa46840b	10036	((INSTANCE) == TIM8))
Kojto	110:165afa46840b	10037
Kojto	110:165afa46840b	10038	/********** TIM Instances : DMA requests generation (COMDE) ***************/
Kojto	110:165afa46840b	10039	#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
Kojto	110:165afa46840b	10040	((INSTANCE) == TIM2) \|\| \
Kojto	110:165afa46840b	10041	((INSTANCE) == TIM3) \|\| \
Kojto	110:165afa46840b	10042	((INSTANCE) == TIM4) \|\| \
Kojto	110:165afa46840b	10043	((INSTANCE) == TIM5) \|\| \
Kojto	110:165afa46840b	10044	((INSTANCE) == TIM8))
Kojto	110:165afa46840b	10045
Kojto	110:165afa46840b	10046	/****************** TIM Instances : DMA burst feature *********************/
Kojto	110:165afa46840b	10047	#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
Kojto	110:165afa46840b	10048	((INSTANCE) == TIM2) \|\| \
Kojto	110:165afa46840b	10049	((INSTANCE) == TIM3) \|\| \
Kojto	110:165afa46840b	10050	((INSTANCE) == TIM4) \|\| \
Kojto	110:165afa46840b	10051	((INSTANCE) == TIM5) \|\| \
Kojto	110:165afa46840b	10052	((INSTANCE) == TIM8))
Kojto	110:165afa46840b	10053
Kojto	110:165afa46840b	10054	/**** TIM Instances : master mode available (TIMx_CR2.MMS available )******/
Kojto	110:165afa46840b	10055	#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
Kojto	110:165afa46840b	10056	((INSTANCE) == TIM2) \|\| \
Kojto	110:165afa46840b	10057	((INSTANCE) == TIM3) \|\| \
Kojto	110:165afa46840b	10058	((INSTANCE) == TIM4) \|\| \
Kojto	110:165afa46840b	10059	((INSTANCE) == TIM5) \|\| \
Kojto	110:165afa46840b	10060	((INSTANCE) == TIM6) \|\| \
Kojto	110:165afa46840b	10061	((INSTANCE) == TIM7) \|\| \
Kojto	110:165afa46840b	10062	((INSTANCE) == TIM8) \|\| \
Kojto	110:165afa46840b	10063	((INSTANCE) == TIM9) \|\| \
Kojto	110:165afa46840b	10064	((INSTANCE) == TIM12))
Kojto	110:165afa46840b	10065
Kojto	110:165afa46840b	10066	/********* TIM Instances : Slave mode available (TIMx_SMCR available )*****/
Kojto	110:165afa46840b	10067	#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
Kojto	110:165afa46840b	10068	((INSTANCE) == TIM2) \|\| \
Kojto	110:165afa46840b	10069	((INSTANCE) == TIM3) \|\| \
Kojto	110:165afa46840b	10070	((INSTANCE) == TIM4) \|\| \
Kojto	110:165afa46840b	10071	((INSTANCE) == TIM5) \|\| \
Kojto	110:165afa46840b	10072	((INSTANCE) == TIM8) \|\| \
Kojto	110:165afa46840b	10073	((INSTANCE) == TIM9) \|\| \
Kojto	110:165afa46840b	10074	((INSTANCE) == TIM12))
Kojto	110:165afa46840b	10075
Kojto	110:165afa46840b	10076	/******************** TIM Instances : 32 bit Counter **********************/
Kojto	110:165afa46840b	10077	#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) \|\| \
Kojto	110:165afa46840b	10078	((INSTANCE) == TIM5))
Kojto	110:165afa46840b	10079
Kojto	110:165afa46840b	10080	/*************** TIM Instances : external trigger input availabe **********/
Kojto	110:165afa46840b	10081	#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
Kojto	110:165afa46840b	10082	((INSTANCE) == TIM2) \|\| \
Kojto	110:165afa46840b	10083	((INSTANCE) == TIM3) \|\| \
Kojto	110:165afa46840b	10084	((INSTANCE) == TIM4) \|\| \
Kojto	110:165afa46840b	10085	((INSTANCE) == TIM5) \|\| \
Kojto	110:165afa46840b	10086	((INSTANCE) == TIM8))
Kojto	110:165afa46840b	10087
Kojto	110:165afa46840b	10088	/**************** TIM Instances : remapping capability ********************/
Kojto	110:165afa46840b	10089	#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
Kojto	110:165afa46840b	10090	((INSTANCE) == TIM5) \|\| \
Kojto	110:165afa46840b	10091	((INSTANCE) == TIM11))
Kojto	110:165afa46840b	10092
Kojto	110:165afa46840b	10093	/***************** TIM Instances : output(s) available ********************/
Kojto	110:165afa46840b	10094	#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
Kojto	110:165afa46840b	10095	((((INSTANCE) == TIM1) && \
Kojto	110:165afa46840b	10096	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
Kojto	110:165afa46840b	10097	((CHANNEL) == TIM_CHANNEL_2) \|\| \
Kojto	110:165afa46840b	10098	((CHANNEL) == TIM_CHANNEL_3) \|\| \
Kojto	110:165afa46840b	10099	((CHANNEL) == TIM_CHANNEL_4))) \
Kojto	110:165afa46840b	10100	\|\| \
Kojto	110:165afa46840b	10101	(((INSTANCE) == TIM2) && \
Kojto	110:165afa46840b	10102	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
Kojto	110:165afa46840b	10103	((CHANNEL) == TIM_CHANNEL_2) \|\| \
Kojto	110:165afa46840b	10104	((CHANNEL) == TIM_CHANNEL_3) \|\| \
Kojto	110:165afa46840b	10105	((CHANNEL) == TIM_CHANNEL_4))) \
Kojto	110:165afa46840b	10106	\|\| \
Kojto	110:165afa46840b	10107	(((INSTANCE) == TIM3) && \
Kojto	110:165afa46840b	10108	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
Kojto	110:165afa46840b	10109	((CHANNEL) == TIM_CHANNEL_2) \|\| \
Kojto	110:165afa46840b	10110	((CHANNEL) == TIM_CHANNEL_3) \|\| \
Kojto	110:165afa46840b	10111	((CHANNEL) == TIM_CHANNEL_4))) \
Kojto	110:165afa46840b	10112	\|\| \
Kojto	110:165afa46840b	10113	(((INSTANCE) == TIM4) && \
Kojto	110:165afa46840b	10114	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
Kojto	110:165afa46840b	10115	((CHANNEL) == TIM_CHANNEL_2) \|\| \
Kojto	110:165afa46840b	10116	((CHANNEL) == TIM_CHANNEL_3) \|\| \
Kojto	110:165afa46840b	10117	((CHANNEL) == TIM_CHANNEL_4))) \
Kojto	110:165afa46840b	10118	\|\| \
Kojto	110:165afa46840b	10119	(((INSTANCE) == TIM5) && \
Kojto	110:165afa46840b	10120	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
Kojto	110:165afa46840b	10121	((CHANNEL) == TIM_CHANNEL_2) \|\| \
Kojto	110:165afa46840b	10122	((CHANNEL) == TIM_CHANNEL_3) \|\| \
Kojto	110:165afa46840b	10123	((CHANNEL) == TIM_CHANNEL_4))) \
Kojto	110:165afa46840b	10124	\|\| \
Kojto	110:165afa46840b	10125	(((INSTANCE) == TIM8) && \
Kojto	110:165afa46840b	10126	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
Kojto	110:165afa46840b	10127	((CHANNEL) == TIM_CHANNEL_2) \|\| \
Kojto	110:165afa46840b	10128	((CHANNEL) == TIM_CHANNEL_3) \|\| \
Kojto	110:165afa46840b	10129	((CHANNEL) == TIM_CHANNEL_4))) \
Kojto	110:165afa46840b	10130	\|\| \
Kojto	110:165afa46840b	10131	(((INSTANCE) == TIM9) && \
Kojto	110:165afa46840b	10132	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
Kojto	110:165afa46840b	10133	((CHANNEL) == TIM_CHANNEL_2))) \
Kojto	110:165afa46840b	10134	\|\| \
Kojto	110:165afa46840b	10135	(((INSTANCE) == TIM10) && \
Kojto	110:165afa46840b	10136	(((CHANNEL) == TIM_CHANNEL_1))) \
Kojto	110:165afa46840b	10137	\|\| \
Kojto	110:165afa46840b	10138	(((INSTANCE) == TIM11) && \
Kojto	110:165afa46840b	10139	(((CHANNEL) == TIM_CHANNEL_1))) \
Kojto	110:165afa46840b	10140	\|\| \
Kojto	110:165afa46840b	10141	(((INSTANCE) == TIM12) && \
Kojto	110:165afa46840b	10142	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
Kojto	110:165afa46840b	10143	((CHANNEL) == TIM_CHANNEL_2))) \
Kojto	110:165afa46840b	10144	\|\| \
Kojto	110:165afa46840b	10145	(((INSTANCE) == TIM13) && \
Kojto	110:165afa46840b	10146	(((CHANNEL) == TIM_CHANNEL_1))) \
Kojto	110:165afa46840b	10147	\|\| \
Kojto	110:165afa46840b	10148	(((INSTANCE) == TIM14) && \
Kojto	110:165afa46840b	10149	(((CHANNEL) == TIM_CHANNEL_1))))
Kojto	110:165afa46840b	10150
Kojto	110:165afa46840b	10151	/********** TIM Instances : complementary output(s) available *************/
Kojto	110:165afa46840b	10152	#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
Kojto	110:165afa46840b	10153	((((INSTANCE) == TIM1) && \
Kojto	110:165afa46840b	10154	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
Kojto	110:165afa46840b	10155	((CHANNEL) == TIM_CHANNEL_2) \|\| \
Kojto	110:165afa46840b	10156	((CHANNEL) == TIM_CHANNEL_3))) \
Kojto	110:165afa46840b	10157	\|\| \
Kojto	110:165afa46840b	10158	(((INSTANCE) == TIM8) && \
Kojto	110:165afa46840b	10159	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
Kojto	110:165afa46840b	10160	((CHANNEL) == TIM_CHANNEL_2) \|\| \
Kojto	110:165afa46840b	10161	((CHANNEL) == TIM_CHANNEL_3))))
Kojto	110:165afa46840b	10162
Kojto	110:165afa46840b	10163	/****************** USART Instances : Synchronous mode ********************/
Kojto	110:165afa46840b	10164	#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
Kojto	110:165afa46840b	10165	((INSTANCE) == USART2) \|\| \
Kojto	110:165afa46840b	10166	((INSTANCE) == USART3) \|\| \
Kojto	110:165afa46840b	10167	((INSTANCE) == USART6))
Kojto	110:165afa46840b	10168
Kojto	110:165afa46840b	10169	/****************** UART Instances : Asynchronous mode ********************/
Kojto	110:165afa46840b	10170	#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
Kojto	110:165afa46840b	10171	((INSTANCE) == USART2) \|\| \
Kojto	110:165afa46840b	10172	((INSTANCE) == USART3) \|\| \
Kojto	110:165afa46840b	10173	((INSTANCE) == UART4) \|\| \
Kojto	110:165afa46840b	10174	((INSTANCE) == UART5) \|\| \
Kojto	110:165afa46840b	10175	((INSTANCE) == USART6) \|\| \
Kojto	110:165afa46840b	10176	((INSTANCE) == UART7) \|\| \
Kojto	110:165afa46840b	10177	((INSTANCE) == UART8))
Kojto	110:165afa46840b	10178
Kojto	110:165afa46840b	10179	/**************** UART Instances : Hardware Flow control ******************/
Kojto	110:165afa46840b	10180	#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
Kojto	110:165afa46840b	10181	((INSTANCE) == USART2) \|\| \
Kojto	110:165afa46840b	10182	((INSTANCE) == USART3) \|\| \
Kojto	110:165afa46840b	10183	((INSTANCE) == USART6))
Kojto	110:165afa46840b	10184
Kojto	110:165afa46840b	10185	/******************* UART Instances : Smard card mode *********************/
Kojto	110:165afa46840b	10186	#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
Kojto	110:165afa46840b	10187	((INSTANCE) == USART2) \|\| \
Kojto	110:165afa46840b	10188	((INSTANCE) == USART3) \|\| \
Kojto	110:165afa46840b	10189	((INSTANCE) == USART6))
Kojto	110:165afa46840b	10190
Kojto	110:165afa46840b	10191	/********************* UART Instances : IRDA mode *************************/
Kojto	110:165afa46840b	10192	#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
Kojto	110:165afa46840b	10193	((INSTANCE) == USART2) \|\| \
Kojto	110:165afa46840b	10194	((INSTANCE) == USART3) \|\| \
Kojto	110:165afa46840b	10195	((INSTANCE) == UART4) \|\| \
Kojto	110:165afa46840b	10196	((INSTANCE) == UART5) \|\| \
Kojto	110:165afa46840b	10197	((INSTANCE) == USART6) \|\| \
Kojto	110:165afa46840b	10198	((INSTANCE) == UART7) \|\| \
Kojto	110:165afa46840b	10199	((INSTANCE) == UART8))
Kojto	110:165afa46840b	10200
Kojto	122:f9eeca106725	10201	/********************* PCD Instances **************************************/
Kojto	122:f9eeca106725	10202	#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) \|\| \
Kojto	122:f9eeca106725	10203	((INSTANCE) == USB_OTG_HS))
Kojto	122:f9eeca106725	10204
Kojto	122:f9eeca106725	10205	/********************* HCD Instances **************************************/
Kojto	122:f9eeca106725	10206	#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) \|\| \
Kojto	122:f9eeca106725	10207	((INSTANCE) == USB_OTG_HS))
Kojto	122:f9eeca106725	10208
Kojto	110:165afa46840b	10209	/**************************** SDIO Instances ******************************/
Kojto	110:165afa46840b	10210	#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
Kojto	110:165afa46840b	10211
Kojto	110:165afa46840b	10212	/**************************** IWDG Instances ******************************/
Kojto	110:165afa46840b	10213	#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
Kojto	110:165afa46840b	10214
Kojto	110:165afa46840b	10215	/**************************** WWDG Instances ******************************/
Kojto	110:165afa46840b	10216	#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
Kojto	110:165afa46840b	10217
Kojto	110:165afa46840b	10218	/**************************** QSPI Instances ******************************/
Kojto	110:165afa46840b	10219	#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
Kojto	110:165afa46840b	10220
Kojto	110:165afa46840b	10221	/**************************** USB Exported Constants **********************/
Kojto	122:f9eeca106725	10222	#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 12U
Kojto	122:f9eeca106725	10223	#define USB_OTG_FS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
Kojto	122:f9eeca106725	10224	#define USB_OTG_FS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */
Kojto	122:f9eeca106725	10225	#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
Kojto	122:f9eeca106725	10226
Kojto	122:f9eeca106725	10227	#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 16U
Kojto	122:f9eeca106725	10228	#define USB_OTG_HS_MAX_IN_ENDPOINTS 8U /* Including EP0 */
Kojto	122:f9eeca106725	10229	#define USB_OTG_HS_MAX_OUT_ENDPOINTS 8U /* Including EP0 */
Kojto	122:f9eeca106725	10230	#define USB_OTG_HS_TOTAL_FIFO_SIZE 4096U /* in Bytes */
Kojto	110:165afa46840b	10231
Kojto	110:165afa46840b	10232	/**
Kojto	110:165afa46840b	10233	* @}
Kojto	110:165afa46840b	10234	*/
Kojto	110:165afa46840b	10235
Kojto	110:165afa46840b	10236	/**
Kojto	110:165afa46840b	10237	* @}
Kojto	110:165afa46840b	10238	*/
Kojto	110:165afa46840b	10239
Kojto	110:165afa46840b	10240	/**
Kojto	110:165afa46840b	10241	* @}
Kojto	110:165afa46840b	10242	*/
Kojto	110:165afa46840b	10243
Kojto	110:165afa46840b	10244	#ifdef __cplusplus
Kojto	110:165afa46840b	10245	}
Kojto	110:165afa46840b	10246	#endif /* __cplusplus */
Kojto	110:165afa46840b	10247
Kojto	110:165afa46840b	10248	#endif /* __STM32F469xx_H */
Kojto	110:165afa46840b	10249
Kojto	110:165afa46840b	10250
Kojto	110:165afa46840b	10251
Kojto	110:165afa46840b	10252	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/