mbed official / mbed

Important changes to repositories hosted on mbed.com

Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.

To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.

It is also possible to export all your personal repositories from the account settings page.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

TARGET_B96B_F446VE/stm32f4xx_hal_rcc.h@122:f9eeca106725, 2016-07-07 (annotated)

Committer:
Kojto
Date:
Thu Jul 07 14:34:11 2016 +0100
Revision:
122:f9eeca106725
Parent:
116:c0f6e94411f5 
Release 122 of the mbed library



Changes:

- new targets - Nucleo L432KC, Beetle, Nucleo F446ZE, Nucleo L011K4

- Thread safety addition - mbed API should contain a statement about thread safety

- critical section API addition

- CAS API (core_util_atomic_incr/decr)

- DEVICE_ are generated from targets.json file, device.h deprecated

- Callback replaces FunctionPointer to provide std like interface

- mbed HAL API docs improvements

- toolchain - prexif attributes with MBED_

            - add new attributes - packed, weak, forcedinline, align

- target.json - contains targets definitions

- ST - L1XX - Cube update to 1.5

     - SPI clock selection fix (clock from APB domain)

     - F7 - Cube update v1.4.0

     - L0 -  baudrate init fix

     - L1 - Cube update v1.5

     - F3 - baudrate init fix, 3 targets CAN support

     - F4 - Cube update v1.12.0, 3 targets CAN support

     - L4XX - Cube update v1.5.1

     - F0 - update Cube to v1.5.0

     - L4 - 2 targets (L476RG/VG) CAN support

- NXP - pwm clock fix for KSDK2 MCU

      - LPC2368 - remove ARM toolchain support - due to regression

      - KSDK2 - fix SPI , I2C address and repeat start

- Silabs - some fixes backported from mbed 3

- Renesas - RZ_A1H - SystemCoreClockUpdate addition

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 112:6f327212ef96 1 /**
Kojto 112:6f327212ef96 2 ******************************************************************************
Kojto 112:6f327212ef96 3 * @file stm32f4xx_hal_rcc.h
Kojto 112:6f327212ef96 4 * @author MCD Application Team
Kojto 122:f9eeca106725 5 * @version V1.5.0
Kojto 122:f9eeca106725 6 * @date 06-May-2016
Kojto 112:6f327212ef96 7 * @brief Header file of RCC HAL module.
Kojto 112:6f327212ef96 8 ******************************************************************************
Kojto 112:6f327212ef96 9 * @attention
Kojto 112:6f327212ef96 10 *
Kojto 122:f9eeca106725 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
Kojto 112:6f327212ef96 12 *
Kojto 112:6f327212ef96 13 * Redistribution and use in source and binary forms, with or without modification,
Kojto 112:6f327212ef96 14 * are permitted provided that the following conditions are met:
Kojto 112:6f327212ef96 15 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 112:6f327212ef96 16 * this list of conditions and the following disclaimer.
Kojto 112:6f327212ef96 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 112:6f327212ef96 18 * this list of conditions and the following disclaimer in the documentation
Kojto 112:6f327212ef96 19 * and/or other materials provided with the distribution.
Kojto 112:6f327212ef96 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto 112:6f327212ef96 21 * may be used to endorse or promote products derived from this software
Kojto 112:6f327212ef96 22 * without specific prior written permission.
Kojto 112:6f327212ef96 23 *
Kojto 112:6f327212ef96 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 112:6f327212ef96 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 112:6f327212ef96 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 112:6f327212ef96 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 112:6f327212ef96 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 112:6f327212ef96 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 112:6f327212ef96 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 112:6f327212ef96 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 112:6f327212ef96 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 112:6f327212ef96 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 112:6f327212ef96 34 *
Kojto 112:6f327212ef96 35 ******************************************************************************
Kojto 112:6f327212ef96 36 */
Kojto 112:6f327212ef96 37
Kojto 112:6f327212ef96 38 /* Define to prevent recursive inclusion -------------------------------------*/
Kojto 112:6f327212ef96 39 #ifndef __STM32F4xx_HAL_RCC_H
Kojto 112:6f327212ef96 40 #define __STM32F4xx_HAL_RCC_H
Kojto 112:6f327212ef96 41
Kojto 112:6f327212ef96 42 #ifdef __cplusplus
Kojto 112:6f327212ef96 43 extern "C" {
Kojto 112:6f327212ef96 44 #endif
Kojto 112:6f327212ef96 45
Kojto 112:6f327212ef96 46 /* Includes ------------------------------------------------------------------*/
Kojto 112:6f327212ef96 47 #include "stm32f4xx_hal_def.h"
Kojto 112:6f327212ef96 48
Kojto 112:6f327212ef96 49 /* Include RCC HAL Extended module */
Kojto 112:6f327212ef96 50 /* (include on top of file since RCC structures are defined in extended file) */
Kojto 112:6f327212ef96 51 #include "stm32f4xx_hal_rcc_ex.h"
Kojto 112:6f327212ef96 52
Kojto 112:6f327212ef96 53 /** @addtogroup STM32F4xx_HAL_Driver
Kojto 112:6f327212ef96 54 * @{
Kojto 112:6f327212ef96 55 */
Kojto 112:6f327212ef96 56
Kojto 112:6f327212ef96 57 /** @addtogroup RCC
Kojto 112:6f327212ef96 58 * @{
Kojto 112:6f327212ef96 59 */
Kojto 112:6f327212ef96 60
Kojto 112:6f327212ef96 61 /* Exported types ------------------------------------------------------------*/
Kojto 112:6f327212ef96 62 /** @defgroup RCC_Exported_Types RCC Exported Types
Kojto 112:6f327212ef96 63 * @{
Kojto 112:6f327212ef96 64 */
Kojto 112:6f327212ef96 65
Kojto 112:6f327212ef96 66 /**
Kojto 112:6f327212ef96 67 * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
Kojto 112:6f327212ef96 68 */
Kojto 112:6f327212ef96 69 typedef struct
Kojto 112:6f327212ef96 70 {
Kojto 112:6f327212ef96 71 uint32_t OscillatorType; /*!< The oscillators to be configured.
Kojto 112:6f327212ef96 72 This parameter can be a value of @ref RCC_Oscillator_Type */
Kojto 112:6f327212ef96 73
Kojto 112:6f327212ef96 74 uint32_t HSEState; /*!< The new state of the HSE.
Kojto 112:6f327212ef96 75 This parameter can be a value of @ref RCC_HSE_Config */
Kojto 112:6f327212ef96 76
Kojto 112:6f327212ef96 77 uint32_t LSEState; /*!< The new state of the LSE.
Kojto 112:6f327212ef96 78 This parameter can be a value of @ref RCC_LSE_Config */
Kojto 122:f9eeca106725 79
Kojto 112:6f327212ef96 80 uint32_t HSIState; /*!< The new state of the HSI.
Kojto 112:6f327212ef96 81 This parameter can be a value of @ref RCC_HSI_Config */
Kojto 112:6f327212ef96 82
Kojto 122:f9eeca106725 83 uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
Kojto 122:f9eeca106725 84 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
Kojto 122:f9eeca106725 85
Kojto 112:6f327212ef96 86 uint32_t LSIState; /*!< The new state of the LSI.
Kojto 112:6f327212ef96 87 This parameter can be a value of @ref RCC_LSI_Config */
Kojto 112:6f327212ef96 88
Kojto 122:f9eeca106725 89 RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
Kojto 112:6f327212ef96 90 }RCC_OscInitTypeDef;
Kojto 112:6f327212ef96 91
Kojto 112:6f327212ef96 92 /**
Kojto 112:6f327212ef96 93 * @brief RCC System, AHB and APB busses clock configuration structure definition
Kojto 112:6f327212ef96 94 */
Kojto 112:6f327212ef96 95 typedef struct
Kojto 112:6f327212ef96 96 {
Kojto 112:6f327212ef96 97 uint32_t ClockType; /*!< The clock to be configured.
Kojto 112:6f327212ef96 98 This parameter can be a value of @ref RCC_System_Clock_Type */
Kojto 112:6f327212ef96 99
Kojto 112:6f327212ef96 100 uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
Kojto 112:6f327212ef96 101 This parameter can be a value of @ref RCC_System_Clock_Source */
Kojto 112:6f327212ef96 102
Kojto 112:6f327212ef96 103 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
Kojto 112:6f327212ef96 104 This parameter can be a value of @ref RCC_AHB_Clock_Source */
Kojto 112:6f327212ef96 105
Kojto 112:6f327212ef96 106 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
Kojto 112:6f327212ef96 107 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
Kojto 112:6f327212ef96 108
Kojto 112:6f327212ef96 109 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
Kojto 112:6f327212ef96 110 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
Kojto 112:6f327212ef96 111
Kojto 112:6f327212ef96 112 }RCC_ClkInitTypeDef;
Kojto 112:6f327212ef96 113
Kojto 112:6f327212ef96 114 /**
Kojto 112:6f327212ef96 115 * @}
Kojto 112:6f327212ef96 116 */
Kojto 112:6f327212ef96 117
Kojto 112:6f327212ef96 118 /* Exported constants --------------------------------------------------------*/
Kojto 112:6f327212ef96 119 /** @defgroup RCC_Exported_Constants RCC Exported Constants
Kojto 112:6f327212ef96 120 * @{
Kojto 112:6f327212ef96 121 */
Kojto 112:6f327212ef96 122
Kojto 112:6f327212ef96 123 /** @defgroup RCC_Oscillator_Type Oscillator Type
Kojto 112:6f327212ef96 124 * @{
Kojto 112:6f327212ef96 125 */
Kojto 122:f9eeca106725 126 #define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 127 #define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001U)
Kojto 122:f9eeca106725 128 #define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002U)
Kojto 122:f9eeca106725 129 #define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004U)
Kojto 122:f9eeca106725 130 #define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008U)
Kojto 112:6f327212ef96 131 /**
Kojto 112:6f327212ef96 132 * @}
Kojto 112:6f327212ef96 133 */
Kojto 112:6f327212ef96 134
Kojto 112:6f327212ef96 135 /** @defgroup RCC_HSE_Config HSE Config
Kojto 112:6f327212ef96 136 * @{
Kojto 112:6f327212ef96 137 */
Kojto 122:f9eeca106725 138 #define RCC_HSE_OFF ((uint8_t)0x00U)
Kojto 122:f9eeca106725 139 #define RCC_HSE_ON ((uint8_t)0x01U)
Kojto 122:f9eeca106725 140 #define RCC_HSE_BYPASS ((uint8_t)0x05U)
Kojto 112:6f327212ef96 141 /**
Kojto 112:6f327212ef96 142 * @}
Kojto 112:6f327212ef96 143 */
Kojto 112:6f327212ef96 144
Kojto 112:6f327212ef96 145 /** @defgroup RCC_LSE_Config LSE Config
Kojto 112:6f327212ef96 146 * @{
Kojto 112:6f327212ef96 147 */
Kojto 122:f9eeca106725 148 #define RCC_LSE_OFF ((uint8_t)0x00U)
Kojto 122:f9eeca106725 149 #define RCC_LSE_ON ((uint8_t)0x01U)
Kojto 122:f9eeca106725 150 #define RCC_LSE_BYPASS ((uint8_t)0x05U)
Kojto 112:6f327212ef96 151 /**
Kojto 112:6f327212ef96 152 * @}
Kojto 112:6f327212ef96 153 */
Kojto 112:6f327212ef96 154
Kojto 112:6f327212ef96 155 /** @defgroup RCC_HSI_Config HSI Config
Kojto 112:6f327212ef96 156 * @{
Kojto 112:6f327212ef96 157 */
Kojto 122:f9eeca106725 158 #define RCC_HSI_OFF ((uint8_t)0x00U)
Kojto 122:f9eeca106725 159 #define RCC_HSI_ON ((uint8_t)0x01U)
Kojto 122:f9eeca106725 160
Kojto 122:f9eeca106725 161 #define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10U) /* Default HSI calibration trimming value */
Kojto 112:6f327212ef96 162 /**
Kojto 112:6f327212ef96 163 * @}
Kojto 112:6f327212ef96 164 */
Kojto 112:6f327212ef96 165
Kojto 112:6f327212ef96 166 /** @defgroup RCC_LSI_Config LSI Config
Kojto 112:6f327212ef96 167 * @{
Kojto 112:6f327212ef96 168 */
Kojto 122:f9eeca106725 169 #define RCC_LSI_OFF ((uint8_t)0x00U)
Kojto 122:f9eeca106725 170 #define RCC_LSI_ON ((uint8_t)0x01U)
Kojto 112:6f327212ef96 171 /**
Kojto 112:6f327212ef96 172 * @}
Kojto 112:6f327212ef96 173 */
Kojto 112:6f327212ef96 174
Kojto 112:6f327212ef96 175 /** @defgroup RCC_PLL_Config PLL Config
Kojto 112:6f327212ef96 176 * @{
Kojto 112:6f327212ef96 177 */
Kojto 122:f9eeca106725 178 #define RCC_PLL_NONE ((uint8_t)0x00U)
Kojto 122:f9eeca106725 179 #define RCC_PLL_OFF ((uint8_t)0x01U)
Kojto 122:f9eeca106725 180 #define RCC_PLL_ON ((uint8_t)0x02U)
Kojto 112:6f327212ef96 181 /**
Kojto 112:6f327212ef96 182 * @}
Kojto 112:6f327212ef96 183 */
Kojto 112:6f327212ef96 184
Kojto 112:6f327212ef96 185 /** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
Kojto 112:6f327212ef96 186 * @{
Kojto 112:6f327212ef96 187 */
Kojto 122:f9eeca106725 188 #define RCC_PLLP_DIV2 ((uint32_t)0x00000002U)
Kojto 122:f9eeca106725 189 #define RCC_PLLP_DIV4 ((uint32_t)0x00000004U)
Kojto 122:f9eeca106725 190 #define RCC_PLLP_DIV6 ((uint32_t)0x00000006U)
Kojto 122:f9eeca106725 191 #define RCC_PLLP_DIV8 ((uint32_t)0x00000008U)
Kojto 112:6f327212ef96 192 /**
Kojto 112:6f327212ef96 193 * @}
Kojto 112:6f327212ef96 194 */
Kojto 112:6f327212ef96 195
Kojto 112:6f327212ef96 196 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source
Kojto 112:6f327212ef96 197 * @{
Kojto 112:6f327212ef96 198 */
Kojto 112:6f327212ef96 199 #define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
Kojto 112:6f327212ef96 200 #define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE
Kojto 112:6f327212ef96 201 /**
Kojto 112:6f327212ef96 202 * @}
Kojto 112:6f327212ef96 203 */
Kojto 112:6f327212ef96 204
Kojto 112:6f327212ef96 205 /** @defgroup RCC_System_Clock_Type System Clock Type
Kojto 112:6f327212ef96 206 * @{
Kojto 112:6f327212ef96 207 */
Kojto 122:f9eeca106725 208 #define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001U)
Kojto 122:f9eeca106725 209 #define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002U)
Kojto 122:f9eeca106725 210 #define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004U)
Kojto 122:f9eeca106725 211 #define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008U)
Kojto 112:6f327212ef96 212 /**
Kojto 112:6f327212ef96 213 * @}
Kojto 112:6f327212ef96 214 */
Kojto 112:6f327212ef96 215
Kojto 112:6f327212ef96 216 /** @defgroup RCC_System_Clock_Source System Clock Source
Kojto 112:6f327212ef96 217 * @{
Kojto 112:6f327212ef96 218 */
Kojto 112:6f327212ef96 219 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
Kojto 112:6f327212ef96 220 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
Kojto 112:6f327212ef96 221 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
Kojto 112:6f327212ef96 222 #define RCC_SYSCLKSOURCE_PLLRCLK ((uint32_t)(RCC_CFGR_SW_0 | RCC_CFGR_SW_1))
Kojto 112:6f327212ef96 223 /**
Kojto 112:6f327212ef96 224 * @}
Kojto 112:6f327212ef96 225 */
Kojto 112:6f327212ef96 226
Kojto 112:6f327212ef96 227 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
Kojto 112:6f327212ef96 228 * @{
Kojto 112:6f327212ef96 229 */
Kojto 112:6f327212ef96 230 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
Kojto 112:6f327212ef96 231 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
Kojto 112:6f327212ef96 232 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
Kojto 122:f9eeca106725 233 #define RCC_SYSCLKSOURCE_STATUS_PLLRCLK ((uint32_t)(RCC_CFGR_SWS_0 | RCC_CFGR_SWS_1)) /*!< PLLR used as system clock */
Kojto 112:6f327212ef96 234 /**
Kojto 112:6f327212ef96 235 * @}
Kojto 112:6f327212ef96 236 */
Kojto 112:6f327212ef96 237
Kojto 112:6f327212ef96 238 /** @defgroup RCC_AHB_Clock_Source AHB Clock Source
Kojto 112:6f327212ef96 239 * @{
Kojto 112:6f327212ef96 240 */
Kojto 112:6f327212ef96 241 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
Kojto 112:6f327212ef96 242 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
Kojto 112:6f327212ef96 243 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
Kojto 112:6f327212ef96 244 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
Kojto 112:6f327212ef96 245 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
Kojto 112:6f327212ef96 246 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
Kojto 112:6f327212ef96 247 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
Kojto 112:6f327212ef96 248 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
Kojto 112:6f327212ef96 249 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
Kojto 112:6f327212ef96 250 /**
Kojto 112:6f327212ef96 251 * @}
Kojto 112:6f327212ef96 252 */
Kojto 112:6f327212ef96 253
Kojto 112:6f327212ef96 254 /** @defgroup RCC_APB1_APB2_Clock_Source APB1/APB2 Clock Source
Kojto 112:6f327212ef96 255 * @{
Kojto 112:6f327212ef96 256 */
Kojto 112:6f327212ef96 257 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
Kojto 112:6f327212ef96 258 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
Kojto 112:6f327212ef96 259 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
Kojto 112:6f327212ef96 260 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
Kojto 112:6f327212ef96 261 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
Kojto 112:6f327212ef96 262 /**
Kojto 112:6f327212ef96 263 * @}
Kojto 112:6f327212ef96 264 */
Kojto 112:6f327212ef96 265
Kojto 112:6f327212ef96 266 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source
Kojto 112:6f327212ef96 267 * @{
Kojto 112:6f327212ef96 268 */
Kojto 122:f9eeca106725 269 #define RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100U)
Kojto 122:f9eeca106725 270 #define RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200U)
Kojto 122:f9eeca106725 271 #define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00020300U)
Kojto 122:f9eeca106725 272 #define RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00030300U)
Kojto 122:f9eeca106725 273 #define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00040300U)
Kojto 122:f9eeca106725 274 #define RCC_RTCCLKSOURCE_HSE_DIV5 ((uint32_t)0x00050300U)
Kojto 122:f9eeca106725 275 #define RCC_RTCCLKSOURCE_HSE_DIV6 ((uint32_t)0x00060300U)
Kojto 122:f9eeca106725 276 #define RCC_RTCCLKSOURCE_HSE_DIV7 ((uint32_t)0x00070300U)
Kojto 122:f9eeca106725 277 #define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)0x00080300U)
Kojto 122:f9eeca106725 278 #define RCC_RTCCLKSOURCE_HSE_DIV9 ((uint32_t)0x00090300U)
Kojto 122:f9eeca106725 279 #define RCC_RTCCLKSOURCE_HSE_DIV10 ((uint32_t)0x000A0300U)
Kojto 122:f9eeca106725 280 #define RCC_RTCCLKSOURCE_HSE_DIV11 ((uint32_t)0x000B0300U)
Kojto 122:f9eeca106725 281 #define RCC_RTCCLKSOURCE_HSE_DIV12 ((uint32_t)0x000C0300U)
Kojto 122:f9eeca106725 282 #define RCC_RTCCLKSOURCE_HSE_DIV13 ((uint32_t)0x000D0300U)
Kojto 122:f9eeca106725 283 #define RCC_RTCCLKSOURCE_HSE_DIV14 ((uint32_t)0x000E0300U)
Kojto 122:f9eeca106725 284 #define RCC_RTCCLKSOURCE_HSE_DIV15 ((uint32_t)0x000F0300U)
Kojto 122:f9eeca106725 285 #define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)0x00100300U)
Kojto 122:f9eeca106725 286 #define RCC_RTCCLKSOURCE_HSE_DIV17 ((uint32_t)0x00110300U)
Kojto 122:f9eeca106725 287 #define RCC_RTCCLKSOURCE_HSE_DIV18 ((uint32_t)0x00120300U)
Kojto 122:f9eeca106725 288 #define RCC_RTCCLKSOURCE_HSE_DIV19 ((uint32_t)0x00130300U)
Kojto 122:f9eeca106725 289 #define RCC_RTCCLKSOURCE_HSE_DIV20 ((uint32_t)0x00140300U)
Kojto 122:f9eeca106725 290 #define RCC_RTCCLKSOURCE_HSE_DIV21 ((uint32_t)0x00150300U)
Kojto 122:f9eeca106725 291 #define RCC_RTCCLKSOURCE_HSE_DIV22 ((uint32_t)0x00160300U)
Kojto 122:f9eeca106725 292 #define RCC_RTCCLKSOURCE_HSE_DIV23 ((uint32_t)0x00170300U)
Kojto 122:f9eeca106725 293 #define RCC_RTCCLKSOURCE_HSE_DIV24 ((uint32_t)0x00180300U)
Kojto 122:f9eeca106725 294 #define RCC_RTCCLKSOURCE_HSE_DIV25 ((uint32_t)0x00190300U)
Kojto 122:f9eeca106725 295 #define RCC_RTCCLKSOURCE_HSE_DIV26 ((uint32_t)0x001A0300U)
Kojto 122:f9eeca106725 296 #define RCC_RTCCLKSOURCE_HSE_DIV27 ((uint32_t)0x001B0300U)
Kojto 122:f9eeca106725 297 #define RCC_RTCCLKSOURCE_HSE_DIV28 ((uint32_t)0x001C0300U)
Kojto 122:f9eeca106725 298 #define RCC_RTCCLKSOURCE_HSE_DIV29 ((uint32_t)0x001D0300U)
Kojto 122:f9eeca106725 299 #define RCC_RTCCLKSOURCE_HSE_DIV30 ((uint32_t)0x001E0300U)
Kojto 122:f9eeca106725 300 #define RCC_RTCCLKSOURCE_HSE_DIV31 ((uint32_t)0x001F0300U)
Kojto 112:6f327212ef96 301 /**
Kojto 112:6f327212ef96 302 * @}
Kojto 112:6f327212ef96 303 */
Kojto 112:6f327212ef96 304
Kojto 112:6f327212ef96 305 /** @defgroup RCC_MCO_Index MCO Index
Kojto 112:6f327212ef96 306 * @{
Kojto 112:6f327212ef96 307 */
Kojto 122:f9eeca106725 308 #define RCC_MCO1 ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 309 #define RCC_MCO2 ((uint32_t)0x00000001U)
Kojto 112:6f327212ef96 310 /**
Kojto 112:6f327212ef96 311 * @}
Kojto 112:6f327212ef96 312 */
Kojto 112:6f327212ef96 313
Kojto 112:6f327212ef96 314 /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
Kojto 112:6f327212ef96 315 * @{
Kojto 112:6f327212ef96 316 */
Kojto 122:f9eeca106725 317 #define RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000U)
Kojto 112:6f327212ef96 318 #define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0
Kojto 112:6f327212ef96 319 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1
Kojto 112:6f327212ef96 320 #define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1
Kojto 112:6f327212ef96 321 /**
Kojto 112:6f327212ef96 322 * @}
Kojto 112:6f327212ef96 323 */
Kojto 112:6f327212ef96 324
Kojto 112:6f327212ef96 325 /** @defgroup RCC_MCOx_Clock_Prescaler MCOx Clock Prescaler
Kojto 112:6f327212ef96 326 * @{
Kojto 112:6f327212ef96 327 */
Kojto 122:f9eeca106725 328 #define RCC_MCODIV_1 ((uint32_t)0x00000000U)
Kojto 112:6f327212ef96 329 #define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2
Kojto 112:6f327212ef96 330 #define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
Kojto 112:6f327212ef96 331 #define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
Kojto 112:6f327212ef96 332 #define RCC_MCODIV_5 RCC_CFGR_MCO1PRE
Kojto 112:6f327212ef96 333 /**
Kojto 112:6f327212ef96 334 * @}
Kojto 112:6f327212ef96 335 */
Kojto 112:6f327212ef96 336
Kojto 112:6f327212ef96 337 /** @defgroup RCC_Interrupt Interrupts
Kojto 112:6f327212ef96 338 * @{
Kojto 112:6f327212ef96 339 */
Kojto 122:f9eeca106725 340 #define RCC_IT_LSIRDY ((uint8_t)0x01U)
Kojto 122:f9eeca106725 341 #define RCC_IT_LSERDY ((uint8_t)0x02U)
Kojto 122:f9eeca106725 342 #define RCC_IT_HSIRDY ((uint8_t)0x04U)
Kojto 122:f9eeca106725 343 #define RCC_IT_HSERDY ((uint8_t)0x08U)
Kojto 122:f9eeca106725 344 #define RCC_IT_PLLRDY ((uint8_t)0x10U)
Kojto 122:f9eeca106725 345 #define RCC_IT_PLLI2SRDY ((uint8_t)0x20U)
Kojto 122:f9eeca106725 346 #define RCC_IT_CSS ((uint8_t)0x80U)
Kojto 112:6f327212ef96 347 /**
Kojto 112:6f327212ef96 348 * @}
Kojto 112:6f327212ef96 349 */
Kojto 112:6f327212ef96 350
Kojto 112:6f327212ef96 351 /** @defgroup RCC_Flag Flags
Kojto 112:6f327212ef96 352 * Elements values convention: 0XXYYYYYb
Kojto 112:6f327212ef96 353 * - YYYYY : Flag position in the register
Kojto 112:6f327212ef96 354 * - 0XX : Register index
Kojto 112:6f327212ef96 355 * - 01: CR register
Kojto 112:6f327212ef96 356 * - 10: BDCR register
Kojto 112:6f327212ef96 357 * - 11: CSR register
Kojto 112:6f327212ef96 358 * @{
Kojto 112:6f327212ef96 359 */
Kojto 112:6f327212ef96 360 /* Flags in the CR register */
Kojto 122:f9eeca106725 361 #define RCC_FLAG_HSIRDY ((uint8_t)0x21U)
Kojto 122:f9eeca106725 362 #define RCC_FLAG_HSERDY ((uint8_t)0x31U)
Kojto 122:f9eeca106725 363 #define RCC_FLAG_PLLRDY ((uint8_t)0x39U)
Kojto 122:f9eeca106725 364 #define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3BU)
Kojto 112:6f327212ef96 365
Kojto 112:6f327212ef96 366 /* Flags in the BDCR register */
Kojto 122:f9eeca106725 367 #define RCC_FLAG_LSERDY ((uint8_t)0x41U)
Kojto 112:6f327212ef96 368
Kojto 112:6f327212ef96 369 /* Flags in the CSR register */
Kojto 122:f9eeca106725 370 #define RCC_FLAG_LSIRDY ((uint8_t)0x61U)
Kojto 122:f9eeca106725 371 #define RCC_FLAG_BORRST ((uint8_t)0x79U)
Kojto 122:f9eeca106725 372 #define RCC_FLAG_PINRST ((uint8_t)0x7AU)
Kojto 122:f9eeca106725 373 #define RCC_FLAG_PORRST ((uint8_t)0x7BU)
Kojto 122:f9eeca106725 374 #define RCC_FLAG_SFTRST ((uint8_t)0x7CU)
Kojto 122:f9eeca106725 375 #define RCC_FLAG_IWDGRST ((uint8_t)0x7DU)
Kojto 122:f9eeca106725 376 #define RCC_FLAG_WWDGRST ((uint8_t)0x7EU)
Kojto 122:f9eeca106725 377 #define RCC_FLAG_LPWRRST ((uint8_t)0x7FU)
Kojto 112:6f327212ef96 378 /**
Kojto 112:6f327212ef96 379 * @}
Kojto 112:6f327212ef96 380 */
Kojto 112:6f327212ef96 381
Kojto 112:6f327212ef96 382 /**
Kojto 112:6f327212ef96 383 * @}
Kojto 112:6f327212ef96 384 */
Kojto 112:6f327212ef96 385
Kojto 112:6f327212ef96 386 /* Exported macro ------------------------------------------------------------*/
Kojto 112:6f327212ef96 387 /** @defgroup RCC_Exported_Macros RCC Exported Macros
Kojto 112:6f327212ef96 388 * @{
Kojto 112:6f327212ef96 389 */
Kojto 112:6f327212ef96 390
Kojto 112:6f327212ef96 391 /** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
Kojto 112:6f327212ef96 392 * @brief Enable or disable the AHB1 peripheral clock.
Kojto 112:6f327212ef96 393 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 112:6f327212ef96 394 * is disabled and the application software has to enable this clock before
Kojto 112:6f327212ef96 395 * using it.
Kojto 112:6f327212ef96 396 * @{
Kojto 112:6f327212ef96 397 */
Kojto 122:f9eeca106725 398 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 399 __IO uint32_t tmpreg = 0x00U; \
Kojto 112:6f327212ef96 400 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
Kojto 112:6f327212ef96 401 /* Delay after an RCC peripheral clock enabling */ \
Kojto 112:6f327212ef96 402 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
Kojto 112:6f327212ef96 403 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 404 } while(0)
Kojto 122:f9eeca106725 405 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 406 __IO uint32_t tmpreg = 0x00U; \
Kojto 112:6f327212ef96 407 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
Kojto 112:6f327212ef96 408 /* Delay after an RCC peripheral clock enabling */ \
Kojto 112:6f327212ef96 409 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
Kojto 112:6f327212ef96 410 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 411 } while(0)
Kojto 122:f9eeca106725 412 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 413 __IO uint32_t tmpreg = 0x00U; \
Kojto 112:6f327212ef96 414 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
Kojto 112:6f327212ef96 415 /* Delay after an RCC peripheral clock enabling */ \
Kojto 112:6f327212ef96 416 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
Kojto 112:6f327212ef96 417 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 418 } while(0)
Kojto 122:f9eeca106725 419 #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 420 __IO uint32_t tmpreg = 0x00U; \
Kojto 112:6f327212ef96 421 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
Kojto 112:6f327212ef96 422 /* Delay after an RCC peripheral clock enabling */ \
Kojto 112:6f327212ef96 423 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
Kojto 112:6f327212ef96 424 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 425 } while(0)
Kojto 122:f9eeca106725 426 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 427 __IO uint32_t tmpreg = 0x00U; \
Kojto 112:6f327212ef96 428 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
Kojto 112:6f327212ef96 429 /* Delay after an RCC peripheral clock enabling */ \
Kojto 112:6f327212ef96 430 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
Kojto 112:6f327212ef96 431 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 432 } while(0)
Kojto 112:6f327212ef96 433 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 434 __IO uint32_t tmpreg = 0x00U; \
Kojto 112:6f327212ef96 435 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
Kojto 112:6f327212ef96 436 /* Delay after an RCC peripheral clock enabling */ \
Kojto 112:6f327212ef96 437 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
Kojto 112:6f327212ef96 438 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 439 } while(0)
Kojto 112:6f327212ef96 440
Kojto 112:6f327212ef96 441 #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
Kojto 112:6f327212ef96 442 #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
Kojto 112:6f327212ef96 443 #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
Kojto 112:6f327212ef96 444 #define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
Kojto 112:6f327212ef96 445 #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
Kojto 112:6f327212ef96 446 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
Kojto 112:6f327212ef96 447 /**
Kojto 112:6f327212ef96 448 * @}
Kojto 112:6f327212ef96 449 */
Kojto 112:6f327212ef96 450
Kojto 122:f9eeca106725 451 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
Kojto 122:f9eeca106725 452 * @brief Get the enable or disable status of the AHB1 peripheral clock.
Kojto 122:f9eeca106725 453 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 122:f9eeca106725 454 * is disabled and the application software has to enable this clock before
Kojto 122:f9eeca106725 455 * using it.
Kojto 122:f9eeca106725 456 * @{
Kojto 122:f9eeca106725 457 */
Kojto 122:f9eeca106725 458 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) != RESET)
Kojto 122:f9eeca106725 459 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) != RESET)
Kojto 122:f9eeca106725 460 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) != RESET)
Kojto 122:f9eeca106725 461 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) != RESET)
Kojto 122:f9eeca106725 462 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) != RESET)
Kojto 122:f9eeca106725 463 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) != RESET)
Kojto 122:f9eeca106725 464
Kojto 122:f9eeca106725 465 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) == RESET)
Kojto 122:f9eeca106725 466 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) == RESET)
Kojto 122:f9eeca106725 467 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) == RESET)
Kojto 122:f9eeca106725 468 #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) == RESET)
Kojto 122:f9eeca106725 469 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) == RESET)
Kojto 122:f9eeca106725 470 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) == RESET)
Kojto 122:f9eeca106725 471 /**
Kojto 122:f9eeca106725 472 * @}
Kojto 122:f9eeca106725 473 */
Kojto 122:f9eeca106725 474
Kojto 112:6f327212ef96 475 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
Kojto 112:6f327212ef96 476 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
Kojto 112:6f327212ef96 477 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 112:6f327212ef96 478 * is disabled and the application software has to enable this clock before
Kojto 112:6f327212ef96 479 * using it.
Kojto 112:6f327212ef96 480 * @{
Kojto 112:6f327212ef96 481 */
Kojto 112:6f327212ef96 482 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 483 __IO uint32_t tmpreg = 0x00U; \
Kojto 112:6f327212ef96 484 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
Kojto 112:6f327212ef96 485 /* Delay after an RCC peripheral clock enabling */ \
Kojto 112:6f327212ef96 486 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
Kojto 112:6f327212ef96 487 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 488 } while(0)
Kojto 112:6f327212ef96 489 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 490 __IO uint32_t tmpreg = 0x00U; \
Kojto 112:6f327212ef96 491 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
Kojto 112:6f327212ef96 492 /* Delay after an RCC peripheral clock enabling */ \
Kojto 112:6f327212ef96 493 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
Kojto 112:6f327212ef96 494 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 495 } while(0)
Kojto 112:6f327212ef96 496 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 497 __IO uint32_t tmpreg = 0x00U; \
Kojto 112:6f327212ef96 498 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
Kojto 112:6f327212ef96 499 /* Delay after an RCC peripheral clock enabling */ \
Kojto 112:6f327212ef96 500 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
Kojto 112:6f327212ef96 501 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 502 } while(0)
Kojto 112:6f327212ef96 503 #define __HAL_RCC_USART2_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 504 __IO uint32_t tmpreg = 0x00U; \
Kojto 112:6f327212ef96 505 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
Kojto 112:6f327212ef96 506 /* Delay after an RCC peripheral clock enabling */ \
Kojto 112:6f327212ef96 507 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
Kojto 112:6f327212ef96 508 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 509 } while(0)
Kojto 112:6f327212ef96 510 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 511 __IO uint32_t tmpreg = 0x00U; \
Kojto 112:6f327212ef96 512 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
Kojto 112:6f327212ef96 513 /* Delay after an RCC peripheral clock enabling */ \
Kojto 112:6f327212ef96 514 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
Kojto 112:6f327212ef96 515 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 516 } while(0)
Kojto 112:6f327212ef96 517 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 518 __IO uint32_t tmpreg = 0x00U; \
Kojto 112:6f327212ef96 519 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
Kojto 112:6f327212ef96 520 /* Delay after an RCC peripheral clock enabling */ \
Kojto 112:6f327212ef96 521 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
Kojto 112:6f327212ef96 522 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 523 } while(0)
Kojto 112:6f327212ef96 524 #define __HAL_RCC_PWR_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 525 __IO uint32_t tmpreg = 0x00U; \
Kojto 112:6f327212ef96 526 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
Kojto 112:6f327212ef96 527 /* Delay after an RCC peripheral clock enabling */ \
Kojto 112:6f327212ef96 528 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
Kojto 112:6f327212ef96 529 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 530 } while(0)
Kojto 112:6f327212ef96 531
Kojto 112:6f327212ef96 532 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
Kojto 112:6f327212ef96 533 #define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
Kojto 112:6f327212ef96 534 #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
Kojto 112:6f327212ef96 535 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
Kojto 112:6f327212ef96 536 #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
Kojto 112:6f327212ef96 537 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
Kojto 112:6f327212ef96 538 #define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
Kojto 112:6f327212ef96 539 /**
Kojto 112:6f327212ef96 540 * @}
Kojto 112:6f327212ef96 541 */
Kojto 112:6f327212ef96 542
Kojto 122:f9eeca106725 543 /** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
Kojto 122:f9eeca106725 544 * @brief Get the enable or disable status of the APB1 peripheral clock.
Kojto 122:f9eeca106725 545 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 122:f9eeca106725 546 * is disabled and the application software has to enable this clock before
Kojto 122:f9eeca106725 547 * using it.
Kojto 122:f9eeca106725 548 * @{
Kojto 122:f9eeca106725 549 */
Kojto 122:f9eeca106725 550 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
Kojto 122:f9eeca106725 551 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
Kojto 122:f9eeca106725 552 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
Kojto 122:f9eeca106725 553 #define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
Kojto 122:f9eeca106725 554 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
Kojto 122:f9eeca106725 555 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
Kojto 122:f9eeca106725 556 #define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
Kojto 122:f9eeca106725 557
Kojto 122:f9eeca106725 558 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
Kojto 122:f9eeca106725 559 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
Kojto 122:f9eeca106725 560 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
Kojto 122:f9eeca106725 561 #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
Kojto 122:f9eeca106725 562 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
Kojto 122:f9eeca106725 563 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
Kojto 122:f9eeca106725 564 #define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
Kojto 122:f9eeca106725 565 /**
Kojto 122:f9eeca106725 566 * @}
Kojto 122:f9eeca106725 567 */
Kojto 122:f9eeca106725 568
Kojto 122:f9eeca106725 569 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
Kojto 112:6f327212ef96 570 * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
Kojto 112:6f327212ef96 571 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 112:6f327212ef96 572 * is disabled and the application software has to enable this clock before
Kojto 112:6f327212ef96 573 * using it.
Kojto 112:6f327212ef96 574 * @{
Kojto 112:6f327212ef96 575 */
Kojto 112:6f327212ef96 576 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 577 __IO uint32_t tmpreg = 0x00U; \
Kojto 112:6f327212ef96 578 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
Kojto 112:6f327212ef96 579 /* Delay after an RCC peripheral clock enabling */ \
Kojto 112:6f327212ef96 580 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
Kojto 112:6f327212ef96 581 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 582 } while(0)
Kojto 112:6f327212ef96 583 #define __HAL_RCC_USART1_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 584 __IO uint32_t tmpreg = 0x00U; \
Kojto 112:6f327212ef96 585 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
Kojto 112:6f327212ef96 586 /* Delay after an RCC peripheral clock enabling */ \
Kojto 112:6f327212ef96 587 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
Kojto 112:6f327212ef96 588 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 589 } while(0)
Kojto 112:6f327212ef96 590 #define __HAL_RCC_USART6_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 591 __IO uint32_t tmpreg = 0x00U; \
Kojto 112:6f327212ef96 592 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
Kojto 112:6f327212ef96 593 /* Delay after an RCC peripheral clock enabling */ \
Kojto 112:6f327212ef96 594 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
Kojto 112:6f327212ef96 595 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 596 } while(0)
Kojto 112:6f327212ef96 597 #define __HAL_RCC_ADC1_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 598 __IO uint32_t tmpreg = 0x00U; \
Kojto 112:6f327212ef96 599 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
Kojto 112:6f327212ef96 600 /* Delay after an RCC peripheral clock enabling */ \
Kojto 112:6f327212ef96 601 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
Kojto 112:6f327212ef96 602 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 603 } while(0)
Kojto 112:6f327212ef96 604 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 605 __IO uint32_t tmpreg = 0x00U; \
Kojto 112:6f327212ef96 606 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
Kojto 112:6f327212ef96 607 /* Delay after an RCC peripheral clock enabling */ \
Kojto 112:6f327212ef96 608 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
Kojto 112:6f327212ef96 609 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 610 } while(0)
Kojto 112:6f327212ef96 611 #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 612 __IO uint32_t tmpreg = 0x00U; \
Kojto 112:6f327212ef96 613 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
Kojto 112:6f327212ef96 614 /* Delay after an RCC peripheral clock enabling */ \
Kojto 112:6f327212ef96 615 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
Kojto 112:6f327212ef96 616 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 617 } while(0)
Kojto 112:6f327212ef96 618 #define __HAL_RCC_TIM9_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 619 __IO uint32_t tmpreg = 0x00U; \
Kojto 112:6f327212ef96 620 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
Kojto 112:6f327212ef96 621 /* Delay after an RCC peripheral clock enabling */ \
Kojto 112:6f327212ef96 622 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
Kojto 112:6f327212ef96 623 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 624 } while(0)
Kojto 112:6f327212ef96 625 #define __HAL_RCC_TIM11_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 626 __IO uint32_t tmpreg = 0x00U; \
Kojto 112:6f327212ef96 627 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
Kojto 112:6f327212ef96 628 /* Delay after an RCC peripheral clock enabling */ \
Kojto 112:6f327212ef96 629 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
Kojto 112:6f327212ef96 630 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 631 } while(0)
Kojto 112:6f327212ef96 632
Kojto 112:6f327212ef96 633 #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
Kojto 112:6f327212ef96 634 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
Kojto 112:6f327212ef96 635 #define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
Kojto 112:6f327212ef96 636 #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
Kojto 112:6f327212ef96 637 #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
Kojto 112:6f327212ef96 638 #define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
Kojto 112:6f327212ef96 639 #define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
Kojto 112:6f327212ef96 640 #define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
Kojto 112:6f327212ef96 641 /**
Kojto 112:6f327212ef96 642 * @}
Kojto 112:6f327212ef96 643 */
Kojto 112:6f327212ef96 644
Kojto 122:f9eeca106725 645 /** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
Kojto 122:f9eeca106725 646 * @brief Get the enable or disable status of the APB2 peripheral clock.
Kojto 122:f9eeca106725 647 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 122:f9eeca106725 648 * is disabled and the application software has to enable this clock before
Kojto 122:f9eeca106725 649 * using it.
Kojto 122:f9eeca106725 650 * @{
Kojto 122:f9eeca106725 651 */
Kojto 122:f9eeca106725 652 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
Kojto 122:f9eeca106725 653 #define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
Kojto 122:f9eeca106725 654 #define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET)
Kojto 122:f9eeca106725 655 #define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
Kojto 122:f9eeca106725 656 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
Kojto 122:f9eeca106725 657 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)
Kojto 122:f9eeca106725 658 #define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)
Kojto 122:f9eeca106725 659 #define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)
Kojto 122:f9eeca106725 660
Kojto 122:f9eeca106725 661 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
Kojto 122:f9eeca106725 662 #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
Kojto 122:f9eeca106725 663 #define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET)
Kojto 122:f9eeca106725 664 #define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
Kojto 122:f9eeca106725 665 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
Kojto 122:f9eeca106725 666 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)
Kojto 122:f9eeca106725 667 #define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)
Kojto 122:f9eeca106725 668 #define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)
Kojto 122:f9eeca106725 669 /**
Kojto 122:f9eeca106725 670 * @}
Kojto 122:f9eeca106725 671 */
Kojto 122:f9eeca106725 672
Kojto 112:6f327212ef96 673 /** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Force Release Reset
Kojto 112:6f327212ef96 674 * @brief Force or release AHB1 peripheral reset.
Kojto 112:6f327212ef96 675 * @{
Kojto 112:6f327212ef96 676 */
Kojto 122:f9eeca106725 677 #define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU)
Kojto 112:6f327212ef96 678 #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST))
Kojto 112:6f327212ef96 679 #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST))
Kojto 112:6f327212ef96 680 #define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST))
Kojto 112:6f327212ef96 681 #define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST))
Kojto 112:6f327212ef96 682 #define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))
Kojto 112:6f327212ef96 683 #define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
Kojto 112:6f327212ef96 684
Kojto 122:f9eeca106725 685 #define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U)
Kojto 112:6f327212ef96 686 #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
Kojto 112:6f327212ef96 687 #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
Kojto 112:6f327212ef96 688 #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
Kojto 112:6f327212ef96 689 #define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
Kojto 112:6f327212ef96 690 #define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))
Kojto 112:6f327212ef96 691 #define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
Kojto 112:6f327212ef96 692 /**
Kojto 112:6f327212ef96 693 * @}
Kojto 112:6f327212ef96 694 */
Kojto 112:6f327212ef96 695
Kojto 112:6f327212ef96 696 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
Kojto 112:6f327212ef96 697 * @brief Force or release APB1 peripheral reset.
Kojto 112:6f327212ef96 698 * @{
Kojto 112:6f327212ef96 699 */
Kojto 122:f9eeca106725 700 #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU)
Kojto 112:6f327212ef96 701 #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
Kojto 112:6f327212ef96 702 #define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
Kojto 112:6f327212ef96 703 #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
Kojto 112:6f327212ef96 704 #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
Kojto 112:6f327212ef96 705 #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
Kojto 112:6f327212ef96 706 #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
Kojto 112:6f327212ef96 707 #define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
Kojto 112:6f327212ef96 708
Kojto 122:f9eeca106725 709 #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U)
Kojto 112:6f327212ef96 710 #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
Kojto 112:6f327212ef96 711 #define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
Kojto 112:6f327212ef96 712 #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
Kojto 112:6f327212ef96 713 #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
Kojto 112:6f327212ef96 714 #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
Kojto 112:6f327212ef96 715 #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
Kojto 112:6f327212ef96 716 #define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
Kojto 112:6f327212ef96 717 /**
Kojto 112:6f327212ef96 718 * @}
Kojto 112:6f327212ef96 719 */
Kojto 112:6f327212ef96 720
Kojto 112:6f327212ef96 721 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
Kojto 112:6f327212ef96 722 * @brief Force or release APB2 peripheral reset.
Kojto 112:6f327212ef96 723 * @{
Kojto 112:6f327212ef96 724 */
Kojto 122:f9eeca106725 725 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
Kojto 112:6f327212ef96 726 #define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
Kojto 112:6f327212ef96 727 #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
Kojto 112:6f327212ef96 728 #define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
Kojto 112:6f327212ef96 729 #define __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST))
Kojto 112:6f327212ef96 730 #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
Kojto 112:6f327212ef96 731 #define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
Kojto 112:6f327212ef96 732 #define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
Kojto 112:6f327212ef96 733 #define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
Kojto 112:6f327212ef96 734
Kojto 122:f9eeca106725 735 #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U)
Kojto 112:6f327212ef96 736 #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
Kojto 112:6f327212ef96 737 #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
Kojto 112:6f327212ef96 738 #define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
Kojto 112:6f327212ef96 739 #define __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
Kojto 112:6f327212ef96 740 #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
Kojto 112:6f327212ef96 741 #define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
Kojto 112:6f327212ef96 742 #define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
Kojto 112:6f327212ef96 743 #define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
Kojto 112:6f327212ef96 744 /**
Kojto 112:6f327212ef96 745 * @}
Kojto 112:6f327212ef96 746 */
Kojto 112:6f327212ef96 747
Kojto 112:6f327212ef96 748 /** @defgroup RCC_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
Kojto 112:6f327212ef96 749 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
Kojto 112:6f327212ef96 750 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 112:6f327212ef96 751 * power consumption.
Kojto 112:6f327212ef96 752 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
Kojto 112:6f327212ef96 753 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 112:6f327212ef96 754 * @{
Kojto 112:6f327212ef96 755 */
Kojto 112:6f327212ef96 756 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN))
Kojto 112:6f327212ef96 757 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN))
Kojto 112:6f327212ef96 758 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN))
Kojto 112:6f327212ef96 759 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN))
Kojto 112:6f327212ef96 760 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
Kojto 112:6f327212ef96 761 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
Kojto 112:6f327212ef96 762
Kojto 112:6f327212ef96 763 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
Kojto 112:6f327212ef96 764 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
Kojto 112:6f327212ef96 765 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
Kojto 112:6f327212ef96 766 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
Kojto 112:6f327212ef96 767 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))
Kojto 112:6f327212ef96 768 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))
Kojto 112:6f327212ef96 769 /**
Kojto 112:6f327212ef96 770 * @}
Kojto 112:6f327212ef96 771 */
Kojto 112:6f327212ef96 772
Kojto 112:6f327212ef96 773 /** @defgroup RCC_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
Kojto 112:6f327212ef96 774 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
Kojto 112:6f327212ef96 775 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 112:6f327212ef96 776 * power consumption.
Kojto 112:6f327212ef96 777 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
Kojto 112:6f327212ef96 778 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 112:6f327212ef96 779 * @{
Kojto 112:6f327212ef96 780 */
Kojto 112:6f327212ef96 781 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))
Kojto 112:6f327212ef96 782 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN))
Kojto 112:6f327212ef96 783 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN))
Kojto 112:6f327212ef96 784 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN))
Kojto 112:6f327212ef96 785 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN))
Kojto 112:6f327212ef96 786 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN))
Kojto 112:6f327212ef96 787 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN))
Kojto 112:6f327212ef96 788
Kojto 112:6f327212ef96 789 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
Kojto 112:6f327212ef96 790 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
Kojto 112:6f327212ef96 791 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
Kojto 112:6f327212ef96 792 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
Kojto 112:6f327212ef96 793 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
Kojto 112:6f327212ef96 794 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
Kojto 112:6f327212ef96 795 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
Kojto 112:6f327212ef96 796 /**
Kojto 112:6f327212ef96 797 * @}
Kojto 112:6f327212ef96 798 */
Kojto 112:6f327212ef96 799
Kojto 112:6f327212ef96 800 /** @defgroup RCC_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
Kojto 112:6f327212ef96 801 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
Kojto 112:6f327212ef96 802 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 112:6f327212ef96 803 * power consumption.
Kojto 112:6f327212ef96 804 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
Kojto 112:6f327212ef96 805 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 112:6f327212ef96 806 * @{
Kojto 112:6f327212ef96 807 */
Kojto 112:6f327212ef96 808 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN))
Kojto 112:6f327212ef96 809 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN))
Kojto 112:6f327212ef96 810 #define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN))
Kojto 112:6f327212ef96 811 #define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN))
Kojto 112:6f327212ef96 812 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN))
Kojto 112:6f327212ef96 813 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN))
Kojto 112:6f327212ef96 814 #define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN))
Kojto 112:6f327212ef96 815 #define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN))
Kojto 112:6f327212ef96 816
Kojto 112:6f327212ef96 817 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
Kojto 112:6f327212ef96 818 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
Kojto 112:6f327212ef96 819 #define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
Kojto 112:6f327212ef96 820 #define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
Kojto 112:6f327212ef96 821 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
Kojto 112:6f327212ef96 822 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
Kojto 112:6f327212ef96 823 #define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
Kojto 112:6f327212ef96 824 #define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
Kojto 112:6f327212ef96 825 /**
Kojto 112:6f327212ef96 826 * @}
Kojto 112:6f327212ef96 827 */
Kojto 112:6f327212ef96 828
Kojto 112:6f327212ef96 829 /** @defgroup RCC_HSI_Configuration HSI Configuration
Kojto 112:6f327212ef96 830 * @{
Kojto 112:6f327212ef96 831 */
Kojto 112:6f327212ef96 832
Kojto 112:6f327212ef96 833 /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
Kojto 112:6f327212ef96 834 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
Kojto 112:6f327212ef96 835 * It is used (enabled by hardware) as system clock source after startup
Kojto 112:6f327212ef96 836 * from Reset, wake-up from STOP and STANDBY mode, or in case of failure
Kojto 112:6f327212ef96 837 * of the HSE used directly or indirectly as system clock (if the Clock
Kojto 112:6f327212ef96 838 * Security System CSS is enabled).
Kojto 112:6f327212ef96 839 * @note HSI can not be stopped if it is used as system clock source. In this case,
Kojto 112:6f327212ef96 840 * you have to select another source of the system clock then stop the HSI.
Kojto 112:6f327212ef96 841 * @note After enabling the HSI, the application software should wait on HSIRDY
Kojto 112:6f327212ef96 842 * flag to be set indicating that HSI clock is stable and can be used as
Kojto 112:6f327212ef96 843 * system clock source.
Kojto 112:6f327212ef96 844 * This parameter can be: ENABLE or DISABLE.
Kojto 112:6f327212ef96 845 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
Kojto 112:6f327212ef96 846 * clock cycles.
Kojto 112:6f327212ef96 847 */
Kojto 112:6f327212ef96 848 #define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)
Kojto 112:6f327212ef96 849 #define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)
Kojto 112:6f327212ef96 850
Kojto 112:6f327212ef96 851 /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
Kojto 112:6f327212ef96 852 * @note The calibration is used to compensate for the variations in voltage
Kojto 112:6f327212ef96 853 * and temperature that influence the frequency of the internal HSI RC.
Kojto 112:6f327212ef96 854 * @param __HSICalibrationValue__: specifies the calibration trimming value.
Kojto 122:f9eeca106725 855 * (default is RCC_HSICALIBRATION_DEFAULT).
Kojto 112:6f327212ef96 856 * This parameter must be a number between 0 and 0x1F.
Kojto 112:6f327212ef96 857 */
Kojto 112:6f327212ef96 858 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->CR,\
Kojto 112:6f327212ef96 859 RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << POSITION_VAL(RCC_CR_HSITRIM)))
Kojto 112:6f327212ef96 860 /**
Kojto 112:6f327212ef96 861 * @}
Kojto 112:6f327212ef96 862 */
Kojto 112:6f327212ef96 863
Kojto 112:6f327212ef96 864 /** @defgroup RCC_LSI_Configuration LSI Configuration
Kojto 112:6f327212ef96 865 * @{
Kojto 112:6f327212ef96 866 */
Kojto 112:6f327212ef96 867
Kojto 112:6f327212ef96 868 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
Kojto 112:6f327212ef96 869 * @note After enabling the LSI, the application software should wait on
Kojto 112:6f327212ef96 870 * LSIRDY flag to be set indicating that LSI clock is stable and can
Kojto 112:6f327212ef96 871 * be used to clock the IWDG and/or the RTC.
Kojto 112:6f327212ef96 872 * @note LSI can not be disabled if the IWDG is running.
Kojto 112:6f327212ef96 873 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
Kojto 112:6f327212ef96 874 * clock cycles.
Kojto 112:6f327212ef96 875 */
Kojto 112:6f327212ef96 876 #define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)
Kojto 112:6f327212ef96 877 #define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)
Kojto 112:6f327212ef96 878 /**
Kojto 112:6f327212ef96 879 * @}
Kojto 112:6f327212ef96 880 */
Kojto 112:6f327212ef96 881
Kojto 112:6f327212ef96 882 /** @defgroup RCC_HSE_Configuration HSE Configuration
Kojto 112:6f327212ef96 883 * @{
Kojto 112:6f327212ef96 884 */
Kojto 112:6f327212ef96 885
Kojto 112:6f327212ef96 886 /**
Kojto 112:6f327212ef96 887 * @brief Macro to configure the External High Speed oscillator (HSE).
Kojto 112:6f327212ef96 888 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro.
Kojto 112:6f327212ef96 889 * User should request a transition to HSE Off first and then HSE On or HSE Bypass.
Kojto 112:6f327212ef96 890 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
Kojto 112:6f327212ef96 891 * software should wait on HSERDY flag to be set indicating that HSE clock
Kojto 112:6f327212ef96 892 * is stable and can be used to clock the PLL and/or system clock.
Kojto 112:6f327212ef96 893 * @note HSE state can not be changed if it is used directly or through the
Kojto 112:6f327212ef96 894 * PLL as system clock. In this case, you have to select another source
Kojto 112:6f327212ef96 895 * of the system clock then change the HSE state (ex. disable it).
Kojto 112:6f327212ef96 896 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
Kojto 112:6f327212ef96 897 * @note This function reset the CSSON bit, so if the clock security system(CSS)
Kojto 112:6f327212ef96 898 * was previously enabled you have to enable it again after calling this
Kojto 112:6f327212ef96 899 * function.
Kojto 112:6f327212ef96 900 * @param __STATE__: specifies the new state of the HSE.
Kojto 112:6f327212ef96 901 * This parameter can be one of the following values:
Kojto 112:6f327212ef96 902 * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
Kojto 112:6f327212ef96 903 * 6 HSE oscillator clock cycles.
Kojto 112:6f327212ef96 904 * @arg RCC_HSE_ON: turn ON the HSE oscillator.
Kojto 112:6f327212ef96 905 * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
Kojto 112:6f327212ef96 906 */
Kojto 112:6f327212ef96 907 #define __HAL_RCC_HSE_CONFIG(__STATE__) (*(__IO uint8_t *) RCC_CR_BYTE2_ADDRESS = (__STATE__))
Kojto 112:6f327212ef96 908 /**
Kojto 112:6f327212ef96 909 * @}
Kojto 112:6f327212ef96 910 */
Kojto 112:6f327212ef96 911
Kojto 112:6f327212ef96 912 /** @defgroup RCC_LSE_Configuration LSE Configuration
Kojto 112:6f327212ef96 913 * @{
Kojto 112:6f327212ef96 914 */
Kojto 112:6f327212ef96 915
Kojto 112:6f327212ef96 916 /**
Kojto 112:6f327212ef96 917 * @brief Macro to configure the External Low Speed oscillator (LSE).
Kojto 112:6f327212ef96 918 * @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
Kojto 112:6f327212ef96 919 * User should request a transition to LSE Off first and then LSE On or LSE Bypass.
Kojto 112:6f327212ef96 920 * @note As the LSE is in the Backup domain and write access is denied to
Kojto 112:6f327212ef96 921 * this domain after reset, you have to enable write access using
Kojto 112:6f327212ef96 922 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
Kojto 112:6f327212ef96 923 * (to be done once after reset).
Kojto 112:6f327212ef96 924 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
Kojto 112:6f327212ef96 925 * software should wait on LSERDY flag to be set indicating that LSE clock
Kojto 112:6f327212ef96 926 * is stable and can be used to clock the RTC.
Kojto 112:6f327212ef96 927 * @param __STATE__: specifies the new state of the LSE.
Kojto 112:6f327212ef96 928 * This parameter can be one of the following values:
Kojto 112:6f327212ef96 929 * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
Kojto 112:6f327212ef96 930 * 6 LSE oscillator clock cycles.
Kojto 112:6f327212ef96 931 * @arg RCC_LSE_ON: turn ON the LSE oscillator.
Kojto 112:6f327212ef96 932 * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
Kojto 112:6f327212ef96 933 */
Kojto 112:6f327212ef96 934 #define __HAL_RCC_LSE_CONFIG(__STATE__) (*(__IO uint8_t *) RCC_BDCR_BYTE0_ADDRESS = (__STATE__))
Kojto 112:6f327212ef96 935
Kojto 112:6f327212ef96 936 /**
Kojto 112:6f327212ef96 937 * @}
Kojto 112:6f327212ef96 938 */
Kojto 112:6f327212ef96 939
Kojto 112:6f327212ef96 940 /** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration
Kojto 112:6f327212ef96 941 * @{
Kojto 112:6f327212ef96 942 */
Kojto 112:6f327212ef96 943
Kojto 112:6f327212ef96 944 /** @brief Macros to enable or disable the RTC clock.
Kojto 112:6f327212ef96 945 * @note These macros must be used only after the RTC clock source was selected.
Kojto 112:6f327212ef96 946 */
Kojto 112:6f327212ef96 947 #define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE)
Kojto 112:6f327212ef96 948 #define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE)
Kojto 112:6f327212ef96 949
Kojto 112:6f327212ef96 950 /** @brief Macros to configure the RTC clock (RTCCLK).
Kojto 112:6f327212ef96 951 * @note As the RTC clock configuration bits are in the Backup domain and write
Kojto 112:6f327212ef96 952 * access is denied to this domain after reset, you have to enable write
Kojto 112:6f327212ef96 953 * access using the Power Backup Access macro before to configure
Kojto 112:6f327212ef96 954 * the RTC clock source (to be done once after reset).
Kojto 112:6f327212ef96 955 * @note Once the RTC clock is configured it can't be changed unless the
Kojto 112:6f327212ef96 956 * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
Kojto 112:6f327212ef96 957 * a Power On Reset (POR).
Kojto 112:6f327212ef96 958 * @param __RTCCLKSource__: specifies the RTC clock source.
Kojto 112:6f327212ef96 959 * This parameter can be one of the following values:
Kojto 112:6f327212ef96 960 * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
Kojto 112:6f327212ef96 961 * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
Kojto 112:6f327212ef96 962 * @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected
Kojto 112:6f327212ef96 963 * as RTC clock, where x:[2,31]
Kojto 112:6f327212ef96 964 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
Kojto 112:6f327212ef96 965 * work in STOP and STANDBY modes, and can be used as wake-up source.
Kojto 112:6f327212ef96 966 * However, when the HSE clock is used as RTC clock source, the RTC
Kojto 112:6f327212ef96 967 * cannot be used in STOP and STANDBY modes.
Kojto 112:6f327212ef96 968 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
Kojto 112:6f327212ef96 969 * RTC clock source).
Kojto 112:6f327212ef96 970 */
Kojto 112:6f327212ef96 971 #define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \
Kojto 122:f9eeca106725 972 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFFU)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
Kojto 112:6f327212ef96 973
Kojto 112:6f327212ef96 974 #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \
Kojto 122:f9eeca106725 975 RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFFU); \
Kojto 112:6f327212ef96 976 } while (0)
Kojto 112:6f327212ef96 977
Kojto 112:6f327212ef96 978 /** @brief Macros to force or release the Backup domain reset.
Kojto 112:6f327212ef96 979 * @note This function resets the RTC peripheral (including the backup registers)
Kojto 112:6f327212ef96 980 * and the RTC clock source selection in RCC_CSR register.
Kojto 112:6f327212ef96 981 * @note The BKPSRAM is not affected by this reset.
Kojto 112:6f327212ef96 982 */
Kojto 112:6f327212ef96 983 #define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE)
Kojto 112:6f327212ef96 984 #define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE)
Kojto 112:6f327212ef96 985 /**
Kojto 112:6f327212ef96 986 * @}
Kojto 112:6f327212ef96 987 */
Kojto 112:6f327212ef96 988
Kojto 112:6f327212ef96 989 /** @defgroup RCC_PLL_Configuration PLL Configuration
Kojto 112:6f327212ef96 990 * @{
Kojto 112:6f327212ef96 991 */
Kojto 112:6f327212ef96 992
Kojto 112:6f327212ef96 993 /** @brief Macros to enable or disable the main PLL.
Kojto 112:6f327212ef96 994 * @note After enabling the main PLL, the application software should wait on
Kojto 112:6f327212ef96 995 * PLLRDY flag to be set indicating that PLL clock is stable and can
Kojto 112:6f327212ef96 996 * be used as system clock source.
Kojto 112:6f327212ef96 997 * @note The main PLL can not be disabled if it is used as system clock source
Kojto 112:6f327212ef96 998 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
Kojto 112:6f327212ef96 999 */
Kojto 112:6f327212ef96 1000 #define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)
Kojto 112:6f327212ef96 1001 #define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)
Kojto 112:6f327212ef96 1002
Kojto 112:6f327212ef96 1003 /** @brief Macro to configure the PLL clock source.
Kojto 112:6f327212ef96 1004 * @note This function must be used only when the main PLL is disabled.
Kojto 112:6f327212ef96 1005 * @param __PLLSOURCE__: specifies the PLL entry clock source.
Kojto 112:6f327212ef96 1006 * This parameter can be one of the following values:
Kojto 112:6f327212ef96 1007 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
Kojto 112:6f327212ef96 1008 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
Kojto 112:6f327212ef96 1009 *
Kojto 112:6f327212ef96 1010 */
Kojto 112:6f327212ef96 1011 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
Kojto 112:6f327212ef96 1012
Kojto 112:6f327212ef96 1013 /** @brief Macro to configure the PLL multiplication factor.
Kojto 112:6f327212ef96 1014 * @note This function must be used only when the main PLL is disabled.
Kojto 112:6f327212ef96 1015 * @param __PLLM__: specifies the division factor for PLL VCO input clock
Kojto 112:6f327212ef96 1016 * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
Kojto 112:6f327212ef96 1017 * @note You have to set the PLLM parameter correctly to ensure that the VCO input
Kojto 112:6f327212ef96 1018 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
Kojto 112:6f327212ef96 1019 * of 2 MHz to limit PLL jitter.
Kojto 112:6f327212ef96 1020 *
Kojto 112:6f327212ef96 1021 */
Kojto 112:6f327212ef96 1022 #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))
Kojto 112:6f327212ef96 1023 /**
Kojto 112:6f327212ef96 1024 * @}
Kojto 122:f9eeca106725 1025 */
Kojto 122:f9eeca106725 1026
Kojto 112:6f327212ef96 1027 /** @defgroup RCC_Get_Clock_source Get Clock source
Kojto 112:6f327212ef96 1028 * @{
Kojto 112:6f327212ef96 1029 */
Kojto 112:6f327212ef96 1030 /**
Kojto 112:6f327212ef96 1031 * @brief Macro to configure the system clock source.
Kojto 112:6f327212ef96 1032 * @param __RCC_SYSCLKSOURCE__: specifies the system clock source.
Kojto 112:6f327212ef96 1033 * This parameter can be one of the following values:
Kojto 112:6f327212ef96 1034 * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
Kojto 112:6f327212ef96 1035 * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
Kojto 112:6f327212ef96 1036 * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
Kojto 112:6f327212ef96 1037 * - RCC_SYSCLKSOURCE_PLLRCLK: PLLR output is used as system clock source.
Kojto 112:6f327212ef96 1038 */
Kojto 112:6f327212ef96 1039 #define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
Kojto 112:6f327212ef96 1040
Kojto 112:6f327212ef96 1041 /** @brief Macro to get the clock source used as system clock.
Kojto 112:6f327212ef96 1042 * @retval The clock source used as system clock. The returned value can be one
Kojto 112:6f327212ef96 1043 * of the following:
Kojto 112:6f327212ef96 1044 * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
Kojto 112:6f327212ef96 1045 * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
Kojto 112:6f327212ef96 1046 * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
Kojto 112:6f327212ef96 1047 * - RCC_SYSCLKSOURCE_STATUS_PLLRCLK: PLLR used as system clock.
Kojto 112:6f327212ef96 1048 */
Kojto 112:6f327212ef96 1049 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
Kojto 112:6f327212ef96 1050
Kojto 112:6f327212ef96 1051 /** @brief Macro to get the oscillator used as PLL clock source.
Kojto 112:6f327212ef96 1052 * @retval The oscillator used as PLL clock source. The returned value can be one
Kojto 112:6f327212ef96 1053 * of the following:
Kojto 112:6f327212ef96 1054 * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
Kojto 112:6f327212ef96 1055 * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
Kojto 112:6f327212ef96 1056 */
Kojto 112:6f327212ef96 1057 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
Kojto 112:6f327212ef96 1058 /**
Kojto 112:6f327212ef96 1059 * @}
Kojto 112:6f327212ef96 1060 */
Kojto 112:6f327212ef96 1061
Kojto 112:6f327212ef96 1062 /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
Kojto 112:6f327212ef96 1063 * @{
Kojto 112:6f327212ef96 1064 */
Kojto 112:6f327212ef96 1065
Kojto 112:6f327212ef96 1066 /** @brief Macro to configure the MCO1 clock.
Kojto 112:6f327212ef96 1067 * @param __MCOCLKSOURCE__ specifies the MCO clock source.
Kojto 112:6f327212ef96 1068 * This parameter can be one of the following values:
Kojto 112:6f327212ef96 1069 * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
Kojto 112:6f327212ef96 1070 * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
Kojto 112:6f327212ef96 1071 * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
Kojto 112:6f327212ef96 1072 * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
Kojto 112:6f327212ef96 1073 * @param __MCODIV__ specifies the MCO clock prescaler.
Kojto 112:6f327212ef96 1074 * This parameter can be one of the following values:
Kojto 112:6f327212ef96 1075 * @arg RCC_MCODIV_1: no division applied to MCOx clock
Kojto 112:6f327212ef96 1076 * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
Kojto 112:6f327212ef96 1077 * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
Kojto 112:6f327212ef96 1078 * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
Kojto 112:6f327212ef96 1079 * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
Kojto 112:6f327212ef96 1080 */
Kojto 112:6f327212ef96 1081 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
Kojto 112:6f327212ef96 1082 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
Kojto 122:f9eeca106725 1083
Kojto 112:6f327212ef96 1084 /** @brief Macro to configure the MCO2 clock.
Kojto 112:6f327212ef96 1085 * @param __MCOCLKSOURCE__ specifies the MCO clock source.
Kojto 112:6f327212ef96 1086 * This parameter can be one of the following values:
Kojto 112:6f327212ef96 1087 * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
Kojto 112:6f327212ef96 1088 * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx
Kojto 112:6f327212ef96 1089 * @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410Rx devices
Kojto 112:6f327212ef96 1090 * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
Kojto 112:6f327212ef96 1091 * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
Kojto 112:6f327212ef96 1092 * @param __MCODIV__ specifies the MCO clock prescaler.
Kojto 112:6f327212ef96 1093 * This parameter can be one of the following values:
Kojto 112:6f327212ef96 1094 * @arg RCC_MCODIV_1: no division applied to MCOx clock
Kojto 112:6f327212ef96 1095 * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
Kojto 112:6f327212ef96 1096 * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
Kojto 112:6f327212ef96 1097 * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
Kojto 112:6f327212ef96 1098 * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
Kojto 122:f9eeca106725 1099 * @note For STM32F410Rx devices, to output I2SCLK clock on MCO2, you should have
Kojto 122:f9eeca106725 1100 * at least one of the SPI clocks enabled (SPI1, SPI2 or SPI5).
Kojto 112:6f327212ef96 1101 */
Kojto 112:6f327212ef96 1102 #define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
Kojto 122:f9eeca106725 1103 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 3U)));
Kojto 112:6f327212ef96 1104 /**
Kojto 112:6f327212ef96 1105 * @}
Kojto 112:6f327212ef96 1106 */
Kojto 112:6f327212ef96 1107
Kojto 112:6f327212ef96 1108 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
Kojto 112:6f327212ef96 1109 * @brief macros to manage the specified RCC Flags and interrupts.
Kojto 112:6f327212ef96 1110 * @{
Kojto 112:6f327212ef96 1111 */
Kojto 112:6f327212ef96 1112
Kojto 112:6f327212ef96 1113 /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
Kojto 112:6f327212ef96 1114 * the selected interrupts).
Kojto 112:6f327212ef96 1115 * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
Kojto 112:6f327212ef96 1116 * This parameter can be any combination of the following values:
Kojto 112:6f327212ef96 1117 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
Kojto 112:6f327212ef96 1118 * @arg RCC_IT_LSERDY: LSE ready interrupt.
Kojto 112:6f327212ef96 1119 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
Kojto 112:6f327212ef96 1120 * @arg RCC_IT_HSERDY: HSE ready interrupt.
Kojto 112:6f327212ef96 1121 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
Kojto 112:6f327212ef96 1122 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
Kojto 112:6f327212ef96 1123 */
Kojto 112:6f327212ef96 1124 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
Kojto 112:6f327212ef96 1125
Kojto 112:6f327212ef96 1126 /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
Kojto 112:6f327212ef96 1127 * the selected interrupts).
Kojto 112:6f327212ef96 1128 * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
Kojto 112:6f327212ef96 1129 * This parameter can be any combination of the following values:
Kojto 112:6f327212ef96 1130 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
Kojto 112:6f327212ef96 1131 * @arg RCC_IT_LSERDY: LSE ready interrupt.
Kojto 112:6f327212ef96 1132 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
Kojto 112:6f327212ef96 1133 * @arg RCC_IT_HSERDY: HSE ready interrupt.
Kojto 112:6f327212ef96 1134 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
Kojto 112:6f327212ef96 1135 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
Kojto 112:6f327212ef96 1136 */
Kojto 122:f9eeca106725 1137 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
Kojto 112:6f327212ef96 1138
Kojto 112:6f327212ef96 1139 /** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
Kojto 112:6f327212ef96 1140 * bits to clear the selected interrupt pending bits.
Kojto 112:6f327212ef96 1141 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
Kojto 112:6f327212ef96 1142 * This parameter can be any combination of the following values:
Kojto 112:6f327212ef96 1143 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
Kojto 112:6f327212ef96 1144 * @arg RCC_IT_LSERDY: LSE ready interrupt.
Kojto 112:6f327212ef96 1145 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
Kojto 112:6f327212ef96 1146 * @arg RCC_IT_HSERDY: HSE ready interrupt.
Kojto 112:6f327212ef96 1147 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
Kojto 112:6f327212ef96 1148 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
Kojto 112:6f327212ef96 1149 * @arg RCC_IT_CSS: Clock Security System interrupt
Kojto 112:6f327212ef96 1150 */
Kojto 112:6f327212ef96 1151 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
Kojto 112:6f327212ef96 1152
Kojto 112:6f327212ef96 1153 /** @brief Check the RCC's interrupt has occurred or not.
Kojto 112:6f327212ef96 1154 * @param __INTERRUPT__: specifies the RCC interrupt source to check.
Kojto 112:6f327212ef96 1155 * This parameter can be one of the following values:
Kojto 112:6f327212ef96 1156 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
Kojto 112:6f327212ef96 1157 * @arg RCC_IT_LSERDY: LSE ready interrupt.
Kojto 112:6f327212ef96 1158 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
Kojto 112:6f327212ef96 1159 * @arg RCC_IT_HSERDY: HSE ready interrupt.
Kojto 112:6f327212ef96 1160 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
Kojto 112:6f327212ef96 1161 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
Kojto 112:6f327212ef96 1162 * @arg RCC_IT_CSS: Clock Security System interrupt
Kojto 112:6f327212ef96 1163 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
Kojto 112:6f327212ef96 1164 */
Kojto 112:6f327212ef96 1165 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
Kojto 112:6f327212ef96 1166
Kojto 112:6f327212ef96 1167 /** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST,
Kojto 112:6f327212ef96 1168 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
Kojto 112:6f327212ef96 1169 */
Kojto 112:6f327212ef96 1170 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
Kojto 112:6f327212ef96 1171
Kojto 112:6f327212ef96 1172 /** @brief Check RCC flag is set or not.
Kojto 112:6f327212ef96 1173 * @param __FLAG__: specifies the flag to check.
Kojto 112:6f327212ef96 1174 * This parameter can be one of the following values:
Kojto 112:6f327212ef96 1175 * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
Kojto 112:6f327212ef96 1176 * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
Kojto 112:6f327212ef96 1177 * @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
Kojto 112:6f327212ef96 1178 * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready.
Kojto 112:6f327212ef96 1179 * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
Kojto 112:6f327212ef96 1180 * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
Kojto 112:6f327212ef96 1181 * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset.
Kojto 112:6f327212ef96 1182 * @arg RCC_FLAG_PINRST: Pin reset.
Kojto 112:6f327212ef96 1183 * @arg RCC_FLAG_PORRST: POR/PDR reset.
Kojto 112:6f327212ef96 1184 * @arg RCC_FLAG_SFTRST: Software reset.
Kojto 112:6f327212ef96 1185 * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
Kojto 112:6f327212ef96 1186 * @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
Kojto 112:6f327212ef96 1187 * @arg RCC_FLAG_LPWRRST: Low Power reset.
Kojto 112:6f327212ef96 1188 * @retval The new state of __FLAG__ (TRUE or FALSE).
Kojto 112:6f327212ef96 1189 */
Kojto 122:f9eeca106725 1190 #define RCC_FLAG_MASK ((uint8_t)0x1FU)
Kojto 122:f9eeca106725 1191 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR :((((__FLAG__) >> 5U) == 3U)? RCC->CSR :RCC->CIR))) & ((uint32_t)1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)
Kojto 112:6f327212ef96 1192
Kojto 112:6f327212ef96 1193 /**
Kojto 112:6f327212ef96 1194 * @}
Kojto 112:6f327212ef96 1195 */
Kojto 112:6f327212ef96 1196
Kojto 112:6f327212ef96 1197 /**
Kojto 112:6f327212ef96 1198 * @}
Kojto 112:6f327212ef96 1199 */
Kojto 112:6f327212ef96 1200
Kojto 112:6f327212ef96 1201 /* Exported functions --------------------------------------------------------*/
Kojto 112:6f327212ef96 1202 /** @addtogroup RCC_Exported_Functions
Kojto 112:6f327212ef96 1203 * @{
Kojto 112:6f327212ef96 1204 */
Kojto 112:6f327212ef96 1205
Kojto 112:6f327212ef96 1206 /** @addtogroup RCC_Exported_Functions_Group1
Kojto 112:6f327212ef96 1207 * @{
Kojto 112:6f327212ef96 1208 */
Kojto 112:6f327212ef96 1209 /* Initialization and de-initialization functions ******************************/
Kojto 112:6f327212ef96 1210 void HAL_RCC_DeInit(void);
Kojto 112:6f327212ef96 1211 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
Kojto 112:6f327212ef96 1212 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
Kojto 112:6f327212ef96 1213 /**
Kojto 112:6f327212ef96 1214 * @}
Kojto 112:6f327212ef96 1215 */
Kojto 112:6f327212ef96 1216
Kojto 112:6f327212ef96 1217 /** @addtogroup RCC_Exported_Functions_Group2
Kojto 112:6f327212ef96 1218 * @{
Kojto 112:6f327212ef96 1219 */
Kojto 112:6f327212ef96 1220 /* Peripheral Control functions ************************************************/
Kojto 112:6f327212ef96 1221 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
Kojto 112:6f327212ef96 1222 void HAL_RCC_EnableCSS(void);
Kojto 112:6f327212ef96 1223 void HAL_RCC_DisableCSS(void);
Kojto 112:6f327212ef96 1224 uint32_t HAL_RCC_GetSysClockFreq(void);
Kojto 112:6f327212ef96 1225 uint32_t HAL_RCC_GetHCLKFreq(void);
Kojto 112:6f327212ef96 1226 uint32_t HAL_RCC_GetPCLK1Freq(void);
Kojto 112:6f327212ef96 1227 uint32_t HAL_RCC_GetPCLK2Freq(void);
Kojto 112:6f327212ef96 1228 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
Kojto 112:6f327212ef96 1229 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
Kojto 112:6f327212ef96 1230
Kojto 112:6f327212ef96 1231 /* CSS NMI IRQ handler */
Kojto 112:6f327212ef96 1232 void HAL_RCC_NMI_IRQHandler(void);
Kojto 112:6f327212ef96 1233
Kojto 112:6f327212ef96 1234 /* User Callbacks in non blocking mode (IT mode) */
Kojto 112:6f327212ef96 1235 void HAL_RCC_CSSCallback(void);
Kojto 112:6f327212ef96 1236
Kojto 112:6f327212ef96 1237 /**
Kojto 112:6f327212ef96 1238 * @}
Kojto 112:6f327212ef96 1239 */
Kojto 112:6f327212ef96 1240
Kojto 112:6f327212ef96 1241 /**
Kojto 112:6f327212ef96 1242 * @}
Kojto 112:6f327212ef96 1243 */
Kojto 112:6f327212ef96 1244
Kojto 112:6f327212ef96 1245 /* Private types -------------------------------------------------------------*/
Kojto 112:6f327212ef96 1246 /* Private variables ---------------------------------------------------------*/
Kojto 112:6f327212ef96 1247 /* Private constants ---------------------------------------------------------*/
Kojto 112:6f327212ef96 1248 /** @defgroup RCC_Private_Constants RCC Private Constants
Kojto 112:6f327212ef96 1249 * @{
Kojto 112:6f327212ef96 1250 */
Kojto 112:6f327212ef96 1251
Kojto 112:6f327212ef96 1252 /** @defgroup RCC_BitAddress_AliasRegion RCC BitAddress AliasRegion
Kojto 112:6f327212ef96 1253 * @brief RCC registers bit address in the alias region
Kojto 112:6f327212ef96 1254 * @{
Kojto 112:6f327212ef96 1255 */
Kojto 112:6f327212ef96 1256 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
Kojto 112:6f327212ef96 1257 /* --- CR Register ---*/
Kojto 112:6f327212ef96 1258 /* Alias word address of HSION bit */
Kojto 122:f9eeca106725 1259 #define RCC_CR_OFFSET (RCC_OFFSET + 0x00U)
Kojto 122:f9eeca106725 1260 #define RCC_HSION_BIT_NUMBER 0x00U
Kojto 122:f9eeca106725 1261 #define RCC_CR_HSION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_HSION_BIT_NUMBER * 4U))
Kojto 112:6f327212ef96 1262 /* Alias word address of CSSON bit */
Kojto 122:f9eeca106725 1263 #define RCC_CSSON_BIT_NUMBER 0x13U
Kojto 122:f9eeca106725 1264 #define RCC_CR_CSSON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_CSSON_BIT_NUMBER * 4U))
Kojto 112:6f327212ef96 1265 /* Alias word address of PLLON bit */
Kojto 122:f9eeca106725 1266 #define RCC_PLLON_BIT_NUMBER 0x18U
Kojto 122:f9eeca106725 1267 #define RCC_CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLON_BIT_NUMBER * 4U))
Kojto 112:6f327212ef96 1268
Kojto 112:6f327212ef96 1269 /* --- BDCR Register ---*/
Kojto 112:6f327212ef96 1270 /* Alias word address of RTCEN bit */
Kojto 122:f9eeca106725 1271 #define RCC_BDCR_OFFSET (RCC_OFFSET + 0x70U)
Kojto 122:f9eeca106725 1272 #define RCC_RTCEN_BIT_NUMBER 0x0FU
Kojto 122:f9eeca106725 1273 #define RCC_BDCR_RTCEN_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U))
Kojto 112:6f327212ef96 1274 /* Alias word address of BDRST bit */
Kojto 122:f9eeca106725 1275 #define RCC_BDRST_BIT_NUMBER 0x10U
Kojto 122:f9eeca106725 1276 #define RCC_BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_BDRST_BIT_NUMBER * 4U))
Kojto 112:6f327212ef96 1277
Kojto 112:6f327212ef96 1278 /* --- CSR Register ---*/
Kojto 112:6f327212ef96 1279 /* Alias word address of LSION bit */
Kojto 122:f9eeca106725 1280 #define RCC_CSR_OFFSET (RCC_OFFSET + 0x74U)
Kojto 122:f9eeca106725 1281 #define RCC_LSION_BIT_NUMBER 0x00U
Kojto 122:f9eeca106725 1282 #define RCC_CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32U) + (RCC_LSION_BIT_NUMBER * 4U))
Kojto 112:6f327212ef96 1283
Kojto 112:6f327212ef96 1284 /* CR register byte 3 (Bits[23:16]) base address */
Kojto 122:f9eeca106725 1285 #define RCC_CR_BYTE2_ADDRESS ((uint32_t)0x40023802U)
Kojto 112:6f327212ef96 1286
Kojto 112:6f327212ef96 1287 /* CIR register byte 2 (Bits[15:8]) base address */
Kojto 122:f9eeca106725 1288 #define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x01U))
Kojto 112:6f327212ef96 1289
Kojto 112:6f327212ef96 1290 /* CIR register byte 3 (Bits[23:16]) base address */
Kojto 122:f9eeca106725 1291 #define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x02U))
Kojto 112:6f327212ef96 1292
Kojto 112:6f327212ef96 1293 /* BDCR register base address */
Kojto 112:6f327212ef96 1294 #define RCC_BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)
Kojto 112:6f327212ef96 1295
Kojto 122:f9eeca106725 1296 #define RCC_DBP_TIMEOUT_VALUE ((uint32_t)2U)
Kojto 122:f9eeca106725 1297 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
Kojto 112:6f327212ef96 1298
Kojto 112:6f327212ef96 1299 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
Kojto 122:f9eeca106725 1300 #define HSI_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms */
Kojto 122:f9eeca106725 1301 #define LSI_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms */
Kojto 112:6f327212ef96 1302
Kojto 112:6f327212ef96 1303 /**
Kojto 112:6f327212ef96 1304 * @}
Kojto 112:6f327212ef96 1305 */
Kojto 112:6f327212ef96 1306
Kojto 112:6f327212ef96 1307 /**
Kojto 112:6f327212ef96 1308 * @}
Kojto 112:6f327212ef96 1309 */
Kojto 112:6f327212ef96 1310
Kojto 112:6f327212ef96 1311 /* Private macros ------------------------------------------------------------*/
Kojto 122:f9eeca106725 1312 /** @defgroup RCC_Private_Macros RCC Private Macros
Kojto 112:6f327212ef96 1313 * @{
Kojto 112:6f327212ef96 1314 */
Kojto 112:6f327212ef96 1315
Kojto 112:6f327212ef96 1316 /** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters
Kojto 112:6f327212ef96 1317 * @{
Kojto 112:6f327212ef96 1318 */
Kojto 122:f9eeca106725 1319 #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15U)
Kojto 112:6f327212ef96 1320
Kojto 112:6f327212ef96 1321 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
Kojto 112:6f327212ef96 1322 ((HSE) == RCC_HSE_BYPASS))
Kojto 112:6f327212ef96 1323
Kojto 112:6f327212ef96 1324 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
Kojto 112:6f327212ef96 1325 ((LSE) == RCC_LSE_BYPASS))
Kojto 112:6f327212ef96 1326
Kojto 112:6f327212ef96 1327 #define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))
Kojto 112:6f327212ef96 1328
Kojto 112:6f327212ef96 1329 #define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
Kojto 112:6f327212ef96 1330
Kojto 112:6f327212ef96 1331 #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))
Kojto 112:6f327212ef96 1332
Kojto 112:6f327212ef96 1333 #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
Kojto 112:6f327212ef96 1334 ((SOURCE) == RCC_PLLSOURCE_HSE))
Kojto 112:6f327212ef96 1335
Kojto 112:6f327212ef96 1336 #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
Kojto 112:6f327212ef96 1337 ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
Kojto 112:6f327212ef96 1338 ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) || \
Kojto 112:6f327212ef96 1339 ((SOURCE) == RCC_SYSCLKSOURCE_PLLRCLK))
Kojto 112:6f327212ef96 1340
Kojto 122:f9eeca106725 1341 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
Kojto 122:f9eeca106725 1342 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
Kojto 122:f9eeca106725 1343 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) || \
Kojto 122:f9eeca106725 1344 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV3) || \
Kojto 122:f9eeca106725 1345 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) || \
Kojto 122:f9eeca106725 1346 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV5) || \
Kojto 122:f9eeca106725 1347 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV6) || \
Kojto 122:f9eeca106725 1348 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV7) || \
Kojto 122:f9eeca106725 1349 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) || \
Kojto 122:f9eeca106725 1350 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV9) || \
Kojto 122:f9eeca106725 1351 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV10) || \
Kojto 122:f9eeca106725 1352 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV11) || \
Kojto 122:f9eeca106725 1353 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV12) || \
Kojto 122:f9eeca106725 1354 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV13) || \
Kojto 122:f9eeca106725 1355 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV14) || \
Kojto 122:f9eeca106725 1356 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV15) || \
Kojto 122:f9eeca106725 1357 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16) || \
Kojto 122:f9eeca106725 1358 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV17) || \
Kojto 122:f9eeca106725 1359 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV18) || \
Kojto 122:f9eeca106725 1360 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV19) || \
Kojto 122:f9eeca106725 1361 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV20) || \
Kojto 122:f9eeca106725 1362 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV21) || \
Kojto 122:f9eeca106725 1363 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV22) || \
Kojto 122:f9eeca106725 1364 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV23) || \
Kojto 122:f9eeca106725 1365 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV24) || \
Kojto 122:f9eeca106725 1366 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV25) || \
Kojto 122:f9eeca106725 1367 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV26) || \
Kojto 122:f9eeca106725 1368 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV27) || \
Kojto 122:f9eeca106725 1369 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV28) || \
Kojto 122:f9eeca106725 1370 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV29) || \
Kojto 122:f9eeca106725 1371 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV30) || \
Kojto 122:f9eeca106725 1372 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV31))
Kojto 122:f9eeca106725 1373
Kojto 122:f9eeca106725 1374 #define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63U)
Kojto 112:6f327212ef96 1375
Kojto 122:f9eeca106725 1376 #define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2U) || ((VALUE) == 4U) || ((VALUE) == 6U) || ((VALUE) == 8U))
Kojto 112:6f327212ef96 1377
Kojto 122:f9eeca106725 1378 #define IS_RCC_PLLQ_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 15U))
Kojto 112:6f327212ef96 1379
Kojto 112:6f327212ef96 1380 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || \
Kojto 112:6f327212ef96 1381 ((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || \
Kojto 112:6f327212ef96 1382 ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || \
Kojto 112:6f327212ef96 1383 ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \
Kojto 112:6f327212ef96 1384 ((HCLK) == RCC_SYSCLK_DIV512))
Kojto 112:6f327212ef96 1385
Kojto 122:f9eeca106725 1386 #define IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 15U))
Kojto 112:6f327212ef96 1387
Kojto 112:6f327212ef96 1388 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \
Kojto 112:6f327212ef96 1389 ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \
Kojto 112:6f327212ef96 1390 ((PCLK) == RCC_HCLK_DIV16))
Kojto 112:6f327212ef96 1391
Kojto 112:6f327212ef96 1392 #define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2))
Kojto 112:6f327212ef96 1393
Kojto 112:6f327212ef96 1394 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
Kojto 112:6f327212ef96 1395 ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))
Kojto 112:6f327212ef96 1396
Kojto 112:6f327212ef96 1397 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \
Kojto 112:6f327212ef96 1398 ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \
Kojto 112:6f327212ef96 1399 ((DIV) == RCC_MCODIV_5))
Kojto 122:f9eeca106725 1400 #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1FU)
Kojto 112:6f327212ef96 1401
Kojto 112:6f327212ef96 1402 /**
Kojto 112:6f327212ef96 1403 * @}
Kojto 112:6f327212ef96 1404 */
Kojto 112:6f327212ef96 1405
Kojto 112:6f327212ef96 1406 /**
Kojto 112:6f327212ef96 1407 * @}
Kojto 112:6f327212ef96 1408 */
Kojto 112:6f327212ef96 1409
Kojto 112:6f327212ef96 1410 /**
Kojto 112:6f327212ef96 1411 * @}
Kojto 112:6f327212ef96 1412 */
Kojto 112:6f327212ef96 1413
Kojto 112:6f327212ef96 1414 /**
Kojto 112:6f327212ef96 1415 * @}
Kojto 112:6f327212ef96 1416 */
Kojto 112:6f327212ef96 1417
Kojto 112:6f327212ef96 1418 #ifdef __cplusplus
Kojto 112:6f327212ef96 1419 }
Kojto 112:6f327212ef96 1420 #endif
Kojto 112:6f327212ef96 1421
Kojto 112:6f327212ef96 1422 #endif /* __STM32F4xx_HAL_RCC_H */
Kojto 112:6f327212ef96 1423
Kojto 112:6f327212ef96 1424 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/