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Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

TARGET_ARCH_MAX/stm32f4xx_ll_sdmmc.h@122:f9eeca106725, 2016-07-07 (annotated)

Committer:
Kojto
Date:
Thu Jul 07 14:34:11 2016 +0100
Revision:
122:f9eeca106725
Parent:
110:165afa46840b 
Release 122 of the mbed library



Changes:

- new targets - Nucleo L432KC, Beetle, Nucleo F446ZE, Nucleo L011K4

- Thread safety addition - mbed API should contain a statement about thread safety

- critical section API addition

- CAS API (core_util_atomic_incr/decr)

- DEVICE_ are generated from targets.json file, device.h deprecated

- Callback replaces FunctionPointer to provide std like interface

- mbed HAL API docs improvements

- toolchain - prexif attributes with MBED_

            - add new attributes - packed, weak, forcedinline, align

- target.json - contains targets definitions

- ST - L1XX - Cube update to 1.5

     - SPI clock selection fix (clock from APB domain)

     - F7 - Cube update v1.4.0

     - L0 -  baudrate init fix

     - L1 - Cube update v1.5

     - F3 - baudrate init fix, 3 targets CAN support

     - F4 - Cube update v1.12.0, 3 targets CAN support

     - L4XX - Cube update v1.5.1

     - F0 - update Cube to v1.5.0

     - L4 - 2 targets (L476RG/VG) CAN support

- NXP - pwm clock fix for KSDK2 MCU

      - LPC2368 - remove ARM toolchain support - due to regression

      - KSDK2 - fix SPI , I2C address and repeat start

- Silabs - some fixes backported from mbed 3

- Renesas - RZ_A1H - SystemCoreClockUpdate addition

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 89:552587b429a1 1 /**
bogdanm 89:552587b429a1 2 ******************************************************************************
bogdanm 89:552587b429a1 3 * @file stm32f4xx_ll_sdmmc.h
bogdanm 89:552587b429a1 4 * @author MCD Application Team
Kojto 122:f9eeca106725 5 * @version V1.5.0
Kojto 122:f9eeca106725 6 * @date 06-May-2016
bogdanm 89:552587b429a1 7 * @brief Header file of SDMMC HAL module.
bogdanm 89:552587b429a1 8 ******************************************************************************
bogdanm 89:552587b429a1 9 * @attention
bogdanm 89:552587b429a1 10 *
Kojto 122:f9eeca106725 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
bogdanm 89:552587b429a1 12 *
bogdanm 89:552587b429a1 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 89:552587b429a1 14 * are permitted provided that the following conditions are met:
bogdanm 89:552587b429a1 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 89:552587b429a1 16 * this list of conditions and the following disclaimer.
bogdanm 89:552587b429a1 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 89:552587b429a1 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 89:552587b429a1 19 * and/or other materials provided with the distribution.
bogdanm 89:552587b429a1 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 89:552587b429a1 21 * may be used to endorse or promote products derived from this software
bogdanm 89:552587b429a1 22 * without specific prior written permission.
bogdanm 89:552587b429a1 23 *
bogdanm 89:552587b429a1 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 89:552587b429a1 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 89:552587b429a1 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 89:552587b429a1 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 89:552587b429a1 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 89:552587b429a1 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 89:552587b429a1 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 89:552587b429a1 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 89:552587b429a1 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 89:552587b429a1 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 89:552587b429a1 34 *
bogdanm 89:552587b429a1 35 ******************************************************************************
bogdanm 89:552587b429a1 36 */
bogdanm 89:552587b429a1 37
bogdanm 89:552587b429a1 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 89:552587b429a1 39 #ifndef __STM32F4xx_LL_SDMMC_H
bogdanm 89:552587b429a1 40 #define __STM32F4xx_LL_SDMMC_H
bogdanm 89:552587b429a1 41
bogdanm 89:552587b429a1 42 #ifdef __cplusplus
bogdanm 89:552587b429a1 43 extern "C" {
bogdanm 89:552587b429a1 44 #endif
Kojto 110:165afa46840b 45 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
Kojto 110:165afa46840b 46 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
Kojto 110:165afa46840b 47 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
Kojto 122:f9eeca106725 48 defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
Kojto 122:f9eeca106725 49 defined(STM32F412Rx) || defined(STM32F412Cx)
bogdanm 89:552587b429a1 50 /* Includes ------------------------------------------------------------------*/
bogdanm 89:552587b429a1 51 #include "stm32f4xx_hal_def.h"
bogdanm 89:552587b429a1 52
bogdanm 89:552587b429a1 53 /** @addtogroup STM32F4xx_Driver
bogdanm 89:552587b429a1 54 * @{
bogdanm 89:552587b429a1 55 */
bogdanm 89:552587b429a1 56
Kojto 99:dbbf35b96557 57 /** @addtogroup SDMMC_LL
bogdanm 89:552587b429a1 58 * @{
bogdanm 89:552587b429a1 59 */
bogdanm 89:552587b429a1 60
bogdanm 89:552587b429a1 61 /* Exported types ------------------------------------------------------------*/
Kojto 99:dbbf35b96557 62 /** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types
bogdanm 92:4fc01daae5a5 63 * @{
bogdanm 92:4fc01daae5a5 64 */
bogdanm 92:4fc01daae5a5 65
bogdanm 89:552587b429a1 66 /**
bogdanm 89:552587b429a1 67 * @brief SDMMC Configuration Structure definition
bogdanm 89:552587b429a1 68 */
bogdanm 89:552587b429a1 69 typedef struct
bogdanm 89:552587b429a1 70 {
bogdanm 89:552587b429a1 71 uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.
bogdanm 89:552587b429a1 72 This parameter can be a value of @ref SDIO_Clock_Edge */
bogdanm 89:552587b429a1 73
bogdanm 89:552587b429a1 74 uint32_t ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is
bogdanm 89:552587b429a1 75 enabled or disabled.
bogdanm 89:552587b429a1 76 This parameter can be a value of @ref SDIO_Clock_Bypass */
bogdanm 89:552587b429a1 77
bogdanm 89:552587b429a1 78 uint32_t ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or
bogdanm 89:552587b429a1 79 disabled when the bus is idle.
bogdanm 89:552587b429a1 80 This parameter can be a value of @ref SDIO_Clock_Power_Save */
bogdanm 89:552587b429a1 81
bogdanm 89:552587b429a1 82 uint32_t BusWide; /*!< Specifies the SDIO bus width.
bogdanm 89:552587b429a1 83 This parameter can be a value of @ref SDIO_Bus_Wide */
bogdanm 89:552587b429a1 84
bogdanm 89:552587b429a1 85 uint32_t HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.
bogdanm 89:552587b429a1 86 This parameter can be a value of @ref SDIO_Hardware_Flow_Control */
bogdanm 89:552587b429a1 87
bogdanm 89:552587b429a1 88 uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDIO controller.
Kojto 122:f9eeca106725 89 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
bogdanm 89:552587b429a1 90
bogdanm 89:552587b429a1 91 }SDIO_InitTypeDef;
bogdanm 89:552587b429a1 92
bogdanm 89:552587b429a1 93
bogdanm 89:552587b429a1 94 /**
bogdanm 89:552587b429a1 95 * @brief SDIO Command Control structure
bogdanm 89:552587b429a1 96 */
Kojto 122:f9eeca106725 97 typedef struct
bogdanm 89:552587b429a1 98 {
bogdanm 89:552587b429a1 99 uint32_t Argument; /*!< Specifies the SDIO command argument which is sent
bogdanm 89:552587b429a1 100 to a card as part of a command message. If a command
bogdanm 89:552587b429a1 101 contains an argument, it must be loaded into this register
bogdanm 89:552587b429a1 102 before writing the command to the command register. */
bogdanm 89:552587b429a1 103
bogdanm 89:552587b429a1 104 uint32_t CmdIndex; /*!< Specifies the SDIO command index. It must be Min_Data = 0 and
bogdanm 89:552587b429a1 105 Max_Data = 64 */
bogdanm 89:552587b429a1 106
bogdanm 89:552587b429a1 107 uint32_t Response; /*!< Specifies the SDIO response type.
bogdanm 89:552587b429a1 108 This parameter can be a value of @ref SDIO_Response_Type */
bogdanm 89:552587b429a1 109
bogdanm 89:552587b429a1 110 uint32_t WaitForInterrupt; /*!< Specifies whether SDIO wait for interrupt request is
bogdanm 89:552587b429a1 111 enabled or disabled.
bogdanm 89:552587b429a1 112 This parameter can be a value of @ref SDIO_Wait_Interrupt_State */
bogdanm 89:552587b429a1 113
bogdanm 89:552587b429a1 114 uint32_t CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM)
bogdanm 89:552587b429a1 115 is enabled or disabled.
bogdanm 89:552587b429a1 116 This parameter can be a value of @ref SDIO_CPSM_State */
bogdanm 89:552587b429a1 117 }SDIO_CmdInitTypeDef;
bogdanm 89:552587b429a1 118
bogdanm 89:552587b429a1 119
bogdanm 89:552587b429a1 120 /**
bogdanm 89:552587b429a1 121 * @brief SDIO Data Control structure
bogdanm 89:552587b429a1 122 */
bogdanm 89:552587b429a1 123 typedef struct
bogdanm 89:552587b429a1 124 {
bogdanm 89:552587b429a1 125 uint32_t DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */
bogdanm 89:552587b429a1 126
bogdanm 89:552587b429a1 127 uint32_t DataLength; /*!< Specifies the number of data bytes to be transferred. */
bogdanm 89:552587b429a1 128
bogdanm 89:552587b429a1 129 uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer.
bogdanm 89:552587b429a1 130 This parameter can be a value of @ref SDIO_Data_Block_Size */
bogdanm 89:552587b429a1 131
bogdanm 89:552587b429a1 132 uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer
bogdanm 89:552587b429a1 133 is a read or write.
bogdanm 89:552587b429a1 134 This parameter can be a value of @ref SDIO_Transfer_Direction */
bogdanm 89:552587b429a1 135
bogdanm 89:552587b429a1 136 uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
bogdanm 89:552587b429a1 137 This parameter can be a value of @ref SDIO_Transfer_Type */
bogdanm 89:552587b429a1 138
bogdanm 89:552587b429a1 139 uint32_t DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM)
bogdanm 89:552587b429a1 140 is enabled or disabled.
bogdanm 89:552587b429a1 141 This parameter can be a value of @ref SDIO_DPSM_State */
bogdanm 89:552587b429a1 142 }SDIO_DataInitTypeDef;
bogdanm 89:552587b429a1 143
bogdanm 92:4fc01daae5a5 144 /**
bogdanm 92:4fc01daae5a5 145 * @}
bogdanm 92:4fc01daae5a5 146 */
bogdanm 92:4fc01daae5a5 147
bogdanm 89:552587b429a1 148 /* Exported constants --------------------------------------------------------*/
Kojto 99:dbbf35b96557 149 /** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
bogdanm 89:552587b429a1 150 * @{
bogdanm 89:552587b429a1 151 */
bogdanm 89:552587b429a1 152
Kojto 99:dbbf35b96557 153 /** @defgroup SDIO_Clock_Edge Clock Edge
bogdanm 89:552587b429a1 154 * @{
bogdanm 89:552587b429a1 155 */
Kojto 122:f9eeca106725 156 #define SDIO_CLOCK_EDGE_RISING ((uint32_t)0x00000000U)
bogdanm 92:4fc01daae5a5 157 #define SDIO_CLOCK_EDGE_FALLING SDIO_CLKCR_NEGEDGE
bogdanm 89:552587b429a1 158
bogdanm 89:552587b429a1 159 #define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) || \
bogdanm 89:552587b429a1 160 ((EDGE) == SDIO_CLOCK_EDGE_FALLING))
bogdanm 89:552587b429a1 161 /**
bogdanm 89:552587b429a1 162 * @}
bogdanm 89:552587b429a1 163 */
bogdanm 89:552587b429a1 164
Kojto 99:dbbf35b96557 165 /** @defgroup SDIO_Clock_Bypass Clock Bypass
bogdanm 89:552587b429a1 166 * @{
bogdanm 89:552587b429a1 167 */
Kojto 122:f9eeca106725 168 #define SDIO_CLOCK_BYPASS_DISABLE ((uint32_t)0x00000000U)
bogdanm 92:4fc01daae5a5 169 #define SDIO_CLOCK_BYPASS_ENABLE SDIO_CLKCR_BYPASS
bogdanm 89:552587b429a1 170
bogdanm 89:552587b429a1 171 #define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) || \
bogdanm 89:552587b429a1 172 ((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE))
bogdanm 89:552587b429a1 173 /**
bogdanm 89:552587b429a1 174 * @}
bogdanm 89:552587b429a1 175 */
bogdanm 89:552587b429a1 176
Kojto 99:dbbf35b96557 177 /** @defgroup SDIO_Clock_Power_Save Clock Power Saving
bogdanm 89:552587b429a1 178 * @{
bogdanm 89:552587b429a1 179 */
Kojto 122:f9eeca106725 180 #define SDIO_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000U)
bogdanm 92:4fc01daae5a5 181 #define SDIO_CLOCK_POWER_SAVE_ENABLE SDIO_CLKCR_PWRSAV
bogdanm 89:552587b429a1 182
bogdanm 89:552587b429a1 183 #define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) || \
bogdanm 89:552587b429a1 184 ((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE))
bogdanm 89:552587b429a1 185 /**
bogdanm 89:552587b429a1 186 * @}
bogdanm 89:552587b429a1 187 */
bogdanm 89:552587b429a1 188
Kojto 99:dbbf35b96557 189 /** @defgroup SDIO_Bus_Wide Bus Width
bogdanm 89:552587b429a1 190 * @{
bogdanm 89:552587b429a1 191 */
Kojto 122:f9eeca106725 192 #define SDIO_BUS_WIDE_1B ((uint32_t)0x00000000U)
bogdanm 92:4fc01daae5a5 193 #define SDIO_BUS_WIDE_4B SDIO_CLKCR_WIDBUS_0
bogdanm 92:4fc01daae5a5 194 #define SDIO_BUS_WIDE_8B SDIO_CLKCR_WIDBUS_1
bogdanm 89:552587b429a1 195
bogdanm 89:552587b429a1 196 #define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BUS_WIDE_1B) || \
bogdanm 89:552587b429a1 197 ((WIDE) == SDIO_BUS_WIDE_4B) || \
bogdanm 89:552587b429a1 198 ((WIDE) == SDIO_BUS_WIDE_8B))
bogdanm 89:552587b429a1 199 /**
bogdanm 89:552587b429a1 200 * @}
bogdanm 89:552587b429a1 201 */
bogdanm 89:552587b429a1 202
Kojto 99:dbbf35b96557 203 /** @defgroup SDIO_Hardware_Flow_Control Hardware Flow Control
bogdanm 89:552587b429a1 204 * @{
bogdanm 89:552587b429a1 205 */
Kojto 122:f9eeca106725 206 #define SDIO_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000U)
bogdanm 92:4fc01daae5a5 207 #define SDIO_HARDWARE_FLOW_CONTROL_ENABLE SDIO_CLKCR_HWFC_EN
bogdanm 89:552587b429a1 208
bogdanm 89:552587b429a1 209 #define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) || \
bogdanm 89:552587b429a1 210 ((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE))
bogdanm 89:552587b429a1 211 /**
bogdanm 89:552587b429a1 212 * @}
bogdanm 89:552587b429a1 213 */
bogdanm 89:552587b429a1 214
Kojto 99:dbbf35b96557 215 /** @defgroup SDIO_Clock_Division Clock Division
bogdanm 89:552587b429a1 216 * @{
bogdanm 89:552587b429a1 217 */
Kojto 122:f9eeca106725 218 #define IS_SDIO_CLKDIV(DIV) ((DIV) <= 0xFFU)
bogdanm 89:552587b429a1 219 /**
bogdanm 89:552587b429a1 220 * @}
bogdanm 89:552587b429a1 221 */
bogdanm 89:552587b429a1 222
Kojto 99:dbbf35b96557 223 /** @defgroup SDIO_Command_Index Command Index
bogdanm 89:552587b429a1 224 * @{
bogdanm 89:552587b429a1 225 */
Kojto 122:f9eeca106725 226 #define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40U)
bogdanm 89:552587b429a1 227 /**
bogdanm 89:552587b429a1 228 * @}
bogdanm 89:552587b429a1 229 */
bogdanm 89:552587b429a1 230
Kojto 99:dbbf35b96557 231 /** @defgroup SDIO_Response_Type Response Type
bogdanm 89:552587b429a1 232 * @{
bogdanm 89:552587b429a1 233 */
Kojto 122:f9eeca106725 234 #define SDIO_RESPONSE_NO ((uint32_t)0x00000000U)
bogdanm 92:4fc01daae5a5 235 #define SDIO_RESPONSE_SHORT SDIO_CMD_WAITRESP_0
bogdanm 92:4fc01daae5a5 236 #define SDIO_RESPONSE_LONG SDIO_CMD_WAITRESP
bogdanm 89:552587b429a1 237
bogdanm 89:552587b429a1 238 #define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_NO) || \
bogdanm 89:552587b429a1 239 ((RESPONSE) == SDIO_RESPONSE_SHORT) || \
bogdanm 89:552587b429a1 240 ((RESPONSE) == SDIO_RESPONSE_LONG))
bogdanm 89:552587b429a1 241 /**
bogdanm 89:552587b429a1 242 * @}
bogdanm 89:552587b429a1 243 */
bogdanm 89:552587b429a1 244
Kojto 99:dbbf35b96557 245 /** @defgroup SDIO_Wait_Interrupt_State Wait Interrupt
bogdanm 89:552587b429a1 246 * @{
bogdanm 89:552587b429a1 247 */
Kojto 122:f9eeca106725 248 #define SDIO_WAIT_NO ((uint32_t)0x00000000U)
bogdanm 92:4fc01daae5a5 249 #define SDIO_WAIT_IT SDIO_CMD_WAITINT
bogdanm 92:4fc01daae5a5 250 #define SDIO_WAIT_PEND SDIO_CMD_WAITPEND
bogdanm 89:552587b429a1 251
bogdanm 89:552587b429a1 252 #define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) || \
bogdanm 89:552587b429a1 253 ((WAIT) == SDIO_WAIT_IT) || \
bogdanm 89:552587b429a1 254 ((WAIT) == SDIO_WAIT_PEND))
bogdanm 89:552587b429a1 255 /**
bogdanm 89:552587b429a1 256 * @}
bogdanm 89:552587b429a1 257 */
bogdanm 89:552587b429a1 258
Kojto 99:dbbf35b96557 259 /** @defgroup SDIO_CPSM_State CPSM State
bogdanm 89:552587b429a1 260 * @{
bogdanm 89:552587b429a1 261 */
Kojto 122:f9eeca106725 262 #define SDIO_CPSM_DISABLE ((uint32_t)0x00000000U)
bogdanm 92:4fc01daae5a5 263 #define SDIO_CPSM_ENABLE SDIO_CMD_CPSMEN
bogdanm 89:552587b429a1 264
bogdanm 89:552587b429a1 265 #define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) || \
bogdanm 89:552587b429a1 266 ((CPSM) == SDIO_CPSM_ENABLE))
bogdanm 89:552587b429a1 267 /**
bogdanm 89:552587b429a1 268 * @}
bogdanm 89:552587b429a1 269 */
bogdanm 89:552587b429a1 270
Kojto 99:dbbf35b96557 271 /** @defgroup SDIO_Response_Registers Response Register
bogdanm 89:552587b429a1 272 * @{
bogdanm 89:552587b429a1 273 */
Kojto 122:f9eeca106725 274 #define SDIO_RESP1 ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 275 #define SDIO_RESP2 ((uint32_t)0x00000004U)
Kojto 122:f9eeca106725 276 #define SDIO_RESP3 ((uint32_t)0x00000008U)
Kojto 122:f9eeca106725 277 #define SDIO_RESP4 ((uint32_t)0x0000000CU)
bogdanm 89:552587b429a1 278
bogdanm 89:552587b429a1 279 #define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || \
bogdanm 89:552587b429a1 280 ((RESP) == SDIO_RESP2) || \
bogdanm 89:552587b429a1 281 ((RESP) == SDIO_RESP3) || \
bogdanm 89:552587b429a1 282 ((RESP) == SDIO_RESP4))
bogdanm 89:552587b429a1 283 /**
bogdanm 89:552587b429a1 284 * @}
bogdanm 89:552587b429a1 285 */
bogdanm 89:552587b429a1 286
Kojto 99:dbbf35b96557 287 /** @defgroup SDIO_Data_Length Data Lenght
bogdanm 89:552587b429a1 288 * @{
bogdanm 89:552587b429a1 289 */
Kojto 122:f9eeca106725 290 #define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU)
bogdanm 89:552587b429a1 291 /**
bogdanm 89:552587b429a1 292 * @}
bogdanm 89:552587b429a1 293 */
bogdanm 89:552587b429a1 294
Kojto 99:dbbf35b96557 295 /** @defgroup SDIO_Data_Block_Size Data Block Size
bogdanm 89:552587b429a1 296 * @{
bogdanm 89:552587b429a1 297 */
Kojto 122:f9eeca106725 298 #define SDIO_DATABLOCK_SIZE_1B ((uint32_t)0x00000000U)
bogdanm 92:4fc01daae5a5 299 #define SDIO_DATABLOCK_SIZE_2B SDIO_DCTRL_DBLOCKSIZE_0
bogdanm 92:4fc01daae5a5 300 #define SDIO_DATABLOCK_SIZE_4B SDIO_DCTRL_DBLOCKSIZE_1
Kojto 122:f9eeca106725 301 #define SDIO_DATABLOCK_SIZE_8B ((uint32_t)0x00000030U)
bogdanm 92:4fc01daae5a5 302 #define SDIO_DATABLOCK_SIZE_16B SDIO_DCTRL_DBLOCKSIZE_2
Kojto 122:f9eeca106725 303 #define SDIO_DATABLOCK_SIZE_32B ((uint32_t)0x00000050U)
Kojto 122:f9eeca106725 304 #define SDIO_DATABLOCK_SIZE_64B ((uint32_t)0x00000060U)
Kojto 122:f9eeca106725 305 #define SDIO_DATABLOCK_SIZE_128B ((uint32_t)0x00000070U)
bogdanm 92:4fc01daae5a5 306 #define SDIO_DATABLOCK_SIZE_256B SDIO_DCTRL_DBLOCKSIZE_3
Kojto 122:f9eeca106725 307 #define SDIO_DATABLOCK_SIZE_512B ((uint32_t)0x00000090U)
Kojto 122:f9eeca106725 308 #define SDIO_DATABLOCK_SIZE_1024B ((uint32_t)0x000000A0U)
Kojto 122:f9eeca106725 309 #define SDIO_DATABLOCK_SIZE_2048B ((uint32_t)0x000000B0U)
Kojto 122:f9eeca106725 310 #define SDIO_DATABLOCK_SIZE_4096B ((uint32_t)0x000000C0U)
Kojto 122:f9eeca106725 311 #define SDIO_DATABLOCK_SIZE_8192B ((uint32_t)0x000000D0U)
Kojto 122:f9eeca106725 312 #define SDIO_DATABLOCK_SIZE_16384B ((uint32_t)0x000000E0U)
bogdanm 89:552587b429a1 313
bogdanm 89:552587b429a1 314 #define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DATABLOCK_SIZE_1B) || \
bogdanm 89:552587b429a1 315 ((SIZE) == SDIO_DATABLOCK_SIZE_2B) || \
bogdanm 89:552587b429a1 316 ((SIZE) == SDIO_DATABLOCK_SIZE_4B) || \
bogdanm 89:552587b429a1 317 ((SIZE) == SDIO_DATABLOCK_SIZE_8B) || \
bogdanm 89:552587b429a1 318 ((SIZE) == SDIO_DATABLOCK_SIZE_16B) || \
bogdanm 89:552587b429a1 319 ((SIZE) == SDIO_DATABLOCK_SIZE_32B) || \
bogdanm 89:552587b429a1 320 ((SIZE) == SDIO_DATABLOCK_SIZE_64B) || \
bogdanm 89:552587b429a1 321 ((SIZE) == SDIO_DATABLOCK_SIZE_128B) || \
bogdanm 89:552587b429a1 322 ((SIZE) == SDIO_DATABLOCK_SIZE_256B) || \
bogdanm 89:552587b429a1 323 ((SIZE) == SDIO_DATABLOCK_SIZE_512B) || \
bogdanm 89:552587b429a1 324 ((SIZE) == SDIO_DATABLOCK_SIZE_1024B) || \
bogdanm 89:552587b429a1 325 ((SIZE) == SDIO_DATABLOCK_SIZE_2048B) || \
bogdanm 89:552587b429a1 326 ((SIZE) == SDIO_DATABLOCK_SIZE_4096B) || \
bogdanm 89:552587b429a1 327 ((SIZE) == SDIO_DATABLOCK_SIZE_8192B) || \
bogdanm 89:552587b429a1 328 ((SIZE) == SDIO_DATABLOCK_SIZE_16384B))
bogdanm 89:552587b429a1 329 /**
bogdanm 89:552587b429a1 330 * @}
bogdanm 89:552587b429a1 331 */
bogdanm 89:552587b429a1 332
Kojto 99:dbbf35b96557 333 /** @defgroup SDIO_Transfer_Direction Transfer Direction
bogdanm 89:552587b429a1 334 * @{
bogdanm 89:552587b429a1 335 */
Kojto 122:f9eeca106725 336 #define SDIO_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000U)
bogdanm 92:4fc01daae5a5 337 #define SDIO_TRANSFER_DIR_TO_SDIO SDIO_DCTRL_DTDIR
bogdanm 89:552587b429a1 338
bogdanm 89:552587b429a1 339 #define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) || \
bogdanm 89:552587b429a1 340 ((DIR) == SDIO_TRANSFER_DIR_TO_SDIO))
bogdanm 89:552587b429a1 341 /**
bogdanm 89:552587b429a1 342 * @}
bogdanm 89:552587b429a1 343 */
bogdanm 89:552587b429a1 344
Kojto 99:dbbf35b96557 345 /** @defgroup SDIO_Transfer_Type Transfer Type
bogdanm 89:552587b429a1 346 * @{
bogdanm 89:552587b429a1 347 */
Kojto 122:f9eeca106725 348 #define SDIO_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000U)
bogdanm 92:4fc01daae5a5 349 #define SDIO_TRANSFER_MODE_STREAM SDIO_DCTRL_DTMODE
bogdanm 89:552587b429a1 350
bogdanm 89:552587b429a1 351 #define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) || \
bogdanm 89:552587b429a1 352 ((MODE) == SDIO_TRANSFER_MODE_STREAM))
bogdanm 89:552587b429a1 353 /**
bogdanm 89:552587b429a1 354 * @}
bogdanm 89:552587b429a1 355 */
bogdanm 89:552587b429a1 356
Kojto 99:dbbf35b96557 357 /** @defgroup SDIO_DPSM_State DPSM State
bogdanm 89:552587b429a1 358 * @{
bogdanm 89:552587b429a1 359 */
Kojto 122:f9eeca106725 360 #define SDIO_DPSM_DISABLE ((uint32_t)0x00000000U)
bogdanm 92:4fc01daae5a5 361 #define SDIO_DPSM_ENABLE SDIO_DCTRL_DTEN
bogdanm 89:552587b429a1 362
bogdanm 89:552587b429a1 363 #define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) ||\
bogdanm 89:552587b429a1 364 ((DPSM) == SDIO_DPSM_ENABLE))
bogdanm 89:552587b429a1 365 /**
bogdanm 89:552587b429a1 366 * @}
bogdanm 89:552587b429a1 367 */
bogdanm 89:552587b429a1 368
Kojto 99:dbbf35b96557 369 /** @defgroup SDIO_Read_Wait_Mode Read Wait Mode
bogdanm 89:552587b429a1 370 * @{
bogdanm 89:552587b429a1 371 */
Kojto 122:f9eeca106725 372 #define SDIO_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 373 #define SDIO_READ_WAIT_MODE_CLK ((uint32_t)0x00000001U)
bogdanm 89:552587b429a1 374
bogdanm 89:552587b429a1 375 #define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) || \
bogdanm 89:552587b429a1 376 ((MODE) == SDIO_READ_WAIT_MODE_DATA2))
bogdanm 89:552587b429a1 377 /**
bogdanm 89:552587b429a1 378 * @}
bogdanm 89:552587b429a1 379 */
bogdanm 89:552587b429a1 380
Kojto 99:dbbf35b96557 381 /** @defgroup SDIO_Interrupt_sources Interrupt Sources
bogdanm 89:552587b429a1 382 * @{
bogdanm 89:552587b429a1 383 */
bogdanm 92:4fc01daae5a5 384 #define SDIO_IT_CCRCFAIL SDIO_STA_CCRCFAIL
bogdanm 92:4fc01daae5a5 385 #define SDIO_IT_DCRCFAIL SDIO_STA_DCRCFAIL
bogdanm 92:4fc01daae5a5 386 #define SDIO_IT_CTIMEOUT SDIO_STA_CTIMEOUT
bogdanm 92:4fc01daae5a5 387 #define SDIO_IT_DTIMEOUT SDIO_STA_DTIMEOUT
bogdanm 92:4fc01daae5a5 388 #define SDIO_IT_TXUNDERR SDIO_STA_TXUNDERR
bogdanm 92:4fc01daae5a5 389 #define SDIO_IT_RXOVERR SDIO_STA_RXOVERR
bogdanm 92:4fc01daae5a5 390 #define SDIO_IT_CMDREND SDIO_STA_CMDREND
bogdanm 92:4fc01daae5a5 391 #define SDIO_IT_CMDSENT SDIO_STA_CMDSENT
bogdanm 92:4fc01daae5a5 392 #define SDIO_IT_DATAEND SDIO_STA_DATAEND
bogdanm 92:4fc01daae5a5 393 #define SDIO_IT_STBITERR SDIO_STA_STBITERR
bogdanm 92:4fc01daae5a5 394 #define SDIO_IT_DBCKEND SDIO_STA_DBCKEND
bogdanm 92:4fc01daae5a5 395 #define SDIO_IT_CMDACT SDIO_STA_CMDACT
bogdanm 92:4fc01daae5a5 396 #define SDIO_IT_TXACT SDIO_STA_TXACT
bogdanm 92:4fc01daae5a5 397 #define SDIO_IT_RXACT SDIO_STA_RXACT
bogdanm 92:4fc01daae5a5 398 #define SDIO_IT_TXFIFOHE SDIO_STA_TXFIFOHE
bogdanm 92:4fc01daae5a5 399 #define SDIO_IT_RXFIFOHF SDIO_STA_RXFIFOHF
bogdanm 92:4fc01daae5a5 400 #define SDIO_IT_TXFIFOF SDIO_STA_TXFIFOF
bogdanm 92:4fc01daae5a5 401 #define SDIO_IT_RXFIFOF SDIO_STA_RXFIFOF
bogdanm 92:4fc01daae5a5 402 #define SDIO_IT_TXFIFOE SDIO_STA_TXFIFOE
bogdanm 92:4fc01daae5a5 403 #define SDIO_IT_RXFIFOE SDIO_STA_RXFIFOE
bogdanm 92:4fc01daae5a5 404 #define SDIO_IT_TXDAVL SDIO_STA_TXDAVL
bogdanm 92:4fc01daae5a5 405 #define SDIO_IT_RXDAVL SDIO_STA_RXDAVL
bogdanm 92:4fc01daae5a5 406 #define SDIO_IT_SDIOIT SDIO_STA_SDIOIT
bogdanm 92:4fc01daae5a5 407 #define SDIO_IT_CEATAEND SDIO_STA_CEATAEND
bogdanm 89:552587b429a1 408 /**
bogdanm 89:552587b429a1 409 * @}
bogdanm 89:552587b429a1 410 */
bogdanm 89:552587b429a1 411
Kojto 99:dbbf35b96557 412 /** @defgroup SDIO_Flags Flags
bogdanm 89:552587b429a1 413 * @{
bogdanm 89:552587b429a1 414 */
bogdanm 92:4fc01daae5a5 415 #define SDIO_FLAG_CCRCFAIL SDIO_STA_CCRCFAIL
bogdanm 92:4fc01daae5a5 416 #define SDIO_FLAG_DCRCFAIL SDIO_STA_DCRCFAIL
bogdanm 92:4fc01daae5a5 417 #define SDIO_FLAG_CTIMEOUT SDIO_STA_CTIMEOUT
bogdanm 92:4fc01daae5a5 418 #define SDIO_FLAG_DTIMEOUT SDIO_STA_DTIMEOUT
bogdanm 92:4fc01daae5a5 419 #define SDIO_FLAG_TXUNDERR SDIO_STA_TXUNDERR
bogdanm 92:4fc01daae5a5 420 #define SDIO_FLAG_RXOVERR SDIO_STA_RXOVERR
bogdanm 92:4fc01daae5a5 421 #define SDIO_FLAG_CMDREND SDIO_STA_CMDREND
bogdanm 92:4fc01daae5a5 422 #define SDIO_FLAG_CMDSENT SDIO_STA_CMDSENT
bogdanm 92:4fc01daae5a5 423 #define SDIO_FLAG_DATAEND SDIO_STA_DATAEND
bogdanm 92:4fc01daae5a5 424 #define SDIO_FLAG_STBITERR SDIO_STA_STBITERR
bogdanm 92:4fc01daae5a5 425 #define SDIO_FLAG_DBCKEND SDIO_STA_DBCKEND
bogdanm 92:4fc01daae5a5 426 #define SDIO_FLAG_CMDACT SDIO_STA_CMDACT
bogdanm 92:4fc01daae5a5 427 #define SDIO_FLAG_TXACT SDIO_STA_TXACT
bogdanm 92:4fc01daae5a5 428 #define SDIO_FLAG_RXACT SDIO_STA_RXACT
bogdanm 92:4fc01daae5a5 429 #define SDIO_FLAG_TXFIFOHE SDIO_STA_TXFIFOHE
bogdanm 92:4fc01daae5a5 430 #define SDIO_FLAG_RXFIFOHF SDIO_STA_RXFIFOHF
bogdanm 92:4fc01daae5a5 431 #define SDIO_FLAG_TXFIFOF SDIO_STA_TXFIFOF
bogdanm 92:4fc01daae5a5 432 #define SDIO_FLAG_RXFIFOF SDIO_STA_RXFIFOF
bogdanm 92:4fc01daae5a5 433 #define SDIO_FLAG_TXFIFOE SDIO_STA_TXFIFOE
bogdanm 92:4fc01daae5a5 434 #define SDIO_FLAG_RXFIFOE SDIO_STA_RXFIFOE
bogdanm 92:4fc01daae5a5 435 #define SDIO_FLAG_TXDAVL SDIO_STA_TXDAVL
bogdanm 92:4fc01daae5a5 436 #define SDIO_FLAG_RXDAVL SDIO_STA_RXDAVL
bogdanm 92:4fc01daae5a5 437 #define SDIO_FLAG_SDIOIT SDIO_STA_SDIOIT
bogdanm 92:4fc01daae5a5 438 #define SDIO_FLAG_CEATAEND SDIO_STA_CEATAEND
Kojto 99:dbbf35b96557 439 /**
Kojto 99:dbbf35b96557 440 * @}
Kojto 99:dbbf35b96557 441 */
bogdanm 89:552587b429a1 442
bogdanm 89:552587b429a1 443 /**
bogdanm 89:552587b429a1 444 * @}
bogdanm 89:552587b429a1 445 */
Kojto 99:dbbf35b96557 446 /* Exported macro ------------------------------------------------------------*/
Kojto 99:dbbf35b96557 447 /** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros
bogdanm 89:552587b429a1 448 * @{
Kojto 99:dbbf35b96557 449 */
bogdanm 89:552587b429a1 450
Kojto 99:dbbf35b96557 451 /** @defgroup SDMMC_LL_Alias_Region Bit Address in the alias region
Kojto 99:dbbf35b96557 452 * @{
bogdanm 89:552587b429a1 453 */
bogdanm 89:552587b429a1 454 /* ------------ SDIO registers bit address in the alias region -------------- */
bogdanm 89:552587b429a1 455 #define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
bogdanm 89:552587b429a1 456
bogdanm 89:552587b429a1 457 /* --- CLKCR Register ---*/
bogdanm 89:552587b429a1 458 /* Alias word address of CLKEN bit */
Kojto 122:f9eeca106725 459 #define CLKCR_OFFSET (SDIO_OFFSET + 0x04U)
Kojto 122:f9eeca106725 460 #define CLKEN_BITNUMBER 0x08U
Kojto 122:f9eeca106725 461 #define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32U) + (CLKEN_BITNUMBER * 4U))
bogdanm 89:552587b429a1 462
bogdanm 89:552587b429a1 463 /* --- CMD Register ---*/
bogdanm 89:552587b429a1 464 /* Alias word address of SDIOSUSPEND bit */
Kojto 122:f9eeca106725 465 #define CMD_OFFSET (SDIO_OFFSET + 0x0CU)
Kojto 122:f9eeca106725 466 #define SDIOSUSPEND_BITNUMBER 0x0BU
Kojto 122:f9eeca106725 467 #define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (SDIOSUSPEND_BITNUMBER * 4U))
bogdanm 89:552587b429a1 468
bogdanm 89:552587b429a1 469 /* Alias word address of ENCMDCOMPL bit */
Kojto 122:f9eeca106725 470 #define ENCMDCOMPL_BITNUMBER 0x0CU
Kojto 122:f9eeca106725 471 #define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (ENCMDCOMPL_BITNUMBER * 4U))
bogdanm 89:552587b429a1 472
bogdanm 89:552587b429a1 473 /* Alias word address of NIEN bit */
Kojto 122:f9eeca106725 474 #define NIEN_BITNUMBER 0x0DU
Kojto 122:f9eeca106725 475 #define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (NIEN_BITNUMBER * 4U))
bogdanm 89:552587b429a1 476
bogdanm 89:552587b429a1 477 /* Alias word address of ATACMD bit */
Kojto 122:f9eeca106725 478 #define ATACMD_BITNUMBER 0x0EU
Kojto 122:f9eeca106725 479 #define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (ATACMD_BITNUMBER * 4U))
bogdanm 89:552587b429a1 480
bogdanm 89:552587b429a1 481 /* --- DCTRL Register ---*/
bogdanm 89:552587b429a1 482 /* Alias word address of DMAEN bit */
Kojto 122:f9eeca106725 483 #define DCTRL_OFFSET (SDIO_OFFSET + 0x2CU)
Kojto 122:f9eeca106725 484 #define DMAEN_BITNUMBER 0x03U
Kojto 122:f9eeca106725 485 #define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (DMAEN_BITNUMBER * 4U))
bogdanm 89:552587b429a1 486
bogdanm 89:552587b429a1 487 /* Alias word address of RWSTART bit */
Kojto 122:f9eeca106725 488 #define RWSTART_BITNUMBER 0x08U
Kojto 122:f9eeca106725 489 #define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWSTART_BITNUMBER * 4U))
bogdanm 89:552587b429a1 490
bogdanm 89:552587b429a1 491 /* Alias word address of RWSTOP bit */
Kojto 122:f9eeca106725 492 #define RWSTOP_BITNUMBER 0x09U
Kojto 122:f9eeca106725 493 #define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWSTOP_BITNUMBER * 4U))
bogdanm 89:552587b429a1 494
bogdanm 89:552587b429a1 495 /* Alias word address of RWMOD bit */
Kojto 122:f9eeca106725 496 #define RWMOD_BITNUMBER 0x0AU
Kojto 122:f9eeca106725 497 #define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWMOD_BITNUMBER * 4U))
bogdanm 89:552587b429a1 498
bogdanm 89:552587b429a1 499 /* Alias word address of SDIOEN bit */
Kojto 122:f9eeca106725 500 #define SDIOEN_BITNUMBER 0x0BU
Kojto 122:f9eeca106725 501 #define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (SDIOEN_BITNUMBER * 4U))
Kojto 99:dbbf35b96557 502 /**
Kojto 99:dbbf35b96557 503 * @}
Kojto 99:dbbf35b96557 504 */
Kojto 99:dbbf35b96557 505
Kojto 99:dbbf35b96557 506 /** @defgroup SDMMC_LL_Register Bits And Addresses Definitions
Kojto 99:dbbf35b96557 507 * @brief SDMMC_LL registers bit address in the alias region
Kojto 99:dbbf35b96557 508 * @{
Kojto 99:dbbf35b96557 509 */
bogdanm 89:552587b429a1 510
bogdanm 89:552587b429a1 511 /* ---------------------- SDIO registers bit mask --------------------------- */
bogdanm 89:552587b429a1 512 /* --- CLKCR Register ---*/
bogdanm 92:4fc01daae5a5 513 /* CLKCR register clear mask */
bogdanm 92:4fc01daae5a5 514 #define CLKCR_CLEAR_MASK ((uint32_t)(SDIO_CLKCR_CLKDIV | SDIO_CLKCR_PWRSAV |\
bogdanm 92:4fc01daae5a5 515 SDIO_CLKCR_BYPASS | SDIO_CLKCR_WIDBUS |\
bogdanm 92:4fc01daae5a5 516 SDIO_CLKCR_NEGEDGE | SDIO_CLKCR_HWFC_EN))
bogdanm 89:552587b429a1 517
bogdanm 89:552587b429a1 518 /* --- PWRCTRL Register ---*/
bogdanm 89:552587b429a1 519 /* --- DCTRL Register ---*/
bogdanm 89:552587b429a1 520 /* SDIO DCTRL Clear Mask */
bogdanm 92:4fc01daae5a5 521 #define DCTRL_CLEAR_MASK ((uint32_t)(SDIO_DCTRL_DTEN | SDIO_DCTRL_DTDIR |\
bogdanm 92:4fc01daae5a5 522 SDIO_DCTRL_DTMODE | SDIO_DCTRL_DBLOCKSIZE))
bogdanm 89:552587b429a1 523
bogdanm 89:552587b429a1 524 /* --- CMD Register ---*/
bogdanm 89:552587b429a1 525 /* CMD Register clear mask */
bogdanm 92:4fc01daae5a5 526 #define CMD_CLEAR_MASK ((uint32_t)(SDIO_CMD_CMDINDEX | SDIO_CMD_WAITRESP |\
bogdanm 92:4fc01daae5a5 527 SDIO_CMD_WAITINT | SDIO_CMD_WAITPEND |\
bogdanm 92:4fc01daae5a5 528 SDIO_CMD_CPSMEN | SDIO_CMD_SDIOSUSPEND))
bogdanm 89:552587b429a1 529
bogdanm 89:552587b429a1 530 /* SDIO RESP Registers Address */
Kojto 122:f9eeca106725 531 #define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14U))
bogdanm 89:552587b429a1 532
Kojto 99:dbbf35b96557 533 /* SDIO Initialization Frequency (400KHz max) */
Kojto 122:f9eeca106725 534 #define SDIO_INIT_CLK_DIV ((uint8_t)0x76U)
bogdanm 89:552587b429a1 535
bogdanm 89:552587b429a1 536 /* SDIO Data Transfer Frequency (25MHz max) */
Kojto 122:f9eeca106725 537 #define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x00U)
Kojto 99:dbbf35b96557 538 /**
Kojto 99:dbbf35b96557 539 * @}
Kojto 99:dbbf35b96557 540 */
bogdanm 89:552587b429a1 541
Kojto 99:dbbf35b96557 542 /** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration
Kojto 99:dbbf35b96557 543 * @brief macros to handle interrupts and specific clock configurations
Kojto 99:dbbf35b96557 544 * @{
Kojto 99:dbbf35b96557 545 */
Kojto 99:dbbf35b96557 546
bogdanm 89:552587b429a1 547 /**
bogdanm 89:552587b429a1 548 * @brief Enable the SDIO device.
bogdanm 89:552587b429a1 549 * @retval None
bogdanm 89:552587b429a1 550 */
bogdanm 89:552587b429a1 551 #define __SDIO_ENABLE() (*(__IO uint32_t *)CLKCR_CLKEN_BB = ENABLE)
bogdanm 89:552587b429a1 552
bogdanm 89:552587b429a1 553 /**
bogdanm 89:552587b429a1 554 * @brief Disable the SDIO device.
bogdanm 89:552587b429a1 555 * @retval None
bogdanm 89:552587b429a1 556 */
bogdanm 89:552587b429a1 557 #define __SDIO_DISABLE() (*(__IO uint32_t *)CLKCR_CLKEN_BB = DISABLE)
bogdanm 89:552587b429a1 558
bogdanm 89:552587b429a1 559 /**
bogdanm 89:552587b429a1 560 * @brief Enable the SDIO DMA transfer.
bogdanm 89:552587b429a1 561 * @retval None
bogdanm 89:552587b429a1 562 */
bogdanm 89:552587b429a1 563 #define __SDIO_DMA_ENABLE() (*(__IO uint32_t *)DCTRL_DMAEN_BB = ENABLE)
bogdanm 89:552587b429a1 564
bogdanm 89:552587b429a1 565 /**
bogdanm 89:552587b429a1 566 * @brief Disable the SDIO DMA transfer.
bogdanm 89:552587b429a1 567 * @retval None
bogdanm 89:552587b429a1 568 */
bogdanm 89:552587b429a1 569 #define __SDIO_DMA_DISABLE() (*(__IO uint32_t *)DCTRL_DMAEN_BB = DISABLE)
bogdanm 89:552587b429a1 570
bogdanm 89:552587b429a1 571 /**
bogdanm 89:552587b429a1 572 * @brief Enable the SDIO device interrupt.
bogdanm 89:552587b429a1 573 * @param __INSTANCE__ : Pointer to SDIO register base
bogdanm 89:552587b429a1 574 * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be enabled.
bogdanm 89:552587b429a1 575 * This parameter can be one or a combination of the following values:
bogdanm 89:552587b429a1 576 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
bogdanm 89:552587b429a1 577 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
bogdanm 89:552587b429a1 578 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
bogdanm 89:552587b429a1 579 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
bogdanm 89:552587b429a1 580 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
bogdanm 89:552587b429a1 581 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
bogdanm 89:552587b429a1 582 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
bogdanm 89:552587b429a1 583 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
bogdanm 89:552587b429a1 584 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
bogdanm 89:552587b429a1 585 * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
bogdanm 89:552587b429a1 586 * bus mode interrupt
bogdanm 89:552587b429a1 587 * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
bogdanm 89:552587b429a1 588 * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
bogdanm 89:552587b429a1 589 * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
bogdanm 89:552587b429a1 590 * @arg SDIO_IT_RXACT: Data receive in progress interrupt
bogdanm 89:552587b429a1 591 * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
bogdanm 89:552587b429a1 592 * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
bogdanm 89:552587b429a1 593 * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
bogdanm 89:552587b429a1 594 * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
bogdanm 89:552587b429a1 595 * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
bogdanm 89:552587b429a1 596 * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
bogdanm 89:552587b429a1 597 * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
bogdanm 89:552587b429a1 598 * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
bogdanm 89:552587b429a1 599 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
bogdanm 89:552587b429a1 600 * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
bogdanm 89:552587b429a1 601 * @retval None
bogdanm 89:552587b429a1 602 */
bogdanm 89:552587b429a1 603 #define __SDIO_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__))
bogdanm 89:552587b429a1 604
bogdanm 89:552587b429a1 605 /**
bogdanm 89:552587b429a1 606 * @brief Disable the SDIO device interrupt.
bogdanm 89:552587b429a1 607 * @param __INSTANCE__ : Pointer to SDIO register base
bogdanm 89:552587b429a1 608 * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be disabled.
bogdanm 89:552587b429a1 609 * This parameter can be one or a combination of the following values:
bogdanm 89:552587b429a1 610 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
bogdanm 89:552587b429a1 611 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
bogdanm 89:552587b429a1 612 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
bogdanm 89:552587b429a1 613 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
bogdanm 89:552587b429a1 614 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
bogdanm 89:552587b429a1 615 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
bogdanm 89:552587b429a1 616 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
bogdanm 89:552587b429a1 617 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
bogdanm 89:552587b429a1 618 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
bogdanm 89:552587b429a1 619 * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
bogdanm 89:552587b429a1 620 * bus mode interrupt
bogdanm 89:552587b429a1 621 * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
bogdanm 89:552587b429a1 622 * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
bogdanm 89:552587b429a1 623 * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
bogdanm 89:552587b429a1 624 * @arg SDIO_IT_RXACT: Data receive in progress interrupt
bogdanm 89:552587b429a1 625 * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
bogdanm 89:552587b429a1 626 * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
bogdanm 89:552587b429a1 627 * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
bogdanm 89:552587b429a1 628 * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
bogdanm 89:552587b429a1 629 * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
bogdanm 89:552587b429a1 630 * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
bogdanm 89:552587b429a1 631 * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
bogdanm 89:552587b429a1 632 * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
bogdanm 89:552587b429a1 633 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
bogdanm 89:552587b429a1 634 * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
bogdanm 89:552587b429a1 635 * @retval None
bogdanm 89:552587b429a1 636 */
bogdanm 89:552587b429a1 637 #define __SDIO_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
bogdanm 89:552587b429a1 638
bogdanm 89:552587b429a1 639 /**
bogdanm 89:552587b429a1 640 * @brief Checks whether the specified SDIO flag is set or not.
bogdanm 89:552587b429a1 641 * @param __INSTANCE__ : Pointer to SDIO register base
bogdanm 89:552587b429a1 642 * @param __FLAG__: specifies the flag to check.
bogdanm 89:552587b429a1 643 * This parameter can be one of the following values:
bogdanm 89:552587b429a1 644 * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
bogdanm 89:552587b429a1 645 * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
bogdanm 89:552587b429a1 646 * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
bogdanm 89:552587b429a1 647 * @arg SDIO_FLAG_DTIMEOUT: Data timeout
bogdanm 89:552587b429a1 648 * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
bogdanm 89:552587b429a1 649 * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
bogdanm 89:552587b429a1 650 * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
bogdanm 89:552587b429a1 651 * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
bogdanm 89:552587b429a1 652 * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
bogdanm 89:552587b429a1 653 * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode.
bogdanm 89:552587b429a1 654 * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
bogdanm 89:552587b429a1 655 * @arg SDIO_FLAG_CMDACT: Command transfer in progress
bogdanm 89:552587b429a1 656 * @arg SDIO_FLAG_TXACT: Data transmit in progress
bogdanm 89:552587b429a1 657 * @arg SDIO_FLAG_RXACT: Data receive in progress
bogdanm 89:552587b429a1 658 * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
bogdanm 89:552587b429a1 659 * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
bogdanm 89:552587b429a1 660 * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
bogdanm 89:552587b429a1 661 * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
bogdanm 89:552587b429a1 662 * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
bogdanm 89:552587b429a1 663 * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
bogdanm 89:552587b429a1 664 * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
bogdanm 89:552587b429a1 665 * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
bogdanm 89:552587b429a1 666 * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
bogdanm 89:552587b429a1 667 * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
bogdanm 89:552587b429a1 668 * @retval The new state of SDIO_FLAG (SET or RESET).
bogdanm 89:552587b429a1 669 */
bogdanm 89:552587b429a1 670 #define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET)
bogdanm 89:552587b429a1 671
bogdanm 89:552587b429a1 672
bogdanm 89:552587b429a1 673 /**
bogdanm 92:4fc01daae5a5 674 * @brief Clears the SDIO pending flags.
bogdanm 89:552587b429a1 675 * @param __INSTANCE__ : Pointer to SDIO register base
bogdanm 89:552587b429a1 676 * @param __FLAG__: specifies the flag to clear.
bogdanm 89:552587b429a1 677 * This parameter can be one or a combination of the following values:
bogdanm 89:552587b429a1 678 * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
bogdanm 89:552587b429a1 679 * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
bogdanm 89:552587b429a1 680 * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
bogdanm 89:552587b429a1 681 * @arg SDIO_FLAG_DTIMEOUT: Data timeout
bogdanm 89:552587b429a1 682 * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
bogdanm 89:552587b429a1 683 * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
bogdanm 89:552587b429a1 684 * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
bogdanm 89:552587b429a1 685 * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
bogdanm 89:552587b429a1 686 * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
bogdanm 89:552587b429a1 687 * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode
bogdanm 89:552587b429a1 688 * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
bogdanm 89:552587b429a1 689 * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
bogdanm 89:552587b429a1 690 * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
bogdanm 89:552587b429a1 691 * @retval None
bogdanm 89:552587b429a1 692 */
bogdanm 89:552587b429a1 693 #define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__))
bogdanm 89:552587b429a1 694
bogdanm 89:552587b429a1 695 /**
bogdanm 89:552587b429a1 696 * @brief Checks whether the specified SDIO interrupt has occurred or not.
bogdanm 89:552587b429a1 697 * @param __INSTANCE__ : Pointer to SDIO register base
bogdanm 89:552587b429a1 698 * @param __INTERRUPT__: specifies the SDIO interrupt source to check.
bogdanm 89:552587b429a1 699 * This parameter can be one of the following values:
bogdanm 89:552587b429a1 700 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
bogdanm 89:552587b429a1 701 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
bogdanm 89:552587b429a1 702 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
bogdanm 89:552587b429a1 703 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
bogdanm 89:552587b429a1 704 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
bogdanm 89:552587b429a1 705 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
bogdanm 89:552587b429a1 706 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
bogdanm 89:552587b429a1 707 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
bogdanm 89:552587b429a1 708 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
bogdanm 89:552587b429a1 709 * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
bogdanm 89:552587b429a1 710 * bus mode interrupt
bogdanm 89:552587b429a1 711 * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
bogdanm 89:552587b429a1 712 * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
bogdanm 89:552587b429a1 713 * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
bogdanm 89:552587b429a1 714 * @arg SDIO_IT_RXACT: Data receive in progress interrupt
bogdanm 89:552587b429a1 715 * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
bogdanm 89:552587b429a1 716 * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
bogdanm 89:552587b429a1 717 * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
bogdanm 89:552587b429a1 718 * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
bogdanm 89:552587b429a1 719 * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
bogdanm 89:552587b429a1 720 * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
bogdanm 89:552587b429a1 721 * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
bogdanm 89:552587b429a1 722 * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
bogdanm 89:552587b429a1 723 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
bogdanm 89:552587b429a1 724 * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
bogdanm 89:552587b429a1 725 * @retval The new state of SDIO_IT (SET or RESET).
bogdanm 89:552587b429a1 726 */
bogdanm 89:552587b429a1 727 #define __SDIO_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
bogdanm 89:552587b429a1 728
bogdanm 89:552587b429a1 729 /**
bogdanm 89:552587b429a1 730 * @brief Clears the SDIO's interrupt pending bits.
bogdanm 89:552587b429a1 731 * @param __INSTANCE__ : Pointer to SDIO register base
bogdanm 89:552587b429a1 732 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
bogdanm 89:552587b429a1 733 * This parameter can be one or a combination of the following values:
bogdanm 89:552587b429a1 734 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
bogdanm 89:552587b429a1 735 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
bogdanm 89:552587b429a1 736 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
bogdanm 89:552587b429a1 737 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
bogdanm 89:552587b429a1 738 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
bogdanm 89:552587b429a1 739 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
bogdanm 89:552587b429a1 740 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
bogdanm 89:552587b429a1 741 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
bogdanm 89:552587b429a1 742 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt
bogdanm 89:552587b429a1 743 * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
bogdanm 89:552587b429a1 744 * bus mode interrupt
bogdanm 89:552587b429a1 745 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
bogdanm 89:552587b429a1 746 * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
bogdanm 89:552587b429a1 747 * @retval None
bogdanm 89:552587b429a1 748 */
bogdanm 89:552587b429a1 749 #define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__))
bogdanm 89:552587b429a1 750
bogdanm 89:552587b429a1 751 /**
bogdanm 89:552587b429a1 752 * @brief Enable Start the SD I/O Read Wait operation.
bogdanm 89:552587b429a1 753 * @retval None
bogdanm 89:552587b429a1 754 */
bogdanm 89:552587b429a1 755 #define __SDIO_START_READWAIT_ENABLE() (*(__IO uint32_t *) DCTRL_RWSTART_BB = ENABLE)
bogdanm 89:552587b429a1 756
bogdanm 89:552587b429a1 757 /**
bogdanm 89:552587b429a1 758 * @brief Disable Start the SD I/O Read Wait operations.
bogdanm 89:552587b429a1 759 * @retval None
bogdanm 89:552587b429a1 760 */
bogdanm 89:552587b429a1 761 #define __SDIO_START_READWAIT_DISABLE() (*(__IO uint32_t *) DCTRL_RWSTART_BB = DISABLE)
bogdanm 89:552587b429a1 762
bogdanm 89:552587b429a1 763 /**
bogdanm 89:552587b429a1 764 * @brief Enable Start the SD I/O Read Wait operation.
bogdanm 89:552587b429a1 765 * @retval None
bogdanm 89:552587b429a1 766 */
bogdanm 89:552587b429a1 767 #define __SDIO_STOP_READWAIT_ENABLE() (*(__IO uint32_t *) DCTRL_RWSTOP_BB = ENABLE)
bogdanm 89:552587b429a1 768
bogdanm 89:552587b429a1 769 /**
bogdanm 89:552587b429a1 770 * @brief Disable Stop the SD I/O Read Wait operations.
bogdanm 89:552587b429a1 771 * @retval None
bogdanm 89:552587b429a1 772 */
bogdanm 89:552587b429a1 773 #define __SDIO_STOP_READWAIT_DISABLE() (*(__IO uint32_t *) DCTRL_RWSTOP_BB = DISABLE)
bogdanm 89:552587b429a1 774
bogdanm 89:552587b429a1 775 /**
bogdanm 89:552587b429a1 776 * @brief Enable the SD I/O Mode Operation.
bogdanm 89:552587b429a1 777 * @retval None
bogdanm 89:552587b429a1 778 */
bogdanm 89:552587b429a1 779 #define __SDIO_OPERATION_ENABLE() (*(__IO uint32_t *) DCTRL_SDIOEN_BB = ENABLE)
bogdanm 89:552587b429a1 780
bogdanm 89:552587b429a1 781 /**
bogdanm 89:552587b429a1 782 * @brief Disable the SD I/O Mode Operation.
bogdanm 89:552587b429a1 783 * @retval None
bogdanm 89:552587b429a1 784 */
bogdanm 89:552587b429a1 785 #define __SDIO_OPERATION_DISABLE() (*(__IO uint32_t *) DCTRL_SDIOEN_BB = DISABLE)
bogdanm 89:552587b429a1 786
bogdanm 89:552587b429a1 787 /**
bogdanm 89:552587b429a1 788 * @brief Enable the SD I/O Suspend command sending.
bogdanm 89:552587b429a1 789 * @retval None
bogdanm 89:552587b429a1 790 */
bogdanm 89:552587b429a1 791 #define __SDIO_SUSPEND_CMD_ENABLE() (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = ENABLE)
bogdanm 89:552587b429a1 792
bogdanm 89:552587b429a1 793 /**
bogdanm 89:552587b429a1 794 * @brief Disable the SD I/O Suspend command sending.
bogdanm 89:552587b429a1 795 * @retval None
bogdanm 89:552587b429a1 796 */
bogdanm 89:552587b429a1 797 #define __SDIO_SUSPEND_CMD_DISABLE() (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = DISABLE)
Kojto 99:dbbf35b96557 798
Kojto 110:165afa46840b 799 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
Kojto 110:165afa46840b 800 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
Kojto 122:f9eeca106725 801 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F412Zx) ||\
Kojto 122:f9eeca106725 802 defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
bogdanm 89:552587b429a1 803 /**
bogdanm 89:552587b429a1 804 * @brief Enable the command completion signal.
bogdanm 89:552587b429a1 805 * @retval None
bogdanm 89:552587b429a1 806 */
bogdanm 89:552587b429a1 807 #define __SDIO_CEATA_CMD_COMPLETION_ENABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = ENABLE)
bogdanm 89:552587b429a1 808
bogdanm 89:552587b429a1 809 /**
bogdanm 89:552587b429a1 810 * @brief Disable the command completion signal.
bogdanm 89:552587b429a1 811 * @retval None
bogdanm 89:552587b429a1 812 */
bogdanm 89:552587b429a1 813 #define __SDIO_CEATA_CMD_COMPLETION_DISABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = DISABLE)
bogdanm 89:552587b429a1 814
bogdanm 89:552587b429a1 815 /**
bogdanm 89:552587b429a1 816 * @brief Enable the CE-ATA interrupt.
bogdanm 89:552587b429a1 817 * @retval None
bogdanm 89:552587b429a1 818 */
Kojto 122:f9eeca106725 819 #define __SDIO_CEATA_ENABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)0U)
bogdanm 89:552587b429a1 820
bogdanm 89:552587b429a1 821 /**
bogdanm 89:552587b429a1 822 * @brief Disable the CE-ATA interrupt.
bogdanm 89:552587b429a1 823 * @retval None
bogdanm 89:552587b429a1 824 */
Kojto 122:f9eeca106725 825 #define __SDIO_CEATA_DISABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)1U)
bogdanm 89:552587b429a1 826
bogdanm 89:552587b429a1 827 /**
bogdanm 89:552587b429a1 828 * @brief Enable send CE-ATA command (CMD61).
bogdanm 89:552587b429a1 829 * @retval None
bogdanm 89:552587b429a1 830 */
bogdanm 89:552587b429a1 831 #define __SDIO_CEATA_SENDCMD_ENABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = ENABLE)
bogdanm 89:552587b429a1 832
bogdanm 89:552587b429a1 833 /**
bogdanm 89:552587b429a1 834 * @brief Disable send CE-ATA command (CMD61).
bogdanm 89:552587b429a1 835 * @retval None
bogdanm 89:552587b429a1 836 */
bogdanm 89:552587b429a1 837 #define __SDIO_CEATA_SENDCMD_DISABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = DISABLE)
Kojto 110:165afa46840b 838 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE ||\
Kojto 122:f9eeca106725 839 STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F412Zx || STM32F412Vx || STM32F412Rx ||\
Kojto 122:f9eeca106725 840 STM32F412Cx */
bogdanm 89:552587b429a1 841 /**
bogdanm 89:552587b429a1 842 * @}
bogdanm 89:552587b429a1 843 */
bogdanm 89:552587b429a1 844
bogdanm 92:4fc01daae5a5 845 /**
bogdanm 92:4fc01daae5a5 846 * @}
bogdanm 92:4fc01daae5a5 847 */
bogdanm 92:4fc01daae5a5 848
bogdanm 89:552587b429a1 849 /* Exported functions --------------------------------------------------------*/
Kojto 99:dbbf35b96557 850 /** @addtogroup SDMMC_LL_Exported_Functions
bogdanm 92:4fc01daae5a5 851 * @{
bogdanm 92:4fc01daae5a5 852 */
bogdanm 92:4fc01daae5a5 853
bogdanm 89:552587b429a1 854 /* Initialization/de-initialization functions **********************************/
Kojto 99:dbbf35b96557 855 /** @addtogroup HAL_SDMMC_LL_Group1
bogdanm 92:4fc01daae5a5 856 * @{
bogdanm 92:4fc01daae5a5 857 */
bogdanm 89:552587b429a1 858 HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init);
bogdanm 92:4fc01daae5a5 859 /**
bogdanm 92:4fc01daae5a5 860 * @}
bogdanm 92:4fc01daae5a5 861 */
bogdanm 92:4fc01daae5a5 862
bogdanm 89:552587b429a1 863 /* I/O operation functions *****************************************************/
Kojto 99:dbbf35b96557 864 /** @addtogroup HAL_SDMMC_LL_Group2
bogdanm 92:4fc01daae5a5 865 * @{
bogdanm 92:4fc01daae5a5 866 */
bogdanm 89:552587b429a1 867 /* Blocking mode: Polling */
bogdanm 89:552587b429a1 868 uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx);
bogdanm 89:552587b429a1 869 HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData);
bogdanm 92:4fc01daae5a5 870 /**
bogdanm 92:4fc01daae5a5 871 * @}
bogdanm 92:4fc01daae5a5 872 */
bogdanm 92:4fc01daae5a5 873
bogdanm 89:552587b429a1 874 /* Peripheral Control functions ************************************************/
Kojto 99:dbbf35b96557 875 /** @addtogroup HAL_SDMMC_LL_Group3
bogdanm 92:4fc01daae5a5 876 * @{
bogdanm 92:4fc01daae5a5 877 */
bogdanm 89:552587b429a1 878 HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx);
bogdanm 89:552587b429a1 879 HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx);
bogdanm 89:552587b429a1 880 uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx);
bogdanm 89:552587b429a1 881
bogdanm 89:552587b429a1 882 /* Command path state machine (CPSM) management functions */
bogdanm 89:552587b429a1 883 HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);
bogdanm 89:552587b429a1 884 uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx);
bogdanm 89:552587b429a1 885 uint32_t SDIO_GetResponse(uint32_t SDIO_RESP);
bogdanm 89:552587b429a1 886
bogdanm 89:552587b429a1 887 /* Data path state machine (DPSM) management functions */
bogdanm 89:552587b429a1 888 HAL_StatusTypeDef SDIO_DataConfig(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* SDIO_DataInitStruct);
bogdanm 89:552587b429a1 889 uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx);
bogdanm 89:552587b429a1 890 uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx);
bogdanm 89:552587b429a1 891
bogdanm 89:552587b429a1 892 /* SDIO IO Cards mode management functions */
bogdanm 89:552587b429a1 893 HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
bogdanm 89:552587b429a1 894
bogdanm 92:4fc01daae5a5 895 /**
bogdanm 92:4fc01daae5a5 896 * @}
bogdanm 92:4fc01daae5a5 897 */
bogdanm 92:4fc01daae5a5 898
bogdanm 92:4fc01daae5a5 899 /**
bogdanm 92:4fc01daae5a5 900 * @}
bogdanm 92:4fc01daae5a5 901 */
bogdanm 92:4fc01daae5a5 902
bogdanm 92:4fc01daae5a5 903 /**
bogdanm 92:4fc01daae5a5 904 * @}
bogdanm 92:4fc01daae5a5 905 */
bogdanm 92:4fc01daae5a5 906
bogdanm 92:4fc01daae5a5 907 /**
bogdanm 92:4fc01daae5a5 908 * @}
bogdanm 92:4fc01daae5a5 909 */
Kojto 110:165afa46840b 910 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
Kojto 122:f9eeca106725 911 STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||
Kojto 122:f9eeca106725 912 STM32F412Rx || STM32F412Cx */
bogdanm 89:552587b429a1 913 #ifdef __cplusplus
bogdanm 89:552587b429a1 914 }
bogdanm 89:552587b429a1 915 #endif
bogdanm 89:552587b429a1 916
bogdanm 89:552587b429a1 917 #endif /* __STM32F4xx_LL_SDMMC_H */
bogdanm 89:552587b429a1 918
bogdanm 89:552587b429a1 919 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/