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TARGET_NUCLEO_L432KC/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_cortex.h@157:e7ca05fa8600, 2017-11-09 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 09 11:14:10 2017 +0000
Revision:
157:e7ca05fa8600
Parent:
156:ff21514d8981
Child:
161:aa5281ff4a02
Release 155 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 156:ff21514d8981 1 /**
AnnaBridge 156:ff21514d8981 2 ******************************************************************************
AnnaBridge 156:ff21514d8981 3 * @file stm32l4xx_ll_cortex.h
AnnaBridge 156:ff21514d8981 4 * @author MCD Application Team
AnnaBridge 156:ff21514d8981 5 * @version V1.7.1
AnnaBridge 156:ff21514d8981 6 * @date 21-April-2017
AnnaBridge 156:ff21514d8981 7 * @brief Header file of CORTEX LL module.
AnnaBridge 156:ff21514d8981 8 @verbatim
AnnaBridge 156:ff21514d8981 9 ==============================================================================
AnnaBridge 156:ff21514d8981 10 ##### How to use this driver #####
AnnaBridge 156:ff21514d8981 11 ==============================================================================
AnnaBridge 156:ff21514d8981 12 [..]
AnnaBridge 156:ff21514d8981 13 The LL CORTEX driver contains a set of generic APIs that can be
AnnaBridge 156:ff21514d8981 14 used by user:
AnnaBridge 156:ff21514d8981 15 (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
AnnaBridge 156:ff21514d8981 16 functions
AnnaBridge 156:ff21514d8981 17 (+) Low power mode configuration (SCB register of Cortex-MCU)
AnnaBridge 156:ff21514d8981 18 (+) MPU API to configure and enable regions
AnnaBridge 156:ff21514d8981 19 (+) API to access to MCU info (CPUID register)
AnnaBridge 156:ff21514d8981 20 (+) API to enable fault handler (SHCSR accesses)
AnnaBridge 156:ff21514d8981 21
AnnaBridge 156:ff21514d8981 22 @endverbatim
AnnaBridge 156:ff21514d8981 23 ******************************************************************************
AnnaBridge 156:ff21514d8981 24 * @attention
AnnaBridge 156:ff21514d8981 25 *
AnnaBridge 156:ff21514d8981 26 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge 156:ff21514d8981 27 *
AnnaBridge 156:ff21514d8981 28 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 156:ff21514d8981 29 * are permitted provided that the following conditions are met:
AnnaBridge 156:ff21514d8981 30 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 156:ff21514d8981 31 * this list of conditions and the following disclaimer.
AnnaBridge 156:ff21514d8981 32 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 156:ff21514d8981 33 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 156:ff21514d8981 34 * and/or other materials provided with the distribution.
AnnaBridge 156:ff21514d8981 35 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 156:ff21514d8981 36 * may be used to endorse or promote products derived from this software
AnnaBridge 156:ff21514d8981 37 * without specific prior written permission.
AnnaBridge 156:ff21514d8981 38 *
AnnaBridge 156:ff21514d8981 39 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 156:ff21514d8981 40 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 156:ff21514d8981 41 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 156:ff21514d8981 42 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 156:ff21514d8981 43 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 156:ff21514d8981 44 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 156:ff21514d8981 45 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 156:ff21514d8981 46 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 156:ff21514d8981 47 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 156:ff21514d8981 48 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 156:ff21514d8981 49 *
AnnaBridge 156:ff21514d8981 50 ******************************************************************************
AnnaBridge 156:ff21514d8981 51 */
AnnaBridge 156:ff21514d8981 52
AnnaBridge 156:ff21514d8981 53 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 156:ff21514d8981 54 #ifndef __STM32L4xx_LL_CORTEX_H
AnnaBridge 156:ff21514d8981 55 #define __STM32L4xx_LL_CORTEX_H
AnnaBridge 156:ff21514d8981 56
AnnaBridge 156:ff21514d8981 57 #ifdef __cplusplus
AnnaBridge 156:ff21514d8981 58 extern "C" {
AnnaBridge 156:ff21514d8981 59 #endif
AnnaBridge 156:ff21514d8981 60
AnnaBridge 156:ff21514d8981 61 /* Includes ------------------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 62 #include "stm32l4xx.h"
AnnaBridge 156:ff21514d8981 63
AnnaBridge 156:ff21514d8981 64 /** @addtogroup STM32L4xx_LL_Driver
AnnaBridge 156:ff21514d8981 65 * @{
AnnaBridge 156:ff21514d8981 66 */
AnnaBridge 156:ff21514d8981 67
AnnaBridge 156:ff21514d8981 68 /** @defgroup CORTEX_LL CORTEX
AnnaBridge 156:ff21514d8981 69 * @{
AnnaBridge 156:ff21514d8981 70 */
AnnaBridge 156:ff21514d8981 71
AnnaBridge 156:ff21514d8981 72 /* Private types -------------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 73 /* Private variables ---------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 74
AnnaBridge 156:ff21514d8981 75 /* Private constants ---------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 76
AnnaBridge 156:ff21514d8981 77 /* Private macros ------------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 78
AnnaBridge 156:ff21514d8981 79 /* Exported types ------------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 80 /* Exported constants --------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 81 /** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
AnnaBridge 156:ff21514d8981 82 * @{
AnnaBridge 156:ff21514d8981 83 */
AnnaBridge 156:ff21514d8981 84
AnnaBridge 156:ff21514d8981 85 /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
AnnaBridge 156:ff21514d8981 86 * @{
AnnaBridge 156:ff21514d8981 87 */
AnnaBridge 156:ff21514d8981 88 #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/
AnnaBridge 156:ff21514d8981 89 #define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */
AnnaBridge 156:ff21514d8981 90 /**
AnnaBridge 156:ff21514d8981 91 * @}
AnnaBridge 156:ff21514d8981 92 */
AnnaBridge 156:ff21514d8981 93
AnnaBridge 156:ff21514d8981 94 /** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
AnnaBridge 156:ff21514d8981 95 * @{
AnnaBridge 156:ff21514d8981 96 */
AnnaBridge 156:ff21514d8981 97 #define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */
AnnaBridge 156:ff21514d8981 98 #define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */
AnnaBridge 156:ff21514d8981 99 #define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */
AnnaBridge 156:ff21514d8981 100 /**
AnnaBridge 156:ff21514d8981 101 * @}
AnnaBridge 156:ff21514d8981 102 */
AnnaBridge 156:ff21514d8981 103
AnnaBridge 156:ff21514d8981 104 #if __MPU_PRESENT
AnnaBridge 156:ff21514d8981 105
AnnaBridge 156:ff21514d8981 106 /** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
AnnaBridge 156:ff21514d8981 107 * @{
AnnaBridge 156:ff21514d8981 108 */
AnnaBridge 156:ff21514d8981 109 #define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U /*!< Disable NMI and privileged SW access */
AnnaBridge 156:ff21514d8981 110 #define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
AnnaBridge 156:ff21514d8981 111 #define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */
AnnaBridge 156:ff21514d8981 112 #define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
AnnaBridge 156:ff21514d8981 113 /**
AnnaBridge 156:ff21514d8981 114 * @}
AnnaBridge 156:ff21514d8981 115 */
AnnaBridge 156:ff21514d8981 116
AnnaBridge 156:ff21514d8981 117 /** @defgroup CORTEX_LL_EC_REGION MPU Region Number
AnnaBridge 156:ff21514d8981 118 * @{
AnnaBridge 156:ff21514d8981 119 */
AnnaBridge 156:ff21514d8981 120 #define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */
AnnaBridge 156:ff21514d8981 121 #define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */
AnnaBridge 156:ff21514d8981 122 #define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */
AnnaBridge 156:ff21514d8981 123 #define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */
AnnaBridge 156:ff21514d8981 124 #define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */
AnnaBridge 156:ff21514d8981 125 #define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */
AnnaBridge 156:ff21514d8981 126 #define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */
AnnaBridge 156:ff21514d8981 127 #define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */
AnnaBridge 156:ff21514d8981 128 /**
AnnaBridge 156:ff21514d8981 129 * @}
AnnaBridge 156:ff21514d8981 130 */
AnnaBridge 156:ff21514d8981 131
AnnaBridge 156:ff21514d8981 132 /** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
AnnaBridge 156:ff21514d8981 133 * @{
AnnaBridge 156:ff21514d8981 134 */
AnnaBridge 156:ff21514d8981 135 #define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
AnnaBridge 156:ff21514d8981 136 #define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */
AnnaBridge 156:ff21514d8981 137 #define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */
AnnaBridge 156:ff21514d8981 138 #define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
AnnaBridge 156:ff21514d8981 139 #define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
AnnaBridge 156:ff21514d8981 140 #define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
AnnaBridge 156:ff21514d8981 141 #define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
AnnaBridge 156:ff21514d8981 142 #define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
AnnaBridge 156:ff21514d8981 143 #define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
AnnaBridge 156:ff21514d8981 144 #define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
AnnaBridge 156:ff21514d8981 145 #define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
AnnaBridge 156:ff21514d8981 146 #define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
AnnaBridge 156:ff21514d8981 147 #define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
AnnaBridge 156:ff21514d8981 148 #define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
AnnaBridge 156:ff21514d8981 149 #define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
AnnaBridge 156:ff21514d8981 150 #define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
AnnaBridge 156:ff21514d8981 151 #define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
AnnaBridge 156:ff21514d8981 152 #define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
AnnaBridge 156:ff21514d8981 153 #define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
AnnaBridge 156:ff21514d8981 154 #define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
AnnaBridge 156:ff21514d8981 155 #define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
AnnaBridge 156:ff21514d8981 156 #define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
AnnaBridge 156:ff21514d8981 157 #define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
AnnaBridge 156:ff21514d8981 158 #define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
AnnaBridge 156:ff21514d8981 159 #define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
AnnaBridge 156:ff21514d8981 160 #define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
AnnaBridge 156:ff21514d8981 161 #define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
AnnaBridge 156:ff21514d8981 162 #define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
AnnaBridge 156:ff21514d8981 163 /**
AnnaBridge 156:ff21514d8981 164 * @}
AnnaBridge 156:ff21514d8981 165 */
AnnaBridge 156:ff21514d8981 166
AnnaBridge 156:ff21514d8981 167 /** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
AnnaBridge 156:ff21514d8981 168 * @{
AnnaBridge 156:ff21514d8981 169 */
AnnaBridge 156:ff21514d8981 170 #define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos) /*!< No access*/
AnnaBridge 156:ff21514d8981 171 #define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
AnnaBridge 156:ff21514d8981 172 #define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
AnnaBridge 156:ff21514d8981 173 #define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
AnnaBridge 156:ff21514d8981 174 #define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
AnnaBridge 156:ff21514d8981 175 #define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
AnnaBridge 156:ff21514d8981 176 /**
AnnaBridge 156:ff21514d8981 177 * @}
AnnaBridge 156:ff21514d8981 178 */
AnnaBridge 156:ff21514d8981 179
AnnaBridge 156:ff21514d8981 180 /** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
AnnaBridge 156:ff21514d8981 181 * @{
AnnaBridge 156:ff21514d8981 182 */
AnnaBridge 156:ff21514d8981 183 #define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
AnnaBridge 156:ff21514d8981 184 #define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
AnnaBridge 156:ff21514d8981 185 #define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
AnnaBridge 156:ff21514d8981 186 #define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
AnnaBridge 156:ff21514d8981 187 /**
AnnaBridge 156:ff21514d8981 188 * @}
AnnaBridge 156:ff21514d8981 189 */
AnnaBridge 156:ff21514d8981 190
AnnaBridge 156:ff21514d8981 191 /** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
AnnaBridge 156:ff21514d8981 192 * @{
AnnaBridge 156:ff21514d8981 193 */
AnnaBridge 156:ff21514d8981 194 #define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U /*!< Instruction fetches enabled */
AnnaBridge 156:ff21514d8981 195 #define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/
AnnaBridge 156:ff21514d8981 196 /**
AnnaBridge 156:ff21514d8981 197 * @}
AnnaBridge 156:ff21514d8981 198 */
AnnaBridge 156:ff21514d8981 199
AnnaBridge 156:ff21514d8981 200 /** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
AnnaBridge 156:ff21514d8981 201 * @{
AnnaBridge 156:ff21514d8981 202 */
AnnaBridge 156:ff21514d8981 203 #define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */
AnnaBridge 156:ff21514d8981 204 #define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U /*!< Not Shareable memory attribute */
AnnaBridge 156:ff21514d8981 205 /**
AnnaBridge 156:ff21514d8981 206 * @}
AnnaBridge 156:ff21514d8981 207 */
AnnaBridge 156:ff21514d8981 208
AnnaBridge 156:ff21514d8981 209 /** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
AnnaBridge 156:ff21514d8981 210 * @{
AnnaBridge 156:ff21514d8981 211 */
AnnaBridge 156:ff21514d8981 212 #define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */
AnnaBridge 156:ff21514d8981 213 #define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U /*!< Not Cacheable memory attribute */
AnnaBridge 156:ff21514d8981 214 /**
AnnaBridge 156:ff21514d8981 215 * @}
AnnaBridge 156:ff21514d8981 216 */
AnnaBridge 156:ff21514d8981 217
AnnaBridge 156:ff21514d8981 218 /** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
AnnaBridge 156:ff21514d8981 219 * @{
AnnaBridge 156:ff21514d8981 220 */
AnnaBridge 156:ff21514d8981 221 #define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */
AnnaBridge 156:ff21514d8981 222 #define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U /*!< Not Bufferable memory attribute */
AnnaBridge 156:ff21514d8981 223 /**
AnnaBridge 156:ff21514d8981 224 * @}
AnnaBridge 156:ff21514d8981 225 */
AnnaBridge 156:ff21514d8981 226 #endif /* __MPU_PRESENT */
AnnaBridge 156:ff21514d8981 227 /**
AnnaBridge 156:ff21514d8981 228 * @}
AnnaBridge 156:ff21514d8981 229 */
AnnaBridge 156:ff21514d8981 230
AnnaBridge 156:ff21514d8981 231 /* Exported macro ------------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 232
AnnaBridge 156:ff21514d8981 233 /* Exported functions --------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 234 /** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
AnnaBridge 156:ff21514d8981 235 * @{
AnnaBridge 156:ff21514d8981 236 */
AnnaBridge 156:ff21514d8981 237
AnnaBridge 156:ff21514d8981 238 /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
AnnaBridge 156:ff21514d8981 239 * @{
AnnaBridge 156:ff21514d8981 240 */
AnnaBridge 156:ff21514d8981 241
AnnaBridge 156:ff21514d8981 242 /**
AnnaBridge 156:ff21514d8981 243 * @brief This function checks if the Systick counter flag is active or not.
AnnaBridge 156:ff21514d8981 244 * @note It can be used in timeout function on application side.
AnnaBridge 156:ff21514d8981 245 * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
AnnaBridge 156:ff21514d8981 246 * @retval State of bit (1 or 0).
AnnaBridge 156:ff21514d8981 247 */
AnnaBridge 156:ff21514d8981 248 __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
AnnaBridge 156:ff21514d8981 249 {
AnnaBridge 156:ff21514d8981 250 return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));
AnnaBridge 156:ff21514d8981 251 }
AnnaBridge 156:ff21514d8981 252
AnnaBridge 156:ff21514d8981 253 /**
AnnaBridge 156:ff21514d8981 254 * @brief Configures the SysTick clock source
AnnaBridge 156:ff21514d8981 255 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
AnnaBridge 156:ff21514d8981 256 * @param Source This parameter can be one of the following values:
AnnaBridge 156:ff21514d8981 257 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
AnnaBridge 156:ff21514d8981 258 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
AnnaBridge 156:ff21514d8981 259 * @retval None
AnnaBridge 156:ff21514d8981 260 */
AnnaBridge 156:ff21514d8981 261 __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
AnnaBridge 156:ff21514d8981 262 {
AnnaBridge 156:ff21514d8981 263 if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
AnnaBridge 156:ff21514d8981 264 {
AnnaBridge 156:ff21514d8981 265 SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
AnnaBridge 156:ff21514d8981 266 }
AnnaBridge 156:ff21514d8981 267 else
AnnaBridge 156:ff21514d8981 268 {
AnnaBridge 156:ff21514d8981 269 CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
AnnaBridge 156:ff21514d8981 270 }
AnnaBridge 156:ff21514d8981 271 }
AnnaBridge 156:ff21514d8981 272
AnnaBridge 156:ff21514d8981 273 /**
AnnaBridge 156:ff21514d8981 274 * @brief Get the SysTick clock source
AnnaBridge 156:ff21514d8981 275 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
AnnaBridge 156:ff21514d8981 276 * @retval Returned value can be one of the following values:
AnnaBridge 156:ff21514d8981 277 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
AnnaBridge 156:ff21514d8981 278 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
AnnaBridge 156:ff21514d8981 279 */
AnnaBridge 156:ff21514d8981 280 __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
AnnaBridge 156:ff21514d8981 281 {
AnnaBridge 156:ff21514d8981 282 return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
AnnaBridge 156:ff21514d8981 283 }
AnnaBridge 156:ff21514d8981 284
AnnaBridge 156:ff21514d8981 285 /**
AnnaBridge 156:ff21514d8981 286 * @brief Enable SysTick exception request
AnnaBridge 156:ff21514d8981 287 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
AnnaBridge 156:ff21514d8981 288 * @retval None
AnnaBridge 156:ff21514d8981 289 */
AnnaBridge 156:ff21514d8981 290 __STATIC_INLINE void LL_SYSTICK_EnableIT(void)
AnnaBridge 156:ff21514d8981 291 {
AnnaBridge 156:ff21514d8981 292 SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
AnnaBridge 156:ff21514d8981 293 }
AnnaBridge 156:ff21514d8981 294
AnnaBridge 156:ff21514d8981 295 /**
AnnaBridge 156:ff21514d8981 296 * @brief Disable SysTick exception request
AnnaBridge 156:ff21514d8981 297 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
AnnaBridge 156:ff21514d8981 298 * @retval None
AnnaBridge 156:ff21514d8981 299 */
AnnaBridge 156:ff21514d8981 300 __STATIC_INLINE void LL_SYSTICK_DisableIT(void)
AnnaBridge 156:ff21514d8981 301 {
AnnaBridge 156:ff21514d8981 302 CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
AnnaBridge 156:ff21514d8981 303 }
AnnaBridge 156:ff21514d8981 304
AnnaBridge 156:ff21514d8981 305 /**
AnnaBridge 156:ff21514d8981 306 * @brief Checks if the SYSTICK interrupt is enabled or disabled.
AnnaBridge 156:ff21514d8981 307 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
AnnaBridge 156:ff21514d8981 308 * @retval State of bit (1 or 0).
AnnaBridge 156:ff21514d8981 309 */
AnnaBridge 156:ff21514d8981 310 __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
AnnaBridge 156:ff21514d8981 311 {
AnnaBridge 156:ff21514d8981 312 return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));
AnnaBridge 156:ff21514d8981 313 }
AnnaBridge 156:ff21514d8981 314
AnnaBridge 156:ff21514d8981 315 /**
AnnaBridge 156:ff21514d8981 316 * @}
AnnaBridge 156:ff21514d8981 317 */
AnnaBridge 156:ff21514d8981 318
AnnaBridge 156:ff21514d8981 319 /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
AnnaBridge 156:ff21514d8981 320 * @{
AnnaBridge 156:ff21514d8981 321 */
AnnaBridge 156:ff21514d8981 322
AnnaBridge 156:ff21514d8981 323 /**
AnnaBridge 156:ff21514d8981 324 * @brief Processor uses sleep as its low power mode
AnnaBridge 156:ff21514d8981 325 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
AnnaBridge 156:ff21514d8981 326 * @retval None
AnnaBridge 156:ff21514d8981 327 */
AnnaBridge 156:ff21514d8981 328 __STATIC_INLINE void LL_LPM_EnableSleep(void)
AnnaBridge 156:ff21514d8981 329 {
AnnaBridge 156:ff21514d8981 330 /* Clear SLEEPDEEP bit of Cortex System Control Register */
AnnaBridge 156:ff21514d8981 331 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
AnnaBridge 156:ff21514d8981 332 }
AnnaBridge 156:ff21514d8981 333
AnnaBridge 156:ff21514d8981 334 /**
AnnaBridge 156:ff21514d8981 335 * @brief Processor uses deep sleep as its low power mode
AnnaBridge 156:ff21514d8981 336 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
AnnaBridge 156:ff21514d8981 337 * @retval None
AnnaBridge 156:ff21514d8981 338 */
AnnaBridge 156:ff21514d8981 339 __STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
AnnaBridge 156:ff21514d8981 340 {
AnnaBridge 156:ff21514d8981 341 /* Set SLEEPDEEP bit of Cortex System Control Register */
AnnaBridge 156:ff21514d8981 342 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
AnnaBridge 156:ff21514d8981 343 }
AnnaBridge 156:ff21514d8981 344
AnnaBridge 156:ff21514d8981 345 /**
AnnaBridge 156:ff21514d8981 346 * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
AnnaBridge 156:ff21514d8981 347 * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
AnnaBridge 156:ff21514d8981 348 * empty main application.
AnnaBridge 156:ff21514d8981 349 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
AnnaBridge 156:ff21514d8981 350 * @retval None
AnnaBridge 156:ff21514d8981 351 */
AnnaBridge 156:ff21514d8981 352 __STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
AnnaBridge 156:ff21514d8981 353 {
AnnaBridge 156:ff21514d8981 354 /* Set SLEEPONEXIT bit of Cortex System Control Register */
AnnaBridge 156:ff21514d8981 355 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
AnnaBridge 156:ff21514d8981 356 }
AnnaBridge 156:ff21514d8981 357
AnnaBridge 156:ff21514d8981 358 /**
AnnaBridge 156:ff21514d8981 359 * @brief Do not sleep when returning to Thread mode.
AnnaBridge 156:ff21514d8981 360 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
AnnaBridge 156:ff21514d8981 361 * @retval None
AnnaBridge 156:ff21514d8981 362 */
AnnaBridge 156:ff21514d8981 363 __STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
AnnaBridge 156:ff21514d8981 364 {
AnnaBridge 156:ff21514d8981 365 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
AnnaBridge 156:ff21514d8981 366 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
AnnaBridge 156:ff21514d8981 367 }
AnnaBridge 156:ff21514d8981 368
AnnaBridge 156:ff21514d8981 369 /**
AnnaBridge 156:ff21514d8981 370 * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
AnnaBridge 156:ff21514d8981 371 * processor.
AnnaBridge 156:ff21514d8981 372 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
AnnaBridge 156:ff21514d8981 373 * @retval None
AnnaBridge 156:ff21514d8981 374 */
AnnaBridge 156:ff21514d8981 375 __STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
AnnaBridge 156:ff21514d8981 376 {
AnnaBridge 156:ff21514d8981 377 /* Set SEVEONPEND bit of Cortex System Control Register */
AnnaBridge 156:ff21514d8981 378 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
AnnaBridge 156:ff21514d8981 379 }
AnnaBridge 156:ff21514d8981 380
AnnaBridge 156:ff21514d8981 381 /**
AnnaBridge 156:ff21514d8981 382 * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
AnnaBridge 156:ff21514d8981 383 * excluded
AnnaBridge 156:ff21514d8981 384 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
AnnaBridge 156:ff21514d8981 385 * @retval None
AnnaBridge 156:ff21514d8981 386 */
AnnaBridge 156:ff21514d8981 387 __STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
AnnaBridge 156:ff21514d8981 388 {
AnnaBridge 156:ff21514d8981 389 /* Clear SEVEONPEND bit of Cortex System Control Register */
AnnaBridge 156:ff21514d8981 390 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
AnnaBridge 156:ff21514d8981 391 }
AnnaBridge 156:ff21514d8981 392
AnnaBridge 156:ff21514d8981 393 /**
AnnaBridge 156:ff21514d8981 394 * @}
AnnaBridge 156:ff21514d8981 395 */
AnnaBridge 156:ff21514d8981 396
AnnaBridge 156:ff21514d8981 397 /** @defgroup CORTEX_LL_EF_HANDLER HANDLER
AnnaBridge 156:ff21514d8981 398 * @{
AnnaBridge 156:ff21514d8981 399 */
AnnaBridge 156:ff21514d8981 400
AnnaBridge 156:ff21514d8981 401 /**
AnnaBridge 156:ff21514d8981 402 * @brief Enable a fault in System handler control register (SHCSR)
AnnaBridge 156:ff21514d8981 403 * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault
AnnaBridge 156:ff21514d8981 404 * @param Fault This parameter can be a combination of the following values:
AnnaBridge 156:ff21514d8981 405 * @arg @ref LL_HANDLER_FAULT_USG
AnnaBridge 156:ff21514d8981 406 * @arg @ref LL_HANDLER_FAULT_BUS
AnnaBridge 156:ff21514d8981 407 * @arg @ref LL_HANDLER_FAULT_MEM
AnnaBridge 156:ff21514d8981 408 * @retval None
AnnaBridge 156:ff21514d8981 409 */
AnnaBridge 156:ff21514d8981 410 __STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
AnnaBridge 156:ff21514d8981 411 {
AnnaBridge 156:ff21514d8981 412 /* Enable the system handler fault */
AnnaBridge 156:ff21514d8981 413 SET_BIT(SCB->SHCSR, Fault);
AnnaBridge 156:ff21514d8981 414 }
AnnaBridge 156:ff21514d8981 415
AnnaBridge 156:ff21514d8981 416 /**
AnnaBridge 156:ff21514d8981 417 * @brief Disable a fault in System handler control register (SHCSR)
AnnaBridge 156:ff21514d8981 418 * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault
AnnaBridge 156:ff21514d8981 419 * @param Fault This parameter can be a combination of the following values:
AnnaBridge 156:ff21514d8981 420 * @arg @ref LL_HANDLER_FAULT_USG
AnnaBridge 156:ff21514d8981 421 * @arg @ref LL_HANDLER_FAULT_BUS
AnnaBridge 156:ff21514d8981 422 * @arg @ref LL_HANDLER_FAULT_MEM
AnnaBridge 156:ff21514d8981 423 * @retval None
AnnaBridge 156:ff21514d8981 424 */
AnnaBridge 156:ff21514d8981 425 __STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
AnnaBridge 156:ff21514d8981 426 {
AnnaBridge 156:ff21514d8981 427 /* Disable the system handler fault */
AnnaBridge 156:ff21514d8981 428 CLEAR_BIT(SCB->SHCSR, Fault);
AnnaBridge 156:ff21514d8981 429 }
AnnaBridge 156:ff21514d8981 430
AnnaBridge 156:ff21514d8981 431 /**
AnnaBridge 156:ff21514d8981 432 * @}
AnnaBridge 156:ff21514d8981 433 */
AnnaBridge 156:ff21514d8981 434
AnnaBridge 156:ff21514d8981 435 /** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
AnnaBridge 156:ff21514d8981 436 * @{
AnnaBridge 156:ff21514d8981 437 */
AnnaBridge 156:ff21514d8981 438
AnnaBridge 156:ff21514d8981 439 /**
AnnaBridge 156:ff21514d8981 440 * @brief Get Implementer code
AnnaBridge 156:ff21514d8981 441 * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
AnnaBridge 156:ff21514d8981 442 * @retval Value should be equal to 0x41 for ARM
AnnaBridge 156:ff21514d8981 443 */
AnnaBridge 156:ff21514d8981 444 __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
AnnaBridge 156:ff21514d8981 445 {
AnnaBridge 156:ff21514d8981 446 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
AnnaBridge 156:ff21514d8981 447 }
AnnaBridge 156:ff21514d8981 448
AnnaBridge 156:ff21514d8981 449 /**
AnnaBridge 156:ff21514d8981 450 * @brief Get Variant number (The r value in the rnpn product revision identifier)
AnnaBridge 156:ff21514d8981 451 * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
AnnaBridge 156:ff21514d8981 452 * @retval Value between 0 and 255 (0x0: revision 0)
AnnaBridge 156:ff21514d8981 453 */
AnnaBridge 156:ff21514d8981 454 __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
AnnaBridge 156:ff21514d8981 455 {
AnnaBridge 156:ff21514d8981 456 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
AnnaBridge 156:ff21514d8981 457 }
AnnaBridge 156:ff21514d8981 458
AnnaBridge 156:ff21514d8981 459 /**
AnnaBridge 156:ff21514d8981 460 * @brief Get Constant number
AnnaBridge 156:ff21514d8981 461 * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant
AnnaBridge 156:ff21514d8981 462 * @retval Value should be equal to 0xF for Cortex-M4 devices
AnnaBridge 156:ff21514d8981 463 */
AnnaBridge 156:ff21514d8981 464 __STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
AnnaBridge 156:ff21514d8981 465 {
AnnaBridge 156:ff21514d8981 466 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
AnnaBridge 156:ff21514d8981 467 }
AnnaBridge 156:ff21514d8981 468
AnnaBridge 156:ff21514d8981 469 /**
AnnaBridge 156:ff21514d8981 470 * @brief Get Part number
AnnaBridge 156:ff21514d8981 471 * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
AnnaBridge 156:ff21514d8981 472 * @retval Value should be equal to 0xC24 for Cortex-M4
AnnaBridge 156:ff21514d8981 473 */
AnnaBridge 156:ff21514d8981 474 __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
AnnaBridge 156:ff21514d8981 475 {
AnnaBridge 156:ff21514d8981 476 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
AnnaBridge 156:ff21514d8981 477 }
AnnaBridge 156:ff21514d8981 478
AnnaBridge 156:ff21514d8981 479 /**
AnnaBridge 156:ff21514d8981 480 * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
AnnaBridge 156:ff21514d8981 481 * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
AnnaBridge 156:ff21514d8981 482 * @retval Value between 0 and 255 (0x1: patch 1)
AnnaBridge 156:ff21514d8981 483 */
AnnaBridge 156:ff21514d8981 484 __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
AnnaBridge 156:ff21514d8981 485 {
AnnaBridge 156:ff21514d8981 486 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
AnnaBridge 156:ff21514d8981 487 }
AnnaBridge 156:ff21514d8981 488
AnnaBridge 156:ff21514d8981 489 /**
AnnaBridge 156:ff21514d8981 490 * @}
AnnaBridge 156:ff21514d8981 491 */
AnnaBridge 156:ff21514d8981 492
AnnaBridge 156:ff21514d8981 493 #if __MPU_PRESENT
AnnaBridge 156:ff21514d8981 494 /** @defgroup CORTEX_LL_EF_MPU MPU
AnnaBridge 156:ff21514d8981 495 * @{
AnnaBridge 156:ff21514d8981 496 */
AnnaBridge 156:ff21514d8981 497
AnnaBridge 156:ff21514d8981 498 /**
AnnaBridge 156:ff21514d8981 499 * @brief Enable MPU with input options
AnnaBridge 156:ff21514d8981 500 * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
AnnaBridge 156:ff21514d8981 501 * @param Options This parameter can be one of the following values:
AnnaBridge 156:ff21514d8981 502 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
AnnaBridge 156:ff21514d8981 503 * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
AnnaBridge 156:ff21514d8981 504 * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
AnnaBridge 156:ff21514d8981 505 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
AnnaBridge 156:ff21514d8981 506 * @retval None
AnnaBridge 156:ff21514d8981 507 */
AnnaBridge 156:ff21514d8981 508 __STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
AnnaBridge 156:ff21514d8981 509 {
AnnaBridge 156:ff21514d8981 510 /* Enable the MPU*/
AnnaBridge 156:ff21514d8981 511 WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
AnnaBridge 156:ff21514d8981 512 /* Ensure MPU settings take effects */
AnnaBridge 156:ff21514d8981 513 __DSB();
AnnaBridge 156:ff21514d8981 514 /* Sequence instruction fetches using update settings */
AnnaBridge 156:ff21514d8981 515 __ISB();
AnnaBridge 156:ff21514d8981 516 }
AnnaBridge 156:ff21514d8981 517
AnnaBridge 156:ff21514d8981 518 /**
AnnaBridge 156:ff21514d8981 519 * @brief Disable MPU
AnnaBridge 156:ff21514d8981 520 * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable
AnnaBridge 156:ff21514d8981 521 * @retval None
AnnaBridge 156:ff21514d8981 522 */
AnnaBridge 156:ff21514d8981 523 __STATIC_INLINE void LL_MPU_Disable(void)
AnnaBridge 156:ff21514d8981 524 {
AnnaBridge 156:ff21514d8981 525 /* Make sure outstanding transfers are done */
AnnaBridge 156:ff21514d8981 526 __DMB();
AnnaBridge 156:ff21514d8981 527 /* Disable MPU*/
AnnaBridge 156:ff21514d8981 528 WRITE_REG(MPU->CTRL, 0U);
AnnaBridge 156:ff21514d8981 529 }
AnnaBridge 156:ff21514d8981 530
AnnaBridge 156:ff21514d8981 531 /**
AnnaBridge 156:ff21514d8981 532 * @brief Check if MPU is enabled or not
AnnaBridge 156:ff21514d8981 533 * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
AnnaBridge 156:ff21514d8981 534 * @retval State of bit (1 or 0).
AnnaBridge 156:ff21514d8981 535 */
AnnaBridge 156:ff21514d8981 536 __STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
AnnaBridge 156:ff21514d8981 537 {
AnnaBridge 156:ff21514d8981 538 return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk));
AnnaBridge 156:ff21514d8981 539 }
AnnaBridge 156:ff21514d8981 540
AnnaBridge 156:ff21514d8981 541 /**
AnnaBridge 156:ff21514d8981 542 * @brief Enable a MPU region
AnnaBridge 156:ff21514d8981 543 * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion
AnnaBridge 156:ff21514d8981 544 * @param Region This parameter can be one of the following values:
AnnaBridge 156:ff21514d8981 545 * @arg @ref LL_MPU_REGION_NUMBER0
AnnaBridge 156:ff21514d8981 546 * @arg @ref LL_MPU_REGION_NUMBER1
AnnaBridge 156:ff21514d8981 547 * @arg @ref LL_MPU_REGION_NUMBER2
AnnaBridge 156:ff21514d8981 548 * @arg @ref LL_MPU_REGION_NUMBER3
AnnaBridge 156:ff21514d8981 549 * @arg @ref LL_MPU_REGION_NUMBER4
AnnaBridge 156:ff21514d8981 550 * @arg @ref LL_MPU_REGION_NUMBER5
AnnaBridge 156:ff21514d8981 551 * @arg @ref LL_MPU_REGION_NUMBER6
AnnaBridge 156:ff21514d8981 552 * @arg @ref LL_MPU_REGION_NUMBER7
AnnaBridge 156:ff21514d8981 553 * @retval None
AnnaBridge 156:ff21514d8981 554 */
AnnaBridge 156:ff21514d8981 555 __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
AnnaBridge 156:ff21514d8981 556 {
AnnaBridge 156:ff21514d8981 557 /* Set Region number */
AnnaBridge 156:ff21514d8981 558 WRITE_REG(MPU->RNR, Region);
AnnaBridge 156:ff21514d8981 559 /* Enable the MPU region */
AnnaBridge 156:ff21514d8981 560 SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
AnnaBridge 156:ff21514d8981 561 }
AnnaBridge 156:ff21514d8981 562
AnnaBridge 156:ff21514d8981 563 /**
AnnaBridge 156:ff21514d8981 564 * @brief Configure and enable a region
AnnaBridge 156:ff21514d8981 565 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
AnnaBridge 156:ff21514d8981 566 * MPU_RBAR REGION LL_MPU_ConfigRegion\n
AnnaBridge 156:ff21514d8981 567 * MPU_RBAR ADDR LL_MPU_ConfigRegion\n
AnnaBridge 156:ff21514d8981 568 * MPU_RASR XN LL_MPU_ConfigRegion\n
AnnaBridge 156:ff21514d8981 569 * MPU_RASR AP LL_MPU_ConfigRegion\n
AnnaBridge 156:ff21514d8981 570 * MPU_RASR S LL_MPU_ConfigRegion\n
AnnaBridge 156:ff21514d8981 571 * MPU_RASR C LL_MPU_ConfigRegion\n
AnnaBridge 156:ff21514d8981 572 * MPU_RASR B LL_MPU_ConfigRegion\n
AnnaBridge 156:ff21514d8981 573 * MPU_RASR SIZE LL_MPU_ConfigRegion
AnnaBridge 156:ff21514d8981 574 * @param Region This parameter can be one of the following values:
AnnaBridge 156:ff21514d8981 575 * @arg @ref LL_MPU_REGION_NUMBER0
AnnaBridge 156:ff21514d8981 576 * @arg @ref LL_MPU_REGION_NUMBER1
AnnaBridge 156:ff21514d8981 577 * @arg @ref LL_MPU_REGION_NUMBER2
AnnaBridge 156:ff21514d8981 578 * @arg @ref LL_MPU_REGION_NUMBER3
AnnaBridge 156:ff21514d8981 579 * @arg @ref LL_MPU_REGION_NUMBER4
AnnaBridge 156:ff21514d8981 580 * @arg @ref LL_MPU_REGION_NUMBER5
AnnaBridge 156:ff21514d8981 581 * @arg @ref LL_MPU_REGION_NUMBER6
AnnaBridge 156:ff21514d8981 582 * @arg @ref LL_MPU_REGION_NUMBER7
AnnaBridge 156:ff21514d8981 583 * @param Address Value of region base address
AnnaBridge 156:ff21514d8981 584 * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
AnnaBridge 156:ff21514d8981 585 * @param Attributes This parameter can be a combination of the following values:
AnnaBridge 156:ff21514d8981 586 * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
AnnaBridge 156:ff21514d8981 587 * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
AnnaBridge 156:ff21514d8981 588 * or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
AnnaBridge 156:ff21514d8981 589 * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
AnnaBridge 156:ff21514d8981 590 * or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
AnnaBridge 156:ff21514d8981 591 * or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
AnnaBridge 156:ff21514d8981 592 * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
AnnaBridge 156:ff21514d8981 593 * or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
AnnaBridge 156:ff21514d8981 594 * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
AnnaBridge 156:ff21514d8981 595 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
AnnaBridge 156:ff21514d8981 596 * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
AnnaBridge 156:ff21514d8981 597 * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
AnnaBridge 156:ff21514d8981 598 * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
AnnaBridge 156:ff21514d8981 599 * @retval None
AnnaBridge 156:ff21514d8981 600 */
AnnaBridge 156:ff21514d8981 601 __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
AnnaBridge 156:ff21514d8981 602 {
AnnaBridge 156:ff21514d8981 603 /* Set Region number */
AnnaBridge 156:ff21514d8981 604 WRITE_REG(MPU->RNR, Region);
AnnaBridge 156:ff21514d8981 605 /* Set base address */
AnnaBridge 156:ff21514d8981 606 WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
AnnaBridge 156:ff21514d8981 607 /* Configure MPU */
AnnaBridge 156:ff21514d8981 608 WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos));
AnnaBridge 156:ff21514d8981 609 }
AnnaBridge 156:ff21514d8981 610
AnnaBridge 156:ff21514d8981 611 /**
AnnaBridge 156:ff21514d8981 612 * @brief Disable a region
AnnaBridge 156:ff21514d8981 613 * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
AnnaBridge 156:ff21514d8981 614 * MPU_RASR ENABLE LL_MPU_DisableRegion
AnnaBridge 156:ff21514d8981 615 * @param Region This parameter can be one of the following values:
AnnaBridge 156:ff21514d8981 616 * @arg @ref LL_MPU_REGION_NUMBER0
AnnaBridge 156:ff21514d8981 617 * @arg @ref LL_MPU_REGION_NUMBER1
AnnaBridge 156:ff21514d8981 618 * @arg @ref LL_MPU_REGION_NUMBER2
AnnaBridge 156:ff21514d8981 619 * @arg @ref LL_MPU_REGION_NUMBER3
AnnaBridge 156:ff21514d8981 620 * @arg @ref LL_MPU_REGION_NUMBER4
AnnaBridge 156:ff21514d8981 621 * @arg @ref LL_MPU_REGION_NUMBER5
AnnaBridge 156:ff21514d8981 622 * @arg @ref LL_MPU_REGION_NUMBER6
AnnaBridge 156:ff21514d8981 623 * @arg @ref LL_MPU_REGION_NUMBER7
AnnaBridge 156:ff21514d8981 624 * @retval None
AnnaBridge 156:ff21514d8981 625 */
AnnaBridge 156:ff21514d8981 626 __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
AnnaBridge 156:ff21514d8981 627 {
AnnaBridge 156:ff21514d8981 628 /* Set Region number */
AnnaBridge 156:ff21514d8981 629 WRITE_REG(MPU->RNR, Region);
AnnaBridge 156:ff21514d8981 630 /* Disable the MPU region */
AnnaBridge 156:ff21514d8981 631 CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
AnnaBridge 156:ff21514d8981 632 }
AnnaBridge 156:ff21514d8981 633
AnnaBridge 156:ff21514d8981 634 /**
AnnaBridge 156:ff21514d8981 635 * @}
AnnaBridge 156:ff21514d8981 636 */
AnnaBridge 156:ff21514d8981 637
AnnaBridge 156:ff21514d8981 638 #endif /* __MPU_PRESENT */
AnnaBridge 156:ff21514d8981 639 /**
AnnaBridge 156:ff21514d8981 640 * @}
AnnaBridge 156:ff21514d8981 641 */
AnnaBridge 156:ff21514d8981 642
AnnaBridge 156:ff21514d8981 643 /**
AnnaBridge 156:ff21514d8981 644 * @}
AnnaBridge 156:ff21514d8981 645 */
AnnaBridge 156:ff21514d8981 646
AnnaBridge 156:ff21514d8981 647 /**
AnnaBridge 156:ff21514d8981 648 * @}
AnnaBridge 156:ff21514d8981 649 */
AnnaBridge 156:ff21514d8981 650
AnnaBridge 156:ff21514d8981 651 #ifdef __cplusplus
AnnaBridge 156:ff21514d8981 652 }
AnnaBridge 156:ff21514d8981 653 #endif
AnnaBridge 156:ff21514d8981 654
AnnaBridge 156:ff21514d8981 655 #endif /* __STM32L4xx_LL_CORTEX_H */
AnnaBridge 156:ff21514d8981 656
AnnaBridge 156:ff21514d8981 657 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/