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TARGET_NUCLEO_F410RB/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_spi.h@157:e7ca05fa8600, 2017-11-09 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 09 11:14:10 2017 +0000
Revision:
157:e7ca05fa8600
Parent:
156:ff21514d8981
Child:
163:e59c8e839560
Release 155 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 156:ff21514d8981 1 /**
AnnaBridge 156:ff21514d8981 2 ******************************************************************************
AnnaBridge 156:ff21514d8981 3 * @file stm32f4xx_hal_spi.h
AnnaBridge 156:ff21514d8981 4 * @author MCD Application Team
AnnaBridge 156:ff21514d8981 5 * @version V1.7.1
AnnaBridge 156:ff21514d8981 6 * @date 14-April-2017
AnnaBridge 156:ff21514d8981 7 * @brief Header file of SPI HAL module.
AnnaBridge 156:ff21514d8981 8 ******************************************************************************
AnnaBridge 156:ff21514d8981 9 * @attention
AnnaBridge 156:ff21514d8981 10 *
AnnaBridge 156:ff21514d8981 11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge 156:ff21514d8981 12 *
AnnaBridge 156:ff21514d8981 13 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 156:ff21514d8981 14 * are permitted provided that the following conditions are met:
AnnaBridge 156:ff21514d8981 15 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 156:ff21514d8981 16 * this list of conditions and the following disclaimer.
AnnaBridge 156:ff21514d8981 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 156:ff21514d8981 18 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 156:ff21514d8981 19 * and/or other materials provided with the distribution.
AnnaBridge 156:ff21514d8981 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 156:ff21514d8981 21 * may be used to endorse or promote products derived from this software
AnnaBridge 156:ff21514d8981 22 * without specific prior written permission.
AnnaBridge 156:ff21514d8981 23 *
AnnaBridge 156:ff21514d8981 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 156:ff21514d8981 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 156:ff21514d8981 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 156:ff21514d8981 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 156:ff21514d8981 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 156:ff21514d8981 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 156:ff21514d8981 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 156:ff21514d8981 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 156:ff21514d8981 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 156:ff21514d8981 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 156:ff21514d8981 34 *
AnnaBridge 156:ff21514d8981 35 ******************************************************************************
AnnaBridge 156:ff21514d8981 36 */
AnnaBridge 156:ff21514d8981 37
AnnaBridge 156:ff21514d8981 38 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 156:ff21514d8981 39 #ifndef __STM32F4xx_HAL_SPI_H
AnnaBridge 156:ff21514d8981 40 #define __STM32F4xx_HAL_SPI_H
AnnaBridge 156:ff21514d8981 41
AnnaBridge 156:ff21514d8981 42 #ifdef __cplusplus
AnnaBridge 156:ff21514d8981 43 extern "C" {
AnnaBridge 156:ff21514d8981 44 #endif
AnnaBridge 156:ff21514d8981 45
AnnaBridge 156:ff21514d8981 46 /* Includes ------------------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 47 #include "stm32f4xx_hal_def.h"
AnnaBridge 156:ff21514d8981 48
AnnaBridge 156:ff21514d8981 49 /** @addtogroup STM32F4xx_HAL_Driver
AnnaBridge 156:ff21514d8981 50 * @{
AnnaBridge 156:ff21514d8981 51 */
AnnaBridge 156:ff21514d8981 52
AnnaBridge 156:ff21514d8981 53 /** @addtogroup SPI
AnnaBridge 156:ff21514d8981 54 * @{
AnnaBridge 156:ff21514d8981 55 */
AnnaBridge 156:ff21514d8981 56
AnnaBridge 156:ff21514d8981 57 /* Exported types ------------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 58 /** @defgroup SPI_Exported_Types SPI Exported Types
AnnaBridge 156:ff21514d8981 59 * @{
AnnaBridge 156:ff21514d8981 60 */
AnnaBridge 156:ff21514d8981 61
AnnaBridge 156:ff21514d8981 62 /**
AnnaBridge 156:ff21514d8981 63 * @brief SPI Configuration Structure definition
AnnaBridge 156:ff21514d8981 64 */
AnnaBridge 156:ff21514d8981 65 typedef struct
AnnaBridge 156:ff21514d8981 66 {
AnnaBridge 156:ff21514d8981 67 uint32_t Mode; /*!< Specifies the SPI operating mode.
AnnaBridge 156:ff21514d8981 68 This parameter can be a value of @ref SPI_Mode */
AnnaBridge 156:ff21514d8981 69
AnnaBridge 156:ff21514d8981 70 uint32_t Direction; /*!< Specifies the SPI bidirectional mode state.
AnnaBridge 156:ff21514d8981 71 This parameter can be a value of @ref SPI_Direction */
AnnaBridge 156:ff21514d8981 72
AnnaBridge 156:ff21514d8981 73 uint32_t DataSize; /*!< Specifies the SPI data size.
AnnaBridge 156:ff21514d8981 74 This parameter can be a value of @ref SPI_Data_Size */
AnnaBridge 156:ff21514d8981 75
AnnaBridge 156:ff21514d8981 76 uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
AnnaBridge 156:ff21514d8981 77 This parameter can be a value of @ref SPI_Clock_Polarity */
AnnaBridge 156:ff21514d8981 78
AnnaBridge 156:ff21514d8981 79 uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture.
AnnaBridge 156:ff21514d8981 80 This parameter can be a value of @ref SPI_Clock_Phase */
AnnaBridge 156:ff21514d8981 81
AnnaBridge 156:ff21514d8981 82 uint32_t NSS; /*!< Specifies whether the NSS signal is managed by
AnnaBridge 156:ff21514d8981 83 hardware (NSS pin) or by software using the SSI bit.
AnnaBridge 156:ff21514d8981 84 This parameter can be a value of @ref SPI_Slave_Select_management */
AnnaBridge 156:ff21514d8981 85
AnnaBridge 156:ff21514d8981 86 uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
AnnaBridge 156:ff21514d8981 87 used to configure the transmit and receive SCK clock.
AnnaBridge 156:ff21514d8981 88 This parameter can be a value of @ref SPI_BaudRate_Prescaler
AnnaBridge 156:ff21514d8981 89 @note The communication clock is derived from the master
AnnaBridge 156:ff21514d8981 90 clock. The slave clock does not need to be set. */
AnnaBridge 156:ff21514d8981 91
AnnaBridge 156:ff21514d8981 92 uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
AnnaBridge 156:ff21514d8981 93 This parameter can be a value of @ref SPI_MSB_LSB_transmission */
AnnaBridge 156:ff21514d8981 94
AnnaBridge 156:ff21514d8981 95 uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not.
AnnaBridge 156:ff21514d8981 96 This parameter can be a value of @ref SPI_TI_mode */
AnnaBridge 156:ff21514d8981 97
AnnaBridge 156:ff21514d8981 98 uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
AnnaBridge 156:ff21514d8981 99 This parameter can be a value of @ref SPI_CRC_Calculation */
AnnaBridge 156:ff21514d8981 100
AnnaBridge 156:ff21514d8981 101 uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
AnnaBridge 156:ff21514d8981 102 This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */
AnnaBridge 156:ff21514d8981 103 }SPI_InitTypeDef;
AnnaBridge 156:ff21514d8981 104
AnnaBridge 156:ff21514d8981 105 /**
AnnaBridge 156:ff21514d8981 106 * @brief HAL SPI State structure definition
AnnaBridge 156:ff21514d8981 107 */
AnnaBridge 156:ff21514d8981 108 typedef enum
AnnaBridge 156:ff21514d8981 109 {
AnnaBridge 156:ff21514d8981 110 HAL_SPI_STATE_RESET = 0x00U, /*!< Peripheral not Initialized */
AnnaBridge 156:ff21514d8981 111 HAL_SPI_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
AnnaBridge 156:ff21514d8981 112 HAL_SPI_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
AnnaBridge 156:ff21514d8981 113 HAL_SPI_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */
AnnaBridge 156:ff21514d8981 114 HAL_SPI_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */
AnnaBridge 156:ff21514d8981 115 HAL_SPI_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */
AnnaBridge 156:ff21514d8981 116 HAL_SPI_STATE_ERROR = 0x06U /*!< SPI error state */
AnnaBridge 156:ff21514d8981 117 }HAL_SPI_StateTypeDef;
AnnaBridge 156:ff21514d8981 118
AnnaBridge 156:ff21514d8981 119 /**
AnnaBridge 156:ff21514d8981 120 * @brief SPI handle Structure definition
AnnaBridge 156:ff21514d8981 121 */
AnnaBridge 156:ff21514d8981 122 typedef struct __SPI_HandleTypeDef
AnnaBridge 156:ff21514d8981 123 {
AnnaBridge 156:ff21514d8981 124 SPI_TypeDef *Instance; /* SPI registers base address */
AnnaBridge 156:ff21514d8981 125
AnnaBridge 156:ff21514d8981 126 SPI_InitTypeDef Init; /* SPI communication parameters */
AnnaBridge 156:ff21514d8981 127
AnnaBridge 156:ff21514d8981 128 uint8_t *pTxBuffPtr; /* Pointer to SPI Tx transfer Buffer */
AnnaBridge 156:ff21514d8981 129
AnnaBridge 156:ff21514d8981 130 uint16_t TxXferSize; /* SPI Tx Transfer size */
AnnaBridge 156:ff21514d8981 131
AnnaBridge 156:ff21514d8981 132 __IO uint16_t TxXferCount; /* SPI Tx Transfer Counter */
AnnaBridge 156:ff21514d8981 133
AnnaBridge 156:ff21514d8981 134 uint8_t *pRxBuffPtr; /* Pointer to SPI Rx transfer Buffer */
AnnaBridge 156:ff21514d8981 135
AnnaBridge 156:ff21514d8981 136 uint16_t RxXferSize; /* SPI Rx Transfer size */
AnnaBridge 156:ff21514d8981 137
AnnaBridge 156:ff21514d8981 138 __IO uint16_t RxXferCount; /* SPI Rx Transfer Counter */
AnnaBridge 156:ff21514d8981 139
AnnaBridge 156:ff21514d8981 140 void (*RxISR)(struct __SPI_HandleTypeDef * hspi); /* function pointer on Rx ISR */
AnnaBridge 156:ff21514d8981 141
AnnaBridge 156:ff21514d8981 142 void (*TxISR)(struct __SPI_HandleTypeDef * hspi); /* function pointer on Tx ISR */
AnnaBridge 156:ff21514d8981 143
AnnaBridge 156:ff21514d8981 144 DMA_HandleTypeDef *hdmatx; /* SPI Tx DMA Handle parameters */
AnnaBridge 156:ff21514d8981 145
AnnaBridge 156:ff21514d8981 146 DMA_HandleTypeDef *hdmarx; /* SPI Rx DMA Handle parameters */
AnnaBridge 156:ff21514d8981 147
AnnaBridge 156:ff21514d8981 148 HAL_LockTypeDef Lock; /* Locking object */
AnnaBridge 156:ff21514d8981 149
AnnaBridge 156:ff21514d8981 150 __IO HAL_SPI_StateTypeDef State; /* SPI communication state */
AnnaBridge 156:ff21514d8981 151
AnnaBridge 156:ff21514d8981 152 __IO uint32_t ErrorCode; /* SPI Error code */
AnnaBridge 156:ff21514d8981 153
AnnaBridge 156:ff21514d8981 154 }SPI_HandleTypeDef;
AnnaBridge 156:ff21514d8981 155
AnnaBridge 156:ff21514d8981 156 /**
AnnaBridge 156:ff21514d8981 157 * @}
AnnaBridge 156:ff21514d8981 158 */
AnnaBridge 156:ff21514d8981 159
AnnaBridge 156:ff21514d8981 160 /* Exported constants --------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 161 /** @defgroup SPI_Exported_Constants SPI Exported Constants
AnnaBridge 156:ff21514d8981 162 * @{
AnnaBridge 156:ff21514d8981 163 */
AnnaBridge 156:ff21514d8981 164
AnnaBridge 156:ff21514d8981 165 /** @defgroup SPI_Error_Code SPI Error Code
AnnaBridge 156:ff21514d8981 166 * @{
AnnaBridge 156:ff21514d8981 167 */
AnnaBridge 156:ff21514d8981 168 #define HAL_SPI_ERROR_NONE 0x00000000U /*!< No error */
AnnaBridge 156:ff21514d8981 169 #define HAL_SPI_ERROR_MODF 0x00000001U /*!< MODF error */
AnnaBridge 156:ff21514d8981 170 #define HAL_SPI_ERROR_CRC 0x00000002U /*!< CRC error */
AnnaBridge 156:ff21514d8981 171 #define HAL_SPI_ERROR_OVR 0x00000004U /*!< OVR error */
AnnaBridge 156:ff21514d8981 172 #define HAL_SPI_ERROR_FRE 0x00000008U /*!< FRE error */
AnnaBridge 156:ff21514d8981 173 #define HAL_SPI_ERROR_DMA 0x00000010U /*!< DMA transfer error */
AnnaBridge 156:ff21514d8981 174 #define HAL_SPI_ERROR_FLAG 0x00000020U /*!< Flag: RXNE,TXE, BSY */
AnnaBridge 156:ff21514d8981 175 /**
AnnaBridge 156:ff21514d8981 176 * @}
AnnaBridge 156:ff21514d8981 177 */
AnnaBridge 156:ff21514d8981 178
AnnaBridge 156:ff21514d8981 179 /** @defgroup SPI_Mode SPI Mode
AnnaBridge 156:ff21514d8981 180 * @{
AnnaBridge 156:ff21514d8981 181 */
AnnaBridge 156:ff21514d8981 182 #define SPI_MODE_SLAVE 0x00000000U
AnnaBridge 156:ff21514d8981 183 #define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
AnnaBridge 156:ff21514d8981 184 /**
AnnaBridge 156:ff21514d8981 185 * @}
AnnaBridge 156:ff21514d8981 186 */
AnnaBridge 156:ff21514d8981 187
AnnaBridge 156:ff21514d8981 188 /** @defgroup SPI_Direction SPI Direction Mode
AnnaBridge 156:ff21514d8981 189 * @{
AnnaBridge 156:ff21514d8981 190 */
AnnaBridge 156:ff21514d8981 191 #define SPI_DIRECTION_2LINES 0x00000000U
AnnaBridge 156:ff21514d8981 192 #define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
AnnaBridge 156:ff21514d8981 193 #define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
AnnaBridge 156:ff21514d8981 194 /**
AnnaBridge 156:ff21514d8981 195 * @}
AnnaBridge 156:ff21514d8981 196 */
AnnaBridge 156:ff21514d8981 197
AnnaBridge 156:ff21514d8981 198 /** @defgroup SPI_Data_Size SPI Data Size
AnnaBridge 156:ff21514d8981 199 * @{
AnnaBridge 156:ff21514d8981 200 */
AnnaBridge 156:ff21514d8981 201 #define SPI_DATASIZE_8BIT 0x00000000U
AnnaBridge 156:ff21514d8981 202 #define SPI_DATASIZE_16BIT SPI_CR1_DFF
AnnaBridge 156:ff21514d8981 203 /**
AnnaBridge 156:ff21514d8981 204 * @}
AnnaBridge 156:ff21514d8981 205 */
AnnaBridge 156:ff21514d8981 206
AnnaBridge 156:ff21514d8981 207 /** @defgroup SPI_Clock_Polarity SPI Clock Polarity
AnnaBridge 156:ff21514d8981 208 * @{
AnnaBridge 156:ff21514d8981 209 */
AnnaBridge 156:ff21514d8981 210 #define SPI_POLARITY_LOW 0x00000000U
AnnaBridge 156:ff21514d8981 211 #define SPI_POLARITY_HIGH SPI_CR1_CPOL
AnnaBridge 156:ff21514d8981 212 /**
AnnaBridge 156:ff21514d8981 213 * @}
AnnaBridge 156:ff21514d8981 214 */
AnnaBridge 156:ff21514d8981 215
AnnaBridge 156:ff21514d8981 216 /** @defgroup SPI_Clock_Phase SPI Clock Phase
AnnaBridge 156:ff21514d8981 217 * @{
AnnaBridge 156:ff21514d8981 218 */
AnnaBridge 156:ff21514d8981 219 #define SPI_PHASE_1EDGE 0x00000000U
AnnaBridge 156:ff21514d8981 220 #define SPI_PHASE_2EDGE SPI_CR1_CPHA
AnnaBridge 156:ff21514d8981 221 /**
AnnaBridge 156:ff21514d8981 222 * @}
AnnaBridge 156:ff21514d8981 223 */
AnnaBridge 156:ff21514d8981 224
AnnaBridge 156:ff21514d8981 225 /** @defgroup SPI_Slave_Select_management SPI Slave Select Management
AnnaBridge 156:ff21514d8981 226 * @{
AnnaBridge 156:ff21514d8981 227 */
AnnaBridge 156:ff21514d8981 228 #define SPI_NSS_SOFT SPI_CR1_SSM
AnnaBridge 156:ff21514d8981 229 #define SPI_NSS_HARD_INPUT 0x00000000U
AnnaBridge 156:ff21514d8981 230 #define SPI_NSS_HARD_OUTPUT 0x00040000U
AnnaBridge 156:ff21514d8981 231 /**
AnnaBridge 156:ff21514d8981 232 * @}
AnnaBridge 156:ff21514d8981 233 */
AnnaBridge 156:ff21514d8981 234
AnnaBridge 156:ff21514d8981 235 /** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
AnnaBridge 156:ff21514d8981 236 * @{
AnnaBridge 156:ff21514d8981 237 */
AnnaBridge 156:ff21514d8981 238 #define SPI_BAUDRATEPRESCALER_2 0x00000000U
AnnaBridge 156:ff21514d8981 239 #define SPI_BAUDRATEPRESCALER_4 0x00000008U
AnnaBridge 156:ff21514d8981 240 #define SPI_BAUDRATEPRESCALER_8 0x00000010U
AnnaBridge 156:ff21514d8981 241 #define SPI_BAUDRATEPRESCALER_16 0x00000018U
AnnaBridge 156:ff21514d8981 242 #define SPI_BAUDRATEPRESCALER_32 0x00000020U
AnnaBridge 156:ff21514d8981 243 #define SPI_BAUDRATEPRESCALER_64 0x00000028U
AnnaBridge 156:ff21514d8981 244 #define SPI_BAUDRATEPRESCALER_128 0x00000030U
AnnaBridge 156:ff21514d8981 245 #define SPI_BAUDRATEPRESCALER_256 0x00000038U
AnnaBridge 156:ff21514d8981 246 /**
AnnaBridge 156:ff21514d8981 247 * @}
AnnaBridge 156:ff21514d8981 248 */
AnnaBridge 156:ff21514d8981 249
AnnaBridge 156:ff21514d8981 250 /** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission
AnnaBridge 156:ff21514d8981 251 * @{
AnnaBridge 156:ff21514d8981 252 */
AnnaBridge 156:ff21514d8981 253 #define SPI_FIRSTBIT_MSB 0x00000000U
AnnaBridge 156:ff21514d8981 254 #define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
AnnaBridge 156:ff21514d8981 255 /**
AnnaBridge 156:ff21514d8981 256 * @}
AnnaBridge 156:ff21514d8981 257 */
AnnaBridge 156:ff21514d8981 258
AnnaBridge 156:ff21514d8981 259 /** @defgroup SPI_TI_mode SPI TI Mode
AnnaBridge 156:ff21514d8981 260 * @{
AnnaBridge 156:ff21514d8981 261 */
AnnaBridge 156:ff21514d8981 262 #define SPI_TIMODE_DISABLE 0x00000000U
AnnaBridge 156:ff21514d8981 263 #define SPI_TIMODE_ENABLE SPI_CR2_FRF
AnnaBridge 156:ff21514d8981 264 /**
AnnaBridge 156:ff21514d8981 265 * @}
AnnaBridge 156:ff21514d8981 266 */
AnnaBridge 156:ff21514d8981 267
AnnaBridge 156:ff21514d8981 268 /** @defgroup SPI_CRC_Calculation SPI CRC Calculation
AnnaBridge 156:ff21514d8981 269 * @{
AnnaBridge 156:ff21514d8981 270 */
AnnaBridge 156:ff21514d8981 271 #define SPI_CRCCALCULATION_DISABLE 0x00000000U
AnnaBridge 156:ff21514d8981 272 #define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN
AnnaBridge 156:ff21514d8981 273 /**
AnnaBridge 156:ff21514d8981 274 * @}
AnnaBridge 156:ff21514d8981 275 */
AnnaBridge 156:ff21514d8981 276
AnnaBridge 156:ff21514d8981 277 /** @defgroup SPI_Interrupt_definition SPI Interrupt Definition
AnnaBridge 156:ff21514d8981 278 * @{
AnnaBridge 156:ff21514d8981 279 */
AnnaBridge 156:ff21514d8981 280 #define SPI_IT_TXE SPI_CR2_TXEIE
AnnaBridge 156:ff21514d8981 281 #define SPI_IT_RXNE SPI_CR2_RXNEIE
AnnaBridge 156:ff21514d8981 282 #define SPI_IT_ERR SPI_CR2_ERRIE
AnnaBridge 156:ff21514d8981 283 /**
AnnaBridge 156:ff21514d8981 284 * @}
AnnaBridge 156:ff21514d8981 285 */
AnnaBridge 156:ff21514d8981 286
AnnaBridge 156:ff21514d8981 287 /** @defgroup SPI_Flags_definition SPI Flags Definition
AnnaBridge 156:ff21514d8981 288 * @{
AnnaBridge 156:ff21514d8981 289 */
AnnaBridge 156:ff21514d8981 290 #define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */
AnnaBridge 156:ff21514d8981 291 #define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */
AnnaBridge 156:ff21514d8981 292 #define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */
AnnaBridge 156:ff21514d8981 293 #define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
AnnaBridge 156:ff21514d8981 294 #define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */
AnnaBridge 156:ff21514d8981 295 #define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */
AnnaBridge 156:ff21514d8981 296 #define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */
AnnaBridge 156:ff21514d8981 297 /**
AnnaBridge 156:ff21514d8981 298 * @}
AnnaBridge 156:ff21514d8981 299 */
AnnaBridge 156:ff21514d8981 300
AnnaBridge 156:ff21514d8981 301 /**
AnnaBridge 156:ff21514d8981 302 * @}
AnnaBridge 156:ff21514d8981 303 */
AnnaBridge 156:ff21514d8981 304
AnnaBridge 156:ff21514d8981 305 /* Exported macro ------------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 306 /** @defgroup SPI_Exported_Macros SPI Exported Macros
AnnaBridge 156:ff21514d8981 307 * @{
AnnaBridge 156:ff21514d8981 308 */
AnnaBridge 156:ff21514d8981 309
AnnaBridge 156:ff21514d8981 310 /** @brief Reset SPI handle state.
AnnaBridge 156:ff21514d8981 311 * @param __HANDLE__: specifies the SPI Handle.
AnnaBridge 156:ff21514d8981 312 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
AnnaBridge 156:ff21514d8981 313 * @retval None
AnnaBridge 156:ff21514d8981 314 */
AnnaBridge 156:ff21514d8981 315 #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
AnnaBridge 156:ff21514d8981 316
AnnaBridge 156:ff21514d8981 317 /** @brief Enable or disable the specified SPI interrupts.
AnnaBridge 156:ff21514d8981 318 * @param __HANDLE__: specifies the SPI Handle.
AnnaBridge 156:ff21514d8981 319 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
AnnaBridge 156:ff21514d8981 320 * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
AnnaBridge 156:ff21514d8981 321 * This parameter can be one of the following values:
AnnaBridge 156:ff21514d8981 322 * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
AnnaBridge 156:ff21514d8981 323 * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
AnnaBridge 156:ff21514d8981 324 * @arg SPI_IT_ERR: Error interrupt enable
AnnaBridge 156:ff21514d8981 325 * @retval None
AnnaBridge 156:ff21514d8981 326 */
AnnaBridge 156:ff21514d8981 327 #define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
AnnaBridge 156:ff21514d8981 328 #define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
AnnaBridge 156:ff21514d8981 329
AnnaBridge 156:ff21514d8981 330 /** @brief Check whether the specified SPI interrupt source is enabled or not.
AnnaBridge 156:ff21514d8981 331 * @param __HANDLE__: specifies the SPI Handle.
AnnaBridge 156:ff21514d8981 332 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
AnnaBridge 156:ff21514d8981 333 * @param __INTERRUPT__: specifies the SPI interrupt source to check.
AnnaBridge 156:ff21514d8981 334 * This parameter can be one of the following values:
AnnaBridge 156:ff21514d8981 335 * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
AnnaBridge 156:ff21514d8981 336 * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
AnnaBridge 156:ff21514d8981 337 * @arg SPI_IT_ERR: Error interrupt enable
AnnaBridge 156:ff21514d8981 338 * @retval The new state of __IT__ (TRUE or FALSE).
AnnaBridge 156:ff21514d8981 339 */
AnnaBridge 156:ff21514d8981 340 #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
AnnaBridge 156:ff21514d8981 341
AnnaBridge 156:ff21514d8981 342 /** @brief Check whether the specified SPI flag is set or not.
AnnaBridge 156:ff21514d8981 343 * @param __HANDLE__: specifies the SPI Handle.
AnnaBridge 156:ff21514d8981 344 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
AnnaBridge 156:ff21514d8981 345 * @param __FLAG__: specifies the flag to check.
AnnaBridge 156:ff21514d8981 346 * This parameter can be one of the following values:
AnnaBridge 156:ff21514d8981 347 * @arg SPI_FLAG_RXNE: Receive buffer not empty flag
AnnaBridge 156:ff21514d8981 348 * @arg SPI_FLAG_TXE: Transmit buffer empty flag
AnnaBridge 156:ff21514d8981 349 * @arg SPI_FLAG_CRCERR: CRC error flag
AnnaBridge 156:ff21514d8981 350 * @arg SPI_FLAG_MODF: Mode fault flag
AnnaBridge 156:ff21514d8981 351 * @arg SPI_FLAG_OVR: Overrun flag
AnnaBridge 156:ff21514d8981 352 * @arg SPI_FLAG_BSY: Busy flag
AnnaBridge 156:ff21514d8981 353 * @arg SPI_FLAG_FRE: Frame format error flag
AnnaBridge 156:ff21514d8981 354 * @retval The new state of __FLAG__ (TRUE or FALSE).
AnnaBridge 156:ff21514d8981 355 */
AnnaBridge 156:ff21514d8981 356 #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
AnnaBridge 156:ff21514d8981 357
AnnaBridge 156:ff21514d8981 358 /** @brief Clear the SPI CRCERR pending flag.
AnnaBridge 156:ff21514d8981 359 * @param __HANDLE__: specifies the SPI Handle.
AnnaBridge 156:ff21514d8981 360 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
AnnaBridge 156:ff21514d8981 361 * @retval None
AnnaBridge 156:ff21514d8981 362 */
AnnaBridge 156:ff21514d8981 363 #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
AnnaBridge 156:ff21514d8981 364
AnnaBridge 156:ff21514d8981 365 /** @brief Clear the SPI MODF pending flag.
AnnaBridge 156:ff21514d8981 366 * @param __HANDLE__: specifies the SPI Handle.
AnnaBridge 156:ff21514d8981 367 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
AnnaBridge 156:ff21514d8981 368 * @retval None
AnnaBridge 156:ff21514d8981 369 */
AnnaBridge 156:ff21514d8981 370 #define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \
AnnaBridge 156:ff21514d8981 371 do{ \
AnnaBridge 156:ff21514d8981 372 __IO uint32_t tmpreg_modf = 0x00U; \
AnnaBridge 156:ff21514d8981 373 tmpreg_modf = (__HANDLE__)->Instance->SR; \
AnnaBridge 156:ff21514d8981 374 (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \
AnnaBridge 156:ff21514d8981 375 UNUSED(tmpreg_modf); \
AnnaBridge 156:ff21514d8981 376 } while(0U)
AnnaBridge 156:ff21514d8981 377
AnnaBridge 156:ff21514d8981 378 /** @brief Clear the SPI OVR pending flag.
AnnaBridge 156:ff21514d8981 379 * @param __HANDLE__: specifies the SPI Handle.
AnnaBridge 156:ff21514d8981 380 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
AnnaBridge 156:ff21514d8981 381 * @retval None
AnnaBridge 156:ff21514d8981 382 */
AnnaBridge 156:ff21514d8981 383 #define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \
AnnaBridge 156:ff21514d8981 384 do{ \
AnnaBridge 156:ff21514d8981 385 __IO uint32_t tmpreg_ovr = 0x00U; \
AnnaBridge 156:ff21514d8981 386 tmpreg_ovr = (__HANDLE__)->Instance->DR; \
AnnaBridge 156:ff21514d8981 387 tmpreg_ovr = (__HANDLE__)->Instance->SR; \
AnnaBridge 156:ff21514d8981 388 UNUSED(tmpreg_ovr); \
AnnaBridge 156:ff21514d8981 389 } while(0U)
AnnaBridge 156:ff21514d8981 390
AnnaBridge 156:ff21514d8981 391 /** @brief Clear the SPI FRE pending flag.
AnnaBridge 156:ff21514d8981 392 * @param __HANDLE__: specifies the SPI Handle.
AnnaBridge 156:ff21514d8981 393 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
AnnaBridge 156:ff21514d8981 394 * @retval None
AnnaBridge 156:ff21514d8981 395 */
AnnaBridge 156:ff21514d8981 396 #define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \
AnnaBridge 156:ff21514d8981 397 do{ \
AnnaBridge 156:ff21514d8981 398 __IO uint32_t tmpreg_fre = 0x00U; \
AnnaBridge 156:ff21514d8981 399 tmpreg_fre = (__HANDLE__)->Instance->SR; \
AnnaBridge 156:ff21514d8981 400 UNUSED(tmpreg_fre); \
AnnaBridge 156:ff21514d8981 401 }while(0U)
AnnaBridge 156:ff21514d8981 402
AnnaBridge 156:ff21514d8981 403 /** @brief Enable the SPI peripheral.
AnnaBridge 156:ff21514d8981 404 * @param __HANDLE__: specifies the SPI Handle.
AnnaBridge 156:ff21514d8981 405 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
AnnaBridge 156:ff21514d8981 406 * @retval None
AnnaBridge 156:ff21514d8981 407 */
AnnaBridge 156:ff21514d8981 408 #define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE)
AnnaBridge 156:ff21514d8981 409
AnnaBridge 156:ff21514d8981 410 /** @brief Disable the SPI peripheral.
AnnaBridge 156:ff21514d8981 411 * @param __HANDLE__: specifies the SPI Handle.
AnnaBridge 156:ff21514d8981 412 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
AnnaBridge 156:ff21514d8981 413 * @retval None
AnnaBridge 156:ff21514d8981 414 */
AnnaBridge 156:ff21514d8981 415 #define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE))
AnnaBridge 156:ff21514d8981 416 /**
AnnaBridge 156:ff21514d8981 417 * @}
AnnaBridge 156:ff21514d8981 418 */
AnnaBridge 156:ff21514d8981 419
AnnaBridge 156:ff21514d8981 420 /* Exported functions --------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 421 /** @addtogroup SPI_Exported_Functions
AnnaBridge 156:ff21514d8981 422 * @{
AnnaBridge 156:ff21514d8981 423 */
AnnaBridge 156:ff21514d8981 424
AnnaBridge 156:ff21514d8981 425 /** @addtogroup SPI_Exported_Functions_Group1
AnnaBridge 156:ff21514d8981 426 * @{
AnnaBridge 156:ff21514d8981 427 */
AnnaBridge 156:ff21514d8981 428 /* Initialization/de-initialization functions **********************************/
AnnaBridge 156:ff21514d8981 429 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
AnnaBridge 156:ff21514d8981 430 HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi);
AnnaBridge 156:ff21514d8981 431 void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
AnnaBridge 156:ff21514d8981 432 void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
AnnaBridge 156:ff21514d8981 433 /**
AnnaBridge 156:ff21514d8981 434 * @}
AnnaBridge 156:ff21514d8981 435 */
AnnaBridge 156:ff21514d8981 436
AnnaBridge 156:ff21514d8981 437 /** @addtogroup SPI_Exported_Functions_Group2
AnnaBridge 156:ff21514d8981 438 * @{
AnnaBridge 156:ff21514d8981 439 */
AnnaBridge 156:ff21514d8981 440 /* I/O operation functions *****************************************************/
AnnaBridge 156:ff21514d8981 441 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
AnnaBridge 156:ff21514d8981 442 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
AnnaBridge 156:ff21514d8981 443 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
AnnaBridge 156:ff21514d8981 444 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
AnnaBridge 156:ff21514d8981 445 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
AnnaBridge 156:ff21514d8981 446 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
AnnaBridge 156:ff21514d8981 447 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
AnnaBridge 156:ff21514d8981 448 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
AnnaBridge 156:ff21514d8981 449 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
AnnaBridge 156:ff21514d8981 450 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
AnnaBridge 156:ff21514d8981 451 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
AnnaBridge 156:ff21514d8981 452 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
AnnaBridge 156:ff21514d8981 453 /* Transfer Abort functions */
AnnaBridge 156:ff21514d8981 454 HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi);
AnnaBridge 156:ff21514d8981 455 HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi);
AnnaBridge 156:ff21514d8981 456
AnnaBridge 156:ff21514d8981 457 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
AnnaBridge 156:ff21514d8981 458 void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
AnnaBridge 156:ff21514d8981 459 void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
AnnaBridge 156:ff21514d8981 460 void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
AnnaBridge 156:ff21514d8981 461 void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
AnnaBridge 156:ff21514d8981 462 void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
AnnaBridge 156:ff21514d8981 463 void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
AnnaBridge 156:ff21514d8981 464 void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
AnnaBridge 156:ff21514d8981 465 void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);
AnnaBridge 156:ff21514d8981 466 /**
AnnaBridge 156:ff21514d8981 467 * @}
AnnaBridge 156:ff21514d8981 468 */
AnnaBridge 156:ff21514d8981 469
AnnaBridge 156:ff21514d8981 470 /** @addtogroup SPI_Exported_Functions_Group3
AnnaBridge 156:ff21514d8981 471 * @{
AnnaBridge 156:ff21514d8981 472 */
AnnaBridge 156:ff21514d8981 473 /* Peripheral State and Error functions ***************************************/
AnnaBridge 156:ff21514d8981 474 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
AnnaBridge 156:ff21514d8981 475 uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
AnnaBridge 156:ff21514d8981 476 /**
AnnaBridge 156:ff21514d8981 477 * @}
AnnaBridge 156:ff21514d8981 478 */
AnnaBridge 156:ff21514d8981 479
AnnaBridge 156:ff21514d8981 480 /**
AnnaBridge 156:ff21514d8981 481 * @}
AnnaBridge 156:ff21514d8981 482 */
AnnaBridge 156:ff21514d8981 483
AnnaBridge 156:ff21514d8981 484 /* Private types -------------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 485 /* Private variables ---------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 486 /* Private constants ---------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 487
AnnaBridge 156:ff21514d8981 488 /* Private macros ------------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 489 /** @defgroup SPI_Private_Macros SPI Private Macros
AnnaBridge 156:ff21514d8981 490 * @{
AnnaBridge 156:ff21514d8981 491 */
AnnaBridge 156:ff21514d8981 492
AnnaBridge 156:ff21514d8981 493 /** @brief Set the SPI transmit-only mode.
AnnaBridge 156:ff21514d8981 494 * @param __HANDLE__: specifies the SPI Handle.
AnnaBridge 156:ff21514d8981 495 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
AnnaBridge 156:ff21514d8981 496 * @retval None
AnnaBridge 156:ff21514d8981 497 */
AnnaBridge 156:ff21514d8981 498 #define SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)
AnnaBridge 156:ff21514d8981 499
AnnaBridge 156:ff21514d8981 500 /** @brief Set the SPI receive-only mode.
AnnaBridge 156:ff21514d8981 501 * @param __HANDLE__: specifies the SPI Handle.
AnnaBridge 156:ff21514d8981 502 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
AnnaBridge 156:ff21514d8981 503 * @retval None
AnnaBridge 156:ff21514d8981 504 */
AnnaBridge 156:ff21514d8981 505 #define SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE))
AnnaBridge 156:ff21514d8981 506
AnnaBridge 156:ff21514d8981 507 /** @brief Reset the CRC calculation of the SPI.
AnnaBridge 156:ff21514d8981 508 * @param __HANDLE__: specifies the SPI Handle.
AnnaBridge 156:ff21514d8981 509 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
AnnaBridge 156:ff21514d8981 510 * @retval None
AnnaBridge 156:ff21514d8981 511 */
AnnaBridge 156:ff21514d8981 512 #define SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_CRCEN);\
AnnaBridge 156:ff21514d8981 513 (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0U)
AnnaBridge 156:ff21514d8981 514
AnnaBridge 156:ff21514d8981 515 #define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
AnnaBridge 156:ff21514d8981 516 ((MODE) == SPI_MODE_MASTER))
AnnaBridge 156:ff21514d8981 517
AnnaBridge 156:ff21514d8981 518 #define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
AnnaBridge 156:ff21514d8981 519 ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
AnnaBridge 156:ff21514d8981 520 ((MODE) == SPI_DIRECTION_1LINE))
AnnaBridge 156:ff21514d8981 521
AnnaBridge 156:ff21514d8981 522 #define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
AnnaBridge 156:ff21514d8981 523
AnnaBridge 156:ff21514d8981 524 #define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
AnnaBridge 156:ff21514d8981 525 ((MODE) == SPI_DIRECTION_1LINE))
AnnaBridge 156:ff21514d8981 526
AnnaBridge 156:ff21514d8981 527 #define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
AnnaBridge 156:ff21514d8981 528 ((DATASIZE) == SPI_DATASIZE_8BIT))
AnnaBridge 156:ff21514d8981 529
AnnaBridge 156:ff21514d8981 530 #define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
AnnaBridge 156:ff21514d8981 531 ((CPOL) == SPI_POLARITY_HIGH))
AnnaBridge 156:ff21514d8981 532
AnnaBridge 156:ff21514d8981 533 #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
AnnaBridge 156:ff21514d8981 534 ((CPHA) == SPI_PHASE_2EDGE))
AnnaBridge 156:ff21514d8981 535
AnnaBridge 156:ff21514d8981 536 #define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \
AnnaBridge 156:ff21514d8981 537 ((NSS) == SPI_NSS_HARD_INPUT) || \
AnnaBridge 156:ff21514d8981 538 ((NSS) == SPI_NSS_HARD_OUTPUT))
AnnaBridge 156:ff21514d8981 539
AnnaBridge 156:ff21514d8981 540 #define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \
AnnaBridge 156:ff21514d8981 541 ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \
AnnaBridge 156:ff21514d8981 542 ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \
AnnaBridge 156:ff21514d8981 543 ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \
AnnaBridge 156:ff21514d8981 544 ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \
AnnaBridge 156:ff21514d8981 545 ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \
AnnaBridge 156:ff21514d8981 546 ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
AnnaBridge 156:ff21514d8981 547 ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
AnnaBridge 156:ff21514d8981 548
AnnaBridge 156:ff21514d8981 549 #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
AnnaBridge 156:ff21514d8981 550 ((BIT) == SPI_FIRSTBIT_LSB))
AnnaBridge 156:ff21514d8981 551
AnnaBridge 156:ff21514d8981 552 #define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \
AnnaBridge 156:ff21514d8981 553 ((MODE) == SPI_TIMODE_ENABLE))
AnnaBridge 156:ff21514d8981 554
AnnaBridge 156:ff21514d8981 555 #define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \
AnnaBridge 156:ff21514d8981 556 ((CALCULATION) == SPI_CRCCALCULATION_ENABLE))
AnnaBridge 156:ff21514d8981 557
AnnaBridge 156:ff21514d8981 558 #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x01U) && ((POLYNOMIAL) <= 0xFFFFU))
AnnaBridge 156:ff21514d8981 559
AnnaBridge 156:ff21514d8981 560 /**
AnnaBridge 156:ff21514d8981 561 * @}
AnnaBridge 156:ff21514d8981 562 */
AnnaBridge 156:ff21514d8981 563
AnnaBridge 156:ff21514d8981 564 /* Private functions ---------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 565 /** @defgroup SPI_Private_Functions SPI Private Functions
AnnaBridge 156:ff21514d8981 566 * @{
AnnaBridge 156:ff21514d8981 567 */
AnnaBridge 156:ff21514d8981 568
AnnaBridge 156:ff21514d8981 569 /**
AnnaBridge 156:ff21514d8981 570 * @}
AnnaBridge 156:ff21514d8981 571 */
AnnaBridge 156:ff21514d8981 572
AnnaBridge 156:ff21514d8981 573 /**
AnnaBridge 156:ff21514d8981 574 * @}
AnnaBridge 156:ff21514d8981 575 */
AnnaBridge 156:ff21514d8981 576
AnnaBridge 156:ff21514d8981 577 /**
AnnaBridge 156:ff21514d8981 578 * @}
AnnaBridge 156:ff21514d8981 579 */
AnnaBridge 156:ff21514d8981 580
AnnaBridge 156:ff21514d8981 581 #ifdef __cplusplus
AnnaBridge 156:ff21514d8981 582 }
AnnaBridge 156:ff21514d8981 583 #endif
AnnaBridge 156:ff21514d8981 584
AnnaBridge 156:ff21514d8981 585 #endif /* __STM32F4xx_HAL_SPI_H */
AnnaBridge 156:ff21514d8981 586
AnnaBridge 156:ff21514d8981 587 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/