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TARGET_NUCLEO_F031K6/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tim.h@157:e7ca05fa8600, 2017-11-09 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 09 11:14:10 2017 +0000
Revision:
157:e7ca05fa8600
Parent:
156:ff21514d8981
Child:
160:5571c4ff569f
Release 155 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 156:ff21514d8981 1 /**
AnnaBridge 156:ff21514d8981 2 ******************************************************************************
AnnaBridge 156:ff21514d8981 3 * @file stm32f0xx_hal_tim.h
AnnaBridge 156:ff21514d8981 4 * @author MCD Application Team
AnnaBridge 156:ff21514d8981 5 * @version V1.5.0
AnnaBridge 156:ff21514d8981 6 * @date 04-November-2016
AnnaBridge 156:ff21514d8981 7 * @brief Header file of TIM HAL module.
AnnaBridge 156:ff21514d8981 8 ******************************************************************************
AnnaBridge 156:ff21514d8981 9 * @attention
AnnaBridge 156:ff21514d8981 10 *
AnnaBridge 156:ff21514d8981 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge 156:ff21514d8981 12 *
AnnaBridge 156:ff21514d8981 13 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 156:ff21514d8981 14 * are permitted provided that the following conditions are met:
AnnaBridge 156:ff21514d8981 15 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 156:ff21514d8981 16 * this list of conditions and the following disclaimer.
AnnaBridge 156:ff21514d8981 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 156:ff21514d8981 18 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 156:ff21514d8981 19 * and/or other materials provided with the distribution.
AnnaBridge 156:ff21514d8981 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 156:ff21514d8981 21 * may be used to endorse or promote products derived from this software
AnnaBridge 156:ff21514d8981 22 * without specific prior written permission.
AnnaBridge 156:ff21514d8981 23 *
AnnaBridge 156:ff21514d8981 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 156:ff21514d8981 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 156:ff21514d8981 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 156:ff21514d8981 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 156:ff21514d8981 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 156:ff21514d8981 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 156:ff21514d8981 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 156:ff21514d8981 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 156:ff21514d8981 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 156:ff21514d8981 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 156:ff21514d8981 34 *
AnnaBridge 156:ff21514d8981 35 ******************************************************************************
AnnaBridge 156:ff21514d8981 36 */
AnnaBridge 156:ff21514d8981 37
AnnaBridge 156:ff21514d8981 38 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 156:ff21514d8981 39 #ifndef __STM32F0xx_HAL_TIM_H
AnnaBridge 156:ff21514d8981 40 #define __STM32F0xx_HAL_TIM_H
AnnaBridge 156:ff21514d8981 41
AnnaBridge 156:ff21514d8981 42 #ifdef __cplusplus
AnnaBridge 156:ff21514d8981 43 extern "C" {
AnnaBridge 156:ff21514d8981 44 #endif
AnnaBridge 156:ff21514d8981 45
AnnaBridge 156:ff21514d8981 46 /* Includes ------------------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 47 #include "stm32f0xx_hal_def.h"
AnnaBridge 156:ff21514d8981 48
AnnaBridge 156:ff21514d8981 49 /** @addtogroup STM32F0xx_HAL_Driver
AnnaBridge 156:ff21514d8981 50 * @{
AnnaBridge 156:ff21514d8981 51 */
AnnaBridge 156:ff21514d8981 52
AnnaBridge 156:ff21514d8981 53 /** @addtogroup TIM
AnnaBridge 156:ff21514d8981 54 * @{
AnnaBridge 156:ff21514d8981 55 */
AnnaBridge 156:ff21514d8981 56
AnnaBridge 156:ff21514d8981 57 /* Exported types ------------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 58 /** @defgroup TIM_Exported_Types TIM Exported Types
AnnaBridge 156:ff21514d8981 59 * @{
AnnaBridge 156:ff21514d8981 60 */
AnnaBridge 156:ff21514d8981 61 /**
AnnaBridge 156:ff21514d8981 62 * @brief TIM Time base Configuration Structure definition
AnnaBridge 156:ff21514d8981 63 */
AnnaBridge 156:ff21514d8981 64 typedef struct
AnnaBridge 156:ff21514d8981 65 {
AnnaBridge 156:ff21514d8981 66 uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
AnnaBridge 156:ff21514d8981 67 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
AnnaBridge 156:ff21514d8981 68
AnnaBridge 156:ff21514d8981 69 uint32_t CounterMode; /*!< Specifies the counter mode.
AnnaBridge 156:ff21514d8981 70 This parameter can be a value of @ref TIM_Counter_Mode */
AnnaBridge 156:ff21514d8981 71
AnnaBridge 156:ff21514d8981 72 uint32_t Period; /*!< Specifies the period value to be loaded into the active
AnnaBridge 156:ff21514d8981 73 Auto-Reload Register at the next update event.
AnnaBridge 156:ff21514d8981 74 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
AnnaBridge 156:ff21514d8981 75
AnnaBridge 156:ff21514d8981 76 uint32_t ClockDivision; /*!< Specifies the clock division.
AnnaBridge 156:ff21514d8981 77 This parameter can be a value of @ref TIM_ClockDivision */
AnnaBridge 156:ff21514d8981 78
AnnaBridge 156:ff21514d8981 79 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
AnnaBridge 156:ff21514d8981 80 reaches zero, an update event is generated and counting restarts
AnnaBridge 156:ff21514d8981 81 from the RCR value (N).
AnnaBridge 156:ff21514d8981 82 This means in PWM mode that (N+1) corresponds to:
AnnaBridge 156:ff21514d8981 83 - the number of PWM periods in edge-aligned mode
AnnaBridge 156:ff21514d8981 84 - the number of half PWM period in center-aligned mode
AnnaBridge 156:ff21514d8981 85 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
AnnaBridge 156:ff21514d8981 86 @note This parameter is valid only for TIM1 and TIM8. */
AnnaBridge 156:ff21514d8981 87
AnnaBridge 156:ff21514d8981 88 uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload.
AnnaBridge 156:ff21514d8981 89 This parameter can be a value of @ref TIM_AutoReloadPreload */
AnnaBridge 156:ff21514d8981 90 } TIM_Base_InitTypeDef;
AnnaBridge 156:ff21514d8981 91
AnnaBridge 156:ff21514d8981 92 /**
AnnaBridge 156:ff21514d8981 93 * @brief TIM Output Compare Configuration Structure definition
AnnaBridge 156:ff21514d8981 94 */
AnnaBridge 156:ff21514d8981 95 typedef struct
AnnaBridge 156:ff21514d8981 96 {
AnnaBridge 156:ff21514d8981 97 uint32_t OCMode; /*!< Specifies the TIM mode.
AnnaBridge 156:ff21514d8981 98 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
AnnaBridge 156:ff21514d8981 99
AnnaBridge 156:ff21514d8981 100 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
AnnaBridge 156:ff21514d8981 101 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
AnnaBridge 156:ff21514d8981 102
AnnaBridge 156:ff21514d8981 103 uint32_t OCPolarity; /*!< Specifies the output polarity.
AnnaBridge 156:ff21514d8981 104 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
AnnaBridge 156:ff21514d8981 105
AnnaBridge 156:ff21514d8981 106 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
AnnaBridge 156:ff21514d8981 107 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
AnnaBridge 156:ff21514d8981 108 @note This parameter is valid only for TIM1 and TIM8. */
AnnaBridge 156:ff21514d8981 109
AnnaBridge 156:ff21514d8981 110 uint32_t OCFastMode; /*!< Specifies the Fast mode state.
AnnaBridge 156:ff21514d8981 111 This parameter can be a value of @ref TIM_Output_Fast_State
AnnaBridge 156:ff21514d8981 112 @note This parameter is valid only in PWM1 and PWM2 mode. */
AnnaBridge 156:ff21514d8981 113
AnnaBridge 156:ff21514d8981 114
AnnaBridge 156:ff21514d8981 115 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
AnnaBridge 156:ff21514d8981 116 This parameter can be a value of @ref TIM_Output_Compare_Idle_State
AnnaBridge 156:ff21514d8981 117 @note This parameter is valid only for TIM1 and TIM8. */
AnnaBridge 156:ff21514d8981 118
AnnaBridge 156:ff21514d8981 119 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
AnnaBridge 156:ff21514d8981 120 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
AnnaBridge 156:ff21514d8981 121 @note This parameter is valid only for TIM1 and TIM8. */
AnnaBridge 156:ff21514d8981 122 } TIM_OC_InitTypeDef;
AnnaBridge 156:ff21514d8981 123
AnnaBridge 156:ff21514d8981 124 /**
AnnaBridge 156:ff21514d8981 125 * @brief TIM One Pulse Mode Configuration Structure definition
AnnaBridge 156:ff21514d8981 126 */
AnnaBridge 156:ff21514d8981 127 typedef struct
AnnaBridge 156:ff21514d8981 128 {
AnnaBridge 156:ff21514d8981 129 uint32_t OCMode; /*!< Specifies the TIM mode.
AnnaBridge 156:ff21514d8981 130 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
AnnaBridge 156:ff21514d8981 131
AnnaBridge 156:ff21514d8981 132 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
AnnaBridge 156:ff21514d8981 133 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
AnnaBridge 156:ff21514d8981 134
AnnaBridge 156:ff21514d8981 135 uint32_t OCPolarity; /*!< Specifies the output polarity.
AnnaBridge 156:ff21514d8981 136 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
AnnaBridge 156:ff21514d8981 137
AnnaBridge 156:ff21514d8981 138 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
AnnaBridge 156:ff21514d8981 139 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
AnnaBridge 156:ff21514d8981 140 @note This parameter is valid only for TIM1 and TIM8. */
AnnaBridge 156:ff21514d8981 141
AnnaBridge 156:ff21514d8981 142 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
AnnaBridge 156:ff21514d8981 143 This parameter can be a value of @ref TIM_Output_Compare_Idle_State
AnnaBridge 156:ff21514d8981 144 @note This parameter is valid only for TIM1 and TIM8. */
AnnaBridge 156:ff21514d8981 145
AnnaBridge 156:ff21514d8981 146 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
AnnaBridge 156:ff21514d8981 147 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
AnnaBridge 156:ff21514d8981 148 @note This parameter is valid only for TIM1 and TIM8. */
AnnaBridge 156:ff21514d8981 149
AnnaBridge 156:ff21514d8981 150 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
AnnaBridge 156:ff21514d8981 151 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
AnnaBridge 156:ff21514d8981 152
AnnaBridge 156:ff21514d8981 153 uint32_t ICSelection; /*!< Specifies the input.
AnnaBridge 156:ff21514d8981 154 This parameter can be a value of @ref TIM_Input_Capture_Selection */
AnnaBridge 156:ff21514d8981 155
AnnaBridge 156:ff21514d8981 156 uint32_t ICFilter; /*!< Specifies the input capture filter.
AnnaBridge 156:ff21514d8981 157 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
AnnaBridge 156:ff21514d8981 158 } TIM_OnePulse_InitTypeDef;
AnnaBridge 156:ff21514d8981 159
AnnaBridge 156:ff21514d8981 160
AnnaBridge 156:ff21514d8981 161 /**
AnnaBridge 156:ff21514d8981 162 * @brief TIM Input Capture Configuration Structure definition
AnnaBridge 156:ff21514d8981 163 */
AnnaBridge 156:ff21514d8981 164 typedef struct
AnnaBridge 156:ff21514d8981 165 {
AnnaBridge 156:ff21514d8981 166 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
AnnaBridge 156:ff21514d8981 167 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
AnnaBridge 156:ff21514d8981 168
AnnaBridge 156:ff21514d8981 169 uint32_t ICSelection; /*!< Specifies the input.
AnnaBridge 156:ff21514d8981 170 This parameter can be a value of @ref TIM_Input_Capture_Selection */
AnnaBridge 156:ff21514d8981 171
AnnaBridge 156:ff21514d8981 172 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
AnnaBridge 156:ff21514d8981 173 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
AnnaBridge 156:ff21514d8981 174
AnnaBridge 156:ff21514d8981 175 uint32_t ICFilter; /*!< Specifies the input capture filter.
AnnaBridge 156:ff21514d8981 176 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
AnnaBridge 156:ff21514d8981 177 } TIM_IC_InitTypeDef;
AnnaBridge 156:ff21514d8981 178
AnnaBridge 156:ff21514d8981 179 /**
AnnaBridge 156:ff21514d8981 180 * @brief TIM Encoder Configuration Structure definition
AnnaBridge 156:ff21514d8981 181 */
AnnaBridge 156:ff21514d8981 182 typedef struct
AnnaBridge 156:ff21514d8981 183 {
AnnaBridge 156:ff21514d8981 184 uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
AnnaBridge 156:ff21514d8981 185 This parameter can be a value of @ref TIM_Encoder_Mode */
AnnaBridge 156:ff21514d8981 186
AnnaBridge 156:ff21514d8981 187 uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
AnnaBridge 156:ff21514d8981 188 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
AnnaBridge 156:ff21514d8981 189
AnnaBridge 156:ff21514d8981 190 uint32_t IC1Selection; /*!< Specifies the input.
AnnaBridge 156:ff21514d8981 191 This parameter can be a value of @ref TIM_Input_Capture_Selection */
AnnaBridge 156:ff21514d8981 192
AnnaBridge 156:ff21514d8981 193 uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
AnnaBridge 156:ff21514d8981 194 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
AnnaBridge 156:ff21514d8981 195
AnnaBridge 156:ff21514d8981 196 uint32_t IC1Filter; /*!< Specifies the input capture filter.
AnnaBridge 156:ff21514d8981 197 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
AnnaBridge 156:ff21514d8981 198
AnnaBridge 156:ff21514d8981 199 uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
AnnaBridge 156:ff21514d8981 200 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
AnnaBridge 156:ff21514d8981 201
AnnaBridge 156:ff21514d8981 202 uint32_t IC2Selection; /*!< Specifies the input.
AnnaBridge 156:ff21514d8981 203 This parameter can be a value of @ref TIM_Input_Capture_Selection */
AnnaBridge 156:ff21514d8981 204
AnnaBridge 156:ff21514d8981 205 uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
AnnaBridge 156:ff21514d8981 206 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
AnnaBridge 156:ff21514d8981 207
AnnaBridge 156:ff21514d8981 208 uint32_t IC2Filter; /*!< Specifies the input capture filter.
AnnaBridge 156:ff21514d8981 209 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
AnnaBridge 156:ff21514d8981 210 } TIM_Encoder_InitTypeDef;
AnnaBridge 156:ff21514d8981 211
AnnaBridge 156:ff21514d8981 212
AnnaBridge 156:ff21514d8981 213 /**
AnnaBridge 156:ff21514d8981 214 * @brief TIM Clock Configuration Handle Structure definition
AnnaBridge 156:ff21514d8981 215 */
AnnaBridge 156:ff21514d8981 216 typedef struct
AnnaBridge 156:ff21514d8981 217 {
AnnaBridge 156:ff21514d8981 218 uint32_t ClockSource; /*!< TIM clock sources
AnnaBridge 156:ff21514d8981 219 This parameter can be a value of @ref TIM_Clock_Source */
AnnaBridge 156:ff21514d8981 220 uint32_t ClockPolarity; /*!< TIM clock polarity
AnnaBridge 156:ff21514d8981 221 This parameter can be a value of @ref TIM_Clock_Polarity */
AnnaBridge 156:ff21514d8981 222 uint32_t ClockPrescaler; /*!< TIM clock prescaler
AnnaBridge 156:ff21514d8981 223 This parameter can be a value of @ref TIM_Clock_Prescaler */
AnnaBridge 156:ff21514d8981 224 uint32_t ClockFilter; /*!< TIM clock filter
AnnaBridge 156:ff21514d8981 225 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
AnnaBridge 156:ff21514d8981 226 }TIM_ClockConfigTypeDef;
AnnaBridge 156:ff21514d8981 227
AnnaBridge 156:ff21514d8981 228 /**
AnnaBridge 156:ff21514d8981 229 * @brief TIM Clear Input Configuration Handle Structure definition
AnnaBridge 156:ff21514d8981 230 */
AnnaBridge 156:ff21514d8981 231 typedef struct
AnnaBridge 156:ff21514d8981 232 {
AnnaBridge 156:ff21514d8981 233 uint32_t ClearInputState; /*!< TIM clear Input state
AnnaBridge 156:ff21514d8981 234 This parameter can be ENABLE or DISABLE */
AnnaBridge 156:ff21514d8981 235 uint32_t ClearInputSource; /*!< TIM clear Input sources
AnnaBridge 156:ff21514d8981 236 This parameter can be a value of @ref TIMEx_Clock_Clear_Input_Source */
AnnaBridge 156:ff21514d8981 237 uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
AnnaBridge 156:ff21514d8981 238 This parameter can be a value of @ref TIM_ClearInput_Polarity */
AnnaBridge 156:ff21514d8981 239 uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
AnnaBridge 156:ff21514d8981 240 This parameter can be a value of @ref TIM_ClearInput_Prescaler */
AnnaBridge 156:ff21514d8981 241 uint32_t ClearInputFilter; /*!< TIM Clear Input filter
AnnaBridge 156:ff21514d8981 242 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
AnnaBridge 156:ff21514d8981 243 }TIM_ClearInputConfigTypeDef;
AnnaBridge 156:ff21514d8981 244
AnnaBridge 156:ff21514d8981 245 /**
AnnaBridge 156:ff21514d8981 246 * @brief TIM Slave configuration Structure definition
AnnaBridge 156:ff21514d8981 247 */
AnnaBridge 156:ff21514d8981 248 typedef struct {
AnnaBridge 156:ff21514d8981 249 uint32_t SlaveMode; /*!< Slave mode selection
AnnaBridge 156:ff21514d8981 250 This parameter can be a value of @ref TIM_Slave_Mode */
AnnaBridge 156:ff21514d8981 251 uint32_t InputTrigger; /*!< Input Trigger source
AnnaBridge 156:ff21514d8981 252 This parameter can be a value of @ref TIM_Trigger_Selection */
AnnaBridge 156:ff21514d8981 253 uint32_t TriggerPolarity; /*!< Input Trigger polarity
AnnaBridge 156:ff21514d8981 254 This parameter can be a value of @ref TIM_Trigger_Polarity */
AnnaBridge 156:ff21514d8981 255 uint32_t TriggerPrescaler; /*!< Input trigger prescaler
AnnaBridge 156:ff21514d8981 256 This parameter can be a value of @ref TIM_Trigger_Prescaler */
AnnaBridge 156:ff21514d8981 257 uint32_t TriggerFilter; /*!< Input trigger filter
AnnaBridge 156:ff21514d8981 258 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
AnnaBridge 156:ff21514d8981 259
AnnaBridge 156:ff21514d8981 260 }TIM_SlaveConfigTypeDef;
AnnaBridge 156:ff21514d8981 261
AnnaBridge 156:ff21514d8981 262 /**
AnnaBridge 156:ff21514d8981 263 * @brief HAL State structures definition
AnnaBridge 156:ff21514d8981 264 */
AnnaBridge 156:ff21514d8981 265 typedef enum
AnnaBridge 156:ff21514d8981 266 {
AnnaBridge 156:ff21514d8981 267 HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */
AnnaBridge 156:ff21514d8981 268 HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
AnnaBridge 156:ff21514d8981 269 HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
AnnaBridge 156:ff21514d8981 270 HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
AnnaBridge 156:ff21514d8981 271 HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
AnnaBridge 156:ff21514d8981 272 }HAL_TIM_StateTypeDef;
AnnaBridge 156:ff21514d8981 273
AnnaBridge 156:ff21514d8981 274 /**
AnnaBridge 156:ff21514d8981 275 * @brief HAL Active channel structures definition
AnnaBridge 156:ff21514d8981 276 */
AnnaBridge 156:ff21514d8981 277 typedef enum
AnnaBridge 156:ff21514d8981 278 {
AnnaBridge 156:ff21514d8981 279 HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */
AnnaBridge 156:ff21514d8981 280 HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */
AnnaBridge 156:ff21514d8981 281 HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */
AnnaBridge 156:ff21514d8981 282 HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */
AnnaBridge 156:ff21514d8981 283 HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */
AnnaBridge 156:ff21514d8981 284 }HAL_TIM_ActiveChannel;
AnnaBridge 156:ff21514d8981 285
AnnaBridge 156:ff21514d8981 286 /**
AnnaBridge 156:ff21514d8981 287 * @brief TIM Time Base Handle Structure definition
AnnaBridge 156:ff21514d8981 288 */
AnnaBridge 156:ff21514d8981 289 typedef struct
AnnaBridge 156:ff21514d8981 290 {
AnnaBridge 156:ff21514d8981 291 TIM_TypeDef *Instance; /*!< Register base address */
AnnaBridge 156:ff21514d8981 292 TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
AnnaBridge 156:ff21514d8981 293 HAL_TIM_ActiveChannel Channel; /*!< Active channel */
AnnaBridge 156:ff21514d8981 294 DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
AnnaBridge 156:ff21514d8981 295 This array is accessed by a @ref TIM_DMA_Handle_index */
AnnaBridge 156:ff21514d8981 296 HAL_LockTypeDef Lock; /*!< Locking object */
AnnaBridge 156:ff21514d8981 297 __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
AnnaBridge 156:ff21514d8981 298 }TIM_HandleTypeDef;
AnnaBridge 156:ff21514d8981 299
AnnaBridge 156:ff21514d8981 300 /**
AnnaBridge 156:ff21514d8981 301 * @}
AnnaBridge 156:ff21514d8981 302 */
AnnaBridge 156:ff21514d8981 303
AnnaBridge 156:ff21514d8981 304 /* Exported constants --------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 305 /** @defgroup TIM_Exported_Constants TIM Exported Constants
AnnaBridge 156:ff21514d8981 306 * @{
AnnaBridge 156:ff21514d8981 307 */
AnnaBridge 156:ff21514d8981 308
AnnaBridge 156:ff21514d8981 309 /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity
AnnaBridge 156:ff21514d8981 310 * @{
AnnaBridge 156:ff21514d8981 311 */
AnnaBridge 156:ff21514d8981 312 #define TIM_INPUTCHANNELPOLARITY_RISING (0x00000000U) /*!< Polarity for TIx source */
AnnaBridge 156:ff21514d8981 313 #define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */
AnnaBridge 156:ff21514d8981 314 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */
AnnaBridge 156:ff21514d8981 315 /**
AnnaBridge 156:ff21514d8981 316 * @}
AnnaBridge 156:ff21514d8981 317 */
AnnaBridge 156:ff21514d8981 318
AnnaBridge 156:ff21514d8981 319 /** @defgroup TIM_ETR_Polarity TIM ETR Polarity
AnnaBridge 156:ff21514d8981 320 * @{
AnnaBridge 156:ff21514d8981 321 */
AnnaBridge 156:ff21514d8981 322 #define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */
AnnaBridge 156:ff21514d8981 323 #define TIM_ETRPOLARITY_NONINVERTED (0x0000U) /*!< Polarity for ETR source */
AnnaBridge 156:ff21514d8981 324 /**
AnnaBridge 156:ff21514d8981 325 * @}
AnnaBridge 156:ff21514d8981 326 */
AnnaBridge 156:ff21514d8981 327
AnnaBridge 156:ff21514d8981 328 /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
AnnaBridge 156:ff21514d8981 329 * @{
AnnaBridge 156:ff21514d8981 330 */
AnnaBridge 156:ff21514d8981 331 #define TIM_ETRPRESCALER_DIV1 (0x0000U) /*!< No prescaler is used */
AnnaBridge 156:ff21514d8981 332 #define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */
AnnaBridge 156:ff21514d8981 333 #define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */
AnnaBridge 156:ff21514d8981 334 #define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */
AnnaBridge 156:ff21514d8981 335 /**
AnnaBridge 156:ff21514d8981 336 * @}
AnnaBridge 156:ff21514d8981 337 */
AnnaBridge 156:ff21514d8981 338
AnnaBridge 156:ff21514d8981 339 /** @defgroup TIM_Counter_Mode TIM Counter Mode
AnnaBridge 156:ff21514d8981 340 * @{
AnnaBridge 156:ff21514d8981 341 */
AnnaBridge 156:ff21514d8981 342 #define TIM_COUNTERMODE_UP (0x0000U)
AnnaBridge 156:ff21514d8981 343 #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
AnnaBridge 156:ff21514d8981 344 #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
AnnaBridge 156:ff21514d8981 345 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
AnnaBridge 156:ff21514d8981 346 #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
AnnaBridge 156:ff21514d8981 347 /**
AnnaBridge 156:ff21514d8981 348 * @}
AnnaBridge 156:ff21514d8981 349 */
AnnaBridge 156:ff21514d8981 350
AnnaBridge 156:ff21514d8981 351 /** @defgroup TIM_ClockDivision TIM Clock Division
AnnaBridge 156:ff21514d8981 352 * @{
AnnaBridge 156:ff21514d8981 353 */
AnnaBridge 156:ff21514d8981 354 #define TIM_CLOCKDIVISION_DIV1 (0x0000U)
AnnaBridge 156:ff21514d8981 355 #define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
AnnaBridge 156:ff21514d8981 356 #define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
AnnaBridge 156:ff21514d8981 357 /**
AnnaBridge 156:ff21514d8981 358 * @}
AnnaBridge 156:ff21514d8981 359 */
AnnaBridge 156:ff21514d8981 360
AnnaBridge 156:ff21514d8981 361 /** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
AnnaBridge 156:ff21514d8981 362 * @{
AnnaBridge 156:ff21514d8981 363 */
AnnaBridge 156:ff21514d8981 364 #define TIM_AUTORELOAD_PRELOAD_DISABLE (0x0000U) /*!< TIMx_ARR register is not buffered */
AnnaBridge 156:ff21514d8981 365 #define TIM_AUTORELOAD_PRELOAD_ENABLE (TIM_CR1_ARPE) /*!< TIMx_ARR register is buffered */
AnnaBridge 156:ff21514d8981 366 /**
AnnaBridge 156:ff21514d8981 367 * @}
AnnaBridge 156:ff21514d8981 368 */
AnnaBridge 156:ff21514d8981 369
AnnaBridge 156:ff21514d8981 370 /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM modes
AnnaBridge 156:ff21514d8981 371 * @{
AnnaBridge 156:ff21514d8981 372 */
AnnaBridge 156:ff21514d8981 373 #define TIM_OCMODE_TIMING (0x0000U)
AnnaBridge 156:ff21514d8981 374 #define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)
AnnaBridge 156:ff21514d8981 375 #define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)
AnnaBridge 156:ff21514d8981 376 #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1)
AnnaBridge 156:ff21514d8981 377 #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
AnnaBridge 156:ff21514d8981 378 #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)
AnnaBridge 156:ff21514d8981 379 #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
AnnaBridge 156:ff21514d8981 380 #define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)
AnnaBridge 156:ff21514d8981 381 /**
AnnaBridge 156:ff21514d8981 382 * @}
AnnaBridge 156:ff21514d8981 383 */
AnnaBridge 156:ff21514d8981 384
AnnaBridge 156:ff21514d8981 385 /** @defgroup TIM_Output_Fast_State TIM Output Fast State
AnnaBridge 156:ff21514d8981 386 * @{
AnnaBridge 156:ff21514d8981 387 */
AnnaBridge 156:ff21514d8981 388 #define TIM_OCFAST_DISABLE (0x0000U)
AnnaBridge 156:ff21514d8981 389 #define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
AnnaBridge 156:ff21514d8981 390 /**
AnnaBridge 156:ff21514d8981 391 * @}
AnnaBridge 156:ff21514d8981 392 */
AnnaBridge 156:ff21514d8981 393
AnnaBridge 156:ff21514d8981 394 /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
AnnaBridge 156:ff21514d8981 395 * @{
AnnaBridge 156:ff21514d8981 396 */
AnnaBridge 156:ff21514d8981 397 #define TIM_OCPOLARITY_HIGH (0x0000U)
AnnaBridge 156:ff21514d8981 398 #define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
AnnaBridge 156:ff21514d8981 399 /**
AnnaBridge 156:ff21514d8981 400 * @}
AnnaBridge 156:ff21514d8981 401 */
AnnaBridge 156:ff21514d8981 402
AnnaBridge 156:ff21514d8981 403 /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
AnnaBridge 156:ff21514d8981 404 * @{
AnnaBridge 156:ff21514d8981 405 */
AnnaBridge 156:ff21514d8981 406 #define TIM_OCNPOLARITY_HIGH (0x0000U)
AnnaBridge 156:ff21514d8981 407 #define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
AnnaBridge 156:ff21514d8981 408 /**
AnnaBridge 156:ff21514d8981 409 * @}
AnnaBridge 156:ff21514d8981 410 */
AnnaBridge 156:ff21514d8981 411
AnnaBridge 156:ff21514d8981 412 /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
AnnaBridge 156:ff21514d8981 413 * @{
AnnaBridge 156:ff21514d8981 414 */
AnnaBridge 156:ff21514d8981 415 #define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
AnnaBridge 156:ff21514d8981 416 #define TIM_OCIDLESTATE_RESET (0x0000U)
AnnaBridge 156:ff21514d8981 417 /**
AnnaBridge 156:ff21514d8981 418 * @}
AnnaBridge 156:ff21514d8981 419 */
AnnaBridge 156:ff21514d8981 420
AnnaBridge 156:ff21514d8981 421 /** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
AnnaBridge 156:ff21514d8981 422 * @{
AnnaBridge 156:ff21514d8981 423 */
AnnaBridge 156:ff21514d8981 424 #define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
AnnaBridge 156:ff21514d8981 425 #define TIM_OCNIDLESTATE_RESET (0x0000U)
AnnaBridge 156:ff21514d8981 426 /**
AnnaBridge 156:ff21514d8981 427 * @}
AnnaBridge 156:ff21514d8981 428 */
AnnaBridge 156:ff21514d8981 429
AnnaBridge 156:ff21514d8981 430 /** @defgroup TIM_Channel TIM Channel
AnnaBridge 156:ff21514d8981 431 * @{
AnnaBridge 156:ff21514d8981 432 */
AnnaBridge 156:ff21514d8981 433 #define TIM_CHANNEL_1 (0x0000U)
AnnaBridge 156:ff21514d8981 434 #define TIM_CHANNEL_2 (0x0004U)
AnnaBridge 156:ff21514d8981 435 #define TIM_CHANNEL_3 (0x0008U)
AnnaBridge 156:ff21514d8981 436 #define TIM_CHANNEL_4 (0x000CU)
AnnaBridge 156:ff21514d8981 437 #define TIM_CHANNEL_ALL (0x0018U)
AnnaBridge 156:ff21514d8981 438 /**
AnnaBridge 156:ff21514d8981 439 * @}
AnnaBridge 156:ff21514d8981 440 */
AnnaBridge 156:ff21514d8981 441
AnnaBridge 156:ff21514d8981 442 /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
AnnaBridge 156:ff21514d8981 443 * @{
AnnaBridge 156:ff21514d8981 444 */
AnnaBridge 156:ff21514d8981 445 #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
AnnaBridge 156:ff21514d8981 446 #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
AnnaBridge 156:ff21514d8981 447 #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
AnnaBridge 156:ff21514d8981 448 /**
AnnaBridge 156:ff21514d8981 449 * @}
AnnaBridge 156:ff21514d8981 450 */
AnnaBridge 156:ff21514d8981 451
AnnaBridge 156:ff21514d8981 452 /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
AnnaBridge 156:ff21514d8981 453 * @{
AnnaBridge 156:ff21514d8981 454 */
AnnaBridge 156:ff21514d8981 455 #define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
AnnaBridge 156:ff21514d8981 456 connected to IC1, IC2, IC3 or IC4, respectively */
AnnaBridge 156:ff21514d8981 457 #define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
AnnaBridge 156:ff21514d8981 458 connected to IC2, IC1, IC4 or IC3, respectively */
AnnaBridge 156:ff21514d8981 459 #define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
AnnaBridge 156:ff21514d8981 460 /**
AnnaBridge 156:ff21514d8981 461 * @}
AnnaBridge 156:ff21514d8981 462 */
AnnaBridge 156:ff21514d8981 463
AnnaBridge 156:ff21514d8981 464 /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
AnnaBridge 156:ff21514d8981 465 * @{
AnnaBridge 156:ff21514d8981 466 */
AnnaBridge 156:ff21514d8981 467 #define TIM_ICPSC_DIV1 (0x0000U) /*!< Capture performed each time an edge is detected on the capture input */
AnnaBridge 156:ff21514d8981 468 #define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */
AnnaBridge 156:ff21514d8981 469 #define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */
AnnaBridge 156:ff21514d8981 470 #define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */
AnnaBridge 156:ff21514d8981 471 /**
AnnaBridge 156:ff21514d8981 472 * @}
AnnaBridge 156:ff21514d8981 473 */
AnnaBridge 156:ff21514d8981 474
AnnaBridge 156:ff21514d8981 475 /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
AnnaBridge 156:ff21514d8981 476 * @{
AnnaBridge 156:ff21514d8981 477 */
AnnaBridge 156:ff21514d8981 478 #define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
AnnaBridge 156:ff21514d8981 479 #define TIM_OPMODE_REPETITIVE (0x0000U)
AnnaBridge 156:ff21514d8981 480 /**
AnnaBridge 156:ff21514d8981 481 * @}
AnnaBridge 156:ff21514d8981 482 */
AnnaBridge 156:ff21514d8981 483
AnnaBridge 156:ff21514d8981 484 /** @defgroup TIM_Encoder_Mode TIM Encoder Mode
AnnaBridge 156:ff21514d8981 485 * @{
AnnaBridge 156:ff21514d8981 486 */
AnnaBridge 156:ff21514d8981 487 #define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
AnnaBridge 156:ff21514d8981 488 #define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
AnnaBridge 156:ff21514d8981 489 #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
AnnaBridge 156:ff21514d8981 490 /**
AnnaBridge 156:ff21514d8981 491 * @}
AnnaBridge 156:ff21514d8981 492 */
AnnaBridge 156:ff21514d8981 493
AnnaBridge 156:ff21514d8981 494 /** @defgroup TIM_Interrupt_definition TIM Interrupt Definition
AnnaBridge 156:ff21514d8981 495 * @{
AnnaBridge 156:ff21514d8981 496 */
AnnaBridge 156:ff21514d8981 497 #define TIM_IT_UPDATE (TIM_DIER_UIE)
AnnaBridge 156:ff21514d8981 498 #define TIM_IT_CC1 (TIM_DIER_CC1IE)
AnnaBridge 156:ff21514d8981 499 #define TIM_IT_CC2 (TIM_DIER_CC2IE)
AnnaBridge 156:ff21514d8981 500 #define TIM_IT_CC3 (TIM_DIER_CC3IE)
AnnaBridge 156:ff21514d8981 501 #define TIM_IT_CC4 (TIM_DIER_CC4IE)
AnnaBridge 156:ff21514d8981 502 #define TIM_IT_COM (TIM_DIER_COMIE)
AnnaBridge 156:ff21514d8981 503 #define TIM_IT_TRIGGER (TIM_DIER_TIE)
AnnaBridge 156:ff21514d8981 504 #define TIM_IT_BREAK (TIM_DIER_BIE)
AnnaBridge 156:ff21514d8981 505 /**
AnnaBridge 156:ff21514d8981 506 * @}
AnnaBridge 156:ff21514d8981 507 */
AnnaBridge 156:ff21514d8981 508
AnnaBridge 156:ff21514d8981 509 /** @defgroup TIM_Commutation_Source TIM Commutation Source
AnnaBridge 156:ff21514d8981 510 * @{
AnnaBridge 156:ff21514d8981 511 */
AnnaBridge 156:ff21514d8981 512 #define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
AnnaBridge 156:ff21514d8981 513 #define TIM_COMMUTATION_SOFTWARE (0x0000U)
AnnaBridge 156:ff21514d8981 514
AnnaBridge 156:ff21514d8981 515 /**
AnnaBridge 156:ff21514d8981 516 * @}
AnnaBridge 156:ff21514d8981 517 */
AnnaBridge 156:ff21514d8981 518
AnnaBridge 156:ff21514d8981 519 /** @defgroup TIM_DMA_sources TIM DMA Sources
AnnaBridge 156:ff21514d8981 520 * @{
AnnaBridge 156:ff21514d8981 521 */
AnnaBridge 156:ff21514d8981 522 #define TIM_DMA_UPDATE (TIM_DIER_UDE)
AnnaBridge 156:ff21514d8981 523 #define TIM_DMA_CC1 (TIM_DIER_CC1DE)
AnnaBridge 156:ff21514d8981 524 #define TIM_DMA_CC2 (TIM_DIER_CC2DE)
AnnaBridge 156:ff21514d8981 525 #define TIM_DMA_CC3 (TIM_DIER_CC3DE)
AnnaBridge 156:ff21514d8981 526 #define TIM_DMA_CC4 (TIM_DIER_CC4DE)
AnnaBridge 156:ff21514d8981 527 #define TIM_DMA_COM (TIM_DIER_COMDE)
AnnaBridge 156:ff21514d8981 528 #define TIM_DMA_TRIGGER (TIM_DIER_TDE)
AnnaBridge 156:ff21514d8981 529 /**
AnnaBridge 156:ff21514d8981 530 * @}
AnnaBridge 156:ff21514d8981 531 */
AnnaBridge 156:ff21514d8981 532
AnnaBridge 156:ff21514d8981 533 /** @defgroup TIM_Event_Source TIM Event Source
AnnaBridge 156:ff21514d8981 534 * @{
AnnaBridge 156:ff21514d8981 535 */
AnnaBridge 156:ff21514d8981 536 #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
AnnaBridge 156:ff21514d8981 537 #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
AnnaBridge 156:ff21514d8981 538 #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
AnnaBridge 156:ff21514d8981 539 #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
AnnaBridge 156:ff21514d8981 540 #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
AnnaBridge 156:ff21514d8981 541 #define TIM_EVENTSOURCE_COM TIM_EGR_COMG
AnnaBridge 156:ff21514d8981 542 #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
AnnaBridge 156:ff21514d8981 543 #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG
AnnaBridge 156:ff21514d8981 544 /**
AnnaBridge 156:ff21514d8981 545 * @}
AnnaBridge 156:ff21514d8981 546 */
AnnaBridge 156:ff21514d8981 547
AnnaBridge 156:ff21514d8981 548 /** @defgroup TIM_Flag_definition TIM Flag Definition
AnnaBridge 156:ff21514d8981 549 * @{
AnnaBridge 156:ff21514d8981 550 */
AnnaBridge 156:ff21514d8981 551 #define TIM_FLAG_UPDATE (TIM_SR_UIF)
AnnaBridge 156:ff21514d8981 552 #define TIM_FLAG_CC1 (TIM_SR_CC1IF)
AnnaBridge 156:ff21514d8981 553 #define TIM_FLAG_CC2 (TIM_SR_CC2IF)
AnnaBridge 156:ff21514d8981 554 #define TIM_FLAG_CC3 (TIM_SR_CC3IF)
AnnaBridge 156:ff21514d8981 555 #define TIM_FLAG_CC4 (TIM_SR_CC4IF)
AnnaBridge 156:ff21514d8981 556 #define TIM_FLAG_COM (TIM_SR_COMIF)
AnnaBridge 156:ff21514d8981 557 #define TIM_FLAG_TRIGGER (TIM_SR_TIF)
AnnaBridge 156:ff21514d8981 558 #define TIM_FLAG_BREAK (TIM_SR_BIF)
AnnaBridge 156:ff21514d8981 559 #define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
AnnaBridge 156:ff21514d8981 560 #define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
AnnaBridge 156:ff21514d8981 561 #define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
AnnaBridge 156:ff21514d8981 562 #define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
AnnaBridge 156:ff21514d8981 563 /**
AnnaBridge 156:ff21514d8981 564 * @}
AnnaBridge 156:ff21514d8981 565 */
AnnaBridge 156:ff21514d8981 566
AnnaBridge 156:ff21514d8981 567 /** @defgroup TIM_Clock_Source TIM Clock Source
AnnaBridge 156:ff21514d8981 568 * @{
AnnaBridge 156:ff21514d8981 569 */
AnnaBridge 156:ff21514d8981 570 #define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
AnnaBridge 156:ff21514d8981 571 #define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
AnnaBridge 156:ff21514d8981 572 #define TIM_CLOCKSOURCE_ITR0 (0x0000U)
AnnaBridge 156:ff21514d8981 573 #define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
AnnaBridge 156:ff21514d8981 574 #define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
AnnaBridge 156:ff21514d8981 575 #define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
AnnaBridge 156:ff21514d8981 576 #define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
AnnaBridge 156:ff21514d8981 577 #define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
AnnaBridge 156:ff21514d8981 578 #define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
AnnaBridge 156:ff21514d8981 579 #define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
AnnaBridge 156:ff21514d8981 580 /**
AnnaBridge 156:ff21514d8981 581 * @}
AnnaBridge 156:ff21514d8981 582 */
AnnaBridge 156:ff21514d8981 583
AnnaBridge 156:ff21514d8981 584 /** @defgroup TIM_Clock_Polarity TIM Clock Polarity
AnnaBridge 156:ff21514d8981 585 * @{
AnnaBridge 156:ff21514d8981 586 */
AnnaBridge 156:ff21514d8981 587 #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */
AnnaBridge 156:ff21514d8981 588 #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */
AnnaBridge 156:ff21514d8981 589 #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */
AnnaBridge 156:ff21514d8981 590 #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */
AnnaBridge 156:ff21514d8981 591 #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */
AnnaBridge 156:ff21514d8981 592 /**
AnnaBridge 156:ff21514d8981 593 * @}
AnnaBridge 156:ff21514d8981 594 */
AnnaBridge 156:ff21514d8981 595
AnnaBridge 156:ff21514d8981 596 /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
AnnaBridge 156:ff21514d8981 597 * @{
AnnaBridge 156:ff21514d8981 598 */
AnnaBridge 156:ff21514d8981 599 #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
AnnaBridge 156:ff21514d8981 600 #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
AnnaBridge 156:ff21514d8981 601 #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
AnnaBridge 156:ff21514d8981 602 #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
AnnaBridge 156:ff21514d8981 603 /**
AnnaBridge 156:ff21514d8981 604 * @}
AnnaBridge 156:ff21514d8981 605 */
AnnaBridge 156:ff21514d8981 606
AnnaBridge 156:ff21514d8981 607 /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
AnnaBridge 156:ff21514d8981 608 * @{
AnnaBridge 156:ff21514d8981 609 */
AnnaBridge 156:ff21514d8981 610 #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
AnnaBridge 156:ff21514d8981 611 #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
AnnaBridge 156:ff21514d8981 612 /**
AnnaBridge 156:ff21514d8981 613 * @}
AnnaBridge 156:ff21514d8981 614 */
AnnaBridge 156:ff21514d8981 615
AnnaBridge 156:ff21514d8981 616 /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
AnnaBridge 156:ff21514d8981 617 * @{
AnnaBridge 156:ff21514d8981 618 */
AnnaBridge 156:ff21514d8981 619 #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
AnnaBridge 156:ff21514d8981 620 #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
AnnaBridge 156:ff21514d8981 621 #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
AnnaBridge 156:ff21514d8981 622 #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
AnnaBridge 156:ff21514d8981 623 /**
AnnaBridge 156:ff21514d8981 624 * @}
AnnaBridge 156:ff21514d8981 625 */
AnnaBridge 156:ff21514d8981 626
AnnaBridge 156:ff21514d8981 627 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR Off State Selection for Run mode state
AnnaBridge 156:ff21514d8981 628 * @{
AnnaBridge 156:ff21514d8981 629 */
AnnaBridge 156:ff21514d8981 630 #define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
AnnaBridge 156:ff21514d8981 631 #define TIM_OSSR_DISABLE (0x0000U)
AnnaBridge 156:ff21514d8981 632 /**
AnnaBridge 156:ff21514d8981 633 * @}
AnnaBridge 156:ff21514d8981 634 */
AnnaBridge 156:ff21514d8981 635
AnnaBridge 156:ff21514d8981 636 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI Off State Selection for Idle mode state
AnnaBridge 156:ff21514d8981 637 * @{
AnnaBridge 156:ff21514d8981 638 */
AnnaBridge 156:ff21514d8981 639 #define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
AnnaBridge 156:ff21514d8981 640 #define TIM_OSSI_DISABLE (0x0000U)
AnnaBridge 156:ff21514d8981 641 /**
AnnaBridge 156:ff21514d8981 642 * @}
AnnaBridge 156:ff21514d8981 643 */
AnnaBridge 156:ff21514d8981 644
AnnaBridge 156:ff21514d8981 645 /** @defgroup TIM_Lock_level TIM Lock level
AnnaBridge 156:ff21514d8981 646 * @{
AnnaBridge 156:ff21514d8981 647 */
AnnaBridge 156:ff21514d8981 648 #define TIM_LOCKLEVEL_OFF (0x0000U)
AnnaBridge 156:ff21514d8981 649 #define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
AnnaBridge 156:ff21514d8981 650 #define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
AnnaBridge 156:ff21514d8981 651 #define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
AnnaBridge 156:ff21514d8981 652 /**
AnnaBridge 156:ff21514d8981 653 * @}
AnnaBridge 156:ff21514d8981 654 */
AnnaBridge 156:ff21514d8981 655
AnnaBridge 156:ff21514d8981 656 /** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable Disable
AnnaBridge 156:ff21514d8981 657 * @{
AnnaBridge 156:ff21514d8981 658 */
AnnaBridge 156:ff21514d8981 659 #define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
AnnaBridge 156:ff21514d8981 660 #define TIM_BREAK_DISABLE (0x0000U)
AnnaBridge 156:ff21514d8981 661 /**
AnnaBridge 156:ff21514d8981 662 * @}
AnnaBridge 156:ff21514d8981 663 */
AnnaBridge 156:ff21514d8981 664
AnnaBridge 156:ff21514d8981 665 /** @defgroup TIM_Break_Polarity TIM Break Input Polarity
AnnaBridge 156:ff21514d8981 666 * @{
AnnaBridge 156:ff21514d8981 667 */
AnnaBridge 156:ff21514d8981 668 #define TIM_BREAKPOLARITY_LOW (0x0000U)
AnnaBridge 156:ff21514d8981 669 #define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
AnnaBridge 156:ff21514d8981 670 /**
AnnaBridge 156:ff21514d8981 671 * @}
AnnaBridge 156:ff21514d8981 672 */
AnnaBridge 156:ff21514d8981 673 /** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
AnnaBridge 156:ff21514d8981 674 * @{
AnnaBridge 156:ff21514d8981 675 */
AnnaBridge 156:ff21514d8981 676 #define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
AnnaBridge 156:ff21514d8981 677 #define TIM_AUTOMATICOUTPUT_DISABLE (0x0000U)
AnnaBridge 156:ff21514d8981 678 /**
AnnaBridge 156:ff21514d8981 679 * @}
AnnaBridge 156:ff21514d8981 680 */
AnnaBridge 156:ff21514d8981 681
AnnaBridge 156:ff21514d8981 682 /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
AnnaBridge 156:ff21514d8981 683 * @{
AnnaBridge 156:ff21514d8981 684 */
AnnaBridge 156:ff21514d8981 685 #define TIM_TRGO_RESET (0x0000U)
AnnaBridge 156:ff21514d8981 686 #define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
AnnaBridge 156:ff21514d8981 687 #define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
AnnaBridge 156:ff21514d8981 688 #define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
AnnaBridge 156:ff21514d8981 689 #define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
AnnaBridge 156:ff21514d8981 690 #define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
AnnaBridge 156:ff21514d8981 691 #define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
AnnaBridge 156:ff21514d8981 692 #define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
AnnaBridge 156:ff21514d8981 693 /**
AnnaBridge 156:ff21514d8981 694 * @}
AnnaBridge 156:ff21514d8981 695 */
AnnaBridge 156:ff21514d8981 696
AnnaBridge 156:ff21514d8981 697 /** @defgroup TIM_Slave_Mode TIM Slave Mode
AnnaBridge 156:ff21514d8981 698 * @{
AnnaBridge 156:ff21514d8981 699 */
AnnaBridge 156:ff21514d8981 700 #define TIM_SLAVEMODE_DISABLE (0x0000U)
AnnaBridge 156:ff21514d8981 701 #define TIM_SLAVEMODE_RESET (0x0004U)
AnnaBridge 156:ff21514d8981 702 #define TIM_SLAVEMODE_GATED (0x0005U)
AnnaBridge 156:ff21514d8981 703 #define TIM_SLAVEMODE_TRIGGER (0x0006U)
AnnaBridge 156:ff21514d8981 704 #define TIM_SLAVEMODE_EXTERNAL1 (0x0007U)
AnnaBridge 156:ff21514d8981 705 /**
AnnaBridge 156:ff21514d8981 706 * @}
AnnaBridge 156:ff21514d8981 707 */
AnnaBridge 156:ff21514d8981 708
AnnaBridge 156:ff21514d8981 709 /** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode
AnnaBridge 156:ff21514d8981 710 * @{
AnnaBridge 156:ff21514d8981 711 */
AnnaBridge 156:ff21514d8981 712 #define TIM_MASTERSLAVEMODE_ENABLE (0x0080U)
AnnaBridge 156:ff21514d8981 713 #define TIM_MASTERSLAVEMODE_DISABLE (0x0000U)
AnnaBridge 156:ff21514d8981 714 /**
AnnaBridge 156:ff21514d8981 715 * @}
AnnaBridge 156:ff21514d8981 716 */
AnnaBridge 156:ff21514d8981 717
AnnaBridge 156:ff21514d8981 718 /** @defgroup TIM_Trigger_Selection TIM Trigger Selection
AnnaBridge 156:ff21514d8981 719 * @{
AnnaBridge 156:ff21514d8981 720 */
AnnaBridge 156:ff21514d8981 721 #define TIM_TS_ITR0 (0x0000U)
AnnaBridge 156:ff21514d8981 722 #define TIM_TS_ITR1 (0x0010U)
AnnaBridge 156:ff21514d8981 723 #define TIM_TS_ITR2 (0x0020U)
AnnaBridge 156:ff21514d8981 724 #define TIM_TS_ITR3 (0x0030U)
AnnaBridge 156:ff21514d8981 725 #define TIM_TS_TI1F_ED (0x0040U)
AnnaBridge 156:ff21514d8981 726 #define TIM_TS_TI1FP1 (0x0050U)
AnnaBridge 156:ff21514d8981 727 #define TIM_TS_TI2FP2 (0x0060U)
AnnaBridge 156:ff21514d8981 728 #define TIM_TS_ETRF (0x0070U)
AnnaBridge 156:ff21514d8981 729 #define TIM_TS_NONE (0xFFFFU)
AnnaBridge 156:ff21514d8981 730 /**
AnnaBridge 156:ff21514d8981 731 * @}
AnnaBridge 156:ff21514d8981 732 */
AnnaBridge 156:ff21514d8981 733
AnnaBridge 156:ff21514d8981 734 /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
AnnaBridge 156:ff21514d8981 735 * @{
AnnaBridge 156:ff21514d8981 736 */
AnnaBridge 156:ff21514d8981 737 #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */
AnnaBridge 156:ff21514d8981 738 #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */
AnnaBridge 156:ff21514d8981 739 #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
AnnaBridge 156:ff21514d8981 740 #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
AnnaBridge 156:ff21514d8981 741 #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */
AnnaBridge 156:ff21514d8981 742 /**
AnnaBridge 156:ff21514d8981 743 * @}
AnnaBridge 156:ff21514d8981 744 */
AnnaBridge 156:ff21514d8981 745
AnnaBridge 156:ff21514d8981 746 /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
AnnaBridge 156:ff21514d8981 747 * @{
AnnaBridge 156:ff21514d8981 748 */
AnnaBridge 156:ff21514d8981 749 #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
AnnaBridge 156:ff21514d8981 750 #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
AnnaBridge 156:ff21514d8981 751 #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
AnnaBridge 156:ff21514d8981 752 #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
AnnaBridge 156:ff21514d8981 753 /**
AnnaBridge 156:ff21514d8981 754 * @}
AnnaBridge 156:ff21514d8981 755 */
AnnaBridge 156:ff21514d8981 756
AnnaBridge 156:ff21514d8981 757 /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
AnnaBridge 156:ff21514d8981 758 * @{
AnnaBridge 156:ff21514d8981 759 */
AnnaBridge 156:ff21514d8981 760 #define TIM_TI1SELECTION_CH1 (0x0000U)
AnnaBridge 156:ff21514d8981 761 #define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
AnnaBridge 156:ff21514d8981 762 /**
AnnaBridge 156:ff21514d8981 763 * @}
AnnaBridge 156:ff21514d8981 764 */
AnnaBridge 156:ff21514d8981 765
AnnaBridge 156:ff21514d8981 766 /** @defgroup TIM_DMA_Base_address TIM DMA Base Address
AnnaBridge 156:ff21514d8981 767 * @{
AnnaBridge 156:ff21514d8981 768 */
AnnaBridge 156:ff21514d8981 769 #define TIM_DMABASE_CR1 (0x00000000)
AnnaBridge 156:ff21514d8981 770 #define TIM_DMABASE_CR2 (0x00000001)
AnnaBridge 156:ff21514d8981 771 #define TIM_DMABASE_SMCR (0x00000002)
AnnaBridge 156:ff21514d8981 772 #define TIM_DMABASE_DIER (0x00000003)
AnnaBridge 156:ff21514d8981 773 #define TIM_DMABASE_SR (0x00000004)
AnnaBridge 156:ff21514d8981 774 #define TIM_DMABASE_EGR (0x00000005)
AnnaBridge 156:ff21514d8981 775 #define TIM_DMABASE_CCMR1 (0x00000006)
AnnaBridge 156:ff21514d8981 776 #define TIM_DMABASE_CCMR2 (0x00000007)
AnnaBridge 156:ff21514d8981 777 #define TIM_DMABASE_CCER (0x00000008)
AnnaBridge 156:ff21514d8981 778 #define TIM_DMABASE_CNT (0x00000009)
AnnaBridge 156:ff21514d8981 779 #define TIM_DMABASE_PSC (0x0000000A)
AnnaBridge 156:ff21514d8981 780 #define TIM_DMABASE_ARR (0x0000000B)
AnnaBridge 156:ff21514d8981 781 #define TIM_DMABASE_RCR (0x0000000C)
AnnaBridge 156:ff21514d8981 782 #define TIM_DMABASE_CCR1 (0x0000000D)
AnnaBridge 156:ff21514d8981 783 #define TIM_DMABASE_CCR2 (0x0000000E)
AnnaBridge 156:ff21514d8981 784 #define TIM_DMABASE_CCR3 (0x0000000F)
AnnaBridge 156:ff21514d8981 785 #define TIM_DMABASE_CCR4 (0x00000010)
AnnaBridge 156:ff21514d8981 786 #define TIM_DMABASE_BDTR (0x00000011)
AnnaBridge 156:ff21514d8981 787 #define TIM_DMABASE_DCR (0x00000012)
AnnaBridge 156:ff21514d8981 788 #define TIM_DMABASE_OR (0x00000013)
AnnaBridge 156:ff21514d8981 789 /**
AnnaBridge 156:ff21514d8981 790 * @}
AnnaBridge 156:ff21514d8981 791 */
AnnaBridge 156:ff21514d8981 792
AnnaBridge 156:ff21514d8981 793 /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
AnnaBridge 156:ff21514d8981 794 * @{
AnnaBridge 156:ff21514d8981 795 */
AnnaBridge 156:ff21514d8981 796 #define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000)
AnnaBridge 156:ff21514d8981 797 #define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100)
AnnaBridge 156:ff21514d8981 798 #define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200)
AnnaBridge 156:ff21514d8981 799 #define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300)
AnnaBridge 156:ff21514d8981 800 #define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400)
AnnaBridge 156:ff21514d8981 801 #define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500)
AnnaBridge 156:ff21514d8981 802 #define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600)
AnnaBridge 156:ff21514d8981 803 #define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700)
AnnaBridge 156:ff21514d8981 804 #define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800)
AnnaBridge 156:ff21514d8981 805 #define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900)
AnnaBridge 156:ff21514d8981 806 #define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00)
AnnaBridge 156:ff21514d8981 807 #define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00)
AnnaBridge 156:ff21514d8981 808 #define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00)
AnnaBridge 156:ff21514d8981 809 #define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00)
AnnaBridge 156:ff21514d8981 810 #define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00)
AnnaBridge 156:ff21514d8981 811 #define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00)
AnnaBridge 156:ff21514d8981 812 #define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000)
AnnaBridge 156:ff21514d8981 813 #define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100)
AnnaBridge 156:ff21514d8981 814 /**
AnnaBridge 156:ff21514d8981 815 * @}
AnnaBridge 156:ff21514d8981 816 */
AnnaBridge 156:ff21514d8981 817
AnnaBridge 156:ff21514d8981 818 /** @defgroup TIM_DMA_Handle_index TIM DMA Handle Index
AnnaBridge 156:ff21514d8981 819 * @{
AnnaBridge 156:ff21514d8981 820 */
AnnaBridge 156:ff21514d8981 821 #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0U) /*!< Index of the DMA handle used for Update DMA requests */
AnnaBridge 156:ff21514d8981 822 #define TIM_DMA_ID_CC1 ((uint16_t) 0x1U) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
AnnaBridge 156:ff21514d8981 823 #define TIM_DMA_ID_CC2 ((uint16_t) 0x2U) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
AnnaBridge 156:ff21514d8981 824 #define TIM_DMA_ID_CC3 ((uint16_t) 0x3U) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
AnnaBridge 156:ff21514d8981 825 #define TIM_DMA_ID_CC4 ((uint16_t) 0x4U) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
AnnaBridge 156:ff21514d8981 826 #define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5U) /*!< Index of the DMA handle used for Commutation DMA requests */
AnnaBridge 156:ff21514d8981 827 #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6U) /*!< Index of the DMA handle used for Trigger DMA requests */
AnnaBridge 156:ff21514d8981 828 /**
AnnaBridge 156:ff21514d8981 829 * @}
AnnaBridge 156:ff21514d8981 830 */
AnnaBridge 156:ff21514d8981 831
AnnaBridge 156:ff21514d8981 832 /** @defgroup TIM_Channel_CC_State TIM Capture/Compare Channel State
AnnaBridge 156:ff21514d8981 833 * @{
AnnaBridge 156:ff21514d8981 834 */
AnnaBridge 156:ff21514d8981 835 #define TIM_CCx_ENABLE (0x0001U)
AnnaBridge 156:ff21514d8981 836 #define TIM_CCx_DISABLE (0x0000U)
AnnaBridge 156:ff21514d8981 837 #define TIM_CCxN_ENABLE (0x0004U)
AnnaBridge 156:ff21514d8981 838 #define TIM_CCxN_DISABLE (0x0000U)
AnnaBridge 156:ff21514d8981 839 /**
AnnaBridge 156:ff21514d8981 840 * @}
AnnaBridge 156:ff21514d8981 841 */
AnnaBridge 156:ff21514d8981 842
AnnaBridge 156:ff21514d8981 843 /**
AnnaBridge 156:ff21514d8981 844 * @}
AnnaBridge 156:ff21514d8981 845 */
AnnaBridge 156:ff21514d8981 846
AnnaBridge 156:ff21514d8981 847 /* Private Constants -----------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 848 /** @defgroup TIM_Private_Constants TIM Private Constants
AnnaBridge 156:ff21514d8981 849 * @{
AnnaBridge 156:ff21514d8981 850 */
AnnaBridge 156:ff21514d8981 851
AnnaBridge 156:ff21514d8981 852 /* The counter of a timer instance is disabled only if all the CCx and CCxN
AnnaBridge 156:ff21514d8981 853 channels have been disabled */
AnnaBridge 156:ff21514d8981 854 #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
AnnaBridge 156:ff21514d8981 855 #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
AnnaBridge 156:ff21514d8981 856
AnnaBridge 156:ff21514d8981 857 /**
AnnaBridge 156:ff21514d8981 858 * @}
AnnaBridge 156:ff21514d8981 859 */
AnnaBridge 156:ff21514d8981 860
AnnaBridge 156:ff21514d8981 861 /* Private Macros -----------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 862 /** @defgroup TIM_Private_Macros TIM Private Macros
AnnaBridge 156:ff21514d8981 863 * @{
AnnaBridge 156:ff21514d8981 864 */
AnnaBridge 156:ff21514d8981 865
AnnaBridge 156:ff21514d8981 866 #define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) || \
AnnaBridge 156:ff21514d8981 867 ((MODE) == TIM_COUNTERMODE_DOWN) || \
AnnaBridge 156:ff21514d8981 868 ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) || \
AnnaBridge 156:ff21514d8981 869 ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) || \
AnnaBridge 156:ff21514d8981 870 ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
AnnaBridge 156:ff21514d8981 871
AnnaBridge 156:ff21514d8981 872 #define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \
AnnaBridge 156:ff21514d8981 873 ((DIV) == TIM_CLOCKDIVISION_DIV2) || \
AnnaBridge 156:ff21514d8981 874 ((DIV) == TIM_CLOCKDIVISION_DIV4))
AnnaBridge 156:ff21514d8981 875
AnnaBridge 156:ff21514d8981 876 #define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
AnnaBridge 156:ff21514d8981 877 ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
AnnaBridge 156:ff21514d8981 878
AnnaBridge 156:ff21514d8981 879 #define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \
AnnaBridge 156:ff21514d8981 880 ((MODE) == TIM_OCMODE_PWM2))
AnnaBridge 156:ff21514d8981 881
AnnaBridge 156:ff21514d8981 882 #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \
AnnaBridge 156:ff21514d8981 883 ((MODE) == TIM_OCMODE_ACTIVE) || \
AnnaBridge 156:ff21514d8981 884 ((MODE) == TIM_OCMODE_INACTIVE) || \
AnnaBridge 156:ff21514d8981 885 ((MODE) == TIM_OCMODE_TOGGLE) || \
AnnaBridge 156:ff21514d8981 886 ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \
AnnaBridge 156:ff21514d8981 887 ((MODE) == TIM_OCMODE_FORCED_INACTIVE))
AnnaBridge 156:ff21514d8981 888
AnnaBridge 156:ff21514d8981 889 #define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \
AnnaBridge 156:ff21514d8981 890 ((STATE) == TIM_OCFAST_ENABLE))
AnnaBridge 156:ff21514d8981 891
AnnaBridge 156:ff21514d8981 892 #define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \
AnnaBridge 156:ff21514d8981 893 ((POLARITY) == TIM_OCPOLARITY_LOW))
AnnaBridge 156:ff21514d8981 894
AnnaBridge 156:ff21514d8981 895 #define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) || \
AnnaBridge 156:ff21514d8981 896 ((POLARITY) == TIM_OCNPOLARITY_LOW))
AnnaBridge 156:ff21514d8981 897
AnnaBridge 156:ff21514d8981 898 #define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \
AnnaBridge 156:ff21514d8981 899 ((STATE) == TIM_OCIDLESTATE_RESET))
AnnaBridge 156:ff21514d8981 900
AnnaBridge 156:ff21514d8981 901 #define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || \
AnnaBridge 156:ff21514d8981 902 ((STATE) == TIM_OCNIDLESTATE_RESET))
AnnaBridge 156:ff21514d8981 903
AnnaBridge 156:ff21514d8981 904 #define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 156:ff21514d8981 905 ((CHANNEL) == TIM_CHANNEL_2) || \
AnnaBridge 156:ff21514d8981 906 ((CHANNEL) == TIM_CHANNEL_3) || \
AnnaBridge 156:ff21514d8981 907 ((CHANNEL) == TIM_CHANNEL_4) || \
AnnaBridge 156:ff21514d8981 908 ((CHANNEL) == TIM_CHANNEL_ALL))
AnnaBridge 156:ff21514d8981 909
AnnaBridge 156:ff21514d8981 910 #define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 156:ff21514d8981 911 ((CHANNEL) == TIM_CHANNEL_2))
AnnaBridge 156:ff21514d8981 912
AnnaBridge 156:ff21514d8981 913 #define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 156:ff21514d8981 914 ((CHANNEL) == TIM_CHANNEL_2) || \
AnnaBridge 156:ff21514d8981 915 ((CHANNEL) == TIM_CHANNEL_3))
AnnaBridge 156:ff21514d8981 916
AnnaBridge 156:ff21514d8981 917 #define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) || \
AnnaBridge 156:ff21514d8981 918 ((POLARITY) == TIM_ICPOLARITY_FALLING) || \
AnnaBridge 156:ff21514d8981 919 ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
AnnaBridge 156:ff21514d8981 920
AnnaBridge 156:ff21514d8981 921 #define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \
AnnaBridge 156:ff21514d8981 922 ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \
AnnaBridge 156:ff21514d8981 923 ((SELECTION) == TIM_ICSELECTION_TRC))
AnnaBridge 156:ff21514d8981 924
AnnaBridge 156:ff21514d8981 925 #define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
AnnaBridge 156:ff21514d8981 926 ((PRESCALER) == TIM_ICPSC_DIV2) || \
AnnaBridge 156:ff21514d8981 927 ((PRESCALER) == TIM_ICPSC_DIV4) || \
AnnaBridge 156:ff21514d8981 928 ((PRESCALER) == TIM_ICPSC_DIV8))
AnnaBridge 156:ff21514d8981 929
AnnaBridge 156:ff21514d8981 930 #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \
AnnaBridge 156:ff21514d8981 931 ((MODE) == TIM_OPMODE_REPETITIVE))
AnnaBridge 156:ff21514d8981 932
AnnaBridge 156:ff21514d8981 933 #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \
AnnaBridge 156:ff21514d8981 934 ((MODE) == TIM_ENCODERMODE_TI2) || \
AnnaBridge 156:ff21514d8981 935 ((MODE) == TIM_ENCODERMODE_TI12))
AnnaBridge 156:ff21514d8981 936
AnnaBridge 156:ff21514d8981 937 #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FFU) == 0x00000000U) && ((SOURCE) != 0x00000000U))
AnnaBridge 156:ff21514d8981 938
AnnaBridge 156:ff21514d8981 939 #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00U) == 0x00000000U) && ((SOURCE) != 0x00000000U))
AnnaBridge 156:ff21514d8981 940
AnnaBridge 156:ff21514d8981 941 #define IS_TIM_FLAG(FLAG) (((FLAG) == TIM_FLAG_UPDATE) || \
AnnaBridge 156:ff21514d8981 942 ((FLAG) == TIM_FLAG_CC1) || \
AnnaBridge 156:ff21514d8981 943 ((FLAG) == TIM_FLAG_CC2) || \
AnnaBridge 156:ff21514d8981 944 ((FLAG) == TIM_FLAG_CC3) || \
AnnaBridge 156:ff21514d8981 945 ((FLAG) == TIM_FLAG_CC4) || \
AnnaBridge 156:ff21514d8981 946 ((FLAG) == TIM_FLAG_COM) || \
AnnaBridge 156:ff21514d8981 947 ((FLAG) == TIM_FLAG_TRIGGER) || \
AnnaBridge 156:ff21514d8981 948 ((FLAG) == TIM_FLAG_BREAK) || \
AnnaBridge 156:ff21514d8981 949 ((FLAG) == TIM_FLAG_CC1OF) || \
AnnaBridge 156:ff21514d8981 950 ((FLAG) == TIM_FLAG_CC2OF) || \
AnnaBridge 156:ff21514d8981 951 ((FLAG) == TIM_FLAG_CC3OF) || \
AnnaBridge 156:ff21514d8981 952 ((FLAG) == TIM_FLAG_CC4OF))
AnnaBridge 156:ff21514d8981 953
AnnaBridge 156:ff21514d8981 954 #define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \
AnnaBridge 156:ff21514d8981 955 ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \
AnnaBridge 156:ff21514d8981 956 ((CLOCK) == TIM_CLOCKSOURCE_ITR0) || \
AnnaBridge 156:ff21514d8981 957 ((CLOCK) == TIM_CLOCKSOURCE_ITR1) || \
AnnaBridge 156:ff21514d8981 958 ((CLOCK) == TIM_CLOCKSOURCE_ITR2) || \
AnnaBridge 156:ff21514d8981 959 ((CLOCK) == TIM_CLOCKSOURCE_ITR3) || \
AnnaBridge 156:ff21514d8981 960 ((CLOCK) == TIM_CLOCKSOURCE_TI1ED) || \
AnnaBridge 156:ff21514d8981 961 ((CLOCK) == TIM_CLOCKSOURCE_TI1) || \
AnnaBridge 156:ff21514d8981 962 ((CLOCK) == TIM_CLOCKSOURCE_TI2) || \
AnnaBridge 156:ff21514d8981 963 ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
AnnaBridge 156:ff21514d8981 964
AnnaBridge 156:ff21514d8981 965 #define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) || \
AnnaBridge 156:ff21514d8981 966 ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \
AnnaBridge 156:ff21514d8981 967 ((POLARITY) == TIM_CLOCKPOLARITY_RISING) || \
AnnaBridge 156:ff21514d8981 968 ((POLARITY) == TIM_CLOCKPOLARITY_FALLING) || \
AnnaBridge 156:ff21514d8981 969 ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
AnnaBridge 156:ff21514d8981 970
AnnaBridge 156:ff21514d8981 971 #define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \
AnnaBridge 156:ff21514d8981 972 ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \
AnnaBridge 156:ff21514d8981 973 ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \
AnnaBridge 156:ff21514d8981 974 ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
AnnaBridge 156:ff21514d8981 975
AnnaBridge 156:ff21514d8981 976 #define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xFU)
AnnaBridge 156:ff21514d8981 977
AnnaBridge 156:ff21514d8981 978 #define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
AnnaBridge 156:ff21514d8981 979 ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
AnnaBridge 156:ff21514d8981 980
AnnaBridge 156:ff21514d8981 981 #define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \
AnnaBridge 156:ff21514d8981 982 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \
AnnaBridge 156:ff21514d8981 983 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \
AnnaBridge 156:ff21514d8981 984 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
AnnaBridge 156:ff21514d8981 985
AnnaBridge 156:ff21514d8981 986 #define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xFU)
AnnaBridge 156:ff21514d8981 987
AnnaBridge 156:ff21514d8981 988 #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \
AnnaBridge 156:ff21514d8981 989 ((STATE) == TIM_OSSR_DISABLE))
AnnaBridge 156:ff21514d8981 990
AnnaBridge 156:ff21514d8981 991 #define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \
AnnaBridge 156:ff21514d8981 992 ((STATE) == TIM_OSSI_DISABLE))
AnnaBridge 156:ff21514d8981 993
AnnaBridge 156:ff21514d8981 994 #define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \
AnnaBridge 156:ff21514d8981 995 ((LEVEL) == TIM_LOCKLEVEL_1) || \
AnnaBridge 156:ff21514d8981 996 ((LEVEL) == TIM_LOCKLEVEL_2) || \
AnnaBridge 156:ff21514d8981 997 ((LEVEL) == TIM_LOCKLEVEL_3))
AnnaBridge 156:ff21514d8981 998
AnnaBridge 156:ff21514d8981 999 #define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || \
AnnaBridge 156:ff21514d8981 1000 ((STATE) == TIM_BREAK_DISABLE))
AnnaBridge 156:ff21514d8981 1001
AnnaBridge 156:ff21514d8981 1002 #define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || \
AnnaBridge 156:ff21514d8981 1003 ((POLARITY) == TIM_BREAKPOLARITY_HIGH))
AnnaBridge 156:ff21514d8981 1004
AnnaBridge 156:ff21514d8981 1005 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \
AnnaBridge 156:ff21514d8981 1006 ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
AnnaBridge 156:ff21514d8981 1007
AnnaBridge 156:ff21514d8981 1008 #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \
AnnaBridge 156:ff21514d8981 1009 ((SOURCE) == TIM_TRGO_ENABLE) || \
AnnaBridge 156:ff21514d8981 1010 ((SOURCE) == TIM_TRGO_UPDATE) || \
AnnaBridge 156:ff21514d8981 1011 ((SOURCE) == TIM_TRGO_OC1) || \
AnnaBridge 156:ff21514d8981 1012 ((SOURCE) == TIM_TRGO_OC1REF) || \
AnnaBridge 156:ff21514d8981 1013 ((SOURCE) == TIM_TRGO_OC2REF) || \
AnnaBridge 156:ff21514d8981 1014 ((SOURCE) == TIM_TRGO_OC3REF) || \
AnnaBridge 156:ff21514d8981 1015 ((SOURCE) == TIM_TRGO_OC4REF))
AnnaBridge 156:ff21514d8981 1016
AnnaBridge 156:ff21514d8981 1017 #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \
AnnaBridge 156:ff21514d8981 1018 ((MODE) == TIM_SLAVEMODE_GATED) || \
AnnaBridge 156:ff21514d8981 1019 ((MODE) == TIM_SLAVEMODE_RESET) || \
AnnaBridge 156:ff21514d8981 1020 ((MODE) == TIM_SLAVEMODE_TRIGGER) || \
AnnaBridge 156:ff21514d8981 1021 ((MODE) == TIM_SLAVEMODE_EXTERNAL1))
AnnaBridge 156:ff21514d8981 1022
AnnaBridge 156:ff21514d8981 1023 #define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \
AnnaBridge 156:ff21514d8981 1024 ((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
AnnaBridge 156:ff21514d8981 1025
AnnaBridge 156:ff21514d8981 1026 #define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
AnnaBridge 156:ff21514d8981 1027 ((SELECTION) == TIM_TS_ITR1) || \
AnnaBridge 156:ff21514d8981 1028 ((SELECTION) == TIM_TS_ITR2) || \
AnnaBridge 156:ff21514d8981 1029 ((SELECTION) == TIM_TS_ITR3) || \
AnnaBridge 156:ff21514d8981 1030 ((SELECTION) == TIM_TS_TI1F_ED) || \
AnnaBridge 156:ff21514d8981 1031 ((SELECTION) == TIM_TS_TI1FP1) || \
AnnaBridge 156:ff21514d8981 1032 ((SELECTION) == TIM_TS_TI2FP2) || \
AnnaBridge 156:ff21514d8981 1033 ((SELECTION) == TIM_TS_ETRF))
AnnaBridge 156:ff21514d8981 1034
AnnaBridge 156:ff21514d8981 1035 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
AnnaBridge 156:ff21514d8981 1036 ((SELECTION) == TIM_TS_ITR1) || \
AnnaBridge 156:ff21514d8981 1037 ((SELECTION) == TIM_TS_ITR2) || \
AnnaBridge 156:ff21514d8981 1038 ((SELECTION) == TIM_TS_ITR3) || \
AnnaBridge 156:ff21514d8981 1039 ((SELECTION) == TIM_TS_NONE))
AnnaBridge 156:ff21514d8981 1040
AnnaBridge 156:ff21514d8981 1041 #define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) || \
AnnaBridge 156:ff21514d8981 1042 ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
AnnaBridge 156:ff21514d8981 1043 ((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) || \
AnnaBridge 156:ff21514d8981 1044 ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) || \
AnnaBridge 156:ff21514d8981 1045 ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
AnnaBridge 156:ff21514d8981 1046
AnnaBridge 156:ff21514d8981 1047 #define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \
AnnaBridge 156:ff21514d8981 1048 ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \
AnnaBridge 156:ff21514d8981 1049 ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \
AnnaBridge 156:ff21514d8981 1050 ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
AnnaBridge 156:ff21514d8981 1051
AnnaBridge 156:ff21514d8981 1052 #define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xFU)
AnnaBridge 156:ff21514d8981 1053
AnnaBridge 156:ff21514d8981 1054 #define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \
AnnaBridge 156:ff21514d8981 1055 ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
AnnaBridge 156:ff21514d8981 1056
AnnaBridge 156:ff21514d8981 1057 #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) || \
AnnaBridge 156:ff21514d8981 1058 ((BASE) == TIM_DMABASE_CR2) || \
AnnaBridge 156:ff21514d8981 1059 ((BASE) == TIM_DMABASE_SMCR) || \
AnnaBridge 156:ff21514d8981 1060 ((BASE) == TIM_DMABASE_DIER) || \
AnnaBridge 156:ff21514d8981 1061 ((BASE) == TIM_DMABASE_SR) || \
AnnaBridge 156:ff21514d8981 1062 ((BASE) == TIM_DMABASE_EGR) || \
AnnaBridge 156:ff21514d8981 1063 ((BASE) == TIM_DMABASE_CCMR1) || \
AnnaBridge 156:ff21514d8981 1064 ((BASE) == TIM_DMABASE_CCMR2) || \
AnnaBridge 156:ff21514d8981 1065 ((BASE) == TIM_DMABASE_CCER) || \
AnnaBridge 156:ff21514d8981 1066 ((BASE) == TIM_DMABASE_CNT) || \
AnnaBridge 156:ff21514d8981 1067 ((BASE) == TIM_DMABASE_PSC) || \
AnnaBridge 156:ff21514d8981 1068 ((BASE) == TIM_DMABASE_ARR) || \
AnnaBridge 156:ff21514d8981 1069 ((BASE) == TIM_DMABASE_RCR) || \
AnnaBridge 156:ff21514d8981 1070 ((BASE) == TIM_DMABASE_CCR1) || \
AnnaBridge 156:ff21514d8981 1071 ((BASE) == TIM_DMABASE_CCR2) || \
AnnaBridge 156:ff21514d8981 1072 ((BASE) == TIM_DMABASE_CCR3) || \
AnnaBridge 156:ff21514d8981 1073 ((BASE) == TIM_DMABASE_CCR4) || \
AnnaBridge 156:ff21514d8981 1074 ((BASE) == TIM_DMABASE_BDTR) || \
AnnaBridge 156:ff21514d8981 1075 ((BASE) == TIM_DMABASE_DCR) || \
AnnaBridge 156:ff21514d8981 1076 ((BASE) == TIM_DMABASE_OR))
AnnaBridge 156:ff21514d8981 1077
AnnaBridge 156:ff21514d8981 1078 #define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER) || \
AnnaBridge 156:ff21514d8981 1079 ((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
AnnaBridge 156:ff21514d8981 1080 ((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
AnnaBridge 156:ff21514d8981 1081 ((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
AnnaBridge 156:ff21514d8981 1082 ((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
AnnaBridge 156:ff21514d8981 1083 ((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
AnnaBridge 156:ff21514d8981 1084 ((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
AnnaBridge 156:ff21514d8981 1085 ((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
AnnaBridge 156:ff21514d8981 1086 ((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
AnnaBridge 156:ff21514d8981 1087 ((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
AnnaBridge 156:ff21514d8981 1088 ((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
AnnaBridge 156:ff21514d8981 1089 ((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
AnnaBridge 156:ff21514d8981 1090 ((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
AnnaBridge 156:ff21514d8981 1091 ((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
AnnaBridge 156:ff21514d8981 1092 ((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
AnnaBridge 156:ff21514d8981 1093 ((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
AnnaBridge 156:ff21514d8981 1094 ((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
AnnaBridge 156:ff21514d8981 1095 ((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS))
AnnaBridge 156:ff21514d8981 1096
AnnaBridge 156:ff21514d8981 1097 #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xFU)
AnnaBridge 156:ff21514d8981 1098
AnnaBridge 156:ff21514d8981 1099 /** @brief Set TIM IC prescaler
AnnaBridge 156:ff21514d8981 1100 * @param __HANDLE__: TIM handle
AnnaBridge 156:ff21514d8981 1101 * @param __CHANNEL__: specifies TIM Channel
AnnaBridge 156:ff21514d8981 1102 * @param __ICPSC__: specifies the prescaler value.
AnnaBridge 156:ff21514d8981 1103 * @retval None
AnnaBridge 156:ff21514d8981 1104 */
AnnaBridge 156:ff21514d8981 1105 #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
AnnaBridge 156:ff21514d8981 1106 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
AnnaBridge 156:ff21514d8981 1107 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
AnnaBridge 156:ff21514d8981 1108 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
AnnaBridge 156:ff21514d8981 1109 ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
AnnaBridge 156:ff21514d8981 1110
AnnaBridge 156:ff21514d8981 1111 /** @brief Reset TIM IC prescaler
AnnaBridge 156:ff21514d8981 1112 * @param __HANDLE__: TIM handle
AnnaBridge 156:ff21514d8981 1113 * @param __CHANNEL__: specifies TIM Channel
AnnaBridge 156:ff21514d8981 1114 * @retval None
AnnaBridge 156:ff21514d8981 1115 */
AnnaBridge 156:ff21514d8981 1116 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
AnnaBridge 156:ff21514d8981 1117 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
AnnaBridge 156:ff21514d8981 1118 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
AnnaBridge 156:ff21514d8981 1119 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
AnnaBridge 156:ff21514d8981 1120 ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
AnnaBridge 156:ff21514d8981 1121
AnnaBridge 156:ff21514d8981 1122
AnnaBridge 156:ff21514d8981 1123 /** @brief Set TIM IC polarity
AnnaBridge 156:ff21514d8981 1124 * @param __HANDLE__: TIM handle
AnnaBridge 156:ff21514d8981 1125 * @param __CHANNEL__: specifies TIM Channel
AnnaBridge 156:ff21514d8981 1126 * @param __POLARITY__: specifies TIM Channel Polarity
AnnaBridge 156:ff21514d8981 1127 * @retval None
AnnaBridge 156:ff21514d8981 1128 */
AnnaBridge 156:ff21514d8981 1129 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
AnnaBridge 156:ff21514d8981 1130 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
AnnaBridge 156:ff21514d8981 1131 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
AnnaBridge 156:ff21514d8981 1132 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
AnnaBridge 156:ff21514d8981 1133 ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 12U)))
AnnaBridge 156:ff21514d8981 1134
AnnaBridge 156:ff21514d8981 1135 /** @brief Reset TIM IC polarity
AnnaBridge 156:ff21514d8981 1136 * @param __HANDLE__: TIM handle
AnnaBridge 156:ff21514d8981 1137 * @param __CHANNEL__: specifies TIM Channel
AnnaBridge 156:ff21514d8981 1138 * @retval None
AnnaBridge 156:ff21514d8981 1139 */
AnnaBridge 156:ff21514d8981 1140 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
AnnaBridge 156:ff21514d8981 1141 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
AnnaBridge 156:ff21514d8981 1142 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
AnnaBridge 156:ff21514d8981 1143 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
AnnaBridge 156:ff21514d8981 1144 ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
AnnaBridge 156:ff21514d8981 1145
AnnaBridge 156:ff21514d8981 1146 /**
AnnaBridge 156:ff21514d8981 1147 * @}
AnnaBridge 156:ff21514d8981 1148 */
AnnaBridge 156:ff21514d8981 1149
AnnaBridge 156:ff21514d8981 1150 /* Private Functions --------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 1151 /** @addtogroup TIM_Private_Functions
AnnaBridge 156:ff21514d8981 1152 * @{
AnnaBridge 156:ff21514d8981 1153 */
AnnaBridge 156:ff21514d8981 1154 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
AnnaBridge 156:ff21514d8981 1155 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
AnnaBridge 156:ff21514d8981 1156 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
AnnaBridge 156:ff21514d8981 1157 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
AnnaBridge 156:ff21514d8981 1158 void TIM_DMAError(DMA_HandleTypeDef *hdma);
AnnaBridge 156:ff21514d8981 1159 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
AnnaBridge 156:ff21514d8981 1160 void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
AnnaBridge 156:ff21514d8981 1161 /**
AnnaBridge 156:ff21514d8981 1162 * @}
AnnaBridge 156:ff21514d8981 1163 */
AnnaBridge 156:ff21514d8981 1164
AnnaBridge 156:ff21514d8981 1165 /* Exported macros -----------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 1166 /** @defgroup TIM_Exported_Macros TIM Exported Macros
AnnaBridge 156:ff21514d8981 1167 * @{
AnnaBridge 156:ff21514d8981 1168 */
AnnaBridge 156:ff21514d8981 1169
AnnaBridge 156:ff21514d8981 1170 /** @brief Reset TIM handle state
AnnaBridge 156:ff21514d8981 1171 * @param __HANDLE__: TIM handle.
AnnaBridge 156:ff21514d8981 1172 * @retval None
AnnaBridge 156:ff21514d8981 1173 */
AnnaBridge 156:ff21514d8981 1174 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
AnnaBridge 156:ff21514d8981 1175
AnnaBridge 156:ff21514d8981 1176 /**
AnnaBridge 156:ff21514d8981 1177 * @brief Enable the TIM peripheral.
AnnaBridge 156:ff21514d8981 1178 * @param __HANDLE__: TIM handle
AnnaBridge 156:ff21514d8981 1179 * @retval None
AnnaBridge 156:ff21514d8981 1180 */
AnnaBridge 156:ff21514d8981 1181 #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
AnnaBridge 156:ff21514d8981 1182
AnnaBridge 156:ff21514d8981 1183 /**
AnnaBridge 156:ff21514d8981 1184 * @brief Enable the TIM main Output.
AnnaBridge 156:ff21514d8981 1185 * @param __HANDLE__: TIM handle
AnnaBridge 156:ff21514d8981 1186 * @retval None
AnnaBridge 156:ff21514d8981 1187 */
AnnaBridge 156:ff21514d8981 1188 #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
AnnaBridge 156:ff21514d8981 1189
AnnaBridge 156:ff21514d8981 1190 /**
AnnaBridge 156:ff21514d8981 1191 * @brief Disable the TIM peripheral.
AnnaBridge 156:ff21514d8981 1192 * @param __HANDLE__: TIM handle
AnnaBridge 156:ff21514d8981 1193 * @retval None
AnnaBridge 156:ff21514d8981 1194 */
AnnaBridge 156:ff21514d8981 1195 #define __HAL_TIM_DISABLE(__HANDLE__) \
AnnaBridge 156:ff21514d8981 1196 do { \
AnnaBridge 156:ff21514d8981 1197 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
AnnaBridge 156:ff21514d8981 1198 { \
AnnaBridge 156:ff21514d8981 1199 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
AnnaBridge 156:ff21514d8981 1200 { \
AnnaBridge 156:ff21514d8981 1201 (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
AnnaBridge 156:ff21514d8981 1202 } \
AnnaBridge 156:ff21514d8981 1203 } \
AnnaBridge 156:ff21514d8981 1204 } while(0)
AnnaBridge 156:ff21514d8981 1205 /* The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN
AnnaBridge 156:ff21514d8981 1206 channels have been disabled */
AnnaBridge 156:ff21514d8981 1207 /**
AnnaBridge 156:ff21514d8981 1208 * @brief Disable the TIM main Output.
AnnaBridge 156:ff21514d8981 1209 * @param __HANDLE__: TIM handle
AnnaBridge 156:ff21514d8981 1210 * @retval None
AnnaBridge 156:ff21514d8981 1211 * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
AnnaBridge 156:ff21514d8981 1212 */
AnnaBridge 156:ff21514d8981 1213 #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
AnnaBridge 156:ff21514d8981 1214 do { \
AnnaBridge 156:ff21514d8981 1215 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
AnnaBridge 156:ff21514d8981 1216 { \
AnnaBridge 156:ff21514d8981 1217 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
AnnaBridge 156:ff21514d8981 1218 { \
AnnaBridge 156:ff21514d8981 1219 (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
AnnaBridge 156:ff21514d8981 1220 } \
AnnaBridge 156:ff21514d8981 1221 } \
AnnaBridge 156:ff21514d8981 1222 } while(0)
AnnaBridge 156:ff21514d8981 1223
AnnaBridge 156:ff21514d8981 1224 /**
AnnaBridge 156:ff21514d8981 1225 * @brief Enables the specified TIM interrupt.
AnnaBridge 156:ff21514d8981 1226 * @param __HANDLE__: specifies the TIM Handle.
AnnaBridge 156:ff21514d8981 1227 * @param __INTERRUPT__: specifies the TIM interrupt source to enable.
AnnaBridge 156:ff21514d8981 1228 * This parameter can be one of the following values:
AnnaBridge 156:ff21514d8981 1229 * @arg TIM_IT_UPDATE: Update interrupt
AnnaBridge 156:ff21514d8981 1230 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
AnnaBridge 156:ff21514d8981 1231 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
AnnaBridge 156:ff21514d8981 1232 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
AnnaBridge 156:ff21514d8981 1233 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
AnnaBridge 156:ff21514d8981 1234 * @arg TIM_IT_COM: Commutation interrupt
AnnaBridge 156:ff21514d8981 1235 * @arg TIM_IT_TRIGGER: Trigger interrupt
AnnaBridge 156:ff21514d8981 1236 * @arg TIM_IT_BREAK: Break interrupt
AnnaBridge 156:ff21514d8981 1237 * @retval None
AnnaBridge 156:ff21514d8981 1238 */
AnnaBridge 156:ff21514d8981 1239 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
AnnaBridge 156:ff21514d8981 1240
AnnaBridge 156:ff21514d8981 1241 /**
AnnaBridge 156:ff21514d8981 1242 * @brief Disables the specified TIM interrupt.
AnnaBridge 156:ff21514d8981 1243 * @param __HANDLE__: specifies the TIM Handle.
AnnaBridge 156:ff21514d8981 1244 * @param __INTERRUPT__: specifies the TIM interrupt source to disable.
AnnaBridge 156:ff21514d8981 1245 * This parameter can be one of the following values:
AnnaBridge 156:ff21514d8981 1246 * @arg TIM_IT_UPDATE: Update interrupt
AnnaBridge 156:ff21514d8981 1247 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
AnnaBridge 156:ff21514d8981 1248 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
AnnaBridge 156:ff21514d8981 1249 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
AnnaBridge 156:ff21514d8981 1250 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
AnnaBridge 156:ff21514d8981 1251 * @arg TIM_IT_COM: Commutation interrupt
AnnaBridge 156:ff21514d8981 1252 * @arg TIM_IT_TRIGGER: Trigger interrupt
AnnaBridge 156:ff21514d8981 1253 * @arg TIM_IT_BREAK: Break interrupt
AnnaBridge 156:ff21514d8981 1254 * @retval None
AnnaBridge 156:ff21514d8981 1255 */
AnnaBridge 156:ff21514d8981 1256 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
AnnaBridge 156:ff21514d8981 1257
AnnaBridge 156:ff21514d8981 1258 /**
AnnaBridge 156:ff21514d8981 1259 * @brief Enables the specified DMA request.
AnnaBridge 156:ff21514d8981 1260 * @param __HANDLE__: specifies the TIM Handle.
AnnaBridge 156:ff21514d8981 1261 * @param __DMA__: specifies the TIM DMA request to enable.
AnnaBridge 156:ff21514d8981 1262 * This parameter can be one of the following values:
AnnaBridge 156:ff21514d8981 1263 * @arg TIM_DMA_UPDATE: Update DMA request
AnnaBridge 156:ff21514d8981 1264 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
AnnaBridge 156:ff21514d8981 1265 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
AnnaBridge 156:ff21514d8981 1266 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
AnnaBridge 156:ff21514d8981 1267 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
AnnaBridge 156:ff21514d8981 1268 * @arg TIM_DMA_COM: Commutation DMA request
AnnaBridge 156:ff21514d8981 1269 * @arg TIM_DMA_TRIGGER: Trigger DMA request
AnnaBridge 156:ff21514d8981 1270 * @retval None
AnnaBridge 156:ff21514d8981 1271 */
AnnaBridge 156:ff21514d8981 1272 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
AnnaBridge 156:ff21514d8981 1273
AnnaBridge 156:ff21514d8981 1274 /**
AnnaBridge 156:ff21514d8981 1275 * @brief Disables the specified DMA request.
AnnaBridge 156:ff21514d8981 1276 * @param __HANDLE__: specifies the TIM Handle.
AnnaBridge 156:ff21514d8981 1277 * @param __DMA__: specifies the TIM DMA request to disable.
AnnaBridge 156:ff21514d8981 1278 * This parameter can be one of the following values:
AnnaBridge 156:ff21514d8981 1279 * @arg TIM_DMA_UPDATE: Update DMA request
AnnaBridge 156:ff21514d8981 1280 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
AnnaBridge 156:ff21514d8981 1281 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
AnnaBridge 156:ff21514d8981 1282 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
AnnaBridge 156:ff21514d8981 1283 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
AnnaBridge 156:ff21514d8981 1284 * @arg TIM_DMA_COM: Commutation DMA request
AnnaBridge 156:ff21514d8981 1285 * @arg TIM_DMA_TRIGGER: Trigger DMA request
AnnaBridge 156:ff21514d8981 1286 * @retval None
AnnaBridge 156:ff21514d8981 1287 */
AnnaBridge 156:ff21514d8981 1288 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
AnnaBridge 156:ff21514d8981 1289
AnnaBridge 156:ff21514d8981 1290 /**
AnnaBridge 156:ff21514d8981 1291 * @brief Checks whether the specified TIM interrupt flag is set or not.
AnnaBridge 156:ff21514d8981 1292 * @param __HANDLE__: specifies the TIM Handle.
AnnaBridge 156:ff21514d8981 1293 * @param __FLAG__: specifies the TIM interrupt flag to check.
AnnaBridge 156:ff21514d8981 1294 * This parameter can be one of the following values:
AnnaBridge 156:ff21514d8981 1295 * @arg TIM_FLAG_UPDATE: Update interrupt flag
AnnaBridge 156:ff21514d8981 1296 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
AnnaBridge 156:ff21514d8981 1297 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
AnnaBridge 156:ff21514d8981 1298 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
AnnaBridge 156:ff21514d8981 1299 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
AnnaBridge 156:ff21514d8981 1300 * @arg TIM_FLAG_COM: Commutation interrupt flag
AnnaBridge 156:ff21514d8981 1301 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
AnnaBridge 156:ff21514d8981 1302 * @arg TIM_FLAG_BREAK: Break interrupt flag
AnnaBridge 156:ff21514d8981 1303 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
AnnaBridge 156:ff21514d8981 1304 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
AnnaBridge 156:ff21514d8981 1305 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
AnnaBridge 156:ff21514d8981 1306 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
AnnaBridge 156:ff21514d8981 1307 * @retval The new state of __FLAG__ (TRUE or FALSE).
AnnaBridge 156:ff21514d8981 1308 */
AnnaBridge 156:ff21514d8981 1309 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
AnnaBridge 156:ff21514d8981 1310
AnnaBridge 156:ff21514d8981 1311 /**
AnnaBridge 156:ff21514d8981 1312 * @brief Clears the specified TIM interrupt flag.
AnnaBridge 156:ff21514d8981 1313 * @param __HANDLE__: specifies the TIM Handle.
AnnaBridge 156:ff21514d8981 1314 * @param __FLAG__: specifies the TIM interrupt flag to clear.
AnnaBridge 156:ff21514d8981 1315 * This parameter can be one of the following values:
AnnaBridge 156:ff21514d8981 1316 * @arg TIM_FLAG_UPDATE: Update interrupt flag
AnnaBridge 156:ff21514d8981 1317 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
AnnaBridge 156:ff21514d8981 1318 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
AnnaBridge 156:ff21514d8981 1319 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
AnnaBridge 156:ff21514d8981 1320 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
AnnaBridge 156:ff21514d8981 1321 * @arg TIM_FLAG_COM: Commutation interrupt flag
AnnaBridge 156:ff21514d8981 1322 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
AnnaBridge 156:ff21514d8981 1323 * @arg TIM_FLAG_BREAK: Break interrupt flag
AnnaBridge 156:ff21514d8981 1324 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
AnnaBridge 156:ff21514d8981 1325 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
AnnaBridge 156:ff21514d8981 1326 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
AnnaBridge 156:ff21514d8981 1327 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
AnnaBridge 156:ff21514d8981 1328 * @retval The new state of __FLAG__ (TRUE or FALSE).
AnnaBridge 156:ff21514d8981 1329 */
AnnaBridge 156:ff21514d8981 1330 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
AnnaBridge 156:ff21514d8981 1331
AnnaBridge 156:ff21514d8981 1332 /**
AnnaBridge 156:ff21514d8981 1333 * @brief Checks whether the specified TIM interrupt has occurred or not.
AnnaBridge 156:ff21514d8981 1334 * @param __HANDLE__: TIM handle
AnnaBridge 156:ff21514d8981 1335 * @param __INTERRUPT__: specifies the TIM interrupt source to check.
AnnaBridge 156:ff21514d8981 1336 * @retval The state of TIM_IT (SET or RESET).
AnnaBridge 156:ff21514d8981 1337 */
AnnaBridge 156:ff21514d8981 1338 #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
AnnaBridge 156:ff21514d8981 1339
AnnaBridge 156:ff21514d8981 1340 /**
AnnaBridge 156:ff21514d8981 1341 * @brief Clear the TIM interrupt pending bits
AnnaBridge 156:ff21514d8981 1342 * @param __HANDLE__: TIM handle
AnnaBridge 156:ff21514d8981 1343 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
AnnaBridge 156:ff21514d8981 1344 * @retval None
AnnaBridge 156:ff21514d8981 1345 */
AnnaBridge 156:ff21514d8981 1346 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
AnnaBridge 156:ff21514d8981 1347
AnnaBridge 156:ff21514d8981 1348 /**
AnnaBridge 156:ff21514d8981 1349 * @brief Indicates whether or not the TIM Counter is used as downcounter
AnnaBridge 156:ff21514d8981 1350 * @param __HANDLE__: TIM handle.
AnnaBridge 156:ff21514d8981 1351 * @retval False (Counter used as upcounter) or True (Counter used as downcounter)
AnnaBridge 156:ff21514d8981 1352 * @note This macro is particularly usefull to get the counting mode when the timer operates in Center-aligned mode or Encoder
AnnaBridge 156:ff21514d8981 1353 mode.
AnnaBridge 156:ff21514d8981 1354 */
AnnaBridge 156:ff21514d8981 1355 #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 & (TIM_CR1_DIR)) == (TIM_CR1_DIR))
AnnaBridge 156:ff21514d8981 1356
AnnaBridge 156:ff21514d8981 1357 /**
AnnaBridge 156:ff21514d8981 1358 * @brief Sets the TIM active prescaler register value on update event.
AnnaBridge 156:ff21514d8981 1359 * @param __HANDLE__: TIM handle.
AnnaBridge 156:ff21514d8981 1360 * @param __PRESC__: specifies the active prescaler register new value.
AnnaBridge 156:ff21514d8981 1361 * @retval None
AnnaBridge 156:ff21514d8981 1362 */
AnnaBridge 156:ff21514d8981 1363 #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
AnnaBridge 156:ff21514d8981 1364
AnnaBridge 156:ff21514d8981 1365 /**
AnnaBridge 156:ff21514d8981 1366 * @brief Sets the TIM Capture Compare Register value on runtime without
AnnaBridge 156:ff21514d8981 1367 * calling another time ConfigChannel function.
AnnaBridge 156:ff21514d8981 1368 * @param __HANDLE__: TIM handle.
AnnaBridge 156:ff21514d8981 1369 * @param __CHANNEL__ : TIM Channels to be configured.
AnnaBridge 156:ff21514d8981 1370 * This parameter can be one of the following values:
AnnaBridge 156:ff21514d8981 1371 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
AnnaBridge 156:ff21514d8981 1372 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
AnnaBridge 156:ff21514d8981 1373 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
AnnaBridge 156:ff21514d8981 1374 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
AnnaBridge 156:ff21514d8981 1375 * @param __COMPARE__: specifies the Capture Compare register new value.
AnnaBridge 156:ff21514d8981 1376 * @retval None
AnnaBridge 156:ff21514d8981 1377 */
AnnaBridge 156:ff21514d8981 1378 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
AnnaBridge 156:ff21514d8981 1379 (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)) = (__COMPARE__))
AnnaBridge 156:ff21514d8981 1380
AnnaBridge 156:ff21514d8981 1381 /**
AnnaBridge 156:ff21514d8981 1382 * @brief Gets the TIM Capture Compare Register value on runtime
AnnaBridge 156:ff21514d8981 1383 * @param __HANDLE__: TIM handle.
AnnaBridge 156:ff21514d8981 1384 * @param __CHANNEL__ : TIM Channel associated with the capture compare register
AnnaBridge 156:ff21514d8981 1385 * This parameter can be one of the following values:
AnnaBridge 156:ff21514d8981 1386 * @arg TIM_CHANNEL_1: get capture/compare 1 register value
AnnaBridge 156:ff21514d8981 1387 * @arg TIM_CHANNEL_2: get capture/compare 2 register value
AnnaBridge 156:ff21514d8981 1388 * @arg TIM_CHANNEL_3: get capture/compare 3 register value
AnnaBridge 156:ff21514d8981 1389 * @arg TIM_CHANNEL_4: get capture/compare 4 register value
AnnaBridge 156:ff21514d8981 1390 * @retval None
AnnaBridge 156:ff21514d8981 1391 */
AnnaBridge 156:ff21514d8981 1392 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
AnnaBridge 156:ff21514d8981 1393 (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)))
AnnaBridge 156:ff21514d8981 1394
AnnaBridge 156:ff21514d8981 1395 /**
AnnaBridge 156:ff21514d8981 1396 * @brief Sets the TIM Counter Register value on runtime.
AnnaBridge 156:ff21514d8981 1397 * @param __HANDLE__: TIM handle.
AnnaBridge 156:ff21514d8981 1398 * @param __COUNTER__: specifies the Counter register new value.
AnnaBridge 156:ff21514d8981 1399 * @retval None
AnnaBridge 156:ff21514d8981 1400 */
AnnaBridge 156:ff21514d8981 1401 #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
AnnaBridge 156:ff21514d8981 1402
AnnaBridge 156:ff21514d8981 1403 /**
AnnaBridge 156:ff21514d8981 1404 * @brief Gets the TIM Counter Register value on runtime.
AnnaBridge 156:ff21514d8981 1405 * @param __HANDLE__: TIM handle.
AnnaBridge 156:ff21514d8981 1406 * @retval None
AnnaBridge 156:ff21514d8981 1407 */
AnnaBridge 156:ff21514d8981 1408 #define __HAL_TIM_GET_COUNTER(__HANDLE__) \
AnnaBridge 156:ff21514d8981 1409 ((__HANDLE__)->Instance->CNT)
AnnaBridge 156:ff21514d8981 1410
AnnaBridge 156:ff21514d8981 1411 /**
AnnaBridge 156:ff21514d8981 1412 * @brief Sets the TIM Autoreload Register value on runtime without calling
AnnaBridge 156:ff21514d8981 1413 * another time any Init function.
AnnaBridge 156:ff21514d8981 1414 * @param __HANDLE__: TIM handle.
AnnaBridge 156:ff21514d8981 1415 * @param __AUTORELOAD__: specifies the Counter register new value.
AnnaBridge 156:ff21514d8981 1416 * @retval None
AnnaBridge 156:ff21514d8981 1417 */
AnnaBridge 156:ff21514d8981 1418 #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
AnnaBridge 156:ff21514d8981 1419 do{ \
AnnaBridge 156:ff21514d8981 1420 (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
AnnaBridge 156:ff21514d8981 1421 (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
AnnaBridge 156:ff21514d8981 1422 } while(0)
AnnaBridge 156:ff21514d8981 1423
AnnaBridge 156:ff21514d8981 1424 /**
AnnaBridge 156:ff21514d8981 1425 * @brief Gets the TIM Autoreload Register value on runtime
AnnaBridge 156:ff21514d8981 1426 * @param __HANDLE__: TIM handle.
AnnaBridge 156:ff21514d8981 1427 * @retval None
AnnaBridge 156:ff21514d8981 1428 */
AnnaBridge 156:ff21514d8981 1429 #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \
AnnaBridge 156:ff21514d8981 1430 ((__HANDLE__)->Instance->ARR)
AnnaBridge 156:ff21514d8981 1431
AnnaBridge 156:ff21514d8981 1432 /**
AnnaBridge 156:ff21514d8981 1433 * @brief Sets the TIM Clock Division value on runtime without calling
AnnaBridge 156:ff21514d8981 1434 * another time any Init function.
AnnaBridge 156:ff21514d8981 1435 * @param __HANDLE__: TIM handle.
AnnaBridge 156:ff21514d8981 1436 * @param __CKD__: specifies the clock division value.
AnnaBridge 156:ff21514d8981 1437 * This parameter can be one of the following value:
AnnaBridge 156:ff21514d8981 1438 * @arg TIM_CLOCKDIVISION_DIV1
AnnaBridge 156:ff21514d8981 1439 * @arg TIM_CLOCKDIVISION_DIV2
AnnaBridge 156:ff21514d8981 1440 * @arg TIM_CLOCKDIVISION_DIV4
AnnaBridge 156:ff21514d8981 1441 * @retval None
AnnaBridge 156:ff21514d8981 1442 */
AnnaBridge 156:ff21514d8981 1443 #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
AnnaBridge 156:ff21514d8981 1444 do{ \
AnnaBridge 156:ff21514d8981 1445 (__HANDLE__)->Instance->CR1 &= ~TIM_CR1_CKD; \
AnnaBridge 156:ff21514d8981 1446 (__HANDLE__)->Instance->CR1 |= (__CKD__); \
AnnaBridge 156:ff21514d8981 1447 (__HANDLE__)->Init.ClockDivision = (__CKD__); \
AnnaBridge 156:ff21514d8981 1448 } while(0)
AnnaBridge 156:ff21514d8981 1449
AnnaBridge 156:ff21514d8981 1450 /**
AnnaBridge 156:ff21514d8981 1451 * @brief Gets the TIM Clock Division value on runtime
AnnaBridge 156:ff21514d8981 1452 * @param __HANDLE__: TIM handle.
AnnaBridge 156:ff21514d8981 1453 * @retval None
AnnaBridge 156:ff21514d8981 1454 */
AnnaBridge 156:ff21514d8981 1455 #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \
AnnaBridge 156:ff21514d8981 1456 ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
AnnaBridge 156:ff21514d8981 1457
AnnaBridge 156:ff21514d8981 1458 /**
AnnaBridge 156:ff21514d8981 1459 * @brief Sets the TIM Output compare preload.
AnnaBridge 156:ff21514d8981 1460 * @param __HANDLE__: TIM handle.
AnnaBridge 156:ff21514d8981 1461 * @param __CHANNEL__: TIM Channels to be configured.
AnnaBridge 156:ff21514d8981 1462 * This parameter can be one of the following values:
AnnaBridge 156:ff21514d8981 1463 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
AnnaBridge 156:ff21514d8981 1464 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
AnnaBridge 156:ff21514d8981 1465 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
AnnaBridge 156:ff21514d8981 1466 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
AnnaBridge 156:ff21514d8981 1467 * @retval None
AnnaBridge 156:ff21514d8981 1468 */
AnnaBridge 156:ff21514d8981 1469 #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
AnnaBridge 156:ff21514d8981 1470 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
AnnaBridge 156:ff21514d8981 1471 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
AnnaBridge 156:ff21514d8981 1472 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
AnnaBridge 156:ff21514d8981 1473 ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE))
AnnaBridge 156:ff21514d8981 1474
AnnaBridge 156:ff21514d8981 1475 /**
AnnaBridge 156:ff21514d8981 1476 * @brief Resets the TIM Output compare preload.
AnnaBridge 156:ff21514d8981 1477 * @param __HANDLE__: TIM handle.
AnnaBridge 156:ff21514d8981 1478 * @param __CHANNEL__: TIM Channels to be configured.
AnnaBridge 156:ff21514d8981 1479 * This parameter can be one of the following values:
AnnaBridge 156:ff21514d8981 1480 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
AnnaBridge 156:ff21514d8981 1481 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
AnnaBridge 156:ff21514d8981 1482 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
AnnaBridge 156:ff21514d8981 1483 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
AnnaBridge 156:ff21514d8981 1484 * @retval None
AnnaBridge 156:ff21514d8981 1485 */
AnnaBridge 156:ff21514d8981 1486 #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
AnnaBridge 156:ff21514d8981 1487 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\
AnnaBridge 156:ff21514d8981 1488 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\
AnnaBridge 156:ff21514d8981 1489 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\
AnnaBridge 156:ff21514d8981 1490 ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE))
AnnaBridge 156:ff21514d8981 1491
AnnaBridge 156:ff21514d8981 1492
AnnaBridge 156:ff21514d8981 1493 /**
AnnaBridge 156:ff21514d8981 1494 * @brief Sets the TIM Input Capture prescaler on runtime without calling
AnnaBridge 156:ff21514d8981 1495 * another time HAL_TIM_IC_ConfigChannel() function.
AnnaBridge 156:ff21514d8981 1496 * @param __HANDLE__: TIM handle.
AnnaBridge 156:ff21514d8981 1497 * @param __CHANNEL__ : TIM Channels to be configured.
AnnaBridge 156:ff21514d8981 1498 * This parameter can be one of the following values:
AnnaBridge 156:ff21514d8981 1499 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
AnnaBridge 156:ff21514d8981 1500 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
AnnaBridge 156:ff21514d8981 1501 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
AnnaBridge 156:ff21514d8981 1502 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
AnnaBridge 156:ff21514d8981 1503 * @param __ICPSC__: specifies the Input Capture4 prescaler new value.
AnnaBridge 156:ff21514d8981 1504 * This parameter can be one of the following values:
AnnaBridge 156:ff21514d8981 1505 * @arg TIM_ICPSC_DIV1: no prescaler
AnnaBridge 156:ff21514d8981 1506 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
AnnaBridge 156:ff21514d8981 1507 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
AnnaBridge 156:ff21514d8981 1508 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
AnnaBridge 156:ff21514d8981 1509 * @retval None
AnnaBridge 156:ff21514d8981 1510 */
AnnaBridge 156:ff21514d8981 1511 #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
AnnaBridge 156:ff21514d8981 1512 do{ \
AnnaBridge 156:ff21514d8981 1513 TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
AnnaBridge 156:ff21514d8981 1514 TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
AnnaBridge 156:ff21514d8981 1515 } while(0)
AnnaBridge 156:ff21514d8981 1516
AnnaBridge 156:ff21514d8981 1517 /**
AnnaBridge 156:ff21514d8981 1518 * @brief Gets the TIM Input Capture prescaler on runtime
AnnaBridge 156:ff21514d8981 1519 * @param __HANDLE__: TIM handle.
AnnaBridge 156:ff21514d8981 1520 * @param __CHANNEL__: TIM Channels to be configured.
AnnaBridge 156:ff21514d8981 1521 * This parameter can be one of the following values:
AnnaBridge 156:ff21514d8981 1522 * @arg TIM_CHANNEL_1: get input capture 1 prescaler value
AnnaBridge 156:ff21514d8981 1523 * @arg TIM_CHANNEL_2: get input capture 2 prescaler value
AnnaBridge 156:ff21514d8981 1524 * @arg TIM_CHANNEL_3: get input capture 3 prescaler value
AnnaBridge 156:ff21514d8981 1525 * @arg TIM_CHANNEL_4: get input capture 4 prescaler value
AnnaBridge 156:ff21514d8981 1526 * @retval None
AnnaBridge 156:ff21514d8981 1527 */
AnnaBridge 156:ff21514d8981 1528 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
AnnaBridge 156:ff21514d8981 1529 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
AnnaBridge 156:ff21514d8981 1530 ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
AnnaBridge 156:ff21514d8981 1531 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
AnnaBridge 156:ff21514d8981 1532 (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
AnnaBridge 156:ff21514d8981 1533
AnnaBridge 156:ff21514d8981 1534 /**
AnnaBridge 156:ff21514d8981 1535 * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register
AnnaBridge 156:ff21514d8981 1536 * @param __HANDLE__: TIM handle.
AnnaBridge 156:ff21514d8981 1537 * @note When the USR bit of the TIMx_CR1 register is set, only counter
AnnaBridge 156:ff21514d8981 1538 * overflow/underflow generates an update interrupt or DMA request (if
AnnaBridge 156:ff21514d8981 1539 * enabled)
AnnaBridge 156:ff21514d8981 1540 * @retval None
AnnaBridge 156:ff21514d8981 1541 */
AnnaBridge 156:ff21514d8981 1542 #define __HAL_TIM_URS_ENABLE(__HANDLE__) \
AnnaBridge 156:ff21514d8981 1543 ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS))
AnnaBridge 156:ff21514d8981 1544
AnnaBridge 156:ff21514d8981 1545 /**
AnnaBridge 156:ff21514d8981 1546 * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register
AnnaBridge 156:ff21514d8981 1547 * @param __HANDLE__: TIM handle.
AnnaBridge 156:ff21514d8981 1548 * @note When the USR bit of the TIMx_CR1 register is reset, any of the
AnnaBridge 156:ff21514d8981 1549 * following events generate an update interrupt or DMA request (if
AnnaBridge 156:ff21514d8981 1550 * enabled):
AnnaBridge 156:ff21514d8981 1551 * (+) Counter overflow/underflow
AnnaBridge 156:ff21514d8981 1552 * (+) Setting the UG bit
AnnaBridge 156:ff21514d8981 1553 * (+) Update generation through the slave mode controller
AnnaBridge 156:ff21514d8981 1554 * @retval None
AnnaBridge 156:ff21514d8981 1555 */
AnnaBridge 156:ff21514d8981 1556 #define __HAL_TIM_URS_DISABLE(__HANDLE__) \
AnnaBridge 156:ff21514d8981 1557 ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
AnnaBridge 156:ff21514d8981 1558
AnnaBridge 156:ff21514d8981 1559 /**
AnnaBridge 156:ff21514d8981 1560 * @brief Sets the TIM Capture x input polarity on runtime.
AnnaBridge 156:ff21514d8981 1561 * @param __HANDLE__: TIM handle.
AnnaBridge 156:ff21514d8981 1562 * @param __CHANNEL__: TIM Channels to be configured.
AnnaBridge 156:ff21514d8981 1563 * This parameter can be one of the following values:
AnnaBridge 156:ff21514d8981 1564 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
AnnaBridge 156:ff21514d8981 1565 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
AnnaBridge 156:ff21514d8981 1566 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
AnnaBridge 156:ff21514d8981 1567 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
AnnaBridge 156:ff21514d8981 1568 * @param __POLARITY__: Polarity for TIx source
AnnaBridge 156:ff21514d8981 1569 * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
AnnaBridge 156:ff21514d8981 1570 * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
AnnaBridge 156:ff21514d8981 1571 * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
AnnaBridge 156:ff21514d8981 1572 * @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4.
AnnaBridge 156:ff21514d8981 1573 * @retval None
AnnaBridge 156:ff21514d8981 1574 */
AnnaBridge 156:ff21514d8981 1575 #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
AnnaBridge 156:ff21514d8981 1576 do{ \
AnnaBridge 156:ff21514d8981 1577 TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
AnnaBridge 156:ff21514d8981 1578 TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
AnnaBridge 156:ff21514d8981 1579 }while(0)
AnnaBridge 156:ff21514d8981 1580
AnnaBridge 156:ff21514d8981 1581 /**
AnnaBridge 156:ff21514d8981 1582 * @}
AnnaBridge 156:ff21514d8981 1583 */
AnnaBridge 156:ff21514d8981 1584
AnnaBridge 156:ff21514d8981 1585 /* Include TIM HAL Extension module */
AnnaBridge 156:ff21514d8981 1586 #include "stm32f0xx_hal_tim_ex.h"
AnnaBridge 156:ff21514d8981 1587
AnnaBridge 156:ff21514d8981 1588 /* Exported functions --------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 1589 /** @addtogroup TIM_Exported_Functions
AnnaBridge 156:ff21514d8981 1590 * @{
AnnaBridge 156:ff21514d8981 1591 */
AnnaBridge 156:ff21514d8981 1592
AnnaBridge 156:ff21514d8981 1593 /** @addtogroup TIM_Exported_Functions_Group1
AnnaBridge 156:ff21514d8981 1594 * @{
AnnaBridge 156:ff21514d8981 1595 */
AnnaBridge 156:ff21514d8981 1596 /* Time Base functions ********************************************************/
AnnaBridge 156:ff21514d8981 1597 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1598 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1599 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1600 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1601 /* Blocking mode: Polling */
AnnaBridge 156:ff21514d8981 1602 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1603 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1604 /* Non-Blocking mode: Interrupt */
AnnaBridge 156:ff21514d8981 1605 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1606 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1607 /* Non-Blocking mode: DMA */
AnnaBridge 156:ff21514d8981 1608 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
AnnaBridge 156:ff21514d8981 1609 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1610 /**
AnnaBridge 156:ff21514d8981 1611 * @}
AnnaBridge 156:ff21514d8981 1612 */
AnnaBridge 156:ff21514d8981 1613
AnnaBridge 156:ff21514d8981 1614 /** @addtogroup TIM_Exported_Functions_Group2
AnnaBridge 156:ff21514d8981 1615 * @{
AnnaBridge 156:ff21514d8981 1616 */
AnnaBridge 156:ff21514d8981 1617 /* Timer Output Compare functions **********************************************/
AnnaBridge 156:ff21514d8981 1618 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1619 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1620 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1621 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1622 /* Blocking mode: Polling */
AnnaBridge 156:ff21514d8981 1623 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 156:ff21514d8981 1624 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 156:ff21514d8981 1625 /* Non-Blocking mode: Interrupt */
AnnaBridge 156:ff21514d8981 1626 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 156:ff21514d8981 1627 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 156:ff21514d8981 1628 /* Non-Blocking mode: DMA */
AnnaBridge 156:ff21514d8981 1629 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
AnnaBridge 156:ff21514d8981 1630 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 156:ff21514d8981 1631
AnnaBridge 156:ff21514d8981 1632 /**
AnnaBridge 156:ff21514d8981 1633 * @}
AnnaBridge 156:ff21514d8981 1634 */
AnnaBridge 156:ff21514d8981 1635
AnnaBridge 156:ff21514d8981 1636 /** @addtogroup TIM_Exported_Functions_Group3
AnnaBridge 156:ff21514d8981 1637 * @{
AnnaBridge 156:ff21514d8981 1638 */
AnnaBridge 156:ff21514d8981 1639 /* Timer PWM functions *********************************************************/
AnnaBridge 156:ff21514d8981 1640 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1641 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1642 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1643 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1644 /* Blocking mode: Polling */
AnnaBridge 156:ff21514d8981 1645 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 156:ff21514d8981 1646 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 156:ff21514d8981 1647 /* Non-Blocking mode: Interrupt */
AnnaBridge 156:ff21514d8981 1648 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 156:ff21514d8981 1649 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 156:ff21514d8981 1650 /* Non-Blocking mode: DMA */
AnnaBridge 156:ff21514d8981 1651 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
AnnaBridge 156:ff21514d8981 1652 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 156:ff21514d8981 1653 /**
AnnaBridge 156:ff21514d8981 1654 * @}
AnnaBridge 156:ff21514d8981 1655 */
AnnaBridge 156:ff21514d8981 1656
AnnaBridge 156:ff21514d8981 1657 /** @addtogroup TIM_Exported_Functions_Group4
AnnaBridge 156:ff21514d8981 1658 * @{
AnnaBridge 156:ff21514d8981 1659 */
AnnaBridge 156:ff21514d8981 1660 /* Timer Input Capture functions ***********************************************/
AnnaBridge 156:ff21514d8981 1661 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1662 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1663 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1664 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1665 /* Blocking mode: Polling */
AnnaBridge 156:ff21514d8981 1666 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 156:ff21514d8981 1667 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 156:ff21514d8981 1668 /* Non-Blocking mode: Interrupt */
AnnaBridge 156:ff21514d8981 1669 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 156:ff21514d8981 1670 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 156:ff21514d8981 1671 /* Non-Blocking mode: DMA */
AnnaBridge 156:ff21514d8981 1672 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
AnnaBridge 156:ff21514d8981 1673 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 156:ff21514d8981 1674 /**
AnnaBridge 156:ff21514d8981 1675 * @}
AnnaBridge 156:ff21514d8981 1676 */
AnnaBridge 156:ff21514d8981 1677
AnnaBridge 156:ff21514d8981 1678 /** @addtogroup TIM_Exported_Functions_Group5
AnnaBridge 156:ff21514d8981 1679 * @{
AnnaBridge 156:ff21514d8981 1680 */
AnnaBridge 156:ff21514d8981 1681 /* Timer One Pulse functions ***************************************************/
AnnaBridge 156:ff21514d8981 1682 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
AnnaBridge 156:ff21514d8981 1683 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1684 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1685 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1686 /* Blocking mode: Polling */
AnnaBridge 156:ff21514d8981 1687 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
AnnaBridge 156:ff21514d8981 1688 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
AnnaBridge 156:ff21514d8981 1689 /* Non-Blocking mode: Interrupt */
AnnaBridge 156:ff21514d8981 1690 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
AnnaBridge 156:ff21514d8981 1691 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
AnnaBridge 156:ff21514d8981 1692 /**
AnnaBridge 156:ff21514d8981 1693 * @}
AnnaBridge 156:ff21514d8981 1694 */
AnnaBridge 156:ff21514d8981 1695
AnnaBridge 156:ff21514d8981 1696 /** @addtogroup TIM_Exported_Functions_Group6
AnnaBridge 156:ff21514d8981 1697 * @{
AnnaBridge 156:ff21514d8981 1698 */
AnnaBridge 156:ff21514d8981 1699 /* Timer Encoder functions *****************************************************/
AnnaBridge 156:ff21514d8981 1700 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig);
AnnaBridge 156:ff21514d8981 1701 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1702 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1703 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1704 /* Blocking mode: Polling */
AnnaBridge 156:ff21514d8981 1705 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 156:ff21514d8981 1706 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 156:ff21514d8981 1707 /* Non-Blocking mode: Interrupt */
AnnaBridge 156:ff21514d8981 1708 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 156:ff21514d8981 1709 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 156:ff21514d8981 1710 /* Non-Blocking mode: DMA */
AnnaBridge 156:ff21514d8981 1711 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
AnnaBridge 156:ff21514d8981 1712 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 156:ff21514d8981 1713
AnnaBridge 156:ff21514d8981 1714 /**
AnnaBridge 156:ff21514d8981 1715 * @}
AnnaBridge 156:ff21514d8981 1716 */
AnnaBridge 156:ff21514d8981 1717
AnnaBridge 156:ff21514d8981 1718 /** @addtogroup TIM_Exported_Functions_Group7
AnnaBridge 156:ff21514d8981 1719 * @{
AnnaBridge 156:ff21514d8981 1720 */
AnnaBridge 156:ff21514d8981 1721 /* Interrupt Handler functions **********************************************/
AnnaBridge 156:ff21514d8981 1722 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1723 /**
AnnaBridge 156:ff21514d8981 1724 * @}
AnnaBridge 156:ff21514d8981 1725 */
AnnaBridge 156:ff21514d8981 1726
AnnaBridge 156:ff21514d8981 1727 /** @addtogroup TIM_Exported_Functions_Group8
AnnaBridge 156:ff21514d8981 1728 * @{
AnnaBridge 156:ff21514d8981 1729 */
AnnaBridge 156:ff21514d8981 1730 /* Control functions *********************************************************/
AnnaBridge 156:ff21514d8981 1731 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
AnnaBridge 156:ff21514d8981 1732 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
AnnaBridge 156:ff21514d8981 1733 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel);
AnnaBridge 156:ff21514d8981 1734 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel);
AnnaBridge 156:ff21514d8981 1735 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel);
AnnaBridge 156:ff21514d8981 1736 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig);
AnnaBridge 156:ff21514d8981 1737 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
AnnaBridge 156:ff21514d8981 1738 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
AnnaBridge 156:ff21514d8981 1739 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
AnnaBridge 156:ff21514d8981 1740 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
AnnaBridge 156:ff21514d8981 1741 uint32_t *BurstBuffer, uint32_t BurstLength);
AnnaBridge 156:ff21514d8981 1742 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
AnnaBridge 156:ff21514d8981 1743 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
AnnaBridge 156:ff21514d8981 1744 uint32_t *BurstBuffer, uint32_t BurstLength);
AnnaBridge 156:ff21514d8981 1745 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
AnnaBridge 156:ff21514d8981 1746 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
AnnaBridge 156:ff21514d8981 1747 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 156:ff21514d8981 1748
AnnaBridge 156:ff21514d8981 1749 /**
AnnaBridge 156:ff21514d8981 1750 * @}
AnnaBridge 156:ff21514d8981 1751 */
AnnaBridge 156:ff21514d8981 1752
AnnaBridge 156:ff21514d8981 1753 /** @addtogroup TIM_Exported_Functions_Group9
AnnaBridge 156:ff21514d8981 1754 * @{
AnnaBridge 156:ff21514d8981 1755 */
AnnaBridge 156:ff21514d8981 1756 /* Callback in non blocking modes (Interrupt and DMA) *************************/
AnnaBridge 156:ff21514d8981 1757 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1758 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1759 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1760 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1761 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1762 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1763 /**
AnnaBridge 156:ff21514d8981 1764 * @}
AnnaBridge 156:ff21514d8981 1765 */
AnnaBridge 156:ff21514d8981 1766
AnnaBridge 156:ff21514d8981 1767 /** @addtogroup TIM_Exported_Functions_Group10
AnnaBridge 156:ff21514d8981 1768 * @{
AnnaBridge 156:ff21514d8981 1769 */
AnnaBridge 156:ff21514d8981 1770 /* Peripheral State functions **************************************************/
AnnaBridge 156:ff21514d8981 1771 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1772 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1773 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1774 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1775 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1776 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
AnnaBridge 156:ff21514d8981 1777
AnnaBridge 156:ff21514d8981 1778 /**
AnnaBridge 156:ff21514d8981 1779 * @}
AnnaBridge 156:ff21514d8981 1780 */
AnnaBridge 156:ff21514d8981 1781
AnnaBridge 156:ff21514d8981 1782 /**
AnnaBridge 156:ff21514d8981 1783 * @}
AnnaBridge 156:ff21514d8981 1784 */
AnnaBridge 156:ff21514d8981 1785
AnnaBridge 156:ff21514d8981 1786 /* Private Functions --------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 1787 /** @addtogroup TIM_Private_Functions
AnnaBridge 156:ff21514d8981 1788 * @{
AnnaBridge 156:ff21514d8981 1789 */
AnnaBridge 156:ff21514d8981 1790 void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
AnnaBridge 156:ff21514d8981 1791 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
AnnaBridge 156:ff21514d8981 1792 /**
AnnaBridge 156:ff21514d8981 1793 * @}
AnnaBridge 156:ff21514d8981 1794 */
AnnaBridge 156:ff21514d8981 1795
AnnaBridge 156:ff21514d8981 1796 /**
AnnaBridge 156:ff21514d8981 1797 * @}
AnnaBridge 156:ff21514d8981 1798 */
AnnaBridge 156:ff21514d8981 1799
AnnaBridge 156:ff21514d8981 1800 /**
AnnaBridge 156:ff21514d8981 1801 * @}
AnnaBridge 156:ff21514d8981 1802 */
AnnaBridge 156:ff21514d8981 1803
AnnaBridge 156:ff21514d8981 1804 #ifdef __cplusplus
AnnaBridge 156:ff21514d8981 1805 }
AnnaBridge 156:ff21514d8981 1806 #endif
AnnaBridge 156:ff21514d8981 1807
AnnaBridge 156:ff21514d8981 1808 #endif /* __STM32F0xx_HAL_TIM_H */
AnnaBridge 156:ff21514d8981 1809
AnnaBridge 156:ff21514d8981 1810 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/