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TARGET_DISCO_L476VG/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_rcc_ex.h@157:e7ca05fa8600, 2017-11-09 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 09 11:14:10 2017 +0000
Revision:
157:e7ca05fa8600
Parent:
156:ff21514d8981
Child:
161:aa5281ff4a02
Release 155 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 156:ff21514d8981 1 /**
AnnaBridge 156:ff21514d8981 2 ******************************************************************************
AnnaBridge 156:ff21514d8981 3 * @file stm32l4xx_hal_rcc_ex.h
AnnaBridge 156:ff21514d8981 4 * @author MCD Application Team
AnnaBridge 156:ff21514d8981 5 * @version V1.7.1
AnnaBridge 156:ff21514d8981 6 * @date 21-April-2017
AnnaBridge 156:ff21514d8981 7 * @brief Header file of RCC HAL Extended module.
AnnaBridge 156:ff21514d8981 8 ******************************************************************************
AnnaBridge 156:ff21514d8981 9 * @attention
AnnaBridge 156:ff21514d8981 10 *
AnnaBridge 156:ff21514d8981 11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge 156:ff21514d8981 12 *
AnnaBridge 156:ff21514d8981 13 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 156:ff21514d8981 14 * are permitted provided that the following conditions are met:
AnnaBridge 156:ff21514d8981 15 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 156:ff21514d8981 16 * this list of conditions and the following disclaimer.
AnnaBridge 156:ff21514d8981 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 156:ff21514d8981 18 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 156:ff21514d8981 19 * and/or other materials provided with the distribution.
AnnaBridge 156:ff21514d8981 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 156:ff21514d8981 21 * may be used to endorse or promote products derived from this software
AnnaBridge 156:ff21514d8981 22 * without specific prior written permission.
AnnaBridge 156:ff21514d8981 23 *
AnnaBridge 156:ff21514d8981 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 156:ff21514d8981 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 156:ff21514d8981 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 156:ff21514d8981 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 156:ff21514d8981 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 156:ff21514d8981 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 156:ff21514d8981 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 156:ff21514d8981 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 156:ff21514d8981 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 156:ff21514d8981 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 156:ff21514d8981 34 *
AnnaBridge 156:ff21514d8981 35 ******************************************************************************
AnnaBridge 156:ff21514d8981 36 */
AnnaBridge 156:ff21514d8981 37
AnnaBridge 156:ff21514d8981 38 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 156:ff21514d8981 39 #ifndef __STM32L4xx_HAL_RCC_EX_H
AnnaBridge 156:ff21514d8981 40 #define __STM32L4xx_HAL_RCC_EX_H
AnnaBridge 156:ff21514d8981 41
AnnaBridge 156:ff21514d8981 42 #ifdef __cplusplus
AnnaBridge 156:ff21514d8981 43 extern "C" {
AnnaBridge 156:ff21514d8981 44 #endif
AnnaBridge 156:ff21514d8981 45
AnnaBridge 156:ff21514d8981 46 /* Includes ------------------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 47 #include "stm32l4xx_hal_def.h"
AnnaBridge 156:ff21514d8981 48
AnnaBridge 156:ff21514d8981 49 /** @addtogroup STM32L4xx_HAL_Driver
AnnaBridge 156:ff21514d8981 50 * @{
AnnaBridge 156:ff21514d8981 51 */
AnnaBridge 156:ff21514d8981 52
AnnaBridge 156:ff21514d8981 53 /** @addtogroup RCCEx
AnnaBridge 156:ff21514d8981 54 * @{
AnnaBridge 156:ff21514d8981 55 */
AnnaBridge 156:ff21514d8981 56
AnnaBridge 156:ff21514d8981 57 /* Exported types ------------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 58
AnnaBridge 156:ff21514d8981 59 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types
AnnaBridge 156:ff21514d8981 60 * @{
AnnaBridge 156:ff21514d8981 61 */
AnnaBridge 156:ff21514d8981 62
AnnaBridge 156:ff21514d8981 63 /**
AnnaBridge 156:ff21514d8981 64 * @brief PLLSAI1 Clock structure definition
AnnaBridge 156:ff21514d8981 65 */
AnnaBridge 156:ff21514d8981 66 typedef struct
AnnaBridge 156:ff21514d8981 67 {
AnnaBridge 156:ff21514d8981 68
AnnaBridge 156:ff21514d8981 69 uint32_t PLLSAI1Source; /*!< PLLSAI1Source: PLLSAI1 entry clock source.
AnnaBridge 156:ff21514d8981 70 This parameter must be a value of @ref RCC_PLL_Clock_Source */
AnnaBridge 156:ff21514d8981 71
AnnaBridge 156:ff21514d8981 72 uint32_t PLLSAI1M; /*!< PLLSAI1M: specifies the division factor for PLLSAI1 input clock.
AnnaBridge 156:ff21514d8981 73 This parameter must be a number between Min_Data = 1 and Max_Data = 8 */
AnnaBridge 156:ff21514d8981 74
AnnaBridge 156:ff21514d8981 75 uint32_t PLLSAI1N; /*!< PLLSAI1N: specifies the multiplication factor for PLLSAI1 VCO output clock.
AnnaBridge 156:ff21514d8981 76 This parameter must be a number between 8 and 86 or 127 depending on devices. */
AnnaBridge 156:ff21514d8981 77
AnnaBridge 156:ff21514d8981 78 uint32_t PLLSAI1P; /*!< PLLSAI1P: specifies the division factor for SAI clock.
AnnaBridge 156:ff21514d8981 79 This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
AnnaBridge 156:ff21514d8981 80
AnnaBridge 156:ff21514d8981 81 uint32_t PLLSAI1Q; /*!< PLLSAI1Q: specifies the division factor for USB/RNG/SDMMC1 clock.
AnnaBridge 156:ff21514d8981 82 This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */
AnnaBridge 156:ff21514d8981 83
AnnaBridge 156:ff21514d8981 84 uint32_t PLLSAI1R; /*!< PLLSAI1R: specifies the division factor for ADC clock.
AnnaBridge 156:ff21514d8981 85 This parameter must be a value of @ref RCC_PLLR_Clock_Divider */
AnnaBridge 156:ff21514d8981 86
AnnaBridge 156:ff21514d8981 87 uint32_t PLLSAI1ClockOut; /*!< PLLSAIClockOut: specifies PLLSAI1 output clock to be enabled.
AnnaBridge 156:ff21514d8981 88 This parameter must be a value of @ref RCC_PLLSAI1_Clock_Output */
AnnaBridge 156:ff21514d8981 89 }RCC_PLLSAI1InitTypeDef;
AnnaBridge 156:ff21514d8981 90
AnnaBridge 156:ff21514d8981 91 #if defined(RCC_PLLSAI2_SUPPORT)
AnnaBridge 156:ff21514d8981 92
AnnaBridge 156:ff21514d8981 93 /**
AnnaBridge 156:ff21514d8981 94 * @brief PLLSAI2 Clock structure definition
AnnaBridge 156:ff21514d8981 95 */
AnnaBridge 156:ff21514d8981 96 typedef struct
AnnaBridge 156:ff21514d8981 97 {
AnnaBridge 156:ff21514d8981 98
AnnaBridge 156:ff21514d8981 99 uint32_t PLLSAI2Source; /*!< PLLSAI2Source: PLLSAI2 entry clock source.
AnnaBridge 156:ff21514d8981 100 This parameter must be a value of @ref RCC_PLL_Clock_Source */
AnnaBridge 156:ff21514d8981 101
AnnaBridge 156:ff21514d8981 102 uint32_t PLLSAI2M; /*!< PLLSAI2M: specifies the division factor for PLLSAI2 input clock.
AnnaBridge 156:ff21514d8981 103 This parameter must be a number between Min_Data = 1 and Max_Data = 8 */
AnnaBridge 156:ff21514d8981 104
AnnaBridge 156:ff21514d8981 105 uint32_t PLLSAI2N; /*!< PLLSAI2N: specifies the multiplication factor for PLLSAI2 VCO output clock.
AnnaBridge 156:ff21514d8981 106 This parameter must be a number between 8 and 86 or 127 depending on devices. */
AnnaBridge 156:ff21514d8981 107
AnnaBridge 156:ff21514d8981 108 uint32_t PLLSAI2P; /*!< PLLSAI2P: specifies the division factor for SAI clock.
AnnaBridge 156:ff21514d8981 109 This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
AnnaBridge 156:ff21514d8981 110
AnnaBridge 156:ff21514d8981 111 uint32_t PLLSAI2R; /*!< PLLSAI2R: specifies the division factor for ADC clock.
AnnaBridge 156:ff21514d8981 112 This parameter must be a value of @ref RCC_PLLR_Clock_Divider */
AnnaBridge 156:ff21514d8981 113
AnnaBridge 156:ff21514d8981 114 uint32_t PLLSAI2ClockOut; /*!< PLLSAIClockOut: specifies PLLSAI2 output clock to be enabled.
AnnaBridge 156:ff21514d8981 115 This parameter must be a value of @ref RCC_PLLSAI2_Clock_Output */
AnnaBridge 156:ff21514d8981 116 }RCC_PLLSAI2InitTypeDef;
AnnaBridge 156:ff21514d8981 117
AnnaBridge 156:ff21514d8981 118 #endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge 156:ff21514d8981 119
AnnaBridge 156:ff21514d8981 120 /**
AnnaBridge 156:ff21514d8981 121 * @brief RCC extended clocks structure definition
AnnaBridge 156:ff21514d8981 122 */
AnnaBridge 156:ff21514d8981 123 typedef struct
AnnaBridge 156:ff21514d8981 124 {
AnnaBridge 156:ff21514d8981 125 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
AnnaBridge 156:ff21514d8981 126 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
AnnaBridge 156:ff21514d8981 127
AnnaBridge 156:ff21514d8981 128 RCC_PLLSAI1InitTypeDef PLLSAI1; /*!< PLLSAI1 structure parameters.
AnnaBridge 156:ff21514d8981 129 This parameter will be used only when PLLSAI1 is selected as Clock Source for SAI1, USB/RNG/SDMMC1 or ADC */
AnnaBridge 156:ff21514d8981 130
AnnaBridge 156:ff21514d8981 131 #if defined(RCC_PLLSAI2_SUPPORT)
AnnaBridge 156:ff21514d8981 132
AnnaBridge 156:ff21514d8981 133 RCC_PLLSAI2InitTypeDef PLLSAI2; /*!< PLLSAI2 structure parameters.
AnnaBridge 156:ff21514d8981 134 This parameter will be used only when PLLSAI2 is selected as Clock Source for SAI2 or ADC */
AnnaBridge 156:ff21514d8981 135
AnnaBridge 156:ff21514d8981 136 #endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge 156:ff21514d8981 137
AnnaBridge 156:ff21514d8981 138 uint32_t Usart1ClockSelection; /*!< Specifies USART1 clock source.
AnnaBridge 156:ff21514d8981 139 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
AnnaBridge 156:ff21514d8981 140
AnnaBridge 156:ff21514d8981 141 uint32_t Usart2ClockSelection; /*!< Specifies USART2 clock source.
AnnaBridge 156:ff21514d8981 142 This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
AnnaBridge 156:ff21514d8981 143
AnnaBridge 156:ff21514d8981 144 #if defined(USART3)
AnnaBridge 156:ff21514d8981 145
AnnaBridge 156:ff21514d8981 146 uint32_t Usart3ClockSelection; /*!< Specifies USART3 clock source.
AnnaBridge 156:ff21514d8981 147 This parameter can be a value of @ref RCCEx_USART3_Clock_Source */
AnnaBridge 156:ff21514d8981 148
AnnaBridge 156:ff21514d8981 149 #endif /* USART3 */
AnnaBridge 156:ff21514d8981 150
AnnaBridge 156:ff21514d8981 151 #if defined(UART4)
AnnaBridge 156:ff21514d8981 152
AnnaBridge 156:ff21514d8981 153 uint32_t Uart4ClockSelection; /*!< Specifies UART4 clock source.
AnnaBridge 156:ff21514d8981 154 This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
AnnaBridge 156:ff21514d8981 155
AnnaBridge 156:ff21514d8981 156 #endif /* UART4 */
AnnaBridge 156:ff21514d8981 157
AnnaBridge 156:ff21514d8981 158 #if defined(UART5)
AnnaBridge 156:ff21514d8981 159
AnnaBridge 156:ff21514d8981 160 uint32_t Uart5ClockSelection; /*!< Specifies UART5 clock source.
AnnaBridge 156:ff21514d8981 161 This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
AnnaBridge 156:ff21514d8981 162
AnnaBridge 156:ff21514d8981 163 #endif /* UART5 */
AnnaBridge 156:ff21514d8981 164
AnnaBridge 156:ff21514d8981 165 uint32_t Lpuart1ClockSelection; /*!< Specifies LPUART1 clock source.
AnnaBridge 156:ff21514d8981 166 This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */
AnnaBridge 156:ff21514d8981 167
AnnaBridge 156:ff21514d8981 168 uint32_t I2c1ClockSelection; /*!< Specifies I2C1 clock source.
AnnaBridge 156:ff21514d8981 169 This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */
AnnaBridge 156:ff21514d8981 170
AnnaBridge 156:ff21514d8981 171 #if defined(I2C2)
AnnaBridge 156:ff21514d8981 172
AnnaBridge 156:ff21514d8981 173 uint32_t I2c2ClockSelection; /*!< Specifies I2C2 clock source.
AnnaBridge 156:ff21514d8981 174 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
AnnaBridge 156:ff21514d8981 175
AnnaBridge 156:ff21514d8981 176 #endif /* I2C2 */
AnnaBridge 156:ff21514d8981 177
AnnaBridge 156:ff21514d8981 178 uint32_t I2c3ClockSelection; /*!< Specifies I2C3 clock source.
AnnaBridge 156:ff21514d8981 179 This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
AnnaBridge 156:ff21514d8981 180
AnnaBridge 156:ff21514d8981 181 #if defined(I2C4)
AnnaBridge 156:ff21514d8981 182
AnnaBridge 156:ff21514d8981 183 uint32_t I2c4ClockSelection; /*!< Specifies I2C4 clock source.
AnnaBridge 156:ff21514d8981 184 This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */
AnnaBridge 156:ff21514d8981 185
AnnaBridge 156:ff21514d8981 186 #endif /* I2C4 */
AnnaBridge 156:ff21514d8981 187
AnnaBridge 156:ff21514d8981 188 uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source.
AnnaBridge 156:ff21514d8981 189 This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
AnnaBridge 156:ff21514d8981 190
AnnaBridge 156:ff21514d8981 191 uint32_t Lptim2ClockSelection; /*!< Specifies LPTIM2 clock source.
AnnaBridge 156:ff21514d8981 192 This parameter can be a value of @ref RCCEx_LPTIM2_Clock_Source */
AnnaBridge 156:ff21514d8981 193
AnnaBridge 156:ff21514d8981 194 uint32_t Sai1ClockSelection; /*!< Specifies SAI1 clock source.
AnnaBridge 156:ff21514d8981 195 This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */
AnnaBridge 156:ff21514d8981 196
AnnaBridge 156:ff21514d8981 197 #if defined(SAI2)
AnnaBridge 156:ff21514d8981 198
AnnaBridge 156:ff21514d8981 199 uint32_t Sai2ClockSelection; /*!< Specifies SAI2 clock source.
AnnaBridge 156:ff21514d8981 200 This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */
AnnaBridge 156:ff21514d8981 201
AnnaBridge 156:ff21514d8981 202 #endif /* SAI2 */
AnnaBridge 156:ff21514d8981 203
AnnaBridge 156:ff21514d8981 204 #if defined(USB_OTG_FS) || defined(USB)
AnnaBridge 156:ff21514d8981 205
AnnaBridge 156:ff21514d8981 206 uint32_t UsbClockSelection; /*!< Specifies USB clock source (warning: same source for SDMMC1 and RNG).
AnnaBridge 156:ff21514d8981 207 This parameter can be a value of @ref RCCEx_USB_Clock_Source */
AnnaBridge 156:ff21514d8981 208
AnnaBridge 156:ff21514d8981 209 #endif /* USB_OTG_FS || USB */
AnnaBridge 156:ff21514d8981 210
AnnaBridge 156:ff21514d8981 211 #if defined(SDMMC1)
AnnaBridge 156:ff21514d8981 212
AnnaBridge 156:ff21514d8981 213 uint32_t Sdmmc1ClockSelection; /*!< Specifies SDMMC1 clock source (warning: same source for USB and RNG).
AnnaBridge 156:ff21514d8981 214 This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */
AnnaBridge 156:ff21514d8981 215
AnnaBridge 156:ff21514d8981 216 #endif /* SDMMC1 */
AnnaBridge 156:ff21514d8981 217
AnnaBridge 156:ff21514d8981 218 uint32_t RngClockSelection; /*!< Specifies RNG clock source (warning: same source for USB and SDMMC1).
AnnaBridge 156:ff21514d8981 219 This parameter can be a value of @ref RCCEx_RNG_Clock_Source */
AnnaBridge 156:ff21514d8981 220
AnnaBridge 156:ff21514d8981 221 uint32_t AdcClockSelection; /*!< Specifies ADC interface clock source.
AnnaBridge 156:ff21514d8981 222 This parameter can be a value of @ref RCCEx_ADC_Clock_Source */
AnnaBridge 156:ff21514d8981 223
AnnaBridge 156:ff21514d8981 224 #if defined(SWPMI1)
AnnaBridge 156:ff21514d8981 225
AnnaBridge 156:ff21514d8981 226 uint32_t Swpmi1ClockSelection; /*!< Specifies SWPMI1 clock source.
AnnaBridge 156:ff21514d8981 227 This parameter can be a value of @ref RCCEx_SWPMI1_Clock_Source */
AnnaBridge 156:ff21514d8981 228
AnnaBridge 156:ff21514d8981 229 #endif /* SWPMI1 */
AnnaBridge 156:ff21514d8981 230
AnnaBridge 156:ff21514d8981 231 #if defined(DFSDM1_Filter0)
AnnaBridge 156:ff21514d8981 232
AnnaBridge 156:ff21514d8981 233 uint32_t Dfsdm1ClockSelection; /*!< Specifies DFSDM1 clock source.
AnnaBridge 156:ff21514d8981 234 This parameter can be a value of @ref RCCEx_DFSDM1_Clock_Source */
AnnaBridge 156:ff21514d8981 235
AnnaBridge 156:ff21514d8981 236 #endif /* DFSDM1_Filter0 */
AnnaBridge 156:ff21514d8981 237
AnnaBridge 156:ff21514d8981 238 uint32_t RTCClockSelection; /*!< Specifies RTC clock source.
AnnaBridge 156:ff21514d8981 239 This parameter can be a value of @ref RCC_RTC_Clock_Source */
AnnaBridge 156:ff21514d8981 240 }RCC_PeriphCLKInitTypeDef;
AnnaBridge 156:ff21514d8981 241
AnnaBridge 156:ff21514d8981 242 #if defined(CRS)
AnnaBridge 156:ff21514d8981 243
AnnaBridge 156:ff21514d8981 244 /**
AnnaBridge 156:ff21514d8981 245 * @brief RCC_CRS Init structure definition
AnnaBridge 156:ff21514d8981 246 */
AnnaBridge 156:ff21514d8981 247 typedef struct
AnnaBridge 156:ff21514d8981 248 {
AnnaBridge 156:ff21514d8981 249 uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal.
AnnaBridge 156:ff21514d8981 250 This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */
AnnaBridge 156:ff21514d8981 251
AnnaBridge 156:ff21514d8981 252 uint32_t Source; /*!< Specifies the SYNC signal source.
AnnaBridge 156:ff21514d8981 253 This parameter can be a value of @ref RCCEx_CRS_SynchroSource */
AnnaBridge 156:ff21514d8981 254
AnnaBridge 156:ff21514d8981 255 uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source.
AnnaBridge 156:ff21514d8981 256 This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */
AnnaBridge 156:ff21514d8981 257
AnnaBridge 156:ff21514d8981 258 uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event.
AnnaBridge 156:ff21514d8981 259 It can be calculated in using macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__)
AnnaBridge 156:ff21514d8981 260 This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/
AnnaBridge 156:ff21514d8981 261
AnnaBridge 156:ff21514d8981 262 uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value.
AnnaBridge 156:ff21514d8981 263 This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */
AnnaBridge 156:ff21514d8981 264
AnnaBridge 156:ff21514d8981 265 uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator.
AnnaBridge 156:ff21514d8981 266 This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */
AnnaBridge 156:ff21514d8981 267
AnnaBridge 156:ff21514d8981 268 }RCC_CRSInitTypeDef;
AnnaBridge 156:ff21514d8981 269
AnnaBridge 156:ff21514d8981 270 /**
AnnaBridge 156:ff21514d8981 271 * @brief RCC_CRS Synchronization structure definition
AnnaBridge 156:ff21514d8981 272 */
AnnaBridge 156:ff21514d8981 273 typedef struct
AnnaBridge 156:ff21514d8981 274 {
AnnaBridge 156:ff21514d8981 275 uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value.
AnnaBridge 156:ff21514d8981 276 This parameter must be a number between 0 and 0xFFFF */
AnnaBridge 156:ff21514d8981 277
AnnaBridge 156:ff21514d8981 278 uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming.
AnnaBridge 156:ff21514d8981 279 This parameter must be a number between 0 and 0x3F */
AnnaBridge 156:ff21514d8981 280
AnnaBridge 156:ff21514d8981 281 uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter
AnnaBridge 156:ff21514d8981 282 value latched in the time of the last SYNC event.
AnnaBridge 156:ff21514d8981 283 This parameter must be a number between 0 and 0xFFFF */
AnnaBridge 156:ff21514d8981 284
AnnaBridge 156:ff21514d8981 285 uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the
AnnaBridge 156:ff21514d8981 286 frequency error counter latched in the time of the last SYNC event.
AnnaBridge 156:ff21514d8981 287 It shows whether the actual frequency is below or above the target.
AnnaBridge 156:ff21514d8981 288 This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/
AnnaBridge 156:ff21514d8981 289
AnnaBridge 156:ff21514d8981 290 }RCC_CRSSynchroInfoTypeDef;
AnnaBridge 156:ff21514d8981 291
AnnaBridge 156:ff21514d8981 292 #endif /* CRS */
AnnaBridge 156:ff21514d8981 293 /**
AnnaBridge 156:ff21514d8981 294 * @}
AnnaBridge 156:ff21514d8981 295 */
AnnaBridge 156:ff21514d8981 296
AnnaBridge 156:ff21514d8981 297 /* Exported constants --------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 298 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
AnnaBridge 156:ff21514d8981 299 * @{
AnnaBridge 156:ff21514d8981 300 */
AnnaBridge 156:ff21514d8981 301
AnnaBridge 156:ff21514d8981 302 /** @defgroup RCCEx_LSCO_Clock_Source Low Speed Clock Source
AnnaBridge 156:ff21514d8981 303 * @{
AnnaBridge 156:ff21514d8981 304 */
AnnaBridge 156:ff21514d8981 305 #define RCC_LSCOSOURCE_LSI (uint32_t)0x00000000U /*!< LSI selection for low speed clock output */
AnnaBridge 156:ff21514d8981 306 #define RCC_LSCOSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock output */
AnnaBridge 156:ff21514d8981 307 /**
AnnaBridge 156:ff21514d8981 308 * @}
AnnaBridge 156:ff21514d8981 309 */
AnnaBridge 156:ff21514d8981 310
AnnaBridge 156:ff21514d8981 311 /** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection
AnnaBridge 156:ff21514d8981 312 * @{
AnnaBridge 156:ff21514d8981 313 */
AnnaBridge 156:ff21514d8981 314 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001U)
AnnaBridge 156:ff21514d8981 315 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002U)
AnnaBridge 156:ff21514d8981 316 #if defined(USART3)
AnnaBridge 156:ff21514d8981 317 #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004U)
AnnaBridge 156:ff21514d8981 318 #endif
AnnaBridge 156:ff21514d8981 319 #if defined(UART4)
AnnaBridge 156:ff21514d8981 320 #define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008U)
AnnaBridge 156:ff21514d8981 321 #endif
AnnaBridge 156:ff21514d8981 322 #if defined(UART5)
AnnaBridge 156:ff21514d8981 323 #define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010U)
AnnaBridge 156:ff21514d8981 324 #endif
AnnaBridge 156:ff21514d8981 325 #define RCC_PERIPHCLK_LPUART1 ((uint32_t)0x00000020U)
AnnaBridge 156:ff21514d8981 326 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000040U)
AnnaBridge 156:ff21514d8981 327 #if defined(I2C2)
AnnaBridge 156:ff21514d8981 328 #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000080U)
AnnaBridge 156:ff21514d8981 329 #endif
AnnaBridge 156:ff21514d8981 330 #define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00000100U)
AnnaBridge 156:ff21514d8981 331 #define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00000200U)
AnnaBridge 156:ff21514d8981 332 #define RCC_PERIPHCLK_LPTIM2 ((uint32_t)0x00000400U)
AnnaBridge 156:ff21514d8981 333 #define RCC_PERIPHCLK_SAI1 ((uint32_t)0x00000800U)
AnnaBridge 156:ff21514d8981 334 #if defined(SAI2)
AnnaBridge 156:ff21514d8981 335 #define RCC_PERIPHCLK_SAI2 ((uint32_t)0x00001000U)
AnnaBridge 156:ff21514d8981 336 #endif
AnnaBridge 156:ff21514d8981 337 #if defined(USB_OTG_FS) || defined(USB)
AnnaBridge 156:ff21514d8981 338 #define RCC_PERIPHCLK_USB ((uint32_t)0x00002000U)
AnnaBridge 156:ff21514d8981 339 #endif
AnnaBridge 156:ff21514d8981 340 #define RCC_PERIPHCLK_ADC ((uint32_t)0x00004000U)
AnnaBridge 156:ff21514d8981 341 #if defined(SWPMI1)
AnnaBridge 156:ff21514d8981 342 #define RCC_PERIPHCLK_SWPMI1 ((uint32_t)0x00008000U)
AnnaBridge 156:ff21514d8981 343 #endif
AnnaBridge 156:ff21514d8981 344 #if defined(DFSDM1_Filter0)
AnnaBridge 156:ff21514d8981 345 #define RCC_PERIPHCLK_DFSDM1 ((uint32_t)0x00010000U)
AnnaBridge 156:ff21514d8981 346 #endif
AnnaBridge 156:ff21514d8981 347 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00020000U)
AnnaBridge 156:ff21514d8981 348 #define RCC_PERIPHCLK_RNG ((uint32_t)0x00040000U)
AnnaBridge 156:ff21514d8981 349 #if defined(SDMMC1)
AnnaBridge 156:ff21514d8981 350 #define RCC_PERIPHCLK_SDMMC1 ((uint32_t)0x00080000U)
AnnaBridge 156:ff21514d8981 351 #endif
AnnaBridge 156:ff21514d8981 352 #if defined(I2C4)
AnnaBridge 156:ff21514d8981 353 #define RCC_PERIPHCLK_I2C4 ((uint32_t)0x00100000U)
AnnaBridge 156:ff21514d8981 354 #endif
AnnaBridge 156:ff21514d8981 355 /**
AnnaBridge 156:ff21514d8981 356 * @}
AnnaBridge 156:ff21514d8981 357 */
AnnaBridge 156:ff21514d8981 358
AnnaBridge 156:ff21514d8981 359
AnnaBridge 156:ff21514d8981 360 /** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source
AnnaBridge 156:ff21514d8981 361 * @{
AnnaBridge 156:ff21514d8981 362 */
AnnaBridge 156:ff21514d8981 363 #define RCC_USART1CLKSOURCE_PCLK2 ((uint32_t)0x00000000U)
AnnaBridge 156:ff21514d8981 364 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0
AnnaBridge 156:ff21514d8981 365 #define RCC_USART1CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1
AnnaBridge 156:ff21514d8981 366 #define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1)
AnnaBridge 156:ff21514d8981 367 /**
AnnaBridge 156:ff21514d8981 368 * @}
AnnaBridge 156:ff21514d8981 369 */
AnnaBridge 156:ff21514d8981 370
AnnaBridge 156:ff21514d8981 371 /** @defgroup RCCEx_USART2_Clock_Source USART2 Clock Source
AnnaBridge 156:ff21514d8981 372 * @{
AnnaBridge 156:ff21514d8981 373 */
AnnaBridge 156:ff21514d8981 374 #define RCC_USART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
AnnaBridge 156:ff21514d8981 375 #define RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR_USART2SEL_0
AnnaBridge 156:ff21514d8981 376 #define RCC_USART2CLKSOURCE_HSI RCC_CCIPR_USART2SEL_1
AnnaBridge 156:ff21514d8981 377 #define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR_USART2SEL_0 | RCC_CCIPR_USART2SEL_1)
AnnaBridge 156:ff21514d8981 378 /**
AnnaBridge 156:ff21514d8981 379 * @}
AnnaBridge 156:ff21514d8981 380 */
AnnaBridge 156:ff21514d8981 381
AnnaBridge 156:ff21514d8981 382 #if defined(USART3)
AnnaBridge 156:ff21514d8981 383 /** @defgroup RCCEx_USART3_Clock_Source USART3 Clock Source
AnnaBridge 156:ff21514d8981 384 * @{
AnnaBridge 156:ff21514d8981 385 */
AnnaBridge 156:ff21514d8981 386 #define RCC_USART3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
AnnaBridge 156:ff21514d8981 387 #define RCC_USART3CLKSOURCE_SYSCLK RCC_CCIPR_USART3SEL_0
AnnaBridge 156:ff21514d8981 388 #define RCC_USART3CLKSOURCE_HSI RCC_CCIPR_USART3SEL_1
AnnaBridge 156:ff21514d8981 389 #define RCC_USART3CLKSOURCE_LSE (RCC_CCIPR_USART3SEL_0 | RCC_CCIPR_USART3SEL_1)
AnnaBridge 156:ff21514d8981 390 /**
AnnaBridge 156:ff21514d8981 391 * @}
AnnaBridge 156:ff21514d8981 392 */
AnnaBridge 156:ff21514d8981 393 #endif /* USART3 */
AnnaBridge 156:ff21514d8981 394
AnnaBridge 156:ff21514d8981 395 #if defined(UART4)
AnnaBridge 156:ff21514d8981 396 /** @defgroup RCCEx_UART4_Clock_Source UART4 Clock Source
AnnaBridge 156:ff21514d8981 397 * @{
AnnaBridge 156:ff21514d8981 398 */
AnnaBridge 156:ff21514d8981 399 #define RCC_UART4CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
AnnaBridge 156:ff21514d8981 400 #define RCC_UART4CLKSOURCE_SYSCLK RCC_CCIPR_UART4SEL_0
AnnaBridge 156:ff21514d8981 401 #define RCC_UART4CLKSOURCE_HSI RCC_CCIPR_UART4SEL_1
AnnaBridge 156:ff21514d8981 402 #define RCC_UART4CLKSOURCE_LSE (RCC_CCIPR_UART4SEL_0 | RCC_CCIPR_UART4SEL_1)
AnnaBridge 156:ff21514d8981 403 /**
AnnaBridge 156:ff21514d8981 404 * @}
AnnaBridge 156:ff21514d8981 405 */
AnnaBridge 156:ff21514d8981 406 #endif /* UART4 */
AnnaBridge 156:ff21514d8981 407
AnnaBridge 156:ff21514d8981 408 #if defined(UART5)
AnnaBridge 156:ff21514d8981 409 /** @defgroup RCCEx_UART5_Clock_Source UART5 Clock Source
AnnaBridge 156:ff21514d8981 410 * @{
AnnaBridge 156:ff21514d8981 411 */
AnnaBridge 156:ff21514d8981 412 #define RCC_UART5CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
AnnaBridge 156:ff21514d8981 413 #define RCC_UART5CLKSOURCE_SYSCLK RCC_CCIPR_UART5SEL_0
AnnaBridge 156:ff21514d8981 414 #define RCC_UART5CLKSOURCE_HSI RCC_CCIPR_UART5SEL_1
AnnaBridge 156:ff21514d8981 415 #define RCC_UART5CLKSOURCE_LSE (RCC_CCIPR_UART5SEL_0 | RCC_CCIPR_UART5SEL_1)
AnnaBridge 156:ff21514d8981 416 /**
AnnaBridge 156:ff21514d8981 417 * @}
AnnaBridge 156:ff21514d8981 418 */
AnnaBridge 156:ff21514d8981 419 #endif /* UART5 */
AnnaBridge 156:ff21514d8981 420
AnnaBridge 156:ff21514d8981 421 /** @defgroup RCCEx_LPUART1_Clock_Source LPUART1 Clock Source
AnnaBridge 156:ff21514d8981 422 * @{
AnnaBridge 156:ff21514d8981 423 */
AnnaBridge 156:ff21514d8981 424 #define RCC_LPUART1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
AnnaBridge 156:ff21514d8981 425 #define RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0
AnnaBridge 156:ff21514d8981 426 #define RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1
AnnaBridge 156:ff21514d8981 427 #define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR_LPUART1SEL_0 | RCC_CCIPR_LPUART1SEL_1)
AnnaBridge 156:ff21514d8981 428 /**
AnnaBridge 156:ff21514d8981 429 * @}
AnnaBridge 156:ff21514d8981 430 */
AnnaBridge 156:ff21514d8981 431
AnnaBridge 156:ff21514d8981 432 /** @defgroup RCCEx_I2C1_Clock_Source I2C1 Clock Source
AnnaBridge 156:ff21514d8981 433 * @{
AnnaBridge 156:ff21514d8981 434 */
AnnaBridge 156:ff21514d8981 435 #define RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
AnnaBridge 156:ff21514d8981 436 #define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0
AnnaBridge 156:ff21514d8981 437 #define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR_I2C1SEL_1
AnnaBridge 156:ff21514d8981 438 /**
AnnaBridge 156:ff21514d8981 439 * @}
AnnaBridge 156:ff21514d8981 440 */
AnnaBridge 156:ff21514d8981 441
AnnaBridge 156:ff21514d8981 442 #if defined(I2C2)
AnnaBridge 156:ff21514d8981 443 /** @defgroup RCCEx_I2C2_Clock_Source I2C2 Clock Source
AnnaBridge 156:ff21514d8981 444 * @{
AnnaBridge 156:ff21514d8981 445 */
AnnaBridge 156:ff21514d8981 446 #define RCC_I2C2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
AnnaBridge 156:ff21514d8981 447 #define RCC_I2C2CLKSOURCE_SYSCLK RCC_CCIPR_I2C2SEL_0
AnnaBridge 156:ff21514d8981 448 #define RCC_I2C2CLKSOURCE_HSI RCC_CCIPR_I2C2SEL_1
AnnaBridge 156:ff21514d8981 449 /**
AnnaBridge 156:ff21514d8981 450 * @}
AnnaBridge 156:ff21514d8981 451 */
AnnaBridge 156:ff21514d8981 452 #endif /* I2C2 */
AnnaBridge 156:ff21514d8981 453
AnnaBridge 156:ff21514d8981 454 /** @defgroup RCCEx_I2C3_Clock_Source I2C3 Clock Source
AnnaBridge 156:ff21514d8981 455 * @{
AnnaBridge 156:ff21514d8981 456 */
AnnaBridge 156:ff21514d8981 457 #define RCC_I2C3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
AnnaBridge 156:ff21514d8981 458 #define RCC_I2C3CLKSOURCE_SYSCLK RCC_CCIPR_I2C3SEL_0
AnnaBridge 156:ff21514d8981 459 #define RCC_I2C3CLKSOURCE_HSI RCC_CCIPR_I2C3SEL_1
AnnaBridge 156:ff21514d8981 460 /**
AnnaBridge 156:ff21514d8981 461 * @}
AnnaBridge 156:ff21514d8981 462 */
AnnaBridge 156:ff21514d8981 463
AnnaBridge 156:ff21514d8981 464 #if defined(I2C4)
AnnaBridge 156:ff21514d8981 465 /** @defgroup RCCEx_I2C4_Clock_Source I2C4 Clock Source
AnnaBridge 156:ff21514d8981 466 * @{
AnnaBridge 156:ff21514d8981 467 */
AnnaBridge 156:ff21514d8981 468 #define RCC_I2C4CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
AnnaBridge 156:ff21514d8981 469 #define RCC_I2C4CLKSOURCE_SYSCLK RCC_CCIPR2_I2C4SEL_0
AnnaBridge 156:ff21514d8981 470 #define RCC_I2C4CLKSOURCE_HSI RCC_CCIPR2_I2C4SEL_1
AnnaBridge 156:ff21514d8981 471 /**
AnnaBridge 156:ff21514d8981 472 * @}
AnnaBridge 156:ff21514d8981 473 */
AnnaBridge 156:ff21514d8981 474 #endif /* I2C4 */
AnnaBridge 156:ff21514d8981 475
AnnaBridge 156:ff21514d8981 476 /** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source
AnnaBridge 156:ff21514d8981 477 * @{
AnnaBridge 156:ff21514d8981 478 */
AnnaBridge 156:ff21514d8981 479 #define RCC_SAI1CLKSOURCE_PLLSAI1 ((uint32_t)0x00000000U)
AnnaBridge 156:ff21514d8981 480 #if defined(RCC_PLLSAI2_SUPPORT)
AnnaBridge 156:ff21514d8981 481 #define RCC_SAI1CLKSOURCE_PLLSAI2 RCC_CCIPR_SAI1SEL_0
AnnaBridge 156:ff21514d8981 482 #endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge 156:ff21514d8981 483 #define RCC_SAI1CLKSOURCE_PLL RCC_CCIPR_SAI1SEL_1
AnnaBridge 156:ff21514d8981 484 #define RCC_SAI1CLKSOURCE_PIN RCC_CCIPR_SAI1SEL
AnnaBridge 156:ff21514d8981 485 /**
AnnaBridge 156:ff21514d8981 486 * @}
AnnaBridge 156:ff21514d8981 487 */
AnnaBridge 156:ff21514d8981 488
AnnaBridge 156:ff21514d8981 489 #if defined(SAI2)
AnnaBridge 156:ff21514d8981 490 /** @defgroup RCCEx_SAI2_Clock_Source SAI2 Clock Source
AnnaBridge 156:ff21514d8981 491 * @{
AnnaBridge 156:ff21514d8981 492 */
AnnaBridge 156:ff21514d8981 493 #define RCC_SAI2CLKSOURCE_PLLSAI1 ((uint32_t)0x00000000U)
AnnaBridge 156:ff21514d8981 494 #define RCC_SAI2CLKSOURCE_PLLSAI2 RCC_CCIPR_SAI2SEL_0
AnnaBridge 156:ff21514d8981 495 #define RCC_SAI2CLKSOURCE_PLL RCC_CCIPR_SAI2SEL_1
AnnaBridge 156:ff21514d8981 496 #define RCC_SAI2CLKSOURCE_PIN RCC_CCIPR_SAI2SEL
AnnaBridge 156:ff21514d8981 497 /**
AnnaBridge 156:ff21514d8981 498 * @}
AnnaBridge 156:ff21514d8981 499 */
AnnaBridge 156:ff21514d8981 500 #endif /* SAI2 */
AnnaBridge 156:ff21514d8981 501
AnnaBridge 156:ff21514d8981 502 /** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source
AnnaBridge 156:ff21514d8981 503 * @{
AnnaBridge 156:ff21514d8981 504 */
AnnaBridge 156:ff21514d8981 505 #define RCC_LPTIM1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
AnnaBridge 156:ff21514d8981 506 #define RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0
AnnaBridge 156:ff21514d8981 507 #define RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1
AnnaBridge 156:ff21514d8981 508 #define RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL
AnnaBridge 156:ff21514d8981 509 /**
AnnaBridge 156:ff21514d8981 510 * @}
AnnaBridge 156:ff21514d8981 511 */
AnnaBridge 156:ff21514d8981 512
AnnaBridge 156:ff21514d8981 513 /** @defgroup RCCEx_LPTIM2_Clock_Source LPTIM2 Clock Source
AnnaBridge 156:ff21514d8981 514 * @{
AnnaBridge 156:ff21514d8981 515 */
AnnaBridge 156:ff21514d8981 516 #define RCC_LPTIM2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
AnnaBridge 156:ff21514d8981 517 #define RCC_LPTIM2CLKSOURCE_LSI RCC_CCIPR_LPTIM2SEL_0
AnnaBridge 156:ff21514d8981 518 #define RCC_LPTIM2CLKSOURCE_HSI RCC_CCIPR_LPTIM2SEL_1
AnnaBridge 156:ff21514d8981 519 #define RCC_LPTIM2CLKSOURCE_LSE RCC_CCIPR_LPTIM2SEL
AnnaBridge 156:ff21514d8981 520 /**
AnnaBridge 156:ff21514d8981 521 * @}
AnnaBridge 156:ff21514d8981 522 */
AnnaBridge 156:ff21514d8981 523
AnnaBridge 156:ff21514d8981 524 #if defined(SDMMC1)
AnnaBridge 156:ff21514d8981 525 /** @defgroup RCCEx_SDMMC1_Clock_Source SDMMC1 Clock Source
AnnaBridge 156:ff21514d8981 526 * @{
AnnaBridge 156:ff21514d8981 527 */
AnnaBridge 156:ff21514d8981 528 #if defined(RCC_HSI48_SUPPORT)
AnnaBridge 156:ff21514d8981 529 #define RCC_SDMMC1CLKSOURCE_HSI48 ((uint32_t)0x00000000U)
AnnaBridge 156:ff21514d8981 530 #else
AnnaBridge 156:ff21514d8981 531 #define RCC_SDMMC1CLKSOURCE_NONE ((uint32_t)0x00000000U)
AnnaBridge 156:ff21514d8981 532 #endif /* RCC_HSI48_SUPPORT */
AnnaBridge 156:ff21514d8981 533 #define RCC_SDMMC1CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0
AnnaBridge 156:ff21514d8981 534 #define RCC_SDMMC1CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1
AnnaBridge 156:ff21514d8981 535 #define RCC_SDMMC1CLKSOURCE_MSI RCC_CCIPR_CLK48SEL
AnnaBridge 156:ff21514d8981 536 /**
AnnaBridge 156:ff21514d8981 537 * @}
AnnaBridge 156:ff21514d8981 538 */
AnnaBridge 156:ff21514d8981 539 #endif /* SDMMC1 */
AnnaBridge 156:ff21514d8981 540
AnnaBridge 156:ff21514d8981 541 /** @defgroup RCCEx_RNG_Clock_Source RNG Clock Source
AnnaBridge 156:ff21514d8981 542 * @{
AnnaBridge 156:ff21514d8981 543 */
AnnaBridge 156:ff21514d8981 544 #if defined(RCC_HSI48_SUPPORT)
AnnaBridge 156:ff21514d8981 545 #define RCC_RNGCLKSOURCE_HSI48 ((uint32_t)0x00000000U)
AnnaBridge 156:ff21514d8981 546 #else
AnnaBridge 156:ff21514d8981 547 #define RCC_RNGCLKSOURCE_NONE ((uint32_t)0x00000000U)
AnnaBridge 156:ff21514d8981 548 #endif /* RCC_HSI48_SUPPORT */
AnnaBridge 156:ff21514d8981 549 #define RCC_RNGCLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0
AnnaBridge 156:ff21514d8981 550 #define RCC_RNGCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1
AnnaBridge 156:ff21514d8981 551 #define RCC_RNGCLKSOURCE_MSI RCC_CCIPR_CLK48SEL
AnnaBridge 156:ff21514d8981 552 /**
AnnaBridge 156:ff21514d8981 553 * @}
AnnaBridge 156:ff21514d8981 554 */
AnnaBridge 156:ff21514d8981 555
AnnaBridge 156:ff21514d8981 556 #if defined(USB_OTG_FS) || defined(USB)
AnnaBridge 156:ff21514d8981 557 /** @defgroup RCCEx_USB_Clock_Source USB Clock Source
AnnaBridge 156:ff21514d8981 558 * @{
AnnaBridge 156:ff21514d8981 559 */
AnnaBridge 156:ff21514d8981 560 #if defined(RCC_HSI48_SUPPORT)
AnnaBridge 156:ff21514d8981 561 #define RCC_USBCLKSOURCE_HSI48 ((uint32_t)0x00000000U)
AnnaBridge 156:ff21514d8981 562 #else
AnnaBridge 156:ff21514d8981 563 #define RCC_USBCLKSOURCE_NONE ((uint32_t)0x00000000U)
AnnaBridge 156:ff21514d8981 564 #endif /* RCC_HSI48_SUPPORT */
AnnaBridge 156:ff21514d8981 565 #define RCC_USBCLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0
AnnaBridge 156:ff21514d8981 566 #define RCC_USBCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1
AnnaBridge 156:ff21514d8981 567 #define RCC_USBCLKSOURCE_MSI RCC_CCIPR_CLK48SEL
AnnaBridge 156:ff21514d8981 568 /**
AnnaBridge 156:ff21514d8981 569 * @}
AnnaBridge 156:ff21514d8981 570 */
AnnaBridge 156:ff21514d8981 571 #endif /* USB_OTG_FS || USB */
AnnaBridge 156:ff21514d8981 572
AnnaBridge 156:ff21514d8981 573 /** @defgroup RCCEx_ADC_Clock_Source ADC Clock Source
AnnaBridge 156:ff21514d8981 574 * @{
AnnaBridge 156:ff21514d8981 575 */
AnnaBridge 156:ff21514d8981 576 #define RCC_ADCCLKSOURCE_NONE ((uint32_t)0x00000000U)
AnnaBridge 156:ff21514d8981 577 #define RCC_ADCCLKSOURCE_PLLSAI1 RCC_CCIPR_ADCSEL_0
AnnaBridge 156:ff21514d8981 578 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)
AnnaBridge 156:ff21514d8981 579 #define RCC_ADCCLKSOURCE_PLLSAI2 RCC_CCIPR_ADCSEL_1
AnnaBridge 156:ff21514d8981 580 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */
AnnaBridge 156:ff21514d8981 581 #define RCC_ADCCLKSOURCE_SYSCLK RCC_CCIPR_ADCSEL
AnnaBridge 156:ff21514d8981 582 /**
AnnaBridge 156:ff21514d8981 583 * @}
AnnaBridge 156:ff21514d8981 584 */
AnnaBridge 156:ff21514d8981 585
AnnaBridge 156:ff21514d8981 586 #if defined(SWPMI1)
AnnaBridge 156:ff21514d8981 587 /** @defgroup RCCEx_SWPMI1_Clock_Source SWPMI1 Clock Source
AnnaBridge 156:ff21514d8981 588 * @{
AnnaBridge 156:ff21514d8981 589 */
AnnaBridge 156:ff21514d8981 590 #define RCC_SWPMI1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
AnnaBridge 156:ff21514d8981 591 #define RCC_SWPMI1CLKSOURCE_HSI RCC_CCIPR_SWPMI1SEL
AnnaBridge 156:ff21514d8981 592 /**
AnnaBridge 156:ff21514d8981 593 * @}
AnnaBridge 156:ff21514d8981 594 */
AnnaBridge 156:ff21514d8981 595 #endif /* SWPMI1 */
AnnaBridge 156:ff21514d8981 596
AnnaBridge 156:ff21514d8981 597 #if defined(DFSDM1_Filter0)
AnnaBridge 156:ff21514d8981 598 /** @defgroup RCCEx_DFSDM1_Clock_Source DFSDM1 Clock Source
AnnaBridge 156:ff21514d8981 599 * @{
AnnaBridge 156:ff21514d8981 600 */
AnnaBridge 156:ff21514d8981 601 #define RCC_DFSDM1CLKSOURCE_PCLK2 ((uint32_t)0x00000000U)
AnnaBridge 156:ff21514d8981 602 #define RCC_DFSDM1CLKSOURCE_SYSCLK RCC_CCIPR_DFSDM1SEL
AnnaBridge 156:ff21514d8981 603 /**
AnnaBridge 156:ff21514d8981 604 * @}
AnnaBridge 156:ff21514d8981 605 */
AnnaBridge 156:ff21514d8981 606 #endif /* DFSDM1_Filter0 */
AnnaBridge 156:ff21514d8981 607
AnnaBridge 156:ff21514d8981 608 /** @defgroup RCCEx_EXTI_LINE_LSECSS RCC LSE CSS external interrupt line
AnnaBridge 156:ff21514d8981 609 * @{
AnnaBridge 156:ff21514d8981 610 */
AnnaBridge 156:ff21514d8981 611 #define RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM19 /*!< External interrupt line 19 connected to the LSE CSS EXTI Line */
AnnaBridge 156:ff21514d8981 612 /**
AnnaBridge 156:ff21514d8981 613 * @}
AnnaBridge 156:ff21514d8981 614 */
AnnaBridge 156:ff21514d8981 615
AnnaBridge 156:ff21514d8981 616 #if defined(CRS)
AnnaBridge 156:ff21514d8981 617
AnnaBridge 156:ff21514d8981 618 /** @defgroup RCCEx_CRS_Status RCCEx CRS Status
AnnaBridge 156:ff21514d8981 619 * @{
AnnaBridge 156:ff21514d8981 620 */
AnnaBridge 156:ff21514d8981 621 #define RCC_CRS_NONE ((uint32_t)0x00000000U)
AnnaBridge 156:ff21514d8981 622 #define RCC_CRS_TIMEOUT ((uint32_t)0x00000001U)
AnnaBridge 156:ff21514d8981 623 #define RCC_CRS_SYNCOK ((uint32_t)0x00000002U)
AnnaBridge 156:ff21514d8981 624 #define RCC_CRS_SYNCWARN ((uint32_t)0x00000004U)
AnnaBridge 156:ff21514d8981 625 #define RCC_CRS_SYNCERR ((uint32_t)0x00000008U)
AnnaBridge 156:ff21514d8981 626 #define RCC_CRS_SYNCMISS ((uint32_t)0x00000010U)
AnnaBridge 156:ff21514d8981 627 #define RCC_CRS_TRIMOVF ((uint32_t)0x00000020U)
AnnaBridge 156:ff21514d8981 628 /**
AnnaBridge 156:ff21514d8981 629 * @}
AnnaBridge 156:ff21514d8981 630 */
AnnaBridge 156:ff21514d8981 631
AnnaBridge 156:ff21514d8981 632 /** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource
AnnaBridge 156:ff21514d8981 633 * @{
AnnaBridge 156:ff21514d8981 634 */
AnnaBridge 156:ff21514d8981 635 #define RCC_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00000000U) /*!< Synchro Signal source GPIO */
AnnaBridge 156:ff21514d8981 636 #define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
AnnaBridge 156:ff21514d8981 637 #define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/
AnnaBridge 156:ff21514d8981 638 /**
AnnaBridge 156:ff21514d8981 639 * @}
AnnaBridge 156:ff21514d8981 640 */
AnnaBridge 156:ff21514d8981 641
AnnaBridge 156:ff21514d8981 642 /** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider
AnnaBridge 156:ff21514d8981 643 * @{
AnnaBridge 156:ff21514d8981 644 */
AnnaBridge 156:ff21514d8981 645 #define RCC_CRS_SYNC_DIV1 ((uint32_t)0x00000000U) /*!< Synchro Signal not divided (default) */
AnnaBridge 156:ff21514d8981 646 #define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */
AnnaBridge 156:ff21514d8981 647 #define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */
AnnaBridge 156:ff21514d8981 648 #define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
AnnaBridge 156:ff21514d8981 649 #define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */
AnnaBridge 156:ff21514d8981 650 #define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
AnnaBridge 156:ff21514d8981 651 #define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
AnnaBridge 156:ff21514d8981 652 #define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */
AnnaBridge 156:ff21514d8981 653 /**
AnnaBridge 156:ff21514d8981 654 * @}
AnnaBridge 156:ff21514d8981 655 */
AnnaBridge 156:ff21514d8981 656
AnnaBridge 156:ff21514d8981 657 /** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity
AnnaBridge 156:ff21514d8981 658 * @{
AnnaBridge 156:ff21514d8981 659 */
AnnaBridge 156:ff21514d8981 660 #define RCC_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00000000U) /*!< Synchro Active on rising edge (default) */
AnnaBridge 156:ff21514d8981 661 #define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */
AnnaBridge 156:ff21514d8981 662 /**
AnnaBridge 156:ff21514d8981 663 * @}
AnnaBridge 156:ff21514d8981 664 */
AnnaBridge 156:ff21514d8981 665
AnnaBridge 156:ff21514d8981 666 /** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault
AnnaBridge 156:ff21514d8981 667 * @{
AnnaBridge 156:ff21514d8981 668 */
AnnaBridge 156:ff21514d8981 669 #define RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0x0000BB7FU) /*!< The reset value of the RELOAD field corresponds
AnnaBridge 156:ff21514d8981 670 to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
AnnaBridge 156:ff21514d8981 671 /**
AnnaBridge 156:ff21514d8981 672 * @}
AnnaBridge 156:ff21514d8981 673 */
AnnaBridge 156:ff21514d8981 674
AnnaBridge 156:ff21514d8981 675 /** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault
AnnaBridge 156:ff21514d8981 676 * @{
AnnaBridge 156:ff21514d8981 677 */
AnnaBridge 156:ff21514d8981 678 #define RCC_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x00000022U) /*!< Default Frequency error limit */
AnnaBridge 156:ff21514d8981 679 /**
AnnaBridge 156:ff21514d8981 680 * @}
AnnaBridge 156:ff21514d8981 681 */
AnnaBridge 156:ff21514d8981 682
AnnaBridge 156:ff21514d8981 683 /** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault
AnnaBridge 156:ff21514d8981 684 * @{
AnnaBridge 156:ff21514d8981 685 */
AnnaBridge 156:ff21514d8981 686 #define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x00000020U) /*!< The default value is 32, which corresponds to the middle of the trimming interval.
AnnaBridge 156:ff21514d8981 687 The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value
AnnaBridge 156:ff21514d8981 688 corresponds to a higher output frequency */
AnnaBridge 156:ff21514d8981 689 /**
AnnaBridge 156:ff21514d8981 690 * @}
AnnaBridge 156:ff21514d8981 691 */
AnnaBridge 156:ff21514d8981 692
AnnaBridge 156:ff21514d8981 693 /** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection
AnnaBridge 156:ff21514d8981 694 * @{
AnnaBridge 156:ff21514d8981 695 */
AnnaBridge 156:ff21514d8981 696 #define RCC_CRS_FREQERRORDIR_UP ((uint32_t)0x00000000U) /*!< Upcounting direction, the actual frequency is above the target */
AnnaBridge 156:ff21514d8981 697 #define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */
AnnaBridge 156:ff21514d8981 698 /**
AnnaBridge 156:ff21514d8981 699 * @}
AnnaBridge 156:ff21514d8981 700 */
AnnaBridge 156:ff21514d8981 701
AnnaBridge 156:ff21514d8981 702 /** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources
AnnaBridge 156:ff21514d8981 703 * @{
AnnaBridge 156:ff21514d8981 704 */
AnnaBridge 156:ff21514d8981 705 #define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE /*!< SYNC event OK */
AnnaBridge 156:ff21514d8981 706 #define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE /*!< SYNC warning */
AnnaBridge 156:ff21514d8981 707 #define RCC_CRS_IT_ERR CRS_CR_ERRIE /*!< Error */
AnnaBridge 156:ff21514d8981 708 #define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE /*!< Expected SYNC */
AnnaBridge 156:ff21514d8981 709 #define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE /*!< SYNC error */
AnnaBridge 156:ff21514d8981 710 #define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE /*!< SYNC missed */
AnnaBridge 156:ff21514d8981 711 #define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE /*!< Trimming overflow or underflow */
AnnaBridge 156:ff21514d8981 712
AnnaBridge 156:ff21514d8981 713 /**
AnnaBridge 156:ff21514d8981 714 * @}
AnnaBridge 156:ff21514d8981 715 */
AnnaBridge 156:ff21514d8981 716
AnnaBridge 156:ff21514d8981 717 /** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags
AnnaBridge 156:ff21514d8981 718 * @{
AnnaBridge 156:ff21514d8981 719 */
AnnaBridge 156:ff21514d8981 720 #define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK flag */
AnnaBridge 156:ff21514d8981 721 #define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning flag */
AnnaBridge 156:ff21514d8981 722 #define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /*!< Error flag */
AnnaBridge 156:ff21514d8981 723 #define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC flag */
AnnaBridge 156:ff21514d8981 724 #define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */
AnnaBridge 156:ff21514d8981 725 #define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/
AnnaBridge 156:ff21514d8981 726 #define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */
AnnaBridge 156:ff21514d8981 727
AnnaBridge 156:ff21514d8981 728 /**
AnnaBridge 156:ff21514d8981 729 * @}
AnnaBridge 156:ff21514d8981 730 */
AnnaBridge 156:ff21514d8981 731
AnnaBridge 156:ff21514d8981 732 #endif /* CRS */
AnnaBridge 156:ff21514d8981 733
AnnaBridge 156:ff21514d8981 734 /**
AnnaBridge 156:ff21514d8981 735 * @}
AnnaBridge 156:ff21514d8981 736 */
AnnaBridge 156:ff21514d8981 737
AnnaBridge 156:ff21514d8981 738 /* Exported macros -----------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 739 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
AnnaBridge 156:ff21514d8981 740 * @{
AnnaBridge 156:ff21514d8981 741 */
AnnaBridge 156:ff21514d8981 742
AnnaBridge 156:ff21514d8981 743
AnnaBridge 156:ff21514d8981 744 /**
AnnaBridge 156:ff21514d8981 745 * @brief Macro to configure the PLLSAI1 clock multiplication and division factors.
AnnaBridge 156:ff21514d8981 746 *
AnnaBridge 156:ff21514d8981 747 * @note This function must be used only when the PLLSAI1 is disabled.
AnnaBridge 156:ff21514d8981 748 * @note PLLSAI1 clock source is common with the main PLL (configured through
AnnaBridge 156:ff21514d8981 749 * __HAL_RCC_PLL_CONFIG() macro)
AnnaBridge 156:ff21514d8981 750 *
AnnaBridge 156:ff21514d8981 751 * @param __PLLSAI1N__ specifies the multiplication factor for PLLSAI1 VCO output clock.
AnnaBridge 156:ff21514d8981 752 * This parameter must be a number between 8 and 86.
AnnaBridge 156:ff21514d8981 753 * @note You have to set the PLLSAI1N parameter correctly to ensure that the VCO
AnnaBridge 156:ff21514d8981 754 * output frequency is between 64 and 344 MHz.
AnnaBridge 156:ff21514d8981 755 * PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI1N
AnnaBridge 156:ff21514d8981 756 *
AnnaBridge 156:ff21514d8981 757 * @param __PLLSAI1P__ specifies the division factor for SAI clock.
AnnaBridge 156:ff21514d8981 758 * This parameter must be a number in the range (7 or 17) for STM32L47xxx/L48xxx
AnnaBridge 156:ff21514d8981 759 * else (2 to 31).
AnnaBridge 156:ff21514d8981 760 * SAI1 clock frequency = f(PLLSAI1) / PLLSAI1P
AnnaBridge 156:ff21514d8981 761 *
AnnaBridge 156:ff21514d8981 762 * @param __PLLSAI1Q__ specifies the division factor for USB/RNG/SDMMC1 clock.
AnnaBridge 156:ff21514d8981 763 * This parameter must be in the range (2, 4, 6 or 8).
AnnaBridge 156:ff21514d8981 764 * USB/RNG/SDMMC1 clock frequency = f(PLLSAI1) / PLLSAI1Q
AnnaBridge 156:ff21514d8981 765 *
AnnaBridge 156:ff21514d8981 766 * @param __PLLSAI1R__ specifies the division factor for SAR ADC clock.
AnnaBridge 156:ff21514d8981 767 * This parameter must be in the range (2, 4, 6 or 8).
AnnaBridge 156:ff21514d8981 768 * ADC clock frequency = f(PLLSAI1) / PLLSAI1R
AnnaBridge 156:ff21514d8981 769 *
AnnaBridge 156:ff21514d8981 770 * @retval None
AnnaBridge 156:ff21514d8981 771 */
AnnaBridge 156:ff21514d8981 772 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
AnnaBridge 156:ff21514d8981 773
AnnaBridge 156:ff21514d8981 774 #define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \
AnnaBridge 156:ff21514d8981 775 WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N)) | \
AnnaBridge 156:ff21514d8981 776 ((((__PLLSAI1Q__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q)) | \
AnnaBridge 156:ff21514d8981 777 ((((__PLLSAI1R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R)) | \
AnnaBridge 156:ff21514d8981 778 ((__PLLSAI1P__) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1PDIV)))
AnnaBridge 156:ff21514d8981 779
AnnaBridge 156:ff21514d8981 780 #else
AnnaBridge 156:ff21514d8981 781
AnnaBridge 156:ff21514d8981 782 #define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \
AnnaBridge 156:ff21514d8981 783 WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N)) | \
AnnaBridge 156:ff21514d8981 784 (((__PLLSAI1P__) >> 4U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1P)) | \
AnnaBridge 156:ff21514d8981 785 ((((__PLLSAI1Q__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q)) | \
AnnaBridge 156:ff21514d8981 786 ((((__PLLSAI1R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R)))
AnnaBridge 156:ff21514d8981 787
AnnaBridge 156:ff21514d8981 788 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
AnnaBridge 156:ff21514d8981 789
AnnaBridge 156:ff21514d8981 790 /**
AnnaBridge 156:ff21514d8981 791 * @brief Macro to configure the PLLSAI1 clock multiplication factor N.
AnnaBridge 156:ff21514d8981 792 *
AnnaBridge 156:ff21514d8981 793 * @note This function must be used only when the PLLSAI1 is disabled.
AnnaBridge 156:ff21514d8981 794 * @note PLLSAI1 clock source is common with the main PLL (configured through
AnnaBridge 156:ff21514d8981 795 * __HAL_RCC_PLL_CONFIG() macro)
AnnaBridge 156:ff21514d8981 796 *
AnnaBridge 156:ff21514d8981 797 * @param __PLLSAI1N__ specifies the multiplication factor for PLLSAI1 VCO output clock.
AnnaBridge 156:ff21514d8981 798 * This parameter must be a number between 8 and 86.
AnnaBridge 156:ff21514d8981 799 * @note You have to set the PLLSAI1N parameter correctly to ensure that the VCO
AnnaBridge 156:ff21514d8981 800 * output frequency is between 64 and 344 MHz.
AnnaBridge 156:ff21514d8981 801 * Use to set PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI1N
AnnaBridge 156:ff21514d8981 802 *
AnnaBridge 156:ff21514d8981 803 * @retval None
AnnaBridge 156:ff21514d8981 804 */
AnnaBridge 156:ff21514d8981 805 #define __HAL_RCC_PLLSAI1_MULN_CONFIG(__PLLSAI1N__) \
AnnaBridge 156:ff21514d8981 806 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N, (__PLLSAI1N__) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N))
AnnaBridge 156:ff21514d8981 807
AnnaBridge 156:ff21514d8981 808 /** @brief Macro to configure the PLLSAI1 clock division factor P.
AnnaBridge 156:ff21514d8981 809 *
AnnaBridge 156:ff21514d8981 810 * @note This function must be used only when the PLLSAI1 is disabled.
AnnaBridge 156:ff21514d8981 811 * @note PLLSAI1 clock source is common with the main PLL (configured through
AnnaBridge 156:ff21514d8981 812 * __HAL_RCC_PLL_CONFIG() macro)
AnnaBridge 156:ff21514d8981 813 *
AnnaBridge 156:ff21514d8981 814 * @param __PLLSAI1P__ specifies the division factor for SAI clock.
AnnaBridge 156:ff21514d8981 815 * This parameter must be a number in the range (7 or 17) for STM32L47xxx/L48xxx
AnnaBridge 156:ff21514d8981 816 * else (2 to 31).
AnnaBridge 156:ff21514d8981 817 * Use to set SAI1 clock frequency = f(PLLSAI1) / PLLSAI1P
AnnaBridge 156:ff21514d8981 818 *
AnnaBridge 156:ff21514d8981 819 * @retval None
AnnaBridge 156:ff21514d8981 820 */
AnnaBridge 156:ff21514d8981 821 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
AnnaBridge 156:ff21514d8981 822
AnnaBridge 156:ff21514d8981 823 #define __HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLSAI1P__) \
AnnaBridge 156:ff21514d8981 824 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV, (__PLLSAI1P__) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1PDIV))
AnnaBridge 156:ff21514d8981 825
AnnaBridge 156:ff21514d8981 826 #else
AnnaBridge 156:ff21514d8981 827
AnnaBridge 156:ff21514d8981 828 #define __HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLSAI1P__) \
AnnaBridge 156:ff21514d8981 829 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P, ((__PLLSAI1P__) >> 4U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1P))
AnnaBridge 156:ff21514d8981 830
AnnaBridge 156:ff21514d8981 831 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
AnnaBridge 156:ff21514d8981 832
AnnaBridge 156:ff21514d8981 833 /** @brief Macro to configure the PLLSAI1 clock division factor Q.
AnnaBridge 156:ff21514d8981 834 *
AnnaBridge 156:ff21514d8981 835 * @note This function must be used only when the PLLSAI1 is disabled.
AnnaBridge 156:ff21514d8981 836 * @note PLLSAI1 clock source is common with the main PLL (configured through
AnnaBridge 156:ff21514d8981 837 * __HAL_RCC_PLL_CONFIG() macro)
AnnaBridge 156:ff21514d8981 838 *
AnnaBridge 156:ff21514d8981 839 * @param __PLLSAI1Q__ specifies the division factor for USB/RNG/SDMMC1 clock.
AnnaBridge 156:ff21514d8981 840 * This parameter must be in the range (2, 4, 6 or 8).
AnnaBridge 156:ff21514d8981 841 * Use to set USB/RNG/SDMMC1 clock frequency = f(PLLSAI1) / PLLSAI1Q
AnnaBridge 156:ff21514d8981 842 *
AnnaBridge 156:ff21514d8981 843 * @retval None
AnnaBridge 156:ff21514d8981 844 */
AnnaBridge 156:ff21514d8981 845 #define __HAL_RCC_PLLSAI1_DIVQ_CONFIG(__PLLSAI1Q__) \
AnnaBridge 156:ff21514d8981 846 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q, (((__PLLSAI1Q__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q))
AnnaBridge 156:ff21514d8981 847
AnnaBridge 156:ff21514d8981 848 /** @brief Macro to configure the PLLSAI1 clock division factor R.
AnnaBridge 156:ff21514d8981 849 *
AnnaBridge 156:ff21514d8981 850 * @note This function must be used only when the PLLSAI1 is disabled.
AnnaBridge 156:ff21514d8981 851 * @note PLLSAI1 clock source is common with the main PLL (configured through
AnnaBridge 156:ff21514d8981 852 * __HAL_RCC_PLL_CONFIG() macro)
AnnaBridge 156:ff21514d8981 853 *
AnnaBridge 156:ff21514d8981 854 * @param __PLLSAI1R__ specifies the division factor for ADC clock.
AnnaBridge 156:ff21514d8981 855 * This parameter must be in the range (2, 4, 6 or 8)
AnnaBridge 156:ff21514d8981 856 * Use to set ADC clock frequency = f(PLLSAI1) / PLLSAI1R
AnnaBridge 156:ff21514d8981 857 *
AnnaBridge 156:ff21514d8981 858 * @retval None
AnnaBridge 156:ff21514d8981 859 */
AnnaBridge 156:ff21514d8981 860 #define __HAL_RCC_PLLSAI1_DIVR_CONFIG(__PLLSAI1R__) \
AnnaBridge 156:ff21514d8981 861 MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R, (((__PLLSAI1R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R))
AnnaBridge 156:ff21514d8981 862
AnnaBridge 156:ff21514d8981 863 /**
AnnaBridge 156:ff21514d8981 864 * @brief Macros to enable or disable the PLLSAI1.
AnnaBridge 156:ff21514d8981 865 * @note The PLLSAI1 is disabled by hardware when entering STOP and STANDBY modes.
AnnaBridge 156:ff21514d8981 866 * @retval None
AnnaBridge 156:ff21514d8981 867 */
AnnaBridge 156:ff21514d8981 868
AnnaBridge 156:ff21514d8981 869 #define __HAL_RCC_PLLSAI1_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLSAI1ON)
AnnaBridge 156:ff21514d8981 870
AnnaBridge 156:ff21514d8981 871 #define __HAL_RCC_PLLSAI1_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI1ON)
AnnaBridge 156:ff21514d8981 872
AnnaBridge 156:ff21514d8981 873 /**
AnnaBridge 156:ff21514d8981 874 * @brief Macros to enable or disable each clock output (PLLSAI1_SAI1, PLLSAI1_USB2 and PLLSAI1_ADC1).
AnnaBridge 156:ff21514d8981 875 * @note Enabling and disabling those clocks can be done without the need to stop the PLL.
AnnaBridge 156:ff21514d8981 876 * This is mainly used to save Power.
AnnaBridge 156:ff21514d8981 877 * @param __PLLSAI1_CLOCKOUT__ specifies the PLLSAI1 clock to be output.
AnnaBridge 156:ff21514d8981 878 * This parameter can be one or a combination of the following values:
AnnaBridge 156:ff21514d8981 879 * @arg @ref RCC_PLLSAI1_SAI1CLK This clock is used to generate an accurate clock to achieve
AnnaBridge 156:ff21514d8981 880 * high-quality audio performance on SAI interface in case.
AnnaBridge 156:ff21514d8981 881 * @arg @ref RCC_PLLSAI1_48M2CLK This clock is used to generate the clock for the USB OTG FS (48 MHz),
AnnaBridge 156:ff21514d8981 882 * the random number generator (<=48 MHz) and the SDIO (<= 48 MHz).
AnnaBridge 156:ff21514d8981 883 * @arg @ref RCC_PLLSAI1_ADC1CLK Clock used to clock ADC peripheral.
AnnaBridge 156:ff21514d8981 884 * @retval None
AnnaBridge 156:ff21514d8981 885 */
AnnaBridge 156:ff21514d8981 886
AnnaBridge 156:ff21514d8981 887 #define __HAL_RCC_PLLSAI1CLKOUT_ENABLE(__PLLSAI1_CLOCKOUT__) SET_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))
AnnaBridge 156:ff21514d8981 888
AnnaBridge 156:ff21514d8981 889 #define __HAL_RCC_PLLSAI1CLKOUT_DISABLE(__PLLSAI1_CLOCKOUT__) CLEAR_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))
AnnaBridge 156:ff21514d8981 890
AnnaBridge 156:ff21514d8981 891 /**
AnnaBridge 156:ff21514d8981 892 * @brief Macro to get clock output enable status (PLLSAI1_SAI1, PLLSAI1_USB2 and PLLSAI1_ADC1).
AnnaBridge 156:ff21514d8981 893 * @param __PLLSAI1_CLOCKOUT__ specifies the PLLSAI1 clock to be output.
AnnaBridge 156:ff21514d8981 894 * This parameter can be one of the following values:
AnnaBridge 156:ff21514d8981 895 * @arg @ref RCC_PLLSAI1_SAI1CLK This clock is used to generate an accurate clock to achieve
AnnaBridge 156:ff21514d8981 896 * high-quality audio performance on SAI interface in case.
AnnaBridge 156:ff21514d8981 897 * @arg @ref RCC_PLLSAI1_48M2CLK This clock is used to generate the clock for the USB OTG FS (48 MHz),
AnnaBridge 156:ff21514d8981 898 * the random number generator (<=48 MHz) and the SDIO (<= 48 MHz).
AnnaBridge 156:ff21514d8981 899 * @arg @ref RCC_PLLSAI1_ADC1CLK Clock used to clock ADC peripheral.
AnnaBridge 156:ff21514d8981 900 * @retval SET / RESET
AnnaBridge 156:ff21514d8981 901 */
AnnaBridge 156:ff21514d8981 902 #define __HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(__PLLSAI1_CLOCKOUT__) READ_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))
AnnaBridge 156:ff21514d8981 903
AnnaBridge 156:ff21514d8981 904 #if defined(RCC_PLLSAI2_SUPPORT)
AnnaBridge 156:ff21514d8981 905
AnnaBridge 156:ff21514d8981 906 /**
AnnaBridge 156:ff21514d8981 907 * @brief Macro to configure the PLLSAI2 clock multiplication and division factors.
AnnaBridge 156:ff21514d8981 908 *
AnnaBridge 156:ff21514d8981 909 * @note This function must be used only when the PLLSAI2 is disabled.
AnnaBridge 156:ff21514d8981 910 * @note PLLSAI2 clock source is common with the main PLL (configured through
AnnaBridge 156:ff21514d8981 911 * __HAL_RCC_PLL_CONFIG() macro)
AnnaBridge 156:ff21514d8981 912 *
AnnaBridge 156:ff21514d8981 913 * @param __PLLSAI2N__ specifies the multiplication factor for PLLSAI2 VCO output clock.
AnnaBridge 156:ff21514d8981 914 * This parameter must be a number between 8 and 86.
AnnaBridge 156:ff21514d8981 915 * @note You have to set the PLLSAI2N parameter correctly to ensure that the VCO
AnnaBridge 156:ff21514d8981 916 * output frequency is between 64 and 344 MHz.
AnnaBridge 156:ff21514d8981 917 *
AnnaBridge 156:ff21514d8981 918 * @param __PLLSAI2P__ specifies the division factor for SAI clock.
AnnaBridge 156:ff21514d8981 919 * This parameter must be a number in the range (7 or 17) for STM32L47xxx/L48xxx
AnnaBridge 156:ff21514d8981 920 * else (2 to 31).
AnnaBridge 156:ff21514d8981 921 * SAI2 clock frequency = f(PLLSAI2) / PLLSAI2P
AnnaBridge 156:ff21514d8981 922 *
AnnaBridge 156:ff21514d8981 923 * @param __PLLSAI2R__ specifies the division factor for SAR ADC clock.
AnnaBridge 156:ff21514d8981 924 * This parameter must be in the range (2, 4, 6 or 8).
AnnaBridge 156:ff21514d8981 925 *
AnnaBridge 156:ff21514d8981 926 * @retval None
AnnaBridge 156:ff21514d8981 927 */
AnnaBridge 156:ff21514d8981 928
AnnaBridge 156:ff21514d8981 929 #if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
AnnaBridge 156:ff21514d8981 930
AnnaBridge 156:ff21514d8981 931 #define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \
AnnaBridge 156:ff21514d8981 932 WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N)) | \
AnnaBridge 156:ff21514d8981 933 ((((__PLLSAI2R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R)) | \
AnnaBridge 156:ff21514d8981 934 ((__PLLSAI2P__) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2PDIV)))
AnnaBridge 156:ff21514d8981 935
AnnaBridge 156:ff21514d8981 936 #else
AnnaBridge 156:ff21514d8981 937
AnnaBridge 156:ff21514d8981 938 #define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \
AnnaBridge 156:ff21514d8981 939 WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N)) | \
AnnaBridge 156:ff21514d8981 940 (((__PLLSAI2P__) >> 4U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2P)) | \
AnnaBridge 156:ff21514d8981 941 ((((__PLLSAI2R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R)))
AnnaBridge 156:ff21514d8981 942
AnnaBridge 156:ff21514d8981 943 #endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */
AnnaBridge 156:ff21514d8981 944
AnnaBridge 156:ff21514d8981 945
AnnaBridge 156:ff21514d8981 946 /**
AnnaBridge 156:ff21514d8981 947 * @brief Macro to configure the PLLSAI2 clock multiplication factor N.
AnnaBridge 156:ff21514d8981 948 *
AnnaBridge 156:ff21514d8981 949 * @note This function must be used only when the PLLSAI2 is disabled.
AnnaBridge 156:ff21514d8981 950 * @note PLLSAI2 clock source is common with the main PLL (configured through
AnnaBridge 156:ff21514d8981 951 * __HAL_RCC_PLL_CONFIG() macro)
AnnaBridge 156:ff21514d8981 952 *
AnnaBridge 156:ff21514d8981 953 * @param __PLLSAI2N__ specifies the multiplication factor for PLLSAI2 VCO output clock.
AnnaBridge 156:ff21514d8981 954 * This parameter must be a number between 8 and 86.
AnnaBridge 156:ff21514d8981 955 * @note You have to set the PLLSAI2N parameter correctly to ensure that the VCO
AnnaBridge 156:ff21514d8981 956 * output frequency is between 64 and 344 MHz.
AnnaBridge 156:ff21514d8981 957 * PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI2N
AnnaBridge 156:ff21514d8981 958 *
AnnaBridge 156:ff21514d8981 959 * @retval None
AnnaBridge 156:ff21514d8981 960 */
AnnaBridge 156:ff21514d8981 961 #define __HAL_RCC_PLLSAI2_MULN_CONFIG(__PLLSAI2N__) \
AnnaBridge 156:ff21514d8981 962 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N, (__PLLSAI2N__) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N))
AnnaBridge 156:ff21514d8981 963
AnnaBridge 156:ff21514d8981 964 /** @brief Macro to configure the PLLSAI2 clock division factor P.
AnnaBridge 156:ff21514d8981 965 *
AnnaBridge 156:ff21514d8981 966 * @note This function must be used only when the PLLSAI2 is disabled.
AnnaBridge 156:ff21514d8981 967 * @note PLLSAI2 clock source is common with the main PLL (configured through
AnnaBridge 156:ff21514d8981 968 * __HAL_RCC_PLL_CONFIG() macro)
AnnaBridge 156:ff21514d8981 969 *
AnnaBridge 156:ff21514d8981 970 * @param __PLLSAI2P__ specifies the division factor.
AnnaBridge 156:ff21514d8981 971 * This parameter must be a number in the range (7 or 17).
AnnaBridge 156:ff21514d8981 972 * Use to set SAI2 clock frequency = f(PLLSAI2) / __PLLSAI2P__
AnnaBridge 156:ff21514d8981 973 *
AnnaBridge 156:ff21514d8981 974 * @retval None
AnnaBridge 156:ff21514d8981 975 */
AnnaBridge 156:ff21514d8981 976 #define __HAL_RCC_PLLSAI2_DIVP_CONFIG(__PLLSAI2P__) \
AnnaBridge 156:ff21514d8981 977 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P, ((__PLLSAI2P__) >> 4U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2P))
AnnaBridge 156:ff21514d8981 978
AnnaBridge 156:ff21514d8981 979 /** @brief Macro to configure the PLLSAI2 clock division factor R.
AnnaBridge 156:ff21514d8981 980 *
AnnaBridge 156:ff21514d8981 981 * @note This function must be used only when the PLLSAI2 is disabled.
AnnaBridge 156:ff21514d8981 982 * @note PLLSAI2 clock source is common with the main PLL (configured through
AnnaBridge 156:ff21514d8981 983 * __HAL_RCC_PLL_CONFIG() macro)
AnnaBridge 156:ff21514d8981 984 *
AnnaBridge 156:ff21514d8981 985 * @param __PLLSAI2R__ specifies the division factor.
AnnaBridge 156:ff21514d8981 986 * This parameter must be in the range (2, 4, 6 or 8).
AnnaBridge 156:ff21514d8981 987 * Use to set ADC clock frequency = f(PLLSAI2) / __PLLSAI2R__
AnnaBridge 156:ff21514d8981 988 *
AnnaBridge 156:ff21514d8981 989 * @retval None
AnnaBridge 156:ff21514d8981 990 */
AnnaBridge 156:ff21514d8981 991 #define __HAL_RCC_PLLSAI2_DIVR_CONFIG(__PLLSAI2R__) \
AnnaBridge 156:ff21514d8981 992 MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R, (((__PLLSAI2R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R))
AnnaBridge 156:ff21514d8981 993
AnnaBridge 156:ff21514d8981 994 /**
AnnaBridge 156:ff21514d8981 995 * @brief Macros to enable or disable the PLLSAI2.
AnnaBridge 156:ff21514d8981 996 * @note The PLLSAI2 is disabled by hardware when entering STOP and STANDBY modes.
AnnaBridge 156:ff21514d8981 997 * @retval None
AnnaBridge 156:ff21514d8981 998 */
AnnaBridge 156:ff21514d8981 999
AnnaBridge 156:ff21514d8981 1000 #define __HAL_RCC_PLLSAI2_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLSAI2ON)
AnnaBridge 156:ff21514d8981 1001
AnnaBridge 156:ff21514d8981 1002 #define __HAL_RCC_PLLSAI2_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI2ON)
AnnaBridge 156:ff21514d8981 1003
AnnaBridge 156:ff21514d8981 1004 /**
AnnaBridge 156:ff21514d8981 1005 * @brief Macros to enable or disable each clock output (PLLSAI2_SAI2 and PLLSAI2_ADC2).
AnnaBridge 156:ff21514d8981 1006 * @note Enabling and disabling those clocks can be done without the need to stop the PLL.
AnnaBridge 156:ff21514d8981 1007 * This is mainly used to save Power.
AnnaBridge 156:ff21514d8981 1008 * @param __PLLSAI2_CLOCKOUT__ specifies the PLLSAI2 clock to be output.
AnnaBridge 156:ff21514d8981 1009 * This parameter can be one or a combination of the following values:
AnnaBridge 156:ff21514d8981 1010 * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve
AnnaBridge 156:ff21514d8981 1011 * high-quality audio performance on SAI interface in case.
AnnaBridge 156:ff21514d8981 1012 * @arg @ref RCC_PLLSAI2_ADC2CLK Clock used to clock ADC peripheral.
AnnaBridge 156:ff21514d8981 1013 * @retval None
AnnaBridge 156:ff21514d8981 1014 */
AnnaBridge 156:ff21514d8981 1015
AnnaBridge 156:ff21514d8981 1016 #define __HAL_RCC_PLLSAI2CLKOUT_ENABLE(__PLLSAI2_CLOCKOUT__) SET_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__))
AnnaBridge 156:ff21514d8981 1017
AnnaBridge 156:ff21514d8981 1018 #define __HAL_RCC_PLLSAI2CLKOUT_DISABLE(__PLLSAI2_CLOCKOUT__) CLEAR_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__))
AnnaBridge 156:ff21514d8981 1019
AnnaBridge 156:ff21514d8981 1020 /**
AnnaBridge 156:ff21514d8981 1021 * @brief Macro to get clock output enable status (PLLSAI2_SAI2 and PLLSAI2_ADC2).
AnnaBridge 156:ff21514d8981 1022 * @param __PLLSAI2_CLOCKOUT__ specifies the PLLSAI2 clock to be output.
AnnaBridge 156:ff21514d8981 1023 * This parameter can be one of the following values:
AnnaBridge 156:ff21514d8981 1024 * @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve
AnnaBridge 156:ff21514d8981 1025 * high-quality audio performance on SAI interface in case.
AnnaBridge 156:ff21514d8981 1026 * @arg @ref RCC_PLLSAI2_ADC2CLK Clock used to clock ADC peripheral.
AnnaBridge 156:ff21514d8981 1027 * @retval SET / RESET
AnnaBridge 156:ff21514d8981 1028 */
AnnaBridge 156:ff21514d8981 1029 #define __HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(__PLLSAI2_CLOCKOUT__) READ_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__))
AnnaBridge 156:ff21514d8981 1030
AnnaBridge 156:ff21514d8981 1031 #endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge 156:ff21514d8981 1032
AnnaBridge 156:ff21514d8981 1033 /**
AnnaBridge 156:ff21514d8981 1034 * @brief Macro to configure the SAI1 clock source.
AnnaBridge 156:ff21514d8981 1035 * @param __SAI1_CLKSOURCE__ defines the SAI1 clock source. This clock is derived
AnnaBridge 156:ff21514d8981 1036 * from the PLLSAI1, system PLL or external clock (through a dedicated pin).
AnnaBridge 156:ff21514d8981 1037 * This parameter can be one of the following values:
AnnaBridge 156:ff21514d8981 1038 * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI1 SAI1 clock = PLLSAI1 "P" clock (PLLSAI1CLK)
AnnaBridge 156:ff21514d8981 1039 @if STM32L486xx
AnnaBridge 156:ff21514d8981 1040 * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI2 SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK) for devices with PLLSAI2
AnnaBridge 156:ff21514d8981 1041 @endif
AnnaBridge 156:ff21514d8981 1042 @if STM32L4A6xx
AnnaBridge 156:ff21514d8981 1043 * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI2 SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK) for devices with PLLSAI2
AnnaBridge 156:ff21514d8981 1044 @endif
AnnaBridge 156:ff21514d8981 1045 * @arg @ref RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "P" clock (PLLSAI3CLK if PLLSAI2 exists, else PLLSAI2CLK)
AnnaBridge 156:ff21514d8981 1046 * @arg @ref RCC_SAI1CLKSOURCE_PIN SAI1 clock = External Clock (SAI1_EXTCLK)
AnnaBridge 156:ff21514d8981 1047 *
AnnaBridge 156:ff21514d8981 1048 @if STM32L443xx
AnnaBridge 156:ff21514d8981 1049 * @note HSI16 is automatically set as SAI1 clock source when PLL are disabled for devices without PLLSAI2.
AnnaBridge 156:ff21514d8981 1050 @endif
AnnaBridge 156:ff21514d8981 1051 @if STM32L462xx
AnnaBridge 156:ff21514d8981 1052 * @note HSI16 is automatically set as SAI1 clock source when PLL are disabled for devices without PLLSAI2.
AnnaBridge 156:ff21514d8981 1053 @endif
AnnaBridge 156:ff21514d8981 1054 *
AnnaBridge 156:ff21514d8981 1055 * @retval None
AnnaBridge 156:ff21514d8981 1056 */
AnnaBridge 156:ff21514d8981 1057 #define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\
AnnaBridge 156:ff21514d8981 1058 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, (uint32_t)(__SAI1_CLKSOURCE__))
AnnaBridge 156:ff21514d8981 1059
AnnaBridge 156:ff21514d8981 1060 /** @brief Macro to get the SAI1 clock source.
AnnaBridge 156:ff21514d8981 1061 * @retval The clock source can be one of the following values:
AnnaBridge 156:ff21514d8981 1062 * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI1 SAI1 clock = PLLSAI1 "P" clock (PLLSAI1CLK)
AnnaBridge 156:ff21514d8981 1063 @if STM32L486xx
AnnaBridge 156:ff21514d8981 1064 * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI2 SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK) for devices with PLLSAI2
AnnaBridge 156:ff21514d8981 1065 @endif
AnnaBridge 156:ff21514d8981 1066 @if STM32L4A6xx
AnnaBridge 156:ff21514d8981 1067 * @arg @ref RCC_SAI1CLKSOURCE_PLLSAI2 SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK) for devices with PLLSAI2
AnnaBridge 156:ff21514d8981 1068 @endif
AnnaBridge 156:ff21514d8981 1069 * @arg @ref RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "P" clock (PLLSAI3CLK if PLLSAI2 exists, else PLLSAI2CLK)
AnnaBridge 156:ff21514d8981 1070 * @arg @ref RCC_SAI1CLKSOURCE_PIN SAI1 clock = External Clock (SAI1_EXTCLK)
AnnaBridge 156:ff21514d8981 1071 *
AnnaBridge 156:ff21514d8981 1072 * @note Despite returned values RCC_SAI1CLKSOURCE_PLLSAI1 or RCC_SAI1CLKSOURCE_PLL, HSI16 is automatically set as SAI1
AnnaBridge 156:ff21514d8981 1073 * clock source when PLLs are disabled for devices without PLLSAI2.
AnnaBridge 156:ff21514d8981 1074 *
AnnaBridge 156:ff21514d8981 1075 */
AnnaBridge 156:ff21514d8981 1076 #define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL)))
AnnaBridge 156:ff21514d8981 1077
AnnaBridge 156:ff21514d8981 1078 #if defined(SAI2)
AnnaBridge 156:ff21514d8981 1079
AnnaBridge 156:ff21514d8981 1080 /**
AnnaBridge 156:ff21514d8981 1081 * @brief Macro to configure the SAI2 clock source.
AnnaBridge 156:ff21514d8981 1082 * @param __SAI2_CLKSOURCE__ defines the SAI2 clock source. This clock is derived
AnnaBridge 156:ff21514d8981 1083 * from the PLLSAI2, system PLL or external clock (through a dedicated pin).
AnnaBridge 156:ff21514d8981 1084 * This parameter can be one of the following values:
AnnaBridge 156:ff21514d8981 1085 * @arg @ref RCC_SAI2CLKSOURCE_PLLSAI1 SAI2 clock = PLLSAI1 "P" clock (PLLSAI1CLK)
AnnaBridge 156:ff21514d8981 1086 * @arg @ref RCC_SAI2CLKSOURCE_PLLSAI2 SAI2 clock = PLLSAI2 "P" clock (PLLSAI2CLK)
AnnaBridge 156:ff21514d8981 1087 * @arg @ref RCC_SAI2CLKSOURCE_PLL SAI2 clock = PLL "P" clock (PLLSAI3CLK)
AnnaBridge 156:ff21514d8981 1088 * @arg @ref RCC_SAI2CLKSOURCE_PIN SAI2 clock = External Clock (SAI2_EXTCLK)
AnnaBridge 156:ff21514d8981 1089 *
AnnaBridge 156:ff21514d8981 1090 * @retval None
AnnaBridge 156:ff21514d8981 1091 */
AnnaBridge 156:ff21514d8981 1092 #define __HAL_RCC_SAI2_CONFIG(__SAI2_CLKSOURCE__ )\
AnnaBridge 156:ff21514d8981 1093 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI2SEL, (uint32_t)(__SAI2_CLKSOURCE__))
AnnaBridge 156:ff21514d8981 1094
AnnaBridge 156:ff21514d8981 1095 /** @brief Macro to get the SAI2 clock source.
AnnaBridge 156:ff21514d8981 1096 * @retval The clock source can be one of the following values:
AnnaBridge 156:ff21514d8981 1097 * @arg @ref RCC_SAI2CLKSOURCE_PLLSAI1 SAI2 clock = PLLSAI1 "P" clock (PLLSAI1CLK)
AnnaBridge 156:ff21514d8981 1098 * @arg @ref RCC_SAI2CLKSOURCE_PLLSAI2 SAI2 clock = PLLSAI2 "P" clock (PLLSAI2CLK)
AnnaBridge 156:ff21514d8981 1099 * @arg @ref RCC_SAI2CLKSOURCE_PLL SAI2 clock = PLL "P" clock (PLLSAI3CLK)
AnnaBridge 156:ff21514d8981 1100 * @arg @ref RCC_SAI2CLKSOURCE_PIN SAI2 clock = External Clock (SAI2_EXTCLK)
AnnaBridge 156:ff21514d8981 1101 */
AnnaBridge 156:ff21514d8981 1102 #define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI2SEL)))
AnnaBridge 156:ff21514d8981 1103
AnnaBridge 156:ff21514d8981 1104 #endif /* SAI2 */
AnnaBridge 156:ff21514d8981 1105
AnnaBridge 156:ff21514d8981 1106 /** @brief Macro to configure the I2C1 clock (I2C1CLK).
AnnaBridge 156:ff21514d8981 1107 *
AnnaBridge 156:ff21514d8981 1108 * @param __I2C1_CLKSOURCE__ specifies the I2C1 clock source.
AnnaBridge 156:ff21514d8981 1109 * This parameter can be one of the following values:
AnnaBridge 156:ff21514d8981 1110 * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock
AnnaBridge 156:ff21514d8981 1111 * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
AnnaBridge 156:ff21514d8981 1112 * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock
AnnaBridge 156:ff21514d8981 1113 * @retval None
AnnaBridge 156:ff21514d8981 1114 */
AnnaBridge 156:ff21514d8981 1115 #define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \
AnnaBridge 156:ff21514d8981 1116 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__))
AnnaBridge 156:ff21514d8981 1117
AnnaBridge 156:ff21514d8981 1118 /** @brief Macro to get the I2C1 clock source.
AnnaBridge 156:ff21514d8981 1119 * @retval The clock source can be one of the following values:
AnnaBridge 156:ff21514d8981 1120 * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock
AnnaBridge 156:ff21514d8981 1121 * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
AnnaBridge 156:ff21514d8981 1122 * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock
AnnaBridge 156:ff21514d8981 1123 */
AnnaBridge 156:ff21514d8981 1124 #define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL)))
AnnaBridge 156:ff21514d8981 1125
AnnaBridge 156:ff21514d8981 1126 #if defined(I2C2)
AnnaBridge 156:ff21514d8981 1127
AnnaBridge 156:ff21514d8981 1128 /** @brief Macro to configure the I2C2 clock (I2C2CLK).
AnnaBridge 156:ff21514d8981 1129 *
AnnaBridge 156:ff21514d8981 1130 * @param __I2C2_CLKSOURCE__ specifies the I2C2 clock source.
AnnaBridge 156:ff21514d8981 1131 * This parameter can be one of the following values:
AnnaBridge 156:ff21514d8981 1132 * @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock
AnnaBridge 156:ff21514d8981 1133 * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
AnnaBridge 156:ff21514d8981 1134 * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
AnnaBridge 156:ff21514d8981 1135 * @retval None
AnnaBridge 156:ff21514d8981 1136 */
AnnaBridge 156:ff21514d8981 1137 #define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \
AnnaBridge 156:ff21514d8981 1138 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__))
AnnaBridge 156:ff21514d8981 1139
AnnaBridge 156:ff21514d8981 1140 /** @brief Macro to get the I2C2 clock source.
AnnaBridge 156:ff21514d8981 1141 * @retval The clock source can be one of the following values:
AnnaBridge 156:ff21514d8981 1142 * @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock
AnnaBridge 156:ff21514d8981 1143 * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
AnnaBridge 156:ff21514d8981 1144 * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
AnnaBridge 156:ff21514d8981 1145 */
AnnaBridge 156:ff21514d8981 1146 #define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C2SEL)))
AnnaBridge 156:ff21514d8981 1147
AnnaBridge 156:ff21514d8981 1148 #endif /* I2C2 */
AnnaBridge 156:ff21514d8981 1149
AnnaBridge 156:ff21514d8981 1150 /** @brief Macro to configure the I2C3 clock (I2C3CLK).
AnnaBridge 156:ff21514d8981 1151 *
AnnaBridge 156:ff21514d8981 1152 * @param __I2C3_CLKSOURCE__ specifies the I2C3 clock source.
AnnaBridge 156:ff21514d8981 1153 * This parameter can be one of the following values:
AnnaBridge 156:ff21514d8981 1154 * @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock
AnnaBridge 156:ff21514d8981 1155 * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock
AnnaBridge 156:ff21514d8981 1156 * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock
AnnaBridge 156:ff21514d8981 1157 * @retval None
AnnaBridge 156:ff21514d8981 1158 */
AnnaBridge 156:ff21514d8981 1159 #define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \
AnnaBridge 156:ff21514d8981 1160 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__))
AnnaBridge 156:ff21514d8981 1161
AnnaBridge 156:ff21514d8981 1162 /** @brief Macro to get the I2C3 clock source.
AnnaBridge 156:ff21514d8981 1163 * @retval The clock source can be one of the following values:
AnnaBridge 156:ff21514d8981 1164 * @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock
AnnaBridge 156:ff21514d8981 1165 * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock
AnnaBridge 156:ff21514d8981 1166 * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock
AnnaBridge 156:ff21514d8981 1167 */
AnnaBridge 156:ff21514d8981 1168 #define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL)))
AnnaBridge 156:ff21514d8981 1169
AnnaBridge 156:ff21514d8981 1170 #if defined(I2C4)
AnnaBridge 156:ff21514d8981 1171
AnnaBridge 156:ff21514d8981 1172 /** @brief Macro to configure the I2C4 clock (I2C4CLK).
AnnaBridge 156:ff21514d8981 1173 *
AnnaBridge 156:ff21514d8981 1174 * @param __I2C4_CLKSOURCE__ specifies the I2C4 clock source.
AnnaBridge 156:ff21514d8981 1175 * This parameter can be one of the following values:
AnnaBridge 156:ff21514d8981 1176 * @arg @ref RCC_I2C4CLKSOURCE_PCLK1 PCLK1 selected as I2C4 clock
AnnaBridge 156:ff21514d8981 1177 * @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock
AnnaBridge 156:ff21514d8981 1178 * @arg @ref RCC_I2C4CLKSOURCE_SYSCLK System Clock selected as I2C4 clock
AnnaBridge 156:ff21514d8981 1179 * @retval None
AnnaBridge 156:ff21514d8981 1180 */
AnnaBridge 156:ff21514d8981 1181 #define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \
AnnaBridge 156:ff21514d8981 1182 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL, (uint32_t)(__I2C4_CLKSOURCE__))
AnnaBridge 156:ff21514d8981 1183
AnnaBridge 156:ff21514d8981 1184 /** @brief Macro to get the I2C4 clock source.
AnnaBridge 156:ff21514d8981 1185 * @retval The clock source can be one of the following values:
AnnaBridge 156:ff21514d8981 1186 * @arg @ref RCC_I2C4CLKSOURCE_PCLK1 PCLK1 selected as I2C4 clock
AnnaBridge 156:ff21514d8981 1187 * @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock
AnnaBridge 156:ff21514d8981 1188 * @arg @ref RCC_I2C4CLKSOURCE_SYSCLK System Clock selected as I2C4 clock
AnnaBridge 156:ff21514d8981 1189 */
AnnaBridge 156:ff21514d8981 1190 #define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL)))
AnnaBridge 156:ff21514d8981 1191
AnnaBridge 156:ff21514d8981 1192 #endif /* I2C4 */
AnnaBridge 156:ff21514d8981 1193
AnnaBridge 156:ff21514d8981 1194
AnnaBridge 156:ff21514d8981 1195 /** @brief Macro to configure the USART1 clock (USART1CLK).
AnnaBridge 156:ff21514d8981 1196 *
AnnaBridge 156:ff21514d8981 1197 * @param __USART1_CLKSOURCE__ specifies the USART1 clock source.
AnnaBridge 156:ff21514d8981 1198 * This parameter can be one of the following values:
AnnaBridge 156:ff21514d8981 1199 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
AnnaBridge 156:ff21514d8981 1200 * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
AnnaBridge 156:ff21514d8981 1201 * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock
AnnaBridge 156:ff21514d8981 1202 * @arg @ref RCC_USART1CLKSOURCE_LSE SE selected as USART1 clock
AnnaBridge 156:ff21514d8981 1203 * @retval None
AnnaBridge 156:ff21514d8981 1204 */
AnnaBridge 156:ff21514d8981 1205 #define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \
AnnaBridge 156:ff21514d8981 1206 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__))
AnnaBridge 156:ff21514d8981 1207
AnnaBridge 156:ff21514d8981 1208 /** @brief Macro to get the USART1 clock source.
AnnaBridge 156:ff21514d8981 1209 * @retval The clock source can be one of the following values:
AnnaBridge 156:ff21514d8981 1210 * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
AnnaBridge 156:ff21514d8981 1211 * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
AnnaBridge 156:ff21514d8981 1212 * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock
AnnaBridge 156:ff21514d8981 1213 * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock
AnnaBridge 156:ff21514d8981 1214 */
AnnaBridge 156:ff21514d8981 1215 #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL)))
AnnaBridge 156:ff21514d8981 1216
AnnaBridge 156:ff21514d8981 1217 /** @brief Macro to configure the USART2 clock (USART2CLK).
AnnaBridge 156:ff21514d8981 1218 *
AnnaBridge 156:ff21514d8981 1219 * @param __USART2_CLKSOURCE__ specifies the USART2 clock source.
AnnaBridge 156:ff21514d8981 1220 * This parameter can be one of the following values:
AnnaBridge 156:ff21514d8981 1221 * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock
AnnaBridge 156:ff21514d8981 1222 * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock
AnnaBridge 156:ff21514d8981 1223 * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock
AnnaBridge 156:ff21514d8981 1224 * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock
AnnaBridge 156:ff21514d8981 1225 * @retval None
AnnaBridge 156:ff21514d8981 1226 */
AnnaBridge 156:ff21514d8981 1227 #define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \
AnnaBridge 156:ff21514d8981 1228 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__))
AnnaBridge 156:ff21514d8981 1229
AnnaBridge 156:ff21514d8981 1230 /** @brief Macro to get the USART2 clock source.
AnnaBridge 156:ff21514d8981 1231 * @retval The clock source can be one of the following values:
AnnaBridge 156:ff21514d8981 1232 * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock
AnnaBridge 156:ff21514d8981 1233 * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock
AnnaBridge 156:ff21514d8981 1234 * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock
AnnaBridge 156:ff21514d8981 1235 * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock
AnnaBridge 156:ff21514d8981 1236 */
AnnaBridge 156:ff21514d8981 1237 #define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL)))
AnnaBridge 156:ff21514d8981 1238
AnnaBridge 156:ff21514d8981 1239 #if defined(USART3)
AnnaBridge 156:ff21514d8981 1240
AnnaBridge 156:ff21514d8981 1241 /** @brief Macro to configure the USART3 clock (USART3CLK).
AnnaBridge 156:ff21514d8981 1242 *
AnnaBridge 156:ff21514d8981 1243 * @param __USART3_CLKSOURCE__ specifies the USART3 clock source.
AnnaBridge 156:ff21514d8981 1244 * This parameter can be one of the following values:
AnnaBridge 156:ff21514d8981 1245 * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock
AnnaBridge 156:ff21514d8981 1246 * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock
AnnaBridge 156:ff21514d8981 1247 * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock
AnnaBridge 156:ff21514d8981 1248 * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock
AnnaBridge 156:ff21514d8981 1249 * @retval None
AnnaBridge 156:ff21514d8981 1250 */
AnnaBridge 156:ff21514d8981 1251 #define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \
AnnaBridge 156:ff21514d8981 1252 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__))
AnnaBridge 156:ff21514d8981 1253
AnnaBridge 156:ff21514d8981 1254 /** @brief Macro to get the USART3 clock source.
AnnaBridge 156:ff21514d8981 1255 * @retval The clock source can be one of the following values:
AnnaBridge 156:ff21514d8981 1256 * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock
AnnaBridge 156:ff21514d8981 1257 * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock
AnnaBridge 156:ff21514d8981 1258 * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock
AnnaBridge 156:ff21514d8981 1259 * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock
AnnaBridge 156:ff21514d8981 1260 */
AnnaBridge 156:ff21514d8981 1261 #define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART3SEL)))
AnnaBridge 156:ff21514d8981 1262
AnnaBridge 156:ff21514d8981 1263 #endif /* USART3 */
AnnaBridge 156:ff21514d8981 1264
AnnaBridge 156:ff21514d8981 1265 #if defined(UART4)
AnnaBridge 156:ff21514d8981 1266
AnnaBridge 156:ff21514d8981 1267 /** @brief Macro to configure the UART4 clock (UART4CLK).
AnnaBridge 156:ff21514d8981 1268 *
AnnaBridge 156:ff21514d8981 1269 * @param __UART4_CLKSOURCE__ specifies the UART4 clock source.
AnnaBridge 156:ff21514d8981 1270 * This parameter can be one of the following values:
AnnaBridge 156:ff21514d8981 1271 * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock
AnnaBridge 156:ff21514d8981 1272 * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock
AnnaBridge 156:ff21514d8981 1273 * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock
AnnaBridge 156:ff21514d8981 1274 * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock
AnnaBridge 156:ff21514d8981 1275 * @retval None
AnnaBridge 156:ff21514d8981 1276 */
AnnaBridge 156:ff21514d8981 1277 #define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \
AnnaBridge 156:ff21514d8981 1278 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__))
AnnaBridge 156:ff21514d8981 1279
AnnaBridge 156:ff21514d8981 1280 /** @brief Macro to get the UART4 clock source.
AnnaBridge 156:ff21514d8981 1281 * @retval The clock source can be one of the following values:
AnnaBridge 156:ff21514d8981 1282 * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock
AnnaBridge 156:ff21514d8981 1283 * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock
AnnaBridge 156:ff21514d8981 1284 * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock
AnnaBridge 156:ff21514d8981 1285 * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock
AnnaBridge 156:ff21514d8981 1286 */
AnnaBridge 156:ff21514d8981 1287 #define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_UART4SEL)))
AnnaBridge 156:ff21514d8981 1288
AnnaBridge 156:ff21514d8981 1289 #endif /* UART4 */
AnnaBridge 156:ff21514d8981 1290
AnnaBridge 156:ff21514d8981 1291 #if defined(UART5)
AnnaBridge 156:ff21514d8981 1292
AnnaBridge 156:ff21514d8981 1293 /** @brief Macro to configure the UART5 clock (UART5CLK).
AnnaBridge 156:ff21514d8981 1294 *
AnnaBridge 156:ff21514d8981 1295 * @param __UART5_CLKSOURCE__ specifies the UART5 clock source.
AnnaBridge 156:ff21514d8981 1296 * This parameter can be one of the following values:
AnnaBridge 156:ff21514d8981 1297 * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock
AnnaBridge 156:ff21514d8981 1298 * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock
AnnaBridge 156:ff21514d8981 1299 * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock
AnnaBridge 156:ff21514d8981 1300 * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock
AnnaBridge 156:ff21514d8981 1301 * @retval None
AnnaBridge 156:ff21514d8981 1302 */
AnnaBridge 156:ff21514d8981 1303 #define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \
AnnaBridge 156:ff21514d8981 1304 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__))
AnnaBridge 156:ff21514d8981 1305
AnnaBridge 156:ff21514d8981 1306 /** @brief Macro to get the UART5 clock source.
AnnaBridge 156:ff21514d8981 1307 * @retval The clock source can be one of the following values:
AnnaBridge 156:ff21514d8981 1308 * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock
AnnaBridge 156:ff21514d8981 1309 * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock
AnnaBridge 156:ff21514d8981 1310 * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock
AnnaBridge 156:ff21514d8981 1311 * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock
AnnaBridge 156:ff21514d8981 1312 */
AnnaBridge 156:ff21514d8981 1313 #define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_UART5SEL)))
AnnaBridge 156:ff21514d8981 1314
AnnaBridge 156:ff21514d8981 1315 #endif /* UART5 */
AnnaBridge 156:ff21514d8981 1316
AnnaBridge 156:ff21514d8981 1317 /** @brief Macro to configure the LPUART1 clock (LPUART1CLK).
AnnaBridge 156:ff21514d8981 1318 *
AnnaBridge 156:ff21514d8981 1319 * @param __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source.
AnnaBridge 156:ff21514d8981 1320 * This parameter can be one of the following values:
AnnaBridge 156:ff21514d8981 1321 * @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock
AnnaBridge 156:ff21514d8981 1322 * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock
AnnaBridge 156:ff21514d8981 1323 * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock
AnnaBridge 156:ff21514d8981 1324 * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock
AnnaBridge 156:ff21514d8981 1325 * @retval None
AnnaBridge 156:ff21514d8981 1326 */
AnnaBridge 156:ff21514d8981 1327 #define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \
AnnaBridge 156:ff21514d8981 1328 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (uint32_t)(__LPUART1_CLKSOURCE__))
AnnaBridge 156:ff21514d8981 1329
AnnaBridge 156:ff21514d8981 1330 /** @brief Macro to get the LPUART1 clock source.
AnnaBridge 156:ff21514d8981 1331 * @retval The clock source can be one of the following values:
AnnaBridge 156:ff21514d8981 1332 * @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock
AnnaBridge 156:ff21514d8981 1333 * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock
AnnaBridge 156:ff21514d8981 1334 * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock
AnnaBridge 156:ff21514d8981 1335 * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock
AnnaBridge 156:ff21514d8981 1336 */
AnnaBridge 156:ff21514d8981 1337 #define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL)))
AnnaBridge 156:ff21514d8981 1338
AnnaBridge 156:ff21514d8981 1339 /** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK).
AnnaBridge 156:ff21514d8981 1340 *
AnnaBridge 156:ff21514d8981 1341 * @param __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source.
AnnaBridge 156:ff21514d8981 1342 * This parameter can be one of the following values:
AnnaBridge 156:ff21514d8981 1343 * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1 PCLK1 selected as LPTIM1 clock
AnnaBridge 156:ff21514d8981 1344 * @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPTIM1 clock
AnnaBridge 156:ff21514d8981 1345 * @arg @ref RCC_LPTIM1CLKSOURCE_HSI LSI selected as LPTIM1 clock
AnnaBridge 156:ff21514d8981 1346 * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock
AnnaBridge 156:ff21514d8981 1347 * @retval None
AnnaBridge 156:ff21514d8981 1348 */
AnnaBridge 156:ff21514d8981 1349 #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \
AnnaBridge 156:ff21514d8981 1350 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__))
AnnaBridge 156:ff21514d8981 1351
AnnaBridge 156:ff21514d8981 1352 /** @brief Macro to get the LPTIM1 clock source.
AnnaBridge 156:ff21514d8981 1353 * @retval The clock source can be one of the following values:
AnnaBridge 156:ff21514d8981 1354 * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock
AnnaBridge 156:ff21514d8981 1355 * @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPUART1 clock
AnnaBridge 156:ff21514d8981 1356 * @arg @ref RCC_LPTIM1CLKSOURCE_HSI System Clock selected as LPUART1 clock
AnnaBridge 156:ff21514d8981 1357 * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPUART1 clock
AnnaBridge 156:ff21514d8981 1358 */
AnnaBridge 156:ff21514d8981 1359 #define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL)))
AnnaBridge 156:ff21514d8981 1360
AnnaBridge 156:ff21514d8981 1361 /** @brief Macro to configure the LPTIM2 clock (LPTIM2CLK).
AnnaBridge 156:ff21514d8981 1362 *
AnnaBridge 156:ff21514d8981 1363 * @param __LPTIM2_CLKSOURCE__ specifies the LPTIM2 clock source.
AnnaBridge 156:ff21514d8981 1364 * This parameter can be one of the following values:
AnnaBridge 156:ff21514d8981 1365 * @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1 PCLK1 selected as LPTIM2 clock
AnnaBridge 156:ff21514d8981 1366 * @arg @ref RCC_LPTIM2CLKSOURCE_LSI HSI selected as LPTIM2 clock
AnnaBridge 156:ff21514d8981 1367 * @arg @ref RCC_LPTIM2CLKSOURCE_HSI LSI selected as LPTIM2 clock
AnnaBridge 156:ff21514d8981 1368 * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPTIM2 clock
AnnaBridge 156:ff21514d8981 1369 * @retval None
AnnaBridge 156:ff21514d8981 1370 */
AnnaBridge 156:ff21514d8981 1371 #define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2_CLKSOURCE__) \
AnnaBridge 156:ff21514d8981 1372 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2_CLKSOURCE__))
AnnaBridge 156:ff21514d8981 1373
AnnaBridge 156:ff21514d8981 1374 /** @brief Macro to get the LPTIM2 clock source.
AnnaBridge 156:ff21514d8981 1375 * @retval The clock source can be one of the following values:
AnnaBridge 156:ff21514d8981 1376 * @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock
AnnaBridge 156:ff21514d8981 1377 * @arg @ref RCC_LPTIM2CLKSOURCE_LSI HSI selected as LPUART1 clock
AnnaBridge 156:ff21514d8981 1378 * @arg @ref RCC_LPTIM2CLKSOURCE_HSI System Clock selected as LPUART1 clock
AnnaBridge 156:ff21514d8981 1379 * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPUART1 clock
AnnaBridge 156:ff21514d8981 1380 */
AnnaBridge 156:ff21514d8981 1381 #define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL)))
AnnaBridge 156:ff21514d8981 1382
AnnaBridge 156:ff21514d8981 1383 #if defined(SDMMC1)
AnnaBridge 156:ff21514d8981 1384
AnnaBridge 156:ff21514d8981 1385 /** @brief Macro to configure the SDMMC1 clock.
AnnaBridge 156:ff21514d8981 1386 *
AnnaBridge 156:ff21514d8981 1387 @if STM32L443xx
AnnaBridge 156:ff21514d8981 1388 * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.
AnnaBridge 156:ff21514d8981 1389 @endif
AnnaBridge 156:ff21514d8981 1390 @if STM32L462xx
AnnaBridge 156:ff21514d8981 1391 * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.
AnnaBridge 156:ff21514d8981 1392 @endif
AnnaBridge 156:ff21514d8981 1393 @if STM32L486xx
AnnaBridge 156:ff21514d8981 1394 * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.
AnnaBridge 156:ff21514d8981 1395 @endif
AnnaBridge 156:ff21514d8981 1396 @if STM32L4A6xx
AnnaBridge 156:ff21514d8981 1397 * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.
AnnaBridge 156:ff21514d8981 1398 @endif
AnnaBridge 156:ff21514d8981 1399 *
AnnaBridge 156:ff21514d8981 1400 * @param __SDMMC1_CLKSOURCE__ specifies the SDMMC1 clock source.
AnnaBridge 156:ff21514d8981 1401 * This parameter can be one of the following values:
AnnaBridge 156:ff21514d8981 1402 @if STM32L443xx
AnnaBridge 156:ff21514d8981 1403 * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48
AnnaBridge 156:ff21514d8981 1404 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock
AnnaBridge 156:ff21514d8981 1405 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as SDMMC1 clock
AnnaBridge 156:ff21514d8981 1406 * @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL Clock selected as SDMMC1 clock
AnnaBridge 156:ff21514d8981 1407 @endif
AnnaBridge 156:ff21514d8981 1408 @if STM32L462xx
AnnaBridge 156:ff21514d8981 1409 * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48
AnnaBridge 156:ff21514d8981 1410 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock
AnnaBridge 156:ff21514d8981 1411 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as SDMMC1 clock
AnnaBridge 156:ff21514d8981 1412 * @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL Clock selected as SDMMC1 clock
AnnaBridge 156:ff21514d8981 1413 @endif
AnnaBridge 156:ff21514d8981 1414 @if STM32L486xx
AnnaBridge 156:ff21514d8981 1415 * @arg @ref RCC_SDMMC1CLKSOURCE_NONE No clock selected as SDMMC1 clock for devices without HSI48
AnnaBridge 156:ff21514d8981 1416 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock
AnnaBridge 156:ff21514d8981 1417 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as SDMMC1 clock
AnnaBridge 156:ff21514d8981 1418 * @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL Clock selected as SDMMC1 clock
AnnaBridge 156:ff21514d8981 1419 @endif
AnnaBridge 156:ff21514d8981 1420 @if STM32L4A6xx
AnnaBridge 156:ff21514d8981 1421 * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48
AnnaBridge 156:ff21514d8981 1422 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock
AnnaBridge 156:ff21514d8981 1423 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as SDMMC1 clock
AnnaBridge 156:ff21514d8981 1424 * @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL Clock selected as SDMMC1 clock
AnnaBridge 156:ff21514d8981 1425 @endif
AnnaBridge 156:ff21514d8981 1426 * @retval None
AnnaBridge 156:ff21514d8981 1427 */
AnnaBridge 156:ff21514d8981 1428 #define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \
AnnaBridge 156:ff21514d8981 1429 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (uint32_t)(__SDMMC1_CLKSOURCE__))
AnnaBridge 156:ff21514d8981 1430
AnnaBridge 156:ff21514d8981 1431 /** @brief Macro to get the SDMMC1 clock.
AnnaBridge 156:ff21514d8981 1432 * @retval The clock source can be one of the following values:
AnnaBridge 156:ff21514d8981 1433 @if STM32L443xx
AnnaBridge 156:ff21514d8981 1434 * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48
AnnaBridge 156:ff21514d8981 1435 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock
AnnaBridge 156:ff21514d8981 1436 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock
AnnaBridge 156:ff21514d8981 1437 * @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as SDMMC1 clock
AnnaBridge 156:ff21514d8981 1438 @endif
AnnaBridge 156:ff21514d8981 1439 @if STM32L462xx
AnnaBridge 156:ff21514d8981 1440 * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48
AnnaBridge 156:ff21514d8981 1441 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock
AnnaBridge 156:ff21514d8981 1442 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock
AnnaBridge 156:ff21514d8981 1443 * @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as SDMMC1 clock
AnnaBridge 156:ff21514d8981 1444 @endif
AnnaBridge 156:ff21514d8981 1445 @if STM32L486xx
AnnaBridge 156:ff21514d8981 1446 * @arg @ref RCC_SDMMC1CLKSOURCE_NONE No clock selected as SDMMC1 clock for devices without HSI48
AnnaBridge 156:ff21514d8981 1447 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock
AnnaBridge 156:ff21514d8981 1448 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock
AnnaBridge 156:ff21514d8981 1449 * @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as SDMMC1 clock
AnnaBridge 156:ff21514d8981 1450 @endif
AnnaBridge 156:ff21514d8981 1451 @if STM32L4A6xx
AnnaBridge 156:ff21514d8981 1452 * @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48
AnnaBridge 156:ff21514d8981 1453 * @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock
AnnaBridge 156:ff21514d8981 1454 * @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock
AnnaBridge 156:ff21514d8981 1455 * @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as SDMMC1 clock
AnnaBridge 156:ff21514d8981 1456 @endif
AnnaBridge 156:ff21514d8981 1457 */
AnnaBridge 156:ff21514d8981 1458 #define __HAL_RCC_GET_SDMMC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)))
AnnaBridge 156:ff21514d8981 1459
AnnaBridge 156:ff21514d8981 1460 #endif /* SDMMC1 */
AnnaBridge 156:ff21514d8981 1461
AnnaBridge 156:ff21514d8981 1462 /** @brief Macro to configure the RNG clock.
AnnaBridge 156:ff21514d8981 1463 *
AnnaBridge 156:ff21514d8981 1464 * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.
AnnaBridge 156:ff21514d8981 1465 *
AnnaBridge 156:ff21514d8981 1466 * @param __RNG_CLKSOURCE__ specifies the RNG clock source.
AnnaBridge 156:ff21514d8981 1467 * This parameter can be one of the following values:
AnnaBridge 156:ff21514d8981 1468 @if STM32L443xx
AnnaBridge 156:ff21514d8981 1469 * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock clock for devices with HSI48
AnnaBridge 156:ff21514d8981 1470 @endif
AnnaBridge 156:ff21514d8981 1471 @if STM32L462xx
AnnaBridge 156:ff21514d8981 1472 * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock clock for devices with HSI48
AnnaBridge 156:ff21514d8981 1473 @endif
AnnaBridge 156:ff21514d8981 1474 @if STM32L486xx
AnnaBridge 156:ff21514d8981 1475 * @arg @ref RCC_RNGCLKSOURCE_NONE No clock selected as RNG clock for devices without HSI48
AnnaBridge 156:ff21514d8981 1476 @endif
AnnaBridge 156:ff21514d8981 1477 @if STM32L4A6xx
AnnaBridge 156:ff21514d8981 1478 * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock clock for devices with HSI48
AnnaBridge 156:ff21514d8981 1479 @endif
AnnaBridge 156:ff21514d8981 1480 * @arg @ref RCC_RNGCLKSOURCE_MSI MSI selected as RNG clock
AnnaBridge 156:ff21514d8981 1481 * @arg @ref RCC_RNGCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as RNG clock
AnnaBridge 156:ff21514d8981 1482 * @arg @ref RCC_RNGCLKSOURCE_PLL PLL Clock selected as RNG clock
AnnaBridge 156:ff21514d8981 1483 * @retval None
AnnaBridge 156:ff21514d8981 1484 */
AnnaBridge 156:ff21514d8981 1485 #define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) \
AnnaBridge 156:ff21514d8981 1486 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (uint32_t)(__RNG_CLKSOURCE__))
AnnaBridge 156:ff21514d8981 1487
AnnaBridge 156:ff21514d8981 1488 /** @brief Macro to get the RNG clock.
AnnaBridge 156:ff21514d8981 1489 * @retval The clock source can be one of the following values:
AnnaBridge 156:ff21514d8981 1490 @if STM32L443xx
AnnaBridge 156:ff21514d8981 1491 * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock clock for devices with HSI48
AnnaBridge 156:ff21514d8981 1492 @endif
AnnaBridge 156:ff21514d8981 1493 @if STM32L462xx
AnnaBridge 156:ff21514d8981 1494 * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock clock for devices with HSI48
AnnaBridge 156:ff21514d8981 1495 @endif
AnnaBridge 156:ff21514d8981 1496 @if STM32L486xx
AnnaBridge 156:ff21514d8981 1497 * @arg @ref RCC_RNGCLKSOURCE_NONE No clock selected as RNG clock for devices without HSI48
AnnaBridge 156:ff21514d8981 1498 @endif
AnnaBridge 156:ff21514d8981 1499 @if STM32L4A6xx
AnnaBridge 156:ff21514d8981 1500 * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock clock for devices with HSI48
AnnaBridge 156:ff21514d8981 1501 @endif
AnnaBridge 156:ff21514d8981 1502 * @arg @ref RCC_RNGCLKSOURCE_MSI MSI selected as RNG clock
AnnaBridge 156:ff21514d8981 1503 * @arg @ref RCC_RNGCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as RNG clock
AnnaBridge 156:ff21514d8981 1504 * @arg @ref RCC_RNGCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as RNG clock
AnnaBridge 156:ff21514d8981 1505 */
AnnaBridge 156:ff21514d8981 1506 #define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)))
AnnaBridge 156:ff21514d8981 1507
AnnaBridge 156:ff21514d8981 1508 #if defined(USB_OTG_FS) || defined(USB)
AnnaBridge 156:ff21514d8981 1509
AnnaBridge 156:ff21514d8981 1510 /** @brief Macro to configure the USB clock (USBCLK).
AnnaBridge 156:ff21514d8981 1511 *
AnnaBridge 156:ff21514d8981 1512 * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.
AnnaBridge 156:ff21514d8981 1513 *
AnnaBridge 156:ff21514d8981 1514 * @param __USB_CLKSOURCE__ specifies the USB clock source.
AnnaBridge 156:ff21514d8981 1515 * This parameter can be one of the following values:
AnnaBridge 156:ff21514d8981 1516 @if STM32L443xx
AnnaBridge 156:ff21514d8981 1517 * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48
AnnaBridge 156:ff21514d8981 1518 @endif
AnnaBridge 156:ff21514d8981 1519 @if STM32L462xx
AnnaBridge 156:ff21514d8981 1520 * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48
AnnaBridge 156:ff21514d8981 1521 @endif
AnnaBridge 156:ff21514d8981 1522 @if STM32L486xx
AnnaBridge 156:ff21514d8981 1523 * @arg @ref RCC_USBCLKSOURCE_NONE No clock selected as 48MHz clock for devices without HSI48
AnnaBridge 156:ff21514d8981 1524 @endif
AnnaBridge 156:ff21514d8981 1525 @if STM32L4A6xx
AnnaBridge 156:ff21514d8981 1526 * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48
AnnaBridge 156:ff21514d8981 1527 @endif
AnnaBridge 156:ff21514d8981 1528 * @arg @ref RCC_USBCLKSOURCE_MSI MSI selected as USB clock
AnnaBridge 156:ff21514d8981 1529 * @arg @ref RCC_USBCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as USB clock
AnnaBridge 156:ff21514d8981 1530 * @arg @ref RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock
AnnaBridge 156:ff21514d8981 1531 * @retval None
AnnaBridge 156:ff21514d8981 1532 */
AnnaBridge 156:ff21514d8981 1533 #define __HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__) \
AnnaBridge 156:ff21514d8981 1534 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (uint32_t)(__USB_CLKSOURCE__))
AnnaBridge 156:ff21514d8981 1535
AnnaBridge 156:ff21514d8981 1536 /** @brief Macro to get the USB clock source.
AnnaBridge 156:ff21514d8981 1537 * @retval The clock source can be one of the following values:
AnnaBridge 156:ff21514d8981 1538 @if STM32L443xx
AnnaBridge 156:ff21514d8981 1539 * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48
AnnaBridge 156:ff21514d8981 1540 @endif
AnnaBridge 156:ff21514d8981 1541 @if STM32L462xx
AnnaBridge 156:ff21514d8981 1542 * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48
AnnaBridge 156:ff21514d8981 1543 @endif
AnnaBridge 156:ff21514d8981 1544 @if STM32L486xx
AnnaBridge 156:ff21514d8981 1545 * @arg @ref RCC_USBCLKSOURCE_NONE No clock selected as 48MHz clock for devices without HSI48
AnnaBridge 156:ff21514d8981 1546 @endif
AnnaBridge 156:ff21514d8981 1547 @if STM32L4A6xx
AnnaBridge 156:ff21514d8981 1548 * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48
AnnaBridge 156:ff21514d8981 1549 @endif
AnnaBridge 156:ff21514d8981 1550 * @arg @ref RCC_USBCLKSOURCE_MSI MSI selected as USB clock
AnnaBridge 156:ff21514d8981 1551 * @arg @ref RCC_USBCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as USB clock
AnnaBridge 156:ff21514d8981 1552 * @arg @ref RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock
AnnaBridge 156:ff21514d8981 1553 */
AnnaBridge 156:ff21514d8981 1554 #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)))
AnnaBridge 156:ff21514d8981 1555
AnnaBridge 156:ff21514d8981 1556 #endif /* USB_OTG_FS || USB */
AnnaBridge 156:ff21514d8981 1557
AnnaBridge 156:ff21514d8981 1558 /** @brief Macro to configure the ADC interface clock.
AnnaBridge 156:ff21514d8981 1559 * @param __ADC_CLKSOURCE__ specifies the ADC digital interface clock source.
AnnaBridge 156:ff21514d8981 1560 * This parameter can be one of the following values:
AnnaBridge 156:ff21514d8981 1561 * @arg @ref RCC_ADCCLKSOURCE_NONE No clock selected as ADC clock
AnnaBridge 156:ff21514d8981 1562 * @arg @ref RCC_ADCCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as ADC clock
AnnaBridge 156:ff21514d8981 1563 @if STM32L486xx
AnnaBridge 156:ff21514d8981 1564 * @arg @ref RCC_ADCCLKSOURCE_PLLSAI2 PLLSAI2 Clock selected as ADC clock for STM32L47x/STM32L48x/STM32L49x/STM32L4Ax devices
AnnaBridge 156:ff21514d8981 1565 @endif
AnnaBridge 156:ff21514d8981 1566 @if STM32L4A6xx
AnnaBridge 156:ff21514d8981 1567 * @arg @ref RCC_ADCCLKSOURCE_PLLSAI2 PLLSAI2 Clock selected as ADC clock for STM32L47x/STM32L48x/STM32L49x/STM32L4Ax devices
AnnaBridge 156:ff21514d8981 1568 @endif
AnnaBridge 156:ff21514d8981 1569 * @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock
AnnaBridge 156:ff21514d8981 1570 * @retval None
AnnaBridge 156:ff21514d8981 1571 */
AnnaBridge 156:ff21514d8981 1572 #define __HAL_RCC_ADC_CONFIG(__ADC_CLKSOURCE__) \
AnnaBridge 156:ff21514d8981 1573 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, (uint32_t)(__ADC_CLKSOURCE__))
AnnaBridge 156:ff21514d8981 1574
AnnaBridge 156:ff21514d8981 1575 /** @brief Macro to get the ADC clock source.
AnnaBridge 156:ff21514d8981 1576 * @retval The clock source can be one of the following values:
AnnaBridge 156:ff21514d8981 1577 * @arg @ref RCC_ADCCLKSOURCE_NONE No clock selected as ADC clock
AnnaBridge 156:ff21514d8981 1578 * @arg @ref RCC_ADCCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as ADC clock
AnnaBridge 156:ff21514d8981 1579 @if STM32L486xx
AnnaBridge 156:ff21514d8981 1580 * @arg @ref RCC_ADCCLKSOURCE_PLLSAI2 PLLSAI2 Clock selected as ADC clock for STM32L47x/STM32L48x/STM32L49x/STM32L4Ax devices
AnnaBridge 156:ff21514d8981 1581 @endif
AnnaBridge 156:ff21514d8981 1582 @if STM32L4A6xx
AnnaBridge 156:ff21514d8981 1583 * @arg @ref RCC_ADCCLKSOURCE_PLLSAI2 PLLSAI2 Clock selected as ADC clock for STM32L47x/STM32L48x/STM32L49x/STM32L4Ax devices
AnnaBridge 156:ff21514d8981 1584 @endif
AnnaBridge 156:ff21514d8981 1585 * @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock
AnnaBridge 156:ff21514d8981 1586 */
AnnaBridge 156:ff21514d8981 1587 #define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_ADCSEL)))
AnnaBridge 156:ff21514d8981 1588
AnnaBridge 156:ff21514d8981 1589 #if defined(SWPMI1)
AnnaBridge 156:ff21514d8981 1590
AnnaBridge 156:ff21514d8981 1591 /** @brief Macro to configure the SWPMI1 clock.
AnnaBridge 156:ff21514d8981 1592 * @param __SWPMI1_CLKSOURCE__ specifies the SWPMI1 clock source.
AnnaBridge 156:ff21514d8981 1593 * This parameter can be one of the following values:
AnnaBridge 156:ff21514d8981 1594 * @arg @ref RCC_SWPMI1CLKSOURCE_PCLK1 PCLK1 Clock selected as SWPMI1 clock
AnnaBridge 156:ff21514d8981 1595 * @arg @ref RCC_SWPMI1CLKSOURCE_HSI HSI Clock selected as SWPMI1 clock
AnnaBridge 156:ff21514d8981 1596 * @retval None
AnnaBridge 156:ff21514d8981 1597 */
AnnaBridge 156:ff21514d8981 1598 #define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1_CLKSOURCE__) \
AnnaBridge 156:ff21514d8981 1599 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL, (uint32_t)(__SWPMI1_CLKSOURCE__))
AnnaBridge 156:ff21514d8981 1600
AnnaBridge 156:ff21514d8981 1601 /** @brief Macro to get the SWPMI1 clock source.
AnnaBridge 156:ff21514d8981 1602 * @retval The clock source can be one of the following values:
AnnaBridge 156:ff21514d8981 1603 * @arg @ref RCC_SWPMI1CLKSOURCE_PCLK1 PCLK1 Clock selected as SWPMI1 clock
AnnaBridge 156:ff21514d8981 1604 * @arg @ref RCC_SWPMI1CLKSOURCE_HSI HSI Clock selected as SWPMI1 clock
AnnaBridge 156:ff21514d8981 1605 */
AnnaBridge 156:ff21514d8981 1606 #define __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL)))
AnnaBridge 156:ff21514d8981 1607
AnnaBridge 156:ff21514d8981 1608 #endif /* SWPMI1 */
AnnaBridge 156:ff21514d8981 1609
AnnaBridge 156:ff21514d8981 1610 #if defined(DFSDM1_Filter0)
AnnaBridge 156:ff21514d8981 1611 /** @brief Macro to configure the DFSDM1 clock.
AnnaBridge 156:ff21514d8981 1612 * @param __DFSDM1_CLKSOURCE__ specifies the DFSDM1 clock source.
AnnaBridge 156:ff21514d8981 1613 * This parameter can be one of the following values:
AnnaBridge 156:ff21514d8981 1614 * @arg @ref RCC_DFSDM1CLKSOURCE_PCLK2 PCLK2 Clock selected as DFSDM1 clock
AnnaBridge 156:ff21514d8981 1615 * @arg @ref RCC_DFSDM1CLKSOURCE_SYSCLK System Clock selected as DFSDM1 clock
AnnaBridge 156:ff21514d8981 1616 * @retval None
AnnaBridge 156:ff21514d8981 1617 */
AnnaBridge 156:ff21514d8981 1618 #define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \
AnnaBridge 156:ff21514d8981 1619 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL, (uint32_t)(__DFSDM1_CLKSOURCE__))
AnnaBridge 156:ff21514d8981 1620
AnnaBridge 156:ff21514d8981 1621 /** @brief Macro to get the DFSDM1 clock source.
AnnaBridge 156:ff21514d8981 1622 * @retval The clock source can be one of the following values:
AnnaBridge 156:ff21514d8981 1623 * @arg @ref RCC_DFSDM1CLKSOURCE_PCLK2 PCLK2 Clock selected as DFSDM1 clock
AnnaBridge 156:ff21514d8981 1624 * @arg @ref RCC_DFSDM1CLKSOURCE_SYSCLK System Clock selected as DFSDM1 clock
AnnaBridge 156:ff21514d8981 1625 */
AnnaBridge 156:ff21514d8981 1626 #define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL)))
AnnaBridge 156:ff21514d8981 1627
AnnaBridge 156:ff21514d8981 1628 #endif /* DFSDM1_Filter0 */
AnnaBridge 156:ff21514d8981 1629
AnnaBridge 156:ff21514d8981 1630 /** @defgroup RCCEx_Flags_Interrupts_Management Flags Interrupts Management
AnnaBridge 156:ff21514d8981 1631 * @brief macros to manage the specified RCC Flags and interrupts.
AnnaBridge 156:ff21514d8981 1632 * @{
AnnaBridge 156:ff21514d8981 1633 */
AnnaBridge 156:ff21514d8981 1634
AnnaBridge 156:ff21514d8981 1635 /** @brief Enable PLLSAI1RDY interrupt.
AnnaBridge 156:ff21514d8981 1636 * @retval None
AnnaBridge 156:ff21514d8981 1637 */
AnnaBridge 156:ff21514d8981 1638 #define __HAL_RCC_PLLSAI1_ENABLE_IT() SET_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE)
AnnaBridge 156:ff21514d8981 1639
AnnaBridge 156:ff21514d8981 1640 /** @brief Disable PLLSAI1RDY interrupt.
AnnaBridge 156:ff21514d8981 1641 * @retval None
AnnaBridge 156:ff21514d8981 1642 */
AnnaBridge 156:ff21514d8981 1643 #define __HAL_RCC_PLLSAI1_DISABLE_IT() CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE)
AnnaBridge 156:ff21514d8981 1644
AnnaBridge 156:ff21514d8981 1645 /** @brief Clear the PLLSAI1RDY interrupt pending bit.
AnnaBridge 156:ff21514d8981 1646 * @retval None
AnnaBridge 156:ff21514d8981 1647 */
AnnaBridge 156:ff21514d8981 1648 #define __HAL_RCC_PLLSAI1_CLEAR_IT() WRITE_REG(RCC->CICR, RCC_CICR_PLLSAI1RDYC)
AnnaBridge 156:ff21514d8981 1649
AnnaBridge 156:ff21514d8981 1650 /** @brief Check whether PLLSAI1RDY interrupt has occurred or not.
AnnaBridge 156:ff21514d8981 1651 * @retval TRUE or FALSE.
AnnaBridge 156:ff21514d8981 1652 */
AnnaBridge 156:ff21514d8981 1653 #define __HAL_RCC_PLLSAI1_GET_IT_SOURCE() (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI1RDYF) == RCC_CIFR_PLLSAI1RDYF)
AnnaBridge 156:ff21514d8981 1654
AnnaBridge 156:ff21514d8981 1655 /** @brief Check whether the PLLSAI1RDY flag is set or not.
AnnaBridge 156:ff21514d8981 1656 * @retval TRUE or FALSE.
AnnaBridge 156:ff21514d8981 1657 */
AnnaBridge 156:ff21514d8981 1658 #define __HAL_RCC_PLLSAI1_GET_FLAG() (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == (RCC_CR_PLLSAI1RDY))
AnnaBridge 156:ff21514d8981 1659
AnnaBridge 156:ff21514d8981 1660 #if defined(RCC_PLLSAI2_SUPPORT)
AnnaBridge 156:ff21514d8981 1661
AnnaBridge 156:ff21514d8981 1662 /** @brief Enable PLLSAI2RDY interrupt.
AnnaBridge 156:ff21514d8981 1663 * @retval None
AnnaBridge 156:ff21514d8981 1664 */
AnnaBridge 156:ff21514d8981 1665 #define __HAL_RCC_PLLSAI2_ENABLE_IT() SET_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE)
AnnaBridge 156:ff21514d8981 1666
AnnaBridge 156:ff21514d8981 1667 /** @brief Disable PLLSAI2RDY interrupt.
AnnaBridge 156:ff21514d8981 1668 * @retval None
AnnaBridge 156:ff21514d8981 1669 */
AnnaBridge 156:ff21514d8981 1670 #define __HAL_RCC_PLLSAI2_DISABLE_IT() CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE)
AnnaBridge 156:ff21514d8981 1671
AnnaBridge 156:ff21514d8981 1672 /** @brief Clear the PLLSAI2RDY interrupt pending bit.
AnnaBridge 156:ff21514d8981 1673 * @retval None
AnnaBridge 156:ff21514d8981 1674 */
AnnaBridge 156:ff21514d8981 1675 #define __HAL_RCC_PLLSAI2_CLEAR_IT() WRITE_REG(RCC->CICR, RCC_CICR_PLLSAI2RDYC)
AnnaBridge 156:ff21514d8981 1676
AnnaBridge 156:ff21514d8981 1677 /** @brief Check whether the PLLSAI2RDY interrupt has occurred or not.
AnnaBridge 156:ff21514d8981 1678 * @retval TRUE or FALSE.
AnnaBridge 156:ff21514d8981 1679 */
AnnaBridge 156:ff21514d8981 1680 #define __HAL_RCC_PLLSAI2_GET_IT_SOURCE() (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI2RDYF) == RCC_CIFR_PLLSAI2RDYF)
AnnaBridge 156:ff21514d8981 1681
AnnaBridge 156:ff21514d8981 1682 /** @brief Check whether the PLLSAI2RDY flag is set or not.
AnnaBridge 156:ff21514d8981 1683 * @retval TRUE or FALSE.
AnnaBridge 156:ff21514d8981 1684 */
AnnaBridge 156:ff21514d8981 1685 #define __HAL_RCC_PLLSAI2_GET_FLAG() (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == (RCC_CR_PLLSAI2RDY))
AnnaBridge 156:ff21514d8981 1686
AnnaBridge 156:ff21514d8981 1687 #endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge 156:ff21514d8981 1688
AnnaBridge 156:ff21514d8981 1689
AnnaBridge 156:ff21514d8981 1690 /**
AnnaBridge 156:ff21514d8981 1691 * @brief Enable the RCC LSE CSS Extended Interrupt Line.
AnnaBridge 156:ff21514d8981 1692 * @retval None
AnnaBridge 156:ff21514d8981 1693 */
AnnaBridge 156:ff21514d8981 1694 #define __HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
AnnaBridge 156:ff21514d8981 1695
AnnaBridge 156:ff21514d8981 1696 /**
AnnaBridge 156:ff21514d8981 1697 * @brief Disable the RCC LSE CSS Extended Interrupt Line.
AnnaBridge 156:ff21514d8981 1698 * @retval None
AnnaBridge 156:ff21514d8981 1699 */
AnnaBridge 156:ff21514d8981 1700 #define __HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
AnnaBridge 156:ff21514d8981 1701
AnnaBridge 156:ff21514d8981 1702 /**
AnnaBridge 156:ff21514d8981 1703 * @brief Enable the RCC LSE CSS Event Line.
AnnaBridge 156:ff21514d8981 1704 * @retval None.
AnnaBridge 156:ff21514d8981 1705 */
AnnaBridge 156:ff21514d8981 1706 #define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
AnnaBridge 156:ff21514d8981 1707
AnnaBridge 156:ff21514d8981 1708 /**
AnnaBridge 156:ff21514d8981 1709 * @brief Disable the RCC LSE CSS Event Line.
AnnaBridge 156:ff21514d8981 1710 * @retval None.
AnnaBridge 156:ff21514d8981 1711 */
AnnaBridge 156:ff21514d8981 1712 #define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
AnnaBridge 156:ff21514d8981 1713
AnnaBridge 156:ff21514d8981 1714
AnnaBridge 156:ff21514d8981 1715 /**
AnnaBridge 156:ff21514d8981 1716 * @brief Enable the RCC LSE CSS Extended Interrupt Falling Trigger.
AnnaBridge 156:ff21514d8981 1717 * @retval None.
AnnaBridge 156:ff21514d8981 1718 */
AnnaBridge 156:ff21514d8981 1719 #define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
AnnaBridge 156:ff21514d8981 1720
AnnaBridge 156:ff21514d8981 1721
AnnaBridge 156:ff21514d8981 1722 /**
AnnaBridge 156:ff21514d8981 1723 * @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger.
AnnaBridge 156:ff21514d8981 1724 * @retval None.
AnnaBridge 156:ff21514d8981 1725 */
AnnaBridge 156:ff21514d8981 1726 #define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
AnnaBridge 156:ff21514d8981 1727
AnnaBridge 156:ff21514d8981 1728
AnnaBridge 156:ff21514d8981 1729 /**
AnnaBridge 156:ff21514d8981 1730 * @brief Enable the RCC LSE CSS Extended Interrupt Rising Trigger.
AnnaBridge 156:ff21514d8981 1731 * @retval None.
AnnaBridge 156:ff21514d8981 1732 */
AnnaBridge 156:ff21514d8981 1733 #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
AnnaBridge 156:ff21514d8981 1734
AnnaBridge 156:ff21514d8981 1735 /**
AnnaBridge 156:ff21514d8981 1736 * @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger.
AnnaBridge 156:ff21514d8981 1737 * @retval None.
AnnaBridge 156:ff21514d8981 1738 */
AnnaBridge 156:ff21514d8981 1739 #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
AnnaBridge 156:ff21514d8981 1740
AnnaBridge 156:ff21514d8981 1741 /**
AnnaBridge 156:ff21514d8981 1742 * @brief Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
AnnaBridge 156:ff21514d8981 1743 * @retval None.
AnnaBridge 156:ff21514d8981 1744 */
AnnaBridge 156:ff21514d8981 1745 #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE() \
AnnaBridge 156:ff21514d8981 1746 do { \
AnnaBridge 156:ff21514d8981 1747 __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); \
AnnaBridge 156:ff21514d8981 1748 __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); \
AnnaBridge 156:ff21514d8981 1749 } while(0)
AnnaBridge 156:ff21514d8981 1750
AnnaBridge 156:ff21514d8981 1751 /**
AnnaBridge 156:ff21514d8981 1752 * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
AnnaBridge 156:ff21514d8981 1753 * @retval None.
AnnaBridge 156:ff21514d8981 1754 */
AnnaBridge 156:ff21514d8981 1755 #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE() \
AnnaBridge 156:ff21514d8981 1756 do { \
AnnaBridge 156:ff21514d8981 1757 __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); \
AnnaBridge 156:ff21514d8981 1758 __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); \
AnnaBridge 156:ff21514d8981 1759 } while(0)
AnnaBridge 156:ff21514d8981 1760
AnnaBridge 156:ff21514d8981 1761 /**
AnnaBridge 156:ff21514d8981 1762 * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not.
AnnaBridge 156:ff21514d8981 1763 * @retval EXTI RCC LSE CSS Line Status.
AnnaBridge 156:ff21514d8981 1764 */
AnnaBridge 156:ff21514d8981 1765 #define __HAL_RCC_LSECSS_EXTI_GET_FLAG() (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS)
AnnaBridge 156:ff21514d8981 1766
AnnaBridge 156:ff21514d8981 1767 /**
AnnaBridge 156:ff21514d8981 1768 * @brief Clear the RCC LSE CSS EXTI flag.
AnnaBridge 156:ff21514d8981 1769 * @retval None.
AnnaBridge 156:ff21514d8981 1770 */
AnnaBridge 156:ff21514d8981 1771 #define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS)
AnnaBridge 156:ff21514d8981 1772
AnnaBridge 156:ff21514d8981 1773 /**
AnnaBridge 156:ff21514d8981 1774 * @brief Generate a Software interrupt on the RCC LSE CSS EXTI line.
AnnaBridge 156:ff21514d8981 1775 * @retval None.
AnnaBridge 156:ff21514d8981 1776 */
AnnaBridge 156:ff21514d8981 1777 #define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS)
AnnaBridge 156:ff21514d8981 1778
AnnaBridge 156:ff21514d8981 1779
AnnaBridge 156:ff21514d8981 1780 #if defined(CRS)
AnnaBridge 156:ff21514d8981 1781
AnnaBridge 156:ff21514d8981 1782 /**
AnnaBridge 156:ff21514d8981 1783 * @brief Enable the specified CRS interrupts.
AnnaBridge 156:ff21514d8981 1784 * @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled.
AnnaBridge 156:ff21514d8981 1785 * This parameter can be any combination of the following values:
AnnaBridge 156:ff21514d8981 1786 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
AnnaBridge 156:ff21514d8981 1787 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
AnnaBridge 156:ff21514d8981 1788 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
AnnaBridge 156:ff21514d8981 1789 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
AnnaBridge 156:ff21514d8981 1790 * @retval None
AnnaBridge 156:ff21514d8981 1791 */
AnnaBridge 156:ff21514d8981 1792 #define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__))
AnnaBridge 156:ff21514d8981 1793
AnnaBridge 156:ff21514d8981 1794 /**
AnnaBridge 156:ff21514d8981 1795 * @brief Disable the specified CRS interrupts.
AnnaBridge 156:ff21514d8981 1796 * @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled.
AnnaBridge 156:ff21514d8981 1797 * This parameter can be any combination of the following values:
AnnaBridge 156:ff21514d8981 1798 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
AnnaBridge 156:ff21514d8981 1799 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
AnnaBridge 156:ff21514d8981 1800 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
AnnaBridge 156:ff21514d8981 1801 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
AnnaBridge 156:ff21514d8981 1802 * @retval None
AnnaBridge 156:ff21514d8981 1803 */
AnnaBridge 156:ff21514d8981 1804 #define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__))
AnnaBridge 156:ff21514d8981 1805
AnnaBridge 156:ff21514d8981 1806 /** @brief Check whether the CRS interrupt has occurred or not.
AnnaBridge 156:ff21514d8981 1807 * @param __INTERRUPT__ specifies the CRS interrupt source to check.
AnnaBridge 156:ff21514d8981 1808 * This parameter can be one of the following values:
AnnaBridge 156:ff21514d8981 1809 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
AnnaBridge 156:ff21514d8981 1810 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
AnnaBridge 156:ff21514d8981 1811 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
AnnaBridge 156:ff21514d8981 1812 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
AnnaBridge 156:ff21514d8981 1813 * @retval The new state of __INTERRUPT__ (SET or RESET).
AnnaBridge 156:ff21514d8981 1814 */
AnnaBridge 156:ff21514d8981 1815 #define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != RESET) ? SET : RESET)
AnnaBridge 156:ff21514d8981 1816
AnnaBridge 156:ff21514d8981 1817 /** @brief Clear the CRS interrupt pending bits
AnnaBridge 156:ff21514d8981 1818 * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
AnnaBridge 156:ff21514d8981 1819 * This parameter can be any combination of the following values:
AnnaBridge 156:ff21514d8981 1820 * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
AnnaBridge 156:ff21514d8981 1821 * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
AnnaBridge 156:ff21514d8981 1822 * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
AnnaBridge 156:ff21514d8981 1823 * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
AnnaBridge 156:ff21514d8981 1824 * @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt
AnnaBridge 156:ff21514d8981 1825 * @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt
AnnaBridge 156:ff21514d8981 1826 * @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt
AnnaBridge 156:ff21514d8981 1827 */
AnnaBridge 156:ff21514d8981 1828 /* CRS IT Error Mask */
AnnaBridge 156:ff21514d8981 1829 #define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS))
AnnaBridge 156:ff21514d8981 1830
AnnaBridge 156:ff21514d8981 1831 #define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \
AnnaBridge 156:ff21514d8981 1832 if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != RESET) \
AnnaBridge 156:ff21514d8981 1833 { \
AnnaBridge 156:ff21514d8981 1834 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \
AnnaBridge 156:ff21514d8981 1835 } \
AnnaBridge 156:ff21514d8981 1836 else \
AnnaBridge 156:ff21514d8981 1837 { \
AnnaBridge 156:ff21514d8981 1838 WRITE_REG(CRS->ICR, (__INTERRUPT__)); \
AnnaBridge 156:ff21514d8981 1839 } \
AnnaBridge 156:ff21514d8981 1840 } while(0)
AnnaBridge 156:ff21514d8981 1841
AnnaBridge 156:ff21514d8981 1842 /**
AnnaBridge 156:ff21514d8981 1843 * @brief Check whether the specified CRS flag is set or not.
AnnaBridge 156:ff21514d8981 1844 * @param __FLAG__ specifies the flag to check.
AnnaBridge 156:ff21514d8981 1845 * This parameter can be one of the following values:
AnnaBridge 156:ff21514d8981 1846 * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK
AnnaBridge 156:ff21514d8981 1847 * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning
AnnaBridge 156:ff21514d8981 1848 * @arg @ref RCC_CRS_FLAG_ERR Error
AnnaBridge 156:ff21514d8981 1849 * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC
AnnaBridge 156:ff21514d8981 1850 * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow
AnnaBridge 156:ff21514d8981 1851 * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error
AnnaBridge 156:ff21514d8981 1852 * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed
AnnaBridge 156:ff21514d8981 1853 * @retval The new state of _FLAG_ (TRUE or FALSE).
AnnaBridge 156:ff21514d8981 1854 */
AnnaBridge 156:ff21514d8981 1855 #define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__))
AnnaBridge 156:ff21514d8981 1856
AnnaBridge 156:ff21514d8981 1857 /**
AnnaBridge 156:ff21514d8981 1858 * @brief Clear the CRS specified FLAG.
AnnaBridge 156:ff21514d8981 1859 * @param __FLAG__ specifies the flag to clear.
AnnaBridge 156:ff21514d8981 1860 * This parameter can be one of the following values:
AnnaBridge 156:ff21514d8981 1861 * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK
AnnaBridge 156:ff21514d8981 1862 * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning
AnnaBridge 156:ff21514d8981 1863 * @arg @ref RCC_CRS_FLAG_ERR Error
AnnaBridge 156:ff21514d8981 1864 * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC
AnnaBridge 156:ff21514d8981 1865 * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow
AnnaBridge 156:ff21514d8981 1866 * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error
AnnaBridge 156:ff21514d8981 1867 * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed
AnnaBridge 156:ff21514d8981 1868 * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR
AnnaBridge 156:ff21514d8981 1869 * @retval None
AnnaBridge 156:ff21514d8981 1870 */
AnnaBridge 156:ff21514d8981 1871
AnnaBridge 156:ff21514d8981 1872 /* CRS Flag Error Mask */
AnnaBridge 156:ff21514d8981 1873 #define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS))
AnnaBridge 156:ff21514d8981 1874
AnnaBridge 156:ff21514d8981 1875 #define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \
AnnaBridge 156:ff21514d8981 1876 if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != RESET) \
AnnaBridge 156:ff21514d8981 1877 { \
AnnaBridge 156:ff21514d8981 1878 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \
AnnaBridge 156:ff21514d8981 1879 } \
AnnaBridge 156:ff21514d8981 1880 else \
AnnaBridge 156:ff21514d8981 1881 { \
AnnaBridge 156:ff21514d8981 1882 WRITE_REG(CRS->ICR, (__FLAG__)); \
AnnaBridge 156:ff21514d8981 1883 } \
AnnaBridge 156:ff21514d8981 1884 } while(0)
AnnaBridge 156:ff21514d8981 1885
AnnaBridge 156:ff21514d8981 1886 #endif /* CRS */
AnnaBridge 156:ff21514d8981 1887
AnnaBridge 156:ff21514d8981 1888 /**
AnnaBridge 156:ff21514d8981 1889 * @}
AnnaBridge 156:ff21514d8981 1890 */
AnnaBridge 156:ff21514d8981 1891
AnnaBridge 156:ff21514d8981 1892 #if defined(CRS)
AnnaBridge 156:ff21514d8981 1893
AnnaBridge 156:ff21514d8981 1894 /** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features
AnnaBridge 156:ff21514d8981 1895 * @{
AnnaBridge 156:ff21514d8981 1896 */
AnnaBridge 156:ff21514d8981 1897 /**
AnnaBridge 156:ff21514d8981 1898 * @brief Enable the oscillator clock for frequency error counter.
AnnaBridge 156:ff21514d8981 1899 * @note when the CEN bit is set the CRS_CFGR register becomes write-protected.
AnnaBridge 156:ff21514d8981 1900 * @retval None
AnnaBridge 156:ff21514d8981 1901 */
AnnaBridge 156:ff21514d8981 1902 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN)
AnnaBridge 156:ff21514d8981 1903
AnnaBridge 156:ff21514d8981 1904 /**
AnnaBridge 156:ff21514d8981 1905 * @brief Disable the oscillator clock for frequency error counter.
AnnaBridge 156:ff21514d8981 1906 * @retval None
AnnaBridge 156:ff21514d8981 1907 */
AnnaBridge 156:ff21514d8981 1908 #define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN)
AnnaBridge 156:ff21514d8981 1909
AnnaBridge 156:ff21514d8981 1910 /**
AnnaBridge 156:ff21514d8981 1911 * @brief Enable the automatic hardware adjustement of TRIM bits.
AnnaBridge 156:ff21514d8981 1912 * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
AnnaBridge 156:ff21514d8981 1913 * @retval None
AnnaBridge 156:ff21514d8981 1914 */
AnnaBridge 156:ff21514d8981 1915 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
AnnaBridge 156:ff21514d8981 1916
AnnaBridge 156:ff21514d8981 1917 /**
AnnaBridge 156:ff21514d8981 1918 * @brief Enable or disable the automatic hardware adjustement of TRIM bits.
AnnaBridge 156:ff21514d8981 1919 * @retval None
AnnaBridge 156:ff21514d8981 1920 */
AnnaBridge 156:ff21514d8981 1921 #define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
AnnaBridge 156:ff21514d8981 1922
AnnaBridge 156:ff21514d8981 1923 /**
AnnaBridge 156:ff21514d8981 1924 * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
AnnaBridge 156:ff21514d8981 1925 * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency
AnnaBridge 156:ff21514d8981 1926 * of the synchronization source after prescaling. It is then decreased by one in order to
AnnaBridge 156:ff21514d8981 1927 * reach the expected synchronization on the zero value. The formula is the following:
AnnaBridge 156:ff21514d8981 1928 * RELOAD = (fTARGET / fSYNC) -1
AnnaBridge 156:ff21514d8981 1929 * @param __FTARGET__ Target frequency (value in Hz)
AnnaBridge 156:ff21514d8981 1930 * @param __FSYNC__ Synchronization signal frequency (value in Hz)
AnnaBridge 156:ff21514d8981 1931 * @retval None
AnnaBridge 156:ff21514d8981 1932 */
AnnaBridge 156:ff21514d8981 1933 #define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
AnnaBridge 156:ff21514d8981 1934
AnnaBridge 156:ff21514d8981 1935 /**
AnnaBridge 156:ff21514d8981 1936 * @}
AnnaBridge 156:ff21514d8981 1937 */
AnnaBridge 156:ff21514d8981 1938
AnnaBridge 156:ff21514d8981 1939 #endif /* CRS */
AnnaBridge 156:ff21514d8981 1940
AnnaBridge 156:ff21514d8981 1941 /**
AnnaBridge 156:ff21514d8981 1942 * @}
AnnaBridge 156:ff21514d8981 1943 */
AnnaBridge 156:ff21514d8981 1944
AnnaBridge 156:ff21514d8981 1945 /* Exported functions --------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 1946 /** @addtogroup RCCEx_Exported_Functions
AnnaBridge 156:ff21514d8981 1947 * @{
AnnaBridge 156:ff21514d8981 1948 */
AnnaBridge 156:ff21514d8981 1949
AnnaBridge 156:ff21514d8981 1950 /** @addtogroup RCCEx_Exported_Functions_Group1
AnnaBridge 156:ff21514d8981 1951 * @{
AnnaBridge 156:ff21514d8981 1952 */
AnnaBridge 156:ff21514d8981 1953
AnnaBridge 156:ff21514d8981 1954 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
AnnaBridge 156:ff21514d8981 1955 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
AnnaBridge 156:ff21514d8981 1956 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
AnnaBridge 156:ff21514d8981 1957
AnnaBridge 156:ff21514d8981 1958 /**
AnnaBridge 156:ff21514d8981 1959 * @}
AnnaBridge 156:ff21514d8981 1960 */
AnnaBridge 156:ff21514d8981 1961
AnnaBridge 156:ff21514d8981 1962 /** @addtogroup RCCEx_Exported_Functions_Group2
AnnaBridge 156:ff21514d8981 1963 * @{
AnnaBridge 156:ff21514d8981 1964 */
AnnaBridge 156:ff21514d8981 1965
AnnaBridge 156:ff21514d8981 1966 HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1(RCC_PLLSAI1InitTypeDef *PLLSAI1Init);
AnnaBridge 156:ff21514d8981 1967 HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI1(void);
AnnaBridge 156:ff21514d8981 1968
AnnaBridge 156:ff21514d8981 1969 #if defined(RCC_PLLSAI2_SUPPORT)
AnnaBridge 156:ff21514d8981 1970
AnnaBridge 156:ff21514d8981 1971 HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI2(RCC_PLLSAI2InitTypeDef *PLLSAI2Init);
AnnaBridge 156:ff21514d8981 1972 HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI2(void);
AnnaBridge 156:ff21514d8981 1973
AnnaBridge 156:ff21514d8981 1974 #endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge 156:ff21514d8981 1975
AnnaBridge 156:ff21514d8981 1976 void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk);
AnnaBridge 156:ff21514d8981 1977 void HAL_RCCEx_StandbyMSIRangeConfig(uint32_t MSIRange);
AnnaBridge 156:ff21514d8981 1978 void HAL_RCCEx_EnableLSECSS(void);
AnnaBridge 156:ff21514d8981 1979 void HAL_RCCEx_DisableLSECSS(void);
AnnaBridge 156:ff21514d8981 1980 void HAL_RCCEx_EnableLSECSS_IT(void);
AnnaBridge 156:ff21514d8981 1981 void HAL_RCCEx_LSECSS_IRQHandler(void);
AnnaBridge 156:ff21514d8981 1982 void HAL_RCCEx_LSECSS_Callback(void);
AnnaBridge 156:ff21514d8981 1983 void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource);
AnnaBridge 156:ff21514d8981 1984 void HAL_RCCEx_DisableLSCO(void);
AnnaBridge 156:ff21514d8981 1985 void HAL_RCCEx_EnableMSIPLLMode(void);
AnnaBridge 156:ff21514d8981 1986 void HAL_RCCEx_DisableMSIPLLMode(void);
AnnaBridge 156:ff21514d8981 1987
AnnaBridge 156:ff21514d8981 1988 /**
AnnaBridge 156:ff21514d8981 1989 * @}
AnnaBridge 156:ff21514d8981 1990 */
AnnaBridge 156:ff21514d8981 1991
AnnaBridge 156:ff21514d8981 1992 #if defined(CRS)
AnnaBridge 156:ff21514d8981 1993
AnnaBridge 156:ff21514d8981 1994 /** @addtogroup RCCEx_Exported_Functions_Group3
AnnaBridge 156:ff21514d8981 1995 * @{
AnnaBridge 156:ff21514d8981 1996 */
AnnaBridge 156:ff21514d8981 1997
AnnaBridge 156:ff21514d8981 1998 void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
AnnaBridge 156:ff21514d8981 1999 void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
AnnaBridge 156:ff21514d8981 2000 void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
AnnaBridge 156:ff21514d8981 2001 uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
AnnaBridge 156:ff21514d8981 2002 void HAL_RCCEx_CRS_IRQHandler(void);
AnnaBridge 156:ff21514d8981 2003 void HAL_RCCEx_CRS_SyncOkCallback(void);
AnnaBridge 156:ff21514d8981 2004 void HAL_RCCEx_CRS_SyncWarnCallback(void);
AnnaBridge 156:ff21514d8981 2005 void HAL_RCCEx_CRS_ExpectedSyncCallback(void);
AnnaBridge 156:ff21514d8981 2006 void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error);
AnnaBridge 156:ff21514d8981 2007
AnnaBridge 156:ff21514d8981 2008 /**
AnnaBridge 156:ff21514d8981 2009 * @}
AnnaBridge 156:ff21514d8981 2010 */
AnnaBridge 156:ff21514d8981 2011
AnnaBridge 156:ff21514d8981 2012 #endif /* CRS */
AnnaBridge 156:ff21514d8981 2013
AnnaBridge 156:ff21514d8981 2014 /**
AnnaBridge 156:ff21514d8981 2015 * @}
AnnaBridge 156:ff21514d8981 2016 */
AnnaBridge 156:ff21514d8981 2017
AnnaBridge 156:ff21514d8981 2018 /* Private macros ------------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 2019 /** @addtogroup RCCEx_Private_Macros
AnnaBridge 156:ff21514d8981 2020 * @{
AnnaBridge 156:ff21514d8981 2021 */
AnnaBridge 156:ff21514d8981 2022
AnnaBridge 156:ff21514d8981 2023 #define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \
AnnaBridge 156:ff21514d8981 2024 ((__SOURCE__) == RCC_LSCOSOURCE_LSE))
AnnaBridge 156:ff21514d8981 2025
AnnaBridge 156:ff21514d8981 2026 #if defined(STM32L431xx)
AnnaBridge 156:ff21514d8981 2027
AnnaBridge 156:ff21514d8981 2028 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \
AnnaBridge 156:ff21514d8981 2029 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
AnnaBridge 156:ff21514d8981 2030 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
AnnaBridge 156:ff21514d8981 2031 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
AnnaBridge 156:ff21514d8981 2032 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
AnnaBridge 156:ff21514d8981 2033 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
AnnaBridge 156:ff21514d8981 2034 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
AnnaBridge 156:ff21514d8981 2035 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
AnnaBridge 156:ff21514d8981 2036 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
AnnaBridge 156:ff21514d8981 2037 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
AnnaBridge 156:ff21514d8981 2038 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
AnnaBridge 156:ff21514d8981 2039 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
AnnaBridge 156:ff21514d8981 2040 (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \
AnnaBridge 156:ff21514d8981 2041 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
AnnaBridge 156:ff21514d8981 2042 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
AnnaBridge 156:ff21514d8981 2043 (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1))
AnnaBridge 156:ff21514d8981 2044
AnnaBridge 156:ff21514d8981 2045 #elif defined(STM32L432xx) || defined(STM32L442xx)
AnnaBridge 156:ff21514d8981 2046
AnnaBridge 156:ff21514d8981 2047 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \
AnnaBridge 156:ff21514d8981 2048 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
AnnaBridge 156:ff21514d8981 2049 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
AnnaBridge 156:ff21514d8981 2050 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
AnnaBridge 156:ff21514d8981 2051 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
AnnaBridge 156:ff21514d8981 2052 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
AnnaBridge 156:ff21514d8981 2053 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
AnnaBridge 156:ff21514d8981 2054 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
AnnaBridge 156:ff21514d8981 2055 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
AnnaBridge 156:ff21514d8981 2056 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
AnnaBridge 156:ff21514d8981 2057 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
AnnaBridge 156:ff21514d8981 2058 (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \
AnnaBridge 156:ff21514d8981 2059 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
AnnaBridge 156:ff21514d8981 2060 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG))
AnnaBridge 156:ff21514d8981 2061
AnnaBridge 156:ff21514d8981 2062 #elif defined(STM32L433xx) || defined(STM32L443xx)
AnnaBridge 156:ff21514d8981 2063
AnnaBridge 156:ff21514d8981 2064 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \
AnnaBridge 156:ff21514d8981 2065 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
AnnaBridge 156:ff21514d8981 2066 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
AnnaBridge 156:ff21514d8981 2067 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
AnnaBridge 156:ff21514d8981 2068 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
AnnaBridge 156:ff21514d8981 2069 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
AnnaBridge 156:ff21514d8981 2070 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
AnnaBridge 156:ff21514d8981 2071 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
AnnaBridge 156:ff21514d8981 2072 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
AnnaBridge 156:ff21514d8981 2073 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
AnnaBridge 156:ff21514d8981 2074 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
AnnaBridge 156:ff21514d8981 2075 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
AnnaBridge 156:ff21514d8981 2076 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
AnnaBridge 156:ff21514d8981 2077 (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \
AnnaBridge 156:ff21514d8981 2078 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
AnnaBridge 156:ff21514d8981 2079 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
AnnaBridge 156:ff21514d8981 2080 (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1))
AnnaBridge 156:ff21514d8981 2081
AnnaBridge 156:ff21514d8981 2082 #elif defined(STM32L451xx)
AnnaBridge 156:ff21514d8981 2083
AnnaBridge 156:ff21514d8981 2084 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \
AnnaBridge 156:ff21514d8981 2085 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
AnnaBridge 156:ff21514d8981 2086 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
AnnaBridge 156:ff21514d8981 2087 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
AnnaBridge 156:ff21514d8981 2088 (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
AnnaBridge 156:ff21514d8981 2089 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
AnnaBridge 156:ff21514d8981 2090 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
AnnaBridge 156:ff21514d8981 2091 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
AnnaBridge 156:ff21514d8981 2092 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
AnnaBridge 156:ff21514d8981 2093 (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \
AnnaBridge 156:ff21514d8981 2094 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
AnnaBridge 156:ff21514d8981 2095 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
AnnaBridge 156:ff21514d8981 2096 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
AnnaBridge 156:ff21514d8981 2097 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
AnnaBridge 156:ff21514d8981 2098 (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \
AnnaBridge 156:ff21514d8981 2099 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
AnnaBridge 156:ff21514d8981 2100 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
AnnaBridge 156:ff21514d8981 2101 (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1))
AnnaBridge 156:ff21514d8981 2102
AnnaBridge 156:ff21514d8981 2103 #elif defined(STM32L452xx) || defined(STM32L462xx)
AnnaBridge 156:ff21514d8981 2104
AnnaBridge 156:ff21514d8981 2105 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \
AnnaBridge 156:ff21514d8981 2106 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
AnnaBridge 156:ff21514d8981 2107 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
AnnaBridge 156:ff21514d8981 2108 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
AnnaBridge 156:ff21514d8981 2109 (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
AnnaBridge 156:ff21514d8981 2110 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
AnnaBridge 156:ff21514d8981 2111 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
AnnaBridge 156:ff21514d8981 2112 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
AnnaBridge 156:ff21514d8981 2113 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
AnnaBridge 156:ff21514d8981 2114 (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \
AnnaBridge 156:ff21514d8981 2115 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
AnnaBridge 156:ff21514d8981 2116 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
AnnaBridge 156:ff21514d8981 2117 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
AnnaBridge 156:ff21514d8981 2118 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
AnnaBridge 156:ff21514d8981 2119 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
AnnaBridge 156:ff21514d8981 2120 (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \
AnnaBridge 156:ff21514d8981 2121 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
AnnaBridge 156:ff21514d8981 2122 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
AnnaBridge 156:ff21514d8981 2123 (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1))
AnnaBridge 156:ff21514d8981 2124
AnnaBridge 156:ff21514d8981 2125 #elif defined(STM32L471xx)
AnnaBridge 156:ff21514d8981 2126
AnnaBridge 156:ff21514d8981 2127 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \
AnnaBridge 156:ff21514d8981 2128 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
AnnaBridge 156:ff21514d8981 2129 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
AnnaBridge 156:ff21514d8981 2130 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
AnnaBridge 156:ff21514d8981 2131 (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
AnnaBridge 156:ff21514d8981 2132 (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
AnnaBridge 156:ff21514d8981 2133 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
AnnaBridge 156:ff21514d8981 2134 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
AnnaBridge 156:ff21514d8981 2135 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
AnnaBridge 156:ff21514d8981 2136 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
AnnaBridge 156:ff21514d8981 2137 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
AnnaBridge 156:ff21514d8981 2138 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
AnnaBridge 156:ff21514d8981 2139 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
AnnaBridge 156:ff21514d8981 2140 (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \
AnnaBridge 156:ff21514d8981 2141 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
AnnaBridge 156:ff21514d8981 2142 (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \
AnnaBridge 156:ff21514d8981 2143 (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \
AnnaBridge 156:ff21514d8981 2144 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
AnnaBridge 156:ff21514d8981 2145 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
AnnaBridge 156:ff21514d8981 2146 (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1))
AnnaBridge 156:ff21514d8981 2147
AnnaBridge 156:ff21514d8981 2148 #elif defined(STM32L496xx) || defined(STM32L4A6xx)
AnnaBridge 156:ff21514d8981 2149
AnnaBridge 156:ff21514d8981 2150 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \
AnnaBridge 156:ff21514d8981 2151 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
AnnaBridge 156:ff21514d8981 2152 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
AnnaBridge 156:ff21514d8981 2153 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
AnnaBridge 156:ff21514d8981 2154 (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
AnnaBridge 156:ff21514d8981 2155 (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
AnnaBridge 156:ff21514d8981 2156 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
AnnaBridge 156:ff21514d8981 2157 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
AnnaBridge 156:ff21514d8981 2158 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
AnnaBridge 156:ff21514d8981 2159 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
AnnaBridge 156:ff21514d8981 2160 (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \
AnnaBridge 156:ff21514d8981 2161 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
AnnaBridge 156:ff21514d8981 2162 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
AnnaBridge 156:ff21514d8981 2163 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
AnnaBridge 156:ff21514d8981 2164 (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \
AnnaBridge 156:ff21514d8981 2165 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
AnnaBridge 156:ff21514d8981 2166 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
AnnaBridge 156:ff21514d8981 2167 (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \
AnnaBridge 156:ff21514d8981 2168 (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \
AnnaBridge 156:ff21514d8981 2169 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
AnnaBridge 156:ff21514d8981 2170 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
AnnaBridge 156:ff21514d8981 2171 (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1))
AnnaBridge 156:ff21514d8981 2172
AnnaBridge 156:ff21514d8981 2173 #else
AnnaBridge 156:ff21514d8981 2174
AnnaBridge 156:ff21514d8981 2175 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \
AnnaBridge 156:ff21514d8981 2176 ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
AnnaBridge 156:ff21514d8981 2177 (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
AnnaBridge 156:ff21514d8981 2178 (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
AnnaBridge 156:ff21514d8981 2179 (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
AnnaBridge 156:ff21514d8981 2180 (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
AnnaBridge 156:ff21514d8981 2181 (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
AnnaBridge 156:ff21514d8981 2182 (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
AnnaBridge 156:ff21514d8981 2183 (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
AnnaBridge 156:ff21514d8981 2184 (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
AnnaBridge 156:ff21514d8981 2185 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
AnnaBridge 156:ff21514d8981 2186 (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
AnnaBridge 156:ff21514d8981 2187 (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
AnnaBridge 156:ff21514d8981 2188 (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \
AnnaBridge 156:ff21514d8981 2189 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
AnnaBridge 156:ff21514d8981 2190 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
AnnaBridge 156:ff21514d8981 2191 (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \
AnnaBridge 156:ff21514d8981 2192 (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \
AnnaBridge 156:ff21514d8981 2193 (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
AnnaBridge 156:ff21514d8981 2194 (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
AnnaBridge 156:ff21514d8981 2195 (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1))
AnnaBridge 156:ff21514d8981 2196
AnnaBridge 156:ff21514d8981 2197 #endif /* STM32L431xx */
AnnaBridge 156:ff21514d8981 2198
AnnaBridge 156:ff21514d8981 2199 #define IS_RCC_USART1CLKSOURCE(__SOURCE__) \
AnnaBridge 156:ff21514d8981 2200 (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \
AnnaBridge 156:ff21514d8981 2201 ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \
AnnaBridge 156:ff21514d8981 2202 ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \
AnnaBridge 156:ff21514d8981 2203 ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI))
AnnaBridge 156:ff21514d8981 2204
AnnaBridge 156:ff21514d8981 2205 #define IS_RCC_USART2CLKSOURCE(__SOURCE__) \
AnnaBridge 156:ff21514d8981 2206 (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \
AnnaBridge 156:ff21514d8981 2207 ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \
AnnaBridge 156:ff21514d8981 2208 ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) || \
AnnaBridge 156:ff21514d8981 2209 ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI))
AnnaBridge 156:ff21514d8981 2210
AnnaBridge 156:ff21514d8981 2211 #if defined(USART3)
AnnaBridge 156:ff21514d8981 2212
AnnaBridge 156:ff21514d8981 2213 #define IS_RCC_USART3CLKSOURCE(__SOURCE__) \
AnnaBridge 156:ff21514d8981 2214 (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \
AnnaBridge 156:ff21514d8981 2215 ((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \
AnnaBridge 156:ff21514d8981 2216 ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE) || \
AnnaBridge 156:ff21514d8981 2217 ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI))
AnnaBridge 156:ff21514d8981 2218
AnnaBridge 156:ff21514d8981 2219 #endif /* USART3 */
AnnaBridge 156:ff21514d8981 2220
AnnaBridge 156:ff21514d8981 2221 #if defined(UART4)
AnnaBridge 156:ff21514d8981 2222
AnnaBridge 156:ff21514d8981 2223 #define IS_RCC_UART4CLKSOURCE(__SOURCE__) \
AnnaBridge 156:ff21514d8981 2224 (((__SOURCE__) == RCC_UART4CLKSOURCE_PCLK1) || \
AnnaBridge 156:ff21514d8981 2225 ((__SOURCE__) == RCC_UART4CLKSOURCE_SYSCLK) || \
AnnaBridge 156:ff21514d8981 2226 ((__SOURCE__) == RCC_UART4CLKSOURCE_LSE) || \
AnnaBridge 156:ff21514d8981 2227 ((__SOURCE__) == RCC_UART4CLKSOURCE_HSI))
AnnaBridge 156:ff21514d8981 2228
AnnaBridge 156:ff21514d8981 2229 #endif /* UART4 */
AnnaBridge 156:ff21514d8981 2230
AnnaBridge 156:ff21514d8981 2231 #if defined(UART5)
AnnaBridge 156:ff21514d8981 2232
AnnaBridge 156:ff21514d8981 2233 #define IS_RCC_UART5CLKSOURCE(__SOURCE__) \
AnnaBridge 156:ff21514d8981 2234 (((__SOURCE__) == RCC_UART5CLKSOURCE_PCLK1) || \
AnnaBridge 156:ff21514d8981 2235 ((__SOURCE__) == RCC_UART5CLKSOURCE_SYSCLK) || \
AnnaBridge 156:ff21514d8981 2236 ((__SOURCE__) == RCC_UART5CLKSOURCE_LSE) || \
AnnaBridge 156:ff21514d8981 2237 ((__SOURCE__) == RCC_UART5CLKSOURCE_HSI))
AnnaBridge 156:ff21514d8981 2238
AnnaBridge 156:ff21514d8981 2239 #endif /* UART5 */
AnnaBridge 156:ff21514d8981 2240
AnnaBridge 156:ff21514d8981 2241 #define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) \
AnnaBridge 156:ff21514d8981 2242 (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1) || \
AnnaBridge 156:ff21514d8981 2243 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \
AnnaBridge 156:ff21514d8981 2244 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \
AnnaBridge 156:ff21514d8981 2245 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI))
AnnaBridge 156:ff21514d8981 2246
AnnaBridge 156:ff21514d8981 2247 #define IS_RCC_I2C1CLKSOURCE(__SOURCE__) \
AnnaBridge 156:ff21514d8981 2248 (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \
AnnaBridge 156:ff21514d8981 2249 ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| \
AnnaBridge 156:ff21514d8981 2250 ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI))
AnnaBridge 156:ff21514d8981 2251
AnnaBridge 156:ff21514d8981 2252 #if defined(I2C2)
AnnaBridge 156:ff21514d8981 2253
AnnaBridge 156:ff21514d8981 2254 #define IS_RCC_I2C2CLKSOURCE(__SOURCE__) \
AnnaBridge 156:ff21514d8981 2255 (((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \
AnnaBridge 156:ff21514d8981 2256 ((__SOURCE__) == RCC_I2C2CLKSOURCE_SYSCLK)|| \
AnnaBridge 156:ff21514d8981 2257 ((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI))
AnnaBridge 156:ff21514d8981 2258
AnnaBridge 156:ff21514d8981 2259 #endif /* I2C2 */
AnnaBridge 156:ff21514d8981 2260
AnnaBridge 156:ff21514d8981 2261 #define IS_RCC_I2C3CLKSOURCE(__SOURCE__) \
AnnaBridge 156:ff21514d8981 2262 (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \
AnnaBridge 156:ff21514d8981 2263 ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| \
AnnaBridge 156:ff21514d8981 2264 ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI))
AnnaBridge 156:ff21514d8981 2265
AnnaBridge 156:ff21514d8981 2266 #if defined(I2C4)
AnnaBridge 156:ff21514d8981 2267
AnnaBridge 156:ff21514d8981 2268 #define IS_RCC_I2C4CLKSOURCE(__SOURCE__) \
AnnaBridge 156:ff21514d8981 2269 (((__SOURCE__) == RCC_I2C4CLKSOURCE_PCLK1) || \
AnnaBridge 156:ff21514d8981 2270 ((__SOURCE__) == RCC_I2C4CLKSOURCE_SYSCLK)|| \
AnnaBridge 156:ff21514d8981 2271 ((__SOURCE__) == RCC_I2C4CLKSOURCE_HSI))
AnnaBridge 156:ff21514d8981 2272
AnnaBridge 156:ff21514d8981 2273 #endif /* I2C4 */
AnnaBridge 156:ff21514d8981 2274
AnnaBridge 156:ff21514d8981 2275 #if defined(RCC_PLLSAI2_SUPPORT)
AnnaBridge 156:ff21514d8981 2276
AnnaBridge 156:ff21514d8981 2277 #define IS_RCC_SAI1CLK(__SOURCE__) \
AnnaBridge 156:ff21514d8981 2278 (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \
AnnaBridge 156:ff21514d8981 2279 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI2) || \
AnnaBridge 156:ff21514d8981 2280 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \
AnnaBridge 156:ff21514d8981 2281 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN))
AnnaBridge 156:ff21514d8981 2282
AnnaBridge 156:ff21514d8981 2283 #else
AnnaBridge 156:ff21514d8981 2284
AnnaBridge 156:ff21514d8981 2285 #define IS_RCC_SAI1CLK(__SOURCE__) \
AnnaBridge 156:ff21514d8981 2286 (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \
AnnaBridge 156:ff21514d8981 2287 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \
AnnaBridge 156:ff21514d8981 2288 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN))
AnnaBridge 156:ff21514d8981 2289
AnnaBridge 156:ff21514d8981 2290 #endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge 156:ff21514d8981 2291
AnnaBridge 156:ff21514d8981 2292 #if defined(RCC_PLLSAI2_SUPPORT)
AnnaBridge 156:ff21514d8981 2293
AnnaBridge 156:ff21514d8981 2294 #define IS_RCC_SAI2CLK(__SOURCE__) \
AnnaBridge 156:ff21514d8981 2295 (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI1) || \
AnnaBridge 156:ff21514d8981 2296 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI2) || \
AnnaBridge 156:ff21514d8981 2297 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL) || \
AnnaBridge 156:ff21514d8981 2298 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN))
AnnaBridge 156:ff21514d8981 2299
AnnaBridge 156:ff21514d8981 2300 #endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge 156:ff21514d8981 2301
AnnaBridge 156:ff21514d8981 2302 #define IS_RCC_LPTIM1CLK(__SOURCE__) \
AnnaBridge 156:ff21514d8981 2303 (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK1) || \
AnnaBridge 156:ff21514d8981 2304 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) || \
AnnaBridge 156:ff21514d8981 2305 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI) || \
AnnaBridge 156:ff21514d8981 2306 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE))
AnnaBridge 156:ff21514d8981 2307
AnnaBridge 156:ff21514d8981 2308 #define IS_RCC_LPTIM2CLK(__SOURCE__) \
AnnaBridge 156:ff21514d8981 2309 (((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK1) || \
AnnaBridge 156:ff21514d8981 2310 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI) || \
AnnaBridge 156:ff21514d8981 2311 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_HSI) || \
AnnaBridge 156:ff21514d8981 2312 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE))
AnnaBridge 156:ff21514d8981 2313
AnnaBridge 156:ff21514d8981 2314 #if defined(SDMMC1)
AnnaBridge 156:ff21514d8981 2315 #if defined(RCC_HSI48_SUPPORT)
AnnaBridge 156:ff21514d8981 2316
AnnaBridge 156:ff21514d8981 2317 #define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__) \
AnnaBridge 156:ff21514d8981 2318 (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_HSI48) || \
AnnaBridge 156:ff21514d8981 2319 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) || \
AnnaBridge 156:ff21514d8981 2320 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL) || \
AnnaBridge 156:ff21514d8981 2321 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI))
AnnaBridge 156:ff21514d8981 2322
AnnaBridge 156:ff21514d8981 2323 #else
AnnaBridge 156:ff21514d8981 2324
AnnaBridge 156:ff21514d8981 2325 #define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__) \
AnnaBridge 156:ff21514d8981 2326 (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_NONE) || \
AnnaBridge 156:ff21514d8981 2327 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) || \
AnnaBridge 156:ff21514d8981 2328 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL) || \
AnnaBridge 156:ff21514d8981 2329 ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI))
AnnaBridge 156:ff21514d8981 2330
AnnaBridge 156:ff21514d8981 2331 #endif /* RCC_HSI48_SUPPORT */
AnnaBridge 156:ff21514d8981 2332 #endif /* SDMMC1 */
AnnaBridge 156:ff21514d8981 2333
AnnaBridge 156:ff21514d8981 2334 #if defined(RCC_HSI48_SUPPORT)
AnnaBridge 156:ff21514d8981 2335
AnnaBridge 156:ff21514d8981 2336 #define IS_RCC_RNGCLKSOURCE(__SOURCE__) \
AnnaBridge 156:ff21514d8981 2337 (((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48) || \
AnnaBridge 156:ff21514d8981 2338 ((__SOURCE__) == RCC_RNGCLKSOURCE_PLLSAI1) || \
AnnaBridge 156:ff21514d8981 2339 ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL) || \
AnnaBridge 156:ff21514d8981 2340 ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI))
AnnaBridge 156:ff21514d8981 2341
AnnaBridge 156:ff21514d8981 2342 #else
AnnaBridge 156:ff21514d8981 2343
AnnaBridge 156:ff21514d8981 2344 #define IS_RCC_RNGCLKSOURCE(__SOURCE__) \
AnnaBridge 156:ff21514d8981 2345 (((__SOURCE__) == RCC_RNGCLKSOURCE_NONE) || \
AnnaBridge 156:ff21514d8981 2346 ((__SOURCE__) == RCC_RNGCLKSOURCE_PLLSAI1) || \
AnnaBridge 156:ff21514d8981 2347 ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL) || \
AnnaBridge 156:ff21514d8981 2348 ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI))
AnnaBridge 156:ff21514d8981 2349
AnnaBridge 156:ff21514d8981 2350 #endif /* RCC_HSI48_SUPPORT */
AnnaBridge 156:ff21514d8981 2351
AnnaBridge 156:ff21514d8981 2352 #if defined(USB_OTG_FS) || defined(USB)
AnnaBridge 156:ff21514d8981 2353 #if defined(RCC_HSI48_SUPPORT)
AnnaBridge 156:ff21514d8981 2354
AnnaBridge 156:ff21514d8981 2355 #define IS_RCC_USBCLKSOURCE(__SOURCE__) \
AnnaBridge 156:ff21514d8981 2356 (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) || \
AnnaBridge 156:ff21514d8981 2357 ((__SOURCE__) == RCC_USBCLKSOURCE_PLLSAI1) || \
AnnaBridge 156:ff21514d8981 2358 ((__SOURCE__) == RCC_USBCLKSOURCE_PLL) || \
AnnaBridge 156:ff21514d8981 2359 ((__SOURCE__) == RCC_USBCLKSOURCE_MSI))
AnnaBridge 156:ff21514d8981 2360
AnnaBridge 156:ff21514d8981 2361 #else
AnnaBridge 156:ff21514d8981 2362
AnnaBridge 156:ff21514d8981 2363 #define IS_RCC_USBCLKSOURCE(__SOURCE__) \
AnnaBridge 156:ff21514d8981 2364 (((__SOURCE__) == RCC_USBCLKSOURCE_NONE) || \
AnnaBridge 156:ff21514d8981 2365 ((__SOURCE__) == RCC_USBCLKSOURCE_PLLSAI1) || \
AnnaBridge 156:ff21514d8981 2366 ((__SOURCE__) == RCC_USBCLKSOURCE_PLL) || \
AnnaBridge 156:ff21514d8981 2367 ((__SOURCE__) == RCC_USBCLKSOURCE_MSI))
AnnaBridge 156:ff21514d8981 2368
AnnaBridge 156:ff21514d8981 2369 #endif /* RCC_HSI48_SUPPORT */
AnnaBridge 156:ff21514d8981 2370 #endif /* USB_OTG_FS || USB */
AnnaBridge 156:ff21514d8981 2371
AnnaBridge 156:ff21514d8981 2372 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)
AnnaBridge 156:ff21514d8981 2373
AnnaBridge 156:ff21514d8981 2374 #define IS_RCC_ADCCLKSOURCE(__SOURCE__) \
AnnaBridge 156:ff21514d8981 2375 (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \
AnnaBridge 156:ff21514d8981 2376 ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI1) || \
AnnaBridge 156:ff21514d8981 2377 ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI2) || \
AnnaBridge 156:ff21514d8981 2378 ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK))
AnnaBridge 156:ff21514d8981 2379
AnnaBridge 156:ff21514d8981 2380 #else
AnnaBridge 156:ff21514d8981 2381
AnnaBridge 156:ff21514d8981 2382 #define IS_RCC_ADCCLKSOURCE(__SOURCE__) \
AnnaBridge 156:ff21514d8981 2383 (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \
AnnaBridge 156:ff21514d8981 2384 ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI1) || \
AnnaBridge 156:ff21514d8981 2385 ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK))
AnnaBridge 156:ff21514d8981 2386
AnnaBridge 156:ff21514d8981 2387 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */
AnnaBridge 156:ff21514d8981 2388
AnnaBridge 156:ff21514d8981 2389 #if defined(SWPMI1)
AnnaBridge 156:ff21514d8981 2390
AnnaBridge 156:ff21514d8981 2391 #define IS_RCC_SWPMI1CLKSOURCE(__SOURCE__) \
AnnaBridge 156:ff21514d8981 2392 (((__SOURCE__) == RCC_SWPMI1CLKSOURCE_PCLK1) || \
AnnaBridge 156:ff21514d8981 2393 ((__SOURCE__) == RCC_SWPMI1CLKSOURCE_HSI))
AnnaBridge 156:ff21514d8981 2394
AnnaBridge 156:ff21514d8981 2395 #endif /* SWPMI1 */
AnnaBridge 156:ff21514d8981 2396
AnnaBridge 156:ff21514d8981 2397 #if defined(DFSDM1_Filter0)
AnnaBridge 156:ff21514d8981 2398
AnnaBridge 156:ff21514d8981 2399 #define IS_RCC_DFSDM1CLKSOURCE(__SOURCE__) \
AnnaBridge 156:ff21514d8981 2400 (((__SOURCE__) == RCC_DFSDM1CLKSOURCE_PCLK2) || \
AnnaBridge 156:ff21514d8981 2401 ((__SOURCE__) == RCC_DFSDM1CLKSOURCE_SYSCLK))
AnnaBridge 156:ff21514d8981 2402
AnnaBridge 156:ff21514d8981 2403 #endif /* DFSDM1_Filter0 */
AnnaBridge 156:ff21514d8981 2404
AnnaBridge 156:ff21514d8981 2405 #define IS_RCC_PLLSAI1SOURCE(__VALUE__) IS_RCC_PLLSOURCE(__VALUE__)
AnnaBridge 156:ff21514d8981 2406
AnnaBridge 156:ff21514d8981 2407 #define IS_RCC_PLLSAI1M_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U))
AnnaBridge 156:ff21514d8981 2408
AnnaBridge 156:ff21514d8981 2409 #define IS_RCC_PLLSAI1N_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))
AnnaBridge 156:ff21514d8981 2410
AnnaBridge 156:ff21514d8981 2411 #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
AnnaBridge 156:ff21514d8981 2412 #define IS_RCC_PLLSAI1P_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U))
AnnaBridge 156:ff21514d8981 2413 #else
AnnaBridge 156:ff21514d8981 2414 #define IS_RCC_PLLSAI1P_VALUE(__VALUE__) (((__VALUE__) == 7U) || ((__VALUE__) == 17U))
AnnaBridge 156:ff21514d8981 2415 #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
AnnaBridge 156:ff21514d8981 2416
AnnaBridge 156:ff21514d8981 2417 #define IS_RCC_PLLSAI1Q_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
AnnaBridge 156:ff21514d8981 2418 ((__VALUE__) == 6U) || ((__VALUE__) == 8U))
AnnaBridge 156:ff21514d8981 2419
AnnaBridge 156:ff21514d8981 2420 #define IS_RCC_PLLSAI1R_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
AnnaBridge 156:ff21514d8981 2421 ((__VALUE__) == 6U) || ((__VALUE__) == 8U))
AnnaBridge 156:ff21514d8981 2422
AnnaBridge 156:ff21514d8981 2423 #if defined(RCC_PLLSAI2_SUPPORT)
AnnaBridge 156:ff21514d8981 2424
AnnaBridge 156:ff21514d8981 2425 #define IS_RCC_PLLSAI2SOURCE(__VALUE__) IS_RCC_PLLSOURCE(__VALUE__)
AnnaBridge 156:ff21514d8981 2426
AnnaBridge 156:ff21514d8981 2427 #define IS_RCC_PLLSAI2M_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U))
AnnaBridge 156:ff21514d8981 2428
AnnaBridge 156:ff21514d8981 2429 #define IS_RCC_PLLSAI2N_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))
AnnaBridge 156:ff21514d8981 2430
AnnaBridge 156:ff21514d8981 2431 #if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
AnnaBridge 156:ff21514d8981 2432 #define IS_RCC_PLLSAI2P_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U))
AnnaBridge 156:ff21514d8981 2433 #else
AnnaBridge 156:ff21514d8981 2434 #define IS_RCC_PLLSAI2P_VALUE(__VALUE__) (((__VALUE__) == 7U) || ((__VALUE__) == 17U))
AnnaBridge 156:ff21514d8981 2435 #endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */
AnnaBridge 156:ff21514d8981 2436
AnnaBridge 156:ff21514d8981 2437 #define IS_RCC_PLLSAI2R_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
AnnaBridge 156:ff21514d8981 2438 ((__VALUE__) == 6U) || ((__VALUE__) == 8U))
AnnaBridge 156:ff21514d8981 2439
AnnaBridge 156:ff21514d8981 2440 #endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge 156:ff21514d8981 2441
AnnaBridge 156:ff21514d8981 2442 #if defined(CRS)
AnnaBridge 156:ff21514d8981 2443
AnnaBridge 156:ff21514d8981 2444 #define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \
AnnaBridge 156:ff21514d8981 2445 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \
AnnaBridge 156:ff21514d8981 2446 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB))
AnnaBridge 156:ff21514d8981 2447
AnnaBridge 156:ff21514d8981 2448 #define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2) || \
AnnaBridge 156:ff21514d8981 2449 ((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8) || \
AnnaBridge 156:ff21514d8981 2450 ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \
AnnaBridge 156:ff21514d8981 2451 ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128))
AnnaBridge 156:ff21514d8981 2452
AnnaBridge 156:ff21514d8981 2453 #define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \
AnnaBridge 156:ff21514d8981 2454 ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING))
AnnaBridge 156:ff21514d8981 2455
AnnaBridge 156:ff21514d8981 2456 #define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU))
AnnaBridge 156:ff21514d8981 2457
AnnaBridge 156:ff21514d8981 2458 #define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU))
AnnaBridge 156:ff21514d8981 2459
AnnaBridge 156:ff21514d8981 2460 #define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU))
AnnaBridge 156:ff21514d8981 2461
AnnaBridge 156:ff21514d8981 2462 #define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \
AnnaBridge 156:ff21514d8981 2463 ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN))
AnnaBridge 156:ff21514d8981 2464
AnnaBridge 156:ff21514d8981 2465 #endif /* CRS */
AnnaBridge 156:ff21514d8981 2466
AnnaBridge 156:ff21514d8981 2467 /**
AnnaBridge 156:ff21514d8981 2468 * @}
AnnaBridge 156:ff21514d8981 2469 */
AnnaBridge 156:ff21514d8981 2470
AnnaBridge 156:ff21514d8981 2471 /**
AnnaBridge 156:ff21514d8981 2472 * @}
AnnaBridge 156:ff21514d8981 2473 */
AnnaBridge 156:ff21514d8981 2474
AnnaBridge 156:ff21514d8981 2475 /**
AnnaBridge 156:ff21514d8981 2476 * @}
AnnaBridge 156:ff21514d8981 2477 */
AnnaBridge 156:ff21514d8981 2478
AnnaBridge 156:ff21514d8981 2479 #ifdef __cplusplus
AnnaBridge 156:ff21514d8981 2480 }
AnnaBridge 156:ff21514d8981 2481 #endif
AnnaBridge 156:ff21514d8981 2482
AnnaBridge 156:ff21514d8981 2483 #endif /* __STM32L4xx_HAL_RCC_EX_H */
AnnaBridge 156:ff21514d8981 2484
AnnaBridge 156:ff21514d8981 2485 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/