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Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

TARGET_NUCLEO_F334R8/stm32f3xx_hal_rcc_ex.h@123:b0220dba8be7, 2016-08-12 (annotated)

Committer:
Kojto
Date:
Fri Aug 12 13:04:35 2016 +0200
Revision:
123:b0220dba8be7
Parent:
122:f9eeca106725 
Release 123 of the mbed library



Changes:

- new targets: nucleo_f207zg, beetle, nrf51_dk, hexiwear,

 nuvoton nuc472, vk rz a1h

- ST - fix timer interrupt handler, sleep api fix

- NXP - lpc15xx us ticker fix

- Nordic - analogin fixes, LF clock init addition, enable i2c async

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 86:04dd9b1680ae 1 /**
bogdanm 86:04dd9b1680ae 2 ******************************************************************************
bogdanm 86:04dd9b1680ae 3 * @file stm32f3xx_hal_rcc_ex.h
bogdanm 86:04dd9b1680ae 4 * @author MCD Application Team
Kojto 123:b0220dba8be7 5 * @version V1.3.0
Kojto 123:b0220dba8be7 6 * @date 01-July-2016
Kojto 122:f9eeca106725 7 * @brief Header file of RCC HAL Extension module.
bogdanm 86:04dd9b1680ae 8 ******************************************************************************
bogdanm 86:04dd9b1680ae 9 * @attention
bogdanm 86:04dd9b1680ae 10 *
Kojto 122:f9eeca106725 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
bogdanm 86:04dd9b1680ae 12 *
bogdanm 86:04dd9b1680ae 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 86:04dd9b1680ae 14 * are permitted provided that the following conditions are met:
bogdanm 86:04dd9b1680ae 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 86:04dd9b1680ae 16 * this list of conditions and the following disclaimer.
bogdanm 86:04dd9b1680ae 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 86:04dd9b1680ae 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 86:04dd9b1680ae 19 * and/or other materials provided with the distribution.
bogdanm 86:04dd9b1680ae 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 86:04dd9b1680ae 21 * may be used to endorse or promote products derived from this software
bogdanm 86:04dd9b1680ae 22 * without specific prior written permission.
bogdanm 86:04dd9b1680ae 23 *
bogdanm 86:04dd9b1680ae 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 86:04dd9b1680ae 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 86:04dd9b1680ae 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 86:04dd9b1680ae 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 86:04dd9b1680ae 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 86:04dd9b1680ae 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 86:04dd9b1680ae 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 86:04dd9b1680ae 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 86:04dd9b1680ae 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 86:04dd9b1680ae 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 86:04dd9b1680ae 34 *
bogdanm 86:04dd9b1680ae 35 ******************************************************************************
bogdanm 86:04dd9b1680ae 36 */
bogdanm 86:04dd9b1680ae 37
bogdanm 86:04dd9b1680ae 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 86:04dd9b1680ae 39 #ifndef __STM32F3xx_HAL_RCC_EX_H
bogdanm 86:04dd9b1680ae 40 #define __STM32F3xx_HAL_RCC_EX_H
bogdanm 86:04dd9b1680ae 41
bogdanm 86:04dd9b1680ae 42 #ifdef __cplusplus
bogdanm 86:04dd9b1680ae 43 extern "C" {
bogdanm 86:04dd9b1680ae 44 #endif
bogdanm 86:04dd9b1680ae 45
bogdanm 86:04dd9b1680ae 46 /* Includes ------------------------------------------------------------------*/
bogdanm 86:04dd9b1680ae 47 #include "stm32f3xx_hal_def.h"
bogdanm 86:04dd9b1680ae 48
bogdanm 86:04dd9b1680ae 49 /** @addtogroup STM32F3xx_HAL_Driver
bogdanm 86:04dd9b1680ae 50 * @{
bogdanm 86:04dd9b1680ae 51 */
bogdanm 86:04dd9b1680ae 52
bogdanm 92:4fc01daae5a5 53 /** @addtogroup RCCEx
bogdanm 86:04dd9b1680ae 54 * @{
bogdanm 86:04dd9b1680ae 55 */
bogdanm 86:04dd9b1680ae 56
Kojto 122:f9eeca106725 57 /** @addtogroup RCCEx_Private_Macros
Kojto 122:f9eeca106725 58 * @{
Kojto 122:f9eeca106725 59 */
Kojto 122:f9eeca106725 60
Kojto 122:f9eeca106725 61 #if defined(RCC_CFGR_PLLNODIV)
Kojto 122:f9eeca106725 62 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) || \
Kojto 122:f9eeca106725 63 ((SOURCE) == RCC_MCO1SOURCE_LSI) || \
Kojto 122:f9eeca106725 64 ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
Kojto 122:f9eeca106725 65 ((SOURCE) == RCC_MCO1SOURCE_SYSCLK) || \
Kojto 122:f9eeca106725 66 ((SOURCE) == RCC_MCO1SOURCE_HSI) || \
Kojto 122:f9eeca106725 67 ((SOURCE) == RCC_MCO1SOURCE_HSE) || \
Kojto 122:f9eeca106725 68 ((SOURCE) == RCC_MCO1SOURCE_PLLCLK) || \
Kojto 122:f9eeca106725 69 ((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2))
Kojto 122:f9eeca106725 70 #else
Kojto 122:f9eeca106725 71 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) || \
Kojto 122:f9eeca106725 72 ((SOURCE) == RCC_MCO1SOURCE_LSI) || \
Kojto 122:f9eeca106725 73 ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
Kojto 122:f9eeca106725 74 ((SOURCE) == RCC_MCO1SOURCE_SYSCLK) || \
Kojto 122:f9eeca106725 75 ((SOURCE) == RCC_MCO1SOURCE_HSI) || \
Kojto 122:f9eeca106725 76 ((SOURCE) == RCC_MCO1SOURCE_HSE) || \
Kojto 122:f9eeca106725 77 ((SOURCE) == RCC_MCO1SOURCE_PLLCLK_DIV2))
Kojto 122:f9eeca106725 78 #endif /* RCC_CFGR_PLLNODIV */
Kojto 122:f9eeca106725 79
Kojto 122:f9eeca106725 80 #if defined(STM32F301x8) || defined(STM32F318xx)
Kojto 122:f9eeca106725 81 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | \
Kojto 122:f9eeca106725 82 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
Kojto 122:f9eeca106725 83 RCC_PERIPHCLK_ADC1 | RCC_PERIPHCLK_I2S | \
Kojto 122:f9eeca106725 84 RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_TIM1 | \
Kojto 122:f9eeca106725 85 RCC_PERIPHCLK_TIM15 | RCC_PERIPHCLK_TIM16 | \
Kojto 122:f9eeca106725 86 RCC_PERIPHCLK_TIM17 | RCC_PERIPHCLK_RTC))
Kojto 122:f9eeca106725 87 #endif /* STM32F301x8 || STM32F318xx */
Kojto 122:f9eeca106725 88 #if defined(STM32F302x8)
Kojto 122:f9eeca106725 89 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | \
Kojto 122:f9eeca106725 90 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
Kojto 122:f9eeca106725 91 RCC_PERIPHCLK_ADC1 | RCC_PERIPHCLK_I2S | \
Kojto 122:f9eeca106725 92 RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_TIM1 | \
Kojto 122:f9eeca106725 93 RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USB | \
Kojto 122:f9eeca106725 94 RCC_PERIPHCLK_TIM15 | RCC_PERIPHCLK_TIM16 | \
Kojto 122:f9eeca106725 95 RCC_PERIPHCLK_TIM17))
Kojto 122:f9eeca106725 96 #endif /* STM32F302x8 */
Kojto 122:f9eeca106725 97 #if defined(STM32F302xC)
Kojto 122:f9eeca106725 98 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
Kojto 122:f9eeca106725 99 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
Kojto 122:f9eeca106725 100 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
Kojto 122:f9eeca106725 101 RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_I2S | \
Kojto 122:f9eeca106725 102 RCC_PERIPHCLK_TIM1 | RCC_PERIPHCLK_RTC | \
Kojto 122:f9eeca106725 103 RCC_PERIPHCLK_USB))
Kojto 122:f9eeca106725 104 #endif /* STM32F302xC */
Kojto 122:f9eeca106725 105 #if defined(STM32F303xC)
Kojto 122:f9eeca106725 106 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
Kojto 122:f9eeca106725 107 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
Kojto 122:f9eeca106725 108 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
Kojto 122:f9eeca106725 109 RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_ADC34 | \
Kojto 122:f9eeca106725 110 RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_TIM1 | \
Kojto 122:f9eeca106725 111 RCC_PERIPHCLK_TIM8 | RCC_PERIPHCLK_RTC | \
Kojto 122:f9eeca106725 112 RCC_PERIPHCLK_USB))
Kojto 122:f9eeca106725 113 #endif /* STM32F303xC */
Kojto 122:f9eeca106725 114 #if defined(STM32F302xE)
Kojto 122:f9eeca106725 115 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
Kojto 122:f9eeca106725 116 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
Kojto 122:f9eeca106725 117 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
Kojto 122:f9eeca106725 118 RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_I2S | \
Kojto 122:f9eeca106725 119 RCC_PERIPHCLK_TIM1 | RCC_PERIPHCLK_RTC | \
Kojto 122:f9eeca106725 120 RCC_PERIPHCLK_USB | RCC_PERIPHCLK_I2C3 | \
Kojto 122:f9eeca106725 121 RCC_PERIPHCLK_TIM2 | RCC_PERIPHCLK_TIM34 | \
Kojto 122:f9eeca106725 122 RCC_PERIPHCLK_TIM15 | RCC_PERIPHCLK_TIM16 | \
Kojto 122:f9eeca106725 123 RCC_PERIPHCLK_TIM17))
Kojto 122:f9eeca106725 124 #endif /* STM32F302xE */
Kojto 122:f9eeca106725 125 #if defined(STM32F303xE)
Kojto 122:f9eeca106725 126 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
Kojto 122:f9eeca106725 127 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
Kojto 122:f9eeca106725 128 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
Kojto 122:f9eeca106725 129 RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_ADC34 | \
Kojto 122:f9eeca106725 130 RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_TIM1 | \
Kojto 122:f9eeca106725 131 RCC_PERIPHCLK_TIM8 | RCC_PERIPHCLK_RTC | \
Kojto 122:f9eeca106725 132 RCC_PERIPHCLK_USB | RCC_PERIPHCLK_I2C3 | \
Kojto 122:f9eeca106725 133 RCC_PERIPHCLK_TIM2 | RCC_PERIPHCLK_TIM34 | \
Kojto 122:f9eeca106725 134 RCC_PERIPHCLK_TIM15 | RCC_PERIPHCLK_TIM16 | \
Kojto 122:f9eeca106725 135 RCC_PERIPHCLK_TIM17 | RCC_PERIPHCLK_TIM20))
Kojto 122:f9eeca106725 136 #endif /* STM32F303xE */
Kojto 122:f9eeca106725 137 #if defined(STM32F398xx)
Kojto 122:f9eeca106725 138 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
Kojto 122:f9eeca106725 139 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
Kojto 122:f9eeca106725 140 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
Kojto 122:f9eeca106725 141 RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_ADC34 | \
Kojto 122:f9eeca106725 142 RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_TIM1 | \
Kojto 122:f9eeca106725 143 RCC_PERIPHCLK_TIM8 | RCC_PERIPHCLK_RTC | \
Kojto 122:f9eeca106725 144 RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_TIM2 | \
Kojto 122:f9eeca106725 145 RCC_PERIPHCLK_TIM34 | RCC_PERIPHCLK_TIM15 | \
Kojto 122:f9eeca106725 146 RCC_PERIPHCLK_TIM16 | RCC_PERIPHCLK_TIM17 | \
Kojto 122:f9eeca106725 147 RCC_PERIPHCLK_TIM20))
Kojto 122:f9eeca106725 148 #endif /* STM32F398xx */
Kojto 122:f9eeca106725 149 #if defined(STM32F358xx)
Kojto 122:f9eeca106725 150 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
Kojto 122:f9eeca106725 151 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
Kojto 122:f9eeca106725 152 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
Kojto 122:f9eeca106725 153 RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_ADC34 | \
Kojto 122:f9eeca106725 154 RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_TIM1 | \
Kojto 122:f9eeca106725 155 RCC_PERIPHCLK_TIM8 | RCC_PERIPHCLK_RTC))
Kojto 122:f9eeca106725 156 #endif /* STM32F358xx */
Kojto 122:f9eeca106725 157 #if defined(STM32F303x8)
Kojto 122:f9eeca106725 158 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | \
Kojto 122:f9eeca106725 159 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_ADC12 | \
Kojto 122:f9eeca106725 160 RCC_PERIPHCLK_TIM1 | RCC_PERIPHCLK_RTC))
Kojto 122:f9eeca106725 161 #endif /* STM32F303x8 */
Kojto 122:f9eeca106725 162 #if defined(STM32F334x8)
Kojto 122:f9eeca106725 163 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | \
Kojto 122:f9eeca106725 164 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_ADC12 | \
Kojto 122:f9eeca106725 165 RCC_PERIPHCLK_TIM1 | RCC_PERIPHCLK_HRTIM1 | \
Kojto 122:f9eeca106725 166 RCC_PERIPHCLK_RTC))
Kojto 122:f9eeca106725 167 #endif /* STM32F334x8 */
Kojto 122:f9eeca106725 168 #if defined(STM32F328xx)
Kojto 122:f9eeca106725 169 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | \
Kojto 122:f9eeca106725 170 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_ADC12 | \
Kojto 122:f9eeca106725 171 RCC_PERIPHCLK_TIM1 | RCC_PERIPHCLK_RTC))
Kojto 122:f9eeca106725 172 #endif /* STM32F328xx */
Kojto 122:f9eeca106725 173 #if defined(STM32F373xC)
Kojto 122:f9eeca106725 174 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
Kojto 122:f9eeca106725 175 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
Kojto 122:f9eeca106725 176 RCC_PERIPHCLK_ADC1 | RCC_PERIPHCLK_SDADC | \
Kojto 122:f9eeca106725 177 RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC | \
Kojto 122:f9eeca106725 178 RCC_PERIPHCLK_USB))
Kojto 122:f9eeca106725 179 #endif /* STM32F373xC */
Kojto 122:f9eeca106725 180 #if defined(STM32F378xx)
Kojto 122:f9eeca106725 181 #define IS_RCC_PERIPHCLOCK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
Kojto 122:f9eeca106725 182 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
Kojto 122:f9eeca106725 183 RCC_PERIPHCLK_ADC1 | RCC_PERIPHCLK_SDADC | \
Kojto 122:f9eeca106725 184 RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC))
Kojto 122:f9eeca106725 185 #endif /* STM32F378xx */
Kojto 122:f9eeca106725 186
Kojto 122:f9eeca106725 187 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
Kojto 122:f9eeca106725 188 #define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK1) || \
Kojto 122:f9eeca106725 189 ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
Kojto 122:f9eeca106725 190 ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \
Kojto 122:f9eeca106725 191 ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
Kojto 122:f9eeca106725 192 #define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \
Kojto 122:f9eeca106725 193 ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK))
Kojto 122:f9eeca106725 194 #define IS_RCC_I2C3CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C3CLKSOURCE_HSI) || \
Kojto 122:f9eeca106725 195 ((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK))
Kojto 122:f9eeca106725 196 #define IS_RCC_ADC1PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC1PLLCLK_OFF) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV1) || \
Kojto 122:f9eeca106725 197 ((ADCCLK) == RCC_ADC1PLLCLK_DIV2) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV4) || \
Kojto 122:f9eeca106725 198 ((ADCCLK) == RCC_ADC1PLLCLK_DIV6) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV8) || \
Kojto 122:f9eeca106725 199 ((ADCCLK) == RCC_ADC1PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV12) || \
Kojto 122:f9eeca106725 200 ((ADCCLK) == RCC_ADC1PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV32) || \
Kojto 122:f9eeca106725 201 ((ADCCLK) == RCC_ADC1PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV128) || \
Kojto 122:f9eeca106725 202 ((ADCCLK) == RCC_ADC1PLLCLK_DIV256))
Kojto 122:f9eeca106725 203 #define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_SYSCLK) || \
Kojto 122:f9eeca106725 204 ((SOURCE) == RCC_I2SCLKSOURCE_EXT))
Kojto 122:f9eeca106725 205 #define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) || \
Kojto 122:f9eeca106725 206 ((SOURCE) == RCC_TIM1CLK_PLLCLK))
Kojto 122:f9eeca106725 207 #define IS_RCC_TIM15CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM15CLK_HCLK) || \
Kojto 122:f9eeca106725 208 ((SOURCE) == RCC_TIM15CLK_PLLCLK))
Kojto 122:f9eeca106725 209 #define IS_RCC_TIM16CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM16CLK_HCLK) || \
Kojto 122:f9eeca106725 210 ((SOURCE) == RCC_TIM16CLK_PLLCLK))
Kojto 122:f9eeca106725 211 #define IS_RCC_TIM17CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM17CLK_HCLK) || \
Kojto 122:f9eeca106725 212 ((SOURCE) == RCC_TIM17CLK_PLLCLK))
Kojto 122:f9eeca106725 213 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
Kojto 122:f9eeca106725 214 #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
Kojto 122:f9eeca106725 215 #define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) || \
Kojto 122:f9eeca106725 216 ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
Kojto 122:f9eeca106725 217 ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \
Kojto 122:f9eeca106725 218 ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
Kojto 122:f9eeca106725 219 #define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \
Kojto 122:f9eeca106725 220 ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK))
Kojto 122:f9eeca106725 221 #define IS_RCC_ADC12PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV1) || \
Kojto 122:f9eeca106725 222 ((ADCCLK) == RCC_ADC12PLLCLK_DIV2) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV4) || \
Kojto 122:f9eeca106725 223 ((ADCCLK) == RCC_ADC12PLLCLK_DIV6) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV8) || \
Kojto 122:f9eeca106725 224 ((ADCCLK) == RCC_ADC12PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV12) || \
Kojto 122:f9eeca106725 225 ((ADCCLK) == RCC_ADC12PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV32) || \
Kojto 122:f9eeca106725 226 ((ADCCLK) == RCC_ADC12PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV128) || \
Kojto 122:f9eeca106725 227 ((ADCCLK) == RCC_ADC12PLLCLK_DIV256))
Kojto 122:f9eeca106725 228 #define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_SYSCLK) || \
Kojto 122:f9eeca106725 229 ((SOURCE) == RCC_I2SCLKSOURCE_EXT))
Kojto 122:f9eeca106725 230 #define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) || \
Kojto 122:f9eeca106725 231 ((SOURCE) == RCC_TIM1CLK_PLLCLK))
Kojto 122:f9eeca106725 232 #define IS_RCC_UART4CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART4CLKSOURCE_PCLK1) || \
Kojto 122:f9eeca106725 233 ((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) || \
Kojto 122:f9eeca106725 234 ((SOURCE) == RCC_UART4CLKSOURCE_LSE) || \
Kojto 122:f9eeca106725 235 ((SOURCE) == RCC_UART4CLKSOURCE_HSI))
Kojto 122:f9eeca106725 236 #define IS_RCC_UART5CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART5CLKSOURCE_PCLK1) || \
Kojto 122:f9eeca106725 237 ((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) || \
Kojto 122:f9eeca106725 238 ((SOURCE) == RCC_UART5CLKSOURCE_LSE) || \
Kojto 122:f9eeca106725 239 ((SOURCE) == RCC_UART5CLKSOURCE_HSI))
Kojto 122:f9eeca106725 240 #endif /* STM32F302xC || STM32F303xC || STM32F358xx */
bogdanm 92:4fc01daae5a5 241 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
Kojto 122:f9eeca106725 242 #define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) || \
Kojto 122:f9eeca106725 243 ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
Kojto 122:f9eeca106725 244 ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \
Kojto 122:f9eeca106725 245 ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
Kojto 122:f9eeca106725 246 #define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \
Kojto 122:f9eeca106725 247 ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK))
Kojto 122:f9eeca106725 248 #define IS_RCC_I2C3CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C3CLKSOURCE_HSI) || \
Kojto 122:f9eeca106725 249 ((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK))
Kojto 122:f9eeca106725 250 #define IS_RCC_ADC12PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV1) || \
Kojto 122:f9eeca106725 251 ((ADCCLK) == RCC_ADC12PLLCLK_DIV2) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV4) || \
Kojto 122:f9eeca106725 252 ((ADCCLK) == RCC_ADC12PLLCLK_DIV6) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV8) || \
Kojto 122:f9eeca106725 253 ((ADCCLK) == RCC_ADC12PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV12) || \
Kojto 122:f9eeca106725 254 ((ADCCLK) == RCC_ADC12PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV32) || \
Kojto 122:f9eeca106725 255 ((ADCCLK) == RCC_ADC12PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV128) || \
Kojto 122:f9eeca106725 256 ((ADCCLK) == RCC_ADC12PLLCLK_DIV256))
Kojto 122:f9eeca106725 257 #define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_SYSCLK) || \
Kojto 122:f9eeca106725 258 ((SOURCE) == RCC_I2SCLKSOURCE_EXT))
Kojto 122:f9eeca106725 259 #define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) || \
Kojto 122:f9eeca106725 260 ((SOURCE) == RCC_TIM1CLK_PLLCLK))
Kojto 122:f9eeca106725 261 #define IS_RCC_TIM2CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM2CLK_HCLK) || \
Kojto 122:f9eeca106725 262 ((SOURCE) == RCC_TIM2CLK_PLLCLK))
Kojto 122:f9eeca106725 263 #define IS_RCC_TIM3CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM34CLK_HCLK) || \
Kojto 122:f9eeca106725 264 ((SOURCE) == RCC_TIM34CLK_PLLCLK))
Kojto 122:f9eeca106725 265 #define IS_RCC_TIM15CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM15CLK_HCLK) || \
Kojto 122:f9eeca106725 266 ((SOURCE) == RCC_TIM15CLK_PLLCLK))
Kojto 122:f9eeca106725 267 #define IS_RCC_TIM16CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM16CLK_HCLK) || \
Kojto 122:f9eeca106725 268 ((SOURCE) == RCC_TIM16CLK_PLLCLK))
Kojto 122:f9eeca106725 269 #define IS_RCC_TIM17CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM17CLK_HCLK) || \
Kojto 122:f9eeca106725 270 ((SOURCE) == RCC_TIM17CLK_PLLCLK))
Kojto 122:f9eeca106725 271 #define IS_RCC_UART4CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART4CLKSOURCE_PCLK1) || \
Kojto 122:f9eeca106725 272 ((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) || \
Kojto 122:f9eeca106725 273 ((SOURCE) == RCC_UART4CLKSOURCE_LSE) || \
Kojto 122:f9eeca106725 274 ((SOURCE) == RCC_UART4CLKSOURCE_HSI))
Kojto 122:f9eeca106725 275 #define IS_RCC_UART5CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART5CLKSOURCE_PCLK1) || \
Kojto 122:f9eeca106725 276 ((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) || \
Kojto 122:f9eeca106725 277 ((SOURCE) == RCC_UART5CLKSOURCE_LSE) || \
Kojto 122:f9eeca106725 278 ((SOURCE) == RCC_UART5CLKSOURCE_HSI))
Kojto 122:f9eeca106725 279 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
Kojto 122:f9eeca106725 280 #if defined(STM32F303xE) || defined(STM32F398xx)
Kojto 122:f9eeca106725 281 #define IS_RCC_TIM20CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM20CLK_HCLK) || \
Kojto 122:f9eeca106725 282 ((SOURCE) == RCC_TIM20CLK_PLLCLK))
Kojto 122:f9eeca106725 283 #endif /* STM32F303xE || STM32F398xx */
Kojto 122:f9eeca106725 284 #if defined(STM32F303xE) || defined(STM32F398xx)\
Kojto 122:f9eeca106725 285 || defined(STM32F303xC) || defined(STM32F358xx)
Kojto 122:f9eeca106725 286 #define IS_RCC_ADC34PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC34PLLCLK_OFF) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV1) || \
Kojto 122:f9eeca106725 287 ((ADCCLK) == RCC_ADC34PLLCLK_DIV2) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV4) || \
Kojto 122:f9eeca106725 288 ((ADCCLK) == RCC_ADC34PLLCLK_DIV6) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV8) || \
Kojto 122:f9eeca106725 289 ((ADCCLK) == RCC_ADC34PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV12) || \
Kojto 122:f9eeca106725 290 ((ADCCLK) == RCC_ADC34PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV32) || \
Kojto 122:f9eeca106725 291 ((ADCCLK) == RCC_ADC34PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV128) || \
Kojto 122:f9eeca106725 292 ((ADCCLK) == RCC_ADC34PLLCLK_DIV256))
Kojto 122:f9eeca106725 293 #define IS_RCC_TIM8CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM8CLK_HCLK) || \
Kojto 122:f9eeca106725 294 ((SOURCE) == RCC_TIM8CLK_PLLCLK))
Kojto 122:f9eeca106725 295 #endif /* STM32F303xC || STM32F303xE || STM32F398xx || STM32F358xx */
Kojto 122:f9eeca106725 296 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
Kojto 122:f9eeca106725 297 #define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK1) || \
Kojto 122:f9eeca106725 298 ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
Kojto 122:f9eeca106725 299 ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \
Kojto 122:f9eeca106725 300 ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
Kojto 122:f9eeca106725 301 #define IS_RCC_ADC12PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV1) || \
Kojto 122:f9eeca106725 302 ((ADCCLK) == RCC_ADC12PLLCLK_DIV2) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV4) || \
Kojto 122:f9eeca106725 303 ((ADCCLK) == RCC_ADC12PLLCLK_DIV6) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV8) || \
Kojto 122:f9eeca106725 304 ((ADCCLK) == RCC_ADC12PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV12) || \
Kojto 122:f9eeca106725 305 ((ADCCLK) == RCC_ADC12PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV32) || \
Kojto 122:f9eeca106725 306 ((ADCCLK) == RCC_ADC12PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV128) || \
Kojto 122:f9eeca106725 307 ((ADCCLK) == RCC_ADC12PLLCLK_DIV256))
Kojto 122:f9eeca106725 308 #define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) || \
Kojto 122:f9eeca106725 309 ((SOURCE) == RCC_TIM1CLK_PLLCLK))
Kojto 122:f9eeca106725 310 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
Kojto 122:f9eeca106725 311 #if defined(STM32F334x8)
Kojto 122:f9eeca106725 312 #define IS_RCC_HRTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_HRTIM1CLK_HCLK) || \
Kojto 122:f9eeca106725 313 ((SOURCE) == RCC_HRTIM1CLK_PLLCLK))
Kojto 122:f9eeca106725 314 #endif /* STM32F334x8 */
Kojto 122:f9eeca106725 315 #if defined(STM32F373xC) || defined(STM32F378xx)
Kojto 122:f9eeca106725 316 #define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) || \
Kojto 122:f9eeca106725 317 ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
Kojto 122:f9eeca106725 318 ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \
Kojto 122:f9eeca106725 319 ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
Kojto 122:f9eeca106725 320 #define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \
Kojto 122:f9eeca106725 321 ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK))
Kojto 122:f9eeca106725 322 #define IS_RCC_ADC1PCLK2_DIV(ADCCLK) (((ADCCLK) == RCC_ADC1PCLK2_DIV2) || ((ADCCLK) == RCC_ADC1PCLK2_DIV4) || \
Kojto 122:f9eeca106725 323 ((ADCCLK) == RCC_ADC1PCLK2_DIV6) || ((ADCCLK) == RCC_ADC1PCLK2_DIV8))
Kojto 122:f9eeca106725 324 #define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) || \
Kojto 122:f9eeca106725 325 ((SOURCE) == RCC_CECCLKSOURCE_LSE))
Kojto 122:f9eeca106725 326 #define IS_RCC_SDADCSYSCLK_DIV(DIV) (((DIV) == RCC_SDADCSYSCLK_DIV1) || ((DIV) == RCC_SDADCSYSCLK_DIV2) || \
Kojto 122:f9eeca106725 327 ((DIV) == RCC_SDADCSYSCLK_DIV4) || ((DIV) == RCC_SDADCSYSCLK_DIV6) || \
Kojto 122:f9eeca106725 328 ((DIV) == RCC_SDADCSYSCLK_DIV8) || ((DIV) == RCC_SDADCSYSCLK_DIV10) || \
Kojto 122:f9eeca106725 329 ((DIV) == RCC_SDADCSYSCLK_DIV12) || ((DIV) == RCC_SDADCSYSCLK_DIV14) || \
Kojto 122:f9eeca106725 330 ((DIV) == RCC_SDADCSYSCLK_DIV16) || ((DIV) == RCC_SDADCSYSCLK_DIV20) || \
Kojto 122:f9eeca106725 331 ((DIV) == RCC_SDADCSYSCLK_DIV24) || ((DIV) == RCC_SDADCSYSCLK_DIV28) || \
Kojto 122:f9eeca106725 332 ((DIV) == RCC_SDADCSYSCLK_DIV32) || ((DIV) == RCC_SDADCSYSCLK_DIV36) || \
Kojto 122:f9eeca106725 333 ((DIV) == RCC_SDADCSYSCLK_DIV40) || ((DIV) == RCC_SDADCSYSCLK_DIV44) || \
Kojto 122:f9eeca106725 334 ((DIV) == RCC_SDADCSYSCLK_DIV48))
Kojto 122:f9eeca106725 335 #endif /* STM32F373xC || STM32F378xx */
Kojto 122:f9eeca106725 336 #if defined(STM32F302xE) || defined(STM32F303xE)\
Kojto 122:f9eeca106725 337 || defined(STM32F302xC) || defined(STM32F303xC)\
Kojto 122:f9eeca106725 338 || defined(STM32F302x8) \
Kojto 122:f9eeca106725 339 || defined(STM32F373xC)
Kojto 122:f9eeca106725 340 #define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_PLL) || \
Kojto 122:f9eeca106725 341 ((SOURCE) == RCC_USBCLKSOURCE_PLL_DIV1_5))
Kojto 122:f9eeca106725 342 #endif /* STM32F302xE || STM32F303xE || */
Kojto 122:f9eeca106725 343 /* STM32F302xC || STM32F303xC || */
Kojto 122:f9eeca106725 344 /* STM32F302x8 || */
Kojto 122:f9eeca106725 345 /* STM32F373xC */
Kojto 122:f9eeca106725 346 #if defined(RCC_CFGR_MCOPRE)
Kojto 122:f9eeca106725 347 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \
Kojto 122:f9eeca106725 348 ((DIV) == RCC_MCODIV_4) || ((DIV) == RCC_MCODIV_8) || \
Kojto 122:f9eeca106725 349 ((DIV) == RCC_MCODIV_16) || ((DIV) == RCC_MCODIV_32) || \
Kojto 122:f9eeca106725 350 ((DIV) == RCC_MCODIV_64) || ((DIV) == RCC_MCODIV_128))
Kojto 122:f9eeca106725 351 #else
Kojto 122:f9eeca106725 352 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1))
Kojto 122:f9eeca106725 353 #endif /* RCC_CFGR_MCOPRE */
Kojto 122:f9eeca106725 354
Kojto 122:f9eeca106725 355 #define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || \
Kojto 122:f9eeca106725 356 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \
Kojto 122:f9eeca106725 357 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \
Kojto 122:f9eeca106725 358 ((__DRIVE__) == RCC_LSEDRIVE_HIGH))
bogdanm 92:4fc01daae5a5 359
bogdanm 92:4fc01daae5a5 360 /**
Kojto 122:f9eeca106725 361 * @}
bogdanm 92:4fc01daae5a5 362 */
Kojto 122:f9eeca106725 363
Kojto 122:f9eeca106725 364 /* Exported types ------------------------------------------------------------*/
Kojto 122:f9eeca106725 365 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types
Kojto 122:f9eeca106725 366 * @{
bogdanm 92:4fc01daae5a5 367 */
bogdanm 92:4fc01daae5a5 368
bogdanm 86:04dd9b1680ae 369 /**
bogdanm 86:04dd9b1680ae 370 * @brief RCC extended clocks structure definition
bogdanm 86:04dd9b1680ae 371 */
bogdanm 86:04dd9b1680ae 372 #if defined(STM32F301x8) || defined(STM32F318xx)
bogdanm 86:04dd9b1680ae 373 typedef struct
bogdanm 86:04dd9b1680ae 374 {
bogdanm 86:04dd9b1680ae 375 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm 86:04dd9b1680ae 376 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm 86:04dd9b1680ae 377
bogdanm 86:04dd9b1680ae 378 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm 86:04dd9b1680ae 379 This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm 86:04dd9b1680ae 380
bogdanm 86:04dd9b1680ae 381 uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm 86:04dd9b1680ae 382 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
bogdanm 86:04dd9b1680ae 383
bogdanm 86:04dd9b1680ae 384 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm 86:04dd9b1680ae 385 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm 86:04dd9b1680ae 386
bogdanm 86:04dd9b1680ae 387 uint32_t I2c2ClockSelection; /*!< I2C2 clock source
bogdanm 86:04dd9b1680ae 388 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
bogdanm 86:04dd9b1680ae 389
bogdanm 86:04dd9b1680ae 390 uint32_t I2c3ClockSelection; /*!< I2C3 clock source
bogdanm 86:04dd9b1680ae 391 This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
bogdanm 86:04dd9b1680ae 392
bogdanm 86:04dd9b1680ae 393 uint32_t Adc1ClockSelection; /*!< ADC1 clock source
bogdanm 86:04dd9b1680ae 394 This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */
bogdanm 86:04dd9b1680ae 395
bogdanm 86:04dd9b1680ae 396 uint32_t I2sClockSelection; /*!< I2S clock source
bogdanm 86:04dd9b1680ae 397 This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
bogdanm 86:04dd9b1680ae 398
bogdanm 86:04dd9b1680ae 399 uint32_t Tim1ClockSelection; /*!< TIM1 clock source
bogdanm 86:04dd9b1680ae 400 This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
bogdanm 86:04dd9b1680ae 401
bogdanm 86:04dd9b1680ae 402 uint32_t Tim15ClockSelection; /*!< TIM15 clock source
bogdanm 86:04dd9b1680ae 403 This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
bogdanm 86:04dd9b1680ae 404
bogdanm 86:04dd9b1680ae 405 uint32_t Tim16ClockSelection; /*!< TIM16 clock source
bogdanm 86:04dd9b1680ae 406 This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
bogdanm 86:04dd9b1680ae 407
bogdanm 86:04dd9b1680ae 408 uint32_t Tim17ClockSelection; /*!< TIM17 clock source
bogdanm 86:04dd9b1680ae 409 This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
bogdanm 86:04dd9b1680ae 410 }RCC_PeriphCLKInitTypeDef;
bogdanm 86:04dd9b1680ae 411 #endif /* STM32F301x8 || STM32F318xx */
bogdanm 86:04dd9b1680ae 412
bogdanm 86:04dd9b1680ae 413 #if defined(STM32F302x8)
bogdanm 86:04dd9b1680ae 414 typedef struct
bogdanm 86:04dd9b1680ae 415 {
bogdanm 86:04dd9b1680ae 416 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm 86:04dd9b1680ae 417 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm 86:04dd9b1680ae 418
bogdanm 86:04dd9b1680ae 419 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm 86:04dd9b1680ae 420 This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm 86:04dd9b1680ae 421
bogdanm 86:04dd9b1680ae 422 uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm 86:04dd9b1680ae 423 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
bogdanm 86:04dd9b1680ae 424
bogdanm 86:04dd9b1680ae 425 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm 86:04dd9b1680ae 426 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm 86:04dd9b1680ae 427
bogdanm 86:04dd9b1680ae 428 uint32_t I2c2ClockSelection; /*!< I2C2 clock source
bogdanm 86:04dd9b1680ae 429 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
bogdanm 86:04dd9b1680ae 430
bogdanm 86:04dd9b1680ae 431 uint32_t I2c3ClockSelection; /*!< I2C3 clock source
bogdanm 86:04dd9b1680ae 432 This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
bogdanm 86:04dd9b1680ae 433
bogdanm 86:04dd9b1680ae 434 uint32_t Adc1ClockSelection; /*!< ADC1 clock source
bogdanm 86:04dd9b1680ae 435 This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */
bogdanm 86:04dd9b1680ae 436
bogdanm 86:04dd9b1680ae 437 uint32_t I2sClockSelection; /*!< I2S clock source
bogdanm 86:04dd9b1680ae 438 This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
bogdanm 86:04dd9b1680ae 439
bogdanm 86:04dd9b1680ae 440 uint32_t Tim1ClockSelection; /*!< TIM1 clock source
bogdanm 86:04dd9b1680ae 441 This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
bogdanm 86:04dd9b1680ae 442
bogdanm 86:04dd9b1680ae 443 uint32_t Tim15ClockSelection; /*!< TIM15 clock source
bogdanm 86:04dd9b1680ae 444 This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
bogdanm 86:04dd9b1680ae 445
bogdanm 86:04dd9b1680ae 446 uint32_t Tim16ClockSelection; /*!< TIM16 clock source
bogdanm 86:04dd9b1680ae 447 This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
bogdanm 86:04dd9b1680ae 448
bogdanm 86:04dd9b1680ae 449 uint32_t Tim17ClockSelection; /*!< TIM17 clock source
bogdanm 86:04dd9b1680ae 450 This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
bogdanm 86:04dd9b1680ae 451
bogdanm 86:04dd9b1680ae 452 uint32_t USBClockSelection; /*!< USB clock source
bogdanm 86:04dd9b1680ae 453 This parameter can be a value of @ref RCCEx_USB_Clock_Source */
bogdanm 86:04dd9b1680ae 454
bogdanm 86:04dd9b1680ae 455 }RCC_PeriphCLKInitTypeDef;
bogdanm 86:04dd9b1680ae 456 #endif /* STM32F302x8 */
bogdanm 86:04dd9b1680ae 457
bogdanm 86:04dd9b1680ae 458 #if defined(STM32F302xC)
bogdanm 86:04dd9b1680ae 459 typedef struct
bogdanm 86:04dd9b1680ae 460 {
bogdanm 86:04dd9b1680ae 461 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm 86:04dd9b1680ae 462 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm 86:04dd9b1680ae 463
bogdanm 86:04dd9b1680ae 464 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm 86:04dd9b1680ae 465 This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm 86:04dd9b1680ae 466
bogdanm 86:04dd9b1680ae 467 uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm 86:04dd9b1680ae 468 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
bogdanm 86:04dd9b1680ae 469
bogdanm 86:04dd9b1680ae 470 uint32_t Usart2ClockSelection; /*!< USART2 clock source
bogdanm 86:04dd9b1680ae 471 This parameter can be a value of @ref RCC_USART2_Clock_Source */
bogdanm 86:04dd9b1680ae 472
bogdanm 86:04dd9b1680ae 473 uint32_t Usart3ClockSelection; /*!< USART3 clock source
bogdanm 86:04dd9b1680ae 474 This parameter can be a value of @ref RCC_USART3_Clock_Source */
bogdanm 86:04dd9b1680ae 475
bogdanm 86:04dd9b1680ae 476 uint32_t Uart4ClockSelection; /*!< UART4 clock source
bogdanm 86:04dd9b1680ae 477 This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
bogdanm 86:04dd9b1680ae 478
bogdanm 86:04dd9b1680ae 479 uint32_t Uart5ClockSelection; /*!< UART5 clock source
bogdanm 86:04dd9b1680ae 480 This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
bogdanm 86:04dd9b1680ae 481
bogdanm 86:04dd9b1680ae 482 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm 86:04dd9b1680ae 483 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm 86:04dd9b1680ae 484
bogdanm 86:04dd9b1680ae 485 uint32_t I2c2ClockSelection; /*!< I2C2 clock source
bogdanm 86:04dd9b1680ae 486 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
bogdanm 86:04dd9b1680ae 487
bogdanm 86:04dd9b1680ae 488 uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
bogdanm 86:04dd9b1680ae 489 This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
bogdanm 86:04dd9b1680ae 490
bogdanm 86:04dd9b1680ae 491 uint32_t I2sClockSelection; /*!< I2S clock source
bogdanm 86:04dd9b1680ae 492 This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
bogdanm 86:04dd9b1680ae 493
bogdanm 86:04dd9b1680ae 494 uint32_t Tim1ClockSelection; /*!< TIM1 clock source
bogdanm 86:04dd9b1680ae 495 This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
bogdanm 86:04dd9b1680ae 496
bogdanm 86:04dd9b1680ae 497 uint32_t USBClockSelection; /*!< USB clock source
bogdanm 86:04dd9b1680ae 498 This parameter can be a value of @ref RCCEx_USB_Clock_Source */
bogdanm 86:04dd9b1680ae 499
bogdanm 86:04dd9b1680ae 500 }RCC_PeriphCLKInitTypeDef;
bogdanm 86:04dd9b1680ae 501 #endif /* STM32F302xC */
bogdanm 86:04dd9b1680ae 502
bogdanm 86:04dd9b1680ae 503 #if defined(STM32F303xC)
bogdanm 86:04dd9b1680ae 504 typedef struct
bogdanm 86:04dd9b1680ae 505 {
bogdanm 86:04dd9b1680ae 506 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm 86:04dd9b1680ae 507 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm 86:04dd9b1680ae 508
bogdanm 86:04dd9b1680ae 509 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm 86:04dd9b1680ae 510 This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm 86:04dd9b1680ae 511
bogdanm 86:04dd9b1680ae 512 uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm 86:04dd9b1680ae 513 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
bogdanm 86:04dd9b1680ae 514
bogdanm 86:04dd9b1680ae 515 uint32_t Usart2ClockSelection; /*!< USART2 clock source
bogdanm 86:04dd9b1680ae 516 This parameter can be a value of @ref RCC_USART2_Clock_Source */
bogdanm 86:04dd9b1680ae 517
bogdanm 86:04dd9b1680ae 518 uint32_t Usart3ClockSelection; /*!< USART3 clock source
bogdanm 86:04dd9b1680ae 519 This parameter can be a value of @ref RCC_USART3_Clock_Source */
bogdanm 86:04dd9b1680ae 520
bogdanm 86:04dd9b1680ae 521 uint32_t Uart4ClockSelection; /*!< UART4 clock source
bogdanm 86:04dd9b1680ae 522 This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
bogdanm 86:04dd9b1680ae 523
bogdanm 86:04dd9b1680ae 524 uint32_t Uart5ClockSelection; /*!< UART5 clock source
bogdanm 86:04dd9b1680ae 525 This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
bogdanm 86:04dd9b1680ae 526
bogdanm 86:04dd9b1680ae 527 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm 86:04dd9b1680ae 528 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm 86:04dd9b1680ae 529
bogdanm 86:04dd9b1680ae 530 uint32_t I2c2ClockSelection; /*!< I2C2 clock source
bogdanm 86:04dd9b1680ae 531 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
bogdanm 86:04dd9b1680ae 532
bogdanm 86:04dd9b1680ae 533 uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
bogdanm 86:04dd9b1680ae 534 This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
bogdanm 86:04dd9b1680ae 535
bogdanm 86:04dd9b1680ae 536 uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source
bogdanm 86:04dd9b1680ae 537 This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */
bogdanm 86:04dd9b1680ae 538
bogdanm 86:04dd9b1680ae 539 uint32_t I2sClockSelection; /*!< I2S clock source
bogdanm 86:04dd9b1680ae 540 This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
bogdanm 86:04dd9b1680ae 541
bogdanm 86:04dd9b1680ae 542 uint32_t Tim1ClockSelection; /*!< TIM1 clock source
bogdanm 86:04dd9b1680ae 543 This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
bogdanm 86:04dd9b1680ae 544
bogdanm 86:04dd9b1680ae 545 uint32_t Tim8ClockSelection; /*!< TIM8 clock source
bogdanm 86:04dd9b1680ae 546 This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */
bogdanm 86:04dd9b1680ae 547
bogdanm 86:04dd9b1680ae 548 uint32_t USBClockSelection; /*!< USB clock source
bogdanm 86:04dd9b1680ae 549 This parameter can be a value of @ref RCCEx_USB_Clock_Source */
bogdanm 86:04dd9b1680ae 550
bogdanm 86:04dd9b1680ae 551 }RCC_PeriphCLKInitTypeDef;
bogdanm 86:04dd9b1680ae 552 #endif /* STM32F303xC */
bogdanm 86:04dd9b1680ae 553
bogdanm 92:4fc01daae5a5 554 #if defined(STM32F302xE)
bogdanm 92:4fc01daae5a5 555 typedef struct
bogdanm 92:4fc01daae5a5 556 {
bogdanm 92:4fc01daae5a5 557 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm 92:4fc01daae5a5 558 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm 92:4fc01daae5a5 559
bogdanm 92:4fc01daae5a5 560 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm 92:4fc01daae5a5 561 This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm 92:4fc01daae5a5 562
bogdanm 92:4fc01daae5a5 563 uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm 92:4fc01daae5a5 564 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
bogdanm 92:4fc01daae5a5 565
bogdanm 92:4fc01daae5a5 566 uint32_t Usart2ClockSelection; /*!< USART2 clock source
bogdanm 92:4fc01daae5a5 567 This parameter can be a value of @ref RCC_USART2_Clock_Source */
bogdanm 92:4fc01daae5a5 568
bogdanm 92:4fc01daae5a5 569 uint32_t Usart3ClockSelection; /*!< USART3 clock source
bogdanm 92:4fc01daae5a5 570 This parameter can be a value of @ref RCC_USART3_Clock_Source */
bogdanm 92:4fc01daae5a5 571
bogdanm 92:4fc01daae5a5 572 uint32_t Uart4ClockSelection; /*!< UART4 clock source
bogdanm 92:4fc01daae5a5 573 This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
bogdanm 92:4fc01daae5a5 574
bogdanm 92:4fc01daae5a5 575 uint32_t Uart5ClockSelection; /*!< UART5 clock source
bogdanm 92:4fc01daae5a5 576 This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
bogdanm 92:4fc01daae5a5 577
bogdanm 92:4fc01daae5a5 578 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm 92:4fc01daae5a5 579 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm 92:4fc01daae5a5 580
bogdanm 92:4fc01daae5a5 581 uint32_t I2c2ClockSelection; /*!< I2C2 clock source
bogdanm 92:4fc01daae5a5 582 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
bogdanm 92:4fc01daae5a5 583
bogdanm 92:4fc01daae5a5 584 uint32_t I2c3ClockSelection; /*!< I2C3 clock source
bogdanm 92:4fc01daae5a5 585 This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
bogdanm 92:4fc01daae5a5 586
bogdanm 92:4fc01daae5a5 587 uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
bogdanm 92:4fc01daae5a5 588 This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
bogdanm 92:4fc01daae5a5 589
bogdanm 92:4fc01daae5a5 590 uint32_t I2sClockSelection; /*!< I2S clock source
bogdanm 92:4fc01daae5a5 591 This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
bogdanm 92:4fc01daae5a5 592
bogdanm 92:4fc01daae5a5 593 uint32_t Tim1ClockSelection; /*!< TIM1 clock source
bogdanm 92:4fc01daae5a5 594 This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
bogdanm 92:4fc01daae5a5 595
bogdanm 92:4fc01daae5a5 596 uint32_t Tim2ClockSelection; /*!< TIM2 clock source
bogdanm 92:4fc01daae5a5 597 This parameter can be a value of @ref RCCEx_TIM2_Clock_Source */
bogdanm 92:4fc01daae5a5 598
bogdanm 92:4fc01daae5a5 599 uint32_t Tim34ClockSelection; /*!< TIM3 & TIM4 clock source
bogdanm 92:4fc01daae5a5 600 This parameter can be a value of @ref RCCEx_TIM34_Clock_Source */
bogdanm 92:4fc01daae5a5 601
bogdanm 92:4fc01daae5a5 602 uint32_t Tim15ClockSelection; /*!< TIM15 clock source
bogdanm 92:4fc01daae5a5 603 This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
bogdanm 92:4fc01daae5a5 604
bogdanm 92:4fc01daae5a5 605 uint32_t Tim16ClockSelection; /*!< TIM16 clock source
bogdanm 92:4fc01daae5a5 606 This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
bogdanm 92:4fc01daae5a5 607
bogdanm 92:4fc01daae5a5 608 uint32_t Tim17ClockSelection; /*!< TIM17 clock source
bogdanm 92:4fc01daae5a5 609 This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
bogdanm 92:4fc01daae5a5 610
bogdanm 92:4fc01daae5a5 611 uint32_t USBClockSelection; /*!< USB clock source
bogdanm 92:4fc01daae5a5 612 This parameter can be a value of @ref RCCEx_USB_Clock_Source */
bogdanm 92:4fc01daae5a5 613
bogdanm 92:4fc01daae5a5 614 }RCC_PeriphCLKInitTypeDef;
bogdanm 92:4fc01daae5a5 615 #endif /* STM32F302xE */
bogdanm 92:4fc01daae5a5 616
bogdanm 92:4fc01daae5a5 617 #if defined(STM32F303xE)
bogdanm 92:4fc01daae5a5 618 typedef struct
bogdanm 92:4fc01daae5a5 619 {
bogdanm 92:4fc01daae5a5 620 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm 92:4fc01daae5a5 621 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm 92:4fc01daae5a5 622
bogdanm 92:4fc01daae5a5 623 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm 92:4fc01daae5a5 624 This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm 92:4fc01daae5a5 625
bogdanm 92:4fc01daae5a5 626 uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm 92:4fc01daae5a5 627 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
bogdanm 92:4fc01daae5a5 628
bogdanm 92:4fc01daae5a5 629 uint32_t Usart2ClockSelection; /*!< USART2 clock source
bogdanm 92:4fc01daae5a5 630 This parameter can be a value of @ref RCC_USART2_Clock_Source */
bogdanm 92:4fc01daae5a5 631
bogdanm 92:4fc01daae5a5 632 uint32_t Usart3ClockSelection; /*!< USART3 clock source
bogdanm 92:4fc01daae5a5 633 This parameter can be a value of @ref RCC_USART3_Clock_Source */
bogdanm 92:4fc01daae5a5 634
bogdanm 92:4fc01daae5a5 635 uint32_t Uart4ClockSelection; /*!< UART4 clock source
bogdanm 92:4fc01daae5a5 636 This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
bogdanm 92:4fc01daae5a5 637
bogdanm 92:4fc01daae5a5 638 uint32_t Uart5ClockSelection; /*!< UART5 clock source
bogdanm 92:4fc01daae5a5 639 This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
bogdanm 92:4fc01daae5a5 640
bogdanm 92:4fc01daae5a5 641 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm 92:4fc01daae5a5 642 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm 92:4fc01daae5a5 643
bogdanm 92:4fc01daae5a5 644 uint32_t I2c2ClockSelection; /*!< I2C2 clock source
bogdanm 92:4fc01daae5a5 645 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
bogdanm 92:4fc01daae5a5 646
bogdanm 92:4fc01daae5a5 647 uint32_t I2c3ClockSelection; /*!< I2C3 clock source
bogdanm 92:4fc01daae5a5 648 This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
bogdanm 92:4fc01daae5a5 649
bogdanm 92:4fc01daae5a5 650 uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
bogdanm 92:4fc01daae5a5 651 This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
bogdanm 92:4fc01daae5a5 652
bogdanm 92:4fc01daae5a5 653 uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source
bogdanm 92:4fc01daae5a5 654 This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */
bogdanm 92:4fc01daae5a5 655
bogdanm 92:4fc01daae5a5 656 uint32_t I2sClockSelection; /*!< I2S clock source
bogdanm 92:4fc01daae5a5 657 This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
bogdanm 92:4fc01daae5a5 658
bogdanm 92:4fc01daae5a5 659 uint32_t Tim1ClockSelection; /*!< TIM1 clock source
bogdanm 92:4fc01daae5a5 660 This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
bogdanm 92:4fc01daae5a5 661
bogdanm 92:4fc01daae5a5 662 uint32_t Tim2ClockSelection; /*!< TIM2 clock source
bogdanm 92:4fc01daae5a5 663 This parameter can be a value of @ref RCCEx_TIM2_Clock_Source */
bogdanm 92:4fc01daae5a5 664
bogdanm 92:4fc01daae5a5 665 uint32_t Tim34ClockSelection; /*!< TIM3 & TIM4 clock source
bogdanm 92:4fc01daae5a5 666 This parameter can be a value of @ref RCCEx_TIM34_Clock_Source */
bogdanm 92:4fc01daae5a5 667
bogdanm 92:4fc01daae5a5 668 uint32_t Tim8ClockSelection; /*!< TIM8 clock source
bogdanm 92:4fc01daae5a5 669 This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */
bogdanm 92:4fc01daae5a5 670
bogdanm 92:4fc01daae5a5 671 uint32_t Tim15ClockSelection; /*!< TIM15 clock source
bogdanm 92:4fc01daae5a5 672 This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
bogdanm 92:4fc01daae5a5 673
bogdanm 92:4fc01daae5a5 674 uint32_t Tim16ClockSelection; /*!< TIM16 clock source
bogdanm 92:4fc01daae5a5 675 This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
bogdanm 92:4fc01daae5a5 676
bogdanm 92:4fc01daae5a5 677 uint32_t Tim17ClockSelection; /*!< TIM17 clock source
bogdanm 92:4fc01daae5a5 678 This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
bogdanm 92:4fc01daae5a5 679
bogdanm 92:4fc01daae5a5 680 uint32_t Tim20ClockSelection; /*!< TIM20 clock source
bogdanm 92:4fc01daae5a5 681 This parameter can be a value of @ref RCCEx_TIM20_Clock_Source */
bogdanm 92:4fc01daae5a5 682
bogdanm 92:4fc01daae5a5 683 uint32_t USBClockSelection; /*!< USB clock source
bogdanm 92:4fc01daae5a5 684 This parameter can be a value of @ref RCCEx_USB_Clock_Source */
bogdanm 92:4fc01daae5a5 685
bogdanm 92:4fc01daae5a5 686 }RCC_PeriphCLKInitTypeDef;
bogdanm 92:4fc01daae5a5 687 #endif /* STM32F303xE */
bogdanm 92:4fc01daae5a5 688
bogdanm 92:4fc01daae5a5 689 #if defined(STM32F398xx)
bogdanm 92:4fc01daae5a5 690 typedef struct
bogdanm 92:4fc01daae5a5 691 {
bogdanm 92:4fc01daae5a5 692 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm 92:4fc01daae5a5 693 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm 92:4fc01daae5a5 694
bogdanm 92:4fc01daae5a5 695 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm 92:4fc01daae5a5 696 This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm 92:4fc01daae5a5 697
bogdanm 92:4fc01daae5a5 698 uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm 92:4fc01daae5a5 699 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
bogdanm 92:4fc01daae5a5 700
bogdanm 92:4fc01daae5a5 701 uint32_t Usart2ClockSelection; /*!< USART2 clock source
bogdanm 92:4fc01daae5a5 702 This parameter can be a value of @ref RCC_USART2_Clock_Source */
bogdanm 92:4fc01daae5a5 703
bogdanm 92:4fc01daae5a5 704 uint32_t Usart3ClockSelection; /*!< USART3 clock source
bogdanm 92:4fc01daae5a5 705 This parameter can be a value of @ref RCC_USART3_Clock_Source */
bogdanm 92:4fc01daae5a5 706
bogdanm 92:4fc01daae5a5 707 uint32_t Uart4ClockSelection; /*!< UART4 clock source
bogdanm 92:4fc01daae5a5 708 This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
bogdanm 92:4fc01daae5a5 709
bogdanm 92:4fc01daae5a5 710 uint32_t Uart5ClockSelection; /*!< UART5 clock source
bogdanm 92:4fc01daae5a5 711 This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
bogdanm 92:4fc01daae5a5 712
bogdanm 92:4fc01daae5a5 713 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm 92:4fc01daae5a5 714 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm 92:4fc01daae5a5 715
bogdanm 92:4fc01daae5a5 716 uint32_t I2c2ClockSelection; /*!< I2C2 clock source
bogdanm 92:4fc01daae5a5 717 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
bogdanm 92:4fc01daae5a5 718
bogdanm 92:4fc01daae5a5 719 uint32_t I2c3ClockSelection; /*!< I2C3 clock source
bogdanm 92:4fc01daae5a5 720 This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
bogdanm 92:4fc01daae5a5 721
bogdanm 92:4fc01daae5a5 722 uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
bogdanm 92:4fc01daae5a5 723 This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
bogdanm 92:4fc01daae5a5 724
bogdanm 92:4fc01daae5a5 725 uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source
bogdanm 92:4fc01daae5a5 726 This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */
bogdanm 92:4fc01daae5a5 727
bogdanm 92:4fc01daae5a5 728 uint32_t I2sClockSelection; /*!< I2S clock source
bogdanm 92:4fc01daae5a5 729 This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
bogdanm 92:4fc01daae5a5 730
bogdanm 92:4fc01daae5a5 731 uint32_t Tim1ClockSelection; /*!< TIM1 clock source
bogdanm 92:4fc01daae5a5 732 This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
bogdanm 92:4fc01daae5a5 733
bogdanm 92:4fc01daae5a5 734 uint32_t Tim2ClockSelection; /*!< TIM2 clock source
bogdanm 92:4fc01daae5a5 735 This parameter can be a value of @ref RCCEx_TIM2_Clock_Source */
bogdanm 92:4fc01daae5a5 736
bogdanm 92:4fc01daae5a5 737 uint32_t Tim34ClockSelection; /*!< TIM3 & TIM4 clock source
bogdanm 92:4fc01daae5a5 738 This parameter can be a value of @ref RCCEx_TIM34_Clock_Source */
bogdanm 92:4fc01daae5a5 739
bogdanm 92:4fc01daae5a5 740 uint32_t Tim8ClockSelection; /*!< TIM8 clock source
bogdanm 92:4fc01daae5a5 741 This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */
bogdanm 92:4fc01daae5a5 742
bogdanm 92:4fc01daae5a5 743 uint32_t Tim15ClockSelection; /*!< TIM15 clock source
bogdanm 92:4fc01daae5a5 744 This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
bogdanm 92:4fc01daae5a5 745
bogdanm 92:4fc01daae5a5 746 uint32_t Tim16ClockSelection; /*!< TIM16 clock source
bogdanm 92:4fc01daae5a5 747 This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
bogdanm 92:4fc01daae5a5 748
bogdanm 92:4fc01daae5a5 749 uint32_t Tim17ClockSelection; /*!< TIM17 clock source
bogdanm 92:4fc01daae5a5 750 This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
bogdanm 92:4fc01daae5a5 751
bogdanm 92:4fc01daae5a5 752 uint32_t Tim20ClockSelection; /*!< TIM20 clock source
bogdanm 92:4fc01daae5a5 753 This parameter can be a value of @ref RCCEx_TIM20_Clock_Source */
bogdanm 92:4fc01daae5a5 754
bogdanm 92:4fc01daae5a5 755 }RCC_PeriphCLKInitTypeDef;
bogdanm 92:4fc01daae5a5 756 #endif /* STM32F398xx */
bogdanm 92:4fc01daae5a5 757
bogdanm 86:04dd9b1680ae 758 #if defined(STM32F358xx)
bogdanm 86:04dd9b1680ae 759 typedef struct
bogdanm 86:04dd9b1680ae 760 {
bogdanm 86:04dd9b1680ae 761 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm 86:04dd9b1680ae 762 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm 86:04dd9b1680ae 763
bogdanm 86:04dd9b1680ae 764 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm 86:04dd9b1680ae 765 This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm 86:04dd9b1680ae 766
bogdanm 86:04dd9b1680ae 767 uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm 86:04dd9b1680ae 768 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
bogdanm 86:04dd9b1680ae 769
bogdanm 86:04dd9b1680ae 770 uint32_t Usart2ClockSelection; /*!< USART2 clock source
bogdanm 86:04dd9b1680ae 771 This parameter can be a value of @ref RCC_USART2_Clock_Source */
bogdanm 86:04dd9b1680ae 772
bogdanm 86:04dd9b1680ae 773 uint32_t Usart3ClockSelection; /*!< USART3 clock source
bogdanm 86:04dd9b1680ae 774 This parameter can be a value of @ref RCC_USART3_Clock_Source */
bogdanm 86:04dd9b1680ae 775
bogdanm 86:04dd9b1680ae 776 uint32_t Uart4ClockSelection; /*!< UART4 clock source
bogdanm 86:04dd9b1680ae 777 This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
bogdanm 86:04dd9b1680ae 778
bogdanm 86:04dd9b1680ae 779 uint32_t Uart5ClockSelection; /*!< UART5 clock source
bogdanm 86:04dd9b1680ae 780 This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
bogdanm 86:04dd9b1680ae 781
bogdanm 86:04dd9b1680ae 782 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm 86:04dd9b1680ae 783 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm 86:04dd9b1680ae 784
bogdanm 86:04dd9b1680ae 785 uint32_t I2c2ClockSelection; /*!< I2C2 clock source
bogdanm 86:04dd9b1680ae 786 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
bogdanm 86:04dd9b1680ae 787
bogdanm 86:04dd9b1680ae 788 uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
bogdanm 86:04dd9b1680ae 789 This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
bogdanm 86:04dd9b1680ae 790
bogdanm 86:04dd9b1680ae 791 uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source
bogdanm 86:04dd9b1680ae 792 This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */
bogdanm 86:04dd9b1680ae 793
bogdanm 86:04dd9b1680ae 794 uint32_t I2sClockSelection; /*!< I2S clock source
bogdanm 86:04dd9b1680ae 795 This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
bogdanm 86:04dd9b1680ae 796
bogdanm 86:04dd9b1680ae 797 uint32_t Tim1ClockSelection; /*!< TIM1 clock source
bogdanm 86:04dd9b1680ae 798 This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
bogdanm 86:04dd9b1680ae 799
bogdanm 86:04dd9b1680ae 800 uint32_t Tim8ClockSelection; /*!< TIM8 clock source
bogdanm 86:04dd9b1680ae 801 This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */
bogdanm 86:04dd9b1680ae 802
bogdanm 86:04dd9b1680ae 803 }RCC_PeriphCLKInitTypeDef;
bogdanm 86:04dd9b1680ae 804 #endif /* STM32F358xx */
bogdanm 86:04dd9b1680ae 805
bogdanm 86:04dd9b1680ae 806 #if defined(STM32F303x8)
bogdanm 86:04dd9b1680ae 807 typedef struct
bogdanm 86:04dd9b1680ae 808 {
bogdanm 86:04dd9b1680ae 809 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm 86:04dd9b1680ae 810 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm 86:04dd9b1680ae 811
bogdanm 86:04dd9b1680ae 812 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm 86:04dd9b1680ae 813 This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm 86:04dd9b1680ae 814
bogdanm 92:4fc01daae5a5 815 uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm 86:04dd9b1680ae 816 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
bogdanm 86:04dd9b1680ae 817
bogdanm 86:04dd9b1680ae 818 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm 86:04dd9b1680ae 819 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm 86:04dd9b1680ae 820
bogdanm 86:04dd9b1680ae 821 uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
bogdanm 86:04dd9b1680ae 822 This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
bogdanm 86:04dd9b1680ae 823
bogdanm 86:04dd9b1680ae 824 uint32_t Tim1ClockSelection; /*!< TIM1 clock source
bogdanm 86:04dd9b1680ae 825 This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
bogdanm 86:04dd9b1680ae 826
bogdanm 86:04dd9b1680ae 827 }RCC_PeriphCLKInitTypeDef;
bogdanm 86:04dd9b1680ae 828 #endif /* STM32F303x8 */
bogdanm 86:04dd9b1680ae 829
bogdanm 86:04dd9b1680ae 830 #if defined(STM32F334x8)
bogdanm 86:04dd9b1680ae 831 typedef struct
bogdanm 86:04dd9b1680ae 832 {
bogdanm 86:04dd9b1680ae 833 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm 86:04dd9b1680ae 834 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm 86:04dd9b1680ae 835
bogdanm 86:04dd9b1680ae 836 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm 86:04dd9b1680ae 837 This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm 86:04dd9b1680ae 838
bogdanm 92:4fc01daae5a5 839 uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm 86:04dd9b1680ae 840 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
bogdanm 86:04dd9b1680ae 841
bogdanm 86:04dd9b1680ae 842 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm 86:04dd9b1680ae 843 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm 86:04dd9b1680ae 844
bogdanm 86:04dd9b1680ae 845 uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
bogdanm 86:04dd9b1680ae 846 This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
bogdanm 86:04dd9b1680ae 847
bogdanm 86:04dd9b1680ae 848 uint32_t Tim1ClockSelection; /*!< TIM1 clock source
bogdanm 86:04dd9b1680ae 849 This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
bogdanm 86:04dd9b1680ae 850
bogdanm 86:04dd9b1680ae 851 uint32_t Hrtim1ClockSelection; /*!< HRTIM1 clock source
bogdanm 86:04dd9b1680ae 852 This parameter can be a value of @ref RCCEx_HRTIM1_Clock_Source */
bogdanm 86:04dd9b1680ae 853
bogdanm 86:04dd9b1680ae 854 }RCC_PeriphCLKInitTypeDef;
bogdanm 86:04dd9b1680ae 855 #endif /* STM32F334x8 */
bogdanm 86:04dd9b1680ae 856
bogdanm 86:04dd9b1680ae 857 #if defined(STM32F328xx)
bogdanm 86:04dd9b1680ae 858 typedef struct
bogdanm 86:04dd9b1680ae 859 {
bogdanm 86:04dd9b1680ae 860 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm 86:04dd9b1680ae 861 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm 86:04dd9b1680ae 862
bogdanm 86:04dd9b1680ae 863 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm 86:04dd9b1680ae 864 This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm 86:04dd9b1680ae 865
bogdanm 86:04dd9b1680ae 866 uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto 122:f9eeca106725 867 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
bogdanm 86:04dd9b1680ae 868
bogdanm 86:04dd9b1680ae 869 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm 86:04dd9b1680ae 870 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm 86:04dd9b1680ae 871
bogdanm 86:04dd9b1680ae 872 uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
bogdanm 86:04dd9b1680ae 873 This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
bogdanm 86:04dd9b1680ae 874
bogdanm 86:04dd9b1680ae 875 uint32_t Tim1ClockSelection; /*!< TIM1 clock source
bogdanm 86:04dd9b1680ae 876 This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
bogdanm 86:04dd9b1680ae 877
bogdanm 86:04dd9b1680ae 878 }RCC_PeriphCLKInitTypeDef;
bogdanm 86:04dd9b1680ae 879 #endif /* STM32F328xx */
bogdanm 86:04dd9b1680ae 880
bogdanm 86:04dd9b1680ae 881 #if defined(STM32F373xC)
bogdanm 86:04dd9b1680ae 882 typedef struct
bogdanm 86:04dd9b1680ae 883 {
bogdanm 86:04dd9b1680ae 884 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm 86:04dd9b1680ae 885 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm 86:04dd9b1680ae 886
bogdanm 86:04dd9b1680ae 887 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm 86:04dd9b1680ae 888 This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm 86:04dd9b1680ae 889
bogdanm 86:04dd9b1680ae 890 uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm 86:04dd9b1680ae 891 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
bogdanm 86:04dd9b1680ae 892
bogdanm 86:04dd9b1680ae 893 uint32_t Usart2ClockSelection; /*!< USART2 clock source
bogdanm 86:04dd9b1680ae 894 This parameter can be a value of @ref RCC_USART2_Clock_Source */
bogdanm 86:04dd9b1680ae 895
bogdanm 86:04dd9b1680ae 896 uint32_t Usart3ClockSelection; /*!< USART3 clock source
bogdanm 86:04dd9b1680ae 897 This parameter can be a value of @ref RCC_USART3_Clock_Source */
bogdanm 86:04dd9b1680ae 898
bogdanm 86:04dd9b1680ae 899 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm 86:04dd9b1680ae 900 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm 86:04dd9b1680ae 901
bogdanm 86:04dd9b1680ae 902 uint32_t I2c2ClockSelection; /*!< I2C2 clock source
bogdanm 86:04dd9b1680ae 903 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
bogdanm 86:04dd9b1680ae 904
bogdanm 86:04dd9b1680ae 905 uint32_t Adc1ClockSelection; /*!< ADC1 clock source
bogdanm 86:04dd9b1680ae 906 This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */
bogdanm 86:04dd9b1680ae 907
bogdanm 86:04dd9b1680ae 908 uint32_t SdadcClockSelection; /*!< SDADC clock prescaler
bogdanm 86:04dd9b1680ae 909 This parameter can be a value of @ref RCCEx_SDADC_Clock_Prescaler */
bogdanm 86:04dd9b1680ae 910
bogdanm 86:04dd9b1680ae 911 uint32_t CecClockSelection; /*!< HDMI CEC clock source
bogdanm 86:04dd9b1680ae 912 This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
bogdanm 86:04dd9b1680ae 913
bogdanm 86:04dd9b1680ae 914 uint32_t USBClockSelection; /*!< USB clock source
bogdanm 86:04dd9b1680ae 915 This parameter can be a value of @ref RCCEx_USB_Clock_Source */
bogdanm 86:04dd9b1680ae 916
bogdanm 86:04dd9b1680ae 917 }RCC_PeriphCLKInitTypeDef;
bogdanm 86:04dd9b1680ae 918 #endif /* STM32F373xC */
bogdanm 86:04dd9b1680ae 919
bogdanm 86:04dd9b1680ae 920 #if defined(STM32F378xx)
bogdanm 86:04dd9b1680ae 921 typedef struct
bogdanm 86:04dd9b1680ae 922 {
bogdanm 86:04dd9b1680ae 923 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm 86:04dd9b1680ae 924 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm 86:04dd9b1680ae 925
bogdanm 86:04dd9b1680ae 926 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm 86:04dd9b1680ae 927 This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm 86:04dd9b1680ae 928
bogdanm 86:04dd9b1680ae 929 uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm 86:04dd9b1680ae 930 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
bogdanm 86:04dd9b1680ae 931
bogdanm 86:04dd9b1680ae 932 uint32_t Usart2ClockSelection; /*!< USART2 clock source
bogdanm 86:04dd9b1680ae 933 This parameter can be a value of @ref RCC_USART2_Clock_Source */
bogdanm 86:04dd9b1680ae 934
bogdanm 86:04dd9b1680ae 935 uint32_t Usart3ClockSelection; /*!< USART3 clock source
bogdanm 86:04dd9b1680ae 936 This parameter can be a value of @ref RCC_USART3_Clock_Source */
bogdanm 86:04dd9b1680ae 937
bogdanm 86:04dd9b1680ae 938 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm 86:04dd9b1680ae 939 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm 86:04dd9b1680ae 940
bogdanm 86:04dd9b1680ae 941 uint32_t I2c2ClockSelection; /*!< I2C2 clock source
bogdanm 86:04dd9b1680ae 942 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
bogdanm 86:04dd9b1680ae 943
bogdanm 86:04dd9b1680ae 944 uint32_t Adc1ClockSelection; /*!< ADC1 clock source
bogdanm 86:04dd9b1680ae 945 This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */
bogdanm 86:04dd9b1680ae 946
bogdanm 86:04dd9b1680ae 947 uint32_t SdadcClockSelection; /*!< SDADC clock prescaler
bogdanm 86:04dd9b1680ae 948 This parameter can be a value of @ref RCCEx_SDADC_Clock_Prescaler */
bogdanm 86:04dd9b1680ae 949
bogdanm 86:04dd9b1680ae 950 uint32_t CecClockSelection; /*!< HDMI CEC clock source
bogdanm 86:04dd9b1680ae 951 This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
bogdanm 86:04dd9b1680ae 952
bogdanm 86:04dd9b1680ae 953 }RCC_PeriphCLKInitTypeDef;
bogdanm 86:04dd9b1680ae 954 #endif /* STM32F378xx */
bogdanm 86:04dd9b1680ae 955
bogdanm 92:4fc01daae5a5 956 /**
bogdanm 92:4fc01daae5a5 957 * @}
bogdanm 92:4fc01daae5a5 958 */
bogdanm 92:4fc01daae5a5 959
bogdanm 86:04dd9b1680ae 960 /* Exported constants --------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 961 /** @defgroup RCCEx_Exported_Constants RCC Extended Exported Constants
bogdanm 92:4fc01daae5a5 962 * @{
bogdanm 92:4fc01daae5a5 963 */
bogdanm 92:4fc01daae5a5 964 /** @defgroup RCCEx_MCO_Clock_Source RCC Extended MCO Clock Source
bogdanm 92:4fc01daae5a5 965 * @{
bogdanm 92:4fc01daae5a5 966 */
Kojto 122:f9eeca106725 967 #define RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCO_NOCLOCK
Kojto 122:f9eeca106725 968 #define RCC_MCO1SOURCE_LSI RCC_CFGR_MCO_LSI
Kojto 122:f9eeca106725 969 #define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO_LSE
Kojto 122:f9eeca106725 970 #define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK
Kojto 122:f9eeca106725 971 #define RCC_MCO1SOURCE_HSI RCC_CFGR_MCO_HSI
Kojto 122:f9eeca106725 972 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO_HSE
Kojto 122:f9eeca106725 973 #if defined(RCC_CFGR_PLLNODIV)
Kojto 122:f9eeca106725 974 #define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_PLLNODIV | RCC_CFGR_MCO_PLL)
Kojto 122:f9eeca106725 975 #endif /* RCC_CFGR_PLLNODIV */
Kojto 122:f9eeca106725 976 #define RCC_MCO1SOURCE_PLLCLK_DIV2 RCC_CFGR_MCO_PLL
Kojto 122:f9eeca106725 977
bogdanm 92:4fc01daae5a5 978 /**
bogdanm 92:4fc01daae5a5 979 * @}
bogdanm 92:4fc01daae5a5 980 */
bogdanm 92:4fc01daae5a5 981
bogdanm 92:4fc01daae5a5 982 /** @defgroup RCCEx_Periph_Clock_Selection RCC Extended Periph Clock Selection
bogdanm 86:04dd9b1680ae 983 * @{
bogdanm 86:04dd9b1680ae 984 */
bogdanm 86:04dd9b1680ae 985 #if defined(STM32F301x8) || defined(STM32F318xx)
bogdanm 86:04dd9b1680ae 986 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 987 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
bogdanm 86:04dd9b1680ae 988 #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
bogdanm 86:04dd9b1680ae 989 #define RCC_PERIPHCLK_ADC1 ((uint32_t)0x00000080)
bogdanm 86:04dd9b1680ae 990 #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
bogdanm 86:04dd9b1680ae 991 #define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
bogdanm 86:04dd9b1680ae 992 #define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00008000)
bogdanm 86:04dd9b1680ae 993 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
bogdanm 86:04dd9b1680ae 994 #define RCC_PERIPHCLK_TIM15 ((uint32_t)0x00040000)
bogdanm 86:04dd9b1680ae 995 #define RCC_PERIPHCLK_TIM16 ((uint32_t)0x00080000)
bogdanm 86:04dd9b1680ae 996 #define RCC_PERIPHCLK_TIM17 ((uint32_t)0x00100000)
bogdanm 86:04dd9b1680ae 997
bogdanm 86:04dd9b1680ae 998 #endif /* STM32F301x8 || STM32F318xx */
bogdanm 86:04dd9b1680ae 999
bogdanm 86:04dd9b1680ae 1000 #if defined(STM32F302x8)
bogdanm 86:04dd9b1680ae 1001 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 1002 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
bogdanm 86:04dd9b1680ae 1003 #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
bogdanm 86:04dd9b1680ae 1004 #define RCC_PERIPHCLK_ADC1 ((uint32_t)0x00000080)
bogdanm 86:04dd9b1680ae 1005 #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
bogdanm 86:04dd9b1680ae 1006 #define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
bogdanm 86:04dd9b1680ae 1007 #define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00008000)
bogdanm 86:04dd9b1680ae 1008 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
bogdanm 86:04dd9b1680ae 1009 #define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
bogdanm 86:04dd9b1680ae 1010 #define RCC_PERIPHCLK_TIM15 ((uint32_t)0x00040000)
bogdanm 86:04dd9b1680ae 1011 #define RCC_PERIPHCLK_TIM16 ((uint32_t)0x00080000)
bogdanm 86:04dd9b1680ae 1012 #define RCC_PERIPHCLK_TIM17 ((uint32_t)0x00100000)
bogdanm 86:04dd9b1680ae 1013
Kojto 122:f9eeca106725 1014
bogdanm 86:04dd9b1680ae 1015 #endif /* STM32F302x8 */
bogdanm 86:04dd9b1680ae 1016
bogdanm 86:04dd9b1680ae 1017 #if defined(STM32F302xC)
bogdanm 86:04dd9b1680ae 1018 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 1019 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 1020 #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
bogdanm 86:04dd9b1680ae 1021 #define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008)
bogdanm 86:04dd9b1680ae 1022 #define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010)
bogdanm 86:04dd9b1680ae 1023 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
bogdanm 86:04dd9b1680ae 1024 #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
bogdanm 86:04dd9b1680ae 1025 #define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
bogdanm 86:04dd9b1680ae 1026 #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
bogdanm 86:04dd9b1680ae 1027 #define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
bogdanm 86:04dd9b1680ae 1028 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
bogdanm 86:04dd9b1680ae 1029 #define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
bogdanm 86:04dd9b1680ae 1030
bogdanm 86:04dd9b1680ae 1031 #endif /* STM32F302xC */
bogdanm 86:04dd9b1680ae 1032
bogdanm 86:04dd9b1680ae 1033 #if defined(STM32F303xC)
bogdanm 86:04dd9b1680ae 1034 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 1035 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 1036 #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
bogdanm 86:04dd9b1680ae 1037 #define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008)
bogdanm 86:04dd9b1680ae 1038 #define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010)
bogdanm 86:04dd9b1680ae 1039 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
bogdanm 86:04dd9b1680ae 1040 #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
bogdanm 86:04dd9b1680ae 1041 #define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
bogdanm 86:04dd9b1680ae 1042 #define RCC_PERIPHCLK_ADC34 ((uint32_t)0x00000100)
bogdanm 86:04dd9b1680ae 1043 #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
bogdanm 86:04dd9b1680ae 1044 #define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
bogdanm 86:04dd9b1680ae 1045 #define RCC_PERIPHCLK_TIM8 ((uint32_t)0x00002000)
bogdanm 86:04dd9b1680ae 1046 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
bogdanm 86:04dd9b1680ae 1047 #define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
bogdanm 86:04dd9b1680ae 1048
bogdanm 86:04dd9b1680ae 1049 #endif /* STM32F303xC */
bogdanm 86:04dd9b1680ae 1050
bogdanm 92:4fc01daae5a5 1051 #if defined(STM32F302xE)
bogdanm 92:4fc01daae5a5 1052 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm 92:4fc01daae5a5 1053 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
bogdanm 92:4fc01daae5a5 1054 #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
bogdanm 92:4fc01daae5a5 1055 #define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008)
bogdanm 92:4fc01daae5a5 1056 #define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010)
bogdanm 92:4fc01daae5a5 1057 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
bogdanm 92:4fc01daae5a5 1058 #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
bogdanm 92:4fc01daae5a5 1059 #define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
bogdanm 92:4fc01daae5a5 1060 #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
bogdanm 92:4fc01daae5a5 1061 #define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
bogdanm 92:4fc01daae5a5 1062 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
bogdanm 92:4fc01daae5a5 1063 #define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
bogdanm 92:4fc01daae5a5 1064 #define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00040000)
bogdanm 92:4fc01daae5a5 1065 #define RCC_PERIPHCLK_TIM2 ((uint32_t)0x00100000)
bogdanm 92:4fc01daae5a5 1066 #define RCC_PERIPHCLK_TIM34 ((uint32_t)0x00200000)
bogdanm 92:4fc01daae5a5 1067 #define RCC_PERIPHCLK_TIM15 ((uint32_t)0x00400000)
bogdanm 92:4fc01daae5a5 1068 #define RCC_PERIPHCLK_TIM16 ((uint32_t)0x00800000)
bogdanm 92:4fc01daae5a5 1069 #define RCC_PERIPHCLK_TIM17 ((uint32_t)0x01000000)
bogdanm 92:4fc01daae5a5 1070
bogdanm 92:4fc01daae5a5 1071 #endif /* STM32F302xE */
bogdanm 92:4fc01daae5a5 1072
bogdanm 92:4fc01daae5a5 1073 #if defined(STM32F303xE)
bogdanm 92:4fc01daae5a5 1074 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm 92:4fc01daae5a5 1075 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
bogdanm 92:4fc01daae5a5 1076 #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
bogdanm 92:4fc01daae5a5 1077 #define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008)
bogdanm 92:4fc01daae5a5 1078 #define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010)
bogdanm 92:4fc01daae5a5 1079 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
bogdanm 92:4fc01daae5a5 1080 #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
bogdanm 92:4fc01daae5a5 1081 #define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
bogdanm 92:4fc01daae5a5 1082 #define RCC_PERIPHCLK_ADC34 ((uint32_t)0x00000100)
bogdanm 92:4fc01daae5a5 1083 #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
bogdanm 92:4fc01daae5a5 1084 #define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
bogdanm 92:4fc01daae5a5 1085 #define RCC_PERIPHCLK_TIM8 ((uint32_t)0x00002000)
bogdanm 92:4fc01daae5a5 1086 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
bogdanm 92:4fc01daae5a5 1087 #define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
bogdanm 92:4fc01daae5a5 1088 #define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00040000)
bogdanm 92:4fc01daae5a5 1089 #define RCC_PERIPHCLK_TIM2 ((uint32_t)0x00100000)
bogdanm 92:4fc01daae5a5 1090 #define RCC_PERIPHCLK_TIM34 ((uint32_t)0x00200000)
bogdanm 92:4fc01daae5a5 1091 #define RCC_PERIPHCLK_TIM15 ((uint32_t)0x00400000)
bogdanm 92:4fc01daae5a5 1092 #define RCC_PERIPHCLK_TIM16 ((uint32_t)0x00800000)
bogdanm 92:4fc01daae5a5 1093 #define RCC_PERIPHCLK_TIM17 ((uint32_t)0x01000000)
bogdanm 92:4fc01daae5a5 1094 #define RCC_PERIPHCLK_TIM20 ((uint32_t)0x02000000)
bogdanm 92:4fc01daae5a5 1095
bogdanm 92:4fc01daae5a5 1096 #endif /* STM32F303xE */
bogdanm 92:4fc01daae5a5 1097
bogdanm 92:4fc01daae5a5 1098 #if defined(STM32F398xx)
bogdanm 92:4fc01daae5a5 1099 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm 92:4fc01daae5a5 1100 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
bogdanm 92:4fc01daae5a5 1101 #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
bogdanm 92:4fc01daae5a5 1102 #define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008)
bogdanm 92:4fc01daae5a5 1103 #define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010)
bogdanm 92:4fc01daae5a5 1104 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
bogdanm 92:4fc01daae5a5 1105 #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
bogdanm 92:4fc01daae5a5 1106 #define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
bogdanm 92:4fc01daae5a5 1107 #define RCC_PERIPHCLK_ADC34 ((uint32_t)0x00000100)
bogdanm 92:4fc01daae5a5 1108 #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
bogdanm 92:4fc01daae5a5 1109 #define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
bogdanm 92:4fc01daae5a5 1110 #define RCC_PERIPHCLK_TIM8 ((uint32_t)0x00002000)
bogdanm 92:4fc01daae5a5 1111 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
bogdanm 92:4fc01daae5a5 1112 #define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00040000)
bogdanm 92:4fc01daae5a5 1113 #define RCC_PERIPHCLK_TIM2 ((uint32_t)0x00100000)
bogdanm 92:4fc01daae5a5 1114 #define RCC_PERIPHCLK_TIM34 ((uint32_t)0x00200000)
bogdanm 92:4fc01daae5a5 1115 #define RCC_PERIPHCLK_TIM15 ((uint32_t)0x00400000)
bogdanm 92:4fc01daae5a5 1116 #define RCC_PERIPHCLK_TIM16 ((uint32_t)0x00800000)
bogdanm 92:4fc01daae5a5 1117 #define RCC_PERIPHCLK_TIM17 ((uint32_t)0x01000000)
bogdanm 92:4fc01daae5a5 1118 #define RCC_PERIPHCLK_TIM20 ((uint32_t)0x02000000)
bogdanm 92:4fc01daae5a5 1119
Kojto 122:f9eeca106725 1120
bogdanm 92:4fc01daae5a5 1121 #endif /* STM32F398xx */
bogdanm 92:4fc01daae5a5 1122
bogdanm 86:04dd9b1680ae 1123 #if defined(STM32F358xx)
bogdanm 86:04dd9b1680ae 1124 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 1125 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 1126 #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
bogdanm 86:04dd9b1680ae 1127 #define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008)
bogdanm 86:04dd9b1680ae 1128 #define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010)
bogdanm 86:04dd9b1680ae 1129 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
bogdanm 86:04dd9b1680ae 1130 #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
bogdanm 86:04dd9b1680ae 1131 #define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
bogdanm 86:04dd9b1680ae 1132 #define RCC_PERIPHCLK_ADC34 ((uint32_t)0x00000100)
bogdanm 86:04dd9b1680ae 1133 #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
bogdanm 86:04dd9b1680ae 1134 #define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
bogdanm 86:04dd9b1680ae 1135 #define RCC_PERIPHCLK_TIM8 ((uint32_t)0x00002000)
bogdanm 86:04dd9b1680ae 1136 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
bogdanm 86:04dd9b1680ae 1137
bogdanm 86:04dd9b1680ae 1138 #endif /* STM32F358xx */
bogdanm 86:04dd9b1680ae 1139
bogdanm 86:04dd9b1680ae 1140 #if defined(STM32F303x8)
bogdanm 86:04dd9b1680ae 1141 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 1142 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
bogdanm 86:04dd9b1680ae 1143 #define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
bogdanm 86:04dd9b1680ae 1144 #define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
bogdanm 86:04dd9b1680ae 1145 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
bogdanm 86:04dd9b1680ae 1146
bogdanm 86:04dd9b1680ae 1147 #endif /* STM32F303x8 */
bogdanm 86:04dd9b1680ae 1148
bogdanm 86:04dd9b1680ae 1149 #if defined(STM32F334x8)
bogdanm 86:04dd9b1680ae 1150 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 1151 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
bogdanm 86:04dd9b1680ae 1152 #define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
bogdanm 86:04dd9b1680ae 1153 #define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
bogdanm 86:04dd9b1680ae 1154 #define RCC_PERIPHCLK_HRTIM1 ((uint32_t)0x00004000)
bogdanm 86:04dd9b1680ae 1155 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
bogdanm 86:04dd9b1680ae 1156
Kojto 122:f9eeca106725 1157
bogdanm 86:04dd9b1680ae 1158 #endif /* STM32F334x8 */
bogdanm 86:04dd9b1680ae 1159
bogdanm 86:04dd9b1680ae 1160 #if defined(STM32F328xx)
bogdanm 86:04dd9b1680ae 1161 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 1162 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
bogdanm 86:04dd9b1680ae 1163 #define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
bogdanm 86:04dd9b1680ae 1164 #define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
bogdanm 86:04dd9b1680ae 1165 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
bogdanm 86:04dd9b1680ae 1166
bogdanm 86:04dd9b1680ae 1167 #endif /* STM32F328xx */
bogdanm 86:04dd9b1680ae 1168
bogdanm 86:04dd9b1680ae 1169 #if defined(STM32F373xC)
bogdanm 86:04dd9b1680ae 1170 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 1171 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 1172 #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
bogdanm 86:04dd9b1680ae 1173 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
bogdanm 86:04dd9b1680ae 1174 #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
bogdanm 86:04dd9b1680ae 1175 #define RCC_PERIPHCLK_ADC1 ((uint32_t)0x00000080)
bogdanm 86:04dd9b1680ae 1176 #define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
bogdanm 86:04dd9b1680ae 1177 #define RCC_PERIPHCLK_SDADC ((uint32_t)0x00000800)
bogdanm 86:04dd9b1680ae 1178 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
bogdanm 86:04dd9b1680ae 1179 #define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
bogdanm 86:04dd9b1680ae 1180
bogdanm 86:04dd9b1680ae 1181 #endif /* STM32F373xC */
bogdanm 86:04dd9b1680ae 1182
bogdanm 86:04dd9b1680ae 1183 #if defined(STM32F378xx)
bogdanm 86:04dd9b1680ae 1184 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 1185 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 1186 #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
bogdanm 86:04dd9b1680ae 1187 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
bogdanm 86:04dd9b1680ae 1188 #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
bogdanm 86:04dd9b1680ae 1189 #define RCC_PERIPHCLK_ADC1 ((uint32_t)0x00000080)
bogdanm 86:04dd9b1680ae 1190 #define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
bogdanm 86:04dd9b1680ae 1191 #define RCC_PERIPHCLK_SDADC ((uint32_t)0x00000800)
bogdanm 86:04dd9b1680ae 1192 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
bogdanm 86:04dd9b1680ae 1193
bogdanm 86:04dd9b1680ae 1194 #endif /* STM32F378xx */
bogdanm 86:04dd9b1680ae 1195 /**
bogdanm 86:04dd9b1680ae 1196 * @}
bogdanm 86:04dd9b1680ae 1197 */
bogdanm 86:04dd9b1680ae 1198
bogdanm 86:04dd9b1680ae 1199 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
bogdanm 86:04dd9b1680ae 1200
bogdanm 92:4fc01daae5a5 1201 /** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source
bogdanm 86:04dd9b1680ae 1202 * @{
bogdanm 86:04dd9b1680ae 1203 */
Kojto 122:f9eeca106725 1204 #define RCC_USART1CLKSOURCE_PCLK1 RCC_CFGR3_USART1SW_PCLK1
bogdanm 86:04dd9b1680ae 1205 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
bogdanm 86:04dd9b1680ae 1206 #define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
bogdanm 86:04dd9b1680ae 1207 #define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
bogdanm 86:04dd9b1680ae 1208
bogdanm 86:04dd9b1680ae 1209 /**
bogdanm 86:04dd9b1680ae 1210 * @}
bogdanm 86:04dd9b1680ae 1211 */
bogdanm 86:04dd9b1680ae 1212
bogdanm 92:4fc01daae5a5 1213 /** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source
bogdanm 86:04dd9b1680ae 1214 * @{
bogdanm 86:04dd9b1680ae 1215 */
bogdanm 86:04dd9b1680ae 1216 #define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI
bogdanm 86:04dd9b1680ae 1217 #define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK
bogdanm 86:04dd9b1680ae 1218
bogdanm 86:04dd9b1680ae 1219 /**
bogdanm 86:04dd9b1680ae 1220 * @}
bogdanm 86:04dd9b1680ae 1221 */
bogdanm 86:04dd9b1680ae 1222
bogdanm 92:4fc01daae5a5 1223 /** @defgroup RCCEx_I2C3_Clock_Source RCC Extended I2C3 Clock Source
bogdanm 86:04dd9b1680ae 1224 * @{
bogdanm 86:04dd9b1680ae 1225 */
bogdanm 86:04dd9b1680ae 1226 #define RCC_I2C3CLKSOURCE_HSI RCC_CFGR3_I2C3SW_HSI
bogdanm 86:04dd9b1680ae 1227 #define RCC_I2C3CLKSOURCE_SYSCLK RCC_CFGR3_I2C3SW_SYSCLK
bogdanm 86:04dd9b1680ae 1228
bogdanm 86:04dd9b1680ae 1229 /**
bogdanm 86:04dd9b1680ae 1230 * @}
bogdanm 86:04dd9b1680ae 1231 */
bogdanm 86:04dd9b1680ae 1232
bogdanm 92:4fc01daae5a5 1233 /** @defgroup RCCEx_ADC1_Clock_Source RCC Extended ADC1 Clock Source
bogdanm 86:04dd9b1680ae 1234 * @{
bogdanm 86:04dd9b1680ae 1235 */
bogdanm 86:04dd9b1680ae 1236 #define RCC_ADC1PLLCLK_OFF RCC_CFGR2_ADC1PRES_NO
bogdanm 86:04dd9b1680ae 1237 #define RCC_ADC1PLLCLK_DIV1 RCC_CFGR2_ADC1PRES_DIV1
bogdanm 86:04dd9b1680ae 1238 #define RCC_ADC1PLLCLK_DIV2 RCC_CFGR2_ADC1PRES_DIV2
bogdanm 86:04dd9b1680ae 1239 #define RCC_ADC1PLLCLK_DIV4 RCC_CFGR2_ADC1PRES_DIV4
bogdanm 86:04dd9b1680ae 1240 #define RCC_ADC1PLLCLK_DIV6 RCC_CFGR2_ADC1PRES_DIV6
bogdanm 86:04dd9b1680ae 1241 #define RCC_ADC1PLLCLK_DIV8 RCC_CFGR2_ADC1PRES_DIV8
bogdanm 86:04dd9b1680ae 1242 #define RCC_ADC1PLLCLK_DIV10 RCC_CFGR2_ADC1PRES_DIV10
bogdanm 86:04dd9b1680ae 1243 #define RCC_ADC1PLLCLK_DIV12 RCC_CFGR2_ADC1PRES_DIV12
bogdanm 86:04dd9b1680ae 1244 #define RCC_ADC1PLLCLK_DIV16 RCC_CFGR2_ADC1PRES_DIV16
bogdanm 86:04dd9b1680ae 1245 #define RCC_ADC1PLLCLK_DIV32 RCC_CFGR2_ADC1PRES_DIV32
bogdanm 86:04dd9b1680ae 1246 #define RCC_ADC1PLLCLK_DIV64 RCC_CFGR2_ADC1PRES_DIV64
bogdanm 86:04dd9b1680ae 1247 #define RCC_ADC1PLLCLK_DIV128 RCC_CFGR2_ADC1PRES_DIV128
bogdanm 86:04dd9b1680ae 1248 #define RCC_ADC1PLLCLK_DIV256 RCC_CFGR2_ADC1PRES_DIV256
bogdanm 86:04dd9b1680ae 1249
bogdanm 86:04dd9b1680ae 1250 /**
bogdanm 86:04dd9b1680ae 1251 * @}
bogdanm 86:04dd9b1680ae 1252 */
bogdanm 86:04dd9b1680ae 1253
bogdanm 92:4fc01daae5a5 1254 /** @defgroup RCCEx_I2S_Clock_Source RCC Extended I2S Clock Source
bogdanm 86:04dd9b1680ae 1255 * @{
bogdanm 86:04dd9b1680ae 1256 */
bogdanm 86:04dd9b1680ae 1257 #define RCC_I2SCLKSOURCE_SYSCLK RCC_CFGR_I2SSRC_SYSCLK
bogdanm 86:04dd9b1680ae 1258 #define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC_EXT
bogdanm 86:04dd9b1680ae 1259
bogdanm 86:04dd9b1680ae 1260 /**
bogdanm 86:04dd9b1680ae 1261 * @}
bogdanm 86:04dd9b1680ae 1262 */
bogdanm 86:04dd9b1680ae 1263
bogdanm 92:4fc01daae5a5 1264 /** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source
bogdanm 86:04dd9b1680ae 1265 * @{
bogdanm 86:04dd9b1680ae 1266 */
bogdanm 86:04dd9b1680ae 1267 #define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK
bogdanm 86:04dd9b1680ae 1268 #define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL
bogdanm 86:04dd9b1680ae 1269
bogdanm 86:04dd9b1680ae 1270 /**
bogdanm 86:04dd9b1680ae 1271 * @}
bogdanm 86:04dd9b1680ae 1272 */
bogdanm 86:04dd9b1680ae 1273
bogdanm 92:4fc01daae5a5 1274 /** @defgroup RCCEx_TIM15_Clock_Source RCC Extended TIM15 Clock Source
bogdanm 86:04dd9b1680ae 1275 * @{
bogdanm 86:04dd9b1680ae 1276 */
bogdanm 86:04dd9b1680ae 1277 #define RCC_TIM15CLK_HCLK RCC_CFGR3_TIM15SW_HCLK
bogdanm 86:04dd9b1680ae 1278 #define RCC_TIM15CLK_PLLCLK RCC_CFGR3_TIM15SW_PLL
bogdanm 86:04dd9b1680ae 1279
bogdanm 86:04dd9b1680ae 1280 /**
bogdanm 86:04dd9b1680ae 1281 * @}
bogdanm 86:04dd9b1680ae 1282 */
bogdanm 86:04dd9b1680ae 1283
bogdanm 92:4fc01daae5a5 1284 /** @defgroup RCCEx_TIM16_Clock_Source RCC Extended TIM16 Clock Source
bogdanm 86:04dd9b1680ae 1285 * @{
bogdanm 86:04dd9b1680ae 1286 */
bogdanm 86:04dd9b1680ae 1287 #define RCC_TIM16CLK_HCLK RCC_CFGR3_TIM16SW_HCLK
bogdanm 86:04dd9b1680ae 1288 #define RCC_TIM16CLK_PLLCLK RCC_CFGR3_TIM16SW_PLL
bogdanm 86:04dd9b1680ae 1289
bogdanm 86:04dd9b1680ae 1290 /**
bogdanm 86:04dd9b1680ae 1291 * @}
bogdanm 86:04dd9b1680ae 1292 */
bogdanm 86:04dd9b1680ae 1293
bogdanm 92:4fc01daae5a5 1294 /** @defgroup RCCEx_TIM17_Clock_Source RCC Extended TIM17 Clock Source
bogdanm 86:04dd9b1680ae 1295 * @{
bogdanm 86:04dd9b1680ae 1296 */
bogdanm 86:04dd9b1680ae 1297 #define RCC_TIM17CLK_HCLK RCC_CFGR3_TIM17SW_HCLK
bogdanm 86:04dd9b1680ae 1298 #define RCC_TIM17CLK_PLLCLK RCC_CFGR3_TIM17SW_PLL
bogdanm 86:04dd9b1680ae 1299
bogdanm 86:04dd9b1680ae 1300 /**
bogdanm 86:04dd9b1680ae 1301 * @}
bogdanm 86:04dd9b1680ae 1302 */
bogdanm 86:04dd9b1680ae 1303
bogdanm 86:04dd9b1680ae 1304 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
bogdanm 86:04dd9b1680ae 1305
bogdanm 86:04dd9b1680ae 1306 #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
bogdanm 86:04dd9b1680ae 1307
bogdanm 92:4fc01daae5a5 1308 /** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source
bogdanm 86:04dd9b1680ae 1309 * @{
bogdanm 86:04dd9b1680ae 1310 */
Kojto 122:f9eeca106725 1311 #define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK2
bogdanm 86:04dd9b1680ae 1312 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
bogdanm 86:04dd9b1680ae 1313 #define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
bogdanm 86:04dd9b1680ae 1314 #define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
bogdanm 86:04dd9b1680ae 1315
bogdanm 86:04dd9b1680ae 1316 /**
bogdanm 86:04dd9b1680ae 1317 * @}
bogdanm 86:04dd9b1680ae 1318 */
bogdanm 86:04dd9b1680ae 1319
bogdanm 92:4fc01daae5a5 1320 /** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source
bogdanm 86:04dd9b1680ae 1321 * @{
bogdanm 86:04dd9b1680ae 1322 */
bogdanm 86:04dd9b1680ae 1323 #define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI
bogdanm 86:04dd9b1680ae 1324 #define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK
bogdanm 86:04dd9b1680ae 1325
bogdanm 86:04dd9b1680ae 1326 /**
bogdanm 86:04dd9b1680ae 1327 * @}
bogdanm 86:04dd9b1680ae 1328 */
bogdanm 86:04dd9b1680ae 1329
bogdanm 92:4fc01daae5a5 1330 /** @defgroup RCCEx_ADC12_Clock_Source RCC Extended ADC12 Clock Source
bogdanm 86:04dd9b1680ae 1331 * @{
bogdanm 86:04dd9b1680ae 1332 */
bogdanm 86:04dd9b1680ae 1333
bogdanm 86:04dd9b1680ae 1334 /* ADC1 & ADC2 */
bogdanm 86:04dd9b1680ae 1335 #define RCC_ADC12PLLCLK_OFF RCC_CFGR2_ADCPRE12_NO
bogdanm 86:04dd9b1680ae 1336 #define RCC_ADC12PLLCLK_DIV1 RCC_CFGR2_ADCPRE12_DIV1
bogdanm 86:04dd9b1680ae 1337 #define RCC_ADC12PLLCLK_DIV2 RCC_CFGR2_ADCPRE12_DIV2
bogdanm 86:04dd9b1680ae 1338 #define RCC_ADC12PLLCLK_DIV4 RCC_CFGR2_ADCPRE12_DIV4
bogdanm 86:04dd9b1680ae 1339 #define RCC_ADC12PLLCLK_DIV6 RCC_CFGR2_ADCPRE12_DIV6
bogdanm 86:04dd9b1680ae 1340 #define RCC_ADC12PLLCLK_DIV8 RCC_CFGR2_ADCPRE12_DIV8
bogdanm 86:04dd9b1680ae 1341 #define RCC_ADC12PLLCLK_DIV10 RCC_CFGR2_ADCPRE12_DIV10
bogdanm 86:04dd9b1680ae 1342 #define RCC_ADC12PLLCLK_DIV12 RCC_CFGR2_ADCPRE12_DIV12
bogdanm 86:04dd9b1680ae 1343 #define RCC_ADC12PLLCLK_DIV16 RCC_CFGR2_ADCPRE12_DIV16
bogdanm 86:04dd9b1680ae 1344 #define RCC_ADC12PLLCLK_DIV32 RCC_CFGR2_ADCPRE12_DIV32
bogdanm 86:04dd9b1680ae 1345 #define RCC_ADC12PLLCLK_DIV64 RCC_CFGR2_ADCPRE12_DIV64
bogdanm 86:04dd9b1680ae 1346 #define RCC_ADC12PLLCLK_DIV128 RCC_CFGR2_ADCPRE12_DIV128
bogdanm 86:04dd9b1680ae 1347 #define RCC_ADC12PLLCLK_DIV256 RCC_CFGR2_ADCPRE12_DIV256
bogdanm 86:04dd9b1680ae 1348
bogdanm 86:04dd9b1680ae 1349 /**
bogdanm 86:04dd9b1680ae 1350 * @}
bogdanm 86:04dd9b1680ae 1351 */
bogdanm 86:04dd9b1680ae 1352
bogdanm 92:4fc01daae5a5 1353 /** @defgroup RCCEx_I2S_Clock_Source RCC Extended I2S Clock Source
bogdanm 86:04dd9b1680ae 1354 * @{
bogdanm 86:04dd9b1680ae 1355 */
bogdanm 86:04dd9b1680ae 1356 #define RCC_I2SCLKSOURCE_SYSCLK RCC_CFGR_I2SSRC_SYSCLK
bogdanm 86:04dd9b1680ae 1357 #define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC_EXT
bogdanm 86:04dd9b1680ae 1358
bogdanm 86:04dd9b1680ae 1359 /**
bogdanm 86:04dd9b1680ae 1360 * @}
bogdanm 86:04dd9b1680ae 1361 */
bogdanm 92:4fc01daae5a5 1362 /** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source
bogdanm 86:04dd9b1680ae 1363 * @{
bogdanm 86:04dd9b1680ae 1364 */
bogdanm 86:04dd9b1680ae 1365 #define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK
bogdanm 86:04dd9b1680ae 1366 #define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL
bogdanm 86:04dd9b1680ae 1367
bogdanm 86:04dd9b1680ae 1368 /**
bogdanm 86:04dd9b1680ae 1369 * @}
bogdanm 86:04dd9b1680ae 1370 */
bogdanm 86:04dd9b1680ae 1371
bogdanm 92:4fc01daae5a5 1372 /** @defgroup RCCEx_UART4_Clock_Source RCC Extended UART4 Clock Source
bogdanm 86:04dd9b1680ae 1373 * @{
bogdanm 86:04dd9b1680ae 1374 */
bogdanm 86:04dd9b1680ae 1375 #define RCC_UART4CLKSOURCE_PCLK1 RCC_CFGR3_UART4SW_PCLK
bogdanm 86:04dd9b1680ae 1376 #define RCC_UART4CLKSOURCE_SYSCLK RCC_CFGR3_UART4SW_SYSCLK
bogdanm 86:04dd9b1680ae 1377 #define RCC_UART4CLKSOURCE_LSE RCC_CFGR3_UART4SW_LSE
bogdanm 86:04dd9b1680ae 1378 #define RCC_UART4CLKSOURCE_HSI RCC_CFGR3_UART4SW_HSI
bogdanm 86:04dd9b1680ae 1379
bogdanm 86:04dd9b1680ae 1380 /**
bogdanm 86:04dd9b1680ae 1381 * @}
bogdanm 86:04dd9b1680ae 1382 */
bogdanm 86:04dd9b1680ae 1383
bogdanm 92:4fc01daae5a5 1384 /** @defgroup RCCEx_UART5_Clock_Source RCC Extended UART5 Clock Source
bogdanm 86:04dd9b1680ae 1385 * @{
bogdanm 86:04dd9b1680ae 1386 */
bogdanm 86:04dd9b1680ae 1387 #define RCC_UART5CLKSOURCE_PCLK1 RCC_CFGR3_UART5SW_PCLK
bogdanm 86:04dd9b1680ae 1388 #define RCC_UART5CLKSOURCE_SYSCLK RCC_CFGR3_UART5SW_SYSCLK
bogdanm 86:04dd9b1680ae 1389 #define RCC_UART5CLKSOURCE_LSE RCC_CFGR3_UART5SW_LSE
bogdanm 86:04dd9b1680ae 1390 #define RCC_UART5CLKSOURCE_HSI RCC_CFGR3_UART5SW_HSI
bogdanm 86:04dd9b1680ae 1391
bogdanm 86:04dd9b1680ae 1392 /**
bogdanm 86:04dd9b1680ae 1393 * @}
bogdanm 86:04dd9b1680ae 1394 */
bogdanm 86:04dd9b1680ae 1395
bogdanm 86:04dd9b1680ae 1396 #endif /* STM32F302xC || STM32F303xC || STM32F358xx */
bogdanm 86:04dd9b1680ae 1397
bogdanm 92:4fc01daae5a5 1398 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
bogdanm 92:4fc01daae5a5 1399
bogdanm 92:4fc01daae5a5 1400 /** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source
bogdanm 86:04dd9b1680ae 1401 * @{
bogdanm 86:04dd9b1680ae 1402 */
Kojto 122:f9eeca106725 1403 #define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK2
bogdanm 86:04dd9b1680ae 1404 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
bogdanm 86:04dd9b1680ae 1405 #define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
bogdanm 86:04dd9b1680ae 1406 #define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
bogdanm 86:04dd9b1680ae 1407
bogdanm 86:04dd9b1680ae 1408 /**
bogdanm 86:04dd9b1680ae 1409 * @}
bogdanm 86:04dd9b1680ae 1410 */
bogdanm 86:04dd9b1680ae 1411
bogdanm 92:4fc01daae5a5 1412 /** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source
bogdanm 92:4fc01daae5a5 1413 * @{
bogdanm 92:4fc01daae5a5 1414 */
bogdanm 92:4fc01daae5a5 1415 #define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI
bogdanm 92:4fc01daae5a5 1416 #define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK
bogdanm 92:4fc01daae5a5 1417
bogdanm 92:4fc01daae5a5 1418 /**
bogdanm 92:4fc01daae5a5 1419 * @}
bogdanm 92:4fc01daae5a5 1420 */
bogdanm 92:4fc01daae5a5 1421
bogdanm 92:4fc01daae5a5 1422 /** @defgroup RCCEx_I2C3_Clock_Source RCC Extended I2C3 Clock Source
bogdanm 92:4fc01daae5a5 1423 * @{
bogdanm 92:4fc01daae5a5 1424 */
bogdanm 92:4fc01daae5a5 1425 #define RCC_I2C3CLKSOURCE_HSI RCC_CFGR3_I2C3SW_HSI
bogdanm 92:4fc01daae5a5 1426 #define RCC_I2C3CLKSOURCE_SYSCLK RCC_CFGR3_I2C3SW_SYSCLK
bogdanm 92:4fc01daae5a5 1427
bogdanm 92:4fc01daae5a5 1428 /**
bogdanm 92:4fc01daae5a5 1429 * @}
bogdanm 92:4fc01daae5a5 1430 */
bogdanm 92:4fc01daae5a5 1431
bogdanm 92:4fc01daae5a5 1432 /** @defgroup RCCEx_ADC12_Clock_Source RCC Extended ADC12 Clock Source
bogdanm 92:4fc01daae5a5 1433 * @{
bogdanm 92:4fc01daae5a5 1434 */
bogdanm 92:4fc01daae5a5 1435
bogdanm 92:4fc01daae5a5 1436 /* ADC1 & ADC2 */
bogdanm 92:4fc01daae5a5 1437 #define RCC_ADC12PLLCLK_OFF RCC_CFGR2_ADCPRE12_NO
bogdanm 92:4fc01daae5a5 1438 #define RCC_ADC12PLLCLK_DIV1 RCC_CFGR2_ADCPRE12_DIV1
bogdanm 92:4fc01daae5a5 1439 #define RCC_ADC12PLLCLK_DIV2 RCC_CFGR2_ADCPRE12_DIV2
bogdanm 92:4fc01daae5a5 1440 #define RCC_ADC12PLLCLK_DIV4 RCC_CFGR2_ADCPRE12_DIV4
bogdanm 92:4fc01daae5a5 1441 #define RCC_ADC12PLLCLK_DIV6 RCC_CFGR2_ADCPRE12_DIV6
bogdanm 92:4fc01daae5a5 1442 #define RCC_ADC12PLLCLK_DIV8 RCC_CFGR2_ADCPRE12_DIV8
bogdanm 92:4fc01daae5a5 1443 #define RCC_ADC12PLLCLK_DIV10 RCC_CFGR2_ADCPRE12_DIV10
bogdanm 92:4fc01daae5a5 1444 #define RCC_ADC12PLLCLK_DIV12 RCC_CFGR2_ADCPRE12_DIV12
bogdanm 92:4fc01daae5a5 1445 #define RCC_ADC12PLLCLK_DIV16 RCC_CFGR2_ADCPRE12_DIV16
bogdanm 92:4fc01daae5a5 1446 #define RCC_ADC12PLLCLK_DIV32 RCC_CFGR2_ADCPRE12_DIV32
bogdanm 92:4fc01daae5a5 1447 #define RCC_ADC12PLLCLK_DIV64 RCC_CFGR2_ADCPRE12_DIV64
bogdanm 92:4fc01daae5a5 1448 #define RCC_ADC12PLLCLK_DIV128 RCC_CFGR2_ADCPRE12_DIV128
bogdanm 92:4fc01daae5a5 1449 #define RCC_ADC12PLLCLK_DIV256 RCC_CFGR2_ADCPRE12_DIV256
bogdanm 92:4fc01daae5a5 1450
bogdanm 92:4fc01daae5a5 1451 /**
bogdanm 92:4fc01daae5a5 1452 * @}
bogdanm 92:4fc01daae5a5 1453 */
bogdanm 92:4fc01daae5a5 1454
bogdanm 92:4fc01daae5a5 1455 /** @defgroup RCCEx_I2S_Clock_Source RCC Extended I2S Clock Source
bogdanm 92:4fc01daae5a5 1456 * @{
bogdanm 92:4fc01daae5a5 1457 */
bogdanm 92:4fc01daae5a5 1458 #define RCC_I2SCLKSOURCE_SYSCLK RCC_CFGR_I2SSRC_SYSCLK
bogdanm 92:4fc01daae5a5 1459 #define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC_EXT
bogdanm 92:4fc01daae5a5 1460
bogdanm 92:4fc01daae5a5 1461 /**
bogdanm 92:4fc01daae5a5 1462 * @}
bogdanm 92:4fc01daae5a5 1463 */
bogdanm 92:4fc01daae5a5 1464
bogdanm 92:4fc01daae5a5 1465 /** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source
bogdanm 92:4fc01daae5a5 1466 * @{
bogdanm 92:4fc01daae5a5 1467 */
bogdanm 92:4fc01daae5a5 1468 #define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK
bogdanm 92:4fc01daae5a5 1469 #define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL
bogdanm 92:4fc01daae5a5 1470
bogdanm 92:4fc01daae5a5 1471 /**
bogdanm 92:4fc01daae5a5 1472 * @}
bogdanm 92:4fc01daae5a5 1473 */
bogdanm 92:4fc01daae5a5 1474
bogdanm 92:4fc01daae5a5 1475 /** @defgroup RCCEx_TIM2_Clock_Source RCC Extended TIM2 Clock Source
bogdanm 92:4fc01daae5a5 1476 * @{
bogdanm 92:4fc01daae5a5 1477 */
bogdanm 92:4fc01daae5a5 1478 #define RCC_TIM2CLK_HCLK RCC_CFGR3_TIM2SW_HCLK
bogdanm 92:4fc01daae5a5 1479 #define RCC_TIM2CLK_PLLCLK RCC_CFGR3_TIM2SW_PLL
bogdanm 92:4fc01daae5a5 1480
bogdanm 92:4fc01daae5a5 1481 /**
bogdanm 92:4fc01daae5a5 1482 * @}
bogdanm 92:4fc01daae5a5 1483 */
bogdanm 92:4fc01daae5a5 1484
bogdanm 92:4fc01daae5a5 1485 /** @defgroup RCCEx_TIM34_Clock_Source RCC Extended TIM3 & TIM4 Clock Source
bogdanm 92:4fc01daae5a5 1486 * @{
bogdanm 92:4fc01daae5a5 1487 */
bogdanm 92:4fc01daae5a5 1488 #define RCC_TIM34CLK_HCLK RCC_CFGR3_TIM34SW_HCLK
bogdanm 92:4fc01daae5a5 1489 #define RCC_TIM34CLK_PLLCLK RCC_CFGR3_TIM34SW_PLL
bogdanm 92:4fc01daae5a5 1490
bogdanm 92:4fc01daae5a5 1491 /**
bogdanm 92:4fc01daae5a5 1492 * @}
bogdanm 92:4fc01daae5a5 1493 */
bogdanm 92:4fc01daae5a5 1494
bogdanm 92:4fc01daae5a5 1495 /** @defgroup RCCEx_TIM15_Clock_Source RCC Extended TIM15 Clock Source
bogdanm 92:4fc01daae5a5 1496 * @{
bogdanm 92:4fc01daae5a5 1497 */
bogdanm 92:4fc01daae5a5 1498 #define RCC_TIM15CLK_HCLK RCC_CFGR3_TIM15SW_HCLK
bogdanm 92:4fc01daae5a5 1499 #define RCC_TIM15CLK_PLLCLK RCC_CFGR3_TIM15SW_PLL
bogdanm 92:4fc01daae5a5 1500
bogdanm 92:4fc01daae5a5 1501 /**
bogdanm 92:4fc01daae5a5 1502 * @}
bogdanm 92:4fc01daae5a5 1503 */
bogdanm 92:4fc01daae5a5 1504
bogdanm 92:4fc01daae5a5 1505 /** @defgroup RCCEx_TIM16_Clock_Source RCC Extended TIM16 Clock Source
bogdanm 92:4fc01daae5a5 1506 * @{
bogdanm 92:4fc01daae5a5 1507 */
bogdanm 92:4fc01daae5a5 1508 #define RCC_TIM16CLK_HCLK RCC_CFGR3_TIM16SW_HCLK
bogdanm 92:4fc01daae5a5 1509 #define RCC_TIM16CLK_PLLCLK RCC_CFGR3_TIM16SW_PLL
bogdanm 92:4fc01daae5a5 1510
bogdanm 92:4fc01daae5a5 1511 /**
bogdanm 92:4fc01daae5a5 1512 * @}
bogdanm 92:4fc01daae5a5 1513 */
bogdanm 92:4fc01daae5a5 1514
bogdanm 92:4fc01daae5a5 1515 /** @defgroup RCCEx_TIM17_Clock_Source RCC Extended TIM17 Clock Source
bogdanm 92:4fc01daae5a5 1516 * @{
bogdanm 92:4fc01daae5a5 1517 */
bogdanm 92:4fc01daae5a5 1518 #define RCC_TIM17CLK_HCLK RCC_CFGR3_TIM17SW_HCLK
bogdanm 92:4fc01daae5a5 1519 #define RCC_TIM17CLK_PLLCLK RCC_CFGR3_TIM17SW_PLL
bogdanm 92:4fc01daae5a5 1520
bogdanm 92:4fc01daae5a5 1521 /**
bogdanm 92:4fc01daae5a5 1522 * @}
bogdanm 92:4fc01daae5a5 1523 */
bogdanm 92:4fc01daae5a5 1524
bogdanm 92:4fc01daae5a5 1525 /** @defgroup RCCEx_UART4_Clock_Source RCC Extended UART4 Clock Source
bogdanm 92:4fc01daae5a5 1526 * @{
bogdanm 92:4fc01daae5a5 1527 */
bogdanm 92:4fc01daae5a5 1528 #define RCC_UART4CLKSOURCE_PCLK1 RCC_CFGR3_UART4SW_PCLK
bogdanm 92:4fc01daae5a5 1529 #define RCC_UART4CLKSOURCE_SYSCLK RCC_CFGR3_UART4SW_SYSCLK
bogdanm 92:4fc01daae5a5 1530 #define RCC_UART4CLKSOURCE_LSE RCC_CFGR3_UART4SW_LSE
bogdanm 92:4fc01daae5a5 1531 #define RCC_UART4CLKSOURCE_HSI RCC_CFGR3_UART4SW_HSI
bogdanm 92:4fc01daae5a5 1532
bogdanm 92:4fc01daae5a5 1533 /**
bogdanm 92:4fc01daae5a5 1534 * @}
bogdanm 92:4fc01daae5a5 1535 */
bogdanm 92:4fc01daae5a5 1536
bogdanm 92:4fc01daae5a5 1537 /** @defgroup RCCEx_UART5_Clock_Source RCC Extended UART5 Clock Source
bogdanm 92:4fc01daae5a5 1538 * @{
bogdanm 92:4fc01daae5a5 1539 */
bogdanm 92:4fc01daae5a5 1540 #define RCC_UART5CLKSOURCE_PCLK1 RCC_CFGR3_UART5SW_PCLK
bogdanm 92:4fc01daae5a5 1541 #define RCC_UART5CLKSOURCE_SYSCLK RCC_CFGR3_UART5SW_SYSCLK
bogdanm 92:4fc01daae5a5 1542 #define RCC_UART5CLKSOURCE_LSE RCC_CFGR3_UART5SW_LSE
bogdanm 92:4fc01daae5a5 1543 #define RCC_UART5CLKSOURCE_HSI RCC_CFGR3_UART5SW_HSI
bogdanm 92:4fc01daae5a5 1544
bogdanm 92:4fc01daae5a5 1545 /**
bogdanm 92:4fc01daae5a5 1546 * @}
bogdanm 92:4fc01daae5a5 1547 */
bogdanm 92:4fc01daae5a5 1548
bogdanm 92:4fc01daae5a5 1549 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
bogdanm 92:4fc01daae5a5 1550
bogdanm 92:4fc01daae5a5 1551 #if defined(STM32F303xE) || defined(STM32F398xx)
bogdanm 92:4fc01daae5a5 1552 /** @defgroup RCCEx_TIM20_Clock_Source RCC Extended TIM20 Clock Source
bogdanm 92:4fc01daae5a5 1553 * @{
bogdanm 92:4fc01daae5a5 1554 */
bogdanm 92:4fc01daae5a5 1555 #define RCC_TIM20CLK_HCLK RCC_CFGR3_TIM20SW_HCLK
bogdanm 92:4fc01daae5a5 1556 #define RCC_TIM20CLK_PLLCLK RCC_CFGR3_TIM20SW_PLL
bogdanm 92:4fc01daae5a5 1557
bogdanm 92:4fc01daae5a5 1558 /**
bogdanm 92:4fc01daae5a5 1559 * @}
bogdanm 92:4fc01daae5a5 1560 */
bogdanm 92:4fc01daae5a5 1561 #endif /* STM32F303xE || STM32F398xx */
bogdanm 92:4fc01daae5a5 1562
Kojto 122:f9eeca106725 1563 #if defined(STM32F303xE) || defined(STM32F398xx)\
Kojto 122:f9eeca106725 1564 || defined(STM32F303xC) || defined(STM32F358xx)
bogdanm 92:4fc01daae5a5 1565
bogdanm 92:4fc01daae5a5 1566 /** @defgroup RCCEx_ADC34_Clock_Source RCC Extended ADC34 Clock Source
bogdanm 86:04dd9b1680ae 1567 * @{
bogdanm 86:04dd9b1680ae 1568 */
bogdanm 86:04dd9b1680ae 1569
bogdanm 86:04dd9b1680ae 1570 /* ADC3 & ADC4 */
bogdanm 86:04dd9b1680ae 1571 #define RCC_ADC34PLLCLK_OFF RCC_CFGR2_ADCPRE34_NO
bogdanm 86:04dd9b1680ae 1572 #define RCC_ADC34PLLCLK_DIV1 RCC_CFGR2_ADCPRE34_DIV1
bogdanm 86:04dd9b1680ae 1573 #define RCC_ADC34PLLCLK_DIV2 RCC_CFGR2_ADCPRE34_DIV2
bogdanm 86:04dd9b1680ae 1574 #define RCC_ADC34PLLCLK_DIV4 RCC_CFGR2_ADCPRE34_DIV4
bogdanm 86:04dd9b1680ae 1575 #define RCC_ADC34PLLCLK_DIV6 RCC_CFGR2_ADCPRE34_DIV6
bogdanm 86:04dd9b1680ae 1576 #define RCC_ADC34PLLCLK_DIV8 RCC_CFGR2_ADCPRE34_DIV8
bogdanm 86:04dd9b1680ae 1577 #define RCC_ADC34PLLCLK_DIV10 RCC_CFGR2_ADCPRE34_DIV10
bogdanm 86:04dd9b1680ae 1578 #define RCC_ADC34PLLCLK_DIV12 RCC_CFGR2_ADCPRE34_DIV12
bogdanm 86:04dd9b1680ae 1579 #define RCC_ADC34PLLCLK_DIV16 RCC_CFGR2_ADCPRE34_DIV16
bogdanm 86:04dd9b1680ae 1580 #define RCC_ADC34PLLCLK_DIV32 RCC_CFGR2_ADCPRE34_DIV32
bogdanm 86:04dd9b1680ae 1581 #define RCC_ADC34PLLCLK_DIV64 RCC_CFGR2_ADCPRE34_DIV64
bogdanm 86:04dd9b1680ae 1582 #define RCC_ADC34PLLCLK_DIV128 RCC_CFGR2_ADCPRE34_DIV128
bogdanm 86:04dd9b1680ae 1583 #define RCC_ADC34PLLCLK_DIV256 RCC_CFGR2_ADCPRE34_DIV256
bogdanm 86:04dd9b1680ae 1584
bogdanm 86:04dd9b1680ae 1585 /**
bogdanm 86:04dd9b1680ae 1586 * @}
bogdanm 86:04dd9b1680ae 1587 */
bogdanm 86:04dd9b1680ae 1588
bogdanm 92:4fc01daae5a5 1589 /** @defgroup RCCEx_TIM8_Clock_Source RCC Extended TIM8 Clock Source
bogdanm 86:04dd9b1680ae 1590 * @{
bogdanm 86:04dd9b1680ae 1591 */
bogdanm 86:04dd9b1680ae 1592 #define RCC_TIM8CLK_HCLK RCC_CFGR3_TIM8SW_HCLK
bogdanm 86:04dd9b1680ae 1593 #define RCC_TIM8CLK_PLLCLK RCC_CFGR3_TIM8SW_PLL
bogdanm 86:04dd9b1680ae 1594
bogdanm 86:04dd9b1680ae 1595 /**
bogdanm 86:04dd9b1680ae 1596 * @}
bogdanm 86:04dd9b1680ae 1597 */
bogdanm 86:04dd9b1680ae 1598
bogdanm 92:4fc01daae5a5 1599 #endif /* STM32F303xC || STM32F303xE || STM32F398xx || STM32F358xx */
bogdanm 86:04dd9b1680ae 1600
bogdanm 86:04dd9b1680ae 1601 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
bogdanm 86:04dd9b1680ae 1602
bogdanm 92:4fc01daae5a5 1603 /** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source
bogdanm 86:04dd9b1680ae 1604 * @{
bogdanm 86:04dd9b1680ae 1605 */
Kojto 122:f9eeca106725 1606 #define RCC_USART1CLKSOURCE_PCLK1 RCC_CFGR3_USART1SW_PCLK1
bogdanm 86:04dd9b1680ae 1607 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
bogdanm 86:04dd9b1680ae 1608 #define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
bogdanm 86:04dd9b1680ae 1609 #define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
bogdanm 86:04dd9b1680ae 1610
bogdanm 86:04dd9b1680ae 1611 /**
bogdanm 86:04dd9b1680ae 1612 * @}
bogdanm 86:04dd9b1680ae 1613 */
bogdanm 86:04dd9b1680ae 1614
bogdanm 92:4fc01daae5a5 1615 /** @defgroup RCCEx_ADC12_Clock_Source RCC Extended ADC12 Clock Source
bogdanm 86:04dd9b1680ae 1616 * @{
bogdanm 86:04dd9b1680ae 1617 */
bogdanm 86:04dd9b1680ae 1618 /* ADC1 & ADC2 */
bogdanm 86:04dd9b1680ae 1619 #define RCC_ADC12PLLCLK_OFF RCC_CFGR2_ADCPRE12_NO
bogdanm 86:04dd9b1680ae 1620 #define RCC_ADC12PLLCLK_DIV1 RCC_CFGR2_ADCPRE12_DIV1
bogdanm 86:04dd9b1680ae 1621 #define RCC_ADC12PLLCLK_DIV2 RCC_CFGR2_ADCPRE12_DIV2
bogdanm 86:04dd9b1680ae 1622 #define RCC_ADC12PLLCLK_DIV4 RCC_CFGR2_ADCPRE12_DIV4
bogdanm 86:04dd9b1680ae 1623 #define RCC_ADC12PLLCLK_DIV6 RCC_CFGR2_ADCPRE12_DIV6
bogdanm 86:04dd9b1680ae 1624 #define RCC_ADC12PLLCLK_DIV8 RCC_CFGR2_ADCPRE12_DIV8
bogdanm 86:04dd9b1680ae 1625 #define RCC_ADC12PLLCLK_DIV10 RCC_CFGR2_ADCPRE12_DIV10
bogdanm 86:04dd9b1680ae 1626 #define RCC_ADC12PLLCLK_DIV12 RCC_CFGR2_ADCPRE12_DIV12
bogdanm 86:04dd9b1680ae 1627 #define RCC_ADC12PLLCLK_DIV16 RCC_CFGR2_ADCPRE12_DIV16
bogdanm 86:04dd9b1680ae 1628 #define RCC_ADC12PLLCLK_DIV32 RCC_CFGR2_ADCPRE12_DIV32
bogdanm 86:04dd9b1680ae 1629 #define RCC_ADC12PLLCLK_DIV64 RCC_CFGR2_ADCPRE12_DIV64
bogdanm 86:04dd9b1680ae 1630 #define RCC_ADC12PLLCLK_DIV128 RCC_CFGR2_ADCPRE12_DIV128
bogdanm 86:04dd9b1680ae 1631 #define RCC_ADC12PLLCLK_DIV256 RCC_CFGR2_ADCPRE12_DIV256
bogdanm 86:04dd9b1680ae 1632
bogdanm 86:04dd9b1680ae 1633 /**
bogdanm 86:04dd9b1680ae 1634 * @}
bogdanm 86:04dd9b1680ae 1635 */
bogdanm 86:04dd9b1680ae 1636
bogdanm 92:4fc01daae5a5 1637 /** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source
bogdanm 86:04dd9b1680ae 1638 * @{
bogdanm 86:04dd9b1680ae 1639 */
bogdanm 86:04dd9b1680ae 1640 #define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK
bogdanm 86:04dd9b1680ae 1641 #define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL
bogdanm 86:04dd9b1680ae 1642
bogdanm 86:04dd9b1680ae 1643 /**
bogdanm 86:04dd9b1680ae 1644 * @}
bogdanm 86:04dd9b1680ae 1645 */
bogdanm 86:04dd9b1680ae 1646
bogdanm 86:04dd9b1680ae 1647 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
bogdanm 86:04dd9b1680ae 1648
bogdanm 86:04dd9b1680ae 1649 #if defined(STM32F334x8)
bogdanm 86:04dd9b1680ae 1650
bogdanm 92:4fc01daae5a5 1651 /** @defgroup RCCEx_HRTIM1_Clock_Source RCC Extended HRTIM1 Clock Source
bogdanm 86:04dd9b1680ae 1652 * @{
bogdanm 86:04dd9b1680ae 1653 */
bogdanm 86:04dd9b1680ae 1654 #define RCC_HRTIM1CLK_HCLK RCC_CFGR3_HRTIM1SW_HCLK
bogdanm 86:04dd9b1680ae 1655 #define RCC_HRTIM1CLK_PLLCLK RCC_CFGR3_HRTIM1SW_PLL
bogdanm 86:04dd9b1680ae 1656
bogdanm 86:04dd9b1680ae 1657 /**
bogdanm 86:04dd9b1680ae 1658 * @}
bogdanm 86:04dd9b1680ae 1659 */
bogdanm 86:04dd9b1680ae 1660
bogdanm 86:04dd9b1680ae 1661 #endif /* STM32F334x8 */
bogdanm 86:04dd9b1680ae 1662
bogdanm 86:04dd9b1680ae 1663 #if defined(STM32F373xC) || defined(STM32F378xx)
bogdanm 86:04dd9b1680ae 1664
bogdanm 92:4fc01daae5a5 1665 /** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source
bogdanm 86:04dd9b1680ae 1666 * @{
bogdanm 86:04dd9b1680ae 1667 */
Kojto 122:f9eeca106725 1668 #define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK2
bogdanm 86:04dd9b1680ae 1669 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
bogdanm 86:04dd9b1680ae 1670 #define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
bogdanm 86:04dd9b1680ae 1671 #define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
bogdanm 86:04dd9b1680ae 1672
bogdanm 86:04dd9b1680ae 1673 /**
bogdanm 86:04dd9b1680ae 1674 * @}
bogdanm 86:04dd9b1680ae 1675 */
bogdanm 86:04dd9b1680ae 1676
bogdanm 92:4fc01daae5a5 1677 /** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source
bogdanm 86:04dd9b1680ae 1678 * @{
bogdanm 86:04dd9b1680ae 1679 */
bogdanm 86:04dd9b1680ae 1680 #define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI
bogdanm 86:04dd9b1680ae 1681 #define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK
bogdanm 86:04dd9b1680ae 1682
bogdanm 86:04dd9b1680ae 1683 /**
bogdanm 86:04dd9b1680ae 1684 * @}
bogdanm 86:04dd9b1680ae 1685 */
bogdanm 86:04dd9b1680ae 1686
bogdanm 92:4fc01daae5a5 1687 /** @defgroup RCCEx_ADC1_Clock_Source RCC Extended ADC1 Clock Source
bogdanm 86:04dd9b1680ae 1688 * @{
bogdanm 86:04dd9b1680ae 1689 */
bogdanm 86:04dd9b1680ae 1690
bogdanm 86:04dd9b1680ae 1691 /* ADC1 */
bogdanm 86:04dd9b1680ae 1692 #define RCC_ADC1PCLK2_DIV2 RCC_CFGR_ADCPRE_DIV2
bogdanm 86:04dd9b1680ae 1693 #define RCC_ADC1PCLK2_DIV4 RCC_CFGR_ADCPRE_DIV4
bogdanm 86:04dd9b1680ae 1694 #define RCC_ADC1PCLK2_DIV6 RCC_CFGR_ADCPRE_DIV6
bogdanm 86:04dd9b1680ae 1695 #define RCC_ADC1PCLK2_DIV8 RCC_CFGR_ADCPRE_DIV8
bogdanm 86:04dd9b1680ae 1696
bogdanm 86:04dd9b1680ae 1697 /**
bogdanm 86:04dd9b1680ae 1698 * @}
bogdanm 86:04dd9b1680ae 1699 */
bogdanm 86:04dd9b1680ae 1700
bogdanm 92:4fc01daae5a5 1701 /** @defgroup RCCEx_CEC_Clock_Source RCC Extended CEC Clock Source
bogdanm 86:04dd9b1680ae 1702 * @{
bogdanm 86:04dd9b1680ae 1703 */
bogdanm 86:04dd9b1680ae 1704 #define RCC_CECCLKSOURCE_HSI RCC_CFGR3_CECSW_HSI_DIV244
bogdanm 86:04dd9b1680ae 1705 #define RCC_CECCLKSOURCE_LSE RCC_CFGR3_CECSW_LSE
bogdanm 86:04dd9b1680ae 1706
bogdanm 86:04dd9b1680ae 1707 /**
bogdanm 86:04dd9b1680ae 1708 * @}
bogdanm 86:04dd9b1680ae 1709 */
bogdanm 86:04dd9b1680ae 1710
bogdanm 92:4fc01daae5a5 1711 /** @defgroup RCCEx_SDADC_Clock_Prescaler RCC Extended SDADC Clock Prescaler
bogdanm 86:04dd9b1680ae 1712 * @{
bogdanm 86:04dd9b1680ae 1713 */
bogdanm 86:04dd9b1680ae 1714 #define RCC_SDADCSYSCLK_DIV1 RCC_CFGR_SDADCPRE_DIV1
bogdanm 86:04dd9b1680ae 1715 #define RCC_SDADCSYSCLK_DIV2 RCC_CFGR_SDADCPRE_DIV2
bogdanm 86:04dd9b1680ae 1716 #define RCC_SDADCSYSCLK_DIV4 RCC_CFGR_SDADCPRE_DIV4
bogdanm 86:04dd9b1680ae 1717 #define RCC_SDADCSYSCLK_DIV6 RCC_CFGR_SDADCPRE_DIV6
bogdanm 86:04dd9b1680ae 1718 #define RCC_SDADCSYSCLK_DIV8 RCC_CFGR_SDADCPRE_DIV8
bogdanm 86:04dd9b1680ae 1719 #define RCC_SDADCSYSCLK_DIV10 RCC_CFGR_SDADCPRE_DIV10
bogdanm 86:04dd9b1680ae 1720 #define RCC_SDADCSYSCLK_DIV12 RCC_CFGR_SDADCPRE_DIV12
bogdanm 86:04dd9b1680ae 1721 #define RCC_SDADCSYSCLK_DIV14 RCC_CFGR_SDADCPRE_DIV14
bogdanm 86:04dd9b1680ae 1722 #define RCC_SDADCSYSCLK_DIV16 RCC_CFGR_SDADCPRE_DIV16
bogdanm 86:04dd9b1680ae 1723 #define RCC_SDADCSYSCLK_DIV20 RCC_CFGR_SDADCPRE_DIV20
bogdanm 86:04dd9b1680ae 1724 #define RCC_SDADCSYSCLK_DIV24 RCC_CFGR_SDADCPRE_DIV24
bogdanm 86:04dd9b1680ae 1725 #define RCC_SDADCSYSCLK_DIV28 RCC_CFGR_SDADCPRE_DIV28
bogdanm 86:04dd9b1680ae 1726 #define RCC_SDADCSYSCLK_DIV32 RCC_CFGR_SDADCPRE_DIV32
bogdanm 86:04dd9b1680ae 1727 #define RCC_SDADCSYSCLK_DIV36 RCC_CFGR_SDADCPRE_DIV36
bogdanm 86:04dd9b1680ae 1728 #define RCC_SDADCSYSCLK_DIV40 RCC_CFGR_SDADCPRE_DIV40
bogdanm 86:04dd9b1680ae 1729 #define RCC_SDADCSYSCLK_DIV44 RCC_CFGR_SDADCPRE_DIV44
bogdanm 86:04dd9b1680ae 1730 #define RCC_SDADCSYSCLK_DIV48 RCC_CFGR_SDADCPRE_DIV48
bogdanm 86:04dd9b1680ae 1731
bogdanm 86:04dd9b1680ae 1732 /**
bogdanm 86:04dd9b1680ae 1733 * @}
bogdanm 86:04dd9b1680ae 1734 */
bogdanm 86:04dd9b1680ae 1735
bogdanm 86:04dd9b1680ae 1736 #endif /* STM32F373xC || STM32F378xx */
bogdanm 86:04dd9b1680ae 1737
Kojto 122:f9eeca106725 1738 #if defined(STM32F302xE) || defined(STM32F303xE)\
Kojto 122:f9eeca106725 1739 || defined(STM32F302xC) || defined(STM32F303xC)\
Kojto 122:f9eeca106725 1740 || defined(STM32F302x8) \
Kojto 122:f9eeca106725 1741 || defined(STM32F373xC)
bogdanm 92:4fc01daae5a5 1742 /** @defgroup RCCEx_USB_Clock_Source RCC Extended USB Clock Source
bogdanm 86:04dd9b1680ae 1743 * @{
bogdanm 86:04dd9b1680ae 1744 */
Kojto 122:f9eeca106725 1745
Kojto 122:f9eeca106725 1746 #define RCC_USBCLKSOURCE_PLL RCC_CFGR_USBPRE_DIV1
Kojto 122:f9eeca106725 1747 #define RCC_USBCLKSOURCE_PLL_DIV1_5 RCC_CFGR_USBPRE_DIV1_5
Kojto 122:f9eeca106725 1748
bogdanm 86:04dd9b1680ae 1749 /**
bogdanm 86:04dd9b1680ae 1750 * @}
bogdanm 86:04dd9b1680ae 1751 */
bogdanm 86:04dd9b1680ae 1752
bogdanm 92:4fc01daae5a5 1753 #endif /* STM32F302xE || STM32F303xE || */
bogdanm 92:4fc01daae5a5 1754 /* STM32F302xC || STM32F303xC || */
bogdanm 92:4fc01daae5a5 1755 /* STM32F302x8 || */
bogdanm 92:4fc01daae5a5 1756 /* STM32F373xC */
bogdanm 86:04dd9b1680ae 1757
bogdanm 92:4fc01daae5a5 1758
bogdanm 92:4fc01daae5a5 1759 /** @defgroup RCCEx_MCOx_Clock_Prescaler RCC Extended MCOx Clock Prescaler
bogdanm 86:04dd9b1680ae 1760 * @{
bogdanm 86:04dd9b1680ae 1761 */
Kojto 122:f9eeca106725 1762 #if defined(RCC_CFGR_MCOPRE)
Kojto 122:f9eeca106725 1763
Kojto 122:f9eeca106725 1764 #define RCC_MCODIV_1 ((uint32_t)0x00000000)
Kojto 122:f9eeca106725 1765 #define RCC_MCODIV_2 ((uint32_t)0x10000000)
Kojto 122:f9eeca106725 1766 #define RCC_MCODIV_4 ((uint32_t)0x20000000)
Kojto 122:f9eeca106725 1767 #define RCC_MCODIV_8 ((uint32_t)0x30000000)
Kojto 122:f9eeca106725 1768 #define RCC_MCODIV_16 ((uint32_t)0x40000000)
Kojto 122:f9eeca106725 1769 #define RCC_MCODIV_32 ((uint32_t)0x50000000)
Kojto 122:f9eeca106725 1770 #define RCC_MCODIV_64 ((uint32_t)0x60000000)
Kojto 122:f9eeca106725 1771 #define RCC_MCODIV_128 ((uint32_t)0x70000000)
Kojto 122:f9eeca106725 1772
Kojto 122:f9eeca106725 1773 #else
Kojto 122:f9eeca106725 1774
Kojto 122:f9eeca106725 1775 #define RCC_MCODIV_1 ((uint32_t)0x00000000)
Kojto 122:f9eeca106725 1776
Kojto 122:f9eeca106725 1777 #endif /* RCC_CFGR_MCOPRE */
Kojto 122:f9eeca106725 1778
bogdanm 86:04dd9b1680ae 1779 /**
bogdanm 86:04dd9b1680ae 1780 * @}
bogdanm 86:04dd9b1680ae 1781 */
bogdanm 86:04dd9b1680ae 1782
Kojto 122:f9eeca106725 1783 /** @defgroup RCCEx_LSEDrive_Configuration RCC LSE Drive Configuration
Kojto 122:f9eeca106725 1784 * @{
Kojto 122:f9eeca106725 1785 */
Kojto 122:f9eeca106725 1786
Kojto 122:f9eeca106725 1787 #define RCC_LSEDRIVE_LOW ((uint32_t)0x00000000) /*!< Xtal mode lower driving capability */
Kojto 122:f9eeca106725 1788 #define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium low driving capability */
Kojto 122:f9eeca106725 1789 #define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium high driving capability */
Kojto 122:f9eeca106725 1790 #define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */
Kojto 122:f9eeca106725 1791
Kojto 122:f9eeca106725 1792 /**
Kojto 122:f9eeca106725 1793 * @}
Kojto 122:f9eeca106725 1794 */
bogdanm 86:04dd9b1680ae 1795
bogdanm 86:04dd9b1680ae 1796 /**
bogdanm 86:04dd9b1680ae 1797 * @}
bogdanm 86:04dd9b1680ae 1798 */
bogdanm 86:04dd9b1680ae 1799
bogdanm 86:04dd9b1680ae 1800 /* Exported macro ------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 1801 /** @defgroup RCCEx_Exported_Macros RCC Extended Exported Macros
bogdanm 92:4fc01daae5a5 1802 * @{
bogdanm 92:4fc01daae5a5 1803 */
bogdanm 92:4fc01daae5a5 1804
bogdanm 92:4fc01daae5a5 1805 /** @defgroup RCCEx_PLL_Configuration RCC Extended PLL Configuration
bogdanm 92:4fc01daae5a5 1806 * @{
bogdanm 92:4fc01daae5a5 1807 */
bogdanm 92:4fc01daae5a5 1808 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
bogdanm 92:4fc01daae5a5 1809 /** @brief Macro to configure the PLL clock source, multiplication and division factors.
bogdanm 92:4fc01daae5a5 1810 * @note This macro must be used only when the PLL is disabled.
bogdanm 92:4fc01daae5a5 1811 *
Kojto 122:f9eeca106725 1812 * @param __RCC_PLLSource__ specifies the PLL entry clock source.
bogdanm 92:4fc01daae5a5 1813 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 1814 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry
Kojto 122:f9eeca106725 1815 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
Kojto 122:f9eeca106725 1816 * @param __PREDIV__ specifies the predivider factor for PLL VCO input clock
bogdanm 92:4fc01daae5a5 1817 * This parameter must be a number between RCC_PREDIV_DIV1 and RCC_PREDIV_DIV16.
Kojto 122:f9eeca106725 1818 * @param __PLLMUL__ specifies the multiplication factor for PLL VCO input clock
bogdanm 92:4fc01daae5a5 1819 * This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16.
bogdanm 92:4fc01daae5a5 1820 *
bogdanm 92:4fc01daae5a5 1821 */
bogdanm 92:4fc01daae5a5 1822 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__ , __PREDIV__, __PLLMUL__) \
bogdanm 92:4fc01daae5a5 1823 do { \
bogdanm 92:4fc01daae5a5 1824 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (__PREDIV__)); \
bogdanm 92:4fc01daae5a5 1825 MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)|(__RCC_PLLSource__))); \
bogdanm 92:4fc01daae5a5 1826 } while(0)
bogdanm 92:4fc01daae5a5 1827 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
bogdanm 92:4fc01daae5a5 1828
Kojto 122:f9eeca106725 1829 #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
Kojto 122:f9eeca106725 1830 || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
Kojto 122:f9eeca106725 1831 || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)\
Kojto 122:f9eeca106725 1832 || defined(STM32F373xC) || defined(STM32F378xx)
bogdanm 92:4fc01daae5a5 1833 /** @brief Macro to configure the PLL clock source and multiplication factor.
bogdanm 92:4fc01daae5a5 1834 * @note This macro must be used only when the PLL is disabled.
bogdanm 92:4fc01daae5a5 1835 *
Kojto 122:f9eeca106725 1836 * @param __RCC_PLLSource__ specifies the PLL entry clock source.
bogdanm 92:4fc01daae5a5 1837 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 1838 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry
Kojto 122:f9eeca106725 1839 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
Kojto 122:f9eeca106725 1840 * @param __PLLMUL__ specifies the multiplication factor for PLL VCO input clock
bogdanm 92:4fc01daae5a5 1841 * This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16.
bogdanm 92:4fc01daae5a5 1842 *
bogdanm 92:4fc01daae5a5 1843 */
bogdanm 92:4fc01daae5a5 1844 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__ , __PLLMUL__) \
bogdanm 92:4fc01daae5a5 1845 MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)|(__RCC_PLLSource__)))
bogdanm 92:4fc01daae5a5 1846 #endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
bogdanm 92:4fc01daae5a5 1847 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
bogdanm 92:4fc01daae5a5 1848 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
bogdanm 92:4fc01daae5a5 1849 /* STM32F373xC || STM32F378xx */
bogdanm 92:4fc01daae5a5 1850 /**
bogdanm 92:4fc01daae5a5 1851 * @}
bogdanm 92:4fc01daae5a5 1852 */
bogdanm 92:4fc01daae5a5 1853
Kojto 122:f9eeca106725 1854 #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
Kojto 122:f9eeca106725 1855 || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
Kojto 122:f9eeca106725 1856 || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)\
Kojto 122:f9eeca106725 1857 || defined(STM32F373xC) || defined(STM32F378xx)
bogdanm 92:4fc01daae5a5 1858 /** @defgroup RCCEx_HSE_Configuration RCC Extended HSE Configuration
bogdanm 92:4fc01daae5a5 1859 * @{
bogdanm 92:4fc01daae5a5 1860 */
bogdanm 92:4fc01daae5a5 1861
bogdanm 92:4fc01daae5a5 1862 /**
bogdanm 92:4fc01daae5a5 1863 * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
bogdanm 92:4fc01daae5a5 1864 * @note Predivision factor can not be changed if PLL is used as system clock
bogdanm 92:4fc01daae5a5 1865 * In this case, you have to select another source of the system clock, disable the PLL and
bogdanm 92:4fc01daae5a5 1866 * then change the HSE predivision factor.
Kojto 122:f9eeca106725 1867 * @param __HSE_PREDIV_VALUE__ specifies the division value applied to HSE.
bogdanm 92:4fc01daae5a5 1868 * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16.
bogdanm 92:4fc01daae5a5 1869 */
Kojto 122:f9eeca106725 1870 #define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) \
Kojto 122:f9eeca106725 1871 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (uint32_t)(__HSE_PREDIV_VALUE__))
Kojto 122:f9eeca106725 1872
Kojto 122:f9eeca106725 1873 /**
Kojto 122:f9eeca106725 1874 * @brief Macro to get prediv1 factor for PLL.
Kojto 122:f9eeca106725 1875 */
Kojto 122:f9eeca106725 1876 #define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV)
Kojto 122:f9eeca106725 1877
bogdanm 92:4fc01daae5a5 1878 /**
bogdanm 92:4fc01daae5a5 1879 * @}
bogdanm 92:4fc01daae5a5 1880 */
bogdanm 92:4fc01daae5a5 1881 #endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
bogdanm 92:4fc01daae5a5 1882 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
bogdanm 92:4fc01daae5a5 1883 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
bogdanm 92:4fc01daae5a5 1884 /* STM32F373xC || STM32F378xx */
bogdanm 92:4fc01daae5a5 1885
bogdanm 92:4fc01daae5a5 1886 /** @defgroup RCCEx_AHB_Clock_Enable_Disable RCC Extended AHB Clock Enable Disable
bogdanm 92:4fc01daae5a5 1887 * @brief Enable or disable the AHB peripheral clock.
bogdanm 86:04dd9b1680ae 1888 * @note After reset, the peripheral clock (used for registers read/write access)
bogdanm 86:04dd9b1680ae 1889 * is disabled and the application software has to enable this clock before
bogdanm 86:04dd9b1680ae 1890 * using it.
bogdanm 92:4fc01daae5a5 1891 * @{
bogdanm 86:04dd9b1680ae 1892 */
bogdanm 86:04dd9b1680ae 1893 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
Kojto 122:f9eeca106725 1894 #define __HAL_RCC_ADC1_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1895 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1896 SET_BIT(RCC->AHBENR, RCC_AHBENR_ADC1EN);\
Kojto 122:f9eeca106725 1897 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1898 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ADC1EN);\
Kojto 122:f9eeca106725 1899 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1900 } while(0)
Kojto 122:f9eeca106725 1901
Kojto 122:f9eeca106725 1902 #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC1EN))
bogdanm 86:04dd9b1680ae 1903 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
bogdanm 86:04dd9b1680ae 1904
Kojto 122:f9eeca106725 1905 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
Kojto 122:f9eeca106725 1906 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
Kojto 122:f9eeca106725 1907 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1908 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1909 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
Kojto 122:f9eeca106725 1910 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1911 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
Kojto 122:f9eeca106725 1912 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1913 } while(0)
Kojto 122:f9eeca106725 1914 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1915 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1916 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
Kojto 122:f9eeca106725 1917 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1918 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
Kojto 122:f9eeca106725 1919 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1920 } while(0)
Kojto 122:f9eeca106725 1921 #define __HAL_RCC_ADC12_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1922 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1923 SET_BIT(RCC->AHBENR, RCC_AHBENR_ADC12EN);\
Kojto 122:f9eeca106725 1924 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1925 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ADC12EN);\
Kojto 122:f9eeca106725 1926 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1927 } while(0)
bogdanm 86:04dd9b1680ae 1928 /* Aliases for STM32 F3 compatibility */
Kojto 122:f9eeca106725 1929 #define __HAL_RCC_ADC1_CLK_ENABLE() __HAL_RCC_ADC12_CLK_ENABLE()
Kojto 122:f9eeca106725 1930 #define __HAL_RCC_ADC2_CLK_ENABLE() __HAL_RCC_ADC12_CLK_ENABLE()
Kojto 122:f9eeca106725 1931
Kojto 122:f9eeca106725 1932 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
Kojto 122:f9eeca106725 1933 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
Kojto 122:f9eeca106725 1934 #define __HAL_RCC_ADC12_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC12EN))
bogdanm 86:04dd9b1680ae 1935 /* Aliases for STM32 F3 compatibility */
Kojto 122:f9eeca106725 1936 #define __HAL_RCC_ADC1_CLK_DISABLE() __HAL_RCC_ADC12_CLK_DISABLE()
Kojto 122:f9eeca106725 1937 #define __HAL_RCC_ADC2_CLK_DISABLE() __HAL_RCC_ADC12_CLK_DISABLE()
bogdanm 92:4fc01daae5a5 1938 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
bogdanm 92:4fc01daae5a5 1939 /* STM32F302xC || STM32F303xC || STM32F358xx */
bogdanm 92:4fc01daae5a5 1940
Kojto 122:f9eeca106725 1941 #if defined(STM32F303xE) || defined(STM32F398xx)\
Kojto 122:f9eeca106725 1942 || defined(STM32F303xC) || defined(STM32F358xx)
Kojto 122:f9eeca106725 1943 #define __HAL_RCC_ADC34_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1944 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1945 SET_BIT(RCC->AHBENR, RCC_AHBENR_ADC34EN);\
Kojto 122:f9eeca106725 1946 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1947 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ADC34EN);\
Kojto 122:f9eeca106725 1948 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1949 } while(0)
Kojto 122:f9eeca106725 1950 #define __HAL_RCC_ADC34_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC34EN))
bogdanm 92:4fc01daae5a5 1951 #endif /* STM32F303xE || STM32F398xx || */
bogdanm 92:4fc01daae5a5 1952 /* STM32F303xC || STM32F358xx */
bogdanm 86:04dd9b1680ae 1953
bogdanm 86:04dd9b1680ae 1954 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
Kojto 122:f9eeca106725 1955 #define __HAL_RCC_ADC12_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1956 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1957 SET_BIT(RCC->AHBENR, RCC_AHBENR_ADC12EN);\
Kojto 122:f9eeca106725 1958 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1959 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ADC12EN);\
Kojto 122:f9eeca106725 1960 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1961 } while(0)
bogdanm 86:04dd9b1680ae 1962 /* Aliases for STM32 F3 compatibility */
Kojto 122:f9eeca106725 1963 #define __HAL_RCC_ADC1_CLK_ENABLE() __HAL_RCC_ADC12_CLK_ENABLE()
Kojto 122:f9eeca106725 1964 #define __HAL_RCC_ADC2_CLK_ENABLE() __HAL_RCC_ADC12_CLK_ENABLE()
Kojto 122:f9eeca106725 1965
Kojto 122:f9eeca106725 1966 #define __HAL_RCC_ADC12_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC12EN))
bogdanm 86:04dd9b1680ae 1967 /* Aliases for STM32 F3 compatibility */
Kojto 122:f9eeca106725 1968 #define __HAL_RCC_ADC1_CLK_DISABLE() __HAL_RCC_ADC12_CLK_DISABLE()
Kojto 122:f9eeca106725 1969 #define __HAL_RCC_ADC2_CLK_DISABLE() __HAL_RCC_ADC12_CLK_DISABLE()
bogdanm 86:04dd9b1680ae 1970 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
bogdanm 86:04dd9b1680ae 1971
bogdanm 86:04dd9b1680ae 1972 #if defined(STM32F373xC) || defined(STM32F378xx)
Kojto 122:f9eeca106725 1973 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1974 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1975 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
Kojto 122:f9eeca106725 1976 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1977 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
Kojto 122:f9eeca106725 1978 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1979 } while(0)
Kojto 122:f9eeca106725 1980 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1981 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1982 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
Kojto 122:f9eeca106725 1983 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1984 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
Kojto 122:f9eeca106725 1985 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1986 } while(0)
Kojto 122:f9eeca106725 1987
Kojto 122:f9eeca106725 1988 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
Kojto 122:f9eeca106725 1989 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
bogdanm 86:04dd9b1680ae 1990 #endif /* STM32F373xC || STM32F378xx */
bogdanm 86:04dd9b1680ae 1991
bogdanm 92:4fc01daae5a5 1992 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
Kojto 122:f9eeca106725 1993 #define __HAL_RCC_FMC_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1994 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1995 SET_BIT(RCC->AHBENR, RCC_AHBENR_FMCEN);\
Kojto 122:f9eeca106725 1996 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1997 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FMCEN);\
Kojto 122:f9eeca106725 1998 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1999 } while(0)
Kojto 122:f9eeca106725 2000 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 2001 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 2002 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOGEN);\
Kojto 122:f9eeca106725 2003 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 2004 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOGEN);\
Kojto 122:f9eeca106725 2005 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 2006 } while(0)
Kojto 122:f9eeca106725 2007 #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 2008 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 2009 SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOHEN);\
Kojto 122:f9eeca106725 2010 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 2011 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOHEN);\
Kojto 122:f9eeca106725 2012 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 2013 } while(0)
Kojto 122:f9eeca106725 2014
Kojto 122:f9eeca106725 2015 #define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FMCEN))
Kojto 122:f9eeca106725 2016 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOGEN))
Kojto 122:f9eeca106725 2017 #define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOHEN))
bogdanm 92:4fc01daae5a5 2018 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
bogdanm 92:4fc01daae5a5 2019 /**
bogdanm 92:4fc01daae5a5 2020 * @}
bogdanm 92:4fc01daae5a5 2021 */
bogdanm 92:4fc01daae5a5 2022
bogdanm 92:4fc01daae5a5 2023 /** @defgroup RCCEx_APB1_Clock_Enable_Disable RCC Extended APB1 Clock Enable Disable
bogdanm 92:4fc01daae5a5 2024 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
bogdanm 86:04dd9b1680ae 2025 * @note After reset, the peripheral clock (used for registers read/write access)
bogdanm 86:04dd9b1680ae 2026 * is disabled and the application software has to enable this clock before
bogdanm 86:04dd9b1680ae 2027 * using it.
bogdanm 92:4fc01daae5a5 2028 * @{
bogdanm 86:04dd9b1680ae 2029 */
bogdanm 86:04dd9b1680ae 2030 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
Kojto 122:f9eeca106725 2031 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 2032 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 2033 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
Kojto 122:f9eeca106725 2034 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 2035 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
Kojto 122:f9eeca106725 2036 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 2037 } while(0)
Kojto 122:f9eeca106725 2038 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 2039 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 2040 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
Kojto 122:f9eeca106725 2041 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 2042 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
Kojto 122:f9eeca106725 2043 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 2044 } while(0)
Kojto 122:f9eeca106725 2045 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 2046 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 2047 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
Kojto 122:f9eeca106725 2048 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 2049 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
Kojto 122:f9eeca106725 2050 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 2051 } while(0)
Kojto 122:f9eeca106725 2052 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 2053 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 2054 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
Kojto 122:f9eeca106725 2055 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 2056 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
Kojto 122:f9eeca106725 2057 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 2058 } while(0)
Kojto 122:f9eeca106725 2059
Kojto 122:f9eeca106725 2060 #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
Kojto 122:f9eeca106725 2061 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
Kojto 122:f9eeca106725 2062 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
Kojto 122:f9eeca106725 2063 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
bogdanm 86:04dd9b1680ae 2064 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
bogdanm 86:04dd9b1680ae 2065
Kojto 122:f9eeca106725 2066 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
Kojto 122:f9eeca106725 2067 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
Kojto 122:f9eeca106725 2068 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 2069 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 2070 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
Kojto 122:f9eeca106725 2071 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 2072 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
Kojto 122:f9eeca106725 2073 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 2074 } while(0)
Kojto 122:f9eeca106725 2075 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 2076 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 2077 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
Kojto 122:f9eeca106725 2078 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 2079 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
Kojto 122:f9eeca106725 2080 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 2081 } while(0)
Kojto 122:f9eeca106725 2082 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 2083 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 2084 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
Kojto 122:f9eeca106725 2085 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 2086 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
Kojto 122:f9eeca106725 2087 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 2088 } while(0)
Kojto 122:f9eeca106725 2089 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 2090 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 2091 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
Kojto 122:f9eeca106725 2092 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 2093 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
Kojto 122:f9eeca106725 2094 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 2095 } while(0)
Kojto 122:f9eeca106725 2096 #define __HAL_RCC_UART4_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 2097 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 2098 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
Kojto 122:f9eeca106725 2099 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 2100 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
Kojto 122:f9eeca106725 2101 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 2102 } while(0)
Kojto 122:f9eeca106725 2103 #define __HAL_RCC_UART5_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 2104 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 2105 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
Kojto 122:f9eeca106725 2106 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 2107 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
Kojto 122:f9eeca106725 2108 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 2109 } while(0)
Kojto 122:f9eeca106725 2110 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 2111 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 2112 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
Kojto 122:f9eeca106725 2113 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 2114 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
Kojto 122:f9eeca106725 2115 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 2116 } while(0)
Kojto 122:f9eeca106725 2117
Kojto 122:f9eeca106725 2118 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
Kojto 122:f9eeca106725 2119 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
Kojto 122:f9eeca106725 2120 #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
Kojto 122:f9eeca106725 2121 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
Kojto 122:f9eeca106725 2122 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
Kojto 122:f9eeca106725 2123 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
Kojto 122:f9eeca106725 2124 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
bogdanm 92:4fc01daae5a5 2125 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
bogdanm 92:4fc01daae5a5 2126 /* STM32F302xC || STM32F303xC || STM32F358xx */
bogdanm 86:04dd9b1680ae 2127
bogdanm 86:04dd9b1680ae 2128 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
Kojto 122:f9eeca106725 2129 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 2130 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 2131 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
Kojto 122:f9eeca106725 2132 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 2133 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
Kojto 122:f9eeca106725 2134 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 2135 } while(0)
Kojto 122:f9eeca106725 2136 #define __HAL_RCC_DAC2_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 2137 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 2138 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC2EN);\
Kojto 122:f9eeca106725 2139 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 2140 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC2EN);\
Kojto 122:f9eeca106725 2141 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 2142 } while(0)
Kojto 122:f9eeca106725 2143
Kojto 122:f9eeca106725 2144 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
Kojto 122:f9eeca106725 2145 #define __HAL_RCC_DAC2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC2EN))
bogdanm 86:04dd9b1680ae 2146 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
bogdanm 86:04dd9b1680ae 2147
bogdanm 86:04dd9b1680ae 2148 #if defined(STM32F373xC) || defined(STM32F378xx)
Kojto 122:f9eeca106725 2149 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 2150 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 2151 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
Kojto 122:f9eeca106725 2152 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 2153 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
Kojto 122:f9eeca106725 2154 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 2155 } while(0)
Kojto 122:f9eeca106725 2156 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 2157 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 2158 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
Kojto 122:f9eeca106725 2159 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 2160 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
Kojto 122:f9eeca106725 2161 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 2162 } while(0)
Kojto 122:f9eeca106725 2163 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 2164 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 2165 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
Kojto 122:f9eeca106725 2166 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 2167 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
Kojto 122:f9eeca106725 2168 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 2169 } while(0)
Kojto 122:f9eeca106725 2170 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 2171 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 2172 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
Kojto 122:f9eeca106725 2173 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 2174 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
Kojto 122:f9eeca106725 2175 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 2176 } while(0)
Kojto 122:f9eeca106725 2177 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 2178 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 2179 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
Kojto 122:f9eeca106725 2180 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 2181 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
Kojto 122:f9eeca106725 2182 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 2183 } while(0)
Kojto 122:f9eeca106725 2184 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 2185 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 2186 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto 122:f9eeca106725 2187 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 2188 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto 122:f9eeca106725 2189 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 2190 } while(0)
Kojto 122:f9eeca106725 2191 #define __HAL_RCC_TIM18_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 2192 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 2193 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM18EN);\
Kojto 122:f9eeca106725 2194 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 2195 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM18EN);\
Kojto 122:f9eeca106725 2196 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 2197 } while(0)
Kojto 122:f9eeca106725 2198 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 2199 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 2200 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
Kojto 122:f9eeca106725 2201 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 2202 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
Kojto 122:f9eeca106725 2203 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 2204 } while(0)
Kojto 122:f9eeca106725 2205 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 2206 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 2207 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
Kojto 122:f9eeca106725 2208 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 2209 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
Kojto 122:f9eeca106725 2210 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 2211 } while(0)
Kojto 122:f9eeca106725 2212 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 2213 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 2214 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
Kojto 122:f9eeca106725 2215 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 2216 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
Kojto 122:f9eeca106725 2217 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 2218 } while(0)
Kojto 122:f9eeca106725 2219 #define __HAL_RCC_DAC2_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 2220 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 2221 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC2EN);\
Kojto 122:f9eeca106725 2222 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 2223 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DAC2EN);\
Kojto 122:f9eeca106725 2224 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 2225 } while(0)
Kojto 122:f9eeca106725 2226 #define __HAL_RCC_CEC_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 2227 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 2228 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
Kojto 122:f9eeca106725 2229 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 2230 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
Kojto 122:f9eeca106725 2231 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 2232 } while(0)
Kojto 122:f9eeca106725 2233
Kojto 122:f9eeca106725 2234 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
Kojto 122:f9eeca106725 2235 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
Kojto 122:f9eeca106725 2236 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
Kojto 122:f9eeca106725 2237 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
Kojto 122:f9eeca106725 2238 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
Kojto 122:f9eeca106725 2239 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
Kojto 122:f9eeca106725 2240 #define __HAL_RCC_TIM18_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM18EN))
Kojto 122:f9eeca106725 2241 #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
Kojto 122:f9eeca106725 2242 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
Kojto 122:f9eeca106725 2243 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
Kojto 122:f9eeca106725 2244 #define __HAL_RCC_DAC2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC2EN))
Kojto 122:f9eeca106725 2245 #define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
bogdanm 86:04dd9b1680ae 2246 #endif /* STM32F373xC || STM32F378xx */
bogdanm 86:04dd9b1680ae 2247
Kojto 122:f9eeca106725 2248 #if defined(STM32F303xE) || defined(STM32F398xx) \
Kojto 122:f9eeca106725 2249 || defined(STM32F303xC) || defined(STM32F358xx) \
Kojto 122:f9eeca106725 2250 || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
Kojto 122:f9eeca106725 2251 || defined(STM32F373xC) || defined(STM32F378xx)
Kojto 122:f9eeca106725 2252 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 2253 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 2254 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
Kojto 122:f9eeca106725 2255 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 2256 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
Kojto 122:f9eeca106725 2257 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 2258 } while(0)
Kojto 122:f9eeca106725 2259
Kojto 122:f9eeca106725 2260 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
bogdanm 92:4fc01daae5a5 2261 #endif /* STM32F303xE || STM32F398xx || */
bogdanm 92:4fc01daae5a5 2262 /* STM32F303xC || STM32F358xx || */
bogdanm 92:4fc01daae5a5 2263 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
bogdanm 92:4fc01daae5a5 2264 /* STM32F373xC || STM32F378xx */
bogdanm 92:4fc01daae5a5 2265
Kojto 122:f9eeca106725 2266 #if defined(STM32F302xE) || defined(STM32F303xE)\
Kojto 122:f9eeca106725 2267 || defined(STM32F302xC) || defined(STM32F303xC)\
Kojto 122:f9eeca106725 2268 || defined(STM32F302x8) \
Kojto 122:f9eeca106725 2269 || defined(STM32F373xC)
Kojto 122:f9eeca106725 2270 #define __HAL_RCC_USB_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 2271 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 2272 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
Kojto 122:f9eeca106725 2273 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 2274 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
Kojto 122:f9eeca106725 2275 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 2276 } while(0)
Kojto 122:f9eeca106725 2277
Kojto 122:f9eeca106725 2278 #define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
bogdanm 92:4fc01daae5a5 2279 #endif /* STM32F302xE || STM32F303xE || */
bogdanm 92:4fc01daae5a5 2280 /* STM32F302xC || STM32F303xC || */
bogdanm 92:4fc01daae5a5 2281 /* STM32F302x8 || */
bogdanm 92:4fc01daae5a5 2282 /* STM32F373xC */
bogdanm 86:04dd9b1680ae 2283
bogdanm 86:04dd9b1680ae 2284 #if !defined(STM32F301x8)
Kojto 122:f9eeca106725 2285 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 2286 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 2287 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\
Kojto 122:f9eeca106725 2288 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 2289 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\
Kojto 122:f9eeca106725 2290 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 2291 } while(0)
Kojto 122:f9eeca106725 2292
Kojto 122:f9eeca106725 2293 #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CANEN))
bogdanm 86:04dd9b1680ae 2294 #endif /* STM32F301x8*/
bogdanm 86:04dd9b1680ae 2295
bogdanm 92:4fc01daae5a5 2296 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
Kojto 122:f9eeca106725 2297 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 2298 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 2299 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
Kojto 122:f9eeca106725 2300 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 2301 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
Kojto 122:f9eeca106725 2302 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 2303 } while(0)
Kojto 122:f9eeca106725 2304
Kojto 122:f9eeca106725 2305 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
bogdanm 92:4fc01daae5a5 2306 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
bogdanm 92:4fc01daae5a5 2307 /**
bogdanm 92:4fc01daae5a5 2308 * @}
bogdanm 92:4fc01daae5a5 2309 */
bogdanm 92:4fc01daae5a5 2310
bogdanm 92:4fc01daae5a5 2311 /** @defgroup RCCEx_APB2_Clock_Enable_Disable RCC Extended APB2 Clock Enable Disable
bogdanm 92:4fc01daae5a5 2312 * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
bogdanm 86:04dd9b1680ae 2313 * @note After reset, the peripheral clock (used for registers read/write access)
bogdanm 86:04dd9b1680ae 2314 * is disabled and the application software has to enable this clock before
bogdanm 86:04dd9b1680ae 2315 * using it.
bogdanm 92:4fc01daae5a5 2316 * @{
bogdanm 86:04dd9b1680ae 2317 */
Kojto 122:f9eeca106725 2318 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
Kojto 122:f9eeca106725 2319 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
Kojto 122:f9eeca106725 2320 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 2321 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 2322 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
Kojto 122:f9eeca106725 2323 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 2324 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
Kojto 122:f9eeca106725 2325 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 2326 } while(0)
Kojto 122:f9eeca106725 2327
Kojto 122:f9eeca106725 2328 #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
bogdanm 92:4fc01daae5a5 2329 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
bogdanm 92:4fc01daae5a5 2330 /* STM32F302xC || STM32F303xC || STM32F358xx */
bogdanm 92:4fc01daae5a5 2331
Kojto 122:f9eeca106725 2332 #if defined(STM32F303xE) || defined(STM32F398xx)\
Kojto 122:f9eeca106725 2333 || defined(STM32F303xC) || defined(STM32F358xx)
Kojto 122:f9eeca106725 2334 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 2335 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 2336 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
Kojto 122:f9eeca106725 2337 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 2338 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
Kojto 122:f9eeca106725 2339 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 2340 } while(0)
Kojto 122:f9eeca106725 2341
Kojto 122:f9eeca106725 2342 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
bogdanm 92:4fc01daae5a5 2343 #endif /* STM32F303xE || STM32F398xx || */
bogdanm 92:4fc01daae5a5 2344 /* STM32F303xC || STM32F358xx */
bogdanm 86:04dd9b1680ae 2345
bogdanm 86:04dd9b1680ae 2346 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
Kojto 122:f9eeca106725 2347 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 2348 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 2349 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
Kojto 122:f9eeca106725 2350 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 2351 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
Kojto 122:f9eeca106725 2352 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 2353 } while(0)
Kojto 122:f9eeca106725 2354
Kojto 122:f9eeca106725 2355 #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
bogdanm 86:04dd9b1680ae 2356 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
bogdanm 86:04dd9b1680ae 2357
bogdanm 86:04dd9b1680ae 2358 #if defined(STM32F334x8)
Kojto 122:f9eeca106725 2359 #define __HAL_RCC_HRTIM1_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 2360 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 2361 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN);\
Kojto 122:f9eeca106725 2362 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 2363 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN);\
Kojto 122:f9eeca106725 2364 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 2365 } while(0)
Kojto 122:f9eeca106725 2366
Kojto 122:f9eeca106725 2367 #define __HAL_RCC_HRTIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_HRTIM1EN))
bogdanm 86:04dd9b1680ae 2368 #endif /* STM32F334x8 */
bogdanm 86:04dd9b1680ae 2369
bogdanm 86:04dd9b1680ae 2370 #if defined(STM32F373xC) || defined(STM32F378xx)
Kojto 122:f9eeca106725 2371 #define __HAL_RCC_ADC1_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 2372 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 2373 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
Kojto 122:f9eeca106725 2374 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 2375 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
Kojto 122:f9eeca106725 2376 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 2377 } while(0)
Kojto 122:f9eeca106725 2378 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 2379 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 2380 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
Kojto 122:f9eeca106725 2381 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 2382 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
Kojto 122:f9eeca106725 2383 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 2384 } while(0)
Kojto 122:f9eeca106725 2385 #define __HAL_RCC_TIM19_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 2386 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 2387 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM19EN);\
Kojto 122:f9eeca106725 2388 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 2389 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM19EN);\
Kojto 122:f9eeca106725 2390 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 2391 } while(0)
Kojto 122:f9eeca106725 2392 #define __HAL_RCC_SDADC1_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 2393 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 2394 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC1EN);\
Kojto 122:f9eeca106725 2395 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 2396 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC1EN);\
Kojto 122:f9eeca106725 2397 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 2398 } while(0)
Kojto 122:f9eeca106725 2399 #define __HAL_RCC_SDADC2_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 2400 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 2401 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC2EN);\
Kojto 122:f9eeca106725 2402 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 2403 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC2EN);\
Kojto 122:f9eeca106725 2404 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 2405 } while(0)
Kojto 122:f9eeca106725 2406 #define __HAL_RCC_SDADC3_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 2407 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 2408 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC3EN);\
Kojto 122:f9eeca106725 2409 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 2410 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDADC3EN);\
Kojto 122:f9eeca106725 2411 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 2412 } while(0)
Kojto 122:f9eeca106725 2413
Kojto 122:f9eeca106725 2414 #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
Kojto 122:f9eeca106725 2415 #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
Kojto 122:f9eeca106725 2416 #define __HAL_RCC_TIM19_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM19EN))
Kojto 122:f9eeca106725 2417 #define __HAL_RCC_SDADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC1EN))
Kojto 122:f9eeca106725 2418 #define __HAL_RCC_SDADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC2EN))
Kojto 122:f9eeca106725 2419 #define __HAL_RCC_SDADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC3EN))
bogdanm 86:04dd9b1680ae 2420 #endif /* STM32F373xC || STM32F378xx */
bogdanm 86:04dd9b1680ae 2421
Kojto 122:f9eeca106725 2422 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
Kojto 122:f9eeca106725 2423 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
Kojto 122:f9eeca106725 2424 || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
Kojto 122:f9eeca106725 2425 || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
Kojto 122:f9eeca106725 2426 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 2427 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 2428 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
Kojto 122:f9eeca106725 2429 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 2430 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
Kojto 122:f9eeca106725 2431 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 2432 } while(0)
Kojto 122:f9eeca106725 2433
Kojto 122:f9eeca106725 2434 #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
bogdanm 92:4fc01daae5a5 2435 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
bogdanm 86:04dd9b1680ae 2436 /* STM32F302xC || STM32F303xC || STM32F358xx || */
bogdanm 92:4fc01daae5a5 2437 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
bogdanm 92:4fc01daae5a5 2438 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
bogdanm 92:4fc01daae5a5 2439
bogdanm 92:4fc01daae5a5 2440 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
Kojto 122:f9eeca106725 2441 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 2442 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 2443 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
Kojto 122:f9eeca106725 2444 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 2445 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
Kojto 122:f9eeca106725 2446 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 2447 } while(0)
Kojto 122:f9eeca106725 2448
Kojto 122:f9eeca106725 2449 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
bogdanm 92:4fc01daae5a5 2450 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
bogdanm 92:4fc01daae5a5 2451
bogdanm 92:4fc01daae5a5 2452 #if defined(STM32F303xE) || defined(STM32F398xx)
Kojto 122:f9eeca106725 2453 #define __HAL_RCC_TIM20_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 2454 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 2455 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN);\
Kojto 122:f9eeca106725 2456 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 2457 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN);\
Kojto 122:f9eeca106725 2458 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 2459 } while(0)
Kojto 122:f9eeca106725 2460 #define __HAL_RCC_TIM20_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM20EN))
bogdanm 92:4fc01daae5a5 2461 #endif /* STM32F303xE || STM32F398xx */
bogdanm 92:4fc01daae5a5 2462
bogdanm 92:4fc01daae5a5 2463 /**
bogdanm 92:4fc01daae5a5 2464 * @}
bogdanm 92:4fc01daae5a5 2465 */
Kojto 122:f9eeca106725 2466
Kojto 122:f9eeca106725 2467 /** @defgroup RCCEx_AHB_Peripheral_Clock_Enable_Disable_Status RCC Extended AHB Peripheral Clock Enable Disable Status
Kojto 122:f9eeca106725 2468 * @brief Get the enable or disable status of the AHB peripheral clock.
Kojto 122:f9eeca106725 2469 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 122:f9eeca106725 2470 * is disabled and the application software has to enable this clock before
Kojto 122:f9eeca106725 2471 * using it.
Kojto 122:f9eeca106725 2472 * @{
Kojto 122:f9eeca106725 2473 */
Kojto 122:f9eeca106725 2474 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
Kojto 122:f9eeca106725 2475 #define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC1EN)) != RESET)
Kojto 122:f9eeca106725 2476
Kojto 122:f9eeca106725 2477 #define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC1EN)) == RESET)
Kojto 122:f9eeca106725 2478 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
Kojto 122:f9eeca106725 2479
Kojto 122:f9eeca106725 2480 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
Kojto 122:f9eeca106725 2481 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
Kojto 122:f9eeca106725 2482 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET)
Kojto 122:f9eeca106725 2483 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) != RESET)
Kojto 122:f9eeca106725 2484 #define __HAL_RCC_ADC12_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC12EN)) != RESET)
Kojto 122:f9eeca106725 2485
Kojto 122:f9eeca106725 2486 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET)
Kojto 122:f9eeca106725 2487 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) == RESET)
Kojto 122:f9eeca106725 2488 #define __HAL_RCC_ADC12_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC12EN)) == RESET)
Kojto 122:f9eeca106725 2489 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
Kojto 122:f9eeca106725 2490 /* STM32F302xC || STM32F303xC || STM32F358xx */
Kojto 122:f9eeca106725 2491
Kojto 122:f9eeca106725 2492 #if defined(STM32F303xE) || defined(STM32F398xx)\
Kojto 122:f9eeca106725 2493 || defined(STM32F303xC) || defined(STM32F358xx)
Kojto 122:f9eeca106725 2494 #define __HAL_RCC_ADC34_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC34EN)) != RESET)
Kojto 122:f9eeca106725 2495
Kojto 122:f9eeca106725 2496 #define __HAL_RCC_ADC34_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC34EN)) == RESET)
Kojto 122:f9eeca106725 2497 #endif /* STM32F303xE || STM32F398xx || */
Kojto 122:f9eeca106725 2498 /* STM32F303xC || STM32F358xx */
Kojto 122:f9eeca106725 2499
Kojto 122:f9eeca106725 2500 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
Kojto 122:f9eeca106725 2501 #define __HAL_RCC_ADC12_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC12EN)) != RESET)
Kojto 122:f9eeca106725 2502
Kojto 122:f9eeca106725 2503 #define __HAL_RCC_ADC12_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ADC12EN)) == RESET)
Kojto 122:f9eeca106725 2504 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
Kojto 122:f9eeca106725 2505
Kojto 122:f9eeca106725 2506 #if defined(STM32F373xC) || defined(STM32F378xx)
Kojto 122:f9eeca106725 2507 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET)
Kojto 122:f9eeca106725 2508 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) != RESET)
Kojto 122:f9eeca106725 2509
Kojto 122:f9eeca106725 2510 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET)
Kojto 122:f9eeca106725 2511 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) == RESET)
Kojto 122:f9eeca106725 2512 #endif /* STM32F373xC || STM32F378xx */
Kojto 122:f9eeca106725 2513
Kojto 122:f9eeca106725 2514 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
Kojto 122:f9eeca106725 2515 #define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FMCEN)) != RESET)
Kojto 122:f9eeca106725 2516 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOGEN)) != RESET)
Kojto 122:f9eeca106725 2517 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOHEN)) != RESET)
Kojto 122:f9eeca106725 2518
Kojto 122:f9eeca106725 2519 #define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FMCEN)) == RESET)
Kojto 122:f9eeca106725 2520 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOGEN)) == RESET)
Kojto 122:f9eeca106725 2521 #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOHEN)) == RESET)
Kojto 122:f9eeca106725 2522 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
Kojto 122:f9eeca106725 2523 /**
Kojto 122:f9eeca106725 2524 * @}
Kojto 122:f9eeca106725 2525 */
Kojto 122:f9eeca106725 2526
Kojto 122:f9eeca106725 2527 /** @defgroup RCCEx_APB1_Clock_Enable_Disable_Status RCC Extended APB1 Peripheral Clock Enable Disable Status
Kojto 122:f9eeca106725 2528 * @brief Get the enable or disable status of the APB1 peripheral clock.
Kojto 122:f9eeca106725 2529 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 122:f9eeca106725 2530 * is disabled and the application software has to enable this clock before
Kojto 122:f9eeca106725 2531 * using it.
Kojto 122:f9eeca106725 2532 * @{
Kojto 122:f9eeca106725 2533 */
Kojto 122:f9eeca106725 2534 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
Kojto 122:f9eeca106725 2535 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
Kojto 122:f9eeca106725 2536 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
Kojto 122:f9eeca106725 2537 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
Kojto 122:f9eeca106725 2538 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
Kojto 122:f9eeca106725 2539
Kojto 122:f9eeca106725 2540 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
Kojto 122:f9eeca106725 2541 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
Kojto 122:f9eeca106725 2542 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
Kojto 122:f9eeca106725 2543 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
Kojto 122:f9eeca106725 2544 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
Kojto 122:f9eeca106725 2545
Kojto 122:f9eeca106725 2546 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
Kojto 122:f9eeca106725 2547 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
Kojto 122:f9eeca106725 2548 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
Kojto 122:f9eeca106725 2549 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
Kojto 122:f9eeca106725 2550 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
Kojto 122:f9eeca106725 2551 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
Kojto 122:f9eeca106725 2552 #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
Kojto 122:f9eeca106725 2553 #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
Kojto 122:f9eeca106725 2554 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
Kojto 122:f9eeca106725 2555
Kojto 122:f9eeca106725 2556 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
Kojto 122:f9eeca106725 2557 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
Kojto 122:f9eeca106725 2558 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
Kojto 122:f9eeca106725 2559 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
Kojto 122:f9eeca106725 2560 #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
Kojto 122:f9eeca106725 2561 #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
Kojto 122:f9eeca106725 2562 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
Kojto 122:f9eeca106725 2563 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
Kojto 122:f9eeca106725 2564 /* STM32F302xC || STM32F303xC || STM32F358xx */
Kojto 122:f9eeca106725 2565
Kojto 122:f9eeca106725 2566 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
Kojto 122:f9eeca106725 2567 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
Kojto 122:f9eeca106725 2568 #define __HAL_RCC_DAC2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC2EN)) != RESET)
Kojto 122:f9eeca106725 2569
Kojto 122:f9eeca106725 2570 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
Kojto 122:f9eeca106725 2571 #define __HAL_RCC_DAC2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC2EN)) == RESET)
Kojto 122:f9eeca106725 2572 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
Kojto 122:f9eeca106725 2573
Kojto 122:f9eeca106725 2574 #if defined(STM32F373xC) || defined(STM32F378xx)
Kojto 122:f9eeca106725 2575 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
Kojto 122:f9eeca106725 2576 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
Kojto 122:f9eeca106725 2577 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
Kojto 122:f9eeca106725 2578 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
Kojto 122:f9eeca106725 2579 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
Kojto 122:f9eeca106725 2580 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
Kojto 122:f9eeca106725 2581 #define __HAL_RCC_TIM18_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM18EN)) != RESET)
Kojto 122:f9eeca106725 2582 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
Kojto 122:f9eeca106725 2583 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
Kojto 122:f9eeca106725 2584 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
Kojto 122:f9eeca106725 2585 #define __HAL_RCC_DAC2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC2EN)) != RESET)
Kojto 122:f9eeca106725 2586 #define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
Kojto 122:f9eeca106725 2587
Kojto 122:f9eeca106725 2588 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
Kojto 122:f9eeca106725 2589 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
Kojto 122:f9eeca106725 2590 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
Kojto 122:f9eeca106725 2591 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
Kojto 122:f9eeca106725 2592 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
Kojto 122:f9eeca106725 2593 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
Kojto 122:f9eeca106725 2594 #define __HAL_RCC_TIM18_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM18EN)) == RESET)
Kojto 122:f9eeca106725 2595 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
Kojto 122:f9eeca106725 2596 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
Kojto 122:f9eeca106725 2597 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
Kojto 122:f9eeca106725 2598 #define __HAL_RCC_DAC2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC2EN)) == RESET)
Kojto 122:f9eeca106725 2599 #define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
Kojto 122:f9eeca106725 2600 #endif /* STM32F373xC || STM32F378xx */
Kojto 122:f9eeca106725 2601
Kojto 122:f9eeca106725 2602 #if defined(STM32F303xE) || defined(STM32F398xx) \
Kojto 122:f9eeca106725 2603 || defined(STM32F303xC) || defined(STM32F358xx) \
Kojto 122:f9eeca106725 2604 || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
Kojto 122:f9eeca106725 2605 || defined(STM32F373xC) || defined(STM32F378xx)
Kojto 122:f9eeca106725 2606 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
Kojto 122:f9eeca106725 2607
Kojto 122:f9eeca106725 2608 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
Kojto 122:f9eeca106725 2609 #endif /* STM32F303xE || STM32F398xx || */
Kojto 122:f9eeca106725 2610 /* STM32F303xC || STM32F358xx || */
Kojto 122:f9eeca106725 2611 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
Kojto 122:f9eeca106725 2612 /* STM32F373xC || STM32F378xx */
Kojto 122:f9eeca106725 2613
Kojto 122:f9eeca106725 2614 #if defined(STM32F302xE) || defined(STM32F303xE)\
Kojto 122:f9eeca106725 2615 || defined(STM32F302xC) || defined(STM32F303xC)\
Kojto 122:f9eeca106725 2616 || defined(STM32F302x8) \
Kojto 122:f9eeca106725 2617 || defined(STM32F373xC)
Kojto 122:f9eeca106725 2618 #define __HAL_RCC_USB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET)
Kojto 122:f9eeca106725 2619
Kojto 122:f9eeca106725 2620 #define __HAL_RCC_USB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET)
Kojto 122:f9eeca106725 2621 #endif /* STM32F302xE || STM32F303xE || */
Kojto 122:f9eeca106725 2622 /* STM32F302xC || STM32F303xC || */
Kojto 122:f9eeca106725 2623 /* STM32F302x8 || */
Kojto 122:f9eeca106725 2624 /* STM32F373xC */
Kojto 122:f9eeca106725 2625
Kojto 122:f9eeca106725 2626 #if !defined(STM32F301x8)
Kojto 122:f9eeca106725 2627 #define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CANEN)) != RESET)
Kojto 122:f9eeca106725 2628
Kojto 122:f9eeca106725 2629 #define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CANEN)) == RESET)
Kojto 122:f9eeca106725 2630 #endif /* STM32F301x8*/
Kojto 122:f9eeca106725 2631
Kojto 122:f9eeca106725 2632 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
Kojto 122:f9eeca106725 2633 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
Kojto 122:f9eeca106725 2634
Kojto 122:f9eeca106725 2635 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
Kojto 122:f9eeca106725 2636 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
Kojto 122:f9eeca106725 2637 /**
Kojto 122:f9eeca106725 2638 * @}
Kojto 122:f9eeca106725 2639 */
Kojto 122:f9eeca106725 2640
Kojto 122:f9eeca106725 2641 /** @defgroup RCCEx_APB2_Clock_Enable_Disable_Status RCC Extended APB2 Peripheral Clock Enable Disable Status
Kojto 122:f9eeca106725 2642 * @brief Get the enable or disable status of the APB2 peripheral clock.
Kojto 122:f9eeca106725 2643 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 122:f9eeca106725 2644 * is disabled and the application software has to enable this clock before
Kojto 122:f9eeca106725 2645 * using it.
Kojto 122:f9eeca106725 2646 * @{
Kojto 122:f9eeca106725 2647 */
Kojto 122:f9eeca106725 2648 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
Kojto 122:f9eeca106725 2649 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
Kojto 122:f9eeca106725 2650 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
Kojto 122:f9eeca106725 2651
Kojto 122:f9eeca106725 2652 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
Kojto 122:f9eeca106725 2653 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
Kojto 122:f9eeca106725 2654 /* STM32F302xC || STM32F303xC || STM32F358xx */
Kojto 122:f9eeca106725 2655
Kojto 122:f9eeca106725 2656 #if defined(STM32F303xE) || defined(STM32F398xx)\
Kojto 122:f9eeca106725 2657 || defined(STM32F303xC) || defined(STM32F358xx)
Kojto 122:f9eeca106725 2658 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
Kojto 122:f9eeca106725 2659
Kojto 122:f9eeca106725 2660 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
Kojto 122:f9eeca106725 2661 #endif /* STM32F303xE || STM32F398xx || */
Kojto 122:f9eeca106725 2662 /* STM32F303xC || STM32F358xx */
Kojto 122:f9eeca106725 2663
Kojto 122:f9eeca106725 2664 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
Kojto 122:f9eeca106725 2665 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
Kojto 122:f9eeca106725 2666
Kojto 122:f9eeca106725 2667 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
Kojto 122:f9eeca106725 2668 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
Kojto 122:f9eeca106725 2669
Kojto 122:f9eeca106725 2670 #if defined(STM32F334x8)
Kojto 122:f9eeca106725 2671 #define __HAL_RCC_HRTIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_HRTIM1EN)) != RESET)
Kojto 122:f9eeca106725 2672
Kojto 122:f9eeca106725 2673 #define __HAL_RCC_HRTIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_HRTIM1EN)) == RESET)
Kojto 122:f9eeca106725 2674 #endif /* STM32F334x8 */
Kojto 122:f9eeca106725 2675
Kojto 122:f9eeca106725 2676 #if defined(STM32F373xC) || defined(STM32F378xx)
Kojto 122:f9eeca106725 2677 #define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
Kojto 122:f9eeca106725 2678 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
Kojto 122:f9eeca106725 2679 #define __HAL_RCC_TIM19_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM19EN)) != RESET)
Kojto 122:f9eeca106725 2680 #define __HAL_RCC_SDADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC1EN)) != RESET)
Kojto 122:f9eeca106725 2681 #define __HAL_RCC_SDADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC2EN)) != RESET)
Kojto 122:f9eeca106725 2682 #define __HAL_RCC_SDADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC3EN)) != RESET)
Kojto 122:f9eeca106725 2683
Kojto 122:f9eeca106725 2684 #define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
Kojto 122:f9eeca106725 2685 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
Kojto 122:f9eeca106725 2686 #define __HAL_RCC_TIM19_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM19EN)) == RESET)
Kojto 122:f9eeca106725 2687 #define __HAL_RCC_SDADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC1EN)) == RESET)
Kojto 122:f9eeca106725 2688 #define __HAL_RCC_SDADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC2EN)) == RESET)
Kojto 122:f9eeca106725 2689 #define __HAL_RCC_SDADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDADC3EN)) == RESET)
Kojto 122:f9eeca106725 2690 #endif /* STM32F373xC || STM32F378xx */
Kojto 122:f9eeca106725 2691
Kojto 122:f9eeca106725 2692 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
Kojto 122:f9eeca106725 2693 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
Kojto 122:f9eeca106725 2694 || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
Kojto 122:f9eeca106725 2695 || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
Kojto 122:f9eeca106725 2696 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
Kojto 122:f9eeca106725 2697
Kojto 122:f9eeca106725 2698 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
Kojto 122:f9eeca106725 2699 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
Kojto 122:f9eeca106725 2700 /* STM32F302xC || STM32F303xC || STM32F358xx || */
Kojto 122:f9eeca106725 2701 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
Kojto 122:f9eeca106725 2702 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
Kojto 122:f9eeca106725 2703
Kojto 122:f9eeca106725 2704 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
Kojto 122:f9eeca106725 2705 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
Kojto 122:f9eeca106725 2706
Kojto 122:f9eeca106725 2707 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
Kojto 122:f9eeca106725 2708 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
Kojto 122:f9eeca106725 2709
Kojto 122:f9eeca106725 2710 #if defined(STM32F303xE) || defined(STM32F398xx)
Kojto 122:f9eeca106725 2711 #define __HAL_RCC_TIM20_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM20EN)) != RESET)
Kojto 122:f9eeca106725 2712
Kojto 122:f9eeca106725 2713 #define __HAL_RCC_TIM20_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM20EN)) == RESET)
Kojto 122:f9eeca106725 2714 #endif /* STM32F303xE || STM32F398xx */
Kojto 122:f9eeca106725 2715 /**
Kojto 122:f9eeca106725 2716 * @}
Kojto 122:f9eeca106725 2717 */
Kojto 122:f9eeca106725 2718
bogdanm 92:4fc01daae5a5 2719 /** @defgroup RCCEx_AHB_Force_Release_Reset RCC Extended AHB Force Release Reset
bogdanm 92:4fc01daae5a5 2720 * @brief Force or release AHB peripheral reset.
bogdanm 92:4fc01daae5a5 2721 * @{
bogdanm 86:04dd9b1680ae 2722 */
bogdanm 86:04dd9b1680ae 2723 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
Kojto 122:f9eeca106725 2724 #define __HAL_RCC_ADC1_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ADC1RST))
Kojto 122:f9eeca106725 2725
Kojto 122:f9eeca106725 2726 #define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC1RST))
bogdanm 86:04dd9b1680ae 2727 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
bogdanm 86:04dd9b1680ae 2728
Kojto 122:f9eeca106725 2729 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
Kojto 122:f9eeca106725 2730 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
Kojto 122:f9eeca106725 2731 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST))
Kojto 122:f9eeca106725 2732 #define __HAL_RCC_ADC12_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ADC12RST))
bogdanm 86:04dd9b1680ae 2733 /* Aliases for STM32 F3 compatibility */
Kojto 122:f9eeca106725 2734 #define __HAL_RCC_ADC1_FORCE_RESET() __HAL_RCC_ADC12_FORCE_RESET()
Kojto 122:f9eeca106725 2735 #define __HAL_RCC_ADC2_FORCE_RESET() __HAL_RCC_ADC12_FORCE_RESET()
Kojto 122:f9eeca106725 2736
Kojto 122:f9eeca106725 2737 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))
Kojto 122:f9eeca106725 2738 #define __HAL_RCC_ADC12_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC12RST))
bogdanm 86:04dd9b1680ae 2739 /* Aliases for STM32 F3 compatibility */
Kojto 122:f9eeca106725 2740 #define __HAL_RCC_ADC1_RELEASE_RESET() __HAL_RCC_ADC12_RELEASE_RESET()
Kojto 122:f9eeca106725 2741 #define __HAL_RCC_ADC2_RELEASE_RESET() __HAL_RCC_ADC12_RELEASE_RESET()
bogdanm 92:4fc01daae5a5 2742 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
bogdanm 92:4fc01daae5a5 2743 /* STM32F302xC || STM32F303xC || STM32F358xx */
bogdanm 92:4fc01daae5a5 2744
Kojto 122:f9eeca106725 2745 #if defined(STM32F303xE) || defined(STM32F398xx)\
Kojto 122:f9eeca106725 2746 || defined(STM32F303xC) || defined(STM32F358xx)
Kojto 122:f9eeca106725 2747 #define __HAL_RCC_ADC34_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ADC34RST))
Kojto 122:f9eeca106725 2748
Kojto 122:f9eeca106725 2749 #define __HAL_RCC_ADC34_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC34RST))
bogdanm 92:4fc01daae5a5 2750 #endif /* STM32F303xE || STM32F398xx || */
bogdanm 92:4fc01daae5a5 2751 /* STM32F303xC || STM32F358xx */
bogdanm 86:04dd9b1680ae 2752
bogdanm 86:04dd9b1680ae 2753 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
Kojto 122:f9eeca106725 2754 #define __HAL_RCC_ADC12_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ADC12RST))
bogdanm 86:04dd9b1680ae 2755 /* Aliases for STM32 F3 compatibility */
Kojto 122:f9eeca106725 2756 #define __HAL_RCC_ADC1_FORCE_RESET() __HAL_RCC_ADC12_FORCE_RESET()
Kojto 122:f9eeca106725 2757 #define __HAL_RCC_ADC2_FORCE_RESET() __HAL_RCC_ADC12_FORCE_RESET()
Kojto 122:f9eeca106725 2758
Kojto 122:f9eeca106725 2759 #define __HAL_RCC_ADC12_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC12RST))
bogdanm 86:04dd9b1680ae 2760 /* Aliases for STM32 F3 compatibility */
Kojto 122:f9eeca106725 2761 #define __HAL_RCC_ADC1_RELEASE_RESET() __HAL_RCC_ADC12_RELEASE_RESET()
Kojto 122:f9eeca106725 2762 #define __HAL_RCC_ADC2_RELEASE_RESET() __HAL_RCC_ADC12_RELEASE_RESET()
bogdanm 86:04dd9b1680ae 2763 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
bogdanm 86:04dd9b1680ae 2764
bogdanm 86:04dd9b1680ae 2765 #if defined(STM32F373xC) || defined(STM32F378xx)
Kojto 122:f9eeca106725 2766 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST))
Kojto 122:f9eeca106725 2767
Kojto 122:f9eeca106725 2768 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))
bogdanm 86:04dd9b1680ae 2769 #endif /* STM32F373xC || STM32F378xx */
bogdanm 86:04dd9b1680ae 2770
bogdanm 92:4fc01daae5a5 2771 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
Kojto 122:f9eeca106725 2772 #define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_FMCRST))
Kojto 122:f9eeca106725 2773 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOGRST))
Kojto 122:f9eeca106725 2774 #define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOHRST))
Kojto 122:f9eeca106725 2775
Kojto 122:f9eeca106725 2776 #define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_FMCRST))
Kojto 122:f9eeca106725 2777 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOGRST))
Kojto 122:f9eeca106725 2778 #define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOHRST))
bogdanm 92:4fc01daae5a5 2779 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
bogdanm 92:4fc01daae5a5 2780 /**
bogdanm 92:4fc01daae5a5 2781 * @}
bogdanm 92:4fc01daae5a5 2782 */
bogdanm 92:4fc01daae5a5 2783
bogdanm 92:4fc01daae5a5 2784 /** @defgroup RCCEx_APB1_Force_Release_Reset RCC Extended APB1 Force Release Reset
bogdanm 92:4fc01daae5a5 2785 * @brief Force or release APB1 peripheral reset.
bogdanm 92:4fc01daae5a5 2786 * @{
bogdanm 86:04dd9b1680ae 2787 */
bogdanm 86:04dd9b1680ae 2788 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
Kojto 122:f9eeca106725 2789 #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
Kojto 122:f9eeca106725 2790 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
Kojto 122:f9eeca106725 2791 #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
Kojto 122:f9eeca106725 2792 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
Kojto 122:f9eeca106725 2793
Kojto 122:f9eeca106725 2794 #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
Kojto 122:f9eeca106725 2795 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
Kojto 122:f9eeca106725 2796 #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
Kojto 122:f9eeca106725 2797 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
bogdanm 86:04dd9b1680ae 2798 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
bogdanm 86:04dd9b1680ae 2799
Kojto 122:f9eeca106725 2800 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
Kojto 122:f9eeca106725 2801 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
Kojto 122:f9eeca106725 2802 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
Kojto 122:f9eeca106725 2803 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
Kojto 122:f9eeca106725 2804 #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
Kojto 122:f9eeca106725 2805 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
Kojto 122:f9eeca106725 2806 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
Kojto 122:f9eeca106725 2807 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
Kojto 122:f9eeca106725 2808 #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
Kojto 122:f9eeca106725 2809
Kojto 122:f9eeca106725 2810 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
Kojto 122:f9eeca106725 2811 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
Kojto 122:f9eeca106725 2812 #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
Kojto 122:f9eeca106725 2813 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
Kojto 122:f9eeca106725 2814 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
Kojto 122:f9eeca106725 2815 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
Kojto 122:f9eeca106725 2816 #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
bogdanm 92:4fc01daae5a5 2817 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
bogdanm 92:4fc01daae5a5 2818 /* STM32F302xC || STM32F303xC || STM32F358xx */
bogdanm 86:04dd9b1680ae 2819
bogdanm 86:04dd9b1680ae 2820 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
Kojto 122:f9eeca106725 2821 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
Kojto 122:f9eeca106725 2822 #define __HAL_RCC_DAC2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DAC2RST))
Kojto 122:f9eeca106725 2823
Kojto 122:f9eeca106725 2824 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
Kojto 122:f9eeca106725 2825 #define __HAL_RCC_DAC2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DAC2RST))
bogdanm 86:04dd9b1680ae 2826 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
bogdanm 86:04dd9b1680ae 2827
bogdanm 86:04dd9b1680ae 2828 #if defined(STM32F373xC) || defined(STM32F378xx)
Kojto 122:f9eeca106725 2829 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
Kojto 122:f9eeca106725 2830 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
Kojto 122:f9eeca106725 2831 #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
Kojto 122:f9eeca106725 2832 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
Kojto 122:f9eeca106725 2833 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
Kojto 122:f9eeca106725 2834 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
Kojto 122:f9eeca106725 2835 #define __HAL_RCC_TIM18_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM18RST))
Kojto 122:f9eeca106725 2836 #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
Kojto 122:f9eeca106725 2837 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
Kojto 122:f9eeca106725 2838 #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
Kojto 122:f9eeca106725 2839 #define __HAL_RCC_DAC2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DAC2RST))
Kojto 122:f9eeca106725 2840 #define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))
Kojto 122:f9eeca106725 2841
Kojto 122:f9eeca106725 2842 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
Kojto 122:f9eeca106725 2843 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
Kojto 122:f9eeca106725 2844 #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
Kojto 122:f9eeca106725 2845 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
Kojto 122:f9eeca106725 2846 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
Kojto 122:f9eeca106725 2847 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
Kojto 122:f9eeca106725 2848 #define __HAL_RCC_TIM18_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM18RST))
Kojto 122:f9eeca106725 2849 #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
Kojto 122:f9eeca106725 2850 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
Kojto 122:f9eeca106725 2851 #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
Kojto 122:f9eeca106725 2852 #define __HAL_RCC_DAC2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DAC2RST))
Kojto 122:f9eeca106725 2853 #define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
bogdanm 86:04dd9b1680ae 2854 #endif /* STM32F373xC || STM32F378xx */
bogdanm 86:04dd9b1680ae 2855
Kojto 122:f9eeca106725 2856 #if defined(STM32F303xE) || defined(STM32F398xx)\
Kojto 122:f9eeca106725 2857 || defined(STM32F303xC) || defined(STM32F358xx)\
Kojto 122:f9eeca106725 2858 || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
Kojto 122:f9eeca106725 2859 || defined(STM32F373xC) || defined(STM32F378xx)
Kojto 122:f9eeca106725 2860 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
Kojto 122:f9eeca106725 2861
Kojto 122:f9eeca106725 2862 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
bogdanm 92:4fc01daae5a5 2863 #endif /* STM32F303xE || STM32F398xx || */
bogdanm 92:4fc01daae5a5 2864 /* STM32F303xC || STM32F358xx || */
bogdanm 92:4fc01daae5a5 2865 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
bogdanm 92:4fc01daae5a5 2866 /* STM32F373xC || STM32F378xx */
bogdanm 92:4fc01daae5a5 2867
Kojto 122:f9eeca106725 2868 #if defined(STM32F302xE) || defined(STM32F303xE)\
Kojto 122:f9eeca106725 2869 || defined(STM32F302xC) || defined(STM32F303xC)\
Kojto 122:f9eeca106725 2870 || defined(STM32F302x8) \
Kojto 122:f9eeca106725 2871 || defined(STM32F373xC)
Kojto 122:f9eeca106725 2872 #define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST))
Kojto 122:f9eeca106725 2873
Kojto 122:f9eeca106725 2874 #define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
bogdanm 92:4fc01daae5a5 2875 #endif /* STM32F302xE || STM32F303xE || */
bogdanm 92:4fc01daae5a5 2876 /* STM32F302xC || STM32F303xC || */
bogdanm 92:4fc01daae5a5 2877 /* STM32F302x8 || */
bogdanm 92:4fc01daae5a5 2878 /* STM32F373xC */
bogdanm 86:04dd9b1680ae 2879
bogdanm 86:04dd9b1680ae 2880 #if !defined(STM32F301x8)
Kojto 122:f9eeca106725 2881 #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CANRST))
Kojto 122:f9eeca106725 2882
Kojto 122:f9eeca106725 2883 #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CANRST))
bogdanm 86:04dd9b1680ae 2884 #endif /* STM32F301x8*/
bogdanm 86:04dd9b1680ae 2885
bogdanm 92:4fc01daae5a5 2886 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
Kojto 122:f9eeca106725 2887 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
Kojto 122:f9eeca106725 2888
Kojto 122:f9eeca106725 2889 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
bogdanm 92:4fc01daae5a5 2890 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
bogdanm 92:4fc01daae5a5 2891 /**
bogdanm 92:4fc01daae5a5 2892 * @}
bogdanm 86:04dd9b1680ae 2893 */
bogdanm 92:4fc01daae5a5 2894
bogdanm 92:4fc01daae5a5 2895 /** @defgroup RCCEx_APB2_Force_Release_Reset RCC Extended APB2 Force Release Reset
bogdanm 92:4fc01daae5a5 2896 * @brief Force or release APB2 peripheral reset.
bogdanm 92:4fc01daae5a5 2897 * @{
bogdanm 92:4fc01daae5a5 2898 */
Kojto 122:f9eeca106725 2899 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
Kojto 122:f9eeca106725 2900 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
Kojto 122:f9eeca106725 2901 #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
Kojto 122:f9eeca106725 2902
Kojto 122:f9eeca106725 2903 #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
bogdanm 92:4fc01daae5a5 2904 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
bogdanm 92:4fc01daae5a5 2905 /* STM32F302xC || STM32F303xC || STM32F358xx */
bogdanm 92:4fc01daae5a5 2906
Kojto 122:f9eeca106725 2907 #if defined(STM32F303xE) || defined(STM32F398xx)\
Kojto 122:f9eeca106725 2908 || defined(STM32F303xC) || defined(STM32F358xx)
Kojto 122:f9eeca106725 2909 #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
Kojto 122:f9eeca106725 2910
Kojto 122:f9eeca106725 2911 #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
bogdanm 92:4fc01daae5a5 2912 #endif /* STM32F303xE || STM32F398xx || */
bogdanm 92:4fc01daae5a5 2913 /* STM32F303xC || STM32F358xx */
bogdanm 86:04dd9b1680ae 2914
bogdanm 86:04dd9b1680ae 2915 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
Kojto 122:f9eeca106725 2916 #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
Kojto 122:f9eeca106725 2917
Kojto 122:f9eeca106725 2918 #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
bogdanm 86:04dd9b1680ae 2919 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
bogdanm 86:04dd9b1680ae 2920
bogdanm 86:04dd9b1680ae 2921 #if defined(STM32F334x8)
Kojto 122:f9eeca106725 2922 #define __HAL_RCC_HRTIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_HRTIM1RST))
Kojto 122:f9eeca106725 2923
Kojto 122:f9eeca106725 2924 #define __HAL_RCC_HRTIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_HRTIM1RST))
bogdanm 86:04dd9b1680ae 2925 #endif /* STM32F334x8 */
bogdanm 86:04dd9b1680ae 2926
bogdanm 86:04dd9b1680ae 2927 #if defined(STM32F373xC) || defined(STM32F378xx)
Kojto 122:f9eeca106725 2928 #define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST))
Kojto 122:f9eeca106725 2929 #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
Kojto 122:f9eeca106725 2930 #define __HAL_RCC_TIM19_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM19RST))
Kojto 122:f9eeca106725 2931 #define __HAL_RCC_SDADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDADC1RST))
Kojto 122:f9eeca106725 2932 #define __HAL_RCC_SDADC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDADC2RST))
Kojto 122:f9eeca106725 2933 #define __HAL_RCC_SDADC3_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDADC3RST))
Kojto 122:f9eeca106725 2934
Kojto 122:f9eeca106725 2935 #define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
Kojto 122:f9eeca106725 2936 #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
Kojto 122:f9eeca106725 2937 #define __HAL_RCC_TIM19_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM19RST))
Kojto 122:f9eeca106725 2938 #define __HAL_RCC_SDADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC1RST))
Kojto 122:f9eeca106725 2939 #define __HAL_RCC_SDADC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC2RST))
Kojto 122:f9eeca106725 2940 #define __HAL_RCC_SDADC3_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC3RST))
bogdanm 86:04dd9b1680ae 2941 #endif /* STM32F373xC || STM32F378xx */
bogdanm 86:04dd9b1680ae 2942
Kojto 122:f9eeca106725 2943 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
Kojto 122:f9eeca106725 2944 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
Kojto 122:f9eeca106725 2945 || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
Kojto 122:f9eeca106725 2946 || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
Kojto 122:f9eeca106725 2947 #define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
Kojto 122:f9eeca106725 2948
Kojto 122:f9eeca106725 2949 #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
bogdanm 92:4fc01daae5a5 2950 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
bogdanm 86:04dd9b1680ae 2951 /* STM32F302xC || STM32F303xC || STM32F358xx || */
bogdanm 92:4fc01daae5a5 2952 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
bogdanm 92:4fc01daae5a5 2953 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
bogdanm 92:4fc01daae5a5 2954
bogdanm 92:4fc01daae5a5 2955 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
Kojto 122:f9eeca106725 2956 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
Kojto 122:f9eeca106725 2957
Kojto 122:f9eeca106725 2958 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
bogdanm 92:4fc01daae5a5 2959 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
bogdanm 92:4fc01daae5a5 2960
bogdanm 92:4fc01daae5a5 2961 #if defined(STM32F303xE) || defined(STM32F398xx)
Kojto 122:f9eeca106725 2962 #define __HAL_RCC_TIM20_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM20RST))
Kojto 122:f9eeca106725 2963
Kojto 122:f9eeca106725 2964 #define __HAL_RCC_TIM20_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM20RST))
bogdanm 92:4fc01daae5a5 2965 #endif /* STM32F303xE || STM32F398xx */
bogdanm 92:4fc01daae5a5 2966
bogdanm 92:4fc01daae5a5 2967 /**
bogdanm 92:4fc01daae5a5 2968 * @}
bogdanm 92:4fc01daae5a5 2969 */
bogdanm 86:04dd9b1680ae 2970
bogdanm 86:04dd9b1680ae 2971 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
bogdanm 92:4fc01daae5a5 2972 /** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config
bogdanm 92:4fc01daae5a5 2973 * @{
bogdanm 92:4fc01daae5a5 2974 */
bogdanm 86:04dd9b1680ae 2975
bogdanm 86:04dd9b1680ae 2976 /** @brief Macro to configure the I2C2 clock (I2C2CLK).
Kojto 122:f9eeca106725 2977 * @param __I2C2CLKSource__ specifies the I2C2 clock source.
bogdanm 86:04dd9b1680ae 2978 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 2979 * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
Kojto 122:f9eeca106725 2980 * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
bogdanm 86:04dd9b1680ae 2981 */
bogdanm 86:04dd9b1680ae 2982 #define __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) \
bogdanm 86:04dd9b1680ae 2983 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C2SW, (uint32_t)(__I2C2CLKSource__))
bogdanm 86:04dd9b1680ae 2984
bogdanm 86:04dd9b1680ae 2985 /** @brief Macro to get the I2C2 clock source.
bogdanm 86:04dd9b1680ae 2986 * @retval The clock source can be one of the following values:
Kojto 122:f9eeca106725 2987 * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
Kojto 122:f9eeca106725 2988 * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
bogdanm 86:04dd9b1680ae 2989 */
bogdanm 86:04dd9b1680ae 2990 #define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C2SW)))
bogdanm 86:04dd9b1680ae 2991
bogdanm 86:04dd9b1680ae 2992 /** @brief Macro to configure the I2C3 clock (I2C3CLK).
Kojto 122:f9eeca106725 2993 * @param __I2C3CLKSource__ specifies the I2C3 clock source.
bogdanm 86:04dd9b1680ae 2994 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 2995 * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock
Kojto 122:f9eeca106725 2996 * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock
bogdanm 86:04dd9b1680ae 2997 */
bogdanm 86:04dd9b1680ae 2998 #define __HAL_RCC_I2C3_CONFIG(__I2C3CLKSource__) \
bogdanm 86:04dd9b1680ae 2999 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C3SW, (uint32_t)(__I2C3CLKSource__))
bogdanm 86:04dd9b1680ae 3000
bogdanm 86:04dd9b1680ae 3001 /** @brief Macro to get the I2C3 clock source.
bogdanm 86:04dd9b1680ae 3002 * @retval The clock source can be one of the following values:
Kojto 122:f9eeca106725 3003 * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock
Kojto 122:f9eeca106725 3004 * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock
bogdanm 86:04dd9b1680ae 3005 */
bogdanm 86:04dd9b1680ae 3006 #define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C3SW)))
bogdanm 86:04dd9b1680ae 3007
bogdanm 92:4fc01daae5a5 3008 /**
bogdanm 92:4fc01daae5a5 3009 * @}
bogdanm 92:4fc01daae5a5 3010 */
bogdanm 92:4fc01daae5a5 3011
bogdanm 92:4fc01daae5a5 3012 /** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
bogdanm 92:4fc01daae5a5 3013 * @{
bogdanm 92:4fc01daae5a5 3014 */
bogdanm 86:04dd9b1680ae 3015 /** @brief Macro to configure the TIM1 clock (TIM1CLK).
Kojto 122:f9eeca106725 3016 * @param __TIM1CLKSource__ specifies the TIM1 clock source.
bogdanm 86:04dd9b1680ae 3017 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 3018 * @arg @ref RCC_TIM1CLK_HCLK HCLK selected as TIM1 clock
Kojto 122:f9eeca106725 3019 * @arg @ref RCC_TIM1CLK_PLLCLK PLL Clock selected as TIM1 clock
bogdanm 86:04dd9b1680ae 3020 */
bogdanm 86:04dd9b1680ae 3021 #define __HAL_RCC_TIM1_CONFIG(__TIM1CLKSource__) \
bogdanm 86:04dd9b1680ae 3022 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM1SW, (uint32_t)(__TIM1CLKSource__))
bogdanm 86:04dd9b1680ae 3023
bogdanm 86:04dd9b1680ae 3024 /** @brief Macro to get the TIM1 clock (TIM1CLK).
bogdanm 86:04dd9b1680ae 3025 * @retval The clock source can be one of the following values:
Kojto 122:f9eeca106725 3026 * @arg @ref RCC_TIM1CLK_HCLK HCLK selected as TIM1 clock
Kojto 122:f9eeca106725 3027 * @arg @ref RCC_TIM1CLK_PLLCLK PLL Clock selected as TIM1 clock
bogdanm 86:04dd9b1680ae 3028 */
bogdanm 86:04dd9b1680ae 3029 #define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM1SW)))
bogdanm 86:04dd9b1680ae 3030
bogdanm 86:04dd9b1680ae 3031 /** @brief Macro to configure the TIM15 clock (TIM15CLK).
Kojto 122:f9eeca106725 3032 * @param __TIM15CLKSource__ specifies the TIM15 clock source.
bogdanm 86:04dd9b1680ae 3033 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 3034 * @arg @ref RCC_TIM15CLK_HCLK HCLK selected as TIM15 clock
Kojto 122:f9eeca106725 3035 * @arg @ref RCC_TIM15CLK_PLL PLL Clock selected as TIM15 clock
bogdanm 86:04dd9b1680ae 3036 */
bogdanm 86:04dd9b1680ae 3037 #define __HAL_RCC_TIM15_CONFIG(__TIM15CLKSource__) \
bogdanm 86:04dd9b1680ae 3038 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM15SW, (uint32_t)(__TIM15CLKSource__))
bogdanm 86:04dd9b1680ae 3039
bogdanm 86:04dd9b1680ae 3040 /** @brief Macro to get the TIM15 clock (TIM15CLK).
bogdanm 86:04dd9b1680ae 3041 * @retval The clock source can be one of the following values:
Kojto 122:f9eeca106725 3042 * @arg @ref RCC_TIM15CLK_HCLK HCLK selected as TIM15 clock
Kojto 122:f9eeca106725 3043 * @arg @ref RCC_TIM15CLK_PLL PLL Clock selected as TIM15 clock
bogdanm 86:04dd9b1680ae 3044 */
bogdanm 86:04dd9b1680ae 3045 #define __HAL_RCC_GET_TIM15_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM15SW)))
bogdanm 86:04dd9b1680ae 3046
bogdanm 86:04dd9b1680ae 3047 /** @brief Macro to configure the TIM16 clock (TIM16CLK).
Kojto 122:f9eeca106725 3048 * @param __TIM16CLKSource__ specifies the TIM16 clock source.
bogdanm 86:04dd9b1680ae 3049 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 3050 * @arg @ref RCC_TIM16CLK_HCLK HCLK selected as TIM16 clock
Kojto 122:f9eeca106725 3051 * @arg @ref RCC_TIM16CLK_PLL PLL Clock selected as TIM16 clock
bogdanm 86:04dd9b1680ae 3052 */
bogdanm 86:04dd9b1680ae 3053 #define __HAL_RCC_TIM16_CONFIG(__TIM16CLKSource__) \
bogdanm 86:04dd9b1680ae 3054 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM16SW, (uint32_t)(__TIM16CLKSource__))
bogdanm 86:04dd9b1680ae 3055
bogdanm 86:04dd9b1680ae 3056 /** @brief Macro to get the TIM16 clock (TIM16CLK).
bogdanm 86:04dd9b1680ae 3057 * @retval The clock source can be one of the following values:
Kojto 122:f9eeca106725 3058 * @arg @ref RCC_TIM16CLK_HCLK HCLK selected as TIM16 clock
Kojto 122:f9eeca106725 3059 * @arg @ref RCC_TIM16CLK_PLL PLL Clock selected as TIM16 clock
bogdanm 86:04dd9b1680ae 3060 */
bogdanm 86:04dd9b1680ae 3061 #define __HAL_RCC_GET_TIM16_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM16SW)))
bogdanm 86:04dd9b1680ae 3062
bogdanm 86:04dd9b1680ae 3063 /** @brief Macro to configure the TIM17 clock (TIM17CLK).
Kojto 122:f9eeca106725 3064 * @param __TIM17CLKSource__ specifies the TIM17 clock source.
bogdanm 86:04dd9b1680ae 3065 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 3066 * @arg @ref RCC_TIM17CLK_HCLK HCLK selected as TIM17 clock
Kojto 122:f9eeca106725 3067 * @arg @ref RCC_TIM17CLK_PLL PLL Clock selected as TIM17 clock
bogdanm 86:04dd9b1680ae 3068 */
bogdanm 86:04dd9b1680ae 3069 #define __HAL_RCC_TIM17_CONFIG(__TIM17CLKSource__) \
bogdanm 86:04dd9b1680ae 3070 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM17SW, (uint32_t)(__TIM17CLKSource__))
bogdanm 86:04dd9b1680ae 3071
bogdanm 86:04dd9b1680ae 3072 /** @brief Macro to get the TIM17 clock (TIM17CLK).
bogdanm 86:04dd9b1680ae 3073 * @retval The clock source can be one of the following values:
Kojto 122:f9eeca106725 3074 * @arg @ref RCC_TIM17CLK_HCLK HCLK selected as TIM17 clock
Kojto 122:f9eeca106725 3075 * @arg @ref RCC_TIM17CLK_PLL PLL Clock selected as TIM17 clock
bogdanm 86:04dd9b1680ae 3076 */
bogdanm 86:04dd9b1680ae 3077 #define __HAL_RCC_GET_TIM17_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM17SW)))
bogdanm 86:04dd9b1680ae 3078
bogdanm 92:4fc01daae5a5 3079 /**
bogdanm 92:4fc01daae5a5 3080 * @}
bogdanm 92:4fc01daae5a5 3081 */
bogdanm 92:4fc01daae5a5 3082
bogdanm 92:4fc01daae5a5 3083 /** @defgroup RCCEx_I2Sx_Clock_Config RCC Extended I2Sx Clock Config
bogdanm 92:4fc01daae5a5 3084 * @{
bogdanm 92:4fc01daae5a5 3085 */
bogdanm 86:04dd9b1680ae 3086 /** @brief Macro to configure the I2S clock source (I2SCLK).
bogdanm 86:04dd9b1680ae 3087 * @note This function must be called before enabling the I2S APB clock.
Kojto 122:f9eeca106725 3088 * @param __I2SCLKSource__ specifies the I2S clock source.
bogdanm 86:04dd9b1680ae 3089 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 3090 * @arg @ref RCC_I2SCLKSOURCE_SYSCLK SYSCLK clock used as I2S clock source
Kojto 122:f9eeca106725 3091 * @arg @ref RCC_I2SCLKSOURCE_EXT External clock mapped on the I2S_CKIN pin
bogdanm 86:04dd9b1680ae 3092 * used as I2S clock source
bogdanm 86:04dd9b1680ae 3093 */
bogdanm 86:04dd9b1680ae 3094 #define __HAL_RCC_I2S_CONFIG(__I2SCLKSource__) \
bogdanm 86:04dd9b1680ae 3095 MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, (uint32_t)(__I2SCLKSource__))
bogdanm 86:04dd9b1680ae 3096
bogdanm 86:04dd9b1680ae 3097 /** @brief Macro to get the I2S clock source (I2SCLK).
bogdanm 86:04dd9b1680ae 3098 * @retval The clock source can be one of the following values:
Kojto 122:f9eeca106725 3099 * @arg @ref RCC_I2SCLKSOURCE_SYSCLK SYSCLK clock used as I2S clock source
Kojto 122:f9eeca106725 3100 * @arg @ref RCC_I2SCLKSOURCE_EXT External clock mapped on the I2S_CKIN pin
bogdanm 86:04dd9b1680ae 3101 * used as I2S clock source
bogdanm 86:04dd9b1680ae 3102 */
bogdanm 86:04dd9b1680ae 3103 #define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC)))
bogdanm 92:4fc01daae5a5 3104 /**
bogdanm 92:4fc01daae5a5 3105 * @}
bogdanm 92:4fc01daae5a5 3106 */
bogdanm 92:4fc01daae5a5 3107
bogdanm 92:4fc01daae5a5 3108 /** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
bogdanm 92:4fc01daae5a5 3109 * @{
bogdanm 92:4fc01daae5a5 3110 */
bogdanm 86:04dd9b1680ae 3111
bogdanm 86:04dd9b1680ae 3112 /** @brief Macro to configure the ADC1 clock (ADC1CLK).
Kojto 122:f9eeca106725 3113 * @param __ADC1CLKSource__ specifies the ADC1 clock source.
bogdanm 86:04dd9b1680ae 3114 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 3115 * @arg @ref RCC_ADC1PLLCLK_OFF ADC1 PLL clock disabled, ADC1 can use AHB clock
Kojto 122:f9eeca106725 3116 * @arg @ref RCC_ADC1PLLCLK_DIV1 PLL clock divided by 1 selected as ADC1 clock
Kojto 122:f9eeca106725 3117 * @arg @ref RCC_ADC1PLLCLK_DIV2 PLL clock divided by 2 selected as ADC1 clock
Kojto 122:f9eeca106725 3118 * @arg @ref RCC_ADC1PLLCLK_DIV4 PLL clock divided by 4 selected as ADC1 clock
Kojto 122:f9eeca106725 3119 * @arg @ref RCC_ADC1PLLCLK_DIV6 PLL clock divided by 6 selected as ADC1 clock
Kojto 122:f9eeca106725 3120 * @arg @ref RCC_ADC1PLLCLK_DIV8 PLL clock divided by 8 selected as ADC1 clock
Kojto 122:f9eeca106725 3121 * @arg @ref RCC_ADC1PLLCLK_DIV10 PLL clock divided by 10 selected as ADC1 clock
Kojto 122:f9eeca106725 3122 * @arg @ref RCC_ADC1PLLCLK_DIV12 PLL clock divided by 12 selected as ADC1 clock
Kojto 122:f9eeca106725 3123 * @arg @ref RCC_ADC1PLLCLK_DIV16 PLL clock divided by 16 selected as ADC1 clock
Kojto 122:f9eeca106725 3124 * @arg @ref RCC_ADC1PLLCLK_DIV32 PLL clock divided by 32 selected as ADC1 clock
Kojto 122:f9eeca106725 3125 * @arg @ref RCC_ADC1PLLCLK_DIV64 PLL clock divided by 64 selected as ADC1 clock
Kojto 122:f9eeca106725 3126 * @arg @ref RCC_ADC1PLLCLK_DIV128 PLL clock divided by 128 selected as ADC1 clock
Kojto 122:f9eeca106725 3127 * @arg @ref RCC_ADC1PLLCLK_DIV256 PLL clock divided by 256 selected as ADC1 clock
bogdanm 86:04dd9b1680ae 3128 */
bogdanm 86:04dd9b1680ae 3129 #define __HAL_RCC_ADC1_CONFIG(__ADC1CLKSource__) \
bogdanm 86:04dd9b1680ae 3130 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADC1PRES, (uint32_t)(__ADC1CLKSource__))
bogdanm 86:04dd9b1680ae 3131
bogdanm 86:04dd9b1680ae 3132 /** @brief Macro to get the ADC1 clock
bogdanm 86:04dd9b1680ae 3133 * @retval The clock source can be one of the following values:
Kojto 122:f9eeca106725 3134 * @arg @ref RCC_ADC1PLLCLK_OFF ADC1 PLL clock disabled, ADC1 can use AHB clock
Kojto 122:f9eeca106725 3135 * @arg @ref RCC_ADC1PLLCLK_DIV1 PLL clock divided by 1 selected as ADC1 clock
Kojto 122:f9eeca106725 3136 * @arg @ref RCC_ADC1PLLCLK_DIV2 PLL clock divided by 2 selected as ADC1 clock
Kojto 122:f9eeca106725 3137 * @arg @ref RCC_ADC1PLLCLK_DIV4 PLL clock divided by 4 selected as ADC1 clock
Kojto 122:f9eeca106725 3138 * @arg @ref RCC_ADC1PLLCLK_DIV6 PLL clock divided by 6 selected as ADC1 clock
Kojto 122:f9eeca106725 3139 * @arg @ref RCC_ADC1PLLCLK_DIV8 PLL clock divided by 8 selected as ADC1 clock
Kojto 122:f9eeca106725 3140 * @arg @ref RCC_ADC1PLLCLK_DIV10 PLL clock divided by 10 selected as ADC1 clock
Kojto 122:f9eeca106725 3141 * @arg @ref RCC_ADC1PLLCLK_DIV12 PLL clock divided by 12 selected as ADC1 clock
Kojto 122:f9eeca106725 3142 * @arg @ref RCC_ADC1PLLCLK_DIV16 PLL clock divided by 16 selected as ADC1 clock
Kojto 122:f9eeca106725 3143 * @arg @ref RCC_ADC1PLLCLK_DIV32 PLL clock divided by 32 selected as ADC1 clock
Kojto 122:f9eeca106725 3144 * @arg @ref RCC_ADC1PLLCLK_DIV64 PLL clock divided by 64 selected as ADC1 clock
Kojto 122:f9eeca106725 3145 * @arg @ref RCC_ADC1PLLCLK_DIV128 PLL clock divided by 128 selected as ADC1 clock
Kojto 122:f9eeca106725 3146 * @arg @ref RCC_ADC1PLLCLK_DIV256 PLL clock divided by 256 selected as ADC1 clock
bogdanm 86:04dd9b1680ae 3147 */
bogdanm 86:04dd9b1680ae 3148 #define __HAL_RCC_GET_ADC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADC1PRES)))
bogdanm 92:4fc01daae5a5 3149 /**
bogdanm 92:4fc01daae5a5 3150 * @}
bogdanm 92:4fc01daae5a5 3151 */
bogdanm 86:04dd9b1680ae 3152
bogdanm 86:04dd9b1680ae 3153 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
bogdanm 86:04dd9b1680ae 3154
Kojto 122:f9eeca106725 3155 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
Kojto 122:f9eeca106725 3156 || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
bogdanm 92:4fc01daae5a5 3157 /** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config
bogdanm 92:4fc01daae5a5 3158 * @{
bogdanm 92:4fc01daae5a5 3159 */
bogdanm 86:04dd9b1680ae 3160
bogdanm 86:04dd9b1680ae 3161 /** @brief Macro to configure the I2C2 clock (I2C2CLK).
Kojto 122:f9eeca106725 3162 * @param __I2C2CLKSource__ specifies the I2C2 clock source.
bogdanm 86:04dd9b1680ae 3163 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 3164 * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
Kojto 122:f9eeca106725 3165 * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
bogdanm 86:04dd9b1680ae 3166 */
bogdanm 86:04dd9b1680ae 3167 #define __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) \
bogdanm 86:04dd9b1680ae 3168 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C2SW, (uint32_t)(__I2C2CLKSource__))
bogdanm 86:04dd9b1680ae 3169
bogdanm 86:04dd9b1680ae 3170 /** @brief Macro to get the I2C2 clock source.
bogdanm 86:04dd9b1680ae 3171 * @retval The clock source can be one of the following values:
Kojto 122:f9eeca106725 3172 * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
Kojto 122:f9eeca106725 3173 * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
bogdanm 86:04dd9b1680ae 3174 */
bogdanm 86:04dd9b1680ae 3175 #define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C2SW)))
bogdanm 92:4fc01daae5a5 3176 /**
bogdanm 92:4fc01daae5a5 3177 * @}
bogdanm 92:4fc01daae5a5 3178 */
bogdanm 92:4fc01daae5a5 3179
bogdanm 92:4fc01daae5a5 3180 /** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
bogdanm 92:4fc01daae5a5 3181 * @{
bogdanm 92:4fc01daae5a5 3182 */
bogdanm 86:04dd9b1680ae 3183
bogdanm 86:04dd9b1680ae 3184 /** @brief Macro to configure the ADC1 & ADC2 clock (ADC12CLK).
Kojto 122:f9eeca106725 3185 * @param __ADC12CLKSource__ specifies the ADC1 & ADC2 clock source.
bogdanm 86:04dd9b1680ae 3186 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 3187 * @arg @ref RCC_ADC12PLLCLK_OFF ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock
Kojto 122:f9eeca106725 3188 * @arg @ref RCC_ADC12PLLCLK_DIV1 PLL clock divided by 1 selected as ADC1 & ADC2 clock
Kojto 122:f9eeca106725 3189 * @arg @ref RCC_ADC12PLLCLK_DIV2 PLL clock divided by 2 selected as ADC1 & ADC2 clock
Kojto 122:f9eeca106725 3190 * @arg @ref RCC_ADC12PLLCLK_DIV4 PLL clock divided by 4 selected as ADC1 & ADC2 clock
Kojto 122:f9eeca106725 3191 * @arg @ref RCC_ADC12PLLCLK_DIV6 PLL clock divided by 6 selected as ADC1 & ADC2 clock
Kojto 122:f9eeca106725 3192 * @arg @ref RCC_ADC12PLLCLK_DIV8 PLL clock divided by 8 selected as ADC1 & ADC2 clock
Kojto 122:f9eeca106725 3193 * @arg @ref RCC_ADC12PLLCLK_DIV10 PLL clock divided by 10 selected as ADC1 & ADC2 clock
Kojto 122:f9eeca106725 3194 * @arg @ref RCC_ADC12PLLCLK_DIV12 PLL clock divided by 12 selected as ADC1 & ADC2 clock
Kojto 122:f9eeca106725 3195 * @arg @ref RCC_ADC12PLLCLK_DIV16 PLL clock divided by 16 selected as ADC1 & ADC2 clock
Kojto 122:f9eeca106725 3196 * @arg @ref RCC_ADC12PLLCLK_DIV32 PLL clock divided by 32 selected as ADC1 & ADC2 clock
Kojto 122:f9eeca106725 3197 * @arg @ref RCC_ADC12PLLCLK_DIV64 PLL clock divided by 64 selected as ADC1 & ADC2 clock
Kojto 122:f9eeca106725 3198 * @arg @ref RCC_ADC12PLLCLK_DIV128 PLL clock divided by 128 selected as ADC1 & ADC2 clock
Kojto 122:f9eeca106725 3199 * @arg @ref RCC_ADC12PLLCLK_DIV256 PLL clock divided by 256 selected as ADC1 & ADC2 clock
bogdanm 86:04dd9b1680ae 3200 */
bogdanm 86:04dd9b1680ae 3201 #define __HAL_RCC_ADC12_CONFIG(__ADC12CLKSource__) \
bogdanm 86:04dd9b1680ae 3202 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE12, (uint32_t)(__ADC12CLKSource__))
bogdanm 86:04dd9b1680ae 3203
bogdanm 86:04dd9b1680ae 3204 /** @brief Macro to get the ADC1 & ADC2 clock
bogdanm 86:04dd9b1680ae 3205 * @retval The clock source can be one of the following values:
Kojto 122:f9eeca106725 3206 * @arg @ref RCC_ADC12PLLCLK_OFF ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock
Kojto 122:f9eeca106725 3207 * @arg @ref RCC_ADC12PLLCLK_DIV1 PLL clock divided by 1 selected as ADC1 & ADC2 clock
Kojto 122:f9eeca106725 3208 * @arg @ref RCC_ADC12PLLCLK_DIV2 PLL clock divided by 2 selected as ADC1 & ADC2 clock
Kojto 122:f9eeca106725 3209 * @arg @ref RCC_ADC12PLLCLK_DIV4 PLL clock divided by 4 selected as ADC1 & ADC2 clock
Kojto 122:f9eeca106725 3210 * @arg @ref RCC_ADC12PLLCLK_DIV6 PLL clock divided by 6 selected as ADC1 & ADC2 clock
Kojto 122:f9eeca106725 3211 * @arg @ref RCC_ADC12PLLCLK_DIV8 PLL clock divided by 8 selected as ADC1 & ADC2 clock
Kojto 122:f9eeca106725 3212 * @arg @ref RCC_ADC12PLLCLK_DIV10 PLL clock divided by 10 selected as ADC1 & ADC2 clock
Kojto 122:f9eeca106725 3213 * @arg @ref RCC_ADC12PLLCLK_DIV12 PLL clock divided by 12 selected as ADC1 & ADC2 clock
Kojto 122:f9eeca106725 3214 * @arg @ref RCC_ADC12PLLCLK_DIV16 PLL clock divided by 16 selected as ADC1 & ADC2 clock
Kojto 122:f9eeca106725 3215 * @arg @ref RCC_ADC12PLLCLK_DIV32 PLL clock divided by 32 selected as ADC1 & ADC2 clock
Kojto 122:f9eeca106725 3216 * @arg @ref RCC_ADC12PLLCLK_DIV64 PLL clock divided by 64 selected as ADC1 & ADC2 clock
Kojto 122:f9eeca106725 3217 * @arg @ref RCC_ADC12PLLCLK_DIV128 PLL clock divided by 128 selected as ADC1 & ADC2 clock
Kojto 122:f9eeca106725 3218 * @arg @ref RCC_ADC12PLLCLK_DIV256 PLL clock divided by 256 selected as ADC1 & ADC2 clock
bogdanm 86:04dd9b1680ae 3219 */
bogdanm 86:04dd9b1680ae 3220 #define __HAL_RCC_GET_ADC12_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADCPRE12)))
bogdanm 92:4fc01daae5a5 3221 /**
bogdanm 92:4fc01daae5a5 3222 * @}
bogdanm 92:4fc01daae5a5 3223 */
bogdanm 92:4fc01daae5a5 3224
bogdanm 92:4fc01daae5a5 3225 /** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
bogdanm 92:4fc01daae5a5 3226 * @{
bogdanm 92:4fc01daae5a5 3227 */
bogdanm 86:04dd9b1680ae 3228
bogdanm 86:04dd9b1680ae 3229 /** @brief Macro to configure the TIM1 clock (TIM1CLK).
Kojto 122:f9eeca106725 3230 * @param __TIM1CLKSource__ specifies the TIM1 clock source.
bogdanm 86:04dd9b1680ae 3231 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 3232 * @arg @ref RCC_TIM1CLK_HCLK HCLK selected as TIM1 clock
Kojto 122:f9eeca106725 3233 * @arg @ref RCC_TIM1CLK_PLLCLK PLL Clock selected as TIM1 clock
bogdanm 86:04dd9b1680ae 3234 */
bogdanm 86:04dd9b1680ae 3235 #define __HAL_RCC_TIM1_CONFIG(__TIM1CLKSource__) \
bogdanm 86:04dd9b1680ae 3236 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM1SW, (uint32_t)(__TIM1CLKSource__))
bogdanm 86:04dd9b1680ae 3237
bogdanm 86:04dd9b1680ae 3238 /** @brief Macro to get the TIM1 clock (TIM1CLK).
bogdanm 86:04dd9b1680ae 3239 * @retval The clock source can be one of the following values:
Kojto 122:f9eeca106725 3240 * @arg @ref RCC_TIM1CLK_HCLK HCLK selected as TIM1 clock
Kojto 122:f9eeca106725 3241 * @arg @ref RCC_TIM1CLK_PLLCLK PLL Clock selected as TIM1 clock
bogdanm 86:04dd9b1680ae 3242 */
bogdanm 86:04dd9b1680ae 3243 #define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM1SW)))
bogdanm 92:4fc01daae5a5 3244 /**
bogdanm 92:4fc01daae5a5 3245 * @}
bogdanm 92:4fc01daae5a5 3246 */
bogdanm 92:4fc01daae5a5 3247
bogdanm 92:4fc01daae5a5 3248 /** @defgroup RCCEx_I2Sx_Clock_Config RCC Extended I2Sx Clock Config
bogdanm 92:4fc01daae5a5 3249 * @{
bogdanm 92:4fc01daae5a5 3250 */
bogdanm 86:04dd9b1680ae 3251
bogdanm 86:04dd9b1680ae 3252 /** @brief Macro to configure the I2S clock source (I2SCLK).
bogdanm 86:04dd9b1680ae 3253 * @note This function must be called before enabling the I2S APB clock.
Kojto 122:f9eeca106725 3254 * @param __I2SCLKSource__ specifies the I2S clock source.
bogdanm 86:04dd9b1680ae 3255 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 3256 * @arg @ref RCC_I2SCLKSOURCE_SYSCLK SYSCLK clock used as I2S clock source
Kojto 122:f9eeca106725 3257 * @arg @ref RCC_I2SCLKSOURCE_EXT External clock mapped on the I2S_CKIN pin
bogdanm 86:04dd9b1680ae 3258 * used as I2S clock source
bogdanm 86:04dd9b1680ae 3259 */
bogdanm 86:04dd9b1680ae 3260 #define __HAL_RCC_I2S_CONFIG(__I2SCLKSource__) \
bogdanm 86:04dd9b1680ae 3261 MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, (uint32_t)(__I2SCLKSource__))
bogdanm 86:04dd9b1680ae 3262
bogdanm 86:04dd9b1680ae 3263 /** @brief Macro to get the I2S clock source (I2SCLK).
bogdanm 86:04dd9b1680ae 3264 * @retval The clock source can be one of the following values:
Kojto 122:f9eeca106725 3265 * @arg @ref RCC_I2SCLKSOURCE_SYSCLK SYSCLK clock used as I2S clock source
Kojto 122:f9eeca106725 3266 * @arg @ref RCC_I2SCLKSOURCE_EXT External clock mapped on the I2S_CKIN pin
bogdanm 86:04dd9b1680ae 3267 * used as I2S clock source
bogdanm 86:04dd9b1680ae 3268 */
bogdanm 86:04dd9b1680ae 3269 #define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC)))
bogdanm 92:4fc01daae5a5 3270 /**
bogdanm 92:4fc01daae5a5 3271 * @}
bogdanm 92:4fc01daae5a5 3272 */
bogdanm 92:4fc01daae5a5 3273
bogdanm 92:4fc01daae5a5 3274 /** @defgroup RCCEx_UARTx_Clock_Config RCC Extended UARTx Clock Config
bogdanm 92:4fc01daae5a5 3275 * @{
bogdanm 92:4fc01daae5a5 3276 */
bogdanm 86:04dd9b1680ae 3277
bogdanm 86:04dd9b1680ae 3278 /** @brief Macro to configure the UART4 clock (UART4CLK).
Kojto 122:f9eeca106725 3279 * @param __UART4CLKSource__ specifies the UART4 clock source.
bogdanm 86:04dd9b1680ae 3280 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 3281 * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock
Kojto 122:f9eeca106725 3282 * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock
Kojto 122:f9eeca106725 3283 * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock
Kojto 122:f9eeca106725 3284 * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock
bogdanm 86:04dd9b1680ae 3285 */
bogdanm 86:04dd9b1680ae 3286 #define __HAL_RCC_UART4_CONFIG(__UART4CLKSource__) \
bogdanm 86:04dd9b1680ae 3287 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_UART4SW, (uint32_t)(__UART4CLKSource__))
bogdanm 86:04dd9b1680ae 3288
bogdanm 86:04dd9b1680ae 3289 /** @brief Macro to get the UART4 clock source.
bogdanm 86:04dd9b1680ae 3290 * @retval The clock source can be one of the following values:
Kojto 122:f9eeca106725 3291 * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock
Kojto 122:f9eeca106725 3292 * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock
Kojto 122:f9eeca106725 3293 * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock
Kojto 122:f9eeca106725 3294 * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock
bogdanm 86:04dd9b1680ae 3295 */
bogdanm 86:04dd9b1680ae 3296 #define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_UART4SW)))
bogdanm 86:04dd9b1680ae 3297
bogdanm 86:04dd9b1680ae 3298 /** @brief Macro to configure the UART5 clock (UART5CLK).
Kojto 122:f9eeca106725 3299 * @param __UART5CLKSource__ specifies the UART5 clock source.
bogdanm 86:04dd9b1680ae 3300 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 3301 * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock
Kojto 122:f9eeca106725 3302 * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock
Kojto 122:f9eeca106725 3303 * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock
Kojto 122:f9eeca106725 3304 * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock
bogdanm 86:04dd9b1680ae 3305 */
bogdanm 86:04dd9b1680ae 3306 #define __HAL_RCC_UART5_CONFIG(__UART5CLKSource__) \
bogdanm 86:04dd9b1680ae 3307 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_UART5SW, (uint32_t)(__UART5CLKSource__))
bogdanm 86:04dd9b1680ae 3308
bogdanm 86:04dd9b1680ae 3309 /** @brief Macro to get the UART5 clock source.
bogdanm 86:04dd9b1680ae 3310 * @retval The clock source can be one of the following values:
Kojto 122:f9eeca106725 3311 * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock
Kojto 122:f9eeca106725 3312 * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock
Kojto 122:f9eeca106725 3313 * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock
Kojto 122:f9eeca106725 3314 * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock
bogdanm 86:04dd9b1680ae 3315 */
bogdanm 86:04dd9b1680ae 3316 #define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_UART5SW)))
bogdanm 92:4fc01daae5a5 3317 /**
bogdanm 92:4fc01daae5a5 3318 * @}
bogdanm 92:4fc01daae5a5 3319 */
bogdanm 92:4fc01daae5a5 3320 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
bogdanm 92:4fc01daae5a5 3321 /* STM32F302xC || STM32F303xC || STM32F358xx */
bogdanm 92:4fc01daae5a5 3322
Kojto 122:f9eeca106725 3323 #if defined(STM32F303xE) || defined(STM32F398xx)\
Kojto 122:f9eeca106725 3324 || defined(STM32F303xC) || defined(STM32F358xx)
bogdanm 92:4fc01daae5a5 3325 /** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
bogdanm 92:4fc01daae5a5 3326 * @{
bogdanm 92:4fc01daae5a5 3327 */
bogdanm 86:04dd9b1680ae 3328
bogdanm 86:04dd9b1680ae 3329 /** @brief Macro to configure the ADC3 & ADC4 clock (ADC34CLK).
Kojto 122:f9eeca106725 3330 * @param __ADC34CLKSource__ specifies the ADC3 & ADC4 clock source.
bogdanm 86:04dd9b1680ae 3331 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 3332 * @arg @ref RCC_ADC34PLLCLK_OFF ADC3 & ADC4 PLL clock disabled, ADC3 & ADC4 can use AHB clock
Kojto 122:f9eeca106725 3333 * @arg @ref RCC_ADC34PLLCLK_DIV1 PLL clock divided by 1 selected as ADC3 & ADC4 clock
Kojto 122:f9eeca106725 3334 * @arg @ref RCC_ADC34PLLCLK_DIV2 PLL clock divided by 2 selected as ADC3 & ADC4 clock
Kojto 122:f9eeca106725 3335 * @arg @ref RCC_ADC34PLLCLK_DIV4 PLL clock divided by 4 selected as ADC3 & ADC4 clock
Kojto 122:f9eeca106725 3336 * @arg @ref RCC_ADC34PLLCLK_DIV6 PLL clock divided by 6 selected as ADC3 & ADC4 clock
Kojto 122:f9eeca106725 3337 * @arg @ref RCC_ADC34PLLCLK_DIV8 PLL clock divided by 8 selected as ADC3 & ADC4 clock
Kojto 122:f9eeca106725 3338 * @arg @ref RCC_ADC34PLLCLK_DIV10 PLL clock divided by 10 selected as ADC3 & ADC4 clock
Kojto 122:f9eeca106725 3339 * @arg @ref RCC_ADC34PLLCLK_DIV12 PLL clock divided by 12 selected as ADC3 & ADC4 clock
Kojto 122:f9eeca106725 3340 * @arg @ref RCC_ADC34PLLCLK_DIV16 PLL clock divided by 16 selected as ADC3 & ADC4 clock
Kojto 122:f9eeca106725 3341 * @arg @ref RCC_ADC34PLLCLK_DIV32 PLL clock divided by 32 selected as ADC3 & ADC4 clock
Kojto 122:f9eeca106725 3342 * @arg @ref RCC_ADC34PLLCLK_DIV64 PLL clock divided by 64 selected as ADC3 & ADC4 clock
Kojto 122:f9eeca106725 3343 * @arg @ref RCC_ADC34PLLCLK_DIV128 PLL clock divided by 128 selected as ADC3 & ADC4 clock
Kojto 122:f9eeca106725 3344 * @arg @ref RCC_ADC34PLLCLK_DIV256 PLL clock divided by 256 selected as ADC3 & ADC4 clock
bogdanm 86:04dd9b1680ae 3345 */
bogdanm 86:04dd9b1680ae 3346 #define __HAL_RCC_ADC34_CONFIG(__ADC34CLKSource__) \
bogdanm 86:04dd9b1680ae 3347 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE34, (uint32_t)(__ADC34CLKSource__))
bogdanm 86:04dd9b1680ae 3348
bogdanm 86:04dd9b1680ae 3349 /** @brief Macro to get the ADC3 & ADC4 clock
bogdanm 86:04dd9b1680ae 3350 * @retval The clock source can be one of the following values:
Kojto 122:f9eeca106725 3351 * @arg @ref RCC_ADC34PLLCLK_OFF ADC3 & ADC4 PLL clock disabled, ADC3 & ADC4 can use AHB clock
Kojto 122:f9eeca106725 3352 * @arg @ref RCC_ADC34PLLCLK_DIV1 PLL clock divided by 1 selected as ADC3 & ADC4 clock
Kojto 122:f9eeca106725 3353 * @arg @ref RCC_ADC34PLLCLK_DIV2 PLL clock divided by 2 selected as ADC3 & ADC4 clock
Kojto 122:f9eeca106725 3354 * @arg @ref RCC_ADC34PLLCLK_DIV4 PLL clock divided by 4 selected as ADC3 & ADC4 clock
Kojto 122:f9eeca106725 3355 * @arg @ref RCC_ADC34PLLCLK_DIV6 PLL clock divided by 6 selected as ADC3 & ADC4 clock
Kojto 122:f9eeca106725 3356 * @arg @ref RCC_ADC34PLLCLK_DIV8 PLL clock divided by 8 selected as ADC3 & ADC4 clock
Kojto 122:f9eeca106725 3357 * @arg @ref RCC_ADC34PLLCLK_DIV10 PLL clock divided by 10 selected as ADC3 & ADC4 clock
Kojto 122:f9eeca106725 3358 * @arg @ref RCC_ADC34PLLCLK_DIV12 PLL clock divided by 12 selected as ADC3 & ADC4 clock
Kojto 122:f9eeca106725 3359 * @arg @ref RCC_ADC34PLLCLK_DIV16 PLL clock divided by 16 selected as ADC3 & ADC4 clock
Kojto 122:f9eeca106725 3360 * @arg @ref RCC_ADC34PLLCLK_DIV32 PLL clock divided by 32 selected as ADC3 & ADC4 clock
Kojto 122:f9eeca106725 3361 * @arg @ref RCC_ADC34PLLCLK_DIV64 PLL clock divided by 64 selected as ADC3 & ADC4 clock
Kojto 122:f9eeca106725 3362 * @arg @ref RCC_ADC34PLLCLK_DIV128 PLL clock divided by 128 selected as ADC3 & ADC4 clock
Kojto 122:f9eeca106725 3363 * @arg @ref RCC_ADC34PLLCLK_DIV256 PLL clock divided by 256 selected as ADC3 & ADC4 clock
bogdanm 86:04dd9b1680ae 3364 */
bogdanm 86:04dd9b1680ae 3365 #define __HAL_RCC_GET_ADC34_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADCPRE34)))
bogdanm 92:4fc01daae5a5 3366 /**
bogdanm 92:4fc01daae5a5 3367 * @}
bogdanm 92:4fc01daae5a5 3368 */
bogdanm 92:4fc01daae5a5 3369
bogdanm 92:4fc01daae5a5 3370 /** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
bogdanm 92:4fc01daae5a5 3371 * @{
bogdanm 92:4fc01daae5a5 3372 */
bogdanm 86:04dd9b1680ae 3373
bogdanm 86:04dd9b1680ae 3374 /** @brief Macro to configure the TIM8 clock (TIM8CLK).
Kojto 122:f9eeca106725 3375 * @param __TIM8CLKSource__ specifies the TIM8 clock source.
bogdanm 86:04dd9b1680ae 3376 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 3377 * @arg @ref RCC_TIM8CLK_HCLK HCLK selected as TIM8 clock
Kojto 122:f9eeca106725 3378 * @arg @ref RCC_TIM8CLK_PLLCLK PLL Clock selected as TIM8 clock
bogdanm 86:04dd9b1680ae 3379 */
bogdanm 86:04dd9b1680ae 3380 #define __HAL_RCC_TIM8_CONFIG(__TIM8CLKSource__) \
bogdanm 86:04dd9b1680ae 3381 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM8SW, (uint32_t)(__TIM8CLKSource__))
bogdanm 86:04dd9b1680ae 3382
bogdanm 86:04dd9b1680ae 3383 /** @brief Macro to get the TIM8 clock (TIM8CLK).
bogdanm 86:04dd9b1680ae 3384 * @retval The clock source can be one of the following values:
Kojto 122:f9eeca106725 3385 * @arg @ref RCC_TIM8CLK_HCLK HCLK selected as TIM8 clock
Kojto 122:f9eeca106725 3386 * @arg @ref RCC_TIM8CLK_PLLCLK PLL Clock selected as TIM8 clock
bogdanm 86:04dd9b1680ae 3387 */
bogdanm 86:04dd9b1680ae 3388 #define __HAL_RCC_GET_TIM8_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM8SW)))
bogdanm 86:04dd9b1680ae 3389
bogdanm 92:4fc01daae5a5 3390 /**
bogdanm 92:4fc01daae5a5 3391 * @}
bogdanm 92:4fc01daae5a5 3392 */
bogdanm 92:4fc01daae5a5 3393 #endif /* STM32F303xE || STM32F398xx || */
bogdanm 92:4fc01daae5a5 3394 /* STM32F303xC || STM32F358xx */
bogdanm 86:04dd9b1680ae 3395
bogdanm 86:04dd9b1680ae 3396 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
bogdanm 92:4fc01daae5a5 3397 /** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
bogdanm 92:4fc01daae5a5 3398 * @{
bogdanm 92:4fc01daae5a5 3399 */
bogdanm 86:04dd9b1680ae 3400
bogdanm 86:04dd9b1680ae 3401 /** @brief Macro to configure the ADC1 & ADC2 clock (ADC12CLK).
Kojto 122:f9eeca106725 3402 * @param __ADC12CLKSource__ specifies the ADC1 & ADC2 clock source.
bogdanm 86:04dd9b1680ae 3403 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 3404 * @arg @ref RCC_ADC12PLLCLK_OFF ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock
Kojto 122:f9eeca106725 3405 * @arg @ref RCC_ADC12PLLCLK_DIV1 PLL clock divided by 1 selected as ADC1 & ADC2 clock
Kojto 122:f9eeca106725 3406 * @arg @ref RCC_ADC12PLLCLK_DIV2 PLL clock divided by 2 selected as ADC1 & ADC2 clock
Kojto 122:f9eeca106725 3407 * @arg @ref RCC_ADC12PLLCLK_DIV4 PLL clock divided by 4 selected as ADC1 & ADC2 clock
Kojto 122:f9eeca106725 3408 * @arg @ref RCC_ADC12PLLCLK_DIV6 PLL clock divided by 6 selected as ADC1 & ADC2 clock
Kojto 122:f9eeca106725 3409 * @arg @ref RCC_ADC12PLLCLK_DIV8 PLL clock divided by 8 selected as ADC1 & ADC2 clock
Kojto 122:f9eeca106725 3410 * @arg @ref RCC_ADC12PLLCLK_DIV10 PLL clock divided by 10 selected as ADC1 & ADC2 clock
Kojto 122:f9eeca106725 3411 * @arg @ref RCC_ADC12PLLCLK_DIV12 PLL clock divided by 12 selected as ADC1 & ADC2 clock
Kojto 122:f9eeca106725 3412 * @arg @ref RCC_ADC12PLLCLK_DIV16 PLL clock divided by 16 selected as ADC1 & ADC2 clock
Kojto 122:f9eeca106725 3413 * @arg @ref RCC_ADC12PLLCLK_DIV32 PLL clock divided by 32 selected as ADC1 & ADC2 clock
Kojto 122:f9eeca106725 3414 * @arg @ref RCC_ADC12PLLCLK_DIV64 PLL clock divided by 64 selected as ADC1 & ADC2 clock
Kojto 122:f9eeca106725 3415 * @arg @ref RCC_ADC12PLLCLK_DIV128 PLL clock divided by 128 selected as ADC1 & ADC2 clock
Kojto 122:f9eeca106725 3416 * @arg @ref RCC_ADC12PLLCLK_DIV256 PLL clock divided by 256 selected as ADC1 & ADC2 clock
bogdanm 86:04dd9b1680ae 3417 */
bogdanm 86:04dd9b1680ae 3418 #define __HAL_RCC_ADC12_CONFIG(__ADC12CLKSource__) \
bogdanm 86:04dd9b1680ae 3419 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE12, (uint32_t)(__ADC12CLKSource__))
bogdanm 86:04dd9b1680ae 3420
bogdanm 86:04dd9b1680ae 3421 /** @brief Macro to get the ADC1 & ADC2 clock
bogdanm 86:04dd9b1680ae 3422 * @retval The clock source can be one of the following values:
Kojto 122:f9eeca106725 3423 * @arg @ref RCC_ADC12PLLCLK_OFF ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock
Kojto 122:f9eeca106725 3424 * @arg @ref RCC_ADC12PLLCLK_DIV1 PLL clock divided by 1 selected as ADC1 & ADC2 clock
Kojto 122:f9eeca106725 3425 * @arg @ref RCC_ADC12PLLCLK_DIV2 PLL clock divided by 2 selected as ADC1 & ADC2 clock
Kojto 122:f9eeca106725 3426 * @arg @ref RCC_ADC12PLLCLK_DIV4 PLL clock divided by 4 selected as ADC1 & ADC2 clock
Kojto 122:f9eeca106725 3427 * @arg @ref RCC_ADC12PLLCLK_DIV6 PLL clock divided by 6 selected as ADC1 & ADC2 clock
Kojto 122:f9eeca106725 3428 * @arg @ref RCC_ADC12PLLCLK_DIV8 PLL clock divided by 8 selected as ADC1 & ADC2 clock
Kojto 122:f9eeca106725 3429 * @arg @ref RCC_ADC12PLLCLK_DIV10 PLL clock divided by 10 selected as ADC1 & ADC2 clock
Kojto 122:f9eeca106725 3430 * @arg @ref RCC_ADC12PLLCLK_DIV12 PLL clock divided by 12 selected as ADC1 & ADC2 clock
Kojto 122:f9eeca106725 3431 * @arg @ref RCC_ADC12PLLCLK_DIV16 PLL clock divided by 16 selected as ADC1 & ADC2 clock
Kojto 122:f9eeca106725 3432 * @arg @ref RCC_ADC12PLLCLK_DIV32 PLL clock divided by 32 selected as ADC1 & ADC2 clock
Kojto 122:f9eeca106725 3433 * @arg @ref RCC_ADC12PLLCLK_DIV64 PLL clock divided by 64 selected as ADC1 & ADC2 clock
Kojto 122:f9eeca106725 3434 * @arg @ref RCC_ADC12PLLCLK_DIV128 PLL clock divided by 128 selected as ADC1 & ADC2 clock
Kojto 122:f9eeca106725 3435 * @arg @ref RCC_ADC12PLLCLK_DIV256 PLL clock divided by 256 selected as ADC1 & ADC2 clock
bogdanm 86:04dd9b1680ae 3436 */
bogdanm 86:04dd9b1680ae 3437 #define __HAL_RCC_GET_ADC12_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADCPRE12)))
bogdanm 92:4fc01daae5a5 3438 /**
bogdanm 92:4fc01daae5a5 3439 * @}
bogdanm 92:4fc01daae5a5 3440 */
bogdanm 92:4fc01daae5a5 3441
bogdanm 92:4fc01daae5a5 3442 /** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
bogdanm 92:4fc01daae5a5 3443 * @{
bogdanm 92:4fc01daae5a5 3444 */
bogdanm 86:04dd9b1680ae 3445 /** @brief Macro to configure the TIM1 clock (TIM1CLK).
Kojto 122:f9eeca106725 3446 * @param __TIM1CLKSource__ specifies the TIM1 clock source.
bogdanm 86:04dd9b1680ae 3447 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 3448 * @arg @ref RCC_TIM1CLK_HCLK HCLK selected as TIM1 clock
Kojto 122:f9eeca106725 3449 * @arg @ref RCC_TIM1CLK_PLLCLK PLL Clock selected as TIM1 clock
bogdanm 86:04dd9b1680ae 3450 */
bogdanm 86:04dd9b1680ae 3451 #define __HAL_RCC_TIM1_CONFIG(__TIM1CLKSource__) \
bogdanm 86:04dd9b1680ae 3452 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM1SW, (uint32_t)(__TIM1CLKSource__))
bogdanm 86:04dd9b1680ae 3453
bogdanm 86:04dd9b1680ae 3454 /** @brief Macro to get the TIM1 clock (TIM1CLK).
bogdanm 86:04dd9b1680ae 3455 * @retval The clock source can be one of the following values:
Kojto 122:f9eeca106725 3456 * @arg @ref RCC_TIM1CLK_HCLK HCLK selected as TIM1 clock
Kojto 122:f9eeca106725 3457 * @arg @ref RCC_TIM1CLK_PLLCLK PLL Clock selected as TIM1 clock
bogdanm 86:04dd9b1680ae 3458 */
bogdanm 86:04dd9b1680ae 3459 #define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM1SW)))
bogdanm 92:4fc01daae5a5 3460 /**
bogdanm 92:4fc01daae5a5 3461 * @}
bogdanm 92:4fc01daae5a5 3462 */
bogdanm 86:04dd9b1680ae 3463 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
bogdanm 86:04dd9b1680ae 3464
bogdanm 86:04dd9b1680ae 3465 #if defined(STM32F334x8)
bogdanm 92:4fc01daae5a5 3466 /** @defgroup RCCEx_HRTIMx_Clock_Config RCC Extended HRTIMx Clock Config
bogdanm 92:4fc01daae5a5 3467 * @{
bogdanm 92:4fc01daae5a5 3468 */
bogdanm 86:04dd9b1680ae 3469 /** @brief Macro to configure the HRTIM1 clock.
Kojto 122:f9eeca106725 3470 * @param __HRTIM1CLKSource__ specifies the HRTIM1 clock source.
bogdanm 86:04dd9b1680ae 3471 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 3472 * @arg @ref RCC_HRTIM1CLK_HCLK HCLK selected as HRTIM1 clock
Kojto 122:f9eeca106725 3473 * @arg @ref RCC_HRTIM1CLK_PLLCLK PLL Clock selected as HRTIM1 clock
bogdanm 86:04dd9b1680ae 3474 */
bogdanm 86:04dd9b1680ae 3475 #define __HAL_RCC_HRTIM1_CONFIG(__HRTIM1CLKSource__) \
bogdanm 86:04dd9b1680ae 3476 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_HRTIM1SW, (uint32_t)(__HRTIM1CLKSource__))
bogdanm 86:04dd9b1680ae 3477
bogdanm 86:04dd9b1680ae 3478 /** @brief Macro to get the HRTIM1 clock source.
bogdanm 86:04dd9b1680ae 3479 * @retval The clock source can be one of the following values:
Kojto 122:f9eeca106725 3480 * @arg @ref RCC_HRTIM1CLK_HCLK HCLK selected as HRTIM1 clock
Kojto 122:f9eeca106725 3481 * @arg @ref RCC_HRTIM1CLK_PLLCLK PLL Clock selected as HRTIM1 clock
bogdanm 86:04dd9b1680ae 3482 */
bogdanm 86:04dd9b1680ae 3483 #define __HAL_RCC_GET_HRTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_HRTIM1SW)))
bogdanm 92:4fc01daae5a5 3484 /**
bogdanm 92:4fc01daae5a5 3485 * @}
bogdanm 92:4fc01daae5a5 3486 */
bogdanm 86:04dd9b1680ae 3487 #endif /* STM32F334x8 */
bogdanm 86:04dd9b1680ae 3488
bogdanm 86:04dd9b1680ae 3489 #if defined(STM32F373xC) || defined(STM32F378xx)
bogdanm 92:4fc01daae5a5 3490 /** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config
bogdanm 92:4fc01daae5a5 3491 * @{
bogdanm 92:4fc01daae5a5 3492 */
bogdanm 86:04dd9b1680ae 3493 /** @brief Macro to configure the I2C2 clock (I2C2CLK).
Kojto 122:f9eeca106725 3494 * @param __I2C2CLKSource__ specifies the I2C2 clock source.
bogdanm 86:04dd9b1680ae 3495 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 3496 * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
Kojto 122:f9eeca106725 3497 * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
bogdanm 86:04dd9b1680ae 3498 */
bogdanm 86:04dd9b1680ae 3499 #define __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) \
bogdanm 86:04dd9b1680ae 3500 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C2SW, (uint32_t)(__I2C2CLKSource__))
bogdanm 86:04dd9b1680ae 3501
bogdanm 86:04dd9b1680ae 3502 /** @brief Macro to get the I2C2 clock source.
bogdanm 86:04dd9b1680ae 3503 * @retval The clock source can be one of the following values:
Kojto 122:f9eeca106725 3504 * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
Kojto 122:f9eeca106725 3505 * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
bogdanm 86:04dd9b1680ae 3506 */
bogdanm 86:04dd9b1680ae 3507 #define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C2SW)))
bogdanm 92:4fc01daae5a5 3508 /**
bogdanm 92:4fc01daae5a5 3509 * @}
bogdanm 92:4fc01daae5a5 3510 */
bogdanm 92:4fc01daae5a5 3511
bogdanm 92:4fc01daae5a5 3512 /** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
bogdanm 92:4fc01daae5a5 3513 * @{
bogdanm 92:4fc01daae5a5 3514 */
bogdanm 86:04dd9b1680ae 3515 /** @brief Macro to configure the ADC1 clock (ADC1CLK).
Kojto 122:f9eeca106725 3516 * @param __ADC1CLKSource__ specifies the ADC1 clock source.
bogdanm 86:04dd9b1680ae 3517 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 3518 * @arg @ref RCC_ADC1PCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC1 clock
Kojto 122:f9eeca106725 3519 * @arg @ref RCC_ADC1PCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC1 clock
Kojto 122:f9eeca106725 3520 * @arg @ref RCC_ADC1PCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC1 clock
Kojto 122:f9eeca106725 3521 * @arg @ref RCC_ADC1PCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC1 clock
bogdanm 86:04dd9b1680ae 3522 */
bogdanm 86:04dd9b1680ae 3523 #define __HAL_RCC_ADC1_CONFIG(__ADC1CLKSource__) \
bogdanm 86:04dd9b1680ae 3524 MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, (uint32_t)(__ADC1CLKSource__))
bogdanm 86:04dd9b1680ae 3525
bogdanm 86:04dd9b1680ae 3526 /** @brief Macro to get the ADC1 clock (ADC1CLK).
bogdanm 86:04dd9b1680ae 3527 * @retval The clock source can be one of the following values:
Kojto 122:f9eeca106725 3528 * @arg @ref RCC_ADC1PCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC1 clock
Kojto 122:f9eeca106725 3529 * @arg @ref RCC_ADC1PCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC1 clock
Kojto 122:f9eeca106725 3530 * @arg @ref RCC_ADC1PCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC1 clock
Kojto 122:f9eeca106725 3531 * @arg @ref RCC_ADC1PCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC1 clock
bogdanm 86:04dd9b1680ae 3532 */
bogdanm 86:04dd9b1680ae 3533 #define __HAL_RCC_GET_ADC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_ADCPRE)))
bogdanm 92:4fc01daae5a5 3534 /**
bogdanm 92:4fc01daae5a5 3535 * @}
bogdanm 92:4fc01daae5a5 3536 */
bogdanm 92:4fc01daae5a5 3537
bogdanm 92:4fc01daae5a5 3538 /** @defgroup RCCEx_SDADCx_Clock_Config RCC Extended SDADCx Clock Config
bogdanm 92:4fc01daae5a5 3539 * @{
bogdanm 92:4fc01daae5a5 3540 */
bogdanm 86:04dd9b1680ae 3541 /** @brief Macro to configure the SDADCx clock (SDADCxCLK).
Kojto 122:f9eeca106725 3542 * @param __SDADCPrescaler__ specifies the SDADCx system clock prescaler.
bogdanm 86:04dd9b1680ae 3543 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 3544 * @arg @ref RCC_SDADCSYSCLK_DIV1 SYSCLK clock selected as SDADCx clock
Kojto 122:f9eeca106725 3545 * @arg @ref RCC_SDADCSYSCLK_DIV2 SYSCLK clock divided by 2 selected as SDADCx clock
Kojto 122:f9eeca106725 3546 * @arg @ref RCC_SDADCSYSCLK_DIV4 SYSCLK clock divided by 4 selected as SDADCx clock
Kojto 122:f9eeca106725 3547 * @arg @ref RCC_SDADCSYSCLK_DIV6 SYSCLK clock divided by 6 selected as SDADCx clock
Kojto 122:f9eeca106725 3548 * @arg @ref RCC_SDADCSYSCLK_DIV8 SYSCLK clock divided by 8 selected as SDADCx clock
Kojto 122:f9eeca106725 3549 * @arg @ref RCC_SDADCSYSCLK_DIV10 SYSCLK clock divided by 10 selected as SDADCx clock
Kojto 122:f9eeca106725 3550 * @arg @ref RCC_SDADCSYSCLK_DIV12 SYSCLK clock divided by 12 selected as SDADCx clock
Kojto 122:f9eeca106725 3551 * @arg @ref RCC_SDADCSYSCLK_DIV14 SYSCLK clock divided by 14 selected as SDADCx clock
Kojto 122:f9eeca106725 3552 * @arg @ref RCC_SDADCSYSCLK_DIV16 SYSCLK clock divided by 16 selected as SDADCx clock
Kojto 122:f9eeca106725 3553 * @arg @ref RCC_SDADCSYSCLK_DIV20 SYSCLK clock divided by 20 selected as SDADCx clock
Kojto 122:f9eeca106725 3554 * @arg @ref RCC_SDADCSYSCLK_DIV24 SYSCLK clock divided by 24 selected as SDADCx clock
Kojto 122:f9eeca106725 3555 * @arg @ref RCC_SDADCSYSCLK_DIV28 SYSCLK clock divided by 28 selected as SDADCx clock
Kojto 122:f9eeca106725 3556 * @arg @ref RCC_SDADCSYSCLK_DIV32 SYSCLK clock divided by 32 selected as SDADCx clock
Kojto 122:f9eeca106725 3557 * @arg @ref RCC_SDADCSYSCLK_DIV36 SYSCLK clock divided by 36 selected as SDADCx clock
Kojto 122:f9eeca106725 3558 * @arg @ref RCC_SDADCSYSCLK_DIV40 SYSCLK clock divided by 40 selected as SDADCx clock
Kojto 122:f9eeca106725 3559 * @arg @ref RCC_SDADCSYSCLK_DIV44 SYSCLK clock divided by 44 selected as SDADCx clock
Kojto 122:f9eeca106725 3560 * @arg @ref RCC_SDADCSYSCLK_DIV48 SYSCLK clock divided by 48 selected as SDADCx clock
bogdanm 86:04dd9b1680ae 3561 */
bogdanm 86:04dd9b1680ae 3562 #define __HAL_RCC_SDADC_CONFIG(__SDADCPrescaler__) \
bogdanm 86:04dd9b1680ae 3563 MODIFY_REG(RCC->CFGR, RCC_CFGR_SDADCPRE, (uint32_t)(__SDADCPrescaler__))
bogdanm 86:04dd9b1680ae 3564
bogdanm 86:04dd9b1680ae 3565 /** @brief Macro to get the SDADCx clock prescaler.
bogdanm 86:04dd9b1680ae 3566 * @retval The clock source can be one of the following values:
Kojto 122:f9eeca106725 3567 * @arg @ref RCC_SDADCSYSCLK_DIV1 SYSCLK clock selected as SDADCx clock
Kojto 122:f9eeca106725 3568 * @arg @ref RCC_SDADCSYSCLK_DIV2 SYSCLK clock divided by 2 selected as SDADCx clock
Kojto 122:f9eeca106725 3569 * @arg @ref RCC_SDADCSYSCLK_DIV4 SYSCLK clock divided by 4 selected as SDADCx clock
Kojto 122:f9eeca106725 3570 * @arg @ref RCC_SDADCSYSCLK_DIV6 SYSCLK clock divided by 6 selected as SDADCx clock
Kojto 122:f9eeca106725 3571 * @arg @ref RCC_SDADCSYSCLK_DIV8 SYSCLK clock divided by 8 selected as SDADCx clock
Kojto 122:f9eeca106725 3572 * @arg @ref RCC_SDADCSYSCLK_DIV10 SYSCLK clock divided by 10 selected as SDADCx clock
Kojto 122:f9eeca106725 3573 * @arg @ref RCC_SDADCSYSCLK_DIV12 SYSCLK clock divided by 12 selected as SDADCx clock
Kojto 122:f9eeca106725 3574 * @arg @ref RCC_SDADCSYSCLK_DIV14 SYSCLK clock divided by 14 selected as SDADCx clock
Kojto 122:f9eeca106725 3575 * @arg @ref RCC_SDADCSYSCLK_DIV16 SYSCLK clock divided by 16 selected as SDADCx clock
Kojto 122:f9eeca106725 3576 * @arg @ref RCC_SDADCSYSCLK_DIV20 SYSCLK clock divided by 20 selected as SDADCx clock
Kojto 122:f9eeca106725 3577 * @arg @ref RCC_SDADCSYSCLK_DIV24 SYSCLK clock divided by 24 selected as SDADCx clock
Kojto 122:f9eeca106725 3578 * @arg @ref RCC_SDADCSYSCLK_DIV28 SYSCLK clock divided by 28 selected as SDADCx clock
Kojto 122:f9eeca106725 3579 * @arg @ref RCC_SDADCSYSCLK_DIV32 SYSCLK clock divided by 32 selected as SDADCx clock
Kojto 122:f9eeca106725 3580 * @arg @ref RCC_SDADCSYSCLK_DIV36 SYSCLK clock divided by 36 selected as SDADCx clock
Kojto 122:f9eeca106725 3581 * @arg @ref RCC_SDADCSYSCLK_DIV40 SYSCLK clock divided by 40 selected as SDADCx clock
Kojto 122:f9eeca106725 3582 * @arg @ref RCC_SDADCSYSCLK_DIV44 SYSCLK clock divided by 44 selected as SDADCx clock
Kojto 122:f9eeca106725 3583 * @arg @ref RCC_SDADCSYSCLK_DIV48 SYSCLK clock divided by 48 selected as SDADCx clock
bogdanm 86:04dd9b1680ae 3584 */
bogdanm 86:04dd9b1680ae 3585 #define __HAL_RCC_GET_SDADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SDADCPRE)))
bogdanm 92:4fc01daae5a5 3586 /**
bogdanm 92:4fc01daae5a5 3587 * @}
bogdanm 92:4fc01daae5a5 3588 */
bogdanm 92:4fc01daae5a5 3589
bogdanm 92:4fc01daae5a5 3590 /** @defgroup RCCEx_CECx_Clock_Config RCC Extended CECx Clock Config
bogdanm 92:4fc01daae5a5 3591 * @{
bogdanm 92:4fc01daae5a5 3592 */
bogdanm 86:04dd9b1680ae 3593 /** @brief Macro to configure the CEC clock.
Kojto 122:f9eeca106725 3594 * @param __CECCLKSource__ specifies the CEC clock source.
bogdanm 86:04dd9b1680ae 3595 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 3596 * @arg @ref RCC_CECCLKSOURCE_HSI HSI selected as CEC clock
Kojto 122:f9eeca106725 3597 * @arg @ref RCC_CECCLKSOURCE_LSE LSE selected as CEC clock
bogdanm 86:04dd9b1680ae 3598 */
bogdanm 86:04dd9b1680ae 3599 #define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \
bogdanm 86:04dd9b1680ae 3600 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, (uint32_t)(__CECCLKSource__))
bogdanm 86:04dd9b1680ae 3601
bogdanm 86:04dd9b1680ae 3602 /** @brief Macro to get the HDMI CEC clock source.
bogdanm 86:04dd9b1680ae 3603 * @retval The clock source can be one of the following values:
Kojto 122:f9eeca106725 3604 * @arg @ref RCC_CECCLKSOURCE_HSI HSI selected as CEC clock
Kojto 122:f9eeca106725 3605 * @arg @ref RCC_CECCLKSOURCE_LSE LSE selected as CEC clock
bogdanm 86:04dd9b1680ae 3606 */
bogdanm 86:04dd9b1680ae 3607 #define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_CECSW)))
bogdanm 92:4fc01daae5a5 3608 /**
bogdanm 92:4fc01daae5a5 3609 * @}
bogdanm 92:4fc01daae5a5 3610 */
bogdanm 86:04dd9b1680ae 3611
bogdanm 86:04dd9b1680ae 3612 #endif /* STM32F373xC || STM32F378xx */
bogdanm 86:04dd9b1680ae 3613
Kojto 122:f9eeca106725 3614 #if defined(STM32F302xE) || defined(STM32F303xE)\
Kojto 122:f9eeca106725 3615 || defined(STM32F302xC) || defined(STM32F303xC)\
Kojto 122:f9eeca106725 3616 || defined(STM32F302x8) \
Kojto 122:f9eeca106725 3617 || defined(STM32F373xC)
bogdanm 92:4fc01daae5a5 3618
bogdanm 92:4fc01daae5a5 3619 /** @defgroup RCCEx_USBx_Clock_Config RCC Extended USBx Clock Config
bogdanm 92:4fc01daae5a5 3620 * @{
bogdanm 92:4fc01daae5a5 3621 */
bogdanm 86:04dd9b1680ae 3622 /** @brief Macro to configure the USB clock (USBCLK).
Kojto 122:f9eeca106725 3623 * @param __USBCLKSource__ specifies the USB clock source.
bogdanm 86:04dd9b1680ae 3624 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 3625 * @arg @ref RCC_USBCLKSOURCE_PLL PLL Clock divided by 1 selected as USB clock
Kojto 122:f9eeca106725 3626 * @arg @ref RCC_USBCLKSOURCE_PLL_DIV1_5 PLL Clock divided by 1.5 selected as USB clock
bogdanm 86:04dd9b1680ae 3627 */
bogdanm 86:04dd9b1680ae 3628 #define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \
bogdanm 86:04dd9b1680ae 3629 MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, (uint32_t)(__USBCLKSource__))
bogdanm 86:04dd9b1680ae 3630
bogdanm 86:04dd9b1680ae 3631 /** @brief Macro to get the USB clock source.
bogdanm 86:04dd9b1680ae 3632 * @retval The clock source can be one of the following values:
Kojto 122:f9eeca106725 3633 * @arg @ref RCC_USBCLKSOURCE_PLL PLL Clock divided by 1 selected as USB clock
Kojto 122:f9eeca106725 3634 * @arg @ref RCC_USBCLKSOURCE_PLL_DIV1_5 PLL Clock divided by 1.5 selected as USB clock
bogdanm 86:04dd9b1680ae 3635 */
bogdanm 86:04dd9b1680ae 3636 #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_USBPRE)))
bogdanm 92:4fc01daae5a5 3637 /**
bogdanm 92:4fc01daae5a5 3638 * @}
bogdanm 92:4fc01daae5a5 3639 */
bogdanm 92:4fc01daae5a5 3640
bogdanm 92:4fc01daae5a5 3641 #endif /* STM32F302xE || STM32F303xE || */
bogdanm 92:4fc01daae5a5 3642 /* STM32F302xC || STM32F303xC || */
bogdanm 92:4fc01daae5a5 3643 /* STM32F302x8 || */
bogdanm 92:4fc01daae5a5 3644 /* STM32F373xC */
bogdanm 92:4fc01daae5a5 3645
bogdanm 92:4fc01daae5a5 3646 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
bogdanm 92:4fc01daae5a5 3647
bogdanm 92:4fc01daae5a5 3648 /** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config
bogdanm 92:4fc01daae5a5 3649 * @{
bogdanm 92:4fc01daae5a5 3650 */
bogdanm 92:4fc01daae5a5 3651 /** @brief Macro to configure the I2C3 clock (I2C3CLK).
Kojto 122:f9eeca106725 3652 * @param __I2C3CLKSource__ specifies the I2C3 clock source.
bogdanm 92:4fc01daae5a5 3653 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 3654 * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock
Kojto 122:f9eeca106725 3655 * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock
bogdanm 92:4fc01daae5a5 3656 */
bogdanm 92:4fc01daae5a5 3657 #define __HAL_RCC_I2C3_CONFIG(__I2C3CLKSource__) \
bogdanm 92:4fc01daae5a5 3658 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C3SW, (uint32_t)(__I2C3CLKSource__))
bogdanm 92:4fc01daae5a5 3659
bogdanm 92:4fc01daae5a5 3660 /** @brief Macro to get the I2C3 clock source.
bogdanm 92:4fc01daae5a5 3661 * @retval The clock source can be one of the following values:
Kojto 122:f9eeca106725 3662 * @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock
Kojto 122:f9eeca106725 3663 * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock
bogdanm 92:4fc01daae5a5 3664 */
bogdanm 92:4fc01daae5a5 3665 #define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C3SW)))
bogdanm 92:4fc01daae5a5 3666 /**
bogdanm 92:4fc01daae5a5 3667 * @}
bogdanm 92:4fc01daae5a5 3668 */
bogdanm 92:4fc01daae5a5 3669
bogdanm 92:4fc01daae5a5 3670 /** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
bogdanm 92:4fc01daae5a5 3671 * @{
bogdanm 92:4fc01daae5a5 3672 */
bogdanm 92:4fc01daae5a5 3673 /** @brief Macro to configure the TIM2 clock (TIM2CLK).
Kojto 122:f9eeca106725 3674 * @param __TIM2CLKSource__ specifies the TIM2 clock source.
bogdanm 92:4fc01daae5a5 3675 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 3676 * @arg @ref RCC_TIM2CLK_HCLK HCLK selected as TIM2 clock
Kojto 122:f9eeca106725 3677 * @arg @ref RCC_TIM2CLK_PLL PLL Clock selected as TIM2 clock
bogdanm 92:4fc01daae5a5 3678 */
bogdanm 92:4fc01daae5a5 3679 #define __HAL_RCC_TIM2_CONFIG(__TIM2CLKSource__) \
bogdanm 92:4fc01daae5a5 3680 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM2SW, (uint32_t)(__TIM2CLKSource__))
bogdanm 92:4fc01daae5a5 3681
bogdanm 92:4fc01daae5a5 3682 /** @brief Macro to get the TIM2 clock (TIM2CLK).
bogdanm 92:4fc01daae5a5 3683 * @retval The clock source can be one of the following values:
Kojto 122:f9eeca106725 3684 * @arg @ref RCC_TIM2CLK_HCLK HCLK selected as TIM2 clock
Kojto 122:f9eeca106725 3685 * @arg @ref RCC_TIM2CLK_PLL PLL Clock selected as TIM2 clock
bogdanm 92:4fc01daae5a5 3686 */
bogdanm 92:4fc01daae5a5 3687 #define __HAL_RCC_GET_TIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM2SW)))
bogdanm 92:4fc01daae5a5 3688
bogdanm 92:4fc01daae5a5 3689 /** @brief Macro to configure the TIM3 & TIM4 clock (TIM34CLK).
Kojto 122:f9eeca106725 3690 * @param __TIM34CLKSource__ specifies the TIM3 & TIM4 clock source.
bogdanm 92:4fc01daae5a5 3691 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 3692 * @arg @ref RCC_TIM34CLK_HCLK HCLK selected as TIM3 & TIM4 clock
Kojto 122:f9eeca106725 3693 * @arg @ref RCC_TIM34CLK_PLL PLL Clock selected as TIM3 & TIM4 clock
bogdanm 92:4fc01daae5a5 3694 */
bogdanm 92:4fc01daae5a5 3695 #define __HAL_RCC_TIM34_CONFIG(__TIM34CLKSource__) \
bogdanm 92:4fc01daae5a5 3696 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM34SW, (uint32_t)(__TIM34CLKSource__))
bogdanm 92:4fc01daae5a5 3697
bogdanm 92:4fc01daae5a5 3698 /** @brief Macro to get the TIM3 & TIM4 clock (TIM34CLK).
bogdanm 92:4fc01daae5a5 3699 * @retval The clock source can be one of the following values:
Kojto 122:f9eeca106725 3700 * @arg @ref RCC_TIM34CLK_HCLK HCLK selected as TIM3 & TIM4 clock
Kojto 122:f9eeca106725 3701 * @arg @ref RCC_TIM34CLK_PLL PLL Clock selected as TIM3 & TIM4 clock
bogdanm 92:4fc01daae5a5 3702 */
bogdanm 92:4fc01daae5a5 3703 #define __HAL_RCC_GET_TIM34_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM34SW)))
bogdanm 92:4fc01daae5a5 3704
bogdanm 92:4fc01daae5a5 3705 /** @brief Macro to configure the TIM15 clock (TIM15CLK).
Kojto 122:f9eeca106725 3706 * @param __TIM15CLKSource__ specifies the TIM15 clock source.
bogdanm 92:4fc01daae5a5 3707 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 3708 * @arg @ref RCC_TIM15CLK_HCLK HCLK selected as TIM15 clock
Kojto 122:f9eeca106725 3709 * @arg @ref RCC_TIM15CLK_PLL PLL Clock selected as TIM15 clock
bogdanm 92:4fc01daae5a5 3710 */
bogdanm 92:4fc01daae5a5 3711 #define __HAL_RCC_TIM15_CONFIG(__TIM15CLKSource__) \
bogdanm 92:4fc01daae5a5 3712 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM15SW, (uint32_t)(__TIM15CLKSource__))
bogdanm 92:4fc01daae5a5 3713
bogdanm 92:4fc01daae5a5 3714 /** @brief Macro to get the TIM15 clock (TIM15CLK).
bogdanm 92:4fc01daae5a5 3715 * @retval The clock source can be one of the following values:
Kojto 122:f9eeca106725 3716 * @arg @ref RCC_TIM15CLK_HCLK HCLK selected as TIM15 clock
Kojto 122:f9eeca106725 3717 * @arg @ref RCC_TIM15CLK_PLL PLL Clock selected as TIM15 clock
bogdanm 92:4fc01daae5a5 3718 */
bogdanm 92:4fc01daae5a5 3719 #define __HAL_RCC_GET_TIM15_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM15SW)))
bogdanm 92:4fc01daae5a5 3720
bogdanm 92:4fc01daae5a5 3721 /** @brief Macro to configure the TIM16 clock (TIM16CLK).
Kojto 122:f9eeca106725 3722 * @param __TIM16CLKSource__ specifies the TIM16 clock source.
bogdanm 92:4fc01daae5a5 3723 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 3724 * @arg @ref RCC_TIM16CLK_HCLK HCLK selected as TIM16 clock
Kojto 122:f9eeca106725 3725 * @arg @ref RCC_TIM16CLK_PLL PLL Clock selected as TIM16 clock
bogdanm 92:4fc01daae5a5 3726 */
bogdanm 92:4fc01daae5a5 3727 #define __HAL_RCC_TIM16_CONFIG(__TIM16CLKSource__) \
bogdanm 92:4fc01daae5a5 3728 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM16SW, (uint32_t)(__TIM16CLKSource__))
bogdanm 92:4fc01daae5a5 3729
bogdanm 92:4fc01daae5a5 3730 /** @brief Macro to get the TIM16 clock (TIM16CLK).
bogdanm 92:4fc01daae5a5 3731 * @retval The clock source can be one of the following values:
Kojto 122:f9eeca106725 3732 * @arg @ref RCC_TIM16CLK_HCLK HCLK selected as TIM16 clock
Kojto 122:f9eeca106725 3733 * @arg @ref RCC_TIM16CLK_PLL PLL Clock selected as TIM16 clock
bogdanm 92:4fc01daae5a5 3734 */
bogdanm 92:4fc01daae5a5 3735 #define __HAL_RCC_GET_TIM16_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM16SW)))
bogdanm 92:4fc01daae5a5 3736
bogdanm 92:4fc01daae5a5 3737 /** @brief Macro to configure the TIM17 clock (TIM17CLK).
Kojto 122:f9eeca106725 3738 * @param __TIM17CLKSource__ specifies the TIM17 clock source.
bogdanm 92:4fc01daae5a5 3739 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 3740 * @arg @ref RCC_TIM17CLK_HCLK HCLK selected as TIM17 clock
Kojto 122:f9eeca106725 3741 * @arg @ref RCC_TIM17CLK_PLL PLL Clock selected as TIM17 clock
bogdanm 92:4fc01daae5a5 3742 */
bogdanm 92:4fc01daae5a5 3743 #define __HAL_RCC_TIM17_CONFIG(__TIM17CLKSource__) \
bogdanm 92:4fc01daae5a5 3744 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM17SW, (uint32_t)(__TIM17CLKSource__))
bogdanm 92:4fc01daae5a5 3745
bogdanm 92:4fc01daae5a5 3746 /** @brief Macro to get the TIM17 clock (TIM17CLK).
bogdanm 92:4fc01daae5a5 3747 * @retval The clock source can be one of the following values:
Kojto 122:f9eeca106725 3748 * @arg @ref RCC_TIM17CLK_HCLK HCLK selected as TIM17 clock
Kojto 122:f9eeca106725 3749 * @arg @ref RCC_TIM17CLK_PLL PLL Clock selected as TIM17 clock
bogdanm 92:4fc01daae5a5 3750 */
bogdanm 92:4fc01daae5a5 3751 #define __HAL_RCC_GET_TIM17_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM17SW)))
bogdanm 92:4fc01daae5a5 3752
bogdanm 92:4fc01daae5a5 3753 /**
bogdanm 92:4fc01daae5a5 3754 * @}
bogdanm 92:4fc01daae5a5 3755 */
bogdanm 92:4fc01daae5a5 3756
bogdanm 92:4fc01daae5a5 3757 #endif /* STM32f302xE || STM32f303xE || STM32F398xx */
bogdanm 92:4fc01daae5a5 3758
bogdanm 92:4fc01daae5a5 3759 #if defined(STM32F303xE) || defined(STM32F398xx)
bogdanm 92:4fc01daae5a5 3760 /** @addtogroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
bogdanm 92:4fc01daae5a5 3761 * @{
bogdanm 92:4fc01daae5a5 3762 */
bogdanm 92:4fc01daae5a5 3763 /** @brief Macro to configure the TIM20 clock (TIM20CLK).
Kojto 122:f9eeca106725 3764 * @param __TIM20CLKSource__ specifies the TIM20 clock source.
bogdanm 92:4fc01daae5a5 3765 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 3766 * @arg @ref RCC_TIM20CLK_HCLK HCLK selected as TIM20 clock
Kojto 122:f9eeca106725 3767 * @arg @ref RCC_TIM20CLK_PLL PLL Clock selected as TIM20 clock
bogdanm 92:4fc01daae5a5 3768 */
bogdanm 92:4fc01daae5a5 3769 #define __HAL_RCC_TIM20_CONFIG(__TIM20CLKSource__) \
bogdanm 92:4fc01daae5a5 3770 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM20SW, (uint32_t)(__TIM20CLKSource__))
bogdanm 92:4fc01daae5a5 3771
bogdanm 92:4fc01daae5a5 3772 /** @brief Macro to get the TIM20 clock (TIM20CLK).
bogdanm 92:4fc01daae5a5 3773 * @retval The clock source can be one of the following values:
Kojto 122:f9eeca106725 3774 * @arg @ref RCC_TIM20CLK_HCLK HCLK selected as TIM20 clock
Kojto 122:f9eeca106725 3775 * @arg @ref RCC_TIM20CLK_PLL PLL Clock selected as TIM20 clock
bogdanm 92:4fc01daae5a5 3776 */
bogdanm 92:4fc01daae5a5 3777 #define __HAL_RCC_GET_TIM20_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM20SW)))
bogdanm 92:4fc01daae5a5 3778
bogdanm 92:4fc01daae5a5 3779 /**
bogdanm 92:4fc01daae5a5 3780 * @}
bogdanm 92:4fc01daae5a5 3781 */
bogdanm 92:4fc01daae5a5 3782 #endif /* STM32f303xE || STM32F398xx */
bogdanm 92:4fc01daae5a5 3783
Kojto 122:f9eeca106725 3784 /** @defgroup RCCEx_LSE_Configuration LSE Drive Configuration
Kojto 122:f9eeca106725 3785 * @{
Kojto 122:f9eeca106725 3786 */
Kojto 122:f9eeca106725 3787
Kojto 122:f9eeca106725 3788 /**
Kojto 122:f9eeca106725 3789 * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability.
Kojto 122:f9eeca106725 3790 * @param __RCC_LSEDRIVE__ specifies the new state of the LSE drive capability.
Kojto 122:f9eeca106725 3791 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 3792 * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability.
Kojto 122:f9eeca106725 3793 * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability.
Kojto 122:f9eeca106725 3794 * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability.
Kojto 122:f9eeca106725 3795 * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability.
Kojto 122:f9eeca106725 3796 * @retval None
Kojto 122:f9eeca106725 3797 */
Kojto 122:f9eeca106725 3798 #define __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDRIVE__) (MODIFY_REG(RCC->BDCR,\
Kojto 122:f9eeca106725 3799 RCC_BDCR_LSEDRV, (uint32_t)(__RCC_LSEDRIVE__) ))
Kojto 122:f9eeca106725 3800
Kojto 122:f9eeca106725 3801 /**
Kojto 122:f9eeca106725 3802 * @}
Kojto 122:f9eeca106725 3803 */
bogdanm 86:04dd9b1680ae 3804
bogdanm 86:04dd9b1680ae 3805 /**
bogdanm 86:04dd9b1680ae 3806 * @}
bogdanm 86:04dd9b1680ae 3807 */
bogdanm 86:04dd9b1680ae 3808
bogdanm 86:04dd9b1680ae 3809 /* Exported functions --------------------------------------------------------*/
Kojto 122:f9eeca106725 3810 /** @addtogroup RCCEx_Exported_Functions
bogdanm 92:4fc01daae5a5 3811 * @{
bogdanm 92:4fc01daae5a5 3812 */
bogdanm 92:4fc01daae5a5 3813
Kojto 122:f9eeca106725 3814 /** @addtogroup RCCEx_Exported_Functions_Group1
bogdanm 92:4fc01daae5a5 3815 * @{
bogdanm 92:4fc01daae5a5 3816 */
Kojto 122:f9eeca106725 3817
bogdanm 86:04dd9b1680ae 3818 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
Kojto 122:f9eeca106725 3819 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
Kojto 122:f9eeca106725 3820 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
Kojto 122:f9eeca106725 3821
bogdanm 92:4fc01daae5a5 3822 /**
bogdanm 92:4fc01daae5a5 3823 * @}
bogdanm 92:4fc01daae5a5 3824 */
bogdanm 86:04dd9b1680ae 3825
bogdanm 86:04dd9b1680ae 3826 /**
bogdanm 86:04dd9b1680ae 3827 * @}
bogdanm 86:04dd9b1680ae 3828 */
bogdanm 86:04dd9b1680ae 3829
bogdanm 86:04dd9b1680ae 3830 /**
bogdanm 86:04dd9b1680ae 3831 * @}
bogdanm 86:04dd9b1680ae 3832 */
bogdanm 86:04dd9b1680ae 3833
bogdanm 92:4fc01daae5a5 3834 /**
bogdanm 92:4fc01daae5a5 3835 * @}
bogdanm 92:4fc01daae5a5 3836 */
Kojto 122:f9eeca106725 3837
bogdanm 86:04dd9b1680ae 3838 #ifdef __cplusplus
bogdanm 86:04dd9b1680ae 3839 }
bogdanm 86:04dd9b1680ae 3840 #endif
bogdanm 86:04dd9b1680ae 3841
bogdanm 86:04dd9b1680ae 3842 #endif /* __STM32F3xx_HAL_RCC_EX_H */
bogdanm 86:04dd9b1680ae 3843
bogdanm 86:04dd9b1680ae 3844 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Kojto 122:f9eeca106725 3845