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TARGET_NUCLEO_F031K6/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_i2c.h@134:ad3be0349dc5, 2017-01-16 (annotated)

Committer:: <>
Date:: Mon Jan 16 12:05:23 2017 +0000
Revision:: 134:ad3be0349dc5
Child:: 160:5571c4ff569f

Release 134 of the mbed library

Ports for Upcoming Targets

Fixes and Changes

3488: Dev stm i2c v2 unitary functions https://github.com/ARMmbed/mbed-os/pull/3488

3492: Fix #3463 CAN read() return value https://github.com/ARMmbed/mbed-os/pull/3492

3503: [LPC15xx] Ensure that PWM=1 is resolved correctly https://github.com/ARMmbed/mbed-os/pull/3503

3504: [LPC15xx] CAN implementation improvements https://github.com/ARMmbed/mbed-os/pull/3504

3539: NUCLEO_F412ZG - Add support of TRNG peripheral https://github.com/ARMmbed/mbed-os/pull/3539

3540: STM: SPI: Initialize Rx in spi_master_write https://github.com/ARMmbed/mbed-os/pull/3540

3438: K64F: Add support for SERIAL ASYNCH API https://github.com/ARMmbed/mbed-os/pull/3438

3519: MCUXpresso: Fix ENET driver to enable interrupts after interrupt handler is set https://github.com/ARMmbed/mbed-os/pull/3519

3544: STM32L4 deepsleep improvement https://github.com/ARMmbed/mbed-os/pull/3544

3546: NUCLEO-F412ZG - Add CAN peripheral https://github.com/ARMmbed/mbed-os/pull/3546

3551: Fix I2C driver for RZ/A1H https://github.com/ARMmbed/mbed-os/pull/3551

3558: K64F UART Asynch API: Fix synchronization issue https://github.com/ARMmbed/mbed-os/pull/3558

3563: LPC4088 - Fix vector checksum https://github.com/ARMmbed/mbed-os/pull/3563

3567: Dev stm32 F0 v1.7.0 https://github.com/ARMmbed/mbed-os/pull/3567

3577: Fixes linking errors when building with debug profile https://github.com/ARMmbed/mbed-os/pull/3577

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	134:ad3be0349dc5	1	/**
<>	134:ad3be0349dc5	2	******************************************************************************
<>	134:ad3be0349dc5	3	* @file stm32f0xx_ll_i2c.h
<>	134:ad3be0349dc5	4	* @author MCD Application Team
<>	134:ad3be0349dc5	5	* @version V1.4.0
<>	134:ad3be0349dc5	6	* @date 27-May-2016
<>	134:ad3be0349dc5	7	* @brief Header file of I2C LL module.
<>	134:ad3be0349dc5	8	******************************************************************************
<>	134:ad3be0349dc5	9	* @attention
<>	134:ad3be0349dc5	10	*
<>	134:ad3be0349dc5	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	134:ad3be0349dc5	12	*
<>	134:ad3be0349dc5	13	* Redistribution and use in source and binary forms, with or without modification,
<>	134:ad3be0349dc5	14	* are permitted provided that the following conditions are met:
<>	134:ad3be0349dc5	15	* 1. Redistributions of source code must retain the above copyright notice,
<>	134:ad3be0349dc5	16	* this list of conditions and the following disclaimer.
<>	134:ad3be0349dc5	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	134:ad3be0349dc5	18	* this list of conditions and the following disclaimer in the documentation
<>	134:ad3be0349dc5	19	* and/or other materials provided with the distribution.
<>	134:ad3be0349dc5	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	134:ad3be0349dc5	21	* may be used to endorse or promote products derived from this software
<>	134:ad3be0349dc5	22	* without specific prior written permission.
<>	134:ad3be0349dc5	23	*
<>	134:ad3be0349dc5	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	134:ad3be0349dc5	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	134:ad3be0349dc5	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	134:ad3be0349dc5	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	134:ad3be0349dc5	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	134:ad3be0349dc5	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	134:ad3be0349dc5	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	134:ad3be0349dc5	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	134:ad3be0349dc5	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	134:ad3be0349dc5	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	134:ad3be0349dc5	34	*
<>	134:ad3be0349dc5	35	******************************************************************************
<>	134:ad3be0349dc5	36	*/
<>	134:ad3be0349dc5	37
<>	134:ad3be0349dc5	38	/* Define to prevent recursive inclusion -------------------------------------*/
<>	134:ad3be0349dc5	39	#ifndef __STM32F0xx_LL_I2C_H
<>	134:ad3be0349dc5	40	#define __STM32F0xx_LL_I2C_H
<>	134:ad3be0349dc5	41
<>	134:ad3be0349dc5	42	#ifdef __cplusplus
<>	134:ad3be0349dc5	43	extern "C" {
<>	134:ad3be0349dc5	44	#endif
<>	134:ad3be0349dc5	45
<>	134:ad3be0349dc5	46	/* Includes ------------------------------------------------------------------*/
<>	134:ad3be0349dc5	47	#include "stm32f0xx.h"
<>	134:ad3be0349dc5	48
<>	134:ad3be0349dc5	49	/** @addtogroup STM32F0xx_LL_Driver
<>	134:ad3be0349dc5	50	* @{
<>	134:ad3be0349dc5	51	*/
<>	134:ad3be0349dc5	52
<>	134:ad3be0349dc5	53	#if defined (I2C1) \|\| defined (I2C2)
<>	134:ad3be0349dc5	54
<>	134:ad3be0349dc5	55	/** @defgroup I2C_LL I2C
<>	134:ad3be0349dc5	56	* @{
<>	134:ad3be0349dc5	57	*/
<>	134:ad3be0349dc5	58
<>	134:ad3be0349dc5	59	/* Private types -------------------------------------------------------------*/
<>	134:ad3be0349dc5	60	/* Private variables ---------------------------------------------------------*/
<>	134:ad3be0349dc5	61
<>	134:ad3be0349dc5	62	/* Private constants ---------------------------------------------------------*/
<>	134:ad3be0349dc5	63	/** @defgroup I2C_LL_Private_Constants I2C Private Constants
<>	134:ad3be0349dc5	64	* @{
<>	134:ad3be0349dc5	65	*/
<>	134:ad3be0349dc5	66	/* Defines used for the bit position in the register and perform offsets */
<>	134:ad3be0349dc5	67	#define I2C_POSITION_CR1_DNF (uint32_t)8U
<>	134:ad3be0349dc5	68	#define I2C_POSITION_CR2_NBYTES (uint32_t)16U
<>	134:ad3be0349dc5	69	#define I2C_POSITION_TIMINGR_PRESC (uint32_t)28U
<>	134:ad3be0349dc5	70	#define I2C_POSITION_TIMINGR_SCLDEL (uint32_t)20U
<>	134:ad3be0349dc5	71	#define I2C_POSITION_TIMINGR_SDADEL (uint32_t)16U
<>	134:ad3be0349dc5	72	#define I2C_POSITION_TIMINGR_SCLH (uint32_t)8U
<>	134:ad3be0349dc5	73	#define I2C_POSITION_TIMINGR_SCLL (uint32_t)0U
<>	134:ad3be0349dc5	74	#define I2C_POSITION_ISR_ADDCODE (uint32_t)17U
<>	134:ad3be0349dc5	75	#define I2C_POSITION_TIMEOUTR_TIMEOUTB (uint32_t)16U
<>	134:ad3be0349dc5	76	/**
<>	134:ad3be0349dc5	77	* @}
<>	134:ad3be0349dc5	78	*/
<>	134:ad3be0349dc5	79
<>	134:ad3be0349dc5	80	/* Private macros ------------------------------------------------------------*/
<>	134:ad3be0349dc5	81	#if defined(USE_FULL_LL_DRIVER)
<>	134:ad3be0349dc5	82	/** @defgroup I2C_LL_Private_Macros I2C Private Macros
<>	134:ad3be0349dc5	83	* @{
<>	134:ad3be0349dc5	84	*/
<>	134:ad3be0349dc5	85	/**
<>	134:ad3be0349dc5	86	* @}
<>	134:ad3be0349dc5	87	*/
<>	134:ad3be0349dc5	88	#endif /USE_FULL_LL_DRIVER/
<>	134:ad3be0349dc5	89
<>	134:ad3be0349dc5	90	/* Exported types ------------------------------------------------------------*/
<>	134:ad3be0349dc5	91	#if defined(USE_FULL_LL_DRIVER)
<>	134:ad3be0349dc5	92	/** @defgroup I2C_LL_ES_INIT I2C Exported Init structure
<>	134:ad3be0349dc5	93	* @{
<>	134:ad3be0349dc5	94	*/
<>	134:ad3be0349dc5	95	typedef struct
<>	134:ad3be0349dc5	96	{
<>	134:ad3be0349dc5	97	uint32_t PeripheralMode; /*!< Specifies the peripheral mode.
<>	134:ad3be0349dc5	98	This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE
<>	134:ad3be0349dc5	99
<>	134:ad3be0349dc5	100	This feature can be modified afterwards using unitary function @ref LL_I2C_SetMode(). */
<>	134:ad3be0349dc5	101
<>	134:ad3be0349dc5	102	uint32_t Timing; /*!< Specifies the SDA setup, hold time and the SCL high, low period values.
<>	134:ad3be0349dc5	103	This parameter must be set by referring to the STM32CubeMX Tool and
<>	134:ad3be0349dc5	104	the helper macro @ref __LL_I2C_CONVERT_TIMINGS()
<>	134:ad3be0349dc5	105
<>	134:ad3be0349dc5	106	This feature can be modified afterwards using unitary function @ref LL_I2C_SetTiming(). */
<>	134:ad3be0349dc5	107
<>	134:ad3be0349dc5	108	uint32_t AnalogFilter; /*!< Enables or disables analog noise filter.
<>	134:ad3be0349dc5	109	This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION
<>	134:ad3be0349dc5	110
<>	134:ad3be0349dc5	111	This feature can be modified afterwards using unitary functions @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */
<>	134:ad3be0349dc5	112
<>	134:ad3be0349dc5	113	uint32_t DigitalFilter; /*!< Configures the digital noise filter.
<>	134:ad3be0349dc5	114	This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F
<>	134:ad3be0349dc5	115
<>	134:ad3be0349dc5	116	This feature can be modified afterwards using unitary function @ref LL_I2C_SetDigitalFilter(). */
<>	134:ad3be0349dc5	117
<>	134:ad3be0349dc5	118	uint32_t OwnAddress1; /*!< Specifies the device own address 1.
<>	134:ad3be0349dc5	119	This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF
<>	134:ad3be0349dc5	120
<>	134:ad3be0349dc5	121	This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
<>	134:ad3be0349dc5	122
<>	134:ad3be0349dc5	123	uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
<>	134:ad3be0349dc5	124	This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE
<>	134:ad3be0349dc5	125
<>	134:ad3be0349dc5	126	This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */
<>	134:ad3be0349dc5	127
<>	134:ad3be0349dc5	128	uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit).
<>	134:ad3be0349dc5	129	This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1
<>	134:ad3be0349dc5	130
<>	134:ad3be0349dc5	131	This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
<>	134:ad3be0349dc5	132	} LL_I2C_InitTypeDef;
<>	134:ad3be0349dc5	133	/**
<>	134:ad3be0349dc5	134	* @}
<>	134:ad3be0349dc5	135	*/
<>	134:ad3be0349dc5	136	#endif /USE_FULL_LL_DRIVER/
<>	134:ad3be0349dc5	137
<>	134:ad3be0349dc5	138	/* Exported constants --------------------------------------------------------*/
<>	134:ad3be0349dc5	139	/** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
<>	134:ad3be0349dc5	140	* @{
<>	134:ad3be0349dc5	141	*/
<>	134:ad3be0349dc5	142
<>	134:ad3be0349dc5	143	/** @defgroup I2C_LL_EC_CLEAR_FLAG Clear Flags Defines
<>	134:ad3be0349dc5	144	* @brief Flags defines which can be used with LL_I2C_WriteReg function
<>	134:ad3be0349dc5	145	* @{
<>	134:ad3be0349dc5	146	*/
<>	134:ad3be0349dc5	147	#define LL_I2C_ICR_ADDRCF I2C_ICR_ADDRCF /!< Address Matched flag /
<>	134:ad3be0349dc5	148	#define LL_I2C_ICR_NACKCF I2C_ICR_NACKCF /!< Not Acknowledge flag /
<>	134:ad3be0349dc5	149	#define LL_I2C_ICR_STOPCF I2C_ICR_STOPCF /!< Stop detection flag /
<>	134:ad3be0349dc5	150	#define LL_I2C_ICR_BERRCF I2C_ICR_BERRCF /!< Bus error flag /
<>	134:ad3be0349dc5	151	#define LL_I2C_ICR_ARLOCF I2C_ICR_ARLOCF /!< Arbitration Lost flag /
<>	134:ad3be0349dc5	152	#define LL_I2C_ICR_OVRCF I2C_ICR_OVRCF /!< Overrun/Underrun flag /
<>	134:ad3be0349dc5	153	#define LL_I2C_ICR_PECCF I2C_ICR_PECCF /!< PEC error flag /
<>	134:ad3be0349dc5	154	#define LL_I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF /!< Timeout detection flag /
<>	134:ad3be0349dc5	155	#define LL_I2C_ICR_ALERTCF I2C_ICR_ALERTCF /!< Alert flag /
<>	134:ad3be0349dc5	156	/**
<>	134:ad3be0349dc5	157	* @}
<>	134:ad3be0349dc5	158	*/
<>	134:ad3be0349dc5	159
<>	134:ad3be0349dc5	160	/** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
<>	134:ad3be0349dc5	161	* @brief Flags defines which can be used with LL_I2C_ReadReg function
<>	134:ad3be0349dc5	162	* @{
<>	134:ad3be0349dc5	163	*/
<>	134:ad3be0349dc5	164	#define LL_I2C_ISR_TXE I2C_ISR_TXE /!< Transmit data register empty /
<>	134:ad3be0349dc5	165	#define LL_I2C_ISR_TXIS I2C_ISR_TXIS /!< Transmit interrupt status /
<>	134:ad3be0349dc5	166	#define LL_I2C_ISR_RXNE I2C_ISR_RXNE /!< Receive data register not empty /
<>	134:ad3be0349dc5	167	#define LL_I2C_ISR_ADDR I2C_ISR_ADDR /!< Address matched (slave mode) /
<>	134:ad3be0349dc5	168	#define LL_I2C_ISR_NACKF I2C_ISR_NACKF /!< Not Acknowledge received flag /
<>	134:ad3be0349dc5	169	#define LL_I2C_ISR_STOPF I2C_ISR_STOPF /!< Stop detection flag /
<>	134:ad3be0349dc5	170	#define LL_I2C_ISR_TC I2C_ISR_TC /!< Transfer Complete (master mode) /
<>	134:ad3be0349dc5	171	#define LL_I2C_ISR_TCR I2C_ISR_TCR /!< Transfer Complete Reload /
<>	134:ad3be0349dc5	172	#define LL_I2C_ISR_BERR I2C_ISR_BERR /!< Bus error /
<>	134:ad3be0349dc5	173	#define LL_I2C_ISR_ARLO I2C_ISR_ARLO /!< Arbitration lost /
<>	134:ad3be0349dc5	174	#define LL_I2C_ISR_OVR I2C_ISR_OVR /!< Overrun/Underrun (slave mode) /
<>	134:ad3be0349dc5	175	#define LL_I2C_ISR_PECERR I2C_ISR_PECERR /!< PEC Error in reception (SMBus mode) /
<>	134:ad3be0349dc5	176	#define LL_I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT /!< Timeout detection flag (SMBus mode) /
<>	134:ad3be0349dc5	177	#define LL_I2C_ISR_ALERT I2C_ISR_ALERT /!< SMBus alert (SMBus mode) /
<>	134:ad3be0349dc5	178	#define LL_I2C_ISR_BUSY I2C_ISR_BUSY /!< Bus busy /
<>	134:ad3be0349dc5	179	/**
<>	134:ad3be0349dc5	180	* @}
<>	134:ad3be0349dc5	181	*/
<>	134:ad3be0349dc5	182
<>	134:ad3be0349dc5	183	/** @defgroup I2C_LL_EC_IT IT Defines
<>	134:ad3be0349dc5	184	* @brief IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions
<>	134:ad3be0349dc5	185	* @{
<>	134:ad3be0349dc5	186	*/
<>	134:ad3be0349dc5	187	#define LL_I2C_CR1_TXIE I2C_CR1_TXIE /!< TX Interrupt enable /
<>	134:ad3be0349dc5	188	#define LL_I2C_CR1_RXIE I2C_CR1_RXIE /!< RX Interrupt enable /
<>	134:ad3be0349dc5	189	#define LL_I2C_CR1_ADDRIE I2C_CR1_ADDRIE /!< Address match Interrupt enable (slave only) /
<>	134:ad3be0349dc5	190	#define LL_I2C_CR1_NACKIE I2C_CR1_NACKIE /!< Not acknowledge received Interrupt enable /
<>	134:ad3be0349dc5	191	#define LL_I2C_CR1_STOPIE I2C_CR1_STOPIE /!< STOP detection Interrupt enable /
<>	134:ad3be0349dc5	192	#define LL_I2C_CR1_TCIE I2C_CR1_TCIE /!< Transfer Complete interrupt enable /
<>	134:ad3be0349dc5	193	#define LL_I2C_CR1_ERRIE I2C_CR1_ERRIE /!< Error interrupts enable /
<>	134:ad3be0349dc5	194	/**
<>	134:ad3be0349dc5	195	* @}
<>	134:ad3be0349dc5	196	*/
<>	134:ad3be0349dc5	197
<>	134:ad3be0349dc5	198	/** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
<>	134:ad3be0349dc5	199	* @{
<>	134:ad3be0349dc5	200	*/
<>	134:ad3be0349dc5	201	#define LL_I2C_MODE_I2C ((uint32_t)0x00000000U) /!< I2C Master or Slave mode /
<>	134:ad3be0349dc5	202	#define LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN /!< SMBus Host address acknowledge /
<>	134:ad3be0349dc5	203	#define LL_I2C_MODE_SMBUS_DEVICE ((uint32_t)0x00000000U) /!< SMBus Device default mode (Default address not acknowledge) /
<>	134:ad3be0349dc5	204	#define LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN /!< SMBus Device Default address acknowledge /
<>	134:ad3be0349dc5	205	/**
<>	134:ad3be0349dc5	206	* @}
<>	134:ad3be0349dc5	207	*/
<>	134:ad3be0349dc5	208
<>	134:ad3be0349dc5	209	/** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection
<>	134:ad3be0349dc5	210	* @{
<>	134:ad3be0349dc5	211	*/
<>	134:ad3be0349dc5	212	#define LL_I2C_ANALOGFILTER_ENABLE ((uint32_t)0x00000000U) /!< Analog filter is enabled. /
<>	134:ad3be0349dc5	213	#define LL_I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF /!< Analog filter is disabled. /
<>	134:ad3be0349dc5	214	/**
<>	134:ad3be0349dc5	215	* @}
<>	134:ad3be0349dc5	216	*/
<>	134:ad3be0349dc5	217
<>	134:ad3be0349dc5	218	/** @defgroup I2C_LL_EC_ADDRESSING_MODE Master Addressing Mode
<>	134:ad3be0349dc5	219	* @{
<>	134:ad3be0349dc5	220	*/
<>	134:ad3be0349dc5	221	#define LL_I2C_ADDRESSING_MODE_7BIT ((uint32_t) 0x00000000U) /!< Master operates in 7-bit addressing mode. /
<>	134:ad3be0349dc5	222	#define LL_I2C_ADDRESSING_MODE_10BIT I2C_CR2_ADD10 /!< Master operates in 10-bit addressing mode./
<>	134:ad3be0349dc5	223	/**
<>	134:ad3be0349dc5	224	* @}
<>	134:ad3be0349dc5	225	*/
<>	134:ad3be0349dc5	226
<>	134:ad3be0349dc5	227	/** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length
<>	134:ad3be0349dc5	228	* @{
<>	134:ad3be0349dc5	229	*/
<>	134:ad3be0349dc5	230	#define LL_I2C_OWNADDRESS1_7BIT ((uint32_t)0x00000000U) /!< Own address 1 is a 7-bit address. /
<>	134:ad3be0349dc5	231	#define LL_I2C_OWNADDRESS1_10BIT I2C_OAR1_OA1MODE /!< Own address 1 is a 10-bit address./
<>	134:ad3be0349dc5	232	/**
<>	134:ad3be0349dc5	233	* @}
<>	134:ad3be0349dc5	234	*/
<>	134:ad3be0349dc5	235
<>	134:ad3be0349dc5	236	/** @defgroup I2C_LL_EC_OWNADDRESS2 Own Address 2 Masks
<>	134:ad3be0349dc5	237	* @{
<>	134:ad3be0349dc5	238	*/
<>	134:ad3be0349dc5	239	#define LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK /!< Own Address2 No mask. /
<>	134:ad3be0349dc5	240	#define LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01 /!< Only Address2 bits[7:2] are compared. /
<>	134:ad3be0349dc5	241	#define LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02 /!< Only Address2 bits[7:3] are compared. /
<>	134:ad3be0349dc5	242	#define LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03 /!< Only Address2 bits[7:4] are compared. /
<>	134:ad3be0349dc5	243	#define LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04 /!< Only Address2 bits[7:5] are compared. /
<>	134:ad3be0349dc5	244	#define LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05 /!< Only Address2 bits[7:6] are compared. /
<>	134:ad3be0349dc5	245	#define LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06 /!< Only Address2 bits[7] are compared. /
<>	134:ad3be0349dc5	246	#define LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07 /!< No comparison is done. All Address2 are acknowledged./
<>	134:ad3be0349dc5	247	/**
<>	134:ad3be0349dc5	248	* @}
<>	134:ad3be0349dc5	249	*/
<>	134:ad3be0349dc5	250
<>	134:ad3be0349dc5	251	/** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
<>	134:ad3be0349dc5	252	* @{
<>	134:ad3be0349dc5	253	*/
<>	134:ad3be0349dc5	254	#define LL_I2C_ACK ((uint32_t) 0x00000000U) /!< ACK is sent after current received byte. /
<>	134:ad3be0349dc5	255	#define LL_I2C_NACK I2C_CR2_NACK /!< NACK is sent after current received byte./
<>	134:ad3be0349dc5	256	/**
<>	134:ad3be0349dc5	257	* @}
<>	134:ad3be0349dc5	258	*/
<>	134:ad3be0349dc5	259
<>	134:ad3be0349dc5	260	/** @defgroup I2C_LL_EC_ADDRSLAVE Slave Address Length
<>	134:ad3be0349dc5	261	* @{
<>	134:ad3be0349dc5	262	*/
<>	134:ad3be0349dc5	263	#define LL_I2C_ADDRSLAVE_7BIT ((uint32_t)0x00000000U) /!< Slave Address in 7-bit. /
<>	134:ad3be0349dc5	264	#define LL_I2C_ADDRSLAVE_10BIT I2C_CR2_ADD10 /!< Slave Address in 10-bit./
<>	134:ad3be0349dc5	265	/**
<>	134:ad3be0349dc5	266	* @}
<>	134:ad3be0349dc5	267	*/
<>	134:ad3be0349dc5	268
<>	134:ad3be0349dc5	269	/** @defgroup I2C_LL_EC_REQUEST Transfer Request Direction
<>	134:ad3be0349dc5	270	* @{
<>	134:ad3be0349dc5	271	*/
<>	134:ad3be0349dc5	272	#define LL_I2C_REQUEST_WRITE ((uint32_t)0x00000000U) /!< Master request a write transfer. /
<>	134:ad3be0349dc5	273	#define LL_I2C_REQUEST_READ I2C_CR2_RD_WRN /!< Master request a read transfer. /
<>	134:ad3be0349dc5	274	/**
<>	134:ad3be0349dc5	275	* @}
<>	134:ad3be0349dc5	276	*/
<>	134:ad3be0349dc5	277
<>	134:ad3be0349dc5	278	/** @defgroup I2C_LL_EC_MODE Transfer End Mode
<>	134:ad3be0349dc5	279	* @{
<>	134:ad3be0349dc5	280	*/
<>	134:ad3be0349dc5	281	#define LL_I2C_MODE_RELOAD I2C_CR2_RELOAD /!< Enable I2C Reload mode. /
<>	134:ad3be0349dc5	282	#define LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND /!< Enable I2C Automatic end mode with no HW PEC comparison. /
<>	134:ad3be0349dc5	283	#define LL_I2C_MODE_SOFTEND ((uint32_t)0x00000000U) /!< Enable I2C Software end mode with no HW PEC comparison. /
<>	134:ad3be0349dc5	284	#define LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD /!< Enable SMBUS Automatic end mode with HW PEC comparison. /
<>	134:ad3be0349dc5	285	#define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND /!< Enable SMBUS Automatic end mode with HW PEC comparison. /
<>	134:ad3be0349dc5	286	#define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND /!< Enable SMBUS Software end mode with HW PEC comparison. /
<>	134:ad3be0349dc5	287	#define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_I2C_MODE_AUTOEND \| I2C_CR2_PECBYTE) /!< Enable SMBUS Automatic end mode with HW PEC comparison. /
<>	134:ad3be0349dc5	288	#define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_I2C_MODE_SOFTEND \| I2C_CR2_PECBYTE) /!< Enable SMBUS Software end mode with HW PEC comparison. /
<>	134:ad3be0349dc5	289	/**
<>	134:ad3be0349dc5	290	* @}
<>	134:ad3be0349dc5	291	*/
<>	134:ad3be0349dc5	292
<>	134:ad3be0349dc5	293	/** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation
<>	134:ad3be0349dc5	294	* @{
<>	134:ad3be0349dc5	295	*/
<>	134:ad3be0349dc5	296	#define LL_I2C_GENERATE_NOSTARTSTOP ((uint32_t)0x00000000U) /!< Don't Generate Stop and Start condition. /
<>	134:ad3be0349dc5	297	#define LL_I2C_GENERATE_STOP I2C_CR2_STOP /!< Generate Stop condition (Size should be set to 0). /
<>	134:ad3be0349dc5	298	#define LL_I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START \| I2C_CR2_RD_WRN) /!< Generate Start for read request. /
<>	134:ad3be0349dc5	299	#define LL_I2C_GENERATE_START_WRITE I2C_CR2_START /!< Generate Start for write request. /
<>	134:ad3be0349dc5	300	#define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(I2C_CR2_START \| I2C_CR2_RD_WRN) /!< Generate Restart for read request, slave 7Bit address. /
<>	134:ad3be0349dc5	301	#define LL_I2C_GENERATE_RESTART_7BIT_WRITE I2C_CR2_START /!< Generate Restart for write request, slave 7Bit address. /
<>	134:ad3be0349dc5	302	#define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(I2C_CR2_START \| I2C_CR2_RD_WRN \| I2C_CR2_HEAD10R) /!< Generate Restart for read request, slave 10Bit address. /
<>	134:ad3be0349dc5	303	#define LL_I2C_GENERATE_RESTART_10BIT_WRITE I2C_CR2_START /!< Generate Restart for write request, slave 10Bit address./
<>	134:ad3be0349dc5	304	/**
<>	134:ad3be0349dc5	305	* @}
<>	134:ad3be0349dc5	306	*/
<>	134:ad3be0349dc5	307
<>	134:ad3be0349dc5	308	/** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
<>	134:ad3be0349dc5	309	* @{
<>	134:ad3be0349dc5	310	*/
<>	134:ad3be0349dc5	311	#define LL_I2C_DIRECTION_WRITE ((uint32_t)0x00000000U) /!< Write transfer request by master, slave enters receiver mode. /
<>	134:ad3be0349dc5	312	#define LL_I2C_DIRECTION_READ I2C_ISR_DIR /!< Read transfer request by master, slave enters transmitter mode./
<>	134:ad3be0349dc5	313	/**
<>	134:ad3be0349dc5	314	* @}
<>	134:ad3be0349dc5	315	*/
<>	134:ad3be0349dc5	316
<>	134:ad3be0349dc5	317	/** @defgroup I2C_LL_EC_DMA_REG_DATA DMA Register Data
<>	134:ad3be0349dc5	318	* @{
<>	134:ad3be0349dc5	319	*/
<>	134:ad3be0349dc5	320	#define LL_I2C_DMA_REG_DATA_TRANSMIT ((uint32_t)0x00000000U) /!< Get address of data register used for transmission /
<>	134:ad3be0349dc5	321	#define LL_I2C_DMA_REG_DATA_RECEIVE ((uint32_t)0x00000001U) /!< Get address of data register used for reception /
<>	134:ad3be0349dc5	322	/**
<>	134:ad3be0349dc5	323	* @}
<>	134:ad3be0349dc5	324	*/
<>	134:ad3be0349dc5	325
<>	134:ad3be0349dc5	326	/** @defgroup I2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout
<>	134:ad3be0349dc5	327	* @{
<>	134:ad3be0349dc5	328	*/
<>	134:ad3be0349dc5	329	#define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW ((uint32_t) 0x00000000U) /!< TimeoutA is used to detect SCL low level timeout. /
<>	134:ad3be0349dc5	330	#define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE /!< TimeoutA is used to detect both SCL and SDA high level timeout./
<>	134:ad3be0349dc5	331	/**
<>	134:ad3be0349dc5	332	* @}
<>	134:ad3be0349dc5	333	*/
<>	134:ad3be0349dc5	334
<>	134:ad3be0349dc5	335	/** @defgroup I2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection
<>	134:ad3be0349dc5	336	* @{
<>	134:ad3be0349dc5	337	*/
<>	134:ad3be0349dc5	338	#define LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN /!< TimeoutA enable bit /
<>	134:ad3be0349dc5	339	#define LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN /!< TimeoutB (extended clock) enable bit /
<>	134:ad3be0349dc5	340	#define LL_I2C_SMBUS_ALL_TIMEOUT (uint32_t)(I2C_TIMEOUTR_TIMOUTEN \| I2C_TIMEOUTR_TEXTEN) /!< TimeoutA and TimeoutB (extended clock) enable bits /
<>	134:ad3be0349dc5	341	/**
<>	134:ad3be0349dc5	342	* @}
<>	134:ad3be0349dc5	343	*/
<>	134:ad3be0349dc5	344
<>	134:ad3be0349dc5	345	/**
<>	134:ad3be0349dc5	346	* @}
<>	134:ad3be0349dc5	347	*/
<>	134:ad3be0349dc5	348
<>	134:ad3be0349dc5	349	/* Exported macro ------------------------------------------------------------*/
<>	134:ad3be0349dc5	350	/** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
<>	134:ad3be0349dc5	351	* @{
<>	134:ad3be0349dc5	352	*/
<>	134:ad3be0349dc5	353
<>	134:ad3be0349dc5	354	/** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
<>	134:ad3be0349dc5	355	* @{
<>	134:ad3be0349dc5	356	*/
<>	134:ad3be0349dc5	357
<>	134:ad3be0349dc5	358	/**
<>	134:ad3be0349dc5	359	* @brief Write a value in I2C register
<>	134:ad3be0349dc5	360	* @param __INSTANCE__ I2C Instance
<>	134:ad3be0349dc5	361	* @param __REG__ Register to be written
<>	134:ad3be0349dc5	362	* @param __VALUE__ Value to be written in the register
<>	134:ad3be0349dc5	363	* @retval None
<>	134:ad3be0349dc5	364	*/
<>	134:ad3be0349dc5	365	#define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
<>	134:ad3be0349dc5	366
<>	134:ad3be0349dc5	367	/**
<>	134:ad3be0349dc5	368	* @brief Read a value in I2C register
<>	134:ad3be0349dc5	369	* @param __INSTANCE__ I2C Instance
<>	134:ad3be0349dc5	370	* @param __REG__ Register to be read
<>	134:ad3be0349dc5	371	* @retval Register value
<>	134:ad3be0349dc5	372	*/
<>	134:ad3be0349dc5	373	#define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
<>	134:ad3be0349dc5	374	/**
<>	134:ad3be0349dc5	375	* @}
<>	134:ad3be0349dc5	376	*/
<>	134:ad3be0349dc5	377
<>	134:ad3be0349dc5	378	/** @defgroup I2C_LL_EM_CONVERT_TIMINGS Convert SDA SCL timings
<>	134:ad3be0349dc5	379	* @{
<>	134:ad3be0349dc5	380	*/
<>	134:ad3be0349dc5	381	/**
<>	134:ad3be0349dc5	382	* @brief Configure the SDA setup, hold time and the SCL high, low period.
<>	134:ad3be0349dc5	383	* @param __PRESCALER__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
<>	134:ad3be0349dc5	384	* @param __DATA_SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tscldel = (SCLDEL+1)xtpresc)
<>	134:ad3be0349dc5	385	* @param __DATA_HOLD_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tsdadel = SDADELxtpresc)
<>	134:ad3be0349dc5	386	* @param __CLOCK_HIGH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tsclh = (SCLH+1)xtpresc)
<>	134:ad3be0349dc5	387	* @param __CLOCK_LOW_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tscll = (SCLL+1)xtpresc)
<>	134:ad3be0349dc5	388	* @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
<>	134:ad3be0349dc5	389	*/
<>	134:ad3be0349dc5	390	#define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __DATA_SETUP_TIME__, __DATA_HOLD_TIME__, __CLOCK_HIGH_PERIOD__, __CLOCK_LOW_PERIOD__) \
<>	134:ad3be0349dc5	391	((((uint32_t)(__PRESCALER__) << I2C_POSITION_TIMINGR_PRESC) & I2C_TIMINGR_PRESC) \| \
<>	134:ad3be0349dc5	392	(((uint32_t)(__DATA_SETUP_TIME__) << I2C_POSITION_TIMINGR_SCLDEL) & I2C_TIMINGR_SCLDEL) \| \
<>	134:ad3be0349dc5	393	(((uint32_t)(__DATA_HOLD_TIME__) << I2C_POSITION_TIMINGR_SDADEL) & I2C_TIMINGR_SDADEL) \| \
<>	134:ad3be0349dc5	394	(((uint32_t)(__CLOCK_HIGH_PERIOD__) << I2C_POSITION_TIMINGR_SCLH) & I2C_TIMINGR_SCLH) \| \
<>	134:ad3be0349dc5	395	(((uint32_t)(__CLOCK_LOW_PERIOD__) << I2C_POSITION_TIMINGR_SCLL) & I2C_TIMINGR_SCLL))
<>	134:ad3be0349dc5	396	/**
<>	134:ad3be0349dc5	397	* @}
<>	134:ad3be0349dc5	398	*/
<>	134:ad3be0349dc5	399
<>	134:ad3be0349dc5	400	/**
<>	134:ad3be0349dc5	401	* @}
<>	134:ad3be0349dc5	402	*/
<>	134:ad3be0349dc5	403
<>	134:ad3be0349dc5	404	/* Exported functions --------------------------------------------------------*/
<>	134:ad3be0349dc5	405	/** @defgroup I2C_LL_Exported_Functions I2C Exported Functions
<>	134:ad3be0349dc5	406	* @{
<>	134:ad3be0349dc5	407	*/
<>	134:ad3be0349dc5	408
<>	134:ad3be0349dc5	409	/** @defgroup I2C_LL_EF_Configuration Configuration
<>	134:ad3be0349dc5	410	* @{
<>	134:ad3be0349dc5	411	*/
<>	134:ad3be0349dc5	412
<>	134:ad3be0349dc5	413	/**
<>	134:ad3be0349dc5	414	* @brief Enable I2C peripheral (PE = 1).
<>	134:ad3be0349dc5	415	* @rmtoll CR1 PE LL_I2C_Enable
<>	134:ad3be0349dc5	416	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	417	* @retval None
<>	134:ad3be0349dc5	418	*/
<>	134:ad3be0349dc5	419	__STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	420	{
<>	134:ad3be0349dc5	421	SET_BIT(I2Cx->CR1, I2C_CR1_PE);
<>	134:ad3be0349dc5	422	}
<>	134:ad3be0349dc5	423
<>	134:ad3be0349dc5	424	/**
<>	134:ad3be0349dc5	425	* @brief Disable I2C peripheral (PE = 0).
<>	134:ad3be0349dc5	426	* @note When PE = 0, the I2C SCL and SDA lines are released.
<>	134:ad3be0349dc5	427	* Internal state machines and status bits are put back to their reset value.
<>	134:ad3be0349dc5	428	* When cleared, PE must be kept low for at least 3 APB clock cycles.
<>	134:ad3be0349dc5	429	* @rmtoll CR1 PE LL_I2C_Disable
<>	134:ad3be0349dc5	430	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	431	* @retval None
<>	134:ad3be0349dc5	432	*/
<>	134:ad3be0349dc5	433	__STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	434	{
<>	134:ad3be0349dc5	435	CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
<>	134:ad3be0349dc5	436	}
<>	134:ad3be0349dc5	437
<>	134:ad3be0349dc5	438	/**
<>	134:ad3be0349dc5	439	* @brief Check if the I2C peripheral is enabled or disabled.
<>	134:ad3be0349dc5	440	* @rmtoll CR1 PE LL_I2C_IsEnabled
<>	134:ad3be0349dc5	441	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	442	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	443	*/
<>	134:ad3be0349dc5	444	__STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	445	{
<>	134:ad3be0349dc5	446	return (READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE));
<>	134:ad3be0349dc5	447	}
<>	134:ad3be0349dc5	448
<>	134:ad3be0349dc5	449	/**
<>	134:ad3be0349dc5	450	* @brief Configure Noise Filters (Analog and Digital).
<>	134:ad3be0349dc5	451	* @note If the analog filter is also enabled, the digital filter is added to analog filter.
<>	134:ad3be0349dc5	452	* The filters can only be programmed when the I2C is disabled (PE = 0).
<>	134:ad3be0349dc5	453	* @rmtoll CR1 ANFOFF LL_I2C_ConfigFilters\n
<>	134:ad3be0349dc5	454	* CR1 DNF LL_I2C_ConfigFilters
<>	134:ad3be0349dc5	455	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	456	* @param AnalogFilter This parameter can be one of the following values:
<>	134:ad3be0349dc5	457	* @arg @ref LL_I2C_ANALOGFILTER_ENABLE
<>	134:ad3be0349dc5	458	* @arg @ref LL_I2C_ANALOGFILTER_DISABLE
<>	134:ad3be0349dc5	459	* @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
<>	134:ad3be0349dc5	460	* This parameter is used to configure the digital noise filter on SDA and SCL input.
<>	134:ad3be0349dc5	461	* The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
<>	134:ad3be0349dc5	462	* @retval None
<>	134:ad3be0349dc5	463	*/
<>	134:ad3be0349dc5	464	__STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
<>	134:ad3be0349dc5	465	{
<>	134:ad3be0349dc5	466	MODIFY_REG(I2Cx->CR1, I2C_CR1_ANFOFF \| I2C_CR1_DNF, AnalogFilter \| (DigitalFilter << I2C_POSITION_CR1_DNF));
<>	134:ad3be0349dc5	467	}
<>	134:ad3be0349dc5	468
<>	134:ad3be0349dc5	469	/**
<>	134:ad3be0349dc5	470	* @brief Configure Digital Noise Filter.
<>	134:ad3be0349dc5	471	* @note If the analog filter is also enabled, the digital filter is added to analog filter.
<>	134:ad3be0349dc5	472	* This filter can only be programmed when the I2C is disabled (PE = 0).
<>	134:ad3be0349dc5	473	* @rmtoll CR1 DNF LL_I2C_SetDigitalFilter
<>	134:ad3be0349dc5	474	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	475	* @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
<>	134:ad3be0349dc5	476	* This parameter is used to configure the digital noise filter on SDA and SCL input.
<>	134:ad3be0349dc5	477	* The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
<>	134:ad3be0349dc5	478	* @retval None
<>	134:ad3be0349dc5	479	*/
<>	134:ad3be0349dc5	480	__STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter)
<>	134:ad3be0349dc5	481	{
<>	134:ad3be0349dc5	482	MODIFY_REG(I2Cx->CR1, I2C_CR1_DNF, DigitalFilter << I2C_POSITION_CR1_DNF);
<>	134:ad3be0349dc5	483	}
<>	134:ad3be0349dc5	484
<>	134:ad3be0349dc5	485	/**
<>	134:ad3be0349dc5	486	* @brief Get the current Digital Noise Filter configuration.
<>	134:ad3be0349dc5	487	* @rmtoll CR1 DNF LL_I2C_GetDigitalFilter
<>	134:ad3be0349dc5	488	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	489	* @retval Value between Min_Data=0x0 and Max_Data=0xF
<>	134:ad3be0349dc5	490	*/
<>	134:ad3be0349dc5	491	__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	492	{
<>	134:ad3be0349dc5	493	return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_POSITION_CR1_DNF);
<>	134:ad3be0349dc5	494	}
<>	134:ad3be0349dc5	495
<>	134:ad3be0349dc5	496	/**
<>	134:ad3be0349dc5	497	* @brief Enable Analog Noise Filter.
<>	134:ad3be0349dc5	498	* @note This filter can only be programmed when the I2C is disabled (PE = 0).
<>	134:ad3be0349dc5	499	* @rmtoll CR1 ANFOFF LL_I2C_EnableAnalogFilter
<>	134:ad3be0349dc5	500	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	501	* @retval None
<>	134:ad3be0349dc5	502	*/
<>	134:ad3be0349dc5	503	__STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	504	{
<>	134:ad3be0349dc5	505	CLEAR_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
<>	134:ad3be0349dc5	506	}
<>	134:ad3be0349dc5	507
<>	134:ad3be0349dc5	508	/**
<>	134:ad3be0349dc5	509	* @brief Disable Analog Noise Filter.
<>	134:ad3be0349dc5	510	* @note This filter can only be programmed when the I2C is disabled (PE = 0).
<>	134:ad3be0349dc5	511	* @rmtoll CR1 ANFOFF LL_I2C_DisableAnalogFilter
<>	134:ad3be0349dc5	512	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	513	* @retval None
<>	134:ad3be0349dc5	514	*/
<>	134:ad3be0349dc5	515	__STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	516	{
<>	134:ad3be0349dc5	517	SET_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
<>	134:ad3be0349dc5	518	}
<>	134:ad3be0349dc5	519
<>	134:ad3be0349dc5	520	/**
<>	134:ad3be0349dc5	521	* @brief Check if Analog Noise Filter is enabled or disabled.
<>	134:ad3be0349dc5	522	* @rmtoll CR1 ANFOFF LL_I2C_IsEnabledAnalogFilter
<>	134:ad3be0349dc5	523	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	524	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	525	*/
<>	134:ad3be0349dc5	526	__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	527	{
<>	134:ad3be0349dc5	528	return (READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF));
<>	134:ad3be0349dc5	529	}
<>	134:ad3be0349dc5	530
<>	134:ad3be0349dc5	531	/**
<>	134:ad3be0349dc5	532	* @brief Enable DMA transmission requests.
<>	134:ad3be0349dc5	533	* @rmtoll CR1 TXDMAEN LL_I2C_EnableDMAReq_TX
<>	134:ad3be0349dc5	534	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	535	* @retval None
<>	134:ad3be0349dc5	536	*/
<>	134:ad3be0349dc5	537	__STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	538	{
<>	134:ad3be0349dc5	539	SET_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
<>	134:ad3be0349dc5	540	}
<>	134:ad3be0349dc5	541
<>	134:ad3be0349dc5	542	/**
<>	134:ad3be0349dc5	543	* @brief Disable DMA transmission requests.
<>	134:ad3be0349dc5	544	* @rmtoll CR1 TXDMAEN LL_I2C_DisableDMAReq_TX
<>	134:ad3be0349dc5	545	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	546	* @retval None
<>	134:ad3be0349dc5	547	*/
<>	134:ad3be0349dc5	548	__STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	549	{
<>	134:ad3be0349dc5	550	CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
<>	134:ad3be0349dc5	551	}
<>	134:ad3be0349dc5	552
<>	134:ad3be0349dc5	553	/**
<>	134:ad3be0349dc5	554	* @brief Check if DMA transmission requests are enabled or disabled.
<>	134:ad3be0349dc5	555	* @rmtoll CR1 TXDMAEN LL_I2C_IsEnabledDMAReq_TX
<>	134:ad3be0349dc5	556	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	557	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	558	*/
<>	134:ad3be0349dc5	559	__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	560	{
<>	134:ad3be0349dc5	561	return (READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN));
<>	134:ad3be0349dc5	562	}
<>	134:ad3be0349dc5	563
<>	134:ad3be0349dc5	564	/**
<>	134:ad3be0349dc5	565	* @brief Enable DMA reception requests.
<>	134:ad3be0349dc5	566	* @rmtoll CR1 RXDMAEN LL_I2C_EnableDMAReq_RX
<>	134:ad3be0349dc5	567	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	568	* @retval None
<>	134:ad3be0349dc5	569	*/
<>	134:ad3be0349dc5	570	__STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	571	{
<>	134:ad3be0349dc5	572	SET_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
<>	134:ad3be0349dc5	573	}
<>	134:ad3be0349dc5	574
<>	134:ad3be0349dc5	575	/**
<>	134:ad3be0349dc5	576	* @brief Disable DMA reception requests.
<>	134:ad3be0349dc5	577	* @rmtoll CR1 RXDMAEN LL_I2C_DisableDMAReq_RX
<>	134:ad3be0349dc5	578	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	579	* @retval None
<>	134:ad3be0349dc5	580	*/
<>	134:ad3be0349dc5	581	__STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	582	{
<>	134:ad3be0349dc5	583	CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
<>	134:ad3be0349dc5	584	}
<>	134:ad3be0349dc5	585
<>	134:ad3be0349dc5	586	/**
<>	134:ad3be0349dc5	587	* @brief Check if DMA reception requests are enabled or disabled.
<>	134:ad3be0349dc5	588	* @rmtoll CR1 RXDMAEN LL_I2C_IsEnabledDMAReq_RX
<>	134:ad3be0349dc5	589	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	590	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	591	*/
<>	134:ad3be0349dc5	592	__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	593	{
<>	134:ad3be0349dc5	594	return (READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN));
<>	134:ad3be0349dc5	595	}
<>	134:ad3be0349dc5	596
<>	134:ad3be0349dc5	597	/**
<>	134:ad3be0349dc5	598	* @brief Get the data register address used for DMA transfer
<>	134:ad3be0349dc5	599	* @rmtoll TXDR TXDATA LL_I2C_DMA_GetRegAddr\n
<>	134:ad3be0349dc5	600	* RXDR RXDATA LL_I2C_DMA_GetRegAddr
<>	134:ad3be0349dc5	601	* @param I2Cx I2C Instance
<>	134:ad3be0349dc5	602	* @param Direction This parameter can be one of the following values:
<>	134:ad3be0349dc5	603	* @arg @ref LL_I2C_DMA_REG_DATA_TRANSMIT
<>	134:ad3be0349dc5	604	* @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE
<>	134:ad3be0349dc5	605	* @retval Address of data register
<>	134:ad3be0349dc5	606	*/
<>	134:ad3be0349dc5	607	__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx, uint32_t Direction)
<>	134:ad3be0349dc5	608	{
<>	134:ad3be0349dc5	609	register uint32_t data_reg_addr = 0U;
<>	134:ad3be0349dc5	610
<>	134:ad3be0349dc5	611	if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT)
<>	134:ad3be0349dc5	612	{
<>	134:ad3be0349dc5	613	/* return address of TXDR register */
<>	134:ad3be0349dc5	614	data_reg_addr = (uint32_t) & (I2Cx->TXDR);
<>	134:ad3be0349dc5	615	}
<>	134:ad3be0349dc5	616	else
<>	134:ad3be0349dc5	617	{
<>	134:ad3be0349dc5	618	/* return address of RXDR register */
<>	134:ad3be0349dc5	619	data_reg_addr = (uint32_t) & (I2Cx->RXDR);
<>	134:ad3be0349dc5	620	}
<>	134:ad3be0349dc5	621
<>	134:ad3be0349dc5	622	return data_reg_addr;
<>	134:ad3be0349dc5	623	}
<>	134:ad3be0349dc5	624
<>	134:ad3be0349dc5	625	/**
<>	134:ad3be0349dc5	626	* @brief Enable Clock stretching.
<>	134:ad3be0349dc5	627	* @note This bit can only be programmed when the I2C is disabled (PE = 0).
<>	134:ad3be0349dc5	628	* @rmtoll CR1 NOSTRETCH LL_I2C_EnableClockStretching
<>	134:ad3be0349dc5	629	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	630	* @retval None
<>	134:ad3be0349dc5	631	*/
<>	134:ad3be0349dc5	632	__STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	633	{
<>	134:ad3be0349dc5	634	CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
<>	134:ad3be0349dc5	635	}
<>	134:ad3be0349dc5	636
<>	134:ad3be0349dc5	637	/**
<>	134:ad3be0349dc5	638	* @brief Disable Clock stretching.
<>	134:ad3be0349dc5	639	* @note This bit can only be programmed when the I2C is disabled (PE = 0).
<>	134:ad3be0349dc5	640	* @rmtoll CR1 NOSTRETCH LL_I2C_DisableClockStretching
<>	134:ad3be0349dc5	641	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	642	* @retval None
<>	134:ad3be0349dc5	643	*/
<>	134:ad3be0349dc5	644	__STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	645	{
<>	134:ad3be0349dc5	646	SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
<>	134:ad3be0349dc5	647	}
<>	134:ad3be0349dc5	648
<>	134:ad3be0349dc5	649	/**
<>	134:ad3be0349dc5	650	* @brief Check if Clock stretching is enabled or disabled.
<>	134:ad3be0349dc5	651	* @rmtoll CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching
<>	134:ad3be0349dc5	652	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	653	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	654	*/
<>	134:ad3be0349dc5	655	__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	656	{
<>	134:ad3be0349dc5	657	return (READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH));
<>	134:ad3be0349dc5	658	}
<>	134:ad3be0349dc5	659
<>	134:ad3be0349dc5	660	/**
<>	134:ad3be0349dc5	661	* @brief Enable hardware byte control in slave mode.
<>	134:ad3be0349dc5	662	* @rmtoll CR1 SBC LL_I2C_EnableSlaveByteControl
<>	134:ad3be0349dc5	663	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	664	* @retval None
<>	134:ad3be0349dc5	665	*/
<>	134:ad3be0349dc5	666	__STATIC_INLINE void LL_I2C_EnableSlaveByteControl(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	667	{
<>	134:ad3be0349dc5	668	SET_BIT(I2Cx->CR1, I2C_CR1_SBC);
<>	134:ad3be0349dc5	669	}
<>	134:ad3be0349dc5	670
<>	134:ad3be0349dc5	671	/**
<>	134:ad3be0349dc5	672	* @brief Disable hardware byte control in slave mode.
<>	134:ad3be0349dc5	673	* @rmtoll CR1 SBC LL_I2C_DisableSlaveByteControl
<>	134:ad3be0349dc5	674	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	675	* @retval None
<>	134:ad3be0349dc5	676	*/
<>	134:ad3be0349dc5	677	__STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	678	{
<>	134:ad3be0349dc5	679	CLEAR_BIT(I2Cx->CR1, I2C_CR1_SBC);
<>	134:ad3be0349dc5	680	}
<>	134:ad3be0349dc5	681
<>	134:ad3be0349dc5	682	/**
<>	134:ad3be0349dc5	683	* @brief Check if hardware byte control in slave mode is enabled or disabled.
<>	134:ad3be0349dc5	684	* @rmtoll CR1 SBC LL_I2C_IsEnabledSlaveByteControl
<>	134:ad3be0349dc5	685	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	686	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	687	*/
<>	134:ad3be0349dc5	688	__STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	689	{
<>	134:ad3be0349dc5	690	return (READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC));
<>	134:ad3be0349dc5	691	}
<>	134:ad3be0349dc5	692
<>	134:ad3be0349dc5	693	#if defined(I2C_CR1_WUPEN)
<>	134:ad3be0349dc5	694	/**
<>	134:ad3be0349dc5	695	* @brief Enable Wakeup from STOP.
<>	134:ad3be0349dc5	696	* @note Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
<>	134:ad3be0349dc5	697	* WakeUpFromStop feature is supported by the I2Cx Instance.
<>	134:ad3be0349dc5	698	* @note This bit can only be programmed when Digital Filter is disabled.
<>	134:ad3be0349dc5	699	* @rmtoll CR1 WUPEN LL_I2C_EnableWakeUpFromStop
<>	134:ad3be0349dc5	700	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	701	* @retval None
<>	134:ad3be0349dc5	702	*/
<>	134:ad3be0349dc5	703	__STATIC_INLINE void LL_I2C_EnableWakeUpFromStop(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	704	{
<>	134:ad3be0349dc5	705	SET_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
<>	134:ad3be0349dc5	706	}
<>	134:ad3be0349dc5	707
<>	134:ad3be0349dc5	708	/**
<>	134:ad3be0349dc5	709	* @brief Disable Wakeup from STOP.
<>	134:ad3be0349dc5	710	* @note Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
<>	134:ad3be0349dc5	711	* WakeUpFromStop feature is supported by the I2Cx Instance.
<>	134:ad3be0349dc5	712	* @rmtoll CR1 WUPEN LL_I2C_DisableWakeUpFromStop
<>	134:ad3be0349dc5	713	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	714	* @retval None
<>	134:ad3be0349dc5	715	*/
<>	134:ad3be0349dc5	716	__STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	717	{
<>	134:ad3be0349dc5	718	CLEAR_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
<>	134:ad3be0349dc5	719	}
<>	134:ad3be0349dc5	720
<>	134:ad3be0349dc5	721	/**
<>	134:ad3be0349dc5	722	* @brief Check if Wakeup from STOP is enabled or disabled.
<>	134:ad3be0349dc5	723	* @note Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
<>	134:ad3be0349dc5	724	* WakeUpFromStop feature is supported by the I2Cx Instance.
<>	134:ad3be0349dc5	725	* @rmtoll CR1 WUPEN LL_I2C_IsEnabledWakeUpFromStop
<>	134:ad3be0349dc5	726	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	727	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	728	*/
<>	134:ad3be0349dc5	729	__STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	730	{
<>	134:ad3be0349dc5	731	return (READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN));
<>	134:ad3be0349dc5	732	}
<>	134:ad3be0349dc5	733	#endif
<>	134:ad3be0349dc5	734
<>	134:ad3be0349dc5	735	/**
<>	134:ad3be0349dc5	736	* @brief Enable General Call.
<>	134:ad3be0349dc5	737	* @note When enabled the Address 0x00 is ACKed.
<>	134:ad3be0349dc5	738	* @rmtoll CR1 GCEN LL_I2C_EnableGeneralCall
<>	134:ad3be0349dc5	739	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	740	* @retval None
<>	134:ad3be0349dc5	741	*/
<>	134:ad3be0349dc5	742	__STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	743	{
<>	134:ad3be0349dc5	744	SET_BIT(I2Cx->CR1, I2C_CR1_GCEN);
<>	134:ad3be0349dc5	745	}
<>	134:ad3be0349dc5	746
<>	134:ad3be0349dc5	747	/**
<>	134:ad3be0349dc5	748	* @brief Disable General Call.
<>	134:ad3be0349dc5	749	* @note When disabled the Address 0x00 is NACKed.
<>	134:ad3be0349dc5	750	* @rmtoll CR1 GCEN LL_I2C_DisableGeneralCall
<>	134:ad3be0349dc5	751	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	752	* @retval None
<>	134:ad3be0349dc5	753	*/
<>	134:ad3be0349dc5	754	__STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	755	{
<>	134:ad3be0349dc5	756	CLEAR_BIT(I2Cx->CR1, I2C_CR1_GCEN);
<>	134:ad3be0349dc5	757	}
<>	134:ad3be0349dc5	758
<>	134:ad3be0349dc5	759	/**
<>	134:ad3be0349dc5	760	* @brief Check if General Call is enabled or disabled.
<>	134:ad3be0349dc5	761	* @rmtoll CR1 GCEN LL_I2C_IsEnabledGeneralCall
<>	134:ad3be0349dc5	762	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	763	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	764	*/
<>	134:ad3be0349dc5	765	__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	766	{
<>	134:ad3be0349dc5	767	return (READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN));
<>	134:ad3be0349dc5	768	}
<>	134:ad3be0349dc5	769
<>	134:ad3be0349dc5	770	/**
<>	134:ad3be0349dc5	771	* @brief Configure the Master to operate in 7-bit or 10-bit addressing mode.
<>	134:ad3be0349dc5	772	* @note Changing this bit is not allowed, when the START bit is set.
<>	134:ad3be0349dc5	773	* @rmtoll CR2 ADD10 LL_I2C_SetMasterAddressingMode
<>	134:ad3be0349dc5	774	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	775	* @param AddressingMode This parameter can be one of the following values:
<>	134:ad3be0349dc5	776	* @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
<>	134:ad3be0349dc5	777	* @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
<>	134:ad3be0349dc5	778	* @retval None
<>	134:ad3be0349dc5	779	*/
<>	134:ad3be0349dc5	780	__STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef *I2Cx, uint32_t AddressingMode)
<>	134:ad3be0349dc5	781	{
<>	134:ad3be0349dc5	782	MODIFY_REG(I2Cx->CR2, I2C_CR2_ADD10, AddressingMode);
<>	134:ad3be0349dc5	783	}
<>	134:ad3be0349dc5	784
<>	134:ad3be0349dc5	785	/**
<>	134:ad3be0349dc5	786	* @brief Get the Master addressing mode.
<>	134:ad3be0349dc5	787	* @rmtoll CR2 ADD10 LL_I2C_GetMasterAddressingMode
<>	134:ad3be0349dc5	788	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	789	* @retval Returned value can be one of the following values:
<>	134:ad3be0349dc5	790	* @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
<>	134:ad3be0349dc5	791	* @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
<>	134:ad3be0349dc5	792	*/
<>	134:ad3be0349dc5	793	__STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	794	{
<>	134:ad3be0349dc5	795	return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10));
<>	134:ad3be0349dc5	796	}
<>	134:ad3be0349dc5	797
<>	134:ad3be0349dc5	798	/**
<>	134:ad3be0349dc5	799	* @brief Set the Own Address1.
<>	134:ad3be0349dc5	800	* @rmtoll OAR1 OA1 LL_I2C_SetOwnAddress1\n
<>	134:ad3be0349dc5	801	* OAR1 OA1MODE LL_I2C_SetOwnAddress1
<>	134:ad3be0349dc5	802	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	803	* @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
<>	134:ad3be0349dc5	804	* @param OwnAddrSize This parameter can be one of the following values:
<>	134:ad3be0349dc5	805	* @arg @ref LL_I2C_OWNADDRESS1_7BIT
<>	134:ad3be0349dc5	806	* @arg @ref LL_I2C_OWNADDRESS1_10BIT
<>	134:ad3be0349dc5	807	* @retval None
<>	134:ad3be0349dc5	808	*/
<>	134:ad3be0349dc5	809	__STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
<>	134:ad3be0349dc5	810	{
<>	134:ad3be0349dc5	811	MODIFY_REG(I2Cx->OAR1, I2C_OAR1_OA1 \| I2C_OAR1_OA1MODE, OwnAddress1 \| OwnAddrSize);
<>	134:ad3be0349dc5	812	}
<>	134:ad3be0349dc5	813
<>	134:ad3be0349dc5	814	/**
<>	134:ad3be0349dc5	815	* @brief Enable acknowledge on Own Address1 match address.
<>	134:ad3be0349dc5	816	* @rmtoll OAR1 OA1EN LL_I2C_EnableOwnAddress1
<>	134:ad3be0349dc5	817	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	818	* @retval None
<>	134:ad3be0349dc5	819	*/
<>	134:ad3be0349dc5	820	__STATIC_INLINE void LL_I2C_EnableOwnAddress1(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	821	{
<>	134:ad3be0349dc5	822	SET_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
<>	134:ad3be0349dc5	823	}
<>	134:ad3be0349dc5	824
<>	134:ad3be0349dc5	825	/**
<>	134:ad3be0349dc5	826	* @brief Disable acknowledge on Own Address1 match address.
<>	134:ad3be0349dc5	827	* @rmtoll OAR1 OA1EN LL_I2C_DisableOwnAddress1
<>	134:ad3be0349dc5	828	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	829	* @retval None
<>	134:ad3be0349dc5	830	*/
<>	134:ad3be0349dc5	831	__STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	832	{
<>	134:ad3be0349dc5	833	CLEAR_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
<>	134:ad3be0349dc5	834	}
<>	134:ad3be0349dc5	835
<>	134:ad3be0349dc5	836	/**
<>	134:ad3be0349dc5	837	* @brief Check if Own Address1 acknowledge is enabled or disabled.
<>	134:ad3be0349dc5	838	* @rmtoll OAR1 OA1EN LL_I2C_IsEnabledOwnAddress1
<>	134:ad3be0349dc5	839	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	840	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	841	*/
<>	134:ad3be0349dc5	842	__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	843	{
<>	134:ad3be0349dc5	844	return (READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN));
<>	134:ad3be0349dc5	845	}
<>	134:ad3be0349dc5	846
<>	134:ad3be0349dc5	847	/**
<>	134:ad3be0349dc5	848	* @brief Set the 7bits Own Address2.
<>	134:ad3be0349dc5	849	* @note This action has no effect if own address2 is enabled.
<>	134:ad3be0349dc5	850	* @rmtoll OAR2 OA2 LL_I2C_SetOwnAddress2\n
<>	134:ad3be0349dc5	851	* OAR2 OA2MSK LL_I2C_SetOwnAddress2
<>	134:ad3be0349dc5	852	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	853	* @param OwnAddress2 Value between Min_Data=0 and Max_Data=0x7F.
<>	134:ad3be0349dc5	854	* @param OwnAddrMask This parameter can be one of the following values:
<>	134:ad3be0349dc5	855	* @arg @ref LL_I2C_OWNADDRESS2_NOMASK
<>	134:ad3be0349dc5	856	* @arg @ref LL_I2C_OWNADDRESS2_MASK01
<>	134:ad3be0349dc5	857	* @arg @ref LL_I2C_OWNADDRESS2_MASK02
<>	134:ad3be0349dc5	858	* @arg @ref LL_I2C_OWNADDRESS2_MASK03
<>	134:ad3be0349dc5	859	* @arg @ref LL_I2C_OWNADDRESS2_MASK04
<>	134:ad3be0349dc5	860	* @arg @ref LL_I2C_OWNADDRESS2_MASK05
<>	134:ad3be0349dc5	861	* @arg @ref LL_I2C_OWNADDRESS2_MASK06
<>	134:ad3be0349dc5	862	* @arg @ref LL_I2C_OWNADDRESS2_MASK07
<>	134:ad3be0349dc5	863	* @retval None
<>	134:ad3be0349dc5	864	*/
<>	134:ad3be0349dc5	865	__STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask)
<>	134:ad3be0349dc5	866	{
<>	134:ad3be0349dc5	867	MODIFY_REG(I2Cx->OAR2, I2C_OAR2_OA2 \| I2C_OAR2_OA2MSK, OwnAddress2 \| OwnAddrMask);
<>	134:ad3be0349dc5	868	}
<>	134:ad3be0349dc5	869
<>	134:ad3be0349dc5	870	/**
<>	134:ad3be0349dc5	871	* @brief Enable acknowledge on Own Address2 match address.
<>	134:ad3be0349dc5	872	* @rmtoll OAR2 OA2EN LL_I2C_EnableOwnAddress2
<>	134:ad3be0349dc5	873	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	874	* @retval None
<>	134:ad3be0349dc5	875	*/
<>	134:ad3be0349dc5	876	__STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	877	{
<>	134:ad3be0349dc5	878	SET_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
<>	134:ad3be0349dc5	879	}
<>	134:ad3be0349dc5	880
<>	134:ad3be0349dc5	881	/**
<>	134:ad3be0349dc5	882	* @brief Disable acknowledge on Own Address2 match address.
<>	134:ad3be0349dc5	883	* @rmtoll OAR2 OA2EN LL_I2C_DisableOwnAddress2
<>	134:ad3be0349dc5	884	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	885	* @retval None
<>	134:ad3be0349dc5	886	*/
<>	134:ad3be0349dc5	887	__STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	888	{
<>	134:ad3be0349dc5	889	CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
<>	134:ad3be0349dc5	890	}
<>	134:ad3be0349dc5	891
<>	134:ad3be0349dc5	892	/**
<>	134:ad3be0349dc5	893	* @brief Check if Own Address1 acknowledge is enabled or disabled.
<>	134:ad3be0349dc5	894	* @rmtoll OAR2 OA2EN LL_I2C_IsEnabledOwnAddress2
<>	134:ad3be0349dc5	895	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	896	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	897	*/
<>	134:ad3be0349dc5	898	__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	899	{
<>	134:ad3be0349dc5	900	return (READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN));
<>	134:ad3be0349dc5	901	}
<>	134:ad3be0349dc5	902
<>	134:ad3be0349dc5	903	/**
<>	134:ad3be0349dc5	904	* @brief Configure the SDA setup, hold time and the SCL high, low period.
<>	134:ad3be0349dc5	905	* @note This bit can only be programmed when the I2C is disabled (PE = 0).
<>	134:ad3be0349dc5	906	* @rmtoll TIMINGR TIMINGR LL_I2C_SetTiming
<>	134:ad3be0349dc5	907	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	908	* @param Timing This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF.
<>	134:ad3be0349dc5	909	* @note This parameter is computed with the STM32CubeMX Tool.
<>	134:ad3be0349dc5	910	* @retval None
<>	134:ad3be0349dc5	911	*/
<>	134:ad3be0349dc5	912	__STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing)
<>	134:ad3be0349dc5	913	{
<>	134:ad3be0349dc5	914	WRITE_REG(I2Cx->TIMINGR, Timing);
<>	134:ad3be0349dc5	915	}
<>	134:ad3be0349dc5	916
<>	134:ad3be0349dc5	917	/**
<>	134:ad3be0349dc5	918	* @brief Get the Timing Prescaler setting.
<>	134:ad3be0349dc5	919	* @rmtoll TIMINGR PRESC LL_I2C_GetTimingPrescaler
<>	134:ad3be0349dc5	920	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	921	* @retval Value between Min_Data=0x0 and Max_Data=0xF
<>	134:ad3be0349dc5	922	*/
<>	134:ad3be0349dc5	923	__STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	924	{
<>	134:ad3be0349dc5	925	return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_POSITION_TIMINGR_PRESC);
<>	134:ad3be0349dc5	926	}
<>	134:ad3be0349dc5	927
<>	134:ad3be0349dc5	928	/**
<>	134:ad3be0349dc5	929	* @brief Get the SCL low period setting.
<>	134:ad3be0349dc5	930	* @rmtoll TIMINGR SCLL LL_I2C_GetClockLowPeriod
<>	134:ad3be0349dc5	931	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	932	* @retval Value between Min_Data=0x00 and Max_Data=0xFF
<>	134:ad3be0349dc5	933	*/
<>	134:ad3be0349dc5	934	__STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	935	{
<>	134:ad3be0349dc5	936	return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_POSITION_TIMINGR_SCLL);
<>	134:ad3be0349dc5	937	}
<>	134:ad3be0349dc5	938
<>	134:ad3be0349dc5	939	/**
<>	134:ad3be0349dc5	940	* @brief Get the SCL high period setting.
<>	134:ad3be0349dc5	941	* @rmtoll TIMINGR SCLH LL_I2C_GetClockHighPeriod
<>	134:ad3be0349dc5	942	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	943	* @retval Value between Min_Data=0x00 and Max_Data=0xFF
<>	134:ad3be0349dc5	944	*/
<>	134:ad3be0349dc5	945	__STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	946	{
<>	134:ad3be0349dc5	947	return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_POSITION_TIMINGR_SCLH);
<>	134:ad3be0349dc5	948	}
<>	134:ad3be0349dc5	949
<>	134:ad3be0349dc5	950	/**
<>	134:ad3be0349dc5	951	* @brief Get the SDA hold time.
<>	134:ad3be0349dc5	952	* @rmtoll TIMINGR SDADEL LL_I2C_GetDataHoldTime
<>	134:ad3be0349dc5	953	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	954	* @retval Value between Min_Data=0x0 and Max_Data=0xF
<>	134:ad3be0349dc5	955	*/
<>	134:ad3be0349dc5	956	__STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	957	{
<>	134:ad3be0349dc5	958	return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_POSITION_TIMINGR_SDADEL);
<>	134:ad3be0349dc5	959	}
<>	134:ad3be0349dc5	960
<>	134:ad3be0349dc5	961	/**
<>	134:ad3be0349dc5	962	* @brief Get the SDA setup time.
<>	134:ad3be0349dc5	963	* @rmtoll TIMINGR SCLDEL LL_I2C_GetDataSetupTime
<>	134:ad3be0349dc5	964	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	965	* @retval Value between Min_Data=0x0 and Max_Data=0xF
<>	134:ad3be0349dc5	966	*/
<>	134:ad3be0349dc5	967	__STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	968	{
<>	134:ad3be0349dc5	969	return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_POSITION_TIMINGR_SCLDEL);
<>	134:ad3be0349dc5	970	}
<>	134:ad3be0349dc5	971
<>	134:ad3be0349dc5	972	/**
<>	134:ad3be0349dc5	973	* @brief Configure peripheral mode.
<>	134:ad3be0349dc5	974	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	134:ad3be0349dc5	975	* SMBus feature is supported by the I2Cx Instance.
<>	134:ad3be0349dc5	976	* @rmtoll CR1 SMBHEN LL_I2C_SetMode\n
<>	134:ad3be0349dc5	977	* CR1 SMBDEN LL_I2C_SetMode
<>	134:ad3be0349dc5	978	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	979	* @param PeripheralMode This parameter can be one of the following values:
<>	134:ad3be0349dc5	980	* @arg @ref LL_I2C_MODE_I2C
<>	134:ad3be0349dc5	981	* @arg @ref LL_I2C_MODE_SMBUS_HOST
<>	134:ad3be0349dc5	982	* @arg @ref LL_I2C_MODE_SMBUS_DEVICE
<>	134:ad3be0349dc5	983	* @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
<>	134:ad3be0349dc5	984	* @retval None
<>	134:ad3be0349dc5	985	*/
<>	134:ad3be0349dc5	986	__STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
<>	134:ad3be0349dc5	987	{
<>	134:ad3be0349dc5	988	MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBHEN \| I2C_CR1_SMBDEN, PeripheralMode);
<>	134:ad3be0349dc5	989	}
<>	134:ad3be0349dc5	990
<>	134:ad3be0349dc5	991	/**
<>	134:ad3be0349dc5	992	* @brief Get peripheral mode.
<>	134:ad3be0349dc5	993	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	134:ad3be0349dc5	994	* SMBus feature is supported by the I2Cx Instance.
<>	134:ad3be0349dc5	995	* @rmtoll CR1 SMBHEN LL_I2C_GetMode\n
<>	134:ad3be0349dc5	996	* CR1 SMBDEN LL_I2C_GetMode
<>	134:ad3be0349dc5	997	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	998	* @retval Returned value can be one of the following values:
<>	134:ad3be0349dc5	999	* @arg @ref LL_I2C_MODE_I2C
<>	134:ad3be0349dc5	1000	* @arg @ref LL_I2C_MODE_SMBUS_HOST
<>	134:ad3be0349dc5	1001	* @arg @ref LL_I2C_MODE_SMBUS_DEVICE
<>	134:ad3be0349dc5	1002	* @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
<>	134:ad3be0349dc5	1003	*/
<>	134:ad3be0349dc5	1004	__STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	1005	{
<>	134:ad3be0349dc5	1006	return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN \| I2C_CR1_SMBDEN));
<>	134:ad3be0349dc5	1007	}
<>	134:ad3be0349dc5	1008
<>	134:ad3be0349dc5	1009	/**
<>	134:ad3be0349dc5	1010	* @brief Enable SMBus alert (Host or Device mode)
<>	134:ad3be0349dc5	1011	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	134:ad3be0349dc5	1012	* SMBus feature is supported by the I2Cx Instance.
<>	134:ad3be0349dc5	1013	* @note SMBus Device mode:
<>	134:ad3be0349dc5	1014	* - SMBus Alert pin is drived low and
<>	134:ad3be0349dc5	1015	* Alert Response Address Header acknowledge is enabled.
<>	134:ad3be0349dc5	1016	* SMBus Host mode:
<>	134:ad3be0349dc5	1017	* - SMBus Alert pin management is supported.
<>	134:ad3be0349dc5	1018	* @rmtoll CR1 ALERTEN LL_I2C_EnableSMBusAlert
<>	134:ad3be0349dc5	1019	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1020	* @retval None
<>	134:ad3be0349dc5	1021	*/
<>	134:ad3be0349dc5	1022	__STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	1023	{
<>	134:ad3be0349dc5	1024	SET_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
<>	134:ad3be0349dc5	1025	}
<>	134:ad3be0349dc5	1026
<>	134:ad3be0349dc5	1027	/**
<>	134:ad3be0349dc5	1028	* @brief Disable SMBus alert (Host or Device mode)
<>	134:ad3be0349dc5	1029	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	134:ad3be0349dc5	1030	* SMBus feature is supported by the I2Cx Instance.
<>	134:ad3be0349dc5	1031	* @note SMBus Device mode:
<>	134:ad3be0349dc5	1032	* - SMBus Alert pin is not drived (can be used as a standard GPIO) and
<>	134:ad3be0349dc5	1033	* Alert Response Address Header acknowledge is disabled.
<>	134:ad3be0349dc5	1034	* SMBus Host mode:
<>	134:ad3be0349dc5	1035	* - SMBus Alert pin management is not supported.
<>	134:ad3be0349dc5	1036	* @rmtoll CR1 ALERTEN LL_I2C_DisableSMBusAlert
<>	134:ad3be0349dc5	1037	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1038	* @retval None
<>	134:ad3be0349dc5	1039	*/
<>	134:ad3be0349dc5	1040	__STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	1041	{
<>	134:ad3be0349dc5	1042	CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
<>	134:ad3be0349dc5	1043	}
<>	134:ad3be0349dc5	1044
<>	134:ad3be0349dc5	1045	/**
<>	134:ad3be0349dc5	1046	* @brief Check if SMBus alert (Host or Device mode) is enabled or disabled.
<>	134:ad3be0349dc5	1047	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	134:ad3be0349dc5	1048	* SMBus feature is supported by the I2Cx Instance.
<>	134:ad3be0349dc5	1049	* @rmtoll CR1 ALERTEN LL_I2C_IsEnabledSMBusAlert
<>	134:ad3be0349dc5	1050	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1051	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1052	*/
<>	134:ad3be0349dc5	1053	__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	1054	{
<>	134:ad3be0349dc5	1055	return (READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN));
<>	134:ad3be0349dc5	1056	}
<>	134:ad3be0349dc5	1057
<>	134:ad3be0349dc5	1058	/**
<>	134:ad3be0349dc5	1059	* @brief Enable SMBus Packet Error Calculation (PEC).
<>	134:ad3be0349dc5	1060	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	134:ad3be0349dc5	1061	* SMBus feature is supported by the I2Cx Instance.
<>	134:ad3be0349dc5	1062	* @rmtoll CR1 PECEN LL_I2C_EnableSMBusPEC
<>	134:ad3be0349dc5	1063	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1064	* @retval None
<>	134:ad3be0349dc5	1065	*/
<>	134:ad3be0349dc5	1066	__STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	1067	{
<>	134:ad3be0349dc5	1068	SET_BIT(I2Cx->CR1, I2C_CR1_PECEN);
<>	134:ad3be0349dc5	1069	}
<>	134:ad3be0349dc5	1070
<>	134:ad3be0349dc5	1071	/**
<>	134:ad3be0349dc5	1072	* @brief Disable SMBus Packet Error Calculation (PEC).
<>	134:ad3be0349dc5	1073	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	134:ad3be0349dc5	1074	* SMBus feature is supported by the I2Cx Instance.
<>	134:ad3be0349dc5	1075	* @rmtoll CR1 PECEN LL_I2C_DisableSMBusPEC
<>	134:ad3be0349dc5	1076	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1077	* @retval None
<>	134:ad3be0349dc5	1078	*/
<>	134:ad3be0349dc5	1079	__STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	1080	{
<>	134:ad3be0349dc5	1081	CLEAR_BIT(I2Cx->CR1, I2C_CR1_PECEN);
<>	134:ad3be0349dc5	1082	}
<>	134:ad3be0349dc5	1083
<>	134:ad3be0349dc5	1084	/**
<>	134:ad3be0349dc5	1085	* @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
<>	134:ad3be0349dc5	1086	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	134:ad3be0349dc5	1087	* SMBus feature is supported by the I2Cx Instance.
<>	134:ad3be0349dc5	1088	* @rmtoll CR1 PECEN LL_I2C_IsEnabledSMBusPEC
<>	134:ad3be0349dc5	1089	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1090	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1091	*/
<>	134:ad3be0349dc5	1092	__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	1093	{
<>	134:ad3be0349dc5	1094	return (READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN));
<>	134:ad3be0349dc5	1095	}
<>	134:ad3be0349dc5	1096
<>	134:ad3be0349dc5	1097	/**
<>	134:ad3be0349dc5	1098	* @brief Configure the SMBus Clock Timeout.
<>	134:ad3be0349dc5	1099	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	134:ad3be0349dc5	1100	* SMBus feature is supported by the I2Cx Instance.
<>	134:ad3be0349dc5	1101	* @note This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB).
<>	134:ad3be0349dc5	1102	* @rmtoll TIMEOUTR TIMEOUTA LL_I2C_ConfigSMBusTimeout\n
<>	134:ad3be0349dc5	1103	* TIMEOUTR TIDLE LL_I2C_ConfigSMBusTimeout\n
<>	134:ad3be0349dc5	1104	* TIMEOUTR TIMEOUTB LL_I2C_ConfigSMBusTimeout
<>	134:ad3be0349dc5	1105	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1106	* @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
<>	134:ad3be0349dc5	1107	* @param TimeoutAMode This parameter can be one of the following values:
<>	134:ad3be0349dc5	1108	* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
<>	134:ad3be0349dc5	1109	* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
<>	134:ad3be0349dc5	1110	* @param TimeoutB
<>	134:ad3be0349dc5	1111	* @retval None
<>	134:ad3be0349dc5	1112	*/
<>	134:ad3be0349dc5	1113	__STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode,
<>	134:ad3be0349dc5	1114	uint32_t TimeoutB)
<>	134:ad3be0349dc5	1115	{
<>	134:ad3be0349dc5	1116	MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA \| I2C_TIMEOUTR_TIDLE \| I2C_TIMEOUTR_TIMEOUTB,
<>	134:ad3be0349dc5	1117	TimeoutA \| TimeoutAMode \| (TimeoutB << I2C_POSITION_TIMEOUTR_TIMEOUTB));
<>	134:ad3be0349dc5	1118	}
<>	134:ad3be0349dc5	1119
<>	134:ad3be0349dc5	1120	/**
<>	134:ad3be0349dc5	1121	* @brief Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).
<>	134:ad3be0349dc5	1122	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	134:ad3be0349dc5	1123	* SMBus feature is supported by the I2Cx Instance.
<>	134:ad3be0349dc5	1124	* @note These bits can only be programmed when TimeoutA is disabled.
<>	134:ad3be0349dc5	1125	* @rmtoll TIMEOUTR TIMEOUTA LL_I2C_SetSMBusTimeoutA
<>	134:ad3be0349dc5	1126	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1127	* @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
<>	134:ad3be0349dc5	1128	* @retval None
<>	134:ad3be0349dc5	1129	*/
<>	134:ad3be0349dc5	1130	__STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t TimeoutA)
<>	134:ad3be0349dc5	1131	{
<>	134:ad3be0349dc5	1132	WRITE_REG(I2Cx->TIMEOUTR, TimeoutA);
<>	134:ad3be0349dc5	1133	}
<>	134:ad3be0349dc5	1134
<>	134:ad3be0349dc5	1135	/**
<>	134:ad3be0349dc5	1136	* @brief Get the SMBus Clock TimeoutA setting.
<>	134:ad3be0349dc5	1137	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	134:ad3be0349dc5	1138	* SMBus feature is supported by the I2Cx Instance.
<>	134:ad3be0349dc5	1139	* @rmtoll TIMEOUTR TIMEOUTA LL_I2C_GetSMBusTimeoutA
<>	134:ad3be0349dc5	1140	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1141	* @retval Value between Min_Data=0 and Max_Data=0xFFF
<>	134:ad3be0349dc5	1142	*/
<>	134:ad3be0349dc5	1143	__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	1144	{
<>	134:ad3be0349dc5	1145	return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA));
<>	134:ad3be0349dc5	1146	}
<>	134:ad3be0349dc5	1147
<>	134:ad3be0349dc5	1148	/**
<>	134:ad3be0349dc5	1149	* @brief Set the SMBus Clock TimeoutA mode.
<>	134:ad3be0349dc5	1150	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	134:ad3be0349dc5	1151	* SMBus feature is supported by the I2Cx Instance.
<>	134:ad3be0349dc5	1152	* @note This bit can only be programmed when TimeoutA is disabled.
<>	134:ad3be0349dc5	1153	* @rmtoll TIMEOUTR TIDLE LL_I2C_SetSMBusTimeoutAMode
<>	134:ad3be0349dc5	1154	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1155	* @param TimeoutAMode This parameter can be one of the following values:
<>	134:ad3be0349dc5	1156	* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
<>	134:ad3be0349dc5	1157	* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
<>	134:ad3be0349dc5	1158	* @retval None
<>	134:ad3be0349dc5	1159	*/
<>	134:ad3be0349dc5	1160	__STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t TimeoutAMode)
<>	134:ad3be0349dc5	1161	{
<>	134:ad3be0349dc5	1162	WRITE_REG(I2Cx->TIMEOUTR, TimeoutAMode);
<>	134:ad3be0349dc5	1163	}
<>	134:ad3be0349dc5	1164
<>	134:ad3be0349dc5	1165	/**
<>	134:ad3be0349dc5	1166	* @brief Get the SMBus Clock TimeoutA mode.
<>	134:ad3be0349dc5	1167	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	134:ad3be0349dc5	1168	* SMBus feature is supported by the I2Cx Instance.
<>	134:ad3be0349dc5	1169	* @rmtoll TIMEOUTR TIDLE LL_I2C_GetSMBusTimeoutAMode
<>	134:ad3be0349dc5	1170	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1171	* @retval Returned value can be one of the following values:
<>	134:ad3be0349dc5	1172	* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
<>	134:ad3be0349dc5	1173	* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
<>	134:ad3be0349dc5	1174	*/
<>	134:ad3be0349dc5	1175	__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	1176	{
<>	134:ad3be0349dc5	1177	return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE));
<>	134:ad3be0349dc5	1178	}
<>	134:ad3be0349dc5	1179
<>	134:ad3be0349dc5	1180	/**
<>	134:ad3be0349dc5	1181	* @brief Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).
<>	134:ad3be0349dc5	1182	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	134:ad3be0349dc5	1183	* SMBus feature is supported by the I2Cx Instance.
<>	134:ad3be0349dc5	1184	* @note These bits can only be programmed when TimeoutB is disabled.
<>	134:ad3be0349dc5	1185	* @rmtoll TIMEOUTR TIMEOUTB LL_I2C_SetSMBusTimeoutB
<>	134:ad3be0349dc5	1186	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1187	* @param TimeoutB This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
<>	134:ad3be0349dc5	1188	* @retval None
<>	134:ad3be0349dc5	1189	*/
<>	134:ad3be0349dc5	1190	__STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t TimeoutB)
<>	134:ad3be0349dc5	1191	{
<>	134:ad3be0349dc5	1192	WRITE_REG(I2Cx->TIMEOUTR, TimeoutB << I2C_POSITION_TIMEOUTR_TIMEOUTB);
<>	134:ad3be0349dc5	1193	}
<>	134:ad3be0349dc5	1194
<>	134:ad3be0349dc5	1195	/**
<>	134:ad3be0349dc5	1196	* @brief Get the SMBus Extented Cumulative Clock TimeoutB setting.
<>	134:ad3be0349dc5	1197	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	134:ad3be0349dc5	1198	* SMBus feature is supported by the I2Cx Instance.
<>	134:ad3be0349dc5	1199	* @rmtoll TIMEOUTR TIMEOUTB LL_I2C_GetSMBusTimeoutB
<>	134:ad3be0349dc5	1200	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1201	* @retval Value between Min_Data=0 and Max_Data=0xFFF
<>	134:ad3be0349dc5	1202	*/
<>	134:ad3be0349dc5	1203	__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	1204	{
<>	134:ad3be0349dc5	1205	return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_POSITION_TIMEOUTR_TIMEOUTB);
<>	134:ad3be0349dc5	1206	}
<>	134:ad3be0349dc5	1207
<>	134:ad3be0349dc5	1208	/**
<>	134:ad3be0349dc5	1209	* @brief Enable the SMBus Clock Timeout.
<>	134:ad3be0349dc5	1210	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	134:ad3be0349dc5	1211	* SMBus feature is supported by the I2Cx Instance.
<>	134:ad3be0349dc5	1212	* @rmtoll TIMEOUTR TIMOUTEN LL_I2C_EnableSMBusTimeout\n
<>	134:ad3be0349dc5	1213	* TIMEOUTR TEXTEN LL_I2C_EnableSMBusTimeout
<>	134:ad3be0349dc5	1214	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1215	* @param ClockTimeout This parameter can be one of the following values:
<>	134:ad3be0349dc5	1216	* @arg @ref LL_I2C_SMBUS_TIMEOUTA
<>	134:ad3be0349dc5	1217	* @arg @ref LL_I2C_SMBUS_TIMEOUTB
<>	134:ad3be0349dc5	1218	* @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
<>	134:ad3be0349dc5	1219	* @retval None
<>	134:ad3be0349dc5	1220	*/
<>	134:ad3be0349dc5	1221	__STATIC_INLINE void LL_I2C_EnableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
<>	134:ad3be0349dc5	1222	{
<>	134:ad3be0349dc5	1223	SET_BIT(I2Cx->TIMEOUTR, ClockTimeout);
<>	134:ad3be0349dc5	1224	}
<>	134:ad3be0349dc5	1225
<>	134:ad3be0349dc5	1226	/**
<>	134:ad3be0349dc5	1227	* @brief Disable the SMBus Clock Timeout.
<>	134:ad3be0349dc5	1228	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	134:ad3be0349dc5	1229	* SMBus feature is supported by the I2Cx Instance.
<>	134:ad3be0349dc5	1230	* @rmtoll TIMEOUTR TIMOUTEN LL_I2C_DisableSMBusTimeout\n
<>	134:ad3be0349dc5	1231	* TIMEOUTR TEXTEN LL_I2C_DisableSMBusTimeout
<>	134:ad3be0349dc5	1232	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1233	* @param ClockTimeout This parameter can be one of the following values:
<>	134:ad3be0349dc5	1234	* @arg @ref LL_I2C_SMBUS_TIMEOUTA
<>	134:ad3be0349dc5	1235	* @arg @ref LL_I2C_SMBUS_TIMEOUTB
<>	134:ad3be0349dc5	1236	* @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
<>	134:ad3be0349dc5	1237	* @retval None
<>	134:ad3be0349dc5	1238	*/
<>	134:ad3be0349dc5	1239	__STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
<>	134:ad3be0349dc5	1240	{
<>	134:ad3be0349dc5	1241	CLEAR_BIT(I2Cx->TIMEOUTR, ClockTimeout);
<>	134:ad3be0349dc5	1242	}
<>	134:ad3be0349dc5	1243
<>	134:ad3be0349dc5	1244	/**
<>	134:ad3be0349dc5	1245	* @brief Check if the SMBus Clock Timeout is enabled or disabled.
<>	134:ad3be0349dc5	1246	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	134:ad3be0349dc5	1247	* SMBus feature is supported by the I2Cx Instance.
<>	134:ad3be0349dc5	1248	* @rmtoll TIMEOUTR TIMOUTEN LL_I2C_IsEnabledSMBusTimeout\n
<>	134:ad3be0349dc5	1249	* TIMEOUTR TEXTEN LL_I2C_IsEnabledSMBusTimeout
<>	134:ad3be0349dc5	1250	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1251	* @param ClockTimeout This parameter can be one of the following values:
<>	134:ad3be0349dc5	1252	* @arg @ref LL_I2C_SMBUS_TIMEOUTA
<>	134:ad3be0349dc5	1253	* @arg @ref LL_I2C_SMBUS_TIMEOUTB
<>	134:ad3be0349dc5	1254	* @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
<>	134:ad3be0349dc5	1255	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1256	*/
<>	134:ad3be0349dc5	1257	__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
<>	134:ad3be0349dc5	1258	{
<>	134:ad3be0349dc5	1259	return (READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN \| I2C_TIMEOUTR_TEXTEN)) == (ClockTimeout));
<>	134:ad3be0349dc5	1260	}
<>	134:ad3be0349dc5	1261
<>	134:ad3be0349dc5	1262	/**
<>	134:ad3be0349dc5	1263	* @}
<>	134:ad3be0349dc5	1264	*/
<>	134:ad3be0349dc5	1265
<>	134:ad3be0349dc5	1266	/** @defgroup I2C_LL_EF_IT_Management IT_Management
<>	134:ad3be0349dc5	1267	* @{
<>	134:ad3be0349dc5	1268	*/
<>	134:ad3be0349dc5	1269
<>	134:ad3be0349dc5	1270	/**
<>	134:ad3be0349dc5	1271	* @brief Enable TXIS interrupt.
<>	134:ad3be0349dc5	1272	* @rmtoll CR1 TXIE LL_I2C_EnableIT_TX
<>	134:ad3be0349dc5	1273	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1274	* @retval None
<>	134:ad3be0349dc5	1275	*/
<>	134:ad3be0349dc5	1276	__STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	1277	{
<>	134:ad3be0349dc5	1278	SET_BIT(I2Cx->CR1, I2C_CR1_TXIE);
<>	134:ad3be0349dc5	1279	}
<>	134:ad3be0349dc5	1280
<>	134:ad3be0349dc5	1281	/**
<>	134:ad3be0349dc5	1282	* @brief Disable TXIS interrupt.
<>	134:ad3be0349dc5	1283	* @rmtoll CR1 TXIE LL_I2C_DisableIT_TX
<>	134:ad3be0349dc5	1284	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1285	* @retval None
<>	134:ad3be0349dc5	1286	*/
<>	134:ad3be0349dc5	1287	__STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	1288	{
<>	134:ad3be0349dc5	1289	CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE);
<>	134:ad3be0349dc5	1290	}
<>	134:ad3be0349dc5	1291
<>	134:ad3be0349dc5	1292	/**
<>	134:ad3be0349dc5	1293	* @brief Check if the TXIS Interrupt is enabled or disabled.
<>	134:ad3be0349dc5	1294	* @rmtoll CR1 TXIE LL_I2C_IsEnabledIT_TX
<>	134:ad3be0349dc5	1295	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1296	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1297	*/
<>	134:ad3be0349dc5	1298	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	1299	{
<>	134:ad3be0349dc5	1300	return (READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE));
<>	134:ad3be0349dc5	1301	}
<>	134:ad3be0349dc5	1302
<>	134:ad3be0349dc5	1303	/**
<>	134:ad3be0349dc5	1304	* @brief Enable RXNE interrupt.
<>	134:ad3be0349dc5	1305	* @rmtoll CR1 RXIE LL_I2C_EnableIT_RX
<>	134:ad3be0349dc5	1306	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1307	* @retval None
<>	134:ad3be0349dc5	1308	*/
<>	134:ad3be0349dc5	1309	__STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	1310	{
<>	134:ad3be0349dc5	1311	SET_BIT(I2Cx->CR1, I2C_CR1_RXIE);
<>	134:ad3be0349dc5	1312	}
<>	134:ad3be0349dc5	1313
<>	134:ad3be0349dc5	1314	/**
<>	134:ad3be0349dc5	1315	* @brief Disable RXNE interrupt.
<>	134:ad3be0349dc5	1316	* @rmtoll CR1 RXIE LL_I2C_DisableIT_RX
<>	134:ad3be0349dc5	1317	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1318	* @retval None
<>	134:ad3be0349dc5	1319	*/
<>	134:ad3be0349dc5	1320	__STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	1321	{
<>	134:ad3be0349dc5	1322	CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXIE);
<>	134:ad3be0349dc5	1323	}
<>	134:ad3be0349dc5	1324
<>	134:ad3be0349dc5	1325	/**
<>	134:ad3be0349dc5	1326	* @brief Check if the RXNE Interrupt is enabled or disabled.
<>	134:ad3be0349dc5	1327	* @rmtoll CR1 RXIE LL_I2C_IsEnabledIT_RX
<>	134:ad3be0349dc5	1328	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1329	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1330	*/
<>	134:ad3be0349dc5	1331	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	1332	{
<>	134:ad3be0349dc5	1333	return (READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE));
<>	134:ad3be0349dc5	1334	}
<>	134:ad3be0349dc5	1335
<>	134:ad3be0349dc5	1336	/**
<>	134:ad3be0349dc5	1337	* @brief Enable Address match interrupt (slave mode only).
<>	134:ad3be0349dc5	1338	* @rmtoll CR1 ADDRIE LL_I2C_EnableIT_ADDR
<>	134:ad3be0349dc5	1339	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1340	* @retval None
<>	134:ad3be0349dc5	1341	*/
<>	134:ad3be0349dc5	1342	__STATIC_INLINE void LL_I2C_EnableIT_ADDR(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	1343	{
<>	134:ad3be0349dc5	1344	SET_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
<>	134:ad3be0349dc5	1345	}
<>	134:ad3be0349dc5	1346
<>	134:ad3be0349dc5	1347	/**
<>	134:ad3be0349dc5	1348	* @brief Disable Address match interrupt (slave mode only).
<>	134:ad3be0349dc5	1349	* @rmtoll CR1 ADDRIE LL_I2C_DisableIT_ADDR
<>	134:ad3be0349dc5	1350	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1351	* @retval None
<>	134:ad3be0349dc5	1352	*/
<>	134:ad3be0349dc5	1353	__STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	1354	{
<>	134:ad3be0349dc5	1355	CLEAR_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
<>	134:ad3be0349dc5	1356	}
<>	134:ad3be0349dc5	1357
<>	134:ad3be0349dc5	1358	/**
<>	134:ad3be0349dc5	1359	* @brief Check if Address match interrupt is enabled or disabled.
<>	134:ad3be0349dc5	1360	* @rmtoll CR1 ADDRIE LL_I2C_IsEnabledIT_ADDR
<>	134:ad3be0349dc5	1361	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1362	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1363	*/
<>	134:ad3be0349dc5	1364	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	1365	{
<>	134:ad3be0349dc5	1366	return (READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE));
<>	134:ad3be0349dc5	1367	}
<>	134:ad3be0349dc5	1368
<>	134:ad3be0349dc5	1369	/**
<>	134:ad3be0349dc5	1370	* @brief Enable Not acknowledge received interrupt.
<>	134:ad3be0349dc5	1371	* @rmtoll CR1 NACKIE LL_I2C_EnableIT_NACK
<>	134:ad3be0349dc5	1372	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1373	* @retval None
<>	134:ad3be0349dc5	1374	*/
<>	134:ad3be0349dc5	1375	__STATIC_INLINE void LL_I2C_EnableIT_NACK(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	1376	{
<>	134:ad3be0349dc5	1377	SET_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
<>	134:ad3be0349dc5	1378	}
<>	134:ad3be0349dc5	1379
<>	134:ad3be0349dc5	1380	/**
<>	134:ad3be0349dc5	1381	* @brief Disable Not acknowledge received interrupt.
<>	134:ad3be0349dc5	1382	* @rmtoll CR1 NACKIE LL_I2C_DisableIT_NACK
<>	134:ad3be0349dc5	1383	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1384	* @retval None
<>	134:ad3be0349dc5	1385	*/
<>	134:ad3be0349dc5	1386	__STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	1387	{
<>	134:ad3be0349dc5	1388	CLEAR_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
<>	134:ad3be0349dc5	1389	}
<>	134:ad3be0349dc5	1390
<>	134:ad3be0349dc5	1391	/**
<>	134:ad3be0349dc5	1392	* @brief Check if Not acknowledge received interrupt is enabled or disabled.
<>	134:ad3be0349dc5	1393	* @rmtoll CR1 NACKIE LL_I2C_IsEnabledIT_NACK
<>	134:ad3be0349dc5	1394	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1395	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1396	*/
<>	134:ad3be0349dc5	1397	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	1398	{
<>	134:ad3be0349dc5	1399	return (READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE));
<>	134:ad3be0349dc5	1400	}
<>	134:ad3be0349dc5	1401
<>	134:ad3be0349dc5	1402	/**
<>	134:ad3be0349dc5	1403	* @brief Enable STOP detection interrupt.
<>	134:ad3be0349dc5	1404	* @rmtoll CR1 STOPIE LL_I2C_EnableIT_STOP
<>	134:ad3be0349dc5	1405	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1406	* @retval None
<>	134:ad3be0349dc5	1407	*/
<>	134:ad3be0349dc5	1408	__STATIC_INLINE void LL_I2C_EnableIT_STOP(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	1409	{
<>	134:ad3be0349dc5	1410	SET_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
<>	134:ad3be0349dc5	1411	}
<>	134:ad3be0349dc5	1412
<>	134:ad3be0349dc5	1413	/**
<>	134:ad3be0349dc5	1414	* @brief Disable STOP detection interrupt.
<>	134:ad3be0349dc5	1415	* @rmtoll CR1 STOPIE LL_I2C_DisableIT_STOP
<>	134:ad3be0349dc5	1416	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1417	* @retval None
<>	134:ad3be0349dc5	1418	*/
<>	134:ad3be0349dc5	1419	__STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	1420	{
<>	134:ad3be0349dc5	1421	CLEAR_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
<>	134:ad3be0349dc5	1422	}
<>	134:ad3be0349dc5	1423
<>	134:ad3be0349dc5	1424	/**
<>	134:ad3be0349dc5	1425	* @brief Check if STOP detection interrupt is enabled or disabled.
<>	134:ad3be0349dc5	1426	* @rmtoll CR1 STOPIE LL_I2C_IsEnabledIT_STOP
<>	134:ad3be0349dc5	1427	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1428	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1429	*/
<>	134:ad3be0349dc5	1430	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	1431	{
<>	134:ad3be0349dc5	1432	return (READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE));
<>	134:ad3be0349dc5	1433	}
<>	134:ad3be0349dc5	1434
<>	134:ad3be0349dc5	1435	/**
<>	134:ad3be0349dc5	1436	* @brief Enable Transfer Complete interrupt.
<>	134:ad3be0349dc5	1437	* @note Any of these events will generate interrupt :
<>	134:ad3be0349dc5	1438	* Transfer Complete (TC)
<>	134:ad3be0349dc5	1439	* Transfer Complete Reload (TCR)
<>	134:ad3be0349dc5	1440	* @rmtoll CR1 TCIE LL_I2C_EnableIT_TC
<>	134:ad3be0349dc5	1441	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1442	* @retval None
<>	134:ad3be0349dc5	1443	*/
<>	134:ad3be0349dc5	1444	__STATIC_INLINE void LL_I2C_EnableIT_TC(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	1445	{
<>	134:ad3be0349dc5	1446	SET_BIT(I2Cx->CR1, I2C_CR1_TCIE);
<>	134:ad3be0349dc5	1447	}
<>	134:ad3be0349dc5	1448
<>	134:ad3be0349dc5	1449	/**
<>	134:ad3be0349dc5	1450	* @brief Disable Transfer Complete interrupt.
<>	134:ad3be0349dc5	1451	* @note Any of these events will generate interrupt :
<>	134:ad3be0349dc5	1452	* Transfer Complete (TC)
<>	134:ad3be0349dc5	1453	* Transfer Complete Reload (TCR)
<>	134:ad3be0349dc5	1454	* @rmtoll CR1 TCIE LL_I2C_DisableIT_TC
<>	134:ad3be0349dc5	1455	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1456	* @retval None
<>	134:ad3be0349dc5	1457	*/
<>	134:ad3be0349dc5	1458	__STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	1459	{
<>	134:ad3be0349dc5	1460	CLEAR_BIT(I2Cx->CR1, I2C_CR1_TCIE);
<>	134:ad3be0349dc5	1461	}
<>	134:ad3be0349dc5	1462
<>	134:ad3be0349dc5	1463	/**
<>	134:ad3be0349dc5	1464	* @brief Check if Transfer Complete interrupt is enabled or disabled.
<>	134:ad3be0349dc5	1465	* @rmtoll CR1 TCIE LL_I2C_IsEnabledIT_TC
<>	134:ad3be0349dc5	1466	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1467	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1468	*/
<>	134:ad3be0349dc5	1469	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	1470	{
<>	134:ad3be0349dc5	1471	return (READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE));
<>	134:ad3be0349dc5	1472	}
<>	134:ad3be0349dc5	1473
<>	134:ad3be0349dc5	1474	/**
<>	134:ad3be0349dc5	1475	* @brief Enable Error interrupts.
<>	134:ad3be0349dc5	1476	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	134:ad3be0349dc5	1477	* SMBus feature is supported by the I2Cx Instance.
<>	134:ad3be0349dc5	1478	* @note Any of these errors will generate interrupt :
<>	134:ad3be0349dc5	1479	* Arbitration Loss (ARLO)
<>	134:ad3be0349dc5	1480	* Bus Error detection (BERR)
<>	134:ad3be0349dc5	1481	* Overrun/Underrun (OVR)
<>	134:ad3be0349dc5	1482	* SMBus Timeout detection (TIMEOUT)
<>	134:ad3be0349dc5	1483	* SMBus PEC error detection (PECERR)
<>	134:ad3be0349dc5	1484	* SMBus Alert pin event detection (ALERT)
<>	134:ad3be0349dc5	1485	* @rmtoll CR1 ERRIE LL_I2C_EnableIT_ERR
<>	134:ad3be0349dc5	1486	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1487	* @retval None
<>	134:ad3be0349dc5	1488	*/
<>	134:ad3be0349dc5	1489	__STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	1490	{
<>	134:ad3be0349dc5	1491	SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
<>	134:ad3be0349dc5	1492	}
<>	134:ad3be0349dc5	1493
<>	134:ad3be0349dc5	1494	/**
<>	134:ad3be0349dc5	1495	* @brief Disable Error interrupts.
<>	134:ad3be0349dc5	1496	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	134:ad3be0349dc5	1497	* SMBus feature is supported by the I2Cx Instance.
<>	134:ad3be0349dc5	1498	* @note Any of these errors will generate interrupt :
<>	134:ad3be0349dc5	1499	* Arbitration Loss (ARLO)
<>	134:ad3be0349dc5	1500	* Bus Error detection (BERR)
<>	134:ad3be0349dc5	1501	* Overrun/Underrun (OVR)
<>	134:ad3be0349dc5	1502	* SMBus Timeout detection (TIMEOUT)
<>	134:ad3be0349dc5	1503	* SMBus PEC error detection (PECERR)
<>	134:ad3be0349dc5	1504	* SMBus Alert pin event detection (ALERT)
<>	134:ad3be0349dc5	1505	* @rmtoll CR1 ERRIE LL_I2C_DisableIT_ERR
<>	134:ad3be0349dc5	1506	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1507	* @retval None
<>	134:ad3be0349dc5	1508	*/
<>	134:ad3be0349dc5	1509	__STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	1510	{
<>	134:ad3be0349dc5	1511	CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
<>	134:ad3be0349dc5	1512	}
<>	134:ad3be0349dc5	1513
<>	134:ad3be0349dc5	1514	/**
<>	134:ad3be0349dc5	1515	* @brief Check if Error interrupts are enabled or disabled.
<>	134:ad3be0349dc5	1516	* @rmtoll CR1 ERRIE LL_I2C_IsEnabledIT_ERR
<>	134:ad3be0349dc5	1517	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1518	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1519	*/
<>	134:ad3be0349dc5	1520	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	1521	{
<>	134:ad3be0349dc5	1522	return (READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE));
<>	134:ad3be0349dc5	1523	}
<>	134:ad3be0349dc5	1524
<>	134:ad3be0349dc5	1525	/**
<>	134:ad3be0349dc5	1526	* @}
<>	134:ad3be0349dc5	1527	*/
<>	134:ad3be0349dc5	1528
<>	134:ad3be0349dc5	1529	/** @defgroup I2C_LL_EF_FLAG_management FLAG_management
<>	134:ad3be0349dc5	1530	* @{
<>	134:ad3be0349dc5	1531	*/
<>	134:ad3be0349dc5	1532
<>	134:ad3be0349dc5	1533	/**
<>	134:ad3be0349dc5	1534	* @brief Indicate the status of Transmit data register empty flag.
<>	134:ad3be0349dc5	1535	* @note RESET: When next data is written in Transmit data register.
<>	134:ad3be0349dc5	1536	* SET: When Transmit data register is empty.
<>	134:ad3be0349dc5	1537	* @rmtoll ISR TXE LL_I2C_IsActiveFlag_TXE
<>	134:ad3be0349dc5	1538	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1539	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1540	*/
<>	134:ad3be0349dc5	1541	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	1542	{
<>	134:ad3be0349dc5	1543	return (READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE));
<>	134:ad3be0349dc5	1544	}
<>	134:ad3be0349dc5	1545
<>	134:ad3be0349dc5	1546	/**
<>	134:ad3be0349dc5	1547	* @brief Indicate the status of Transmit interrupt flag.
<>	134:ad3be0349dc5	1548	* @note RESET: When next data is written in Transmit data register.
<>	134:ad3be0349dc5	1549	* SET: When Transmit data register is empty.
<>	134:ad3be0349dc5	1550	* @rmtoll ISR TXIS LL_I2C_IsActiveFlag_TXIS
<>	134:ad3be0349dc5	1551	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1552	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1553	*/
<>	134:ad3be0349dc5	1554	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	1555	{
<>	134:ad3be0349dc5	1556	return (READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS));
<>	134:ad3be0349dc5	1557	}
<>	134:ad3be0349dc5	1558
<>	134:ad3be0349dc5	1559	/**
<>	134:ad3be0349dc5	1560	* @brief Indicate the status of Receive data register not empty flag.
<>	134:ad3be0349dc5	1561	* @note RESET: When Receive data register is read.
<>	134:ad3be0349dc5	1562	* SET: When the received data is copied in Receive data register.
<>	134:ad3be0349dc5	1563	* @rmtoll ISR RXNE LL_I2C_IsActiveFlag_RXNE
<>	134:ad3be0349dc5	1564	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1565	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1566	*/
<>	134:ad3be0349dc5	1567	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	1568	{
<>	134:ad3be0349dc5	1569	return (READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE));
<>	134:ad3be0349dc5	1570	}
<>	134:ad3be0349dc5	1571
<>	134:ad3be0349dc5	1572	/**
<>	134:ad3be0349dc5	1573	* @brief Indicate the status of Address matched flag (slave mode).
<>	134:ad3be0349dc5	1574	* @note RESET: Clear default value.
<>	134:ad3be0349dc5	1575	* SET: When the received slave address matched with one of the enabled slave address.
<>	134:ad3be0349dc5	1576	* @rmtoll ISR ADDR LL_I2C_IsActiveFlag_ADDR
<>	134:ad3be0349dc5	1577	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1578	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1579	*/
<>	134:ad3be0349dc5	1580	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	1581	{
<>	134:ad3be0349dc5	1582	return (READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR));
<>	134:ad3be0349dc5	1583	}
<>	134:ad3be0349dc5	1584
<>	134:ad3be0349dc5	1585	/**
<>	134:ad3be0349dc5	1586	* @brief Indicate the status of Not Acknowledge received flag.
<>	134:ad3be0349dc5	1587	* @note RESET: Clear default value.
<>	134:ad3be0349dc5	1588	* SET: When a NACK is received after a byte transmission.
<>	134:ad3be0349dc5	1589	* @rmtoll ISR NACKF LL_I2C_IsActiveFlag_NACK
<>	134:ad3be0349dc5	1590	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1591	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1592	*/
<>	134:ad3be0349dc5	1593	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	1594	{
<>	134:ad3be0349dc5	1595	return (READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF));
<>	134:ad3be0349dc5	1596	}
<>	134:ad3be0349dc5	1597
<>	134:ad3be0349dc5	1598	/**
<>	134:ad3be0349dc5	1599	* @brief Indicate the status of Stop detection flag.
<>	134:ad3be0349dc5	1600	* @note RESET: Clear default value.
<>	134:ad3be0349dc5	1601	* SET: When a Stop condition is detected.
<>	134:ad3be0349dc5	1602	* @rmtoll ISR STOPF LL_I2C_IsActiveFlag_STOP
<>	134:ad3be0349dc5	1603	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1604	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1605	*/
<>	134:ad3be0349dc5	1606	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	1607	{
<>	134:ad3be0349dc5	1608	return (READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF));
<>	134:ad3be0349dc5	1609	}
<>	134:ad3be0349dc5	1610
<>	134:ad3be0349dc5	1611	/**
<>	134:ad3be0349dc5	1612	* @brief Indicate the status of Transfer complete flag (master mode).
<>	134:ad3be0349dc5	1613	* @note RESET: Clear default value.
<>	134:ad3be0349dc5	1614	* SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred.
<>	134:ad3be0349dc5	1615	* @rmtoll ISR TC LL_I2C_IsActiveFlag_TC
<>	134:ad3be0349dc5	1616	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1617	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1618	*/
<>	134:ad3be0349dc5	1619	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	1620	{
<>	134:ad3be0349dc5	1621	return (READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC));
<>	134:ad3be0349dc5	1622	}
<>	134:ad3be0349dc5	1623
<>	134:ad3be0349dc5	1624	/**
<>	134:ad3be0349dc5	1625	* @brief Indicate the status of Transfer complete flag (master mode).
<>	134:ad3be0349dc5	1626	* @note RESET: Clear default value.
<>	134:ad3be0349dc5	1627	* SET: When RELOAD=1 and NBYTES date have been transferred.
<>	134:ad3be0349dc5	1628	* @rmtoll ISR TCR LL_I2C_IsActiveFlag_TCR
<>	134:ad3be0349dc5	1629	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1630	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1631	*/
<>	134:ad3be0349dc5	1632	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	1633	{
<>	134:ad3be0349dc5	1634	return (READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR));
<>	134:ad3be0349dc5	1635	}
<>	134:ad3be0349dc5	1636
<>	134:ad3be0349dc5	1637	/**
<>	134:ad3be0349dc5	1638	* @brief Indicate the status of Bus error flag.
<>	134:ad3be0349dc5	1639	* @note RESET: Clear default value.
<>	134:ad3be0349dc5	1640	* SET: When a misplaced Start or Stop condition is detected.
<>	134:ad3be0349dc5	1641	* @rmtoll ISR BERR LL_I2C_IsActiveFlag_BERR
<>	134:ad3be0349dc5	1642	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1643	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1644	*/
<>	134:ad3be0349dc5	1645	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	1646	{
<>	134:ad3be0349dc5	1647	return (READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR));
<>	134:ad3be0349dc5	1648	}
<>	134:ad3be0349dc5	1649
<>	134:ad3be0349dc5	1650	/**
<>	134:ad3be0349dc5	1651	* @brief Indicate the status of Arbitration lost flag.
<>	134:ad3be0349dc5	1652	* @note RESET: Clear default value.
<>	134:ad3be0349dc5	1653	* SET: When arbitration lost.
<>	134:ad3be0349dc5	1654	* @rmtoll ISR ARLO LL_I2C_IsActiveFlag_ARLO
<>	134:ad3be0349dc5	1655	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1656	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1657	*/
<>	134:ad3be0349dc5	1658	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	1659	{
<>	134:ad3be0349dc5	1660	return (READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO));
<>	134:ad3be0349dc5	1661	}
<>	134:ad3be0349dc5	1662
<>	134:ad3be0349dc5	1663	/**
<>	134:ad3be0349dc5	1664	* @brief Indicate the status of Overrun/Underrun flag (slave mode).
<>	134:ad3be0349dc5	1665	* @note RESET: Clear default value.
<>	134:ad3be0349dc5	1666	* SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
<>	134:ad3be0349dc5	1667	* @rmtoll ISR OVR LL_I2C_IsActiveFlag_OVR
<>	134:ad3be0349dc5	1668	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1669	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1670	*/
<>	134:ad3be0349dc5	1671	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	1672	{
<>	134:ad3be0349dc5	1673	return (READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR));
<>	134:ad3be0349dc5	1674	}
<>	134:ad3be0349dc5	1675
<>	134:ad3be0349dc5	1676	/**
<>	134:ad3be0349dc5	1677	* @brief Indicate the status of SMBus PEC error flag in reception.
<>	134:ad3be0349dc5	1678	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	134:ad3be0349dc5	1679	* SMBus feature is supported by the I2Cx Instance.
<>	134:ad3be0349dc5	1680	* @note RESET: Clear default value.
<>	134:ad3be0349dc5	1681	* SET: When the received PEC does not match with the PEC register content.
<>	134:ad3be0349dc5	1682	* @rmtoll ISR PECERR LL_I2C_IsActiveSMBusFlag_PECERR
<>	134:ad3be0349dc5	1683	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1684	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1685	*/
<>	134:ad3be0349dc5	1686	__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	1687	{
<>	134:ad3be0349dc5	1688	return (READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR));
<>	134:ad3be0349dc5	1689	}
<>	134:ad3be0349dc5	1690
<>	134:ad3be0349dc5	1691	/**
<>	134:ad3be0349dc5	1692	* @brief Indicate the status of SMBus Timeout detection flag.
<>	134:ad3be0349dc5	1693	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	134:ad3be0349dc5	1694	* SMBus feature is supported by the I2Cx Instance.
<>	134:ad3be0349dc5	1695	* @note RESET: Clear default value.
<>	134:ad3be0349dc5	1696	* SET: When a timeout or extended clock timeout occurs.
<>	134:ad3be0349dc5	1697	* @rmtoll ISR TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT
<>	134:ad3be0349dc5	1698	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1699	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1700	*/
<>	134:ad3be0349dc5	1701	__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	1702	{
<>	134:ad3be0349dc5	1703	return (READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT));
<>	134:ad3be0349dc5	1704	}
<>	134:ad3be0349dc5	1705
<>	134:ad3be0349dc5	1706	/**
<>	134:ad3be0349dc5	1707	* @brief Indicate the status of SMBus alert flag.
<>	134:ad3be0349dc5	1708	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	134:ad3be0349dc5	1709	* SMBus feature is supported by the I2Cx Instance.
<>	134:ad3be0349dc5	1710	* @note RESET: Clear default value.
<>	134:ad3be0349dc5	1711	* SET: When SMBus host configuration, SMBus alert enabled and
<>	134:ad3be0349dc5	1712	* a falling edge event occurs on SMBA pin.
<>	134:ad3be0349dc5	1713	* @rmtoll ISR ALERT LL_I2C_IsActiveSMBusFlag_ALERT
<>	134:ad3be0349dc5	1714	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1715	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1716	*/
<>	134:ad3be0349dc5	1717	__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	1718	{
<>	134:ad3be0349dc5	1719	return (READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT));
<>	134:ad3be0349dc5	1720	}
<>	134:ad3be0349dc5	1721
<>	134:ad3be0349dc5	1722	/**
<>	134:ad3be0349dc5	1723	* @brief Indicate the status of Bus Busy flag.
<>	134:ad3be0349dc5	1724	* @note RESET: Clear default value.
<>	134:ad3be0349dc5	1725	* SET: When a Start condition is detected.
<>	134:ad3be0349dc5	1726	* @rmtoll ISR BUSY LL_I2C_IsActiveFlag_BUSY
<>	134:ad3be0349dc5	1727	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1728	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1729	*/
<>	134:ad3be0349dc5	1730	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	1731	{
<>	134:ad3be0349dc5	1732	return (READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY));
<>	134:ad3be0349dc5	1733	}
<>	134:ad3be0349dc5	1734
<>	134:ad3be0349dc5	1735	/**
<>	134:ad3be0349dc5	1736	* @brief Clear Address Matched flag.
<>	134:ad3be0349dc5	1737	* @rmtoll ICR ADDRCF LL_I2C_ClearFlag_ADDR
<>	134:ad3be0349dc5	1738	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1739	* @retval None
<>	134:ad3be0349dc5	1740	*/
<>	134:ad3be0349dc5	1741	__STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	1742	{
<>	134:ad3be0349dc5	1743	SET_BIT(I2Cx->ICR, I2C_ICR_ADDRCF);
<>	134:ad3be0349dc5	1744	}
<>	134:ad3be0349dc5	1745
<>	134:ad3be0349dc5	1746	/**
<>	134:ad3be0349dc5	1747	* @brief Clear Not Acknowledge flag.
<>	134:ad3be0349dc5	1748	* @rmtoll ICR NACKCF LL_I2C_ClearFlag_NACK
<>	134:ad3be0349dc5	1749	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1750	* @retval None
<>	134:ad3be0349dc5	1751	*/
<>	134:ad3be0349dc5	1752	__STATIC_INLINE void LL_I2C_ClearFlag_NACK(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	1753	{
<>	134:ad3be0349dc5	1754	SET_BIT(I2Cx->ICR, I2C_ICR_NACKCF);
<>	134:ad3be0349dc5	1755	}
<>	134:ad3be0349dc5	1756
<>	134:ad3be0349dc5	1757	/**
<>	134:ad3be0349dc5	1758	* @brief Clear Stop detection flag.
<>	134:ad3be0349dc5	1759	* @rmtoll ICR STOPCF LL_I2C_ClearFlag_STOP
<>	134:ad3be0349dc5	1760	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1761	* @retval None
<>	134:ad3be0349dc5	1762	*/
<>	134:ad3be0349dc5	1763	__STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	1764	{
<>	134:ad3be0349dc5	1765	SET_BIT(I2Cx->ICR, I2C_ICR_STOPCF);
<>	134:ad3be0349dc5	1766	}
<>	134:ad3be0349dc5	1767
<>	134:ad3be0349dc5	1768	/**
<>	134:ad3be0349dc5	1769	* @brief Clear Transmit data register empty flag (TXE).
<>	134:ad3be0349dc5	1770	* @note This bit can be clear by software in order to flush the transmit data register (TXDR).
<>	134:ad3be0349dc5	1771	* @rmtoll ISR TXE LL_I2C_ClearFlag_TXE
<>	134:ad3be0349dc5	1772	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1773	* @retval None
<>	134:ad3be0349dc5	1774	*/
<>	134:ad3be0349dc5	1775	__STATIC_INLINE void LL_I2C_ClearFlag_TXE(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	1776	{
<>	134:ad3be0349dc5	1777	WRITE_REG(I2Cx->ISR, I2C_ISR_TXE);
<>	134:ad3be0349dc5	1778	}
<>	134:ad3be0349dc5	1779
<>	134:ad3be0349dc5	1780	/**
<>	134:ad3be0349dc5	1781	* @brief Clear Bus error flag.
<>	134:ad3be0349dc5	1782	* @rmtoll ICR BERRCF LL_I2C_ClearFlag_BERR
<>	134:ad3be0349dc5	1783	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1784	* @retval None
<>	134:ad3be0349dc5	1785	*/
<>	134:ad3be0349dc5	1786	__STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	1787	{
<>	134:ad3be0349dc5	1788	SET_BIT(I2Cx->ICR, I2C_ICR_BERRCF);
<>	134:ad3be0349dc5	1789	}
<>	134:ad3be0349dc5	1790
<>	134:ad3be0349dc5	1791	/**
<>	134:ad3be0349dc5	1792	* @brief Clear Arbitration lost flag.
<>	134:ad3be0349dc5	1793	* @rmtoll ICR ARLOCF LL_I2C_ClearFlag_ARLO
<>	134:ad3be0349dc5	1794	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1795	* @retval None
<>	134:ad3be0349dc5	1796	*/
<>	134:ad3be0349dc5	1797	__STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	1798	{
<>	134:ad3be0349dc5	1799	SET_BIT(I2Cx->ICR, I2C_ICR_ARLOCF);
<>	134:ad3be0349dc5	1800	}
<>	134:ad3be0349dc5	1801
<>	134:ad3be0349dc5	1802	/**
<>	134:ad3be0349dc5	1803	* @brief Clear Overrun/Underrun flag.
<>	134:ad3be0349dc5	1804	* @rmtoll ICR OVRCF LL_I2C_ClearFlag_OVR
<>	134:ad3be0349dc5	1805	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1806	* @retval None
<>	134:ad3be0349dc5	1807	*/
<>	134:ad3be0349dc5	1808	__STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	1809	{
<>	134:ad3be0349dc5	1810	SET_BIT(I2Cx->ICR, I2C_ICR_OVRCF);
<>	134:ad3be0349dc5	1811	}
<>	134:ad3be0349dc5	1812
<>	134:ad3be0349dc5	1813	/**
<>	134:ad3be0349dc5	1814	* @brief Clear SMBus PEC error flag.
<>	134:ad3be0349dc5	1815	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	134:ad3be0349dc5	1816	* SMBus feature is supported by the I2Cx Instance.
<>	134:ad3be0349dc5	1817	* @rmtoll ICR PECCF LL_I2C_ClearSMBusFlag_PECERR
<>	134:ad3be0349dc5	1818	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1819	* @retval None
<>	134:ad3be0349dc5	1820	*/
<>	134:ad3be0349dc5	1821	__STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	1822	{
<>	134:ad3be0349dc5	1823	SET_BIT(I2Cx->ICR, I2C_ICR_PECCF);
<>	134:ad3be0349dc5	1824	}
<>	134:ad3be0349dc5	1825
<>	134:ad3be0349dc5	1826	/**
<>	134:ad3be0349dc5	1827	* @brief Clear SMBus Timeout detection flag.
<>	134:ad3be0349dc5	1828	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	134:ad3be0349dc5	1829	* SMBus feature is supported by the I2Cx Instance.
<>	134:ad3be0349dc5	1830	* @rmtoll ICR TIMOUTCF LL_I2C_ClearSMBusFlag_TIMEOUT
<>	134:ad3be0349dc5	1831	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1832	* @retval None
<>	134:ad3be0349dc5	1833	*/
<>	134:ad3be0349dc5	1834	__STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	1835	{
<>	134:ad3be0349dc5	1836	SET_BIT(I2Cx->ICR, I2C_ICR_TIMOUTCF);
<>	134:ad3be0349dc5	1837	}
<>	134:ad3be0349dc5	1838
<>	134:ad3be0349dc5	1839	/**
<>	134:ad3be0349dc5	1840	* @brief Clear SMBus Alert flag.
<>	134:ad3be0349dc5	1841	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	134:ad3be0349dc5	1842	* SMBus feature is supported by the I2Cx Instance.
<>	134:ad3be0349dc5	1843	* @rmtoll ICR ALERTCF LL_I2C_ClearSMBusFlag_ALERT
<>	134:ad3be0349dc5	1844	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1845	* @retval None
<>	134:ad3be0349dc5	1846	*/
<>	134:ad3be0349dc5	1847	__STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	1848	{
<>	134:ad3be0349dc5	1849	SET_BIT(I2Cx->ICR, I2C_ICR_ALERTCF);
<>	134:ad3be0349dc5	1850	}
<>	134:ad3be0349dc5	1851
<>	134:ad3be0349dc5	1852	/**
<>	134:ad3be0349dc5	1853	* @}
<>	134:ad3be0349dc5	1854	*/
<>	134:ad3be0349dc5	1855
<>	134:ad3be0349dc5	1856	/** @defgroup I2C_LL_EF_Data_Management Data_Management
<>	134:ad3be0349dc5	1857	* @{
<>	134:ad3be0349dc5	1858	*/
<>	134:ad3be0349dc5	1859
<>	134:ad3be0349dc5	1860	/**
<>	134:ad3be0349dc5	1861	* @brief Enable automatic STOP condition generation (master mode).
<>	134:ad3be0349dc5	1862	* @note Automatic end mode : a STOP condition is automatically sent when NBYTES data are transferred.
<>	134:ad3be0349dc5	1863	* This bit has no effect in slave mode or when RELOAD bit is set.
<>	134:ad3be0349dc5	1864	* @rmtoll CR2 AUTOEND LL_I2C_EnableAutoEndMode
<>	134:ad3be0349dc5	1865	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1866	* @retval None
<>	134:ad3be0349dc5	1867	*/
<>	134:ad3be0349dc5	1868	__STATIC_INLINE void LL_I2C_EnableAutoEndMode(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	1869	{
<>	134:ad3be0349dc5	1870	SET_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
<>	134:ad3be0349dc5	1871	}
<>	134:ad3be0349dc5	1872
<>	134:ad3be0349dc5	1873	/**
<>	134:ad3be0349dc5	1874	* @brief Disable automatic STOP condition generation (master mode).
<>	134:ad3be0349dc5	1875	* @note Software end mode : TC flag is set when NBYTES data are transferre, stretching SCL low.
<>	134:ad3be0349dc5	1876	* @rmtoll CR2 AUTOEND LL_I2C_DisableAutoEndMode
<>	134:ad3be0349dc5	1877	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1878	* @retval None
<>	134:ad3be0349dc5	1879	*/
<>	134:ad3be0349dc5	1880	__STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	1881	{
<>	134:ad3be0349dc5	1882	CLEAR_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
<>	134:ad3be0349dc5	1883	}
<>	134:ad3be0349dc5	1884
<>	134:ad3be0349dc5	1885	/**
<>	134:ad3be0349dc5	1886	* @brief Check if automatic STOP condition is enabled or disabled.
<>	134:ad3be0349dc5	1887	* @rmtoll CR2 AUTOEND LL_I2C_IsEnabledAutoEndMode
<>	134:ad3be0349dc5	1888	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1889	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1890	*/
<>	134:ad3be0349dc5	1891	__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	1892	{
<>	134:ad3be0349dc5	1893	return (READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND));
<>	134:ad3be0349dc5	1894	}
<>	134:ad3be0349dc5	1895
<>	134:ad3be0349dc5	1896	/**
<>	134:ad3be0349dc5	1897	* @brief Enable reload mode (master mode).
<>	134:ad3be0349dc5	1898	* @note The transfer is not completed after the NBYTES data transfer, NBYTES will be reloaded when TCR flag is set.
<>	134:ad3be0349dc5	1899	* @rmtoll CR2 RELOAD LL_I2C_EnableReloadMode
<>	134:ad3be0349dc5	1900	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1901	* @retval None
<>	134:ad3be0349dc5	1902	*/
<>	134:ad3be0349dc5	1903	__STATIC_INLINE void LL_I2C_EnableReloadMode(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	1904	{
<>	134:ad3be0349dc5	1905	SET_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
<>	134:ad3be0349dc5	1906	}
<>	134:ad3be0349dc5	1907
<>	134:ad3be0349dc5	1908	/**
<>	134:ad3be0349dc5	1909	* @brief Disable reload mode (master mode).
<>	134:ad3be0349dc5	1910	* @note The transfer is completed after the NBYTES data transfer(STOP or RESTART will follow).
<>	134:ad3be0349dc5	1911	* @rmtoll CR2 RELOAD LL_I2C_DisableReloadMode
<>	134:ad3be0349dc5	1912	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1913	* @retval None
<>	134:ad3be0349dc5	1914	*/
<>	134:ad3be0349dc5	1915	__STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	1916	{
<>	134:ad3be0349dc5	1917	CLEAR_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
<>	134:ad3be0349dc5	1918	}
<>	134:ad3be0349dc5	1919
<>	134:ad3be0349dc5	1920	/**
<>	134:ad3be0349dc5	1921	* @brief Check if reload mode is enabled or disabled.
<>	134:ad3be0349dc5	1922	* @rmtoll CR2 RELOAD LL_I2C_IsEnabledReloadMode
<>	134:ad3be0349dc5	1923	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1924	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	1925	*/
<>	134:ad3be0349dc5	1926	__STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	1927	{
<>	134:ad3be0349dc5	1928	return (READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD));
<>	134:ad3be0349dc5	1929	}
<>	134:ad3be0349dc5	1930
<>	134:ad3be0349dc5	1931	/**
<>	134:ad3be0349dc5	1932	* @brief Configure the number of bytes for transfer.
<>	134:ad3be0349dc5	1933	* @note Changing these bits when START bit is set is not allowed.
<>	134:ad3be0349dc5	1934	* @rmtoll CR2 NBYTES LL_I2C_SetTransferSize
<>	134:ad3be0349dc5	1935	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1936	* @param TransferSize This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
<>	134:ad3be0349dc5	1937	* @retval None
<>	134:ad3be0349dc5	1938	*/
<>	134:ad3be0349dc5	1939	__STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t TransferSize)
<>	134:ad3be0349dc5	1940	{
<>	134:ad3be0349dc5	1941	MODIFY_REG(I2Cx->CR2, I2C_CR2_NBYTES, TransferSize << I2C_POSITION_CR2_NBYTES);
<>	134:ad3be0349dc5	1942	}
<>	134:ad3be0349dc5	1943
<>	134:ad3be0349dc5	1944	/**
<>	134:ad3be0349dc5	1945	* @brief Get the number of bytes configured for transfer.
<>	134:ad3be0349dc5	1946	* @rmtoll CR2 NBYTES LL_I2C_GetTransferSize
<>	134:ad3be0349dc5	1947	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1948	* @retval Value between Min_Data=0x0 and Max_Data=0xFF
<>	134:ad3be0349dc5	1949	*/
<>	134:ad3be0349dc5	1950	__STATIC_INLINE uint32_t LL_I2C_GetTransferSize(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	1951	{
<>	134:ad3be0349dc5	1952	return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_POSITION_CR2_NBYTES);
<>	134:ad3be0349dc5	1953	}
<>	134:ad3be0349dc5	1954
<>	134:ad3be0349dc5	1955	/**
<>	134:ad3be0349dc5	1956	* @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
<>	134:ad3be0349dc5	1957	* @note Usage in Slave mode only.
<>	134:ad3be0349dc5	1958	* @rmtoll CR2 NACK LL_I2C_AcknowledgeNextData
<>	134:ad3be0349dc5	1959	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1960	* @param TypeAcknowledge This parameter can be one of the following values:
<>	134:ad3be0349dc5	1961	* @arg @ref LL_I2C_ACK
<>	134:ad3be0349dc5	1962	* @arg @ref LL_I2C_NACK
<>	134:ad3be0349dc5	1963	* @retval None
<>	134:ad3be0349dc5	1964	*/
<>	134:ad3be0349dc5	1965	__STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
<>	134:ad3be0349dc5	1966	{
<>	134:ad3be0349dc5	1967	MODIFY_REG(I2Cx->CR2, I2C_CR2_NACK, TypeAcknowledge);
<>	134:ad3be0349dc5	1968	}
<>	134:ad3be0349dc5	1969
<>	134:ad3be0349dc5	1970	/**
<>	134:ad3be0349dc5	1971	* @brief Generate a START or RESTART condition
<>	134:ad3be0349dc5	1972	* @note The START bit can be set even if bus is BUSY or I2C is in slave mode.
<>	134:ad3be0349dc5	1973	* This action has no effect when RELOAD is set.
<>	134:ad3be0349dc5	1974	* @rmtoll CR2 START LL_I2C_GenerateStartCondition
<>	134:ad3be0349dc5	1975	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1976	* @retval None
<>	134:ad3be0349dc5	1977	*/
<>	134:ad3be0349dc5	1978	__STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	1979	{
<>	134:ad3be0349dc5	1980	SET_BIT(I2Cx->CR2, I2C_CR2_START);
<>	134:ad3be0349dc5	1981	}
<>	134:ad3be0349dc5	1982
<>	134:ad3be0349dc5	1983	/**
<>	134:ad3be0349dc5	1984	* @brief Generate a STOP condition after the current byte transfer (master mode).
<>	134:ad3be0349dc5	1985	* @rmtoll CR2 STOP LL_I2C_GenerateStopCondition
<>	134:ad3be0349dc5	1986	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	1987	* @retval None
<>	134:ad3be0349dc5	1988	*/
<>	134:ad3be0349dc5	1989	__STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	1990	{
<>	134:ad3be0349dc5	1991	SET_BIT(I2Cx->CR2, I2C_CR2_STOP);
<>	134:ad3be0349dc5	1992	}
<>	134:ad3be0349dc5	1993
<>	134:ad3be0349dc5	1994	/**
<>	134:ad3be0349dc5	1995	* @brief Enable automatic RESTART Read request condition for 10bit address header (master mode).
<>	134:ad3be0349dc5	1996	* @note The master sends the complete 10bit slave address read sequence :
<>	134:ad3be0349dc5	1997	* Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address in Read direction.
<>	134:ad3be0349dc5	1998	* @rmtoll CR2 HEAD10R LL_I2C_EnableAuto10BitRead
<>	134:ad3be0349dc5	1999	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	2000	* @retval None
<>	134:ad3be0349dc5	2001	*/
<>	134:ad3be0349dc5	2002	__STATIC_INLINE void LL_I2C_EnableAuto10BitRead(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	2003	{
<>	134:ad3be0349dc5	2004	CLEAR_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
<>	134:ad3be0349dc5	2005	}
<>	134:ad3be0349dc5	2006
<>	134:ad3be0349dc5	2007	/**
<>	134:ad3be0349dc5	2008	* @brief Disable automatic RESTART Read request condition for 10bit address header (master mode).
<>	134:ad3be0349dc5	2009	* @note The master only sends the first 7 bits of 10bit address in Read direction.
<>	134:ad3be0349dc5	2010	* @rmtoll CR2 HEAD10R LL_I2C_DisableAuto10BitRead
<>	134:ad3be0349dc5	2011	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	2012	* @retval None
<>	134:ad3be0349dc5	2013	*/
<>	134:ad3be0349dc5	2014	__STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	2015	{
<>	134:ad3be0349dc5	2016	SET_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
<>	134:ad3be0349dc5	2017	}
<>	134:ad3be0349dc5	2018
<>	134:ad3be0349dc5	2019	/**
<>	134:ad3be0349dc5	2020	* @brief Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled.
<>	134:ad3be0349dc5	2021	* @rmtoll CR2 HEAD10R LL_I2C_IsEnabledAuto10BitRead
<>	134:ad3be0349dc5	2022	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	2023	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	2024	*/
<>	134:ad3be0349dc5	2025	__STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	2026	{
<>	134:ad3be0349dc5	2027	return (READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R));
<>	134:ad3be0349dc5	2028	}
<>	134:ad3be0349dc5	2029
<>	134:ad3be0349dc5	2030	/**
<>	134:ad3be0349dc5	2031	* @brief Configure the transfer direction (master mode).
<>	134:ad3be0349dc5	2032	* @note Changing these bits when START bit is set is not allowed.
<>	134:ad3be0349dc5	2033	* @rmtoll CR2 RD_WRN LL_I2C_SetTransferRequest
<>	134:ad3be0349dc5	2034	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	2035	* @param TransferRequest This parameter can be one of the following values:
<>	134:ad3be0349dc5	2036	* @arg @ref LL_I2C_REQUEST_WRITE
<>	134:ad3be0349dc5	2037	* @arg @ref LL_I2C_REQUEST_READ
<>	134:ad3be0349dc5	2038	* @retval None
<>	134:ad3be0349dc5	2039	*/
<>	134:ad3be0349dc5	2040	__STATIC_INLINE void LL_I2C_SetTransferRequest(I2C_TypeDef *I2Cx, uint32_t TransferRequest)
<>	134:ad3be0349dc5	2041	{
<>	134:ad3be0349dc5	2042	MODIFY_REG(I2Cx->CR2, I2C_CR2_RD_WRN, TransferRequest);
<>	134:ad3be0349dc5	2043	}
<>	134:ad3be0349dc5	2044
<>	134:ad3be0349dc5	2045	/**
<>	134:ad3be0349dc5	2046	* @brief Get the transfer direction requested (master mode).
<>	134:ad3be0349dc5	2047	* @rmtoll CR2 RD_WRN LL_I2C_GetTransferRequest
<>	134:ad3be0349dc5	2048	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	2049	* @retval Returned value can be one of the following values:
<>	134:ad3be0349dc5	2050	* @arg @ref LL_I2C_REQUEST_WRITE
<>	134:ad3be0349dc5	2051	* @arg @ref LL_I2C_REQUEST_READ
<>	134:ad3be0349dc5	2052	*/
<>	134:ad3be0349dc5	2053	__STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	2054	{
<>	134:ad3be0349dc5	2055	return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN));
<>	134:ad3be0349dc5	2056	}
<>	134:ad3be0349dc5	2057
<>	134:ad3be0349dc5	2058	/**
<>	134:ad3be0349dc5	2059	* @brief Configure the slave address for transfer (master mode).
<>	134:ad3be0349dc5	2060	* @note Changing these bits when START bit is set is not allowed.
<>	134:ad3be0349dc5	2061	* @rmtoll CR2 SADD LL_I2C_SetSlaveAddr
<>	134:ad3be0349dc5	2062	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	2063	* @param SlaveAddr This parameter must be a value between Min_Data=0x00 and Max_Data=0x3F.
<>	134:ad3be0349dc5	2064	* @retval None
<>	134:ad3be0349dc5	2065	*/
<>	134:ad3be0349dc5	2066	__STATIC_INLINE void LL_I2C_SetSlaveAddr(I2C_TypeDef *I2Cx, uint32_t SlaveAddr)
<>	134:ad3be0349dc5	2067	{
<>	134:ad3be0349dc5	2068	MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD, SlaveAddr);
<>	134:ad3be0349dc5	2069	}
<>	134:ad3be0349dc5	2070
<>	134:ad3be0349dc5	2071	/**
<>	134:ad3be0349dc5	2072	* @brief Get the slave address programmed for transfer.
<>	134:ad3be0349dc5	2073	* @rmtoll CR2 SADD LL_I2C_GetSlaveAddr
<>	134:ad3be0349dc5	2074	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	2075	* @retval Value between Min_Data=0x0 and Max_Data=0x3F
<>	134:ad3be0349dc5	2076	*/
<>	134:ad3be0349dc5	2077	__STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	2078	{
<>	134:ad3be0349dc5	2079	return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD));
<>	134:ad3be0349dc5	2080	}
<>	134:ad3be0349dc5	2081
<>	134:ad3be0349dc5	2082	/**
<>	134:ad3be0349dc5	2083	* @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
<>	134:ad3be0349dc5	2084	* @rmtoll CR2 SADD LL_I2C_HandleTransfer\n
<>	134:ad3be0349dc5	2085	* CR2 ADD10 LL_I2C_HandleTransfer\n
<>	134:ad3be0349dc5	2086	* CR2 RD_WRN LL_I2C_HandleTransfer\n
<>	134:ad3be0349dc5	2087	* CR2 START LL_I2C_HandleTransfer\n
<>	134:ad3be0349dc5	2088	* CR2 STOP LL_I2C_HandleTransfer\n
<>	134:ad3be0349dc5	2089	* CR2 RELOAD LL_I2C_HandleTransfer\n
<>	134:ad3be0349dc5	2090	* CR2 NBYTES LL_I2C_HandleTransfer\n
<>	134:ad3be0349dc5	2091	* CR2 AUTOEND LL_I2C_HandleTransfer\n
<>	134:ad3be0349dc5	2092	* CR2 HEAD10R LL_I2C_HandleTransfer
<>	134:ad3be0349dc5	2093	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	2094	* @param SlaveAddr Specifies the slave address to be programmed.
<>	134:ad3be0349dc5	2095	* @param SlaveAddrSize This parameter can be one of the following values:
<>	134:ad3be0349dc5	2096	* @arg @ref LL_I2C_ADDRSLAVE_7BIT
<>	134:ad3be0349dc5	2097	* @arg @ref LL_I2C_ADDRSLAVE_10BIT
<>	134:ad3be0349dc5	2098	* @param TransferSize Specifies the number of bytes to be programmed.
<>	134:ad3be0349dc5	2099	* This parameter must be a value between Min_Data=0 and Max_Data=255.
<>	134:ad3be0349dc5	2100	* @param EndMode This parameter can be one of the following values:
<>	134:ad3be0349dc5	2101	* @arg @ref LL_I2C_MODE_RELOAD
<>	134:ad3be0349dc5	2102	* @arg @ref LL_I2C_MODE_AUTOEND
<>	134:ad3be0349dc5	2103	* @arg @ref LL_I2C_MODE_SOFTEND
<>	134:ad3be0349dc5	2104	* @arg @ref LL_I2C_MODE_SMBUS_RELOAD
<>	134:ad3be0349dc5	2105	* @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC
<>	134:ad3be0349dc5	2106	* @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC
<>	134:ad3be0349dc5	2107	* @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC
<>	134:ad3be0349dc5	2108	* @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC
<>	134:ad3be0349dc5	2109	* @param Request This parameter can be one of the following values:
<>	134:ad3be0349dc5	2110	* @arg @ref LL_I2C_GENERATE_NOSTARTSTOP
<>	134:ad3be0349dc5	2111	* @arg @ref LL_I2C_GENERATE_STOP
<>	134:ad3be0349dc5	2112	* @arg @ref LL_I2C_GENERATE_START_READ
<>	134:ad3be0349dc5	2113	* @arg @ref LL_I2C_GENERATE_START_WRITE
<>	134:ad3be0349dc5	2114	* @arg @ref LL_I2C_GENERATE_RESTART_7BIT_READ
<>	134:ad3be0349dc5	2115	* @arg @ref LL_I2C_GENERATE_RESTART_7BIT_WRITE
<>	134:ad3be0349dc5	2116	* @arg @ref LL_I2C_GENERATE_RESTART_10BIT_READ
<>	134:ad3be0349dc5	2117	* @arg @ref LL_I2C_GENERATE_RESTART_10BIT_WRITE
<>	134:ad3be0349dc5	2118	* @retval None
<>	134:ad3be0349dc5	2119	*/
<>	134:ad3be0349dc5	2120	__STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize,
<>	134:ad3be0349dc5	2121	uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
<>	134:ad3be0349dc5	2122	{
<>	134:ad3be0349dc5	2123	MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD \| I2C_CR2_ADD10 \| I2C_CR2_RD_WRN \| I2C_CR2_START \| I2C_CR2_STOP \| I2C_CR2_RELOAD \|
<>	134:ad3be0349dc5	2124	I2C_CR2_NBYTES \| I2C_CR2_AUTOEND \| I2C_CR2_HEAD10R,
<>	134:ad3be0349dc5	2125	SlaveAddr \| SlaveAddrSize \| TransferSize << I2C_POSITION_CR2_NBYTES \| EndMode \| Request);
<>	134:ad3be0349dc5	2126	}
<>	134:ad3be0349dc5	2127
<>	134:ad3be0349dc5	2128	/**
<>	134:ad3be0349dc5	2129	* @brief Indicate the value of transfer direction (slave mode).
<>	134:ad3be0349dc5	2130	* @note RESET: Write transfer, Slave enters in receiver mode.
<>	134:ad3be0349dc5	2131	* SET: Read transfer, Slave enters in transmitter mode.
<>	134:ad3be0349dc5	2132	* @rmtoll ISR DIR LL_I2C_GetTransferDirection
<>	134:ad3be0349dc5	2133	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	2134	* @retval Returned value can be one of the following values:
<>	134:ad3be0349dc5	2135	* @arg @ref LL_I2C_DIRECTION_WRITE
<>	134:ad3be0349dc5	2136	* @arg @ref LL_I2C_DIRECTION_READ
<>	134:ad3be0349dc5	2137	*/
<>	134:ad3be0349dc5	2138	__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	2139	{
<>	134:ad3be0349dc5	2140	return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR));
<>	134:ad3be0349dc5	2141	}
<>	134:ad3be0349dc5	2142
<>	134:ad3be0349dc5	2143	/**
<>	134:ad3be0349dc5	2144	* @brief Return the slave matched address.
<>	134:ad3be0349dc5	2145	* @rmtoll ISR ADDCODE LL_I2C_GetAddressMatchCode
<>	134:ad3be0349dc5	2146	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	2147	* @retval Value between Min_Data=0x00 and Max_Data=0x3F
<>	134:ad3be0349dc5	2148	*/
<>	134:ad3be0349dc5	2149	__STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	2150	{
<>	134:ad3be0349dc5	2151	return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_POSITION_ISR_ADDCODE << 1);
<>	134:ad3be0349dc5	2152	}
<>	134:ad3be0349dc5	2153
<>	134:ad3be0349dc5	2154	/**
<>	134:ad3be0349dc5	2155	* @brief Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode).
<>	134:ad3be0349dc5	2156	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	134:ad3be0349dc5	2157	* SMBus feature is supported by the I2Cx Instance.
<>	134:ad3be0349dc5	2158	* @note This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition or an Address Matched is received.
<>	134:ad3be0349dc5	2159	* This bit has no effect when RELOAD bit is set.
<>	134:ad3be0349dc5	2160	* This bit has no effect in device mode when SBC bit is not set.
<>	134:ad3be0349dc5	2161	* @rmtoll CR2 PECBYTE LL_I2C_EnableSMBusPECCompare
<>	134:ad3be0349dc5	2162	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	2163	* @retval None
<>	134:ad3be0349dc5	2164	*/
<>	134:ad3be0349dc5	2165	__STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	2166	{
<>	134:ad3be0349dc5	2167	SET_BIT(I2Cx->CR2, I2C_CR2_PECBYTE);
<>	134:ad3be0349dc5	2168	}
<>	134:ad3be0349dc5	2169
<>	134:ad3be0349dc5	2170	/**
<>	134:ad3be0349dc5	2171	* @brief Check if the SMBus Packet Error byte internal comparison is requested or not.
<>	134:ad3be0349dc5	2172	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	134:ad3be0349dc5	2173	* SMBus feature is supported by the I2Cx Instance.
<>	134:ad3be0349dc5	2174	* @rmtoll CR2 PECBYTE LL_I2C_IsEnabledSMBusPECCompare
<>	134:ad3be0349dc5	2175	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	2176	* @retval State of bit (1 or 0).
<>	134:ad3be0349dc5	2177	*/
<>	134:ad3be0349dc5	2178	__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	2179	{
<>	134:ad3be0349dc5	2180	return (READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE));
<>	134:ad3be0349dc5	2181	}
<>	134:ad3be0349dc5	2182
<>	134:ad3be0349dc5	2183	/**
<>	134:ad3be0349dc5	2184	* @brief Get the SMBus Packet Error byte calculated.
<>	134:ad3be0349dc5	2185	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	134:ad3be0349dc5	2186	* SMBus feature is supported by the I2Cx Instance.
<>	134:ad3be0349dc5	2187	* @rmtoll PECR PEC LL_I2C_GetSMBusPEC
<>	134:ad3be0349dc5	2188	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	2189	* @retval Value between Min_Data=0x00 and Max_Data=0xFF
<>	134:ad3be0349dc5	2190	*/
<>	134:ad3be0349dc5	2191	__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	2192	{
<>	134:ad3be0349dc5	2193	return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC));
<>	134:ad3be0349dc5	2194	}
<>	134:ad3be0349dc5	2195
<>	134:ad3be0349dc5	2196	/**
<>	134:ad3be0349dc5	2197	* @brief Read Receive Data register.
<>	134:ad3be0349dc5	2198	* @rmtoll RXDR RXDATA LL_I2C_ReceiveData8
<>	134:ad3be0349dc5	2199	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	2200	* @retval Value between Min_Data=0x00 and Max_Data=0xFF
<>	134:ad3be0349dc5	2201	*/
<>	134:ad3be0349dc5	2202	__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx)
<>	134:ad3be0349dc5	2203	{
<>	134:ad3be0349dc5	2204	return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA));
<>	134:ad3be0349dc5	2205	}
<>	134:ad3be0349dc5	2206
<>	134:ad3be0349dc5	2207	/**
<>	134:ad3be0349dc5	2208	* @brief Write in Transmit Data Register .
<>	134:ad3be0349dc5	2209	* @rmtoll TXDR TXDATA LL_I2C_TransmitData8
<>	134:ad3be0349dc5	2210	* @param I2Cx I2C Instance.
<>	134:ad3be0349dc5	2211	* @param Data Value between Min_Data=0x00 and Max_Data=0xFF
<>	134:ad3be0349dc5	2212	* @retval None
<>	134:ad3be0349dc5	2213	*/
<>	134:ad3be0349dc5	2214	__STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
<>	134:ad3be0349dc5	2215	{
<>	134:ad3be0349dc5	2216	WRITE_REG(I2Cx->TXDR, Data);
<>	134:ad3be0349dc5	2217	}
<>	134:ad3be0349dc5	2218
<>	134:ad3be0349dc5	2219	/**
<>	134:ad3be0349dc5	2220	* @}
<>	134:ad3be0349dc5	2221	*/
<>	134:ad3be0349dc5	2222
<>	134:ad3be0349dc5	2223	#if defined(USE_FULL_LL_DRIVER)
<>	134:ad3be0349dc5	2224	/** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
<>	134:ad3be0349dc5	2225	* @{
<>	134:ad3be0349dc5	2226	*/
<>	134:ad3be0349dc5	2227
<>	134:ad3be0349dc5	2228	uint32_t LL_I2C_Init(I2C_TypeDef I2Cx, LL_I2C_InitTypeDef I2C_InitStruct);
<>	134:ad3be0349dc5	2229	uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx);
<>	134:ad3be0349dc5	2230	void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
<>	134:ad3be0349dc5	2231
<>	134:ad3be0349dc5	2232
<>	134:ad3be0349dc5	2233	/**
<>	134:ad3be0349dc5	2234	* @}
<>	134:ad3be0349dc5	2235	*/
<>	134:ad3be0349dc5	2236	#endif /* USE_FULL_LL_DRIVER */
<>	134:ad3be0349dc5	2237
<>	134:ad3be0349dc5	2238	/**
<>	134:ad3be0349dc5	2239	* @}
<>	134:ad3be0349dc5	2240	*/
<>	134:ad3be0349dc5	2241
<>	134:ad3be0349dc5	2242	/**
<>	134:ad3be0349dc5	2243	* @}
<>	134:ad3be0349dc5	2244	*/
<>	134:ad3be0349dc5	2245
<>	134:ad3be0349dc5	2246	#endif /* I2C1 \|\| I2C2 */
<>	134:ad3be0349dc5	2247
<>	134:ad3be0349dc5	2248	/**
<>	134:ad3be0349dc5	2249	* @}
<>	134:ad3be0349dc5	2250	*/
<>	134:ad3be0349dc5	2251
<>	134:ad3be0349dc5	2252	#ifdef __cplusplus
<>	134:ad3be0349dc5	2253	}
<>	134:ad3be0349dc5	2254	#endif
<>	134:ad3be0349dc5	2255
<>	134:ad3be0349dc5	2256	#endif /* __STM32F0xx_LL_I2C_H */
<>	134:ad3be0349dc5	2257
<>	134:ad3be0349dc5	2258	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/