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Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

TARGET_NCS36510/TARGET_ONSEMI/TARGET_NCS36510/spi_ipc7207_map.h@126:abea610beb85, 2016-09-16 (annotated)

Committer:
AnnaBridge
Date:
Fri Sep 16 13:57:13 2016 +0100
Revision:
126:abea610beb85
Parent:
125:2e9cc70d1897 
Release 126 of the mbed library



Changes:



New Targets:

#2504: [Disco_F769NI] adding new target [https://github.com/ARMmbed/mbed-os/pull/2504]

#2654: DELTA_DFBM_NQ620 platform porting [https://github.com/ARMmbed/mbed-os/pull/2654]

#2615: [MTM_MTCONNECT04S] Added support for MTM_MTCONNECT04S [https://github.com/ARMmbed/mbed-os/pull/2615]

#2548: Nucleof303ze [https://github.com/ARMmbed/mbed-os/pull/2548]



Fixes:



#2657: [MAX326xx] Removed echoing of characters and carriage return. [https://github.com/ARMmbed/mbed-os/pull/2657]

#2651: Use lp_timer to count time in the deepsleep tests [https://github.com/ARMmbed/mbed-os/pull/2651]

#2643: Fix thread self termination [https://github.com/ARMmbed/mbed-os/pull/2643]

#2623: DISCO_L476VG - Add Serial Flow Control pins + add SERIAL_FC macro [https://github.com/ARMmbed/mbed-os/pull/2623]

#2617: STM32F2xx - Enable Serial Flow Control [https://github.com/ARMmbed/mbed-os/pull/2617]

#2601: Adding ON Semiconductor copyright notice to source and header files. [https://github.com/ARMmbed/mbed-os/pull/2601]

#2597: [HAL] Fixed "intrinsic is deprecated" warnings [https://github.com/ARMmbed/mbed-os/pull/2597]

#2589: [NUC472] Fix heap configuration error with armcc [https://github.com/ARMmbed/mbed-os/pull/2589]

#2587: add PTEx pins as option for SPI on Hexiwear - for SD Card Interface [https://github.com/ARMmbed/mbed-os/pull/2587]

#2584: Set size of callback irq array to IrqCnt [https://github.com/ARMmbed/mbed-os/pull/2584]

#2582: [GCC_CR] fix runtime hang for baremetal build [https://github.com/ARMmbed/mbed-os/pull/2582]

#2562: Fix GCC lazy init race condition and add test [https://github.com/ARMmbed/mbed-os/pull/2562]

#2538: STM32F4xx - Add support of ADC internal channels (Temp, VRef, VBat) [https://github.com/ARMmbed/mbed-os/pull/2538]

#2514: Updated FlexCan and SAI SDK drivers [https://github.com/ARMmbed/mbed-os/pull/2514]

#2442: Malloc heap info [https://github.com/ARMmbed/mbed-os/pull/2442]

#2419: [STM32F1] Add asynchronous serial [https://github.com/ARMmbed/mbed-os/pull/2419]

#2130: stm32 : reduce number of device.h files [https://github.com/ARMmbed/mbed-os/pull/2130]

#2678: Fixing NCS36510 compile on Linux [https://github.com/ARMmbed/mbed-os/pull/2678]

#2607: Fix uvisor memory tracing [https://github.com/ARMmbed/mbed-os/pull/2607]

#2596: [HAL] Improve memory tracer [https://github.com/ARMmbed/mbed-os/pull/2596]

#2487: Runtime dynamic memory tracing [https://github.com/ARMmbed/mbed-os/pull/2487]

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 125:2e9cc70d1897 1 /**
AnnaBridge 125:2e9cc70d1897 2 ******************************************************************************
AnnaBridge 125:2e9cc70d1897 3 * @file spi_ipc7207_map.h
AnnaBridge 125:2e9cc70d1897 4 * @brief SPI IPC 7207 HW register map
AnnaBridge 125:2e9cc70d1897 5 * @internal
AnnaBridge 125:2e9cc70d1897 6 * @author ON Semiconductor
AnnaBridge 125:2e9cc70d1897 7 * $Rev: 2110 $
AnnaBridge 125:2e9cc70d1897 8 * $Date: 2013-07-16 20:13:03 +0530 (Tue, 16 Jul 2013) $
AnnaBridge 125:2e9cc70d1897 9 ******************************************************************************
AnnaBridge 126:abea610beb85 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
AnnaBridge 126:abea610beb85 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
AnnaBridge 126:abea610beb85 12 * under limited terms and conditions. The terms and conditions pertaining to the software
AnnaBridge 126:abea610beb85 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
AnnaBridge 126:abea610beb85 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
AnnaBridge 126:abea610beb85 15 * if applicable the software license agreement. Do not use this software and/or
AnnaBridge 126:abea610beb85 16 * documentation unless you have carefully read and you agree to the limited terms and
AnnaBridge 126:abea610beb85 17 * conditions. By using this software and/or documentation, you agree to the limited
AnnaBridge 126:abea610beb85 18 * terms and conditions.
AnnaBridge 125:2e9cc70d1897 19 *
AnnaBridge 125:2e9cc70d1897 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
AnnaBridge 125:2e9cc70d1897 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
AnnaBridge 125:2e9cc70d1897 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
AnnaBridge 125:2e9cc70d1897 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
AnnaBridge 125:2e9cc70d1897 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
AnnaBridge 125:2e9cc70d1897 25 * @endinternal
AnnaBridge 125:2e9cc70d1897 26 *
AnnaBridge 125:2e9cc70d1897 27 * @ingroup spi_ipc7207
AnnaBridge 125:2e9cc70d1897 28 *
AnnaBridge 125:2e9cc70d1897 29 * @details
AnnaBridge 125:2e9cc70d1897 30 * <p>
AnnaBridge 125:2e9cc70d1897 31 * SPI HW register map description
AnnaBridge 125:2e9cc70d1897 32 * </p>
AnnaBridge 125:2e9cc70d1897 33 *
AnnaBridge 125:2e9cc70d1897 34 * <h1> Reference document(s) </h1>
AnnaBridge 125:2e9cc70d1897 35 * <p>
AnnaBridge 125:2e9cc70d1897 36 * <a href="../pdf/IPC7207_SPI_APB_DS_v1P2.pdf" target="_blank">
AnnaBridge 125:2e9cc70d1897 37 * IPC7207 APB SPI Design Specification v1.2 </a>
AnnaBridge 125:2e9cc70d1897 38 * </p>
AnnaBridge 125:2e9cc70d1897 39 */
AnnaBridge 125:2e9cc70d1897 40
AnnaBridge 125:2e9cc70d1897 41 #ifndef SPI_IPC7207_MAP_H_
AnnaBridge 125:2e9cc70d1897 42 #define SPI_IPC7207_MAP_H_
AnnaBridge 125:2e9cc70d1897 43
AnnaBridge 125:2e9cc70d1897 44 #include "architecture.h"
AnnaBridge 125:2e9cc70d1897 45
AnnaBridge 125:2e9cc70d1897 46 /** SPI HW Structure Overlay */
AnnaBridge 125:2e9cc70d1897 47 typedef struct {
AnnaBridge 125:2e9cc70d1897 48 __O uint32_t TX_DATA;
AnnaBridge 125:2e9cc70d1897 49 __I uint32_t RX_DATA;
AnnaBridge 125:2e9cc70d1897 50 __IO uint32_t FDIV;
AnnaBridge 125:2e9cc70d1897 51 union {
AnnaBridge 125:2e9cc70d1897 52 struct {
AnnaBridge 125:2e9cc70d1897 53 __IO uint32_t ENABLE :1; /**< SPI port enable: 0 = disable , 1 = enable */
AnnaBridge 125:2e9cc70d1897 54 __IO uint32_t SAMPLING_EDGE :1; /**< SDI sampling edge: 0 = opposite to SDO edge / 1 = same as SDO edge */
AnnaBridge 125:2e9cc70d1897 55 __IO uint32_t ENDIAN :1; /**< Bits endianness: 0 = LSB first (little-endian) / 1 = MSB first (big-endian) */
AnnaBridge 125:2e9cc70d1897 56 __IO uint32_t CPHA :1; /**< Clock phase: 0 = SDO set before first SCLK edge / 1 = SDO set after first SCLK edge */
AnnaBridge 125:2e9cc70d1897 57 __IO uint32_t CPOL :1; /**< Clock polarity: 0 = active high / 1 = active low */
AnnaBridge 125:2e9cc70d1897 58 __IO uint32_t MODE :1; /**< Device mode: 0 = slave mode / 1 = master mode */
AnnaBridge 125:2e9cc70d1897 59 __IO uint32_t WORD_WIDTH :2; /**< Word width: 0 = 8b / 1 = 16b / 2 = 32b / 3 = reserved */
AnnaBridge 125:2e9cc70d1897 60 } BITS;
AnnaBridge 125:2e9cc70d1897 61 __IO uint32_t WORD;
AnnaBridge 125:2e9cc70d1897 62 } CONTROL;
AnnaBridge 125:2e9cc70d1897 63 union {
AnnaBridge 125:2e9cc70d1897 64 struct {
AnnaBridge 125:2e9cc70d1897 65 __I uint32_t XFER_IP :1; /**< Transfer in progress: 0 = No transfer in progress / 1 = transfer in progress */
AnnaBridge 125:2e9cc70d1897 66 __I uint32_t XFER_ERROR :1;/**< Transfer error: 0 = no error / 1 = SPI Overflow or Underflow */
AnnaBridge 125:2e9cc70d1897 67 __I uint32_t TX_EMPTY :1; /**< Transmit FIFO/buffer empty flag: 0 = not empty / 1 = empty */
AnnaBridge 125:2e9cc70d1897 68 __I uint32_t TX_HALF :1; /**< Transmit FIFO/buffer "half full" flag: 0 = (< half full) / 1 = (>= half full) */
AnnaBridge 125:2e9cc70d1897 69 __I uint32_t TX_FULL :1; /**< Transmit FIFO/buffer full flag: 0 = not full / 1 = full */
AnnaBridge 125:2e9cc70d1897 70 __I uint32_t RX_EMPTY :1; /**< Receive FIFO/buffer empty flag: 0 = not empty / 1 = empty */
AnnaBridge 125:2e9cc70d1897 71 __I uint32_t RX_HALF :1; /**< Receive FIFO/buffer "half full" flag: 0 = (< half full) / 1 = (>= half full) */
AnnaBridge 125:2e9cc70d1897 72 __I uint32_t RX_FULL :1; /**< Receive FIFO/buffer full flag: 0 = not full / 1 = full */
AnnaBridge 125:2e9cc70d1897 73 } BITS;
AnnaBridge 125:2e9cc70d1897 74 __I uint32_t WORD;
AnnaBridge 125:2e9cc70d1897 75 } STATUS;
AnnaBridge 125:2e9cc70d1897 76 union {
AnnaBridge 125:2e9cc70d1897 77 struct {
AnnaBridge 125:2e9cc70d1897 78 __IO uint32_t SS_ENABLE :4; /**< Slave Select (x4): 0 = disable / 1 = enable */
AnnaBridge 125:2e9cc70d1897 79 __IO uint32_t SS_BURST :1; /**< Slave Select burst mode (maintain SS active if TXFIFO not empty) */
AnnaBridge 125:2e9cc70d1897 80 } BITS;
AnnaBridge 125:2e9cc70d1897 81 __IO uint32_t WORD;
AnnaBridge 125:2e9cc70d1897 82 } SLAVE_SELECT;
AnnaBridge 125:2e9cc70d1897 83 __IO uint32_t SLAVE_SELECT_POLARITY; /**< Slave Select polarity for up to 4 slaves:0 = active low / 1 = active high */
AnnaBridge 125:2e9cc70d1897 84 __IO uint32_t IRQ_ENABLE; /**< IRQ (x8) enable: 0 = disable / 1 = enable */
AnnaBridge 125:2e9cc70d1897 85 __I uint32_t IRQ_STATUS; /**< IRQ (x8) status: 0 = no IRQ occurred / 1 = IRQ occurred */
AnnaBridge 125:2e9cc70d1897 86 __O uint32_t IRQ_CLEAR; /**< IRQ (x8) clearing: write 1 to clear IRQ */
AnnaBridge 125:2e9cc70d1897 87 __IO uint32_t TX_WATERMARK; /**< Transmit FIFO Watermark: Defines level of RX Half Full Flag */
AnnaBridge 125:2e9cc70d1897 88 __IO uint32_t RX_WATERMARK; /**< Receive FIFO Watermark: Defines level of TX Half Full Flag */
AnnaBridge 125:2e9cc70d1897 89 __I uint32_t TX_FIFO_LEVEL; /**< Transmit FIFO Level: Indicates actual fill level of TX FIFO. */
AnnaBridge 125:2e9cc70d1897 90 __I uint32_t RX_FIFO_LEVEL; /**< Transmit FIFO Level: Indicates actual fill level of RX FIFO. */
AnnaBridge 125:2e9cc70d1897 91 } SpiIpc7207Reg_t, *SpiIpc7207Reg_pt;
AnnaBridge 125:2e9cc70d1897 92
AnnaBridge 125:2e9cc70d1897 93 #endif /* SPI_IPC7207_MAP_H_ */