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TARGET_DISCO_L053C8/stm32_hal_legacy.h@119:aae6fcc7d9bb, 2016-04-27 (annotated)

Committer:
Kojto
Date:
Wed Apr 27 12:10:56 2016 -0500
Revision:
119:aae6fcc7d9bb
Parent:
99:dbbf35b96557 
Release 119 of the mbed library



Changes:

- new targets - EFM32PG_STK3401, NUCLEO_L031K6

- ST - hwflwctl support for NUCLEO_L476RG

     - Update STM32CUBE_L0 from v1.2 to v1.5

     - STM32F7 - bugfix - The weak function HAL_Delay is overwritten to use us ticker API.

- Maxim - Fixing the send break for the MAXWSNENV and MAX32600MBED

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 99:dbbf35b96557 1 /**
Kojto 99:dbbf35b96557 2 ******************************************************************************
Kojto 99:dbbf35b96557 3 * @file stm32_hal_legacy.h
Kojto 99:dbbf35b96557 4 * @author MCD Application Team
Kojto 119:aae6fcc7d9bb 5 * @version V1.5.0
Kojto 119:aae6fcc7d9bb 6 * @date 8-January-2016
Kojto 99:dbbf35b96557 7 * @brief This file contains aliases definition for the STM32Cube HAL constants
Kojto 99:dbbf35b96557 8 * macros and functions maintained for legacy purpose.
Kojto 99:dbbf35b96557 9 ******************************************************************************
Kojto 99:dbbf35b96557 10 * @attention
Kojto 99:dbbf35b96557 11 *
Kojto 119:aae6fcc7d9bb 12 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
Kojto 99:dbbf35b96557 13 *
Kojto 99:dbbf35b96557 14 * Redistribution and use in source and binary forms, with or without modification,
Kojto 99:dbbf35b96557 15 * are permitted provided that the following conditions are met:
Kojto 99:dbbf35b96557 16 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 99:dbbf35b96557 17 * this list of conditions and the following disclaimer.
Kojto 99:dbbf35b96557 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 99:dbbf35b96557 19 * this list of conditions and the following disclaimer in the documentation
Kojto 99:dbbf35b96557 20 * and/or other materials provided with the distribution.
Kojto 99:dbbf35b96557 21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto 99:dbbf35b96557 22 * may be used to endorse or promote products derived from this software
Kojto 99:dbbf35b96557 23 * without specific prior written permission.
Kojto 99:dbbf35b96557 24 *
Kojto 99:dbbf35b96557 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 99:dbbf35b96557 26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 99:dbbf35b96557 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 99:dbbf35b96557 28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 99:dbbf35b96557 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 99:dbbf35b96557 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 99:dbbf35b96557 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 99:dbbf35b96557 32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 119:aae6fcc7d9bb 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 99:dbbf35b96557 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 99:dbbf35b96557 35 *
Kojto 99:dbbf35b96557 36 ******************************************************************************
Kojto 99:dbbf35b96557 37 */
Kojto 99:dbbf35b96557 38
Kojto 99:dbbf35b96557 39 /* Define to prevent recursive inclusion -------------------------------------*/
Kojto 99:dbbf35b96557 40 #ifndef __STM32_HAL_LEGACY
Kojto 99:dbbf35b96557 41 #define __STM32_HAL_LEGACY
Kojto 99:dbbf35b96557 42
Kojto 99:dbbf35b96557 43 #ifdef __cplusplus
Kojto 99:dbbf35b96557 44 extern "C" {
Kojto 99:dbbf35b96557 45 #endif
Kojto 99:dbbf35b96557 46
Kojto 99:dbbf35b96557 47 /* Includes ------------------------------------------------------------------*/
Kojto 99:dbbf35b96557 48 /* Exported types ------------------------------------------------------------*/
Kojto 99:dbbf35b96557 49 /* Exported constants --------------------------------------------------------*/
Kojto 99:dbbf35b96557 50
Kojto 99:dbbf35b96557 51 /** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
Kojto 99:dbbf35b96557 52 * @{
Kojto 99:dbbf35b96557 53 */
Kojto 119:aae6fcc7d9bb 54 #define AES_FLAG_RDERR CRYP_FLAG_RDERR
Kojto 119:aae6fcc7d9bb 55 #define AES_FLAG_WRERR CRYP_FLAG_WRERR
Kojto 99:dbbf35b96557 56 #define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
Kojto 99:dbbf35b96557 57 #define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
Kojto 99:dbbf35b96557 58 #define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
Kojto 99:dbbf35b96557 59
Kojto 99:dbbf35b96557 60 /**
Kojto 99:dbbf35b96557 61 * @}
Kojto 99:dbbf35b96557 62 */
Kojto 99:dbbf35b96557 63
Kojto 99:dbbf35b96557 64 /** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
Kojto 99:dbbf35b96557 65 * @{
Kojto 99:dbbf35b96557 66 */
Kojto 99:dbbf35b96557 67 #define ADC_RESOLUTION12b ADC_RESOLUTION_12B
Kojto 99:dbbf35b96557 68 #define ADC_RESOLUTION10b ADC_RESOLUTION_10B
Kojto 99:dbbf35b96557 69 #define ADC_RESOLUTION8b ADC_RESOLUTION_8B
Kojto 99:dbbf35b96557 70 #define ADC_RESOLUTION6b ADC_RESOLUTION_6B
Kojto 99:dbbf35b96557 71 #define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN
Kojto 99:dbbf35b96557 72 #define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED
Kojto 99:dbbf35b96557 73 #define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV
Kojto 99:dbbf35b96557 74 #define EOC_SEQ_CONV ADC_EOC_SEQ_CONV
Kojto 99:dbbf35b96557 75 #define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV
Kojto 99:dbbf35b96557 76 #define REGULAR_GROUP ADC_REGULAR_GROUP
Kojto 99:dbbf35b96557 77 #define INJECTED_GROUP ADC_INJECTED_GROUP
Kojto 99:dbbf35b96557 78 #define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP
Kojto 99:dbbf35b96557 79 #define AWD_EVENT ADC_AWD_EVENT
Kojto 99:dbbf35b96557 80 #define AWD1_EVENT ADC_AWD1_EVENT
Kojto 99:dbbf35b96557 81 #define AWD2_EVENT ADC_AWD2_EVENT
Kojto 99:dbbf35b96557 82 #define AWD3_EVENT ADC_AWD3_EVENT
Kojto 99:dbbf35b96557 83 #define OVR_EVENT ADC_OVR_EVENT
Kojto 99:dbbf35b96557 84 #define JQOVF_EVENT ADC_JQOVF_EVENT
Kojto 99:dbbf35b96557 85 #define ALL_CHANNELS ADC_ALL_CHANNELS
Kojto 99:dbbf35b96557 86 #define REGULAR_CHANNELS ADC_REGULAR_CHANNELS
Kojto 99:dbbf35b96557 87 #define INJECTED_CHANNELS ADC_INJECTED_CHANNELS
Kojto 99:dbbf35b96557 88 #define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR
Kojto 99:dbbf35b96557 89 #define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT
Kojto 99:dbbf35b96557 90 #define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1
Kojto 99:dbbf35b96557 91 #define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2
Kojto 99:dbbf35b96557 92 #define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4
Kojto 119:aae6fcc7d9bb 93 #define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6
Kojto 119:aae6fcc7d9bb 94 #define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8
Kojto 99:dbbf35b96557 95 #define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO
Kojto 99:dbbf35b96557 96 #define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2
Kojto 99:dbbf35b96557 97 #define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO
Kojto 99:dbbf35b96557 98 #define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4
Kojto 99:dbbf35b96557 99 #define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO
Kojto 99:dbbf35b96557 100 #define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11
Kojto 99:dbbf35b96557 101 #define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1
Kojto 99:dbbf35b96557 102 #define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE
Kojto 99:dbbf35b96557 103 #define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING
Kojto 99:dbbf35b96557 104 #define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING
Kojto 119:aae6fcc7d9bb 105 #define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
Kojto 119:aae6fcc7d9bb 106 #define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5
Kojto 119:aae6fcc7d9bb 107
Kojto 119:aae6fcc7d9bb 108 #define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY
Kojto 119:aae6fcc7d9bb 109 #define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY
Kojto 119:aae6fcc7d9bb 110 #define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC
Kojto 119:aae6fcc7d9bb 111 #define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC
Kojto 119:aae6fcc7d9bb 112 #define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL
Kojto 119:aae6fcc7d9bb 113 #define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL
Kojto 119:aae6fcc7d9bb 114 #define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1
Kojto 99:dbbf35b96557 115 /**
Kojto 99:dbbf35b96557 116 * @}
Kojto 99:dbbf35b96557 117 */
Kojto 99:dbbf35b96557 118
Kojto 99:dbbf35b96557 119 /** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
Kojto 99:dbbf35b96557 120 * @{
Kojto 99:dbbf35b96557 121 */
Kojto 99:dbbf35b96557 122
Kojto 99:dbbf35b96557 123 #define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
Kojto 99:dbbf35b96557 124
Kojto 99:dbbf35b96557 125 /**
Kojto 99:dbbf35b96557 126 * @}
Kojto 99:dbbf35b96557 127 */
Kojto 99:dbbf35b96557 128
Kojto 99:dbbf35b96557 129 /** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
Kojto 99:dbbf35b96557 130 * @{
Kojto 99:dbbf35b96557 131 */
Kojto 99:dbbf35b96557 132
Kojto 119:aae6fcc7d9bb 133 #define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE
Kojto 119:aae6fcc7d9bb 134 #define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE
Kojto 119:aae6fcc7d9bb 135 #define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1
Kojto 119:aae6fcc7d9bb 136 #define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2
Kojto 119:aae6fcc7d9bb 137 #define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3
Kojto 119:aae6fcc7d9bb 138 #define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4
Kojto 119:aae6fcc7d9bb 139 #define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5
Kojto 119:aae6fcc7d9bb 140 #define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6
Kojto 119:aae6fcc7d9bb 141 #define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7
Kojto 119:aae6fcc7d9bb 142 #define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR
Kojto 119:aae6fcc7d9bb 143 #if defined(STM32F373xC) || defined(STM32F378xx)
Kojto 119:aae6fcc7d9bb 144 #define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1
Kojto 119:aae6fcc7d9bb 145 #define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR
Kojto 119:aae6fcc7d9bb 146 #endif /* STM32F373xC || STM32F378xx */
Kojto 119:aae6fcc7d9bb 147 /**
Kojto 119:aae6fcc7d9bb 148 * @}
Kojto 119:aae6fcc7d9bb 149 */
Kojto 99:dbbf35b96557 150
Kojto 119:aae6fcc7d9bb 151 /** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose
Kojto 119:aae6fcc7d9bb 152 * @{
Kojto 119:aae6fcc7d9bb 153 */
Kojto 119:aae6fcc7d9bb 154 #define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
Kojto 99:dbbf35b96557 155 /**
Kojto 99:dbbf35b96557 156 * @}
Kojto 99:dbbf35b96557 157 */
Kojto 99:dbbf35b96557 158
Kojto 99:dbbf35b96557 159 /** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
Kojto 99:dbbf35b96557 160 * @{
Kojto 99:dbbf35b96557 161 */
Kojto 99:dbbf35b96557 162
Kojto 99:dbbf35b96557 163 #define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE
Kojto 99:dbbf35b96557 164 #define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE
Kojto 99:dbbf35b96557 165
Kojto 99:dbbf35b96557 166 /**
Kojto 99:dbbf35b96557 167 * @}
Kojto 99:dbbf35b96557 168 */
Kojto 99:dbbf35b96557 169
Kojto 99:dbbf35b96557 170 /** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
Kojto 99:dbbf35b96557 171 * @{
Kojto 99:dbbf35b96557 172 */
Kojto 99:dbbf35b96557 173
Kojto 99:dbbf35b96557 174 #define DAC1_CHANNEL_1 DAC_CHANNEL_1
Kojto 99:dbbf35b96557 175 #define DAC1_CHANNEL_2 DAC_CHANNEL_2
Kojto 99:dbbf35b96557 176 #define DAC2_CHANNEL_1 DAC_CHANNEL_1
Kojto 119:aae6fcc7d9bb 177 #define DAC_WAVE_NONE ((uint32_t)0x00000000U)
Kojto 99:dbbf35b96557 178 #define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0)
Kojto 99:dbbf35b96557 179 #define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1)
Kojto 99:dbbf35b96557 180 #define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE
Kojto 99:dbbf35b96557 181 #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
Kojto 99:dbbf35b96557 182 #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
Kojto 99:dbbf35b96557 183
Kojto 99:dbbf35b96557 184 /**
Kojto 99:dbbf35b96557 185 * @}
Kojto 99:dbbf35b96557 186 */
Kojto 99:dbbf35b96557 187
Kojto 119:aae6fcc7d9bb 188 /** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose
Kojto 119:aae6fcc7d9bb 189 * @{
Kojto 119:aae6fcc7d9bb 190 */
Kojto 119:aae6fcc7d9bb 191 #define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2
Kojto 119:aae6fcc7d9bb 192 #define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4
Kojto 119:aae6fcc7d9bb 193 #define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5
Kojto 119:aae6fcc7d9bb 194 #define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4
Kojto 119:aae6fcc7d9bb 195 #define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2
Kojto 119:aae6fcc7d9bb 196 #define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
Kojto 119:aae6fcc7d9bb 197 #define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6
Kojto 119:aae6fcc7d9bb 198 #define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7
Kojto 119:aae6fcc7d9bb 199 #define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67
Kojto 119:aae6fcc7d9bb 200 #define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67
Kojto 119:aae6fcc7d9bb 201 #define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
Kojto 119:aae6fcc7d9bb 202 #define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76
Kojto 119:aae6fcc7d9bb 203 #define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6
Kojto 119:aae6fcc7d9bb 204 #define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7
Kojto 119:aae6fcc7d9bb 205 #define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6
Kojto 119:aae6fcc7d9bb 206
Kojto 119:aae6fcc7d9bb 207 #define IS_HAL_REMAPDMA IS_DMA_REMAP
Kojto 119:aae6fcc7d9bb 208 #define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE
Kojto 119:aae6fcc7d9bb 209 #define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE
Kojto 119:aae6fcc7d9bb 210
Kojto 119:aae6fcc7d9bb 211
Kojto 119:aae6fcc7d9bb 212
Kojto 119:aae6fcc7d9bb 213 /**
Kojto 119:aae6fcc7d9bb 214 * @}
Kojto 119:aae6fcc7d9bb 215 */
Kojto 99:dbbf35b96557 216
Kojto 99:dbbf35b96557 217 /** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
Kojto 99:dbbf35b96557 218 * @{
Kojto 99:dbbf35b96557 219 */
Kojto 99:dbbf35b96557 220
Kojto 99:dbbf35b96557 221 #define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE
Kojto 99:dbbf35b96557 222 #define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD
Kojto 99:dbbf35b96557 223 #define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD
Kojto 99:dbbf35b96557 224 #define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD
Kojto 99:dbbf35b96557 225 #define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS
Kojto 99:dbbf35b96557 226 #define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES
Kojto 99:dbbf35b96557 227 #define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES
Kojto 99:dbbf35b96557 228 #define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE
Kojto 99:dbbf35b96557 229 #define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE
Kojto 99:dbbf35b96557 230 #define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE
Kojto 99:dbbf35b96557 231 #define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE
Kojto 99:dbbf35b96557 232 #define OBEX_PCROP OPTIONBYTE_PCROP
Kojto 99:dbbf35b96557 233 #define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG
Kojto 99:dbbf35b96557 234 #define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE
Kojto 99:dbbf35b96557 235 #define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE
Kojto 99:dbbf35b96557 236 #define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE
Kojto 99:dbbf35b96557 237 #define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD
Kojto 99:dbbf35b96557 238 #define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD
Kojto 99:dbbf35b96557 239 #define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE
Kojto 99:dbbf35b96557 240 #define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD
Kojto 99:dbbf35b96557 241 #define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD
Kojto 99:dbbf35b96557 242 #define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE
Kojto 99:dbbf35b96557 243 #define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD
Kojto 99:dbbf35b96557 244 #define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD
Kojto 99:dbbf35b96557 245 #define PAGESIZE FLASH_PAGE_SIZE
Kojto 99:dbbf35b96557 246 #define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE
Kojto 99:dbbf35b96557 247 #define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD
Kojto 99:dbbf35b96557 248 #define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD
Kojto 99:dbbf35b96557 249 #define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1
Kojto 99:dbbf35b96557 250 #define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2
Kojto 99:dbbf35b96557 251 #define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3
Kojto 99:dbbf35b96557 252 #define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4
Kojto 99:dbbf35b96557 253 #define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST
Kojto 99:dbbf35b96557 254 #define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST
Kojto 99:dbbf35b96557 255 #define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA
Kojto 99:dbbf35b96557 256 #define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB
Kojto 99:dbbf35b96557 257 #define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA
Kojto 99:dbbf35b96557 258 #define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB
Kojto 99:dbbf35b96557 259 #define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE
Kojto 99:dbbf35b96557 260 #define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN
Kojto 99:dbbf35b96557 261 #define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE
Kojto 99:dbbf35b96557 262 #define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN
Kojto 99:dbbf35b96557 263 #define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE
Kojto 99:dbbf35b96557 264 #define FLASH_ERROR_RD HAL_FLASH_ERROR_RD
Kojto 99:dbbf35b96557 265 #define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG
Kojto 99:dbbf35b96557 266 #define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS
Kojto 99:dbbf35b96557 267 #define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP
Kojto 99:dbbf35b96557 268 #define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV
Kojto 99:dbbf35b96557 269 #define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR
Kojto 99:dbbf35b96557 270 #define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG
Kojto 99:dbbf35b96557 271 #define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION
Kojto 99:dbbf35b96557 272 #define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA
Kojto 99:dbbf35b96557 273 #define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE
Kojto 99:dbbf35b96557 274 #define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE
Kojto 99:dbbf35b96557 275 #define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS
Kojto 99:dbbf35b96557 276 #define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS
Kojto 99:dbbf35b96557 277 #define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST
Kojto 99:dbbf35b96557 278 #define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR
Kojto 99:dbbf35b96557 279 #define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO
Kojto 99:dbbf35b96557 280 #define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION
Kojto 99:dbbf35b96557 281 #define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS
Kojto 119:aae6fcc7d9bb 282 #define OB_WDG_SW OB_IWDG_SW
Kojto 119:aae6fcc7d9bb 283 #define OB_WDG_HW OB_IWDG_HW
Kojto 119:aae6fcc7d9bb 284 #define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET
Kojto 119:aae6fcc7d9bb 285 #define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET
Kojto 119:aae6fcc7d9bb 286 #define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET
Kojto 119:aae6fcc7d9bb 287 #define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET
Kojto 119:aae6fcc7d9bb 288 #define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR
Kojto 119:aae6fcc7d9bb 289 #define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
Kojto 119:aae6fcc7d9bb 290 #define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
Kojto 119:aae6fcc7d9bb 291 #define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
Kojto 99:dbbf35b96557 292 /**
Kojto 99:dbbf35b96557 293 * @}
Kojto 99:dbbf35b96557 294 */
Kojto 99:dbbf35b96557 295
Kojto 99:dbbf35b96557 296 /** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
Kojto 99:dbbf35b96557 297 * @{
Kojto 99:dbbf35b96557 298 */
Kojto 99:dbbf35b96557 299
Kojto 119:aae6fcc7d9bb 300 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9
Kojto 119:aae6fcc7d9bb 301 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10
Kojto 119:aae6fcc7d9bb 302 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6
Kojto 119:aae6fcc7d9bb 303 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7
Kojto 119:aae6fcc7d9bb 304 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8
Kojto 119:aae6fcc7d9bb 305 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9
Kojto 119:aae6fcc7d9bb 306 #define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1
Kojto 119:aae6fcc7d9bb 307 #define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2
Kojto 119:aae6fcc7d9bb 308 #define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3
Kojto 99:dbbf35b96557 309 /**
Kojto 99:dbbf35b96557 310 * @}
Kojto 99:dbbf35b96557 311 */
Kojto 99:dbbf35b96557 312
Kojto 99:dbbf35b96557 313
Kojto 119:aae6fcc7d9bb 314 /** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
Kojto 119:aae6fcc7d9bb 315 * @{
Kojto 119:aae6fcc7d9bb 316 */
Kojto 119:aae6fcc7d9bb 317 #if defined(STM32L4) || defined(STM32F7)
Kojto 119:aae6fcc7d9bb 318 #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE
Kojto 119:aae6fcc7d9bb 319 #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
Kojto 119:aae6fcc7d9bb 320 #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
Kojto 119:aae6fcc7d9bb 321 #define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16
Kojto 119:aae6fcc7d9bb 322 #else
Kojto 119:aae6fcc7d9bb 323 #define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE
Kojto 119:aae6fcc7d9bb 324 #define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE
Kojto 119:aae6fcc7d9bb 325 #define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8
Kojto 119:aae6fcc7d9bb 326 #define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16
Kojto 119:aae6fcc7d9bb 327 #endif
Kojto 119:aae6fcc7d9bb 328 /**
Kojto 119:aae6fcc7d9bb 329 * @}
Kojto 119:aae6fcc7d9bb 330 */
Kojto 119:aae6fcc7d9bb 331
Kojto 99:dbbf35b96557 332 /** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
Kojto 99:dbbf35b96557 333 * @{
Kojto 99:dbbf35b96557 334 */
Kojto 99:dbbf35b96557 335
Kojto 99:dbbf35b96557 336 #define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef
Kojto 99:dbbf35b96557 337 #define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef
Kojto 99:dbbf35b96557 338 /**
Kojto 99:dbbf35b96557 339 * @}
Kojto 99:dbbf35b96557 340 */
Kojto 99:dbbf35b96557 341
Kojto 99:dbbf35b96557 342 /** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
Kojto 99:dbbf35b96557 343 * @{
Kojto 99:dbbf35b96557 344 */
Kojto 99:dbbf35b96557 345 #define GET_GPIO_SOURCE GPIO_GET_INDEX
Kojto 99:dbbf35b96557 346 #define GET_GPIO_INDEX GPIO_GET_INDEX
Kojto 119:aae6fcc7d9bb 347
Kojto 119:aae6fcc7d9bb 348 #if defined(STM32F4)
Kojto 119:aae6fcc7d9bb 349 #define GPIO_AF12_SDMMC GPIO_AF12_SDIO
Kojto 119:aae6fcc7d9bb 350 #define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO
Kojto 119:aae6fcc7d9bb 351 #endif
Kojto 119:aae6fcc7d9bb 352
Kojto 119:aae6fcc7d9bb 353 #if defined(STM32F7)
Kojto 119:aae6fcc7d9bb 354 #define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
Kojto 119:aae6fcc7d9bb 355 #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
Kojto 119:aae6fcc7d9bb 356 #endif
Kojto 119:aae6fcc7d9bb 357
Kojto 119:aae6fcc7d9bb 358 #if defined(STM32L4)
Kojto 119:aae6fcc7d9bb 359 #define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
Kojto 119:aae6fcc7d9bb 360 #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
Kojto 119:aae6fcc7d9bb 361 #endif
Kojto 119:aae6fcc7d9bb 362
Kojto 119:aae6fcc7d9bb 363 #define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
Kojto 119:aae6fcc7d9bb 364 #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
Kojto 119:aae6fcc7d9bb 365 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
Kojto 119:aae6fcc7d9bb 366
Kojto 119:aae6fcc7d9bb 367 #if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7)
Kojto 119:aae6fcc7d9bb 368 #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
Kojto 119:aae6fcc7d9bb 369 #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
Kojto 119:aae6fcc7d9bb 370 #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
Kojto 119:aae6fcc7d9bb 371 #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
Kojto 119:aae6fcc7d9bb 372 #endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 */
Kojto 119:aae6fcc7d9bb 373
Kojto 119:aae6fcc7d9bb 374 #if defined(STM32L1)
Kojto 119:aae6fcc7d9bb 375 #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
Kojto 119:aae6fcc7d9bb 376 #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM
Kojto 119:aae6fcc7d9bb 377 #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH
Kojto 119:aae6fcc7d9bb 378 #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
Kojto 119:aae6fcc7d9bb 379 #endif /* STM32L1 */
Kojto 119:aae6fcc7d9bb 380
Kojto 119:aae6fcc7d9bb 381 #if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)
Kojto 119:aae6fcc7d9bb 382 #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
Kojto 119:aae6fcc7d9bb 383 #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
Kojto 119:aae6fcc7d9bb 384 #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH
Kojto 119:aae6fcc7d9bb 385 #endif /* STM32F0 || STM32F3 || STM32F1 */
Kojto 119:aae6fcc7d9bb 386
Kojto 99:dbbf35b96557 387 /**
Kojto 99:dbbf35b96557 388 * @}
Kojto 99:dbbf35b96557 389 */
Kojto 99:dbbf35b96557 390
Kojto 119:aae6fcc7d9bb 391 /** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
Kojto 119:aae6fcc7d9bb 392 * @{
Kojto 119:aae6fcc7d9bb 393 */
Kojto 119:aae6fcc7d9bb 394 #define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED
Kojto 119:aae6fcc7d9bb 395 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6
Kojto 119:aae6fcc7d9bb 396 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6
Kojto 119:aae6fcc7d9bb 397 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6
Kojto 119:aae6fcc7d9bb 398 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6
Kojto 119:aae6fcc7d9bb 399 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7
Kojto 119:aae6fcc7d9bb 400 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
Kojto 119:aae6fcc7d9bb 401 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
Kojto 119:aae6fcc7d9bb 402 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
Kojto 119:aae6fcc7d9bb 403
Kojto 119:aae6fcc7d9bb 404 #define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER
Kojto 119:aae6fcc7d9bb 405 #define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER
Kojto 119:aae6fcc7d9bb 406 #define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD
Kojto 119:aae6fcc7d9bb 407 #define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD
Kojto 119:aae6fcc7d9bb 408 #define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER
Kojto 119:aae6fcc7d9bb 409 #define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
Kojto 119:aae6fcc7d9bb 410 #define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE
Kojto 119:aae6fcc7d9bb 411 #define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE
Kojto 119:aae6fcc7d9bb 412 /**
Kojto 119:aae6fcc7d9bb 413 * @}
Kojto 119:aae6fcc7d9bb 414 */
Kojto 99:dbbf35b96557 415
Kojto 99:dbbf35b96557 416 /** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
Kojto 99:dbbf35b96557 417 * @{
Kojto 99:dbbf35b96557 418 */
Kojto 99:dbbf35b96557 419 #define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE
Kojto 99:dbbf35b96557 420 #define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE
Kojto 99:dbbf35b96557 421 #define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE
Kojto 99:dbbf35b96557 422 #define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE
Kojto 99:dbbf35b96557 423 #define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE
Kojto 99:dbbf35b96557 424 #define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
Kojto 99:dbbf35b96557 425 #define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
Kojto 99:dbbf35b96557 426 #define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
Kojto 119:aae6fcc7d9bb 427 #if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0)
Kojto 119:aae6fcc7d9bb 428 #define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX
Kojto 119:aae6fcc7d9bb 429 #define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX
Kojto 119:aae6fcc7d9bb 430 #define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX
Kojto 119:aae6fcc7d9bb 431 #define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX
Kojto 119:aae6fcc7d9bb 432 #define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX
Kojto 119:aae6fcc7d9bb 433 #define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX
Kojto 119:aae6fcc7d9bb 434 #endif
Kojto 99:dbbf35b96557 435 /**
Kojto 99:dbbf35b96557 436 * @}
Kojto 99:dbbf35b96557 437 */
Kojto 99:dbbf35b96557 438
Kojto 99:dbbf35b96557 439 /** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
Kojto 99:dbbf35b96557 440 * @{
Kojto 99:dbbf35b96557 441 */
Kojto 99:dbbf35b96557 442 #define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE
Kojto 99:dbbf35b96557 443 #define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE
Kojto 99:dbbf35b96557 444
Kojto 99:dbbf35b96557 445 /**
Kojto 99:dbbf35b96557 446 * @}
Kojto 99:dbbf35b96557 447 */
Kojto 99:dbbf35b96557 448
Kojto 99:dbbf35b96557 449 /** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
Kojto 99:dbbf35b96557 450 * @{
Kojto 99:dbbf35b96557 451 */
Kojto 99:dbbf35b96557 452 #define KR_KEY_RELOAD IWDG_KEY_RELOAD
Kojto 99:dbbf35b96557 453 #define KR_KEY_ENABLE IWDG_KEY_ENABLE
Kojto 99:dbbf35b96557 454 #define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE
Kojto 99:dbbf35b96557 455 #define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE
Kojto 99:dbbf35b96557 456 /**
Kojto 99:dbbf35b96557 457 * @}
Kojto 99:dbbf35b96557 458 */
Kojto 99:dbbf35b96557 459
Kojto 99:dbbf35b96557 460 /** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
Kojto 99:dbbf35b96557 461 * @{
Kojto 99:dbbf35b96557 462 */
Kojto 99:dbbf35b96557 463
Kojto 99:dbbf35b96557 464 #define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
Kojto 99:dbbf35b96557 465 #define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
Kojto 99:dbbf35b96557 466 #define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
Kojto 99:dbbf35b96557 467 #define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
Kojto 99:dbbf35b96557 468
Kojto 99:dbbf35b96557 469 #define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING
Kojto 99:dbbf35b96557 470 #define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING
Kojto 99:dbbf35b96557 471 #define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING
Kojto 119:aae6fcc7d9bb 472
Kojto 119:aae6fcc7d9bb 473 #define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
Kojto 119:aae6fcc7d9bb 474 #define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS
Kojto 119:aae6fcc7d9bb 475 #define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS
Kojto 119:aae6fcc7d9bb 476 #define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS
Kojto 119:aae6fcc7d9bb 477
Kojto 119:aae6fcc7d9bb 478 /* The following 3 definition have also been present in a temporary version of lptim.h */
Kojto 119:aae6fcc7d9bb 479 /* They need to be renamed also to the right name, just in case */
Kojto 119:aae6fcc7d9bb 480 #define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS
Kojto 119:aae6fcc7d9bb 481 #define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS
Kojto 119:aae6fcc7d9bb 482 #define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS
Kojto 119:aae6fcc7d9bb 483
Kojto 99:dbbf35b96557 484 /**
Kojto 99:dbbf35b96557 485 * @}
Kojto 99:dbbf35b96557 486 */
Kojto 99:dbbf35b96557 487
Kojto 99:dbbf35b96557 488 /** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
Kojto 99:dbbf35b96557 489 * @{
Kojto 99:dbbf35b96557 490 */
Kojto 99:dbbf35b96557 491 #define NAND_AddressTypedef NAND_AddressTypeDef
Kojto 99:dbbf35b96557 492
Kojto 119:aae6fcc7d9bb 493 #define __ARRAY_ADDRESS ARRAY_ADDRESS
Kojto 119:aae6fcc7d9bb 494 #define __ADDR_1st_CYCLE ADDR_1ST_CYCLE
Kojto 119:aae6fcc7d9bb 495 #define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE
Kojto 119:aae6fcc7d9bb 496 #define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE
Kojto 119:aae6fcc7d9bb 497 #define __ADDR_4th_CYCLE ADDR_4TH_CYCLE
Kojto 99:dbbf35b96557 498 /**
Kojto 99:dbbf35b96557 499 * @}
Kojto 99:dbbf35b96557 500 */
Kojto 99:dbbf35b96557 501
Kojto 99:dbbf35b96557 502 /** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
Kojto 99:dbbf35b96557 503 * @{
Kojto 99:dbbf35b96557 504 */
Kojto 99:dbbf35b96557 505 #define NOR_StatusTypedef HAL_NOR_StatusTypeDef
Kojto 99:dbbf35b96557 506 #define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS
Kojto 99:dbbf35b96557 507 #define NOR_ONGOING HAL_NOR_STATUS_ONGOING
Kojto 99:dbbf35b96557 508 #define NOR_ERROR HAL_NOR_STATUS_ERROR
Kojto 99:dbbf35b96557 509 #define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT
Kojto 99:dbbf35b96557 510
Kojto 119:aae6fcc7d9bb 511 #define __NOR_WRITE NOR_WRITE
Kojto 119:aae6fcc7d9bb 512 #define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT
Kojto 99:dbbf35b96557 513 /**
Kojto 99:dbbf35b96557 514 * @}
Kojto 99:dbbf35b96557 515 */
Kojto 99:dbbf35b96557 516
Kojto 99:dbbf35b96557 517 /** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
Kojto 99:dbbf35b96557 518 * @{
Kojto 99:dbbf35b96557 519 */
Kojto 99:dbbf35b96557 520
Kojto 99:dbbf35b96557 521 #define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0
Kojto 99:dbbf35b96557 522 #define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1
Kojto 99:dbbf35b96557 523 #define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2
Kojto 99:dbbf35b96557 524 #define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3
Kojto 99:dbbf35b96557 525
Kojto 99:dbbf35b96557 526 #define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0
Kojto 99:dbbf35b96557 527 #define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1
Kojto 99:dbbf35b96557 528 #define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2
Kojto 99:dbbf35b96557 529 #define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3
Kojto 99:dbbf35b96557 530
Kojto 99:dbbf35b96557 531 #define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
Kojto 99:dbbf35b96557 532 #define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
Kojto 99:dbbf35b96557 533
Kojto 99:dbbf35b96557 534 #define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
Kojto 99:dbbf35b96557 535 #define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
Kojto 99:dbbf35b96557 536
Kojto 99:dbbf35b96557 537 #define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0
Kojto 99:dbbf35b96557 538 #define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1
Kojto 99:dbbf35b96557 539
Kojto 99:dbbf35b96557 540 #define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1
Kojto 99:dbbf35b96557 541
Kojto 99:dbbf35b96557 542 #define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
Kojto 99:dbbf35b96557 543 #define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
Kojto 99:dbbf35b96557 544 #define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
Kojto 99:dbbf35b96557 545
Kojto 99:dbbf35b96557 546 /**
Kojto 99:dbbf35b96557 547 * @}
Kojto 99:dbbf35b96557 548 */
Kojto 99:dbbf35b96557 549
Kojto 99:dbbf35b96557 550 /** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
Kojto 99:dbbf35b96557 551 * @{
Kojto 99:dbbf35b96557 552 */
Kojto 99:dbbf35b96557 553 #define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
Kojto 99:dbbf35b96557 554 /**
Kojto 99:dbbf35b96557 555 * @}
Kojto 99:dbbf35b96557 556 */
Kojto 99:dbbf35b96557 557
Kojto 99:dbbf35b96557 558 /** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
Kojto 99:dbbf35b96557 559 * @{
Kojto 99:dbbf35b96557 560 */
Kojto 99:dbbf35b96557 561
Kojto 99:dbbf35b96557 562 /* Compact Flash-ATA registers description */
Kojto 99:dbbf35b96557 563 #define CF_DATA ATA_DATA
Kojto 99:dbbf35b96557 564 #define CF_SECTOR_COUNT ATA_SECTOR_COUNT
Kojto 99:dbbf35b96557 565 #define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER
Kojto 99:dbbf35b96557 566 #define CF_CYLINDER_LOW ATA_CYLINDER_LOW
Kojto 99:dbbf35b96557 567 #define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH
Kojto 99:dbbf35b96557 568 #define CF_CARD_HEAD ATA_CARD_HEAD
Kojto 99:dbbf35b96557 569 #define CF_STATUS_CMD ATA_STATUS_CMD
Kojto 99:dbbf35b96557 570 #define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE
Kojto 99:dbbf35b96557 571 #define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA
Kojto 99:dbbf35b96557 572
Kojto 99:dbbf35b96557 573 /* Compact Flash-ATA commands */
Kojto 99:dbbf35b96557 574 #define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD
Kojto 99:dbbf35b96557 575 #define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD
Kojto 99:dbbf35b96557 576 #define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD
Kojto 99:dbbf35b96557 577 #define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD
Kojto 99:dbbf35b96557 578
Kojto 99:dbbf35b96557 579 #define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef
Kojto 99:dbbf35b96557 580 #define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS
Kojto 99:dbbf35b96557 581 #define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING
Kojto 99:dbbf35b96557 582 #define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR
Kojto 99:dbbf35b96557 583 #define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT
Kojto 99:dbbf35b96557 584 /**
Kojto 99:dbbf35b96557 585 * @}
Kojto 99:dbbf35b96557 586 */
Kojto 99:dbbf35b96557 587
Kojto 99:dbbf35b96557 588 /** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
Kojto 99:dbbf35b96557 589 * @{
Kojto 99:dbbf35b96557 590 */
Kojto 99:dbbf35b96557 591
Kojto 99:dbbf35b96557 592 #define FORMAT_BIN RTC_FORMAT_BIN
Kojto 99:dbbf35b96557 593 #define FORMAT_BCD RTC_FORMAT_BCD
Kojto 99:dbbf35b96557 594
Kojto 99:dbbf35b96557 595 #define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE
Kojto 99:dbbf35b96557 596 #define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
Kojto 99:dbbf35b96557 597 #define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
Kojto 99:dbbf35b96557 598 #define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
Kojto 99:dbbf35b96557 599 #define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
Kojto 99:dbbf35b96557 600
Kojto 119:aae6fcc7d9bb 601 #define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
Kojto 99:dbbf35b96557 602 #define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
Kojto 119:aae6fcc7d9bb 603 #define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
Kojto 119:aae6fcc7d9bb 604 #define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
Kojto 119:aae6fcc7d9bb 605 #define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
Kojto 99:dbbf35b96557 606 #define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
Kojto 119:aae6fcc7d9bb 607 #define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
Kojto 119:aae6fcc7d9bb 608 #define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
Kojto 119:aae6fcc7d9bb 609
Kojto 119:aae6fcc7d9bb 610 #define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT
Kojto 119:aae6fcc7d9bb 611 #define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
Kojto 119:aae6fcc7d9bb 612 #define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
Kojto 119:aae6fcc7d9bb 613 #define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2
Kojto 119:aae6fcc7d9bb 614
Kojto 119:aae6fcc7d9bb 615 #define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE
Kojto 119:aae6fcc7d9bb 616 #define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1
Kojto 119:aae6fcc7d9bb 617 #define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1
Kojto 119:aae6fcc7d9bb 618
Kojto 119:aae6fcc7d9bb 619 #define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT
Kojto 119:aae6fcc7d9bb 620 #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
Kojto 119:aae6fcc7d9bb 621 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
Kojto 99:dbbf35b96557 622
Kojto 99:dbbf35b96557 623 /**
Kojto 99:dbbf35b96557 624 * @}
Kojto 99:dbbf35b96557 625 */
Kojto 99:dbbf35b96557 626
Kojto 99:dbbf35b96557 627
Kojto 99:dbbf35b96557 628 /** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
Kojto 99:dbbf35b96557 629 * @{
Kojto 99:dbbf35b96557 630 */
Kojto 99:dbbf35b96557 631 #define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE
Kojto 99:dbbf35b96557 632 #define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE
Kojto 99:dbbf35b96557 633
Kojto 99:dbbf35b96557 634 #define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE
Kojto 99:dbbf35b96557 635 #define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE
Kojto 99:dbbf35b96557 636 #define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE
Kojto 99:dbbf35b96557 637 #define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE
Kojto 99:dbbf35b96557 638
Kojto 99:dbbf35b96557 639 #define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE
Kojto 99:dbbf35b96557 640 #define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE
Kojto 99:dbbf35b96557 641
Kojto 99:dbbf35b96557 642 #define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE
Kojto 99:dbbf35b96557 643 #define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE
Kojto 99:dbbf35b96557 644 /**
Kojto 99:dbbf35b96557 645 * @}
Kojto 99:dbbf35b96557 646 */
Kojto 99:dbbf35b96557 647
Kojto 99:dbbf35b96557 648
Kojto 99:dbbf35b96557 649 /** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
Kojto 99:dbbf35b96557 650 * @{
Kojto 99:dbbf35b96557 651 */
Kojto 99:dbbf35b96557 652 #define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE
Kojto 99:dbbf35b96557 653 #define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE
Kojto 99:dbbf35b96557 654 #define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE
Kojto 99:dbbf35b96557 655 #define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE
Kojto 99:dbbf35b96557 656 #define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE
Kojto 99:dbbf35b96557 657 #define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE
Kojto 99:dbbf35b96557 658 #define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE
Kojto 99:dbbf35b96557 659 #define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE
Kojto 119:aae6fcc7d9bb 660 #define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE
Kojto 119:aae6fcc7d9bb 661 #define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE
Kojto 99:dbbf35b96557 662 #define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN
Kojto 99:dbbf35b96557 663 /**
Kojto 99:dbbf35b96557 664 * @}
Kojto 99:dbbf35b96557 665 */
Kojto 99:dbbf35b96557 666
Kojto 99:dbbf35b96557 667 /** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
Kojto 99:dbbf35b96557 668 * @{
Kojto 99:dbbf35b96557 669 */
Kojto 99:dbbf35b96557 670 #define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE
Kojto 99:dbbf35b96557 671 #define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE
Kojto 99:dbbf35b96557 672
Kojto 99:dbbf35b96557 673 #define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE
Kojto 99:dbbf35b96557 674 #define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE
Kojto 99:dbbf35b96557 675
Kojto 99:dbbf35b96557 676 #define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE
Kojto 99:dbbf35b96557 677 #define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE
Kojto 99:dbbf35b96557 678
Kojto 99:dbbf35b96557 679 /**
Kojto 99:dbbf35b96557 680 * @}
Kojto 99:dbbf35b96557 681 */
Kojto 99:dbbf35b96557 682
Kojto 99:dbbf35b96557 683 /** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
Kojto 99:dbbf35b96557 684 * @{
Kojto 99:dbbf35b96557 685 */
Kojto 99:dbbf35b96557 686 #define CCER_CCxE_MASK TIM_CCER_CCxE_MASK
Kojto 99:dbbf35b96557 687 #define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK
Kojto 99:dbbf35b96557 688
Kojto 99:dbbf35b96557 689 #define TIM_DMABase_CR1 TIM_DMABASE_CR1
Kojto 99:dbbf35b96557 690 #define TIM_DMABase_CR2 TIM_DMABASE_CR2
Kojto 99:dbbf35b96557 691 #define TIM_DMABase_SMCR TIM_DMABASE_SMCR
Kojto 99:dbbf35b96557 692 #define TIM_DMABase_DIER TIM_DMABASE_DIER
Kojto 99:dbbf35b96557 693 #define TIM_DMABase_SR TIM_DMABASE_SR
Kojto 99:dbbf35b96557 694 #define TIM_DMABase_EGR TIM_DMABASE_EGR
Kojto 99:dbbf35b96557 695 #define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1
Kojto 99:dbbf35b96557 696 #define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2
Kojto 99:dbbf35b96557 697 #define TIM_DMABase_CCER TIM_DMABASE_CCER
Kojto 99:dbbf35b96557 698 #define TIM_DMABase_CNT TIM_DMABASE_CNT
Kojto 99:dbbf35b96557 699 #define TIM_DMABase_PSC TIM_DMABASE_PSC
Kojto 99:dbbf35b96557 700 #define TIM_DMABase_ARR TIM_DMABASE_ARR
Kojto 99:dbbf35b96557 701 #define TIM_DMABase_RCR TIM_DMABASE_RCR
Kojto 99:dbbf35b96557 702 #define TIM_DMABase_CCR1 TIM_DMABASE_CCR1
Kojto 99:dbbf35b96557 703 #define TIM_DMABase_CCR2 TIM_DMABASE_CCR2
Kojto 99:dbbf35b96557 704 #define TIM_DMABase_CCR3 TIM_DMABASE_CCR3
Kojto 99:dbbf35b96557 705 #define TIM_DMABase_CCR4 TIM_DMABASE_CCR4
Kojto 99:dbbf35b96557 706 #define TIM_DMABase_BDTR TIM_DMABASE_BDTR
Kojto 99:dbbf35b96557 707 #define TIM_DMABase_DCR TIM_DMABASE_DCR
Kojto 99:dbbf35b96557 708 #define TIM_DMABase_DMAR TIM_DMABASE_DMAR
Kojto 99:dbbf35b96557 709 #define TIM_DMABase_OR1 TIM_DMABASE_OR1
Kojto 99:dbbf35b96557 710 #define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3
Kojto 99:dbbf35b96557 711 #define TIM_DMABase_CCR5 TIM_DMABASE_CCR5
Kojto 99:dbbf35b96557 712 #define TIM_DMABase_CCR6 TIM_DMABASE_CCR6
Kojto 99:dbbf35b96557 713 #define TIM_DMABase_OR2 TIM_DMABASE_OR2
Kojto 99:dbbf35b96557 714 #define TIM_DMABase_OR3 TIM_DMABASE_OR3
Kojto 119:aae6fcc7d9bb 715 #define TIM_DMABase_OR TIM_DMABASE_OR
Kojto 99:dbbf35b96557 716
Kojto 99:dbbf35b96557 717 #define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE
Kojto 99:dbbf35b96557 718 #define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1
Kojto 99:dbbf35b96557 719 #define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2
Kojto 99:dbbf35b96557 720 #define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3
Kojto 99:dbbf35b96557 721 #define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4
Kojto 99:dbbf35b96557 722 #define TIM_EventSource_COM TIM_EVENTSOURCE_COM
Kojto 99:dbbf35b96557 723 #define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER
Kojto 99:dbbf35b96557 724 #define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK
Kojto 99:dbbf35b96557 725 #define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2
Kojto 99:dbbf35b96557 726
Kojto 99:dbbf35b96557 727 #define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER
Kojto 99:dbbf35b96557 728 #define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS
Kojto 99:dbbf35b96557 729 #define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS
Kojto 99:dbbf35b96557 730 #define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS
Kojto 99:dbbf35b96557 731 #define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS
Kojto 99:dbbf35b96557 732 #define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS
Kojto 99:dbbf35b96557 733 #define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS
Kojto 99:dbbf35b96557 734 #define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS
Kojto 99:dbbf35b96557 735 #define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS
Kojto 99:dbbf35b96557 736 #define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS
Kojto 99:dbbf35b96557 737 #define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS
Kojto 99:dbbf35b96557 738 #define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS
Kojto 99:dbbf35b96557 739 #define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS
Kojto 99:dbbf35b96557 740 #define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS
Kojto 99:dbbf35b96557 741 #define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS
Kojto 99:dbbf35b96557 742 #define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS
Kojto 99:dbbf35b96557 743 #define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS
Kojto 99:dbbf35b96557 744 #define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS
Kojto 99:dbbf35b96557 745
Kojto 99:dbbf35b96557 746 /**
Kojto 99:dbbf35b96557 747 * @}
Kojto 99:dbbf35b96557 748 */
Kojto 99:dbbf35b96557 749
Kojto 119:aae6fcc7d9bb 750 /** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose
Kojto 119:aae6fcc7d9bb 751 * @{
Kojto 119:aae6fcc7d9bb 752 */
Kojto 119:aae6fcc7d9bb 753 #define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING
Kojto 119:aae6fcc7d9bb 754 #define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING
Kojto 119:aae6fcc7d9bb 755 /**
Kojto 119:aae6fcc7d9bb 756 * @}
Kojto 119:aae6fcc7d9bb 757 */
Kojto 119:aae6fcc7d9bb 758
Kojto 99:dbbf35b96557 759 /** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
Kojto 99:dbbf35b96557 760 * @{
Kojto 99:dbbf35b96557 761 */
Kojto 99:dbbf35b96557 762 #define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
Kojto 99:dbbf35b96557 763 #define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
Kojto 99:dbbf35b96557 764 #define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
Kojto 99:dbbf35b96557 765 #define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
Kojto 99:dbbf35b96557 766
Kojto 99:dbbf35b96557 767 #define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE
Kojto 99:dbbf35b96557 768 #define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE
Kojto 99:dbbf35b96557 769
Kojto 99:dbbf35b96557 770 #define __DIV_SAMPLING16 UART_DIV_SAMPLING16
Kojto 99:dbbf35b96557 771 #define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16
Kojto 99:dbbf35b96557 772 #define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16
Kojto 99:dbbf35b96557 773 #define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16
Kojto 99:dbbf35b96557 774
Kojto 99:dbbf35b96557 775 #define __DIV_SAMPLING8 UART_DIV_SAMPLING8
Kojto 99:dbbf35b96557 776 #define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8
Kojto 99:dbbf35b96557 777 #define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8
Kojto 99:dbbf35b96557 778 #define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8
Kojto 99:dbbf35b96557 779
Kojto 99:dbbf35b96557 780 #define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE
Kojto 99:dbbf35b96557 781 #define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK
Kojto 99:dbbf35b96557 782
Kojto 99:dbbf35b96557 783 /**
Kojto 99:dbbf35b96557 784 * @}
Kojto 99:dbbf35b96557 785 */
Kojto 99:dbbf35b96557 786
Kojto 99:dbbf35b96557 787
Kojto 99:dbbf35b96557 788 /** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
Kojto 99:dbbf35b96557 789 * @{
Kojto 99:dbbf35b96557 790 */
Kojto 99:dbbf35b96557 791
Kojto 99:dbbf35b96557 792 #define USART_CLOCK_DISABLED USART_CLOCK_DISABLE
Kojto 99:dbbf35b96557 793 #define USART_CLOCK_ENABLED USART_CLOCK_ENABLE
Kojto 99:dbbf35b96557 794
Kojto 99:dbbf35b96557 795 #define USARTNACK_ENABLED USART_NACK_ENABLE
Kojto 99:dbbf35b96557 796 #define USARTNACK_DISABLED USART_NACK_DISABLE
Kojto 99:dbbf35b96557 797 /**
Kojto 99:dbbf35b96557 798 * @}
Kojto 99:dbbf35b96557 799 */
Kojto 99:dbbf35b96557 800
Kojto 99:dbbf35b96557 801 /** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
Kojto 99:dbbf35b96557 802 * @{
Kojto 99:dbbf35b96557 803 */
Kojto 99:dbbf35b96557 804 #define CFR_BASE WWDG_CFR_BASE
Kojto 99:dbbf35b96557 805
Kojto 99:dbbf35b96557 806 /**
Kojto 99:dbbf35b96557 807 * @}
Kojto 99:dbbf35b96557 808 */
Kojto 99:dbbf35b96557 809
Kojto 99:dbbf35b96557 810 /** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
Kojto 99:dbbf35b96557 811 * @{
Kojto 99:dbbf35b96557 812 */
Kojto 99:dbbf35b96557 813 #define CAN_FilterFIFO0 CAN_FILTER_FIFO0
Kojto 99:dbbf35b96557 814 #define CAN_FilterFIFO1 CAN_FILTER_FIFO1
Kojto 99:dbbf35b96557 815 #define CAN_IT_RQCP0 CAN_IT_TME
Kojto 99:dbbf35b96557 816 #define CAN_IT_RQCP1 CAN_IT_TME
Kojto 99:dbbf35b96557 817 #define CAN_IT_RQCP2 CAN_IT_TME
Kojto 99:dbbf35b96557 818 #define INAK_TIMEOUT CAN_TIMEOUT_VALUE
Kojto 99:dbbf35b96557 819 #define SLAK_TIMEOUT CAN_TIMEOUT_VALUE
Kojto 119:aae6fcc7d9bb 820 #define CAN_TXSTATUS_FAILED ((uint8_t)0x00U)
Kojto 119:aae6fcc7d9bb 821 #define CAN_TXSTATUS_OK ((uint8_t)0x01U)
Kojto 119:aae6fcc7d9bb 822 #define CAN_TXSTATUS_PENDING ((uint8_t)0x02U)
Kojto 99:dbbf35b96557 823
Kojto 99:dbbf35b96557 824 /**
Kojto 99:dbbf35b96557 825 * @}
Kojto 99:dbbf35b96557 826 */
Kojto 99:dbbf35b96557 827
Kojto 99:dbbf35b96557 828 /** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
Kojto 99:dbbf35b96557 829 * @{
Kojto 99:dbbf35b96557 830 */
Kojto 99:dbbf35b96557 831
Kojto 99:dbbf35b96557 832 #define VLAN_TAG ETH_VLAN_TAG
Kojto 99:dbbf35b96557 833 #define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD
Kojto 99:dbbf35b96557 834 #define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD
Kojto 99:dbbf35b96557 835 #define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD
Kojto 99:dbbf35b96557 836 #define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK
Kojto 99:dbbf35b96557 837 #define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK
Kojto 99:dbbf35b96557 838 #define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK
Kojto 99:dbbf35b96557 839 #define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK
Kojto 99:dbbf35b96557 840
Kojto 119:aae6fcc7d9bb 841 #define ETH_MMCCR ((uint32_t)0x00000100U)
Kojto 119:aae6fcc7d9bb 842 #define ETH_MMCRIR ((uint32_t)0x00000104U)
Kojto 119:aae6fcc7d9bb 843 #define ETH_MMCTIR ((uint32_t)0x00000108U)
Kojto 119:aae6fcc7d9bb 844 #define ETH_MMCRIMR ((uint32_t)0x0000010CU)
Kojto 119:aae6fcc7d9bb 845 #define ETH_MMCTIMR ((uint32_t)0x00000110U)
Kojto 119:aae6fcc7d9bb 846 #define ETH_MMCTGFSCCR ((uint32_t)0x0000014CU)
Kojto 119:aae6fcc7d9bb 847 #define ETH_MMCTGFMSCCR ((uint32_t)0x00000150U)
Kojto 119:aae6fcc7d9bb 848 #define ETH_MMCTGFCR ((uint32_t)0x00000168U)
Kojto 119:aae6fcc7d9bb 849 #define ETH_MMCRFCECR ((uint32_t)0x00000194U)
Kojto 119:aae6fcc7d9bb 850 #define ETH_MMCRFAECR ((uint32_t)0x00000198U)
Kojto 119:aae6fcc7d9bb 851 #define ETH_MMCRGUFCR ((uint32_t)0x000001C4U)
Kojto 99:dbbf35b96557 852
Kojto 99:dbbf35b96557 853 /**
Kojto 99:dbbf35b96557 854 * @}
Kojto 99:dbbf35b96557 855 */
Kojto 99:dbbf35b96557 856
Kojto 99:dbbf35b96557 857 /** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
Kojto 99:dbbf35b96557 858 * @{
Kojto 99:dbbf35b96557 859 */
Kojto 99:dbbf35b96557 860
Kojto 99:dbbf35b96557 861 /**
Kojto 99:dbbf35b96557 862 * @}
Kojto 99:dbbf35b96557 863 */
Kojto 99:dbbf35b96557 864
Kojto 99:dbbf35b96557 865 /* Exported functions --------------------------------------------------------*/
Kojto 99:dbbf35b96557 866
Kojto 99:dbbf35b96557 867 /** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
Kojto 99:dbbf35b96557 868 * @{
Kojto 99:dbbf35b96557 869 */
Kojto 99:dbbf35b96557 870 #define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback
Kojto 99:dbbf35b96557 871 /**
Kojto 99:dbbf35b96557 872 * @}
Kojto 99:dbbf35b96557 873 */
Kojto 99:dbbf35b96557 874
Kojto 99:dbbf35b96557 875 /** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
Kojto 99:dbbf35b96557 876 * @{
Kojto 99:dbbf35b96557 877 */
Kojto 119:aae6fcc7d9bb 878 #define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef
Kojto 119:aae6fcc7d9bb 879 #define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef
Kojto 99:dbbf35b96557 880 #define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish
Kojto 99:dbbf35b96557 881 #define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish
Kojto 99:dbbf35b96557 882 #define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish
Kojto 99:dbbf35b96557 883 #define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish
Kojto 99:dbbf35b96557 884
Kojto 99:dbbf35b96557 885 /*HASH Algorithm Selection*/
Kojto 99:dbbf35b96557 886
Kojto 99:dbbf35b96557 887 #define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1
Kojto 99:dbbf35b96557 888 #define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224
Kojto 99:dbbf35b96557 889 #define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256
Kojto 99:dbbf35b96557 890 #define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5
Kojto 99:dbbf35b96557 891
Kojto 99:dbbf35b96557 892 #define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH
Kojto 99:dbbf35b96557 893 #define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC
Kojto 99:dbbf35b96557 894
Kojto 99:dbbf35b96557 895 #define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
Kojto 99:dbbf35b96557 896 #define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
Kojto 99:dbbf35b96557 897 /**
Kojto 99:dbbf35b96557 898 * @}
Kojto 99:dbbf35b96557 899 */
Kojto 99:dbbf35b96557 900
Kojto 99:dbbf35b96557 901 /** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
Kojto 99:dbbf35b96557 902 * @{
Kojto 99:dbbf35b96557 903 */
Kojto 99:dbbf35b96557 904 #define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
Kojto 99:dbbf35b96557 905 #define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
Kojto 99:dbbf35b96557 906 #define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
Kojto 99:dbbf35b96557 907 #define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
Kojto 99:dbbf35b96557 908 #define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
Kojto 99:dbbf35b96557 909 #define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
Kojto 99:dbbf35b96557 910 #define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
Kojto 99:dbbf35b96557 911 #define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
Kojto 99:dbbf35b96557 912 #define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
Kojto 99:dbbf35b96557 913 #define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
Kojto 99:dbbf35b96557 914 #define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
Kojto 99:dbbf35b96557 915 #define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
Kojto 99:dbbf35b96557 916 /**
Kojto 99:dbbf35b96557 917 * @}
Kojto 99:dbbf35b96557 918 */
Kojto 99:dbbf35b96557 919
Kojto 99:dbbf35b96557 920 /** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
Kojto 99:dbbf35b96557 921 * @{
Kojto 99:dbbf35b96557 922 */
Kojto 99:dbbf35b96557 923 #define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram
Kojto 99:dbbf35b96557 924 #define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown
Kojto 99:dbbf35b96557 925 #define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown
Kojto 99:dbbf35b96557 926 #define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock
Kojto 99:dbbf35b96557 927 #define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock
Kojto 99:dbbf35b96557 928 #define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase
Kojto 99:dbbf35b96557 929 #define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program
Kojto 99:dbbf35b96557 930
Kojto 99:dbbf35b96557 931 /**
Kojto 99:dbbf35b96557 932 * @}
Kojto 99:dbbf35b96557 933 */
Kojto 99:dbbf35b96557 934
Kojto 99:dbbf35b96557 935 /** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
Kojto 99:dbbf35b96557 936 * @{
Kojto 99:dbbf35b96557 937 */
Kojto 99:dbbf35b96557 938 #define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter
Kojto 99:dbbf35b96557 939 #define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter
Kojto 99:dbbf35b96557 940
Kojto 99:dbbf35b96557 941 #define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
Kojto 99:dbbf35b96557 942 /**
Kojto 99:dbbf35b96557 943 * @}
Kojto 99:dbbf35b96557 944 */
Kojto 99:dbbf35b96557 945
Kojto 99:dbbf35b96557 946 /** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
Kojto 99:dbbf35b96557 947 * @{
Kojto 99:dbbf35b96557 948 */
Kojto 99:dbbf35b96557 949 #define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
Kojto 99:dbbf35b96557 950 #define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
Kojto 99:dbbf35b96557 951 #define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
Kojto 99:dbbf35b96557 952 #define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor
Kojto 99:dbbf35b96557 953 #define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg
Kojto 99:dbbf35b96557 954 #define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown
Kojto 99:dbbf35b96557 955 #define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor
Kojto 99:dbbf35b96557 956 #define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler
Kojto 99:dbbf35b96557 957 #define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD
Kojto 99:dbbf35b96557 958 #define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler
Kojto 99:dbbf35b96557 959 #define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback
Kojto 99:dbbf35b96557 960 #define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive
Kojto 99:dbbf35b96557 961 #define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive
Kojto 99:dbbf35b96557 962 #define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC
Kojto 99:dbbf35b96557 963 #define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC
Kojto 99:dbbf35b96557 964 #define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM
Kojto 99:dbbf35b96557 965
Kojto 99:dbbf35b96557 966 #define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL
Kojto 99:dbbf35b96557 967 #define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING
Kojto 99:dbbf35b96557 968 #define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING
Kojto 99:dbbf35b96557 969 #define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING
Kojto 99:dbbf35b96557 970 #define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING
Kojto 99:dbbf35b96557 971 #define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING
Kojto 99:dbbf35b96557 972 #define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING
Kojto 99:dbbf35b96557 973
Kojto 99:dbbf35b96557 974 #define CR_OFFSET_BB PWR_CR_OFFSET_BB
Kojto 99:dbbf35b96557 975 #define CSR_OFFSET_BB PWR_CSR_OFFSET_BB
Kojto 99:dbbf35b96557 976
Kojto 99:dbbf35b96557 977 #define DBP_BitNumber DBP_BIT_NUMBER
Kojto 99:dbbf35b96557 978 #define PVDE_BitNumber PVDE_BIT_NUMBER
Kojto 99:dbbf35b96557 979 #define PMODE_BitNumber PMODE_BIT_NUMBER
Kojto 99:dbbf35b96557 980 #define EWUP_BitNumber EWUP_BIT_NUMBER
Kojto 99:dbbf35b96557 981 #define FPDS_BitNumber FPDS_BIT_NUMBER
Kojto 99:dbbf35b96557 982 #define ODEN_BitNumber ODEN_BIT_NUMBER
Kojto 99:dbbf35b96557 983 #define ODSWEN_BitNumber ODSWEN_BIT_NUMBER
Kojto 99:dbbf35b96557 984 #define MRLVDS_BitNumber MRLVDS_BIT_NUMBER
Kojto 99:dbbf35b96557 985 #define LPLVDS_BitNumber LPLVDS_BIT_NUMBER
Kojto 99:dbbf35b96557 986 #define BRE_BitNumber BRE_BIT_NUMBER
Kojto 99:dbbf35b96557 987
Kojto 99:dbbf35b96557 988 #define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
Kojto 99:dbbf35b96557 989
Kojto 99:dbbf35b96557 990 /**
Kojto 99:dbbf35b96557 991 * @}
Kojto 99:dbbf35b96557 992 */
Kojto 99:dbbf35b96557 993
Kojto 99:dbbf35b96557 994 /** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
Kojto 99:dbbf35b96557 995 * @{
Kojto 99:dbbf35b96557 996 */
Kojto 99:dbbf35b96557 997 #define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT
Kojto 99:dbbf35b96557 998 #define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback
Kojto 99:dbbf35b96557 999 #define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback
Kojto 99:dbbf35b96557 1000 /**
Kojto 99:dbbf35b96557 1001 * @}
Kojto 99:dbbf35b96557 1002 */
Kojto 99:dbbf35b96557 1003
Kojto 99:dbbf35b96557 1004 /** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
Kojto 99:dbbf35b96557 1005 * @{
Kojto 99:dbbf35b96557 1006 */
Kojto 99:dbbf35b96557 1007 #define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo
Kojto 99:dbbf35b96557 1008 /**
Kojto 99:dbbf35b96557 1009 * @}
Kojto 99:dbbf35b96557 1010 */
Kojto 99:dbbf35b96557 1011
Kojto 99:dbbf35b96557 1012 /** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
Kojto 99:dbbf35b96557 1013 * @{
Kojto 99:dbbf35b96557 1014 */
Kojto 99:dbbf35b96557 1015 #define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt
Kojto 99:dbbf35b96557 1016 #define HAL_TIM_DMAError TIM_DMAError
Kojto 99:dbbf35b96557 1017 #define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
Kojto 99:dbbf35b96557 1018 #define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
Kojto 99:dbbf35b96557 1019 /**
Kojto 99:dbbf35b96557 1020 * @}
Kojto 99:dbbf35b96557 1021 */
Kojto 99:dbbf35b96557 1022
Kojto 99:dbbf35b96557 1023 /** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
Kojto 99:dbbf35b96557 1024 * @{
Kojto 99:dbbf35b96557 1025 */
Kojto 99:dbbf35b96557 1026 #define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
Kojto 99:dbbf35b96557 1027 /**
Kojto 99:dbbf35b96557 1028 * @}
Kojto 99:dbbf35b96557 1029 */
Kojto 119:aae6fcc7d9bb 1030
Kojto 119:aae6fcc7d9bb 1031 /** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose
Kojto 119:aae6fcc7d9bb 1032 * @{
Kojto 119:aae6fcc7d9bb 1033 */
Kojto 119:aae6fcc7d9bb 1034 #define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
Kojto 119:aae6fcc7d9bb 1035 /**
Kojto 119:aae6fcc7d9bb 1036 * @}
Kojto 119:aae6fcc7d9bb 1037 */
Kojto 99:dbbf35b96557 1038
Kojto 99:dbbf35b96557 1039
Kojto 99:dbbf35b96557 1040 /** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
Kojto 99:dbbf35b96557 1041 * @{
Kojto 99:dbbf35b96557 1042 */
Kojto 99:dbbf35b96557 1043
Kojto 99:dbbf35b96557 1044 /**
Kojto 99:dbbf35b96557 1045 * @}
Kojto 99:dbbf35b96557 1046 */
Kojto 99:dbbf35b96557 1047
Kojto 99:dbbf35b96557 1048 /* Exported macros ------------------------------------------------------------*/
Kojto 99:dbbf35b96557 1049
Kojto 99:dbbf35b96557 1050 /** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
Kojto 99:dbbf35b96557 1051 * @{
Kojto 99:dbbf35b96557 1052 */
Kojto 99:dbbf35b96557 1053 #define AES_IT_CC CRYP_IT_CC
Kojto 99:dbbf35b96557 1054 #define AES_IT_ERR CRYP_IT_ERR
Kojto 99:dbbf35b96557 1055 #define AES_FLAG_CCF CRYP_FLAG_CCF
Kojto 99:dbbf35b96557 1056 /**
Kojto 99:dbbf35b96557 1057 * @}
Kojto 99:dbbf35b96557 1058 */
Kojto 99:dbbf35b96557 1059
Kojto 99:dbbf35b96557 1060 /** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
Kojto 99:dbbf35b96557 1061 * @{
Kojto 99:dbbf35b96557 1062 */
Kojto 99:dbbf35b96557 1063 #define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE
Kojto 99:dbbf35b96557 1064 #define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH
Kojto 99:dbbf35b96557 1065 #define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
Kojto 99:dbbf35b96557 1066 #define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM
Kojto 99:dbbf35b96557 1067 #define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC
Kojto 99:dbbf35b96557 1068 #define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
Kojto 99:dbbf35b96557 1069 #define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC
Kojto 99:dbbf35b96557 1070 #define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI
Kojto 99:dbbf35b96557 1071 #define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK
Kojto 99:dbbf35b96557 1072 #define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG
Kojto 99:dbbf35b96557 1073 #define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG
Kojto 99:dbbf35b96557 1074 #define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE
Kojto 99:dbbf35b96557 1075 #define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE
Kojto 99:dbbf35b96557 1076
Kojto 99:dbbf35b96557 1077 #define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY
Kojto 99:dbbf35b96557 1078 #define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48
Kojto 99:dbbf35b96557 1079 #define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS
Kojto 99:dbbf35b96557 1080 #define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER
Kojto 99:dbbf35b96557 1081 #define CMP_PD_BitNumber CMP_PD_BIT_NUMBER
Kojto 99:dbbf35b96557 1082
Kojto 99:dbbf35b96557 1083 /**
Kojto 99:dbbf35b96557 1084 * @}
Kojto 99:dbbf35b96557 1085 */
Kojto 99:dbbf35b96557 1086
Kojto 99:dbbf35b96557 1087
Kojto 99:dbbf35b96557 1088 /** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
Kojto 99:dbbf35b96557 1089 * @{
Kojto 99:dbbf35b96557 1090 */
Kojto 99:dbbf35b96557 1091 #define __ADC_ENABLE __HAL_ADC_ENABLE
Kojto 99:dbbf35b96557 1092 #define __ADC_DISABLE __HAL_ADC_DISABLE
Kojto 99:dbbf35b96557 1093 #define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS
Kojto 99:dbbf35b96557 1094 #define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS
Kojto 99:dbbf35b96557 1095 #define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE
Kojto 99:dbbf35b96557 1096 #define __ADC_IS_ENABLED ADC_IS_ENABLE
Kojto 99:dbbf35b96557 1097 #define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR
Kojto 99:dbbf35b96557 1098 #define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED
Kojto 99:dbbf35b96557 1099 #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
Kojto 99:dbbf35b96557 1100 #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR
Kojto 99:dbbf35b96557 1101 #define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED
Kojto 99:dbbf35b96557 1102 #define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING
Kojto 99:dbbf35b96557 1103 #define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE
Kojto 99:dbbf35b96557 1104
Kojto 99:dbbf35b96557 1105 #define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
Kojto 99:dbbf35b96557 1106 #define __HAL_ADC_JSQR_RK ADC_JSQR_RK
Kojto 99:dbbf35b96557 1107 #define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT
Kojto 99:dbbf35b96557 1108 #define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR
Kojto 99:dbbf35b96557 1109 #define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION
Kojto 99:dbbf35b96557 1110 #define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE
Kojto 99:dbbf35b96557 1111 #define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS
Kojto 99:dbbf35b96557 1112 #define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS
Kojto 99:dbbf35b96557 1113 #define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM
Kojto 99:dbbf35b96557 1114 #define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT
Kojto 99:dbbf35b96557 1115 #define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS
Kojto 99:dbbf35b96557 1116 #define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN
Kojto 99:dbbf35b96557 1117 #define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ
Kojto 99:dbbf35b96557 1118 #define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET
Kojto 99:dbbf35b96557 1119 #define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET
Kojto 99:dbbf35b96557 1120 #define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL
Kojto 99:dbbf35b96557 1121 #define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL
Kojto 99:dbbf35b96557 1122 #define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET
Kojto 99:dbbf35b96557 1123 #define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET
Kojto 99:dbbf35b96557 1124 #define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD
Kojto 99:dbbf35b96557 1125
Kojto 99:dbbf35b96557 1126 #define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION
Kojto 99:dbbf35b96557 1127 #define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
Kojto 99:dbbf35b96557 1128 #define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
Kojto 99:dbbf35b96557 1129 #define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER
Kojto 99:dbbf35b96557 1130 #define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI
Kojto 99:dbbf35b96557 1131 #define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
Kojto 99:dbbf35b96557 1132 #define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
Kojto 99:dbbf35b96557 1133 #define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER
Kojto 99:dbbf35b96557 1134 #define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER
Kojto 99:dbbf35b96557 1135 #define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE
Kojto 99:dbbf35b96557 1136
Kojto 99:dbbf35b96557 1137 #define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT
Kojto 99:dbbf35b96557 1138 #define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT
Kojto 99:dbbf35b96557 1139 #define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL
Kojto 99:dbbf35b96557 1140 #define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM
Kojto 99:dbbf35b96557 1141 #define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET
Kojto 99:dbbf35b96557 1142 #define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE
Kojto 99:dbbf35b96557 1143 #define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE
Kojto 99:dbbf35b96557 1144 #define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER
Kojto 99:dbbf35b96557 1145
Kojto 99:dbbf35b96557 1146 #define __HAL_ADC_SQR1 ADC_SQR1
Kojto 99:dbbf35b96557 1147 #define __HAL_ADC_SMPR1 ADC_SMPR1
Kojto 99:dbbf35b96557 1148 #define __HAL_ADC_SMPR2 ADC_SMPR2
Kojto 99:dbbf35b96557 1149 #define __HAL_ADC_SQR3_RK ADC_SQR3_RK
Kojto 99:dbbf35b96557 1150 #define __HAL_ADC_SQR2_RK ADC_SQR2_RK
Kojto 99:dbbf35b96557 1151 #define __HAL_ADC_SQR1_RK ADC_SQR1_RK
Kojto 99:dbbf35b96557 1152 #define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS
Kojto 99:dbbf35b96557 1153 #define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS
Kojto 99:dbbf35b96557 1154 #define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV
Kojto 99:dbbf35b96557 1155 #define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection
Kojto 99:dbbf35b96557 1156 #define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq
Kojto 99:dbbf35b96557 1157 #define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
Kojto 99:dbbf35b96557 1158 #define __HAL_ADC_JSQR ADC_JSQR
Kojto 99:dbbf35b96557 1159
Kojto 99:dbbf35b96557 1160 #define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL
Kojto 99:dbbf35b96557 1161 #define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS
Kojto 99:dbbf35b96557 1162 #define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF
Kojto 99:dbbf35b96557 1163 #define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT
Kojto 99:dbbf35b96557 1164 #define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS
Kojto 99:dbbf35b96557 1165 #define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN
Kojto 99:dbbf35b96557 1166 #define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR
Kojto 99:dbbf35b96557 1167 #define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ
Kojto 99:dbbf35b96557 1168
Kojto 99:dbbf35b96557 1169 /**
Kojto 99:dbbf35b96557 1170 * @}
Kojto 99:dbbf35b96557 1171 */
Kojto 99:dbbf35b96557 1172
Kojto 99:dbbf35b96557 1173 /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
Kojto 99:dbbf35b96557 1174 * @{
Kojto 99:dbbf35b96557 1175 */
Kojto 99:dbbf35b96557 1176 #define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT
Kojto 99:dbbf35b96557 1177 #define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT
Kojto 99:dbbf35b96557 1178 #define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT
Kojto 99:dbbf35b96557 1179 #define IS_DAC_GENERATE_WAVE IS_DAC_WAVE
Kojto 99:dbbf35b96557 1180
Kojto 99:dbbf35b96557 1181 /**
Kojto 99:dbbf35b96557 1182 * @}
Kojto 99:dbbf35b96557 1183 */
Kojto 99:dbbf35b96557 1184
Kojto 99:dbbf35b96557 1185 /** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
Kojto 99:dbbf35b96557 1186 * @{
Kojto 99:dbbf35b96557 1187 */
Kojto 99:dbbf35b96557 1188 #define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
Kojto 99:dbbf35b96557 1189 #define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
Kojto 99:dbbf35b96557 1190 #define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
Kojto 99:dbbf35b96557 1191 #define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
Kojto 99:dbbf35b96557 1192 #define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
Kojto 99:dbbf35b96557 1193 #define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
Kojto 99:dbbf35b96557 1194 #define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
Kojto 99:dbbf35b96557 1195 #define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
Kojto 99:dbbf35b96557 1196 #define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
Kojto 99:dbbf35b96557 1197 #define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
Kojto 99:dbbf35b96557 1198 #define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
Kojto 99:dbbf35b96557 1199 #define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
Kojto 99:dbbf35b96557 1200 #define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
Kojto 99:dbbf35b96557 1201 #define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
Kojto 99:dbbf35b96557 1202 #define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
Kojto 99:dbbf35b96557 1203 #define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
Kojto 99:dbbf35b96557 1204
Kojto 99:dbbf35b96557 1205 #define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
Kojto 99:dbbf35b96557 1206 #define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
Kojto 99:dbbf35b96557 1207 #define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
Kojto 99:dbbf35b96557 1208 #define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
Kojto 99:dbbf35b96557 1209 #define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
Kojto 99:dbbf35b96557 1210 #define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
Kojto 99:dbbf35b96557 1211 #define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
Kojto 99:dbbf35b96557 1212 #define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
Kojto 99:dbbf35b96557 1213 #define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
Kojto 99:dbbf35b96557 1214 #define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
Kojto 99:dbbf35b96557 1215 #define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
Kojto 99:dbbf35b96557 1216 #define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
Kojto 99:dbbf35b96557 1217 #define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
Kojto 99:dbbf35b96557 1218 #define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
Kojto 99:dbbf35b96557 1219
Kojto 99:dbbf35b96557 1220
Kojto 99:dbbf35b96557 1221 #define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
Kojto 99:dbbf35b96557 1222 #define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
Kojto 99:dbbf35b96557 1223 #define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
Kojto 99:dbbf35b96557 1224 #define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
Kojto 99:dbbf35b96557 1225 #define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
Kojto 99:dbbf35b96557 1226 #define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
Kojto 99:dbbf35b96557 1227 #define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
Kojto 99:dbbf35b96557 1228 #define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
Kojto 99:dbbf35b96557 1229 #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
Kojto 99:dbbf35b96557 1230 #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
Kojto 99:dbbf35b96557 1231 #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
Kojto 99:dbbf35b96557 1232 #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
Kojto 99:dbbf35b96557 1233 #define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
Kojto 99:dbbf35b96557 1234 #define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
Kojto 99:dbbf35b96557 1235 #define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
Kojto 99:dbbf35b96557 1236 #define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
Kojto 99:dbbf35b96557 1237 #define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
Kojto 99:dbbf35b96557 1238 #define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
Kojto 99:dbbf35b96557 1239 #define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
Kojto 99:dbbf35b96557 1240 #define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
Kojto 99:dbbf35b96557 1241 #define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
Kojto 99:dbbf35b96557 1242 #define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
Kojto 99:dbbf35b96557 1243 #define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
Kojto 99:dbbf35b96557 1244 #define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
Kojto 99:dbbf35b96557 1245
Kojto 99:dbbf35b96557 1246 /**
Kojto 99:dbbf35b96557 1247 * @}
Kojto 99:dbbf35b96557 1248 */
Kojto 99:dbbf35b96557 1249
Kojto 99:dbbf35b96557 1250 /** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
Kojto 99:dbbf35b96557 1251 * @{
Kojto 99:dbbf35b96557 1252 */
Kojto 119:aae6fcc7d9bb 1253 #if defined(STM32F3)
Kojto 119:aae6fcc7d9bb 1254 #define COMP_START __HAL_COMP_ENABLE
Kojto 119:aae6fcc7d9bb 1255 #define COMP_STOP __HAL_COMP_DISABLE
Kojto 119:aae6fcc7d9bb 1256 #define COMP_LOCK __HAL_COMP_LOCK
Kojto 119:aae6fcc7d9bb 1257
Kojto 119:aae6fcc7d9bb 1258 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
Kojto 119:aae6fcc7d9bb 1259 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
Kojto 119:aae6fcc7d9bb 1260 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
Kojto 119:aae6fcc7d9bb 1261 __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
Kojto 119:aae6fcc7d9bb 1262 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
Kojto 119:aae6fcc7d9bb 1263 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
Kojto 119:aae6fcc7d9bb 1264 __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
Kojto 119:aae6fcc7d9bb 1265 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
Kojto 119:aae6fcc7d9bb 1266 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
Kojto 119:aae6fcc7d9bb 1267 __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
Kojto 119:aae6fcc7d9bb 1268 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
Kojto 119:aae6fcc7d9bb 1269 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
Kojto 119:aae6fcc7d9bb 1270 __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
Kojto 119:aae6fcc7d9bb 1271 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
Kojto 119:aae6fcc7d9bb 1272 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
Kojto 119:aae6fcc7d9bb 1273 __HAL_COMP_COMP6_EXTI_ENABLE_IT())
Kojto 119:aae6fcc7d9bb 1274 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
Kojto 119:aae6fcc7d9bb 1275 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
Kojto 119:aae6fcc7d9bb 1276 __HAL_COMP_COMP6_EXTI_DISABLE_IT())
Kojto 119:aae6fcc7d9bb 1277 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
Kojto 119:aae6fcc7d9bb 1278 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
Kojto 119:aae6fcc7d9bb 1279 __HAL_COMP_COMP6_EXTI_GET_FLAG())
Kojto 119:aae6fcc7d9bb 1280 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
Kojto 119:aae6fcc7d9bb 1281 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
Kojto 119:aae6fcc7d9bb 1282 __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
Kojto 119:aae6fcc7d9bb 1283 # endif
Kojto 119:aae6fcc7d9bb 1284 # if defined(STM32F302xE) || defined(STM32F302xC)
Kojto 119:aae6fcc7d9bb 1285 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
Kojto 119:aae6fcc7d9bb 1286 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
Kojto 119:aae6fcc7d9bb 1287 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
Kojto 119:aae6fcc7d9bb 1288 __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
Kojto 119:aae6fcc7d9bb 1289 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
Kojto 119:aae6fcc7d9bb 1290 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
Kojto 119:aae6fcc7d9bb 1291 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
Kojto 119:aae6fcc7d9bb 1292 __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
Kojto 119:aae6fcc7d9bb 1293 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
Kojto 119:aae6fcc7d9bb 1294 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
Kojto 119:aae6fcc7d9bb 1295 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
Kojto 119:aae6fcc7d9bb 1296 __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
Kojto 119:aae6fcc7d9bb 1297 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
Kojto 119:aae6fcc7d9bb 1298 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
Kojto 119:aae6fcc7d9bb 1299 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
Kojto 119:aae6fcc7d9bb 1300 __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
Kojto 119:aae6fcc7d9bb 1301 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
Kojto 119:aae6fcc7d9bb 1302 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
Kojto 119:aae6fcc7d9bb 1303 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
Kojto 119:aae6fcc7d9bb 1304 __HAL_COMP_COMP6_EXTI_ENABLE_IT())
Kojto 119:aae6fcc7d9bb 1305 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
Kojto 119:aae6fcc7d9bb 1306 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
Kojto 119:aae6fcc7d9bb 1307 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
Kojto 119:aae6fcc7d9bb 1308 __HAL_COMP_COMP6_EXTI_DISABLE_IT())
Kojto 119:aae6fcc7d9bb 1309 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
Kojto 119:aae6fcc7d9bb 1310 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
Kojto 119:aae6fcc7d9bb 1311 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
Kojto 119:aae6fcc7d9bb 1312 __HAL_COMP_COMP6_EXTI_GET_FLAG())
Kojto 119:aae6fcc7d9bb 1313 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
Kojto 119:aae6fcc7d9bb 1314 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
Kojto 119:aae6fcc7d9bb 1315 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
Kojto 119:aae6fcc7d9bb 1316 __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
Kojto 119:aae6fcc7d9bb 1317 # endif
Kojto 119:aae6fcc7d9bb 1318 # if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
Kojto 119:aae6fcc7d9bb 1319 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
Kojto 119:aae6fcc7d9bb 1320 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
Kojto 119:aae6fcc7d9bb 1321 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
Kojto 119:aae6fcc7d9bb 1322 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
Kojto 119:aae6fcc7d9bb 1323 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \
Kojto 119:aae6fcc7d9bb 1324 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \
Kojto 119:aae6fcc7d9bb 1325 __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
Kojto 119:aae6fcc7d9bb 1326 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
Kojto 119:aae6fcc7d9bb 1327 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
Kojto 119:aae6fcc7d9bb 1328 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \
Kojto 119:aae6fcc7d9bb 1329 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
Kojto 119:aae6fcc7d9bb 1330 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \
Kojto 119:aae6fcc7d9bb 1331 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \
Kojto 119:aae6fcc7d9bb 1332 __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
Kojto 119:aae6fcc7d9bb 1333 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
Kojto 119:aae6fcc7d9bb 1334 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
Kojto 119:aae6fcc7d9bb 1335 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \
Kojto 119:aae6fcc7d9bb 1336 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
Kojto 119:aae6fcc7d9bb 1337 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \
Kojto 119:aae6fcc7d9bb 1338 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \
Kojto 119:aae6fcc7d9bb 1339 __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
Kojto 119:aae6fcc7d9bb 1340 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
Kojto 119:aae6fcc7d9bb 1341 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
Kojto 119:aae6fcc7d9bb 1342 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \
Kojto 119:aae6fcc7d9bb 1343 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
Kojto 119:aae6fcc7d9bb 1344 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \
Kojto 119:aae6fcc7d9bb 1345 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \
Kojto 119:aae6fcc7d9bb 1346 __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
Kojto 119:aae6fcc7d9bb 1347 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
Kojto 119:aae6fcc7d9bb 1348 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
Kojto 119:aae6fcc7d9bb 1349 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \
Kojto 119:aae6fcc7d9bb 1350 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
Kojto 119:aae6fcc7d9bb 1351 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \
Kojto 119:aae6fcc7d9bb 1352 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \
Kojto 119:aae6fcc7d9bb 1353 __HAL_COMP_COMP7_EXTI_ENABLE_IT())
Kojto 119:aae6fcc7d9bb 1354 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
Kojto 119:aae6fcc7d9bb 1355 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
Kojto 119:aae6fcc7d9bb 1356 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \
Kojto 119:aae6fcc7d9bb 1357 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
Kojto 119:aae6fcc7d9bb 1358 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \
Kojto 119:aae6fcc7d9bb 1359 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \
Kojto 119:aae6fcc7d9bb 1360 __HAL_COMP_COMP7_EXTI_DISABLE_IT())
Kojto 119:aae6fcc7d9bb 1361 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
Kojto 119:aae6fcc7d9bb 1362 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
Kojto 119:aae6fcc7d9bb 1363 ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \
Kojto 119:aae6fcc7d9bb 1364 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
Kojto 119:aae6fcc7d9bb 1365 ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \
Kojto 119:aae6fcc7d9bb 1366 ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \
Kojto 119:aae6fcc7d9bb 1367 __HAL_COMP_COMP7_EXTI_GET_FLAG())
Kojto 119:aae6fcc7d9bb 1368 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
Kojto 119:aae6fcc7d9bb 1369 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
Kojto 119:aae6fcc7d9bb 1370 ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \
Kojto 119:aae6fcc7d9bb 1371 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
Kojto 119:aae6fcc7d9bb 1372 ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
Kojto 119:aae6fcc7d9bb 1373 ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
Kojto 119:aae6fcc7d9bb 1374 __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
Kojto 119:aae6fcc7d9bb 1375 # endif
Kojto 119:aae6fcc7d9bb 1376 # if defined(STM32F373xC) ||defined(STM32F378xx)
Kojto 99:dbbf35b96557 1377 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
Kojto 99:dbbf35b96557 1378 __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
Kojto 119:aae6fcc7d9bb 1379 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
Kojto 99:dbbf35b96557 1380 __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
Kojto 99:dbbf35b96557 1381 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
Kojto 99:dbbf35b96557 1382 __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
Kojto 119:aae6fcc7d9bb 1383 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
Kojto 99:dbbf35b96557 1384 __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
Kojto 119:aae6fcc7d9bb 1385 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
Kojto 99:dbbf35b96557 1386 __HAL_COMP_COMP2_EXTI_ENABLE_IT())
Kojto 119:aae6fcc7d9bb 1387 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
Kojto 99:dbbf35b96557 1388 __HAL_COMP_COMP2_EXTI_DISABLE_IT())
Kojto 119:aae6fcc7d9bb 1389 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
Kojto 99:dbbf35b96557 1390 __HAL_COMP_COMP2_EXTI_GET_FLAG())
Kojto 119:aae6fcc7d9bb 1391 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
Kojto 99:dbbf35b96557 1392 __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
Kojto 119:aae6fcc7d9bb 1393 # endif
Kojto 119:aae6fcc7d9bb 1394 #else
Kojto 119:aae6fcc7d9bb 1395 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
Kojto 119:aae6fcc7d9bb 1396 __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
Kojto 119:aae6fcc7d9bb 1397 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
Kojto 119:aae6fcc7d9bb 1398 __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
Kojto 119:aae6fcc7d9bb 1399 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
Kojto 119:aae6fcc7d9bb 1400 __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
Kojto 119:aae6fcc7d9bb 1401 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
Kojto 119:aae6fcc7d9bb 1402 __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
Kojto 119:aae6fcc7d9bb 1403 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
Kojto 119:aae6fcc7d9bb 1404 __HAL_COMP_COMP2_EXTI_ENABLE_IT())
Kojto 119:aae6fcc7d9bb 1405 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
Kojto 119:aae6fcc7d9bb 1406 __HAL_COMP_COMP2_EXTI_DISABLE_IT())
Kojto 119:aae6fcc7d9bb 1407 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
Kojto 119:aae6fcc7d9bb 1408 __HAL_COMP_COMP2_EXTI_GET_FLAG())
Kojto 119:aae6fcc7d9bb 1409 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
Kojto 119:aae6fcc7d9bb 1410 __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
Kojto 119:aae6fcc7d9bb 1411 #endif
Kojto 119:aae6fcc7d9bb 1412
Kojto 99:dbbf35b96557 1413 #define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE
Kojto 99:dbbf35b96557 1414
Kojto 99:dbbf35b96557 1415 /**
Kojto 99:dbbf35b96557 1416 * @}
Kojto 99:dbbf35b96557 1417 */
Kojto 99:dbbf35b96557 1418
Kojto 99:dbbf35b96557 1419 /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
Kojto 99:dbbf35b96557 1420 * @{
Kojto 99:dbbf35b96557 1421 */
Kojto 99:dbbf35b96557 1422
Kojto 99:dbbf35b96557 1423 #define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
Kojto 99:dbbf35b96557 1424 ((WAVE) == DAC_WAVE_NOISE)|| \
Kojto 99:dbbf35b96557 1425 ((WAVE) == DAC_WAVE_TRIANGLE))
Kojto 99:dbbf35b96557 1426
Kojto 99:dbbf35b96557 1427 /**
Kojto 99:dbbf35b96557 1428 * @}
Kojto 99:dbbf35b96557 1429 */
Kojto 99:dbbf35b96557 1430
Kojto 99:dbbf35b96557 1431 /** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
Kojto 99:dbbf35b96557 1432 * @{
Kojto 99:dbbf35b96557 1433 */
Kojto 99:dbbf35b96557 1434
Kojto 99:dbbf35b96557 1435 #define IS_WRPAREA IS_OB_WRPAREA
Kojto 99:dbbf35b96557 1436 #define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM
Kojto 99:dbbf35b96557 1437 #define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
Kojto 99:dbbf35b96557 1438 #define IS_TYPEERASE IS_FLASH_TYPEERASE
Kojto 119:aae6fcc7d9bb 1439 #define IS_NBSECTORS IS_FLASH_NBSECTORS
Kojto 119:aae6fcc7d9bb 1440 #define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE
Kojto 99:dbbf35b96557 1441
Kojto 99:dbbf35b96557 1442 /**
Kojto 99:dbbf35b96557 1443 * @}
Kojto 99:dbbf35b96557 1444 */
Kojto 99:dbbf35b96557 1445
Kojto 99:dbbf35b96557 1446 /** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
Kojto 99:dbbf35b96557 1447 * @{
Kojto 99:dbbf35b96557 1448 */
Kojto 99:dbbf35b96557 1449
Kojto 99:dbbf35b96557 1450 #define __HAL_I2C_RESET_CR2 I2C_RESET_CR2
Kojto 99:dbbf35b96557 1451 #define __HAL_I2C_GENERATE_START I2C_GENERATE_START
Kojto 99:dbbf35b96557 1452 #define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE
Kojto 99:dbbf35b96557 1453 #define __HAL_I2C_RISE_TIME I2C_RISE_TIME
Kojto 99:dbbf35b96557 1454 #define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD
Kojto 99:dbbf35b96557 1455 #define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST
Kojto 99:dbbf35b96557 1456 #define __HAL_I2C_SPEED I2C_SPEED
Kojto 99:dbbf35b96557 1457 #define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE
Kojto 99:dbbf35b96557 1458 #define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ
Kojto 99:dbbf35b96557 1459 #define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS
Kojto 99:dbbf35b96557 1460 #define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE
Kojto 99:dbbf35b96557 1461 #define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ
Kojto 99:dbbf35b96557 1462 #define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB
Kojto 99:dbbf35b96557 1463 #define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB
Kojto 99:dbbf35b96557 1464 #define __HAL_I2C_FREQRANGE I2C_FREQRANGE
Kojto 99:dbbf35b96557 1465 /**
Kojto 99:dbbf35b96557 1466 * @}
Kojto 99:dbbf35b96557 1467 */
Kojto 99:dbbf35b96557 1468
Kojto 99:dbbf35b96557 1469 /** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
Kojto 99:dbbf35b96557 1470 * @{
Kojto 99:dbbf35b96557 1471 */
Kojto 99:dbbf35b96557 1472
Kojto 99:dbbf35b96557 1473 #define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE
Kojto 99:dbbf35b96557 1474 #define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
Kojto 99:dbbf35b96557 1475
Kojto 99:dbbf35b96557 1476 /**
Kojto 99:dbbf35b96557 1477 * @}
Kojto 99:dbbf35b96557 1478 */
Kojto 99:dbbf35b96557 1479
Kojto 99:dbbf35b96557 1480 /** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
Kojto 99:dbbf35b96557 1481 * @{
Kojto 99:dbbf35b96557 1482 */
Kojto 99:dbbf35b96557 1483
Kojto 99:dbbf35b96557 1484 #define __IRDA_DISABLE __HAL_IRDA_DISABLE
Kojto 99:dbbf35b96557 1485 #define __IRDA_ENABLE __HAL_IRDA_ENABLE
Kojto 99:dbbf35b96557 1486
Kojto 99:dbbf35b96557 1487 #define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
Kojto 99:dbbf35b96557 1488 #define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
Kojto 99:dbbf35b96557 1489 #define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
Kojto 99:dbbf35b96557 1490 #define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
Kojto 99:dbbf35b96557 1491
Kojto 99:dbbf35b96557 1492 #define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE
Kojto 99:dbbf35b96557 1493
Kojto 99:dbbf35b96557 1494
Kojto 99:dbbf35b96557 1495 /**
Kojto 99:dbbf35b96557 1496 * @}
Kojto 99:dbbf35b96557 1497 */
Kojto 99:dbbf35b96557 1498
Kojto 99:dbbf35b96557 1499
Kojto 99:dbbf35b96557 1500 /** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
Kojto 99:dbbf35b96557 1501 * @{
Kojto 99:dbbf35b96557 1502 */
Kojto 99:dbbf35b96557 1503 #define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS
Kojto 99:dbbf35b96557 1504 #define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
Kojto 99:dbbf35b96557 1505 /**
Kojto 99:dbbf35b96557 1506 * @}
Kojto 99:dbbf35b96557 1507 */
Kojto 99:dbbf35b96557 1508
Kojto 99:dbbf35b96557 1509
Kojto 99:dbbf35b96557 1510 /** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
Kojto 99:dbbf35b96557 1511 * @{
Kojto 99:dbbf35b96557 1512 */
Kojto 99:dbbf35b96557 1513
Kojto 99:dbbf35b96557 1514 #define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT
Kojto 99:dbbf35b96557 1515 #define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT
Kojto 99:dbbf35b96557 1516 #define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE
Kojto 99:dbbf35b96557 1517
Kojto 99:dbbf35b96557 1518 /**
Kojto 99:dbbf35b96557 1519 * @}
Kojto 99:dbbf35b96557 1520 */
Kojto 99:dbbf35b96557 1521
Kojto 99:dbbf35b96557 1522
Kojto 99:dbbf35b96557 1523 /** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
Kojto 99:dbbf35b96557 1524 * @{
Kojto 99:dbbf35b96557 1525 */
Kojto 99:dbbf35b96557 1526 #define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD
Kojto 99:dbbf35b96557 1527 #define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX
Kojto 99:dbbf35b96557 1528 #define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX
Kojto 99:dbbf35b96557 1529 #define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX
Kojto 99:dbbf35b96557 1530 #define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX
Kojto 99:dbbf35b96557 1531 #define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L
Kojto 99:dbbf35b96557 1532 #define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H
Kojto 99:dbbf35b96557 1533 #define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM
Kojto 99:dbbf35b96557 1534 #define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES
Kojto 99:dbbf35b96557 1535 #define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX
Kojto 99:dbbf35b96557 1536 #define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT
Kojto 99:dbbf35b96557 1537 #define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION
Kojto 99:dbbf35b96557 1538 #define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET
Kojto 99:dbbf35b96557 1539
Kojto 99:dbbf35b96557 1540 /**
Kojto 99:dbbf35b96557 1541 * @}
Kojto 99:dbbf35b96557 1542 */
Kojto 99:dbbf35b96557 1543
Kojto 99:dbbf35b96557 1544
Kojto 99:dbbf35b96557 1545 /** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
Kojto 99:dbbf35b96557 1546 * @{
Kojto 99:dbbf35b96557 1547 */
Kojto 99:dbbf35b96557 1548 #define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
Kojto 99:dbbf35b96557 1549 #define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
Kojto 99:dbbf35b96557 1550 #define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
Kojto 99:dbbf35b96557 1551 #define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
Kojto 99:dbbf35b96557 1552 #define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
Kojto 99:dbbf35b96557 1553 #define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
Kojto 99:dbbf35b96557 1554 #define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE
Kojto 99:dbbf35b96557 1555 #define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE
Kojto 99:dbbf35b96557 1556 #define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
Kojto 99:dbbf35b96557 1557 #define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
Kojto 99:dbbf35b96557 1558 #define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
Kojto 99:dbbf35b96557 1559 #define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
Kojto 99:dbbf35b96557 1560 #define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine
Kojto 99:dbbf35b96557 1561 #define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine
Kojto 99:dbbf35b96557 1562 #define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig
Kojto 99:dbbf35b96557 1563 #define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig
Kojto 119:aae6fcc7d9bb 1564 #define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)
Kojto 99:dbbf35b96557 1565 #define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
Kojto 99:dbbf35b96557 1566 #define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
Kojto 99:dbbf35b96557 1567 #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
Kojto 99:dbbf35b96557 1568 #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
Kojto 99:dbbf35b96557 1569 #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
Kojto 99:dbbf35b96557 1570 #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
Kojto 99:dbbf35b96557 1571 #define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
Kojto 99:dbbf35b96557 1572 #define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
Kojto 119:aae6fcc7d9bb 1573 #define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)
Kojto 119:aae6fcc7d9bb 1574 #define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)
Kojto 99:dbbf35b96557 1575 #define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention
Kojto 99:dbbf35b96557 1576 #define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention
Kojto 99:dbbf35b96557 1577 #define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2
Kojto 99:dbbf35b96557 1578 #define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2
Kojto 99:dbbf35b96557 1579 #define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
Kojto 99:dbbf35b96557 1580 #define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
Kojto 99:dbbf35b96557 1581 #define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB
Kojto 99:dbbf35b96557 1582 #define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB
Kojto 99:dbbf35b96557 1583
Kojto 99:dbbf35b96557 1584 #if defined (STM32F4)
Kojto 99:dbbf35b96557 1585 #define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT()
Kojto 99:dbbf35b96557 1586 #define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT()
Kojto 99:dbbf35b96557 1587 #define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG()
Kojto 99:dbbf35b96557 1588 #define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
Kojto 99:dbbf35b96557 1589 #define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
Kojto 99:dbbf35b96557 1590 #else
Kojto 99:dbbf35b96557 1591 #define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG
Kojto 99:dbbf35b96557 1592 #define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT
Kojto 99:dbbf35b96557 1593 #define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT
Kojto 99:dbbf35b96557 1594 #define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT
Kojto 99:dbbf35b96557 1595 #define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG
Kojto 99:dbbf35b96557 1596 #endif /* STM32F4 */
Kojto 99:dbbf35b96557 1597 /**
Kojto 99:dbbf35b96557 1598 * @}
Kojto 99:dbbf35b96557 1599 */
Kojto 99:dbbf35b96557 1600
Kojto 99:dbbf35b96557 1601
Kojto 99:dbbf35b96557 1602 /** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
Kojto 99:dbbf35b96557 1603 * @{
Kojto 99:dbbf35b96557 1604 */
Kojto 99:dbbf35b96557 1605
Kojto 99:dbbf35b96557 1606 #define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI
Kojto 99:dbbf35b96557 1607 #define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
Kojto 99:dbbf35b96557 1608
Kojto 99:dbbf35b96557 1609 #define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
Kojto 99:dbbf35b96557 1610 #define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
Kojto 99:dbbf35b96557 1611
Kojto 99:dbbf35b96557 1612 #define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
Kojto 99:dbbf35b96557 1613 #define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
Kojto 99:dbbf35b96557 1614 #define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1615 #define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1616 #define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
Kojto 99:dbbf35b96557 1617 #define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
Kojto 99:dbbf35b96557 1618 #define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE
Kojto 99:dbbf35b96557 1619 #define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE
Kojto 99:dbbf35b96557 1620 #define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET
Kojto 99:dbbf35b96557 1621 #define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET
Kojto 99:dbbf35b96557 1622 #define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1623 #define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1624 #define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
Kojto 99:dbbf35b96557 1625 #define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
Kojto 99:dbbf35b96557 1626 #define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
Kojto 99:dbbf35b96557 1627 #define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
Kojto 99:dbbf35b96557 1628 #define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
Kojto 99:dbbf35b96557 1629 #define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
Kojto 99:dbbf35b96557 1630 #define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
Kojto 99:dbbf35b96557 1631 #define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
Kojto 99:dbbf35b96557 1632 #define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
Kojto 99:dbbf35b96557 1633 #define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
Kojto 99:dbbf35b96557 1634 #define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1635 #define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1636 #define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
Kojto 99:dbbf35b96557 1637 #define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
Kojto 99:dbbf35b96557 1638 #define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1639 #define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1640 #define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE
Kojto 99:dbbf35b96557 1641 #define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE
Kojto 99:dbbf35b96557 1642 #define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
Kojto 99:dbbf35b96557 1643 #define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET
Kojto 99:dbbf35b96557 1644 #define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
Kojto 99:dbbf35b96557 1645 #define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
Kojto 99:dbbf35b96557 1646 #define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
Kojto 99:dbbf35b96557 1647 #define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
Kojto 99:dbbf35b96557 1648 #define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
Kojto 99:dbbf35b96557 1649 #define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
Kojto 99:dbbf35b96557 1650 #define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
Kojto 99:dbbf35b96557 1651 #define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
Kojto 99:dbbf35b96557 1652 #define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
Kojto 99:dbbf35b96557 1653 #define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
Kojto 99:dbbf35b96557 1654 #define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
Kojto 99:dbbf35b96557 1655 #define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
Kojto 99:dbbf35b96557 1656 #define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
Kojto 99:dbbf35b96557 1657 #define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
Kojto 99:dbbf35b96557 1658 #define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
Kojto 99:dbbf35b96557 1659 #define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
Kojto 99:dbbf35b96557 1660 #define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
Kojto 99:dbbf35b96557 1661 #define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
Kojto 99:dbbf35b96557 1662 #define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
Kojto 99:dbbf35b96557 1663 #define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
Kojto 99:dbbf35b96557 1664 #define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
Kojto 99:dbbf35b96557 1665 #define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
Kojto 99:dbbf35b96557 1666 #define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1667 #define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1668 #define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
Kojto 99:dbbf35b96557 1669 #define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
Kojto 119:aae6fcc7d9bb 1670 #define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
Kojto 119:aae6fcc7d9bb 1671 #define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
Kojto 119:aae6fcc7d9bb 1672 #define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
Kojto 119:aae6fcc7d9bb 1673 #define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
Kojto 99:dbbf35b96557 1674 #define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
Kojto 99:dbbf35b96557 1675 #define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
Kojto 99:dbbf35b96557 1676 #define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
Kojto 99:dbbf35b96557 1677 #define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
Kojto 99:dbbf35b96557 1678 #define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
Kojto 99:dbbf35b96557 1679 #define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
Kojto 99:dbbf35b96557 1680 #define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE
Kojto 99:dbbf35b96557 1681 #define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE
Kojto 99:dbbf35b96557 1682 #define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET
Kojto 99:dbbf35b96557 1683 #define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET
Kojto 99:dbbf35b96557 1684 #define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1685 #define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1686 #define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
Kojto 99:dbbf35b96557 1687 #define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
Kojto 99:dbbf35b96557 1688 #define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
Kojto 99:dbbf35b96557 1689 #define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
Kojto 99:dbbf35b96557 1690 #define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1691 #define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1692 #define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
Kojto 99:dbbf35b96557 1693 #define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
Kojto 99:dbbf35b96557 1694 #define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
Kojto 99:dbbf35b96557 1695 #define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
Kojto 99:dbbf35b96557 1696 #define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
Kojto 99:dbbf35b96557 1697 #define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
Kojto 99:dbbf35b96557 1698 #define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
Kojto 99:dbbf35b96557 1699 #define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
Kojto 99:dbbf35b96557 1700 #define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1701 #define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1702 #define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
Kojto 99:dbbf35b96557 1703 #define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
Kojto 119:aae6fcc7d9bb 1704 #define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE
Kojto 119:aae6fcc7d9bb 1705 #define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE
Kojto 119:aae6fcc7d9bb 1706 #define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET
Kojto 119:aae6fcc7d9bb 1707 #define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET
Kojto 99:dbbf35b96557 1708 #define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
Kojto 99:dbbf35b96557 1709 #define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
Kojto 99:dbbf35b96557 1710 #define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1711 #define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1712 #define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
Kojto 99:dbbf35b96557 1713 #define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
Kojto 99:dbbf35b96557 1714 #define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
Kojto 99:dbbf35b96557 1715 #define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
Kojto 99:dbbf35b96557 1716 #define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1717 #define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1718 #define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
Kojto 99:dbbf35b96557 1719 #define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
Kojto 99:dbbf35b96557 1720 #define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
Kojto 99:dbbf35b96557 1721 #define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
Kojto 99:dbbf35b96557 1722 #define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1723 #define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1724 #define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
Kojto 99:dbbf35b96557 1725 #define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
Kojto 99:dbbf35b96557 1726 #define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
Kojto 99:dbbf35b96557 1727 #define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
Kojto 99:dbbf35b96557 1728 #define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
Kojto 99:dbbf35b96557 1729 #define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
Kojto 99:dbbf35b96557 1730 #define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
Kojto 99:dbbf35b96557 1731 #define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
Kojto 99:dbbf35b96557 1732 #define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
Kojto 99:dbbf35b96557 1733 #define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
Kojto 99:dbbf35b96557 1734 #define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
Kojto 99:dbbf35b96557 1735 #define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
Kojto 99:dbbf35b96557 1736 #define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
Kojto 99:dbbf35b96557 1737 #define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
Kojto 99:dbbf35b96557 1738 #define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1739 #define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1740 #define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
Kojto 99:dbbf35b96557 1741 #define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
Kojto 99:dbbf35b96557 1742 #define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE
Kojto 99:dbbf35b96557 1743 #define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE
Kojto 99:dbbf35b96557 1744 #define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET
Kojto 99:dbbf35b96557 1745 #define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET
Kojto 99:dbbf35b96557 1746 #define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1747 #define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1748 #define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
Kojto 99:dbbf35b96557 1749 #define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
Kojto 99:dbbf35b96557 1750 #define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1751 #define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1752 #define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
Kojto 99:dbbf35b96557 1753 #define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
Kojto 99:dbbf35b96557 1754 #define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
Kojto 99:dbbf35b96557 1755 #define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
Kojto 99:dbbf35b96557 1756 #define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
Kojto 99:dbbf35b96557 1757 #define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
Kojto 99:dbbf35b96557 1758 #define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1759 #define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1760 #define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
Kojto 99:dbbf35b96557 1761 #define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
Kojto 99:dbbf35b96557 1762 #define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
Kojto 99:dbbf35b96557 1763 #define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
Kojto 99:dbbf35b96557 1764 #define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1765 #define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1766 #define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
Kojto 99:dbbf35b96557 1767 #define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
Kojto 99:dbbf35b96557 1768 #define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
Kojto 99:dbbf35b96557 1769 #define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
Kojto 99:dbbf35b96557 1770 #define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1771 #define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1772 #define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
Kojto 99:dbbf35b96557 1773 #define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
Kojto 99:dbbf35b96557 1774 #define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
Kojto 99:dbbf35b96557 1775 #define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
Kojto 99:dbbf35b96557 1776 #define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1777 #define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1778 #define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
Kojto 99:dbbf35b96557 1779 #define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
Kojto 99:dbbf35b96557 1780 #define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
Kojto 99:dbbf35b96557 1781 #define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
Kojto 99:dbbf35b96557 1782 #define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1783 #define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1784 #define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
Kojto 99:dbbf35b96557 1785 #define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
Kojto 99:dbbf35b96557 1786 #define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
Kojto 99:dbbf35b96557 1787 #define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
Kojto 99:dbbf35b96557 1788 #define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1789 #define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1790 #define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
Kojto 99:dbbf35b96557 1791 #define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
Kojto 99:dbbf35b96557 1792 #define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
Kojto 99:dbbf35b96557 1793 #define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
Kojto 99:dbbf35b96557 1794 #define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1795 #define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1796 #define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
Kojto 99:dbbf35b96557 1797 #define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
Kojto 99:dbbf35b96557 1798 #define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
Kojto 99:dbbf35b96557 1799 #define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
Kojto 99:dbbf35b96557 1800 #define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1801 #define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1802 #define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
Kojto 99:dbbf35b96557 1803 #define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
Kojto 99:dbbf35b96557 1804 #define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
Kojto 99:dbbf35b96557 1805 #define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
Kojto 99:dbbf35b96557 1806 #define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1807 #define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1808 #define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
Kojto 99:dbbf35b96557 1809 #define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
Kojto 99:dbbf35b96557 1810 #define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
Kojto 99:dbbf35b96557 1811 #define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
Kojto 99:dbbf35b96557 1812 #define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1813 #define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1814 #define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
Kojto 99:dbbf35b96557 1815 #define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
Kojto 99:dbbf35b96557 1816 #define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
Kojto 99:dbbf35b96557 1817 #define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
Kojto 99:dbbf35b96557 1818 #define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1819 #define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1820 #define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
Kojto 99:dbbf35b96557 1821 #define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
Kojto 99:dbbf35b96557 1822 #define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
Kojto 99:dbbf35b96557 1823 #define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
Kojto 99:dbbf35b96557 1824 #define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1825 #define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1826 #define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
Kojto 99:dbbf35b96557 1827 #define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
Kojto 99:dbbf35b96557 1828 #define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
Kojto 99:dbbf35b96557 1829 #define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
Kojto 99:dbbf35b96557 1830 #define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1831 #define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1832 #define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
Kojto 99:dbbf35b96557 1833 #define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
Kojto 99:dbbf35b96557 1834 #define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
Kojto 99:dbbf35b96557 1835 #define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
Kojto 99:dbbf35b96557 1836 #define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1837 #define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1838 #define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
Kojto 99:dbbf35b96557 1839 #define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
Kojto 99:dbbf35b96557 1840 #define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
Kojto 99:dbbf35b96557 1841 #define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
Kojto 99:dbbf35b96557 1842 #define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1843 #define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1844 #define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
Kojto 99:dbbf35b96557 1845 #define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
Kojto 99:dbbf35b96557 1846 #define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
Kojto 99:dbbf35b96557 1847 #define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
Kojto 99:dbbf35b96557 1848 #define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1849 #define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1850 #define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
Kojto 99:dbbf35b96557 1851 #define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
Kojto 99:dbbf35b96557 1852 #define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
Kojto 99:dbbf35b96557 1853 #define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
Kojto 99:dbbf35b96557 1854 #define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1855 #define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1856 #define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
Kojto 99:dbbf35b96557 1857 #define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
Kojto 99:dbbf35b96557 1858 #define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
Kojto 99:dbbf35b96557 1859 #define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
Kojto 99:dbbf35b96557 1860 #define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1861 #define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1862 #define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
Kojto 99:dbbf35b96557 1863 #define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
Kojto 99:dbbf35b96557 1864 #define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
Kojto 99:dbbf35b96557 1865 #define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
Kojto 99:dbbf35b96557 1866 #define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1867 #define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1868 #define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
Kojto 99:dbbf35b96557 1869 #define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
Kojto 99:dbbf35b96557 1870 #define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
Kojto 99:dbbf35b96557 1871 #define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
Kojto 99:dbbf35b96557 1872 #define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1873 #define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1874 #define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
Kojto 99:dbbf35b96557 1875 #define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
Kojto 99:dbbf35b96557 1876 #define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
Kojto 99:dbbf35b96557 1877 #define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
Kojto 99:dbbf35b96557 1878 #define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1879 #define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1880 #define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
Kojto 99:dbbf35b96557 1881 #define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
Kojto 99:dbbf35b96557 1882 #define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
Kojto 99:dbbf35b96557 1883 #define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
Kojto 99:dbbf35b96557 1884 #define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1885 #define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1886 #define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
Kojto 99:dbbf35b96557 1887 #define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
Kojto 99:dbbf35b96557 1888 #define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
Kojto 99:dbbf35b96557 1889 #define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
Kojto 99:dbbf35b96557 1890 #define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
Kojto 99:dbbf35b96557 1891 #define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
Kojto 99:dbbf35b96557 1892 #define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1893 #define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1894 #define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
Kojto 99:dbbf35b96557 1895 #define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
Kojto 99:dbbf35b96557 1896 #define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
Kojto 99:dbbf35b96557 1897 #define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
Kojto 99:dbbf35b96557 1898 #define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1899 #define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1900 #define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
Kojto 99:dbbf35b96557 1901 #define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
Kojto 99:dbbf35b96557 1902 #define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
Kojto 99:dbbf35b96557 1903 #define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
Kojto 99:dbbf35b96557 1904 #define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1905 #define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1906 #define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
Kojto 99:dbbf35b96557 1907 #define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
Kojto 99:dbbf35b96557 1908 #define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
Kojto 99:dbbf35b96557 1909 #define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
Kojto 99:dbbf35b96557 1910 #define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1911 #define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1912 #define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
Kojto 99:dbbf35b96557 1913 #define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
Kojto 99:dbbf35b96557 1914 #define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
Kojto 99:dbbf35b96557 1915 #define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
Kojto 99:dbbf35b96557 1916 #define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1917 #define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1918 #define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1919 #define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1920 #define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
Kojto 99:dbbf35b96557 1921 #define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
Kojto 99:dbbf35b96557 1922 #define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1923 #define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1924 #define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
Kojto 99:dbbf35b96557 1925 #define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
Kojto 99:dbbf35b96557 1926 #define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
Kojto 99:dbbf35b96557 1927 #define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
Kojto 99:dbbf35b96557 1928 #define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1929 #define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1930 #define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
Kojto 99:dbbf35b96557 1931 #define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
Kojto 99:dbbf35b96557 1932 #define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
Kojto 99:dbbf35b96557 1933 #define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
Kojto 99:dbbf35b96557 1934 #define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1935 #define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1936 #define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
Kojto 99:dbbf35b96557 1937 #define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
Kojto 99:dbbf35b96557 1938 #define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
Kojto 99:dbbf35b96557 1939 #define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
Kojto 99:dbbf35b96557 1940 #define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
Kojto 99:dbbf35b96557 1941 #define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
Kojto 99:dbbf35b96557 1942 #define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
Kojto 99:dbbf35b96557 1943 #define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
Kojto 99:dbbf35b96557 1944 #define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
Kojto 99:dbbf35b96557 1945 #define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
Kojto 99:dbbf35b96557 1946 #define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
Kojto 99:dbbf35b96557 1947 #define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
Kojto 99:dbbf35b96557 1948 #define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
Kojto 99:dbbf35b96557 1949 #define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
Kojto 99:dbbf35b96557 1950 #define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
Kojto 99:dbbf35b96557 1951 #define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
Kojto 99:dbbf35b96557 1952 #define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
Kojto 99:dbbf35b96557 1953 #define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
Kojto 99:dbbf35b96557 1954 #define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
Kojto 99:dbbf35b96557 1955 #define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
Kojto 99:dbbf35b96557 1956 #define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
Kojto 99:dbbf35b96557 1957 #define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
Kojto 99:dbbf35b96557 1958 #define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
Kojto 99:dbbf35b96557 1959 #define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
Kojto 99:dbbf35b96557 1960 #define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1961 #define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1962 #define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
Kojto 99:dbbf35b96557 1963 #define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
Kojto 99:dbbf35b96557 1964 #define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
Kojto 99:dbbf35b96557 1965 #define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
Kojto 99:dbbf35b96557 1966 #define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1967 #define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1968 #define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
Kojto 99:dbbf35b96557 1969 #define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
Kojto 99:dbbf35b96557 1970 #define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
Kojto 99:dbbf35b96557 1971 #define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
Kojto 99:dbbf35b96557 1972 #define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1973 #define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1974 #define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
Kojto 99:dbbf35b96557 1975 #define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
Kojto 99:dbbf35b96557 1976 #define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
Kojto 99:dbbf35b96557 1977 #define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
Kojto 99:dbbf35b96557 1978 #define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1979 #define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1980 #define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
Kojto 99:dbbf35b96557 1981 #define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
Kojto 99:dbbf35b96557 1982 #define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
Kojto 99:dbbf35b96557 1983 #define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
Kojto 99:dbbf35b96557 1984 #define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1985 #define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1986 #define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
Kojto 99:dbbf35b96557 1987 #define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
Kojto 99:dbbf35b96557 1988 #define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
Kojto 99:dbbf35b96557 1989 #define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
Kojto 99:dbbf35b96557 1990 #define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1991 #define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1992 #define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
Kojto 99:dbbf35b96557 1993 #define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
Kojto 99:dbbf35b96557 1994 #define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
Kojto 99:dbbf35b96557 1995 #define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
Kojto 99:dbbf35b96557 1996 #define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1997 #define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1998 #define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
Kojto 99:dbbf35b96557 1999 #define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
Kojto 99:dbbf35b96557 2000 #define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
Kojto 99:dbbf35b96557 2001 #define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
Kojto 99:dbbf35b96557 2002 #define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 2003 #define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 2004 #define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
Kojto 99:dbbf35b96557 2005 #define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
Kojto 99:dbbf35b96557 2006 #define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
Kojto 99:dbbf35b96557 2007 #define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
Kojto 99:dbbf35b96557 2008 #define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 2009 #define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 2010 #define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
Kojto 99:dbbf35b96557 2011 #define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
Kojto 99:dbbf35b96557 2012 #define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
Kojto 99:dbbf35b96557 2013 #define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
Kojto 99:dbbf35b96557 2014 #define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 2015 #define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 2016 #define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
Kojto 99:dbbf35b96557 2017 #define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
Kojto 99:dbbf35b96557 2018 #define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
Kojto 99:dbbf35b96557 2019 #define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
Kojto 99:dbbf35b96557 2020 #define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
Kojto 99:dbbf35b96557 2021 #define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
Kojto 99:dbbf35b96557 2022 #define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
Kojto 99:dbbf35b96557 2023 #define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
Kojto 99:dbbf35b96557 2024 #define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 2025 #define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 2026 #define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
Kojto 99:dbbf35b96557 2027 #define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
Kojto 99:dbbf35b96557 2028 #define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
Kojto 99:dbbf35b96557 2029 #define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
Kojto 99:dbbf35b96557 2030 #define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 2031 #define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 2032 #define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
Kojto 99:dbbf35b96557 2033 #define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
Kojto 99:dbbf35b96557 2034 #define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
Kojto 99:dbbf35b96557 2035 #define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
Kojto 99:dbbf35b96557 2036 #define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 2037 #define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 2038 #define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
Kojto 99:dbbf35b96557 2039 #define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
Kojto 99:dbbf35b96557 2040 #define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
Kojto 99:dbbf35b96557 2041 #define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
Kojto 99:dbbf35b96557 2042 #define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 2043 #define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 2044 #define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
Kojto 99:dbbf35b96557 2045 #define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
Kojto 99:dbbf35b96557 2046 #define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
Kojto 99:dbbf35b96557 2047 #define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
Kojto 99:dbbf35b96557 2048 #define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 2049 #define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 2050 #define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
Kojto 99:dbbf35b96557 2051 #define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
Kojto 99:dbbf35b96557 2052 #define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
Kojto 99:dbbf35b96557 2053 #define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
Kojto 99:dbbf35b96557 2054 #define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 2055 #define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 2056 #define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
Kojto 99:dbbf35b96557 2057 #define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
Kojto 119:aae6fcc7d9bb 2058 #define __USART4_CLK_DISABLE __HAL_RCC_USART4_CLK_DISABLE
Kojto 119:aae6fcc7d9bb 2059 #define __USART4_CLK_ENABLE __HAL_RCC_USART4_CLK_ENABLE
Kojto 119:aae6fcc7d9bb 2060 #define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_USART4_CLK_SLEEP_ENABLE
Kojto 119:aae6fcc7d9bb 2061 #define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_USART4_CLK_SLEEP_DISABLE
Kojto 119:aae6fcc7d9bb 2062 #define __USART4_FORCE_RESET __HAL_RCC_USART4_FORCE_RESET
Kojto 119:aae6fcc7d9bb 2063 #define __USART4_RELEASE_RESET __HAL_RCC_USART4_RELEASE_RESET
Kojto 119:aae6fcc7d9bb 2064 #define __USART5_CLK_DISABLE __HAL_RCC_USART5_CLK_DISABLE
Kojto 119:aae6fcc7d9bb 2065 #define __USART5_CLK_ENABLE __HAL_RCC_USART5_CLK_ENABLE
Kojto 119:aae6fcc7d9bb 2066 #define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_USART5_CLK_SLEEP_ENABLE
Kojto 119:aae6fcc7d9bb 2067 #define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_USART5_CLK_SLEEP_DISABLE
Kojto 119:aae6fcc7d9bb 2068 #define __USART5_FORCE_RESET __HAL_RCC_USART5_FORCE_RESET
Kojto 119:aae6fcc7d9bb 2069 #define __USART5_RELEASE_RESET __HAL_RCC_USART5_RELEASE_RESET
Kojto 119:aae6fcc7d9bb 2070 #define __USART7_CLK_DISABLE __HAL_RCC_USART7_CLK_DISABLE
Kojto 119:aae6fcc7d9bb 2071 #define __USART7_CLK_ENABLE __HAL_RCC_USART7_CLK_ENABLE
Kojto 119:aae6fcc7d9bb 2072 #define __USART7_FORCE_RESET __HAL_RCC_USART7_FORCE_RESET
Kojto 119:aae6fcc7d9bb 2073 #define __USART7_RELEASE_RESET __HAL_RCC_USART7_RELEASE_RESET
Kojto 119:aae6fcc7d9bb 2074 #define __USART8_CLK_DISABLE __HAL_RCC_USART8_CLK_DISABLE
Kojto 119:aae6fcc7d9bb 2075 #define __USART8_CLK_ENABLE __HAL_RCC_USART8_CLK_ENABLE
Kojto 119:aae6fcc7d9bb 2076 #define __USART8_FORCE_RESET __HAL_RCC_USART8_FORCE_RESET
Kojto 119:aae6fcc7d9bb 2077 #define __USART8_RELEASE_RESET __HAL_RCC_USART8_RELEASE_RESET
Kojto 99:dbbf35b96557 2078 #define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE
Kojto 99:dbbf35b96557 2079 #define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE
Kojto 99:dbbf35b96557 2080 #define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET
Kojto 99:dbbf35b96557 2081 #define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 2082 #define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 2083 #define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
Kojto 99:dbbf35b96557 2084 #define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
Kojto 99:dbbf35b96557 2085 #define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
Kojto 99:dbbf35b96557 2086 #define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
Kojto 99:dbbf35b96557 2087 #define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
Kojto 99:dbbf35b96557 2088 #define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 2089 #define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 2090 #define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
Kojto 99:dbbf35b96557 2091 #define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
Kojto 99:dbbf35b96557 2092 #define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE
Kojto 99:dbbf35b96557 2093 #define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE
Kojto 99:dbbf35b96557 2094 #define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET
Kojto 99:dbbf35b96557 2095 #define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET
Kojto 99:dbbf35b96557 2096 #define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 2097 #define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 2098 #define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE
Kojto 99:dbbf35b96557 2099 #define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE
Kojto 99:dbbf35b96557 2100 #define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET
Kojto 99:dbbf35b96557 2101 #define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET
Kojto 99:dbbf35b96557 2102 #define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 2103 #define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 2104 #define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
Kojto 99:dbbf35b96557 2105 #define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
Kojto 99:dbbf35b96557 2106 #define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 2107 #define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 2108 #define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
Kojto 99:dbbf35b96557 2109 #define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
Kojto 99:dbbf35b96557 2110 #define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
Kojto 99:dbbf35b96557 2111 #define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
Kojto 99:dbbf35b96557 2112
Kojto 99:dbbf35b96557 2113 #define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
Kojto 99:dbbf35b96557 2114 #define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
Kojto 99:dbbf35b96557 2115 #define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 2116 #define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 2117 #define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE
Kojto 99:dbbf35b96557 2118 #define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE
Kojto 99:dbbf35b96557 2119 #define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
Kojto 99:dbbf35b96557 2120 #define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
Kojto 99:dbbf35b96557 2121 #define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 2122 #define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 2123 #define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 2124 #define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 2125 #define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 2126 #define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 2127 #define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 2128 #define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 2129 #define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE
Kojto 99:dbbf35b96557 2130 #define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE
Kojto 99:dbbf35b96557 2131 #define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE
Kojto 99:dbbf35b96557 2132 #define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET
Kojto 99:dbbf35b96557 2133 #define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET
Kojto 99:dbbf35b96557 2134 #define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 2135 #define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 2136 #define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE
Kojto 99:dbbf35b96557 2137 #define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE
Kojto 99:dbbf35b96557 2138 #define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE
Kojto 99:dbbf35b96557 2139 #define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET
Kojto 99:dbbf35b96557 2140 #define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET
Kojto 99:dbbf35b96557 2141 #define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 2142 #define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 2143 #define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE
Kojto 99:dbbf35b96557 2144 #define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE
Kojto 99:dbbf35b96557 2145 #define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET
Kojto 99:dbbf35b96557 2146 #define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET
Kojto 99:dbbf35b96557 2147 #define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 2148 #define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 2149 #define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE
Kojto 99:dbbf35b96557 2150 #define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE
Kojto 99:dbbf35b96557 2151 #define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET
Kojto 99:dbbf35b96557 2152 #define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET
Kojto 99:dbbf35b96557 2153 #define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 2154 #define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 2155 #define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 2156 #define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 2157 #define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 2158 #define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 2159 #define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 2160 #define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 2161 #define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 2162 #define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 2163 #define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 2164 #define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 2165 #define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 2166 #define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE
Kojto 99:dbbf35b96557 2167 #define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE
Kojto 99:dbbf35b96557 2168 #define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 2169 #define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 2170 #define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
Kojto 99:dbbf35b96557 2171 #define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
Kojto 99:dbbf35b96557 2172 #define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE
Kojto 99:dbbf35b96557 2173 #define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE
Kojto 99:dbbf35b96557 2174 #define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET
Kojto 99:dbbf35b96557 2175 #define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET
Kojto 99:dbbf35b96557 2176 #define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 2177 #define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 2178 #define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE
Kojto 99:dbbf35b96557 2179 #define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE
Kojto 99:dbbf35b96557 2180 #define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET
Kojto 99:dbbf35b96557 2181 #define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET
Kojto 99:dbbf35b96557 2182 #define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 2183 #define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 2184 #define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE
Kojto 99:dbbf35b96557 2185 #define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE
Kojto 99:dbbf35b96557 2186 #define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET
Kojto 99:dbbf35b96557 2187 #define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET
Kojto 99:dbbf35b96557 2188 #define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 2189 #define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 2190 #define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE
Kojto 99:dbbf35b96557 2191 #define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE
Kojto 99:dbbf35b96557 2192 #define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET
Kojto 99:dbbf35b96557 2193 #define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET
Kojto 99:dbbf35b96557 2194 #define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 2195 #define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 2196 #define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE
Kojto 99:dbbf35b96557 2197 #define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE
Kojto 99:dbbf35b96557 2198 #define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET
Kojto 99:dbbf35b96557 2199 #define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 2200 #define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 2201 #define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE
Kojto 99:dbbf35b96557 2202 #define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE
Kojto 99:dbbf35b96557 2203 #define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE
Kojto 99:dbbf35b96557 2204 #define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE
Kojto 99:dbbf35b96557 2205 #define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET
Kojto 99:dbbf35b96557 2206 #define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET
Kojto 99:dbbf35b96557 2207 #define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 2208 #define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 2209 #define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
Kojto 99:dbbf35b96557 2210 #define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
Kojto 99:dbbf35b96557 2211 #define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
Kojto 99:dbbf35b96557 2212 #define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
Kojto 99:dbbf35b96557 2213 #define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 2214 #define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 2215 #define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
Kojto 99:dbbf35b96557 2216 #define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
Kojto 99:dbbf35b96557 2217 #define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
Kojto 99:dbbf35b96557 2218 #define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
Kojto 99:dbbf35b96557 2219 #define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 2220 #define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE
Kojto 119:aae6fcc7d9bb 2221 #define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
Kojto 119:aae6fcc7d9bb 2222 #define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
Kojto 119:aae6fcc7d9bb 2223 #define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
Kojto 119:aae6fcc7d9bb 2224 #define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
Kojto 119:aae6fcc7d9bb 2225 #define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
Kojto 119:aae6fcc7d9bb 2226 #define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
Kojto 119:aae6fcc7d9bb 2227 #define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
Kojto 119:aae6fcc7d9bb 2228 #define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
Kojto 119:aae6fcc7d9bb 2229 #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
Kojto 119:aae6fcc7d9bb 2230 #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
Kojto 119:aae6fcc7d9bb 2231 #define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
Kojto 119:aae6fcc7d9bb 2232 #define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
Kojto 119:aae6fcc7d9bb 2233 #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
Kojto 119:aae6fcc7d9bb 2234 #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
Kojto 119:aae6fcc7d9bb 2235 #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
Kojto 119:aae6fcc7d9bb 2236 #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
Kojto 119:aae6fcc7d9bb 2237 #define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
Kojto 119:aae6fcc7d9bb 2238 #define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
Kojto 119:aae6fcc7d9bb 2239 #define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
Kojto 119:aae6fcc7d9bb 2240 #define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
Kojto 119:aae6fcc7d9bb 2241 #define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE
Kojto 119:aae6fcc7d9bb 2242 #define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE
Kojto 119:aae6fcc7d9bb 2243 #define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
Kojto 119:aae6fcc7d9bb 2244 #define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
Kojto 119:aae6fcc7d9bb 2245 #define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
Kojto 119:aae6fcc7d9bb 2246 #define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
Kojto 119:aae6fcc7d9bb 2247 #define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET
Kojto 119:aae6fcc7d9bb 2248 #define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET
Kojto 119:aae6fcc7d9bb 2249 #define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
Kojto 119:aae6fcc7d9bb 2250 #define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
Kojto 119:aae6fcc7d9bb 2251 #define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
Kojto 119:aae6fcc7d9bb 2252 #define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
Kojto 119:aae6fcc7d9bb 2253 #define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
Kojto 119:aae6fcc7d9bb 2254 #define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
Kojto 119:aae6fcc7d9bb 2255 #define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE
Kojto 119:aae6fcc7d9bb 2256 #define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE
Kojto 119:aae6fcc7d9bb 2257 #define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET
Kojto 99:dbbf35b96557 2258 #define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET
Kojto 119:aae6fcc7d9bb 2259 #define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
Kojto 119:aae6fcc7d9bb 2260 #define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 2261
Kojto 99:dbbf35b96557 2262 /* alias define maintained for legacy */
Kojto 99:dbbf35b96557 2263 #define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
Kojto 99:dbbf35b96557 2264 #define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
Kojto 99:dbbf35b96557 2265
Kojto 119:aae6fcc7d9bb 2266 #define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
Kojto 119:aae6fcc7d9bb 2267 #define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
Kojto 119:aae6fcc7d9bb 2268 #define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE
Kojto 119:aae6fcc7d9bb 2269 #define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE
Kojto 119:aae6fcc7d9bb 2270 #define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
Kojto 119:aae6fcc7d9bb 2271 #define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
Kojto 119:aae6fcc7d9bb 2272 #define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE
Kojto 119:aae6fcc7d9bb 2273 #define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE
Kojto 119:aae6fcc7d9bb 2274 #define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE
Kojto 119:aae6fcc7d9bb 2275 #define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE
Kojto 119:aae6fcc7d9bb 2276 #define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE
Kojto 119:aae6fcc7d9bb 2277 #define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE
Kojto 119:aae6fcc7d9bb 2278 #define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE
Kojto 119:aae6fcc7d9bb 2279 #define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE
Kojto 119:aae6fcc7d9bb 2280 #define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE
Kojto 119:aae6fcc7d9bb 2281 #define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE
Kojto 119:aae6fcc7d9bb 2282 #define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE
Kojto 119:aae6fcc7d9bb 2283 #define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE
Kojto 119:aae6fcc7d9bb 2284 #define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE
Kojto 119:aae6fcc7d9bb 2285 #define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE
Kojto 119:aae6fcc7d9bb 2286 #define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE
Kojto 119:aae6fcc7d9bb 2287 #define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE
Kojto 119:aae6fcc7d9bb 2288
Kojto 119:aae6fcc7d9bb 2289 #define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
Kojto 119:aae6fcc7d9bb 2290 #define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
Kojto 119:aae6fcc7d9bb 2291 #define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET
Kojto 119:aae6fcc7d9bb 2292 #define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET
Kojto 119:aae6fcc7d9bb 2293 #define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
Kojto 119:aae6fcc7d9bb 2294 #define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
Kojto 119:aae6fcc7d9bb 2295 #define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET
Kojto 119:aae6fcc7d9bb 2296 #define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET
Kojto 119:aae6fcc7d9bb 2297 #define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET
Kojto 119:aae6fcc7d9bb 2298 #define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET
Kojto 119:aae6fcc7d9bb 2299 #define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET
Kojto 119:aae6fcc7d9bb 2300 #define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET
Kojto 119:aae6fcc7d9bb 2301 #define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET
Kojto 119:aae6fcc7d9bb 2302 #define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET
Kojto 119:aae6fcc7d9bb 2303 #define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET
Kojto 119:aae6fcc7d9bb 2304 #define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET
Kojto 119:aae6fcc7d9bb 2305 #define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET
Kojto 119:aae6fcc7d9bb 2306 #define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET
Kojto 119:aae6fcc7d9bb 2307 #define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET
Kojto 119:aae6fcc7d9bb 2308 #define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET
Kojto 119:aae6fcc7d9bb 2309 #define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET
Kojto 119:aae6fcc7d9bb 2310 #define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET
Kojto 119:aae6fcc7d9bb 2311
Kojto 119:aae6fcc7d9bb 2312 #define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED
Kojto 119:aae6fcc7d9bb 2313 #define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED
Kojto 119:aae6fcc7d9bb 2314 #define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
Kojto 119:aae6fcc7d9bb 2315 #define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
Kojto 119:aae6fcc7d9bb 2316 #define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED
Kojto 119:aae6fcc7d9bb 2317 #define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED
Kojto 119:aae6fcc7d9bb 2318 #define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED
Kojto 119:aae6fcc7d9bb 2319 #define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED
Kojto 119:aae6fcc7d9bb 2320 #define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED
Kojto 119:aae6fcc7d9bb 2321 #define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED
Kojto 119:aae6fcc7d9bb 2322 #define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED
Kojto 119:aae6fcc7d9bb 2323 #define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED
Kojto 119:aae6fcc7d9bb 2324 #define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED
Kojto 119:aae6fcc7d9bb 2325 #define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED
Kojto 119:aae6fcc7d9bb 2326 #define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED
Kojto 119:aae6fcc7d9bb 2327 #define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED
Kojto 119:aae6fcc7d9bb 2328 #define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED
Kojto 119:aae6fcc7d9bb 2329 #define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED
Kojto 119:aae6fcc7d9bb 2330 #define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED
Kojto 119:aae6fcc7d9bb 2331 #define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED
Kojto 119:aae6fcc7d9bb 2332 #define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED
Kojto 119:aae6fcc7d9bb 2333 #define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED
Kojto 119:aae6fcc7d9bb 2334 #define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED
Kojto 119:aae6fcc7d9bb 2335 #define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED
Kojto 119:aae6fcc7d9bb 2336 #define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED
Kojto 119:aae6fcc7d9bb 2337 #define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED
Kojto 119:aae6fcc7d9bb 2338 #define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED
Kojto 119:aae6fcc7d9bb 2339 #define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED
Kojto 119:aae6fcc7d9bb 2340 #define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED
Kojto 119:aae6fcc7d9bb 2341 #define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED
Kojto 119:aae6fcc7d9bb 2342 #define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED
Kojto 119:aae6fcc7d9bb 2343 #define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED
Kojto 119:aae6fcc7d9bb 2344 #define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED
Kojto 119:aae6fcc7d9bb 2345 #define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED
Kojto 119:aae6fcc7d9bb 2346 #define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED
Kojto 119:aae6fcc7d9bb 2347 #define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED
Kojto 119:aae6fcc7d9bb 2348 #define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED
Kojto 119:aae6fcc7d9bb 2349 #define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED
Kojto 119:aae6fcc7d9bb 2350 #define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED
Kojto 119:aae6fcc7d9bb 2351 #define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED
Kojto 119:aae6fcc7d9bb 2352 #define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED
Kojto 119:aae6fcc7d9bb 2353 #define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED
Kojto 119:aae6fcc7d9bb 2354 #define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED
Kojto 119:aae6fcc7d9bb 2355 #define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED
Kojto 119:aae6fcc7d9bb 2356 #define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED
Kojto 119:aae6fcc7d9bb 2357 #define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED
Kojto 119:aae6fcc7d9bb 2358 #define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED
Kojto 119:aae6fcc7d9bb 2359 #define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED
Kojto 119:aae6fcc7d9bb 2360 #define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED
Kojto 119:aae6fcc7d9bb 2361 #define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED
Kojto 119:aae6fcc7d9bb 2362 #define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED
Kojto 119:aae6fcc7d9bb 2363 #define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED
Kojto 119:aae6fcc7d9bb 2364 #define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED
Kojto 119:aae6fcc7d9bb 2365 #define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED
Kojto 119:aae6fcc7d9bb 2366 #define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED
Kojto 119:aae6fcc7d9bb 2367 #define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED
Kojto 119:aae6fcc7d9bb 2368 #define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED
Kojto 119:aae6fcc7d9bb 2369 #define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED
Kojto 119:aae6fcc7d9bb 2370 #define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED
Kojto 119:aae6fcc7d9bb 2371 #define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED
Kojto 119:aae6fcc7d9bb 2372 #define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED
Kojto 119:aae6fcc7d9bb 2373 #define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED
Kojto 119:aae6fcc7d9bb 2374 #define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED
Kojto 119:aae6fcc7d9bb 2375 #define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED
Kojto 119:aae6fcc7d9bb 2376 #define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED
Kojto 119:aae6fcc7d9bb 2377 #define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED
Kojto 119:aae6fcc7d9bb 2378 #define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED
Kojto 119:aae6fcc7d9bb 2379 #define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED
Kojto 119:aae6fcc7d9bb 2380 #define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED
Kojto 119:aae6fcc7d9bb 2381 #define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED
Kojto 119:aae6fcc7d9bb 2382 #define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED
Kojto 119:aae6fcc7d9bb 2383 #define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED
Kojto 119:aae6fcc7d9bb 2384 #define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED
Kojto 119:aae6fcc7d9bb 2385 #define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED
Kojto 119:aae6fcc7d9bb 2386 #define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED
Kojto 119:aae6fcc7d9bb 2387 #define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED
Kojto 119:aae6fcc7d9bb 2388 #define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED
Kojto 119:aae6fcc7d9bb 2389 #define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED
Kojto 119:aae6fcc7d9bb 2390 #define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED
Kojto 119:aae6fcc7d9bb 2391 #define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED
Kojto 119:aae6fcc7d9bb 2392 #define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED
Kojto 119:aae6fcc7d9bb 2393 #define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED
Kojto 119:aae6fcc7d9bb 2394 #define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED
Kojto 119:aae6fcc7d9bb 2395 #define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED
Kojto 119:aae6fcc7d9bb 2396 #define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED
Kojto 119:aae6fcc7d9bb 2397 #define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED
Kojto 119:aae6fcc7d9bb 2398 #define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED
Kojto 119:aae6fcc7d9bb 2399 #define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED
Kojto 119:aae6fcc7d9bb 2400 #define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED
Kojto 119:aae6fcc7d9bb 2401 #define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED
Kojto 119:aae6fcc7d9bb 2402 #define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED
Kojto 119:aae6fcc7d9bb 2403 #define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED
Kojto 119:aae6fcc7d9bb 2404 #define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED
Kojto 119:aae6fcc7d9bb 2405 #define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED
Kojto 119:aae6fcc7d9bb 2406 #define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED
Kojto 119:aae6fcc7d9bb 2407 #define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED
Kojto 119:aae6fcc7d9bb 2408 #define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED
Kojto 119:aae6fcc7d9bb 2409 #define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED
Kojto 119:aae6fcc7d9bb 2410 #define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED
Kojto 119:aae6fcc7d9bb 2411 #define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED
Kojto 119:aae6fcc7d9bb 2412 #define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED
Kojto 119:aae6fcc7d9bb 2413 #define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED
Kojto 119:aae6fcc7d9bb 2414 #define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED
Kojto 119:aae6fcc7d9bb 2415 #define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED
Kojto 119:aae6fcc7d9bb 2416 #define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED
Kojto 119:aae6fcc7d9bb 2417 #define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED
Kojto 119:aae6fcc7d9bb 2418 #define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED
Kojto 119:aae6fcc7d9bb 2419 #define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED
Kojto 119:aae6fcc7d9bb 2420 #define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED
Kojto 119:aae6fcc7d9bb 2421 #define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED
Kojto 119:aae6fcc7d9bb 2422 #define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED
Kojto 119:aae6fcc7d9bb 2423 #define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED
Kojto 119:aae6fcc7d9bb 2424 #define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED
Kojto 119:aae6fcc7d9bb 2425 #define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED
Kojto 119:aae6fcc7d9bb 2426 #define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED
Kojto 119:aae6fcc7d9bb 2427 #define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED
Kojto 119:aae6fcc7d9bb 2428
Kojto 119:aae6fcc7d9bb 2429 #if defined(STM32F4)
Kojto 119:aae6fcc7d9bb 2430 #define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
Kojto 119:aae6fcc7d9bb 2431 #define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
Kojto 119:aae6fcc7d9bb 2432 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
Kojto 119:aae6fcc7d9bb 2433 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
Kojto 119:aae6fcc7d9bb 2434 #define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
Kojto 119:aae6fcc7d9bb 2435 #define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
Kojto 119:aae6fcc7d9bb 2436 #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED
Kojto 119:aae6fcc7d9bb 2437 #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED
Kojto 119:aae6fcc7d9bb 2438 #define Sdmmc1ClockSelection SdioClockSelection
Kojto 119:aae6fcc7d9bb 2439 #define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO
Kojto 119:aae6fcc7d9bb 2440 #define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48
Kojto 119:aae6fcc7d9bb 2441 #define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK
Kojto 119:aae6fcc7d9bb 2442 #define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG
Kojto 119:aae6fcc7d9bb 2443 #define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE
Kojto 119:aae6fcc7d9bb 2444 #endif
Kojto 119:aae6fcc7d9bb 2445
Kojto 119:aae6fcc7d9bb 2446 #if defined(STM32F7) || defined(STM32L4)
Kojto 119:aae6fcc7d9bb 2447 #define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET
Kojto 119:aae6fcc7d9bb 2448 #define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET
Kojto 119:aae6fcc7d9bb 2449 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE
Kojto 119:aae6fcc7d9bb 2450 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE
Kojto 119:aae6fcc7d9bb 2451 #define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE
Kojto 119:aae6fcc7d9bb 2452 #define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE
Kojto 119:aae6fcc7d9bb 2453 #define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED
Kojto 119:aae6fcc7d9bb 2454 #define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED
Kojto 119:aae6fcc7d9bb 2455 #define SdioClockSelection Sdmmc1ClockSelection
Kojto 119:aae6fcc7d9bb 2456 #define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1
Kojto 119:aae6fcc7d9bb 2457 #define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG
Kojto 119:aae6fcc7d9bb 2458 #define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE
Kojto 119:aae6fcc7d9bb 2459 #endif
Kojto 119:aae6fcc7d9bb 2460
Kojto 119:aae6fcc7d9bb 2461 #if defined(STM32F7)
Kojto 119:aae6fcc7d9bb 2462 #define RCC_SDIOCLKSOURCE_CK48 RCC_SDMMC1CLKSOURCE_CLK48
Kojto 119:aae6fcc7d9bb 2463 #define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK
Kojto 119:aae6fcc7d9bb 2464 #endif
Kojto 119:aae6fcc7d9bb 2465
Kojto 99:dbbf35b96557 2466 #define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG
Kojto 99:dbbf35b96557 2467 #define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG
Kojto 99:dbbf35b96557 2468
Kojto 119:aae6fcc7d9bb 2469 #define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE
Kojto 119:aae6fcc7d9bb 2470
Kojto 119:aae6fcc7d9bb 2471 #define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE
Kojto 119:aae6fcc7d9bb 2472 #define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE
Kojto 119:aae6fcc7d9bb 2473 #define IS_RCC_SYSCLK_DIV IS_RCC_HCLK
Kojto 119:aae6fcc7d9bb 2474 #define IS_RCC_HCLK_DIV IS_RCC_PCLK
Kojto 119:aae6fcc7d9bb 2475 #define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK
Kojto 119:aae6fcc7d9bb 2476
Kojto 119:aae6fcc7d9bb 2477 #define RCC_IT_HSI14 RCC_IT_HSI14RDY
Kojto 119:aae6fcc7d9bb 2478
Kojto 119:aae6fcc7d9bb 2479 #if defined(STM32L0)
Kojto 119:aae6fcc7d9bb 2480 #define RCC_IT_LSECSS RCC_IT_CSSLSE
Kojto 119:aae6fcc7d9bb 2481 #define RCC_IT_CSS RCC_IT_CSSHSE
Kojto 119:aae6fcc7d9bb 2482 #endif
Kojto 99:dbbf35b96557 2483
Kojto 119:aae6fcc7d9bb 2484 #define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE
Kojto 119:aae6fcc7d9bb 2485 #define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG
Kojto 119:aae6fcc7d9bb 2486 #define RCC_MCO_NODIV RCC_MCODIV_1
Kojto 119:aae6fcc7d9bb 2487 #define RCC_MCO_DIV1 RCC_MCODIV_1
Kojto 119:aae6fcc7d9bb 2488 #define RCC_MCO_DIV2 RCC_MCODIV_2
Kojto 119:aae6fcc7d9bb 2489 #define RCC_MCO_DIV4 RCC_MCODIV_4
Kojto 119:aae6fcc7d9bb 2490 #define RCC_MCO_DIV8 RCC_MCODIV_8
Kojto 119:aae6fcc7d9bb 2491 #define RCC_MCO_DIV16 RCC_MCODIV_16
Kojto 119:aae6fcc7d9bb 2492 #define RCC_MCO_DIV32 RCC_MCODIV_32
Kojto 119:aae6fcc7d9bb 2493 #define RCC_MCO_DIV64 RCC_MCODIV_64
Kojto 119:aae6fcc7d9bb 2494 #define RCC_MCO_DIV128 RCC_MCODIV_128
Kojto 119:aae6fcc7d9bb 2495 #define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK
Kojto 119:aae6fcc7d9bb 2496 #define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI
Kojto 119:aae6fcc7d9bb 2497 #define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE
Kojto 119:aae6fcc7d9bb 2498 #define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK
Kojto 119:aae6fcc7d9bb 2499 #define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI
Kojto 119:aae6fcc7d9bb 2500 #define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14
Kojto 119:aae6fcc7d9bb 2501 #define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48
Kojto 119:aae6fcc7d9bb 2502 #define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE
Kojto 119:aae6fcc7d9bb 2503 #define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK
Kojto 119:aae6fcc7d9bb 2504 #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
Kojto 119:aae6fcc7d9bb 2505 #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
Kojto 99:dbbf35b96557 2506
Kojto 119:aae6fcc7d9bb 2507 #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
Kojto 119:aae6fcc7d9bb 2508
Kojto 119:aae6fcc7d9bb 2509 #define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1
Kojto 119:aae6fcc7d9bb 2510 #define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL
Kojto 119:aae6fcc7d9bb 2511 #define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI
Kojto 119:aae6fcc7d9bb 2512 #define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL
Kojto 119:aae6fcc7d9bb 2513 #define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL
Kojto 119:aae6fcc7d9bb 2514 #define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5
Kojto 119:aae6fcc7d9bb 2515 #define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2
Kojto 119:aae6fcc7d9bb 2516 #define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3
Kojto 99:dbbf35b96557 2517
Kojto 99:dbbf35b96557 2518 #define HSION_BitNumber RCC_HSION_BIT_NUMBER
Kojto 119:aae6fcc7d9bb 2519 #define HSION_BITNUMBER RCC_HSION_BIT_NUMBER
Kojto 119:aae6fcc7d9bb 2520 #define HSEON_BitNumber RCC_HSEON_BIT_NUMBER
Kojto 119:aae6fcc7d9bb 2521 #define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER
Kojto 119:aae6fcc7d9bb 2522 #define MSION_BITNUMBER RCC_MSION_BIT_NUMBER
Kojto 99:dbbf35b96557 2523 #define CSSON_BitNumber RCC_CSSON_BIT_NUMBER
Kojto 119:aae6fcc7d9bb 2524 #define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER
Kojto 99:dbbf35b96557 2525 #define PLLON_BitNumber RCC_PLLON_BIT_NUMBER
Kojto 119:aae6fcc7d9bb 2526 #define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER
Kojto 99:dbbf35b96557 2527 #define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER
Kojto 99:dbbf35b96557 2528 #define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER
Kojto 99:dbbf35b96557 2529 #define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER
Kojto 119:aae6fcc7d9bb 2530 #define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER
Kojto 99:dbbf35b96557 2531 #define BDRST_BitNumber RCC_BDRST_BIT_NUMBER
Kojto 119:aae6fcc7d9bb 2532 #define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER
Kojto 119:aae6fcc7d9bb 2533 #define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER
Kojto 99:dbbf35b96557 2534 #define LSION_BitNumber RCC_LSION_BIT_NUMBER
Kojto 119:aae6fcc7d9bb 2535 #define LSION_BITNUMBER RCC_LSION_BIT_NUMBER
Kojto 119:aae6fcc7d9bb 2536 #define LSEON_BitNumber RCC_LSEON_BIT_NUMBER
Kojto 119:aae6fcc7d9bb 2537 #define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER
Kojto 119:aae6fcc7d9bb 2538 #define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER
Kojto 99:dbbf35b96557 2539 #define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER
Kojto 99:dbbf35b96557 2540 #define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER
Kojto 119:aae6fcc7d9bb 2541 #define RMVF_BitNumber RCC_RMVF_BIT_NUMBER
Kojto 119:aae6fcc7d9bb 2542 #define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER
Kojto 119:aae6fcc7d9bb 2543 #define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER
Kojto 99:dbbf35b96557 2544 #define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS
Kojto 99:dbbf35b96557 2545 #define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS
Kojto 99:dbbf35b96557 2546 #define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS
Kojto 99:dbbf35b96557 2547 #define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS
Kojto 99:dbbf35b96557 2548 #define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE
Kojto 99:dbbf35b96557 2549 #define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE
Kojto 99:dbbf35b96557 2550
Kojto 99:dbbf35b96557 2551 #define CR_HSION_BB RCC_CR_HSION_BB
Kojto 99:dbbf35b96557 2552 #define CR_CSSON_BB RCC_CR_CSSON_BB
Kojto 99:dbbf35b96557 2553 #define CR_PLLON_BB RCC_CR_PLLON_BB
Kojto 99:dbbf35b96557 2554 #define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB
Kojto 99:dbbf35b96557 2555 #define CR_MSION_BB RCC_CR_MSION_BB
Kojto 99:dbbf35b96557 2556 #define CSR_LSION_BB RCC_CSR_LSION_BB
Kojto 99:dbbf35b96557 2557 #define CSR_LSEON_BB RCC_CSR_LSEON_BB
Kojto 99:dbbf35b96557 2558 #define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB
Kojto 99:dbbf35b96557 2559 #define CSR_RTCEN_BB RCC_CSR_RTCEN_BB
Kojto 99:dbbf35b96557 2560 #define CSR_RTCRST_BB RCC_CSR_RTCRST_BB
Kojto 99:dbbf35b96557 2561 #define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB
Kojto 99:dbbf35b96557 2562 #define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB
Kojto 99:dbbf35b96557 2563 #define BDCR_BDRST_BB RCC_BDCR_BDRST_BB
Kojto 119:aae6fcc7d9bb 2564 #define CR_HSEON_BB RCC_CR_HSEON_BB
Kojto 119:aae6fcc7d9bb 2565 #define CSR_RMVF_BB RCC_CSR_RMVF_BB
Kojto 99:dbbf35b96557 2566 #define CR_PLLSAION_BB RCC_CR_PLLSAION_BB
Kojto 99:dbbf35b96557 2567 #define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB
Kojto 99:dbbf35b96557 2568
Kojto 119:aae6fcc7d9bb 2569 #define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE
Kojto 119:aae6fcc7d9bb 2570 #define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE
Kojto 119:aae6fcc7d9bb 2571 #define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE
Kojto 119:aae6fcc7d9bb 2572 #define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE
Kojto 119:aae6fcc7d9bb 2573 #define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE
Kojto 119:aae6fcc7d9bb 2574
Kojto 119:aae6fcc7d9bb 2575 #define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT
Kojto 99:dbbf35b96557 2576 /**
Kojto 99:dbbf35b96557 2577 * @}
Kojto 99:dbbf35b96557 2578 */
Kojto 99:dbbf35b96557 2579
Kojto 99:dbbf35b96557 2580 /** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
Kojto 99:dbbf35b96557 2581 * @{
Kojto 99:dbbf35b96557 2582 */
Kojto 99:dbbf35b96557 2583 #define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)
Kojto 99:dbbf35b96557 2584
Kojto 99:dbbf35b96557 2585 /**
Kojto 99:dbbf35b96557 2586 * @}
Kojto 99:dbbf35b96557 2587 */
Kojto 99:dbbf35b96557 2588
Kojto 99:dbbf35b96557 2589 /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
Kojto 99:dbbf35b96557 2590 * @{
Kojto 99:dbbf35b96557 2591 */
Kojto 99:dbbf35b96557 2592
Kojto 99:dbbf35b96557 2593 #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
Kojto 99:dbbf35b96557 2594 #define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT
Kojto 99:dbbf35b96557 2595 #define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT
Kojto 99:dbbf35b96557 2596
Kojto 119:aae6fcc7d9bb 2597 #if defined (STM32F1)
Kojto 99:dbbf35b96557 2598 #define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
Kojto 99:dbbf35b96557 2599
Kojto 99:dbbf35b96557 2600 #define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT()
Kojto 99:dbbf35b96557 2601
Kojto 99:dbbf35b96557 2602 #define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT()
Kojto 99:dbbf35b96557 2603
Kojto 99:dbbf35b96557 2604 #define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG()
Kojto 99:dbbf35b96557 2605
Kojto 99:dbbf35b96557 2606 #define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
Kojto 119:aae6fcc7d9bb 2607 #else
Kojto 119:aae6fcc7d9bb 2608 #define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
Kojto 119:aae6fcc7d9bb 2609 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
Kojto 119:aae6fcc7d9bb 2610 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
Kojto 119:aae6fcc7d9bb 2611 #define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
Kojto 119:aae6fcc7d9bb 2612 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
Kojto 119:aae6fcc7d9bb 2613 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
Kojto 119:aae6fcc7d9bb 2614 #define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
Kojto 119:aae6fcc7d9bb 2615 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
Kojto 119:aae6fcc7d9bb 2616 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
Kojto 119:aae6fcc7d9bb 2617 #define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
Kojto 119:aae6fcc7d9bb 2618 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
Kojto 119:aae6fcc7d9bb 2619 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
Kojto 119:aae6fcc7d9bb 2620 #define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
Kojto 119:aae6fcc7d9bb 2621 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
Kojto 119:aae6fcc7d9bb 2622 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
Kojto 119:aae6fcc7d9bb 2623 #endif /* STM32F1 */
Kojto 99:dbbf35b96557 2624
Kojto 99:dbbf35b96557 2625 #define IS_ALARM IS_RTC_ALARM
Kojto 99:dbbf35b96557 2626 #define IS_ALARM_MASK IS_RTC_ALARM_MASK
Kojto 99:dbbf35b96557 2627 #define IS_TAMPER IS_RTC_TAMPER
Kojto 99:dbbf35b96557 2628 #define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE
Kojto 99:dbbf35b96557 2629 #define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER
Kojto 99:dbbf35b96557 2630 #define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT
Kojto 99:dbbf35b96557 2631 #define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE
Kojto 99:dbbf35b96557 2632 #define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION
Kojto 99:dbbf35b96557 2633 #define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE
Kojto 99:dbbf35b96557 2634 #define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ
Kojto 99:dbbf35b96557 2635 #define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
Kojto 99:dbbf35b96557 2636 #define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER
Kojto 99:dbbf35b96557 2637 #define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK
Kojto 99:dbbf35b96557 2638 #define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER
Kojto 99:dbbf35b96557 2639
Kojto 99:dbbf35b96557 2640 #define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
Kojto 99:dbbf35b96557 2641 #define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
Kojto 99:dbbf35b96557 2642
Kojto 99:dbbf35b96557 2643 /**
Kojto 99:dbbf35b96557 2644 * @}
Kojto 99:dbbf35b96557 2645 */
Kojto 99:dbbf35b96557 2646
Kojto 99:dbbf35b96557 2647 /** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose
Kojto 99:dbbf35b96557 2648 * @{
Kojto 99:dbbf35b96557 2649 */
Kojto 99:dbbf35b96557 2650
Kojto 99:dbbf35b96557 2651 #define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
Kojto 99:dbbf35b96557 2652 #define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
Kojto 119:aae6fcc7d9bb 2653
Kojto 119:aae6fcc7d9bb 2654 #if defined(STM32F4)
Kojto 119:aae6fcc7d9bb 2655 #define SD_SDMMC_DISABLED SD_SDIO_DISABLED
Kojto 119:aae6fcc7d9bb 2656 #define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY
Kojto 119:aae6fcc7d9bb 2657 #define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED
Kojto 119:aae6fcc7d9bb 2658 #define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION
Kojto 119:aae6fcc7d9bb 2659 #define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND
Kojto 119:aae6fcc7d9bb 2660 #define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT
Kojto 119:aae6fcc7d9bb 2661 #define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED
Kojto 119:aae6fcc7d9bb 2662 #define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE
Kojto 119:aae6fcc7d9bb 2663 #define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE
Kojto 119:aae6fcc7d9bb 2664 #define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE
Kojto 119:aae6fcc7d9bb 2665 #define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL
Kojto 119:aae6fcc7d9bb 2666 #define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT
Kojto 119:aae6fcc7d9bb 2667 #define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT
Kojto 119:aae6fcc7d9bb 2668 #define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG
Kojto 119:aae6fcc7d9bb 2669 #define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG
Kojto 119:aae6fcc7d9bb 2670 #define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT
Kojto 119:aae6fcc7d9bb 2671 #define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT
Kojto 119:aae6fcc7d9bb 2672 #define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS
Kojto 119:aae6fcc7d9bb 2673 #define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT
Kojto 119:aae6fcc7d9bb 2674 #define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND
Kojto 119:aae6fcc7d9bb 2675 /* alias CMSIS */
Kojto 119:aae6fcc7d9bb 2676 #define SDMMC1_IRQn SDIO_IRQn
Kojto 119:aae6fcc7d9bb 2677 #define SDMMC1_IRQHandler SDIO_IRQHandler
Kojto 119:aae6fcc7d9bb 2678 #endif
Kojto 119:aae6fcc7d9bb 2679
Kojto 119:aae6fcc7d9bb 2680 #if defined(STM32F7) || defined(STM32L4)
Kojto 119:aae6fcc7d9bb 2681 #define SD_SDIO_DISABLED SD_SDMMC_DISABLED
Kojto 119:aae6fcc7d9bb 2682 #define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY
Kojto 119:aae6fcc7d9bb 2683 #define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED
Kojto 119:aae6fcc7d9bb 2684 #define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION
Kojto 119:aae6fcc7d9bb 2685 #define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND
Kojto 119:aae6fcc7d9bb 2686 #define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT
Kojto 119:aae6fcc7d9bb 2687 #define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED
Kojto 119:aae6fcc7d9bb 2688 #define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE
Kojto 119:aae6fcc7d9bb 2689 #define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE
Kojto 119:aae6fcc7d9bb 2690 #define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE
Kojto 119:aae6fcc7d9bb 2691 #define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE
Kojto 119:aae6fcc7d9bb 2692 #define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT
Kojto 119:aae6fcc7d9bb 2693 #define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT
Kojto 119:aae6fcc7d9bb 2694 #define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG
Kojto 119:aae6fcc7d9bb 2695 #define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG
Kojto 119:aae6fcc7d9bb 2696 #define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT
Kojto 119:aae6fcc7d9bb 2697 #define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT
Kojto 119:aae6fcc7d9bb 2698 #define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
Kojto 119:aae6fcc7d9bb 2699 #define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
Kojto 119:aae6fcc7d9bb 2700 #define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
Kojto 119:aae6fcc7d9bb 2701 /* alias CMSIS for compatibilities */
Kojto 119:aae6fcc7d9bb 2702 #define SDIO_IRQn SDMMC1_IRQn
Kojto 119:aae6fcc7d9bb 2703 #define SDIO_IRQHandler SDMMC1_IRQHandler
Kojto 119:aae6fcc7d9bb 2704 #endif
Kojto 99:dbbf35b96557 2705 /**
Kojto 99:dbbf35b96557 2706 * @}
Kojto 99:dbbf35b96557 2707 */
Kojto 99:dbbf35b96557 2708
Kojto 99:dbbf35b96557 2709 /** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
Kojto 99:dbbf35b96557 2710 * @{
Kojto 99:dbbf35b96557 2711 */
Kojto 99:dbbf35b96557 2712
Kojto 99:dbbf35b96557 2713 #define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT
Kojto 99:dbbf35b96557 2714 #define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT
Kojto 99:dbbf35b96557 2715 #define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE
Kojto 99:dbbf35b96557 2716 #define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE
Kojto 99:dbbf35b96557 2717 #define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE
Kojto 99:dbbf35b96557 2718 #define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
Kojto 99:dbbf35b96557 2719
Kojto 99:dbbf35b96557 2720 #define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
Kojto 99:dbbf35b96557 2721 #define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
Kojto 99:dbbf35b96557 2722
Kojto 99:dbbf35b96557 2723 #define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE
Kojto 99:dbbf35b96557 2724
Kojto 99:dbbf35b96557 2725 /**
Kojto 99:dbbf35b96557 2726 * @}
Kojto 99:dbbf35b96557 2727 */
Kojto 99:dbbf35b96557 2728
Kojto 99:dbbf35b96557 2729 /** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
Kojto 99:dbbf35b96557 2730 * @{
Kojto 99:dbbf35b96557 2731 */
Kojto 99:dbbf35b96557 2732 #define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1
Kojto 99:dbbf35b96557 2733 #define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2
Kojto 99:dbbf35b96557 2734 #define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START
Kojto 99:dbbf35b96557 2735 #define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH
Kojto 99:dbbf35b96557 2736 #define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR
Kojto 99:dbbf35b96557 2737 #define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE
Kojto 99:dbbf35b96557 2738 #define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE
Kojto 99:dbbf35b96557 2739 #define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED
Kojto 99:dbbf35b96557 2740 /**
Kojto 99:dbbf35b96557 2741 * @}
Kojto 99:dbbf35b96557 2742 */
Kojto 99:dbbf35b96557 2743
Kojto 99:dbbf35b96557 2744 /** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
Kojto 99:dbbf35b96557 2745 * @{
Kojto 99:dbbf35b96557 2746 */
Kojto 99:dbbf35b96557 2747
Kojto 99:dbbf35b96557 2748 #define __HAL_SPI_1LINE_TX SPI_1LINE_TX
Kojto 99:dbbf35b96557 2749 #define __HAL_SPI_1LINE_RX SPI_1LINE_RX
Kojto 99:dbbf35b96557 2750 #define __HAL_SPI_RESET_CRC SPI_RESET_CRC
Kojto 99:dbbf35b96557 2751
Kojto 99:dbbf35b96557 2752 /**
Kojto 99:dbbf35b96557 2753 * @}
Kojto 99:dbbf35b96557 2754 */
Kojto 99:dbbf35b96557 2755
Kojto 99:dbbf35b96557 2756 /** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
Kojto 99:dbbf35b96557 2757 * @{
Kojto 99:dbbf35b96557 2758 */
Kojto 99:dbbf35b96557 2759
Kojto 99:dbbf35b96557 2760 #define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
Kojto 99:dbbf35b96557 2761 #define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION
Kojto 99:dbbf35b96557 2762 #define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
Kojto 99:dbbf35b96557 2763 #define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION
Kojto 99:dbbf35b96557 2764
Kojto 99:dbbf35b96557 2765 #define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD
Kojto 99:dbbf35b96557 2766
Kojto 99:dbbf35b96557 2767 #define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE
Kojto 99:dbbf35b96557 2768 #define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE
Kojto 99:dbbf35b96557 2769
Kojto 99:dbbf35b96557 2770 /**
Kojto 99:dbbf35b96557 2771 * @}
Kojto 99:dbbf35b96557 2772 */
Kojto 99:dbbf35b96557 2773
Kojto 99:dbbf35b96557 2774
Kojto 99:dbbf35b96557 2775 /** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
Kojto 99:dbbf35b96557 2776 * @{
Kojto 99:dbbf35b96557 2777 */
Kojto 99:dbbf35b96557 2778
Kojto 99:dbbf35b96557 2779 #define __USART_ENABLE_IT __HAL_USART_ENABLE_IT
Kojto 99:dbbf35b96557 2780 #define __USART_DISABLE_IT __HAL_USART_DISABLE_IT
Kojto 99:dbbf35b96557 2781 #define __USART_ENABLE __HAL_USART_ENABLE
Kojto 99:dbbf35b96557 2782 #define __USART_DISABLE __HAL_USART_DISABLE
Kojto 99:dbbf35b96557 2783
Kojto 99:dbbf35b96557 2784 #define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
Kojto 99:dbbf35b96557 2785 #define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
Kojto 99:dbbf35b96557 2786
Kojto 99:dbbf35b96557 2787 /**
Kojto 99:dbbf35b96557 2788 * @}
Kojto 99:dbbf35b96557 2789 */
Kojto 99:dbbf35b96557 2790
Kojto 99:dbbf35b96557 2791 /** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
Kojto 99:dbbf35b96557 2792 * @{
Kojto 99:dbbf35b96557 2793 */
Kojto 99:dbbf35b96557 2794 #define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE
Kojto 99:dbbf35b96557 2795
Kojto 99:dbbf35b96557 2796 #define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
Kojto 99:dbbf35b96557 2797 #define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
Kojto 99:dbbf35b96557 2798 #define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
Kojto 99:dbbf35b96557 2799 #define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE
Kojto 99:dbbf35b96557 2800
Kojto 99:dbbf35b96557 2801 #define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
Kojto 99:dbbf35b96557 2802 #define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
Kojto 99:dbbf35b96557 2803 #define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
Kojto 99:dbbf35b96557 2804 #define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE
Kojto 99:dbbf35b96557 2805
Kojto 99:dbbf35b96557 2806 #define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT
Kojto 99:dbbf35b96557 2807 #define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT
Kojto 99:dbbf35b96557 2808 #define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG
Kojto 99:dbbf35b96557 2809 #define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
Kojto 99:dbbf35b96557 2810 #define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
Kojto 99:dbbf35b96557 2811 #define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
Kojto 99:dbbf35b96557 2812 #define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
Kojto 99:dbbf35b96557 2813
Kojto 99:dbbf35b96557 2814 #define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
Kojto 99:dbbf35b96557 2815 #define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
Kojto 99:dbbf35b96557 2816 #define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
Kojto 99:dbbf35b96557 2817 #define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
Kojto 99:dbbf35b96557 2818 #define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
Kojto 99:dbbf35b96557 2819 #define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
Kojto 99:dbbf35b96557 2820 #define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
Kojto 99:dbbf35b96557 2821 #define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
Kojto 99:dbbf35b96557 2822
Kojto 99:dbbf35b96557 2823 #define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
Kojto 99:dbbf35b96557 2824 #define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
Kojto 99:dbbf35b96557 2825 #define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
Kojto 99:dbbf35b96557 2826 #define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
Kojto 99:dbbf35b96557 2827 #define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
Kojto 99:dbbf35b96557 2828 #define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
Kojto 99:dbbf35b96557 2829 #define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
Kojto 99:dbbf35b96557 2830 #define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
Kojto 99:dbbf35b96557 2831
Kojto 99:dbbf35b96557 2832 #define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup
Kojto 99:dbbf35b96557 2833 #define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup
Kojto 99:dbbf35b96557 2834
Kojto 99:dbbf35b96557 2835 #define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo
Kojto 99:dbbf35b96557 2836 #define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo
Kojto 99:dbbf35b96557 2837 /**
Kojto 99:dbbf35b96557 2838 * @}
Kojto 99:dbbf35b96557 2839 */
Kojto 99:dbbf35b96557 2840
Kojto 99:dbbf35b96557 2841 /** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
Kojto 99:dbbf35b96557 2842 * @{
Kojto 99:dbbf35b96557 2843 */
Kojto 99:dbbf35b96557 2844 #define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE
Kojto 99:dbbf35b96557 2845 #define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
Kojto 99:dbbf35b96557 2846
Kojto 99:dbbf35b96557 2847 #define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
Kojto 99:dbbf35b96557 2848 #define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT
Kojto 99:dbbf35b96557 2849
Kojto 119:aae6fcc7d9bb 2850 #define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
Kojto 119:aae6fcc7d9bb 2851
Kojto 99:dbbf35b96557 2852 #define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN
Kojto 99:dbbf35b96557 2853 #define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER
Kojto 99:dbbf35b96557 2854 #define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER
Kojto 99:dbbf35b96557 2855 #define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER
Kojto 99:dbbf35b96557 2856 #define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD
Kojto 99:dbbf35b96557 2857 #define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD
Kojto 99:dbbf35b96557 2858 #define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION
Kojto 99:dbbf35b96557 2859 #define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION
Kojto 99:dbbf35b96557 2860 #define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER
Kojto 99:dbbf35b96557 2861 #define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER
Kojto 99:dbbf35b96557 2862 #define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE
Kojto 99:dbbf35b96557 2863 #define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
Kojto 99:dbbf35b96557 2864 /**
Kojto 99:dbbf35b96557 2865 * @}
Kojto 99:dbbf35b96557 2866 */
Kojto 99:dbbf35b96557 2867
Kojto 99:dbbf35b96557 2868 /** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
Kojto 99:dbbf35b96557 2869 * @{
Kojto 99:dbbf35b96557 2870 */
Kojto 99:dbbf35b96557 2871
Kojto 99:dbbf35b96557 2872 #define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
Kojto 99:dbbf35b96557 2873 #define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
Kojto 99:dbbf35b96557 2874 #define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG
Kojto 99:dbbf35b96557 2875 #define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
Kojto 99:dbbf35b96557 2876 #define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
Kojto 99:dbbf35b96557 2877 #define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
Kojto 99:dbbf35b96557 2878 #define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
Kojto 99:dbbf35b96557 2879
Kojto 99:dbbf35b96557 2880 #define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE
Kojto 99:dbbf35b96557 2881 #define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE
Kojto 99:dbbf35b96557 2882 #define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE
Kojto 99:dbbf35b96557 2883 /**
Kojto 99:dbbf35b96557 2884 * @}
Kojto 99:dbbf35b96557 2885 */
Kojto 99:dbbf35b96557 2886
Kojto 99:dbbf35b96557 2887 /** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
Kojto 99:dbbf35b96557 2888 * @{
Kojto 99:dbbf35b96557 2889 */
Kojto 99:dbbf35b96557 2890 #define __HAL_LTDC_LAYER LTDC_LAYER
Kojto 99:dbbf35b96557 2891 /**
Kojto 99:dbbf35b96557 2892 * @}
Kojto 99:dbbf35b96557 2893 */
Kojto 99:dbbf35b96557 2894
Kojto 99:dbbf35b96557 2895 /** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
Kojto 99:dbbf35b96557 2896 * @{
Kojto 99:dbbf35b96557 2897 */
Kojto 99:dbbf35b96557 2898 #define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE
Kojto 99:dbbf35b96557 2899 #define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE
Kojto 99:dbbf35b96557 2900 #define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE
Kojto 99:dbbf35b96557 2901 #define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE
Kojto 99:dbbf35b96557 2902 #define SAI_STREOMODE SAI_STEREOMODE
Kojto 99:dbbf35b96557 2903 #define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY
Kojto 99:dbbf35b96557 2904 #define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL
Kojto 99:dbbf35b96557 2905 #define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL
Kojto 99:dbbf35b96557 2906 #define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL
Kojto 99:dbbf35b96557 2907 #define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL
Kojto 99:dbbf35b96557 2908 #define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL
Kojto 99:dbbf35b96557 2909 #define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE
Kojto 99:dbbf35b96557 2910
Kojto 99:dbbf35b96557 2911 /**
Kojto 99:dbbf35b96557 2912 * @}
Kojto 99:dbbf35b96557 2913 */
Kojto 99:dbbf35b96557 2914
Kojto 99:dbbf35b96557 2915
Kojto 99:dbbf35b96557 2916 /** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
Kojto 99:dbbf35b96557 2917 * @{
Kojto 99:dbbf35b96557 2918 */
Kojto 99:dbbf35b96557 2919
Kojto 99:dbbf35b96557 2920 /**
Kojto 99:dbbf35b96557 2921 * @}
Kojto 99:dbbf35b96557 2922 */
Kojto 99:dbbf35b96557 2923
Kojto 99:dbbf35b96557 2924 #ifdef __cplusplus
Kojto 99:dbbf35b96557 2925 }
Kojto 99:dbbf35b96557 2926 #endif
Kojto 99:dbbf35b96557 2927
Kojto 99:dbbf35b96557 2928 #endif /* ___STM32_HAL_LEGACY */
Kojto 99:dbbf35b96557 2929
Kojto 99:dbbf35b96557 2930 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Kojto 99:dbbf35b96557 2931