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TARGET_TY51822R3/core_sc000.h@147:a97add6d7e64, 2017-07-19 (annotated)

Committer:
Kojto
Date:
Wed Jul 19 16:46:19 2017 +0100
Revision:
147:a97add6d7e64
Parent:
145:64910690c574 
Release 147 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 113:f141b2784e32 1 /**************************************************************************//**
Kojto 113:f141b2784e32 2 * @file core_sc000.h
Kojto 113:f141b2784e32 3 * @brief CMSIS SC000 Core Peripheral Access Layer Header File
AnnaBridge 145:64910690c574 4 * @version V5.0.2
AnnaBridge 145:64910690c574 5 * @date 13. February 2017
AnnaBridge 145:64910690c574 6 ******************************************************************************/
AnnaBridge 145:64910690c574 7 /*
AnnaBridge 145:64910690c574 8 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
AnnaBridge 145:64910690c574 9 *
AnnaBridge 145:64910690c574 10 * SPDX-License-Identifier: Apache-2.0
Kojto 113:f141b2784e32 11 *
AnnaBridge 145:64910690c574 12 * Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge 145:64910690c574 13 * not use this file except in compliance with the License.
AnnaBridge 145:64910690c574 14 * You may obtain a copy of the License at
AnnaBridge 145:64910690c574 15 *
AnnaBridge 145:64910690c574 16 * www.apache.org/licenses/LICENSE-2.0
Kojto 113:f141b2784e32 17 *
AnnaBridge 145:64910690c574 18 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 145:64910690c574 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge 145:64910690c574 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 145:64910690c574 21 * See the License for the specific language governing permissions and
AnnaBridge 145:64910690c574 22 * limitations under the License.
AnnaBridge 145:64910690c574 23 */
Kojto 113:f141b2784e32 24
AnnaBridge 145:64910690c574 25 #if defined ( __ICCARM__ )
AnnaBridge 145:64910690c574 26 #pragma system_include /* treat file as system include file for MISRA check */
AnnaBridge 145:64910690c574 27 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge 145:64910690c574 28 #pragma clang system_header /* treat file as system include file */
Kojto 113:f141b2784e32 29 #endif
Kojto 113:f141b2784e32 30
Kojto 113:f141b2784e32 31 #ifndef __CORE_SC000_H_GENERIC
Kojto 113:f141b2784e32 32 #define __CORE_SC000_H_GENERIC
Kojto 113:f141b2784e32 33
AnnaBridge 145:64910690c574 34 #include <stdint.h>
AnnaBridge 145:64910690c574 35
Kojto 113:f141b2784e32 36 #ifdef __cplusplus
Kojto 113:f141b2784e32 37 extern "C" {
Kojto 113:f141b2784e32 38 #endif
Kojto 113:f141b2784e32 39
AnnaBridge 145:64910690c574 40 /**
AnnaBridge 145:64910690c574 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Kojto 113:f141b2784e32 42 CMSIS violates the following MISRA-C:2004 rules:
Kojto 113:f141b2784e32 43
Kojto 113:f141b2784e32 44 \li Required Rule 8.5, object/function definition in header file.<br>
Kojto 113:f141b2784e32 45 Function definitions in header files are used to allow 'inlining'.
Kojto 113:f141b2784e32 46
Kojto 113:f141b2784e32 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Kojto 113:f141b2784e32 48 Unions are used for effective representation of core registers.
Kojto 113:f141b2784e32 49
Kojto 113:f141b2784e32 50 \li Advisory Rule 19.7, Function-like macro defined.<br>
Kojto 113:f141b2784e32 51 Function-like macros are used to allow more efficient code.
Kojto 113:f141b2784e32 52 */
Kojto 113:f141b2784e32 53
Kojto 113:f141b2784e32 54
Kojto 113:f141b2784e32 55 /*******************************************************************************
Kojto 113:f141b2784e32 56 * CMSIS definitions
Kojto 113:f141b2784e32 57 ******************************************************************************/
AnnaBridge 145:64910690c574 58 /**
AnnaBridge 145:64910690c574 59 \ingroup SC000
Kojto 113:f141b2784e32 60 @{
Kojto 113:f141b2784e32 61 */
Kojto 113:f141b2784e32 62
Kojto 113:f141b2784e32 63 /* CMSIS SC000 definitions */
AnnaBridge 145:64910690c574 64 #define __SC000_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
AnnaBridge 145:64910690c574 65 #define __SC000_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
AnnaBridge 145:64910690c574 66 #define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
AnnaBridge 145:64910690c574 67 __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
Kojto 113:f141b2784e32 68
AnnaBridge 145:64910690c574 69 #define __CORTEX_SC (000U) /*!< Cortex secure core */
Kojto 113:f141b2784e32 70
Kojto 113:f141b2784e32 71 /** __FPU_USED indicates whether an FPU is used or not.
Kojto 113:f141b2784e32 72 This core does not support an FPU at all
Kojto 113:f141b2784e32 73 */
AnnaBridge 145:64910690c574 74 #define __FPU_USED 0U
Kojto 113:f141b2784e32 75
Kojto 113:f141b2784e32 76 #if defined ( __CC_ARM )
Kojto 113:f141b2784e32 77 #if defined __TARGET_FPU_VFP
AnnaBridge 145:64910690c574 78 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 145:64910690c574 79 #endif
AnnaBridge 145:64910690c574 80
AnnaBridge 145:64910690c574 81 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge 145:64910690c574 82 #if defined __ARM_PCS_VFP
AnnaBridge 145:64910690c574 83 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 113:f141b2784e32 84 #endif
Kojto 113:f141b2784e32 85
Kojto 113:f141b2784e32 86 #elif defined ( __GNUC__ )
Kojto 113:f141b2784e32 87 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
AnnaBridge 145:64910690c574 88 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 113:f141b2784e32 89 #endif
Kojto 113:f141b2784e32 90
Kojto 113:f141b2784e32 91 #elif defined ( __ICCARM__ )
Kojto 113:f141b2784e32 92 #if defined __ARMVFP__
AnnaBridge 145:64910690c574 93 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 113:f141b2784e32 94 #endif
Kojto 113:f141b2784e32 95
AnnaBridge 145:64910690c574 96 #elif defined ( __TI_ARM__ )
AnnaBridge 145:64910690c574 97 #if defined __TI_VFP_SUPPORT__
AnnaBridge 145:64910690c574 98 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 113:f141b2784e32 99 #endif
Kojto 113:f141b2784e32 100
Kojto 113:f141b2784e32 101 #elif defined ( __TASKING__ )
Kojto 113:f141b2784e32 102 #if defined __FPU_VFP__
Kojto 113:f141b2784e32 103 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 113:f141b2784e32 104 #endif
Kojto 113:f141b2784e32 105
AnnaBridge 145:64910690c574 106 #elif defined ( __CSMC__ )
AnnaBridge 145:64910690c574 107 #if ( __CSMC__ & 0x400U)
Kojto 113:f141b2784e32 108 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 113:f141b2784e32 109 #endif
AnnaBridge 145:64910690c574 110
Kojto 113:f141b2784e32 111 #endif
Kojto 113:f141b2784e32 112
AnnaBridge 145:64910690c574 113 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
AnnaBridge 145:64910690c574 114
Kojto 113:f141b2784e32 115
Kojto 113:f141b2784e32 116 #ifdef __cplusplus
Kojto 113:f141b2784e32 117 }
Kojto 113:f141b2784e32 118 #endif
Kojto 113:f141b2784e32 119
Kojto 113:f141b2784e32 120 #endif /* __CORE_SC000_H_GENERIC */
Kojto 113:f141b2784e32 121
Kojto 113:f141b2784e32 122 #ifndef __CMSIS_GENERIC
Kojto 113:f141b2784e32 123
Kojto 113:f141b2784e32 124 #ifndef __CORE_SC000_H_DEPENDANT
Kojto 113:f141b2784e32 125 #define __CORE_SC000_H_DEPENDANT
Kojto 113:f141b2784e32 126
Kojto 113:f141b2784e32 127 #ifdef __cplusplus
Kojto 113:f141b2784e32 128 extern "C" {
Kojto 113:f141b2784e32 129 #endif
Kojto 113:f141b2784e32 130
Kojto 113:f141b2784e32 131 /* check device defines and use defaults */
Kojto 113:f141b2784e32 132 #if defined __CHECK_DEVICE_DEFINES
Kojto 113:f141b2784e32 133 #ifndef __SC000_REV
AnnaBridge 145:64910690c574 134 #define __SC000_REV 0x0000U
Kojto 113:f141b2784e32 135 #warning "__SC000_REV not defined in device header file; using default!"
Kojto 113:f141b2784e32 136 #endif
Kojto 113:f141b2784e32 137
Kojto 113:f141b2784e32 138 #ifndef __MPU_PRESENT
AnnaBridge 145:64910690c574 139 #define __MPU_PRESENT 0U
Kojto 113:f141b2784e32 140 #warning "__MPU_PRESENT not defined in device header file; using default!"
Kojto 113:f141b2784e32 141 #endif
Kojto 113:f141b2784e32 142
Kojto 113:f141b2784e32 143 #ifndef __NVIC_PRIO_BITS
AnnaBridge 145:64910690c574 144 #define __NVIC_PRIO_BITS 2U
Kojto 113:f141b2784e32 145 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Kojto 113:f141b2784e32 146 #endif
Kojto 113:f141b2784e32 147
Kojto 113:f141b2784e32 148 #ifndef __Vendor_SysTickConfig
AnnaBridge 145:64910690c574 149 #define __Vendor_SysTickConfig 0U
Kojto 113:f141b2784e32 150 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Kojto 113:f141b2784e32 151 #endif
Kojto 113:f141b2784e32 152 #endif
Kojto 113:f141b2784e32 153
Kojto 113:f141b2784e32 154 /* IO definitions (access restrictions to peripheral registers) */
Kojto 113:f141b2784e32 155 /**
Kojto 113:f141b2784e32 156 \defgroup CMSIS_glob_defs CMSIS Global Defines
Kojto 113:f141b2784e32 157
Kojto 113:f141b2784e32 158 <strong>IO Type Qualifiers</strong> are used
Kojto 113:f141b2784e32 159 \li to specify the access to peripheral variables.
Kojto 113:f141b2784e32 160 \li for automatic generation of peripheral register debug information.
Kojto 113:f141b2784e32 161 */
Kojto 113:f141b2784e32 162 #ifdef __cplusplus
AnnaBridge 145:64910690c574 163 #define __I volatile /*!< Defines 'read only' permissions */
Kojto 113:f141b2784e32 164 #else
AnnaBridge 145:64910690c574 165 #define __I volatile const /*!< Defines 'read only' permissions */
Kojto 113:f141b2784e32 166 #endif
AnnaBridge 145:64910690c574 167 #define __O volatile /*!< Defines 'write only' permissions */
AnnaBridge 145:64910690c574 168 #define __IO volatile /*!< Defines 'read / write' permissions */
AnnaBridge 145:64910690c574 169
AnnaBridge 145:64910690c574 170 /* following defines should be used for structure members */
AnnaBridge 145:64910690c574 171 #define __IM volatile const /*! Defines 'read only' structure member permissions */
AnnaBridge 145:64910690c574 172 #define __OM volatile /*! Defines 'write only' structure member permissions */
AnnaBridge 145:64910690c574 173 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
Kojto 113:f141b2784e32 174
Kojto 113:f141b2784e32 175 /*@} end of group SC000 */
Kojto 113:f141b2784e32 176
Kojto 113:f141b2784e32 177
Kojto 113:f141b2784e32 178
Kojto 113:f141b2784e32 179 /*******************************************************************************
Kojto 113:f141b2784e32 180 * Register Abstraction
Kojto 113:f141b2784e32 181 Core Register contain:
Kojto 113:f141b2784e32 182 - Core Register
Kojto 113:f141b2784e32 183 - Core NVIC Register
Kojto 113:f141b2784e32 184 - Core SCB Register
Kojto 113:f141b2784e32 185 - Core SysTick Register
Kojto 113:f141b2784e32 186 - Core MPU Register
Kojto 113:f141b2784e32 187 ******************************************************************************/
AnnaBridge 145:64910690c574 188 /**
AnnaBridge 145:64910690c574 189 \defgroup CMSIS_core_register Defines and Type Definitions
AnnaBridge 145:64910690c574 190 \brief Type definitions and defines for Cortex-M processor based devices.
Kojto 113:f141b2784e32 191 */
Kojto 113:f141b2784e32 192
AnnaBridge 145:64910690c574 193 /**
AnnaBridge 145:64910690c574 194 \ingroup CMSIS_core_register
AnnaBridge 145:64910690c574 195 \defgroup CMSIS_CORE Status and Control Registers
AnnaBridge 145:64910690c574 196 \brief Core Register type definitions.
Kojto 113:f141b2784e32 197 @{
Kojto 113:f141b2784e32 198 */
Kojto 113:f141b2784e32 199
AnnaBridge 145:64910690c574 200 /**
AnnaBridge 145:64910690c574 201 \brief Union type to access the Application Program Status Register (APSR).
Kojto 113:f141b2784e32 202 */
Kojto 113:f141b2784e32 203 typedef union
Kojto 113:f141b2784e32 204 {
Kojto 113:f141b2784e32 205 struct
Kojto 113:f141b2784e32 206 {
AnnaBridge 145:64910690c574 207 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
AnnaBridge 145:64910690c574 208 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 145:64910690c574 209 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 145:64910690c574 210 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 145:64910690c574 211 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 145:64910690c574 212 } b; /*!< Structure used for bit access */
AnnaBridge 145:64910690c574 213 uint32_t w; /*!< Type used for word access */
Kojto 113:f141b2784e32 214 } APSR_Type;
Kojto 113:f141b2784e32 215
Kojto 113:f141b2784e32 216 /* APSR Register Definitions */
AnnaBridge 145:64910690c574 217 #define APSR_N_Pos 31U /*!< APSR: N Position */
Kojto 113:f141b2784e32 218 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
Kojto 113:f141b2784e32 219
AnnaBridge 145:64910690c574 220 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
Kojto 113:f141b2784e32 221 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
Kojto 113:f141b2784e32 222
AnnaBridge 145:64910690c574 223 #define APSR_C_Pos 29U /*!< APSR: C Position */
Kojto 113:f141b2784e32 224 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
Kojto 113:f141b2784e32 225
AnnaBridge 145:64910690c574 226 #define APSR_V_Pos 28U /*!< APSR: V Position */
Kojto 113:f141b2784e32 227 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
Kojto 113:f141b2784e32 228
Kojto 113:f141b2784e32 229
AnnaBridge 145:64910690c574 230 /**
AnnaBridge 145:64910690c574 231 \brief Union type to access the Interrupt Program Status Register (IPSR).
Kojto 113:f141b2784e32 232 */
Kojto 113:f141b2784e32 233 typedef union
Kojto 113:f141b2784e32 234 {
Kojto 113:f141b2784e32 235 struct
Kojto 113:f141b2784e32 236 {
AnnaBridge 145:64910690c574 237 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 145:64910690c574 238 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
AnnaBridge 145:64910690c574 239 } b; /*!< Structure used for bit access */
AnnaBridge 145:64910690c574 240 uint32_t w; /*!< Type used for word access */
Kojto 113:f141b2784e32 241 } IPSR_Type;
Kojto 113:f141b2784e32 242
Kojto 113:f141b2784e32 243 /* IPSR Register Definitions */
AnnaBridge 145:64910690c574 244 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
Kojto 113:f141b2784e32 245 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
Kojto 113:f141b2784e32 246
Kojto 113:f141b2784e32 247
AnnaBridge 145:64910690c574 248 /**
AnnaBridge 145:64910690c574 249 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Kojto 113:f141b2784e32 250 */
Kojto 113:f141b2784e32 251 typedef union
Kojto 113:f141b2784e32 252 {
Kojto 113:f141b2784e32 253 struct
Kojto 113:f141b2784e32 254 {
AnnaBridge 145:64910690c574 255 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 145:64910690c574 256 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
AnnaBridge 145:64910690c574 257 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
AnnaBridge 145:64910690c574 258 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
AnnaBridge 145:64910690c574 259 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 145:64910690c574 260 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 145:64910690c574 261 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 145:64910690c574 262 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 145:64910690c574 263 } b; /*!< Structure used for bit access */
AnnaBridge 145:64910690c574 264 uint32_t w; /*!< Type used for word access */
Kojto 113:f141b2784e32 265 } xPSR_Type;
Kojto 113:f141b2784e32 266
Kojto 113:f141b2784e32 267 /* xPSR Register Definitions */
AnnaBridge 145:64910690c574 268 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
Kojto 113:f141b2784e32 269 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
Kojto 113:f141b2784e32 270
AnnaBridge 145:64910690c574 271 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
Kojto 113:f141b2784e32 272 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
Kojto 113:f141b2784e32 273
AnnaBridge 145:64910690c574 274 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
Kojto 113:f141b2784e32 275 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
Kojto 113:f141b2784e32 276
AnnaBridge 145:64910690c574 277 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
Kojto 113:f141b2784e32 278 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
Kojto 113:f141b2784e32 279
AnnaBridge 145:64910690c574 280 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
Kojto 113:f141b2784e32 281 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
Kojto 113:f141b2784e32 282
AnnaBridge 145:64910690c574 283 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
Kojto 113:f141b2784e32 284 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
Kojto 113:f141b2784e32 285
Kojto 113:f141b2784e32 286
AnnaBridge 145:64910690c574 287 /**
AnnaBridge 145:64910690c574 288 \brief Union type to access the Control Registers (CONTROL).
Kojto 113:f141b2784e32 289 */
Kojto 113:f141b2784e32 290 typedef union
Kojto 113:f141b2784e32 291 {
Kojto 113:f141b2784e32 292 struct
Kojto 113:f141b2784e32 293 {
AnnaBridge 145:64910690c574 294 uint32_t _reserved0:1; /*!< bit: 0 Reserved */
AnnaBridge 145:64910690c574 295 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
AnnaBridge 145:64910690c574 296 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
AnnaBridge 145:64910690c574 297 } b; /*!< Structure used for bit access */
AnnaBridge 145:64910690c574 298 uint32_t w; /*!< Type used for word access */
Kojto 113:f141b2784e32 299 } CONTROL_Type;
Kojto 113:f141b2784e32 300
Kojto 113:f141b2784e32 301 /* CONTROL Register Definitions */
AnnaBridge 145:64910690c574 302 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
Kojto 113:f141b2784e32 303 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
Kojto 113:f141b2784e32 304
Kojto 113:f141b2784e32 305 /*@} end of group CMSIS_CORE */
Kojto 113:f141b2784e32 306
Kojto 113:f141b2784e32 307
AnnaBridge 145:64910690c574 308 /**
AnnaBridge 145:64910690c574 309 \ingroup CMSIS_core_register
AnnaBridge 145:64910690c574 310 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
AnnaBridge 145:64910690c574 311 \brief Type definitions for the NVIC Registers
Kojto 113:f141b2784e32 312 @{
Kojto 113:f141b2784e32 313 */
Kojto 113:f141b2784e32 314
AnnaBridge 145:64910690c574 315 /**
AnnaBridge 145:64910690c574 316 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Kojto 113:f141b2784e32 317 */
Kojto 113:f141b2784e32 318 typedef struct
Kojto 113:f141b2784e32 319 {
AnnaBridge 145:64910690c574 320 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
AnnaBridge 145:64910690c574 321 uint32_t RESERVED0[31U];
AnnaBridge 145:64910690c574 322 __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
AnnaBridge 145:64910690c574 323 uint32_t RSERVED1[31U];
AnnaBridge 145:64910690c574 324 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
AnnaBridge 145:64910690c574 325 uint32_t RESERVED2[31U];
AnnaBridge 145:64910690c574 326 __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
AnnaBridge 145:64910690c574 327 uint32_t RESERVED3[31U];
AnnaBridge 145:64910690c574 328 uint32_t RESERVED4[64U];
AnnaBridge 145:64910690c574 329 __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
Kojto 113:f141b2784e32 330 } NVIC_Type;
Kojto 113:f141b2784e32 331
Kojto 113:f141b2784e32 332 /*@} end of group CMSIS_NVIC */
Kojto 113:f141b2784e32 333
Kojto 113:f141b2784e32 334
AnnaBridge 145:64910690c574 335 /**
AnnaBridge 145:64910690c574 336 \ingroup CMSIS_core_register
AnnaBridge 145:64910690c574 337 \defgroup CMSIS_SCB System Control Block (SCB)
AnnaBridge 145:64910690c574 338 \brief Type definitions for the System Control Block Registers
Kojto 113:f141b2784e32 339 @{
Kojto 113:f141b2784e32 340 */
Kojto 113:f141b2784e32 341
AnnaBridge 145:64910690c574 342 /**
AnnaBridge 145:64910690c574 343 \brief Structure type to access the System Control Block (SCB).
Kojto 113:f141b2784e32 344 */
Kojto 113:f141b2784e32 345 typedef struct
Kojto 113:f141b2784e32 346 {
AnnaBridge 145:64910690c574 347 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
AnnaBridge 145:64910690c574 348 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
AnnaBridge 145:64910690c574 349 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
AnnaBridge 145:64910690c574 350 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
AnnaBridge 145:64910690c574 351 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
AnnaBridge 145:64910690c574 352 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
AnnaBridge 145:64910690c574 353 uint32_t RESERVED0[1U];
AnnaBridge 145:64910690c574 354 __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
AnnaBridge 145:64910690c574 355 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
AnnaBridge 145:64910690c574 356 uint32_t RESERVED1[154U];
AnnaBridge 145:64910690c574 357 __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
Kojto 113:f141b2784e32 358 } SCB_Type;
Kojto 113:f141b2784e32 359
Kojto 113:f141b2784e32 360 /* SCB CPUID Register Definitions */
AnnaBridge 145:64910690c574 361 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
Kojto 113:f141b2784e32 362 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
Kojto 113:f141b2784e32 363
AnnaBridge 145:64910690c574 364 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
Kojto 113:f141b2784e32 365 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
Kojto 113:f141b2784e32 366
AnnaBridge 145:64910690c574 367 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
Kojto 113:f141b2784e32 368 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
Kojto 113:f141b2784e32 369
AnnaBridge 145:64910690c574 370 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
Kojto 113:f141b2784e32 371 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
Kojto 113:f141b2784e32 372
AnnaBridge 145:64910690c574 373 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
Kojto 113:f141b2784e32 374 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
Kojto 113:f141b2784e32 375
Kojto 113:f141b2784e32 376 /* SCB Interrupt Control State Register Definitions */
AnnaBridge 145:64910690c574 377 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
Kojto 113:f141b2784e32 378 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
Kojto 113:f141b2784e32 379
AnnaBridge 145:64910690c574 380 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
Kojto 113:f141b2784e32 381 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
Kojto 113:f141b2784e32 382
AnnaBridge 145:64910690c574 383 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
Kojto 113:f141b2784e32 384 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
Kojto 113:f141b2784e32 385
AnnaBridge 145:64910690c574 386 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
Kojto 113:f141b2784e32 387 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
Kojto 113:f141b2784e32 388
AnnaBridge 145:64910690c574 389 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
Kojto 113:f141b2784e32 390 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
Kojto 113:f141b2784e32 391
AnnaBridge 145:64910690c574 392 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
Kojto 113:f141b2784e32 393 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
Kojto 113:f141b2784e32 394
AnnaBridge 145:64910690c574 395 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
Kojto 113:f141b2784e32 396 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
Kojto 113:f141b2784e32 397
AnnaBridge 145:64910690c574 398 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
Kojto 113:f141b2784e32 399 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
Kojto 113:f141b2784e32 400
AnnaBridge 145:64910690c574 401 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
Kojto 113:f141b2784e32 402 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
Kojto 113:f141b2784e32 403
Kojto 113:f141b2784e32 404 /* SCB Interrupt Control State Register Definitions */
AnnaBridge 145:64910690c574 405 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
Kojto 113:f141b2784e32 406 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
Kojto 113:f141b2784e32 407
Kojto 113:f141b2784e32 408 /* SCB Application Interrupt and Reset Control Register Definitions */
AnnaBridge 145:64910690c574 409 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
Kojto 113:f141b2784e32 410 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
Kojto 113:f141b2784e32 411
AnnaBridge 145:64910690c574 412 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
Kojto 113:f141b2784e32 413 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
Kojto 113:f141b2784e32 414
AnnaBridge 145:64910690c574 415 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
Kojto 113:f141b2784e32 416 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
Kojto 113:f141b2784e32 417
AnnaBridge 145:64910690c574 418 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
Kojto 113:f141b2784e32 419 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
Kojto 113:f141b2784e32 420
AnnaBridge 145:64910690c574 421 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
Kojto 113:f141b2784e32 422 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
Kojto 113:f141b2784e32 423
Kojto 113:f141b2784e32 424 /* SCB System Control Register Definitions */
AnnaBridge 145:64910690c574 425 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
Kojto 113:f141b2784e32 426 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
Kojto 113:f141b2784e32 427
AnnaBridge 145:64910690c574 428 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
Kojto 113:f141b2784e32 429 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
Kojto 113:f141b2784e32 430
AnnaBridge 145:64910690c574 431 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
Kojto 113:f141b2784e32 432 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
Kojto 113:f141b2784e32 433
Kojto 113:f141b2784e32 434 /* SCB Configuration Control Register Definitions */
AnnaBridge 145:64910690c574 435 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
Kojto 113:f141b2784e32 436 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
Kojto 113:f141b2784e32 437
AnnaBridge 145:64910690c574 438 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
Kojto 113:f141b2784e32 439 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
Kojto 113:f141b2784e32 440
Kojto 113:f141b2784e32 441 /* SCB System Handler Control and State Register Definitions */
AnnaBridge 145:64910690c574 442 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
Kojto 113:f141b2784e32 443 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
Kojto 113:f141b2784e32 444
Kojto 113:f141b2784e32 445 /*@} end of group CMSIS_SCB */
Kojto 113:f141b2784e32 446
Kojto 113:f141b2784e32 447
AnnaBridge 145:64910690c574 448 /**
AnnaBridge 145:64910690c574 449 \ingroup CMSIS_core_register
AnnaBridge 145:64910690c574 450 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
AnnaBridge 145:64910690c574 451 \brief Type definitions for the System Control and ID Register not in the SCB
Kojto 113:f141b2784e32 452 @{
Kojto 113:f141b2784e32 453 */
Kojto 113:f141b2784e32 454
AnnaBridge 145:64910690c574 455 /**
AnnaBridge 145:64910690c574 456 \brief Structure type to access the System Control and ID Register not in the SCB.
Kojto 113:f141b2784e32 457 */
Kojto 113:f141b2784e32 458 typedef struct
Kojto 113:f141b2784e32 459 {
AnnaBridge 145:64910690c574 460 uint32_t RESERVED0[2U];
AnnaBridge 145:64910690c574 461 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
Kojto 113:f141b2784e32 462 } SCnSCB_Type;
Kojto 113:f141b2784e32 463
Kojto 113:f141b2784e32 464 /* Auxiliary Control Register Definitions */
AnnaBridge 145:64910690c574 465 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
Kojto 113:f141b2784e32 466 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
Kojto 113:f141b2784e32 467
Kojto 113:f141b2784e32 468 /*@} end of group CMSIS_SCnotSCB */
Kojto 113:f141b2784e32 469
Kojto 113:f141b2784e32 470
AnnaBridge 145:64910690c574 471 /**
AnnaBridge 145:64910690c574 472 \ingroup CMSIS_core_register
AnnaBridge 145:64910690c574 473 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
AnnaBridge 145:64910690c574 474 \brief Type definitions for the System Timer Registers.
Kojto 113:f141b2784e32 475 @{
Kojto 113:f141b2784e32 476 */
Kojto 113:f141b2784e32 477
AnnaBridge 145:64910690c574 478 /**
AnnaBridge 145:64910690c574 479 \brief Structure type to access the System Timer (SysTick).
Kojto 113:f141b2784e32 480 */
Kojto 113:f141b2784e32 481 typedef struct
Kojto 113:f141b2784e32 482 {
AnnaBridge 145:64910690c574 483 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
AnnaBridge 145:64910690c574 484 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
AnnaBridge 145:64910690c574 485 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
AnnaBridge 145:64910690c574 486 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
Kojto 113:f141b2784e32 487 } SysTick_Type;
Kojto 113:f141b2784e32 488
Kojto 113:f141b2784e32 489 /* SysTick Control / Status Register Definitions */
AnnaBridge 145:64910690c574 490 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
Kojto 113:f141b2784e32 491 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
Kojto 113:f141b2784e32 492
AnnaBridge 145:64910690c574 493 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
Kojto 113:f141b2784e32 494 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
Kojto 113:f141b2784e32 495
AnnaBridge 145:64910690c574 496 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
Kojto 113:f141b2784e32 497 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
Kojto 113:f141b2784e32 498
AnnaBridge 145:64910690c574 499 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
Kojto 113:f141b2784e32 500 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
Kojto 113:f141b2784e32 501
Kojto 113:f141b2784e32 502 /* SysTick Reload Register Definitions */
AnnaBridge 145:64910690c574 503 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
Kojto 113:f141b2784e32 504 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
Kojto 113:f141b2784e32 505
Kojto 113:f141b2784e32 506 /* SysTick Current Register Definitions */
AnnaBridge 145:64910690c574 507 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
Kojto 113:f141b2784e32 508 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
Kojto 113:f141b2784e32 509
Kojto 113:f141b2784e32 510 /* SysTick Calibration Register Definitions */
AnnaBridge 145:64910690c574 511 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
Kojto 113:f141b2784e32 512 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
Kojto 113:f141b2784e32 513
AnnaBridge 145:64910690c574 514 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
Kojto 113:f141b2784e32 515 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
Kojto 113:f141b2784e32 516
AnnaBridge 145:64910690c574 517 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
Kojto 113:f141b2784e32 518 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
Kojto 113:f141b2784e32 519
Kojto 113:f141b2784e32 520 /*@} end of group CMSIS_SysTick */
Kojto 113:f141b2784e32 521
AnnaBridge 145:64910690c574 522 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge 145:64910690c574 523 /**
AnnaBridge 145:64910690c574 524 \ingroup CMSIS_core_register
AnnaBridge 145:64910690c574 525 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
AnnaBridge 145:64910690c574 526 \brief Type definitions for the Memory Protection Unit (MPU)
Kojto 113:f141b2784e32 527 @{
Kojto 113:f141b2784e32 528 */
Kojto 113:f141b2784e32 529
AnnaBridge 145:64910690c574 530 /**
AnnaBridge 145:64910690c574 531 \brief Structure type to access the Memory Protection Unit (MPU).
Kojto 113:f141b2784e32 532 */
Kojto 113:f141b2784e32 533 typedef struct
Kojto 113:f141b2784e32 534 {
AnnaBridge 145:64910690c574 535 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
AnnaBridge 145:64910690c574 536 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
AnnaBridge 145:64910690c574 537 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
AnnaBridge 145:64910690c574 538 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
AnnaBridge 145:64910690c574 539 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
Kojto 113:f141b2784e32 540 } MPU_Type;
Kojto 113:f141b2784e32 541
AnnaBridge 145:64910690c574 542 /* MPU Type Register Definitions */
AnnaBridge 145:64910690c574 543 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
Kojto 113:f141b2784e32 544 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
Kojto 113:f141b2784e32 545
AnnaBridge 145:64910690c574 546 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
Kojto 113:f141b2784e32 547 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
Kojto 113:f141b2784e32 548
AnnaBridge 145:64910690c574 549 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
Kojto 113:f141b2784e32 550 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
Kojto 113:f141b2784e32 551
AnnaBridge 145:64910690c574 552 /* MPU Control Register Definitions */
AnnaBridge 145:64910690c574 553 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
Kojto 113:f141b2784e32 554 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
Kojto 113:f141b2784e32 555
AnnaBridge 145:64910690c574 556 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
Kojto 113:f141b2784e32 557 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
Kojto 113:f141b2784e32 558
AnnaBridge 145:64910690c574 559 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
Kojto 113:f141b2784e32 560 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
Kojto 113:f141b2784e32 561
AnnaBridge 145:64910690c574 562 /* MPU Region Number Register Definitions */
AnnaBridge 145:64910690c574 563 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
Kojto 113:f141b2784e32 564 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
Kojto 113:f141b2784e32 565
AnnaBridge 145:64910690c574 566 /* MPU Region Base Address Register Definitions */
AnnaBridge 145:64910690c574 567 #define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
Kojto 113:f141b2784e32 568 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
Kojto 113:f141b2784e32 569
AnnaBridge 145:64910690c574 570 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
Kojto 113:f141b2784e32 571 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
Kojto 113:f141b2784e32 572
AnnaBridge 145:64910690c574 573 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
Kojto 113:f141b2784e32 574 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
Kojto 113:f141b2784e32 575
AnnaBridge 145:64910690c574 576 /* MPU Region Attribute and Size Register Definitions */
AnnaBridge 145:64910690c574 577 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
Kojto 113:f141b2784e32 578 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
Kojto 113:f141b2784e32 579
AnnaBridge 145:64910690c574 580 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
Kojto 113:f141b2784e32 581 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
Kojto 113:f141b2784e32 582
AnnaBridge 145:64910690c574 583 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
Kojto 113:f141b2784e32 584 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
Kojto 113:f141b2784e32 585
AnnaBridge 145:64910690c574 586 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
Kojto 113:f141b2784e32 587 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
Kojto 113:f141b2784e32 588
AnnaBridge 145:64910690c574 589 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
Kojto 113:f141b2784e32 590 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
Kojto 113:f141b2784e32 591
AnnaBridge 145:64910690c574 592 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
Kojto 113:f141b2784e32 593 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
Kojto 113:f141b2784e32 594
AnnaBridge 145:64910690c574 595 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
Kojto 113:f141b2784e32 596 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
Kojto 113:f141b2784e32 597
AnnaBridge 145:64910690c574 598 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
Kojto 113:f141b2784e32 599 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
Kojto 113:f141b2784e32 600
AnnaBridge 145:64910690c574 601 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
Kojto 113:f141b2784e32 602 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
Kojto 113:f141b2784e32 603
AnnaBridge 145:64910690c574 604 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
Kojto 113:f141b2784e32 605 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
Kojto 113:f141b2784e32 606
Kojto 113:f141b2784e32 607 /*@} end of group CMSIS_MPU */
Kojto 113:f141b2784e32 608 #endif
Kojto 113:f141b2784e32 609
Kojto 113:f141b2784e32 610
AnnaBridge 145:64910690c574 611 /**
AnnaBridge 145:64910690c574 612 \ingroup CMSIS_core_register
AnnaBridge 145:64910690c574 613 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
AnnaBridge 145:64910690c574 614 \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
AnnaBridge 145:64910690c574 615 Therefore they are not covered by the SC000 header file.
Kojto 113:f141b2784e32 616 @{
Kojto 113:f141b2784e32 617 */
Kojto 113:f141b2784e32 618 /*@} end of group CMSIS_CoreDebug */
Kojto 113:f141b2784e32 619
Kojto 113:f141b2784e32 620
AnnaBridge 145:64910690c574 621 /**
AnnaBridge 145:64910690c574 622 \ingroup CMSIS_core_register
AnnaBridge 145:64910690c574 623 \defgroup CMSIS_core_bitfield Core register bit field macros
AnnaBridge 145:64910690c574 624 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
Kojto 113:f141b2784e32 625 @{
Kojto 113:f141b2784e32 626 */
Kojto 113:f141b2784e32 627
AnnaBridge 145:64910690c574 628 /**
AnnaBridge 145:64910690c574 629 \brief Mask and shift a bit field value for use in a register bit range.
AnnaBridge 145:64910690c574 630 \param[in] field Name of the register bit field.
AnnaBridge 145:64910690c574 631 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
AnnaBridge 145:64910690c574 632 \return Masked and shifted value.
AnnaBridge 145:64910690c574 633 */
AnnaBridge 145:64910690c574 634 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
AnnaBridge 145:64910690c574 635
AnnaBridge 145:64910690c574 636 /**
AnnaBridge 145:64910690c574 637 \brief Mask and shift a register value to extract a bit filed value.
AnnaBridge 145:64910690c574 638 \param[in] field Name of the register bit field.
AnnaBridge 145:64910690c574 639 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
AnnaBridge 145:64910690c574 640 \return Masked and shifted bit field value.
AnnaBridge 145:64910690c574 641 */
AnnaBridge 145:64910690c574 642 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
AnnaBridge 145:64910690c574 643
AnnaBridge 145:64910690c574 644 /*@} end of group CMSIS_core_bitfield */
AnnaBridge 145:64910690c574 645
AnnaBridge 145:64910690c574 646
AnnaBridge 145:64910690c574 647 /**
AnnaBridge 145:64910690c574 648 \ingroup CMSIS_core_register
AnnaBridge 145:64910690c574 649 \defgroup CMSIS_core_base Core Definitions
AnnaBridge 145:64910690c574 650 \brief Definitions for base addresses, unions, and structures.
AnnaBridge 145:64910690c574 651 @{
AnnaBridge 145:64910690c574 652 */
AnnaBridge 145:64910690c574 653
AnnaBridge 145:64910690c574 654 /* Memory mapping of Core Hardware */
Kojto 113:f141b2784e32 655 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
AnnaBridge 145:64910690c574 656 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
AnnaBridge 145:64910690c574 657 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
Kojto 113:f141b2784e32 658 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
Kojto 113:f141b2784e32 659
Kojto 113:f141b2784e32 660 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
AnnaBridge 145:64910690c574 661 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
AnnaBridge 145:64910690c574 662 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
AnnaBridge 145:64910690c574 663 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
Kojto 113:f141b2784e32 664
AnnaBridge 145:64910690c574 665 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge 145:64910690c574 666 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
AnnaBridge 145:64910690c574 667 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
Kojto 113:f141b2784e32 668 #endif
Kojto 113:f141b2784e32 669
Kojto 113:f141b2784e32 670 /*@} */
Kojto 113:f141b2784e32 671
Kojto 113:f141b2784e32 672
Kojto 113:f141b2784e32 673
Kojto 113:f141b2784e32 674 /*******************************************************************************
Kojto 113:f141b2784e32 675 * Hardware Abstraction Layer
Kojto 113:f141b2784e32 676 Core Function Interface contains:
Kojto 113:f141b2784e32 677 - Core NVIC Functions
Kojto 113:f141b2784e32 678 - Core SysTick Functions
Kojto 113:f141b2784e32 679 - Core Register Access Functions
Kojto 113:f141b2784e32 680 ******************************************************************************/
AnnaBridge 145:64910690c574 681 /**
AnnaBridge 145:64910690c574 682 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Kojto 113:f141b2784e32 683 */
Kojto 113:f141b2784e32 684
Kojto 113:f141b2784e32 685
Kojto 113:f141b2784e32 686
Kojto 113:f141b2784e32 687 /* ########################## NVIC functions #################################### */
AnnaBridge 145:64910690c574 688 /**
AnnaBridge 145:64910690c574 689 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 145:64910690c574 690 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
AnnaBridge 145:64910690c574 691 \brief Functions that manage interrupts and exceptions via the NVIC.
AnnaBridge 145:64910690c574 692 @{
Kojto 113:f141b2784e32 693 */
Kojto 113:f141b2784e32 694
AnnaBridge 145:64910690c574 695 #ifdef CMSIS_NVIC_VIRTUAL
AnnaBridge 145:64910690c574 696 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge 145:64910690c574 697 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
AnnaBridge 145:64910690c574 698 #endif
AnnaBridge 145:64910690c574 699 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge 145:64910690c574 700 #else
AnnaBridge 145:64910690c574 701 /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */
AnnaBridge 145:64910690c574 702 /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */
AnnaBridge 145:64910690c574 703 #define NVIC_EnableIRQ __NVIC_EnableIRQ
AnnaBridge 145:64910690c574 704 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
AnnaBridge 145:64910690c574 705 #define NVIC_DisableIRQ __NVIC_DisableIRQ
AnnaBridge 145:64910690c574 706 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
AnnaBridge 145:64910690c574 707 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
AnnaBridge 145:64910690c574 708 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
AnnaBridge 145:64910690c574 709 /*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */
AnnaBridge 145:64910690c574 710 #define NVIC_SetPriority __NVIC_SetPriority
AnnaBridge 145:64910690c574 711 #define NVIC_GetPriority __NVIC_GetPriority
AnnaBridge 145:64910690c574 712 #define NVIC_SystemReset __NVIC_SystemReset
AnnaBridge 145:64910690c574 713 #endif /* CMSIS_NVIC_VIRTUAL */
AnnaBridge 145:64910690c574 714
AnnaBridge 145:64910690c574 715 #ifdef CMSIS_VECTAB_VIRTUAL
AnnaBridge 145:64910690c574 716 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge 145:64910690c574 717 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
AnnaBridge 145:64910690c574 718 #endif
AnnaBridge 145:64910690c574 719 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge 145:64910690c574 720 #else
AnnaBridge 145:64910690c574 721 #define NVIC_SetVector __NVIC_SetVector
AnnaBridge 145:64910690c574 722 #define NVIC_GetVector __NVIC_GetVector
AnnaBridge 145:64910690c574 723 #endif /* (CMSIS_VECTAB_VIRTUAL) */
AnnaBridge 145:64910690c574 724
AnnaBridge 145:64910690c574 725 #define NVIC_USER_IRQ_OFFSET 16
AnnaBridge 145:64910690c574 726
AnnaBridge 145:64910690c574 727
Kojto 113:f141b2784e32 728 /* Interrupt Priorities are WORD accessible only under ARMv6M */
Kojto 113:f141b2784e32 729 /* The following MACROS handle generation of the register offset and byte masks */
Kojto 113:f141b2784e32 730 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
Kojto 113:f141b2784e32 731 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
Kojto 113:f141b2784e32 732 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
Kojto 113:f141b2784e32 733
Kojto 113:f141b2784e32 734
AnnaBridge 145:64910690c574 735 /**
AnnaBridge 145:64910690c574 736 \brief Enable Interrupt
AnnaBridge 145:64910690c574 737 \details Enables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge 145:64910690c574 738 \param [in] IRQn Device specific interrupt number.
AnnaBridge 145:64910690c574 739 \note IRQn must not be negative.
Kojto 113:f141b2784e32 740 */
AnnaBridge 145:64910690c574 741 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
Kojto 113:f141b2784e32 742 {
AnnaBridge 145:64910690c574 743 if ((int32_t)(IRQn) >= 0)
AnnaBridge 145:64910690c574 744 {
AnnaBridge 145:64910690c574 745 NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 145:64910690c574 746 }
Kojto 113:f141b2784e32 747 }
Kojto 113:f141b2784e32 748
Kojto 113:f141b2784e32 749
AnnaBridge 145:64910690c574 750 /**
AnnaBridge 145:64910690c574 751 \brief Get Interrupt Enable status
AnnaBridge 145:64910690c574 752 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
AnnaBridge 145:64910690c574 753 \param [in] IRQn Device specific interrupt number.
AnnaBridge 145:64910690c574 754 \return 0 Interrupt is not enabled.
AnnaBridge 145:64910690c574 755 \return 1 Interrupt is enabled.
AnnaBridge 145:64910690c574 756 \note IRQn must not be negative.
Kojto 113:f141b2784e32 757 */
AnnaBridge 145:64910690c574 758 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
Kojto 113:f141b2784e32 759 {
AnnaBridge 145:64910690c574 760 if ((int32_t)(IRQn) >= 0)
AnnaBridge 145:64910690c574 761 {
AnnaBridge 145:64910690c574 762 return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 145:64910690c574 763 }
AnnaBridge 145:64910690c574 764 else
AnnaBridge 145:64910690c574 765 {
AnnaBridge 145:64910690c574 766 return(0U);
AnnaBridge 145:64910690c574 767 }
Kojto 113:f141b2784e32 768 }
Kojto 113:f141b2784e32 769
Kojto 113:f141b2784e32 770
AnnaBridge 145:64910690c574 771 /**
AnnaBridge 145:64910690c574 772 \brief Disable Interrupt
AnnaBridge 145:64910690c574 773 \details Disables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge 145:64910690c574 774 \param [in] IRQn Device specific interrupt number.
AnnaBridge 145:64910690c574 775 \note IRQn must not be negative.
Kojto 113:f141b2784e32 776 */
AnnaBridge 145:64910690c574 777 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
Kojto 113:f141b2784e32 778 {
AnnaBridge 145:64910690c574 779 if ((int32_t)(IRQn) >= 0)
AnnaBridge 145:64910690c574 780 {
AnnaBridge 145:64910690c574 781 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 145:64910690c574 782 __DSB();
AnnaBridge 145:64910690c574 783 __ISB();
AnnaBridge 145:64910690c574 784 }
Kojto 113:f141b2784e32 785 }
Kojto 113:f141b2784e32 786
Kojto 113:f141b2784e32 787
AnnaBridge 145:64910690c574 788 /**
AnnaBridge 145:64910690c574 789 \brief Get Pending Interrupt
AnnaBridge 145:64910690c574 790 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
AnnaBridge 145:64910690c574 791 \param [in] IRQn Device specific interrupt number.
AnnaBridge 145:64910690c574 792 \return 0 Interrupt status is not pending.
AnnaBridge 145:64910690c574 793 \return 1 Interrupt status is pending.
AnnaBridge 145:64910690c574 794 \note IRQn must not be negative.
Kojto 113:f141b2784e32 795 */
AnnaBridge 145:64910690c574 796 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
Kojto 113:f141b2784e32 797 {
AnnaBridge 145:64910690c574 798 if ((int32_t)(IRQn) >= 0)
AnnaBridge 145:64910690c574 799 {
AnnaBridge 145:64910690c574 800 return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 145:64910690c574 801 }
AnnaBridge 145:64910690c574 802 else
AnnaBridge 145:64910690c574 803 {
AnnaBridge 145:64910690c574 804 return(0U);
AnnaBridge 145:64910690c574 805 }
Kojto 113:f141b2784e32 806 }
Kojto 113:f141b2784e32 807
Kojto 113:f141b2784e32 808
AnnaBridge 145:64910690c574 809 /**
AnnaBridge 145:64910690c574 810 \brief Set Pending Interrupt
AnnaBridge 145:64910690c574 811 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge 145:64910690c574 812 \param [in] IRQn Device specific interrupt number.
AnnaBridge 145:64910690c574 813 \note IRQn must not be negative.
Kojto 113:f141b2784e32 814 */
AnnaBridge 145:64910690c574 815 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
Kojto 113:f141b2784e32 816 {
AnnaBridge 145:64910690c574 817 if ((int32_t)(IRQn) >= 0)
AnnaBridge 145:64910690c574 818 {
AnnaBridge 145:64910690c574 819 NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
Kojto 113:f141b2784e32 820 }
Kojto 113:f141b2784e32 821 }
Kojto 113:f141b2784e32 822
Kojto 113:f141b2784e32 823
AnnaBridge 145:64910690c574 824 /**
AnnaBridge 145:64910690c574 825 \brief Clear Pending Interrupt
AnnaBridge 145:64910690c574 826 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge 145:64910690c574 827 \param [in] IRQn Device specific interrupt number.
AnnaBridge 145:64910690c574 828 \note IRQn must not be negative.
AnnaBridge 145:64910690c574 829 */
AnnaBridge 145:64910690c574 830 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
AnnaBridge 145:64910690c574 831 {
AnnaBridge 145:64910690c574 832 if ((int32_t)(IRQn) >= 0)
AnnaBridge 145:64910690c574 833 {
AnnaBridge 145:64910690c574 834 NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge 145:64910690c574 835 }
AnnaBridge 145:64910690c574 836 }
Kojto 113:f141b2784e32 837
Kojto 113:f141b2784e32 838
AnnaBridge 145:64910690c574 839 /**
AnnaBridge 145:64910690c574 840 \brief Set Interrupt Priority
AnnaBridge 145:64910690c574 841 \details Sets the priority of a device specific interrupt or a processor exception.
AnnaBridge 145:64910690c574 842 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 145:64910690c574 843 or negative to specify a processor exception.
AnnaBridge 145:64910690c574 844 \param [in] IRQn Interrupt number.
AnnaBridge 145:64910690c574 845 \param [in] priority Priority to set.
AnnaBridge 145:64910690c574 846 \note The priority cannot be set for every processor exception.
Kojto 113:f141b2784e32 847 */
AnnaBridge 145:64910690c574 848 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Kojto 113:f141b2784e32 849 {
AnnaBridge 145:64910690c574 850 if ((int32_t)(IRQn) >= 0)
AnnaBridge 145:64910690c574 851 {
AnnaBridge 145:64910690c574 852 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
AnnaBridge 145:64910690c574 853 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Kojto 113:f141b2784e32 854 }
AnnaBridge 145:64910690c574 855 else
AnnaBridge 145:64910690c574 856 {
AnnaBridge 145:64910690c574 857 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
AnnaBridge 145:64910690c574 858 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Kojto 113:f141b2784e32 859 }
Kojto 113:f141b2784e32 860 }
Kojto 113:f141b2784e32 861
Kojto 113:f141b2784e32 862
AnnaBridge 145:64910690c574 863 /**
AnnaBridge 145:64910690c574 864 \brief Get Interrupt Priority
AnnaBridge 145:64910690c574 865 \details Reads the priority of a device specific interrupt or a processor exception.
AnnaBridge 145:64910690c574 866 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 145:64910690c574 867 or negative to specify a processor exception.
AnnaBridge 145:64910690c574 868 \param [in] IRQn Interrupt number.
AnnaBridge 145:64910690c574 869 \return Interrupt Priority.
AnnaBridge 145:64910690c574 870 Value is aligned automatically to the implemented priority bits of the microcontroller.
Kojto 113:f141b2784e32 871 */
AnnaBridge 145:64910690c574 872 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
AnnaBridge 145:64910690c574 873 {
AnnaBridge 145:64910690c574 874
AnnaBridge 145:64910690c574 875 if ((int32_t)(IRQn) >= 0)
AnnaBridge 145:64910690c574 876 {
AnnaBridge 145:64910690c574 877 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge 145:64910690c574 878 }
AnnaBridge 145:64910690c574 879 else
AnnaBridge 145:64910690c574 880 {
AnnaBridge 145:64910690c574 881 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge 145:64910690c574 882 }
AnnaBridge 145:64910690c574 883 }
AnnaBridge 145:64910690c574 884
AnnaBridge 145:64910690c574 885
AnnaBridge 145:64910690c574 886 /**
AnnaBridge 145:64910690c574 887 \brief Set Interrupt Vector
AnnaBridge 145:64910690c574 888 \details Sets an interrupt vector in SRAM based interrupt vector table.
AnnaBridge 145:64910690c574 889 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 145:64910690c574 890 or negative to specify a processor exception.
AnnaBridge 145:64910690c574 891 VTOR must been relocated to SRAM before.
AnnaBridge 145:64910690c574 892 \param [in] IRQn Interrupt number
AnnaBridge 145:64910690c574 893 \param [in] vector Address of interrupt handler function
AnnaBridge 145:64910690c574 894 */
AnnaBridge 145:64910690c574 895 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
Kojto 113:f141b2784e32 896 {
AnnaBridge 145:64910690c574 897 uint32_t *vectors = (uint32_t *)SCB->VTOR;
AnnaBridge 145:64910690c574 898 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
AnnaBridge 145:64910690c574 899 }
AnnaBridge 145:64910690c574 900
AnnaBridge 145:64910690c574 901
AnnaBridge 145:64910690c574 902 /**
AnnaBridge 145:64910690c574 903 \brief Get Interrupt Vector
AnnaBridge 145:64910690c574 904 \details Reads an interrupt vector from interrupt vector table.
AnnaBridge 145:64910690c574 905 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 145:64910690c574 906 or negative to specify a processor exception.
AnnaBridge 145:64910690c574 907 \param [in] IRQn Interrupt number.
AnnaBridge 145:64910690c574 908 \return Address of interrupt handler function
AnnaBridge 145:64910690c574 909 */
AnnaBridge 145:64910690c574 910 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
AnnaBridge 145:64910690c574 911 {
AnnaBridge 145:64910690c574 912 uint32_t *vectors = (uint32_t *)SCB->VTOR;
AnnaBridge 145:64910690c574 913 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
AnnaBridge 145:64910690c574 914 }
AnnaBridge 145:64910690c574 915
AnnaBridge 145:64910690c574 916
AnnaBridge 145:64910690c574 917 /**
AnnaBridge 145:64910690c574 918 \brief System Reset
AnnaBridge 145:64910690c574 919 \details Initiates a system reset request to reset the MCU.
AnnaBridge 145:64910690c574 920 */
AnnaBridge 145:64910690c574 921 __STATIC_INLINE void __NVIC_SystemReset(void)
AnnaBridge 145:64910690c574 922 {
AnnaBridge 145:64910690c574 923 __DSB(); /* Ensure all outstanding memory accesses included
AnnaBridge 145:64910690c574 924 buffered write are completed before reset */
Kojto 113:f141b2784e32 925 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
Kojto 113:f141b2784e32 926 SCB_AIRCR_SYSRESETREQ_Msk);
AnnaBridge 145:64910690c574 927 __DSB(); /* Ensure completion of memory access */
AnnaBridge 145:64910690c574 928
AnnaBridge 145:64910690c574 929 for(;;) /* wait until reset */
AnnaBridge 145:64910690c574 930 {
AnnaBridge 145:64910690c574 931 __NOP();
AnnaBridge 145:64910690c574 932 }
Kojto 113:f141b2784e32 933 }
Kojto 113:f141b2784e32 934
Kojto 113:f141b2784e32 935 /*@} end of CMSIS_Core_NVICFunctions */
Kojto 113:f141b2784e32 936
Kojto 113:f141b2784e32 937
AnnaBridge 145:64910690c574 938 /* ########################## FPU functions #################################### */
AnnaBridge 145:64910690c574 939 /**
AnnaBridge 145:64910690c574 940 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 145:64910690c574 941 \defgroup CMSIS_Core_FpuFunctions FPU Functions
AnnaBridge 145:64910690c574 942 \brief Function that provides FPU type.
Kojto 113:f141b2784e32 943 @{
Kojto 113:f141b2784e32 944 */
Kojto 113:f141b2784e32 945
AnnaBridge 145:64910690c574 946 /**
AnnaBridge 145:64910690c574 947 \brief get FPU type
AnnaBridge 145:64910690c574 948 \details returns the FPU type
AnnaBridge 145:64910690c574 949 \returns
AnnaBridge 145:64910690c574 950 - \b 0: No FPU
AnnaBridge 145:64910690c574 951 - \b 1: Single precision FPU
AnnaBridge 145:64910690c574 952 - \b 2: Double + Single precision FPU
AnnaBridge 145:64910690c574 953 */
AnnaBridge 145:64910690c574 954 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
AnnaBridge 145:64910690c574 955 {
AnnaBridge 145:64910690c574 956 return 0U; /* No FPU */
AnnaBridge 145:64910690c574 957 }
Kojto 113:f141b2784e32 958
Kojto 113:f141b2784e32 959
AnnaBridge 145:64910690c574 960 /*@} end of CMSIS_Core_FpuFunctions */
AnnaBridge 145:64910690c574 961
AnnaBridge 145:64910690c574 962
Kojto 113:f141b2784e32 963
AnnaBridge 145:64910690c574 964 /* ################################## SysTick function ############################################ */
AnnaBridge 145:64910690c574 965 /**
AnnaBridge 145:64910690c574 966 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 145:64910690c574 967 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
AnnaBridge 145:64910690c574 968 \brief Functions that configure the System.
AnnaBridge 145:64910690c574 969 @{
AnnaBridge 145:64910690c574 970 */
Kojto 113:f141b2784e32 971
AnnaBridge 145:64910690c574 972 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
Kojto 113:f141b2784e32 973
AnnaBridge 145:64910690c574 974 /**
AnnaBridge 145:64910690c574 975 \brief System Tick Configuration
AnnaBridge 145:64910690c574 976 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
AnnaBridge 145:64910690c574 977 Counter is in free running mode to generate periodic interrupts.
AnnaBridge 145:64910690c574 978 \param [in] ticks Number of ticks between two interrupts.
AnnaBridge 145:64910690c574 979 \return 0 Function succeeded.
AnnaBridge 145:64910690c574 980 \return 1 Function failed.
AnnaBridge 145:64910690c574 981 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
AnnaBridge 145:64910690c574 982 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
AnnaBridge 145:64910690c574 983 must contain a vendor-specific implementation of this function.
Kojto 113:f141b2784e32 984 */
Kojto 113:f141b2784e32 985 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Kojto 113:f141b2784e32 986 {
AnnaBridge 145:64910690c574 987 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
AnnaBridge 145:64910690c574 988 {
AnnaBridge 145:64910690c574 989 return (1UL); /* Reload value impossible */
AnnaBridge 145:64910690c574 990 }
Kojto 113:f141b2784e32 991
Kojto 113:f141b2784e32 992 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Kojto 113:f141b2784e32 993 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Kojto 113:f141b2784e32 994 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
Kojto 113:f141b2784e32 995 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
Kojto 113:f141b2784e32 996 SysTick_CTRL_TICKINT_Msk |
Kojto 113:f141b2784e32 997 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Kojto 113:f141b2784e32 998 return (0UL); /* Function successful */
Kojto 113:f141b2784e32 999 }
Kojto 113:f141b2784e32 1000
Kojto 113:f141b2784e32 1001 #endif
Kojto 113:f141b2784e32 1002
Kojto 113:f141b2784e32 1003 /*@} end of CMSIS_Core_SysTickFunctions */
Kojto 113:f141b2784e32 1004
Kojto 113:f141b2784e32 1005
Kojto 113:f141b2784e32 1006
Kojto 113:f141b2784e32 1007
Kojto 113:f141b2784e32 1008 #ifdef __cplusplus
Kojto 113:f141b2784e32 1009 }
Kojto 113:f141b2784e32 1010 #endif
Kojto 113:f141b2784e32 1011
Kojto 113:f141b2784e32 1012 #endif /* __CORE_SC000_H_DEPENDANT */
Kojto 113:f141b2784e32 1013
Kojto 113:f141b2784e32 1014 #endif /* __CMSIS_GENERIC */