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TARGET_NUCLEO_F446RE/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma.h@169:a7c7b631e539, 2018-06-22 (annotated)

Committer:
Anna Bridge
Date:
Fri Jun 22 15:38:59 2018 +0100
Revision:
169:a7c7b631e539
Parent:
163:e59c8e839560 
mbed library. Release version 162

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 156:ff21514d8981 1 /**
AnnaBridge 156:ff21514d8981 2 ******************************************************************************
AnnaBridge 156:ff21514d8981 3 * @file stm32f4xx_hal_dma.h
AnnaBridge 156:ff21514d8981 4 * @author MCD Application Team
AnnaBridge 156:ff21514d8981 5 * @brief Header file of DMA HAL module.
AnnaBridge 156:ff21514d8981 6 ******************************************************************************
AnnaBridge 156:ff21514d8981 7 * @attention
AnnaBridge 156:ff21514d8981 8 *
AnnaBridge 156:ff21514d8981 9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge 156:ff21514d8981 10 *
AnnaBridge 156:ff21514d8981 11 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 156:ff21514d8981 12 * are permitted provided that the following conditions are met:
AnnaBridge 156:ff21514d8981 13 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 156:ff21514d8981 14 * this list of conditions and the following disclaimer.
AnnaBridge 156:ff21514d8981 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 156:ff21514d8981 16 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 156:ff21514d8981 17 * and/or other materials provided with the distribution.
AnnaBridge 156:ff21514d8981 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 156:ff21514d8981 19 * may be used to endorse or promote products derived from this software
AnnaBridge 156:ff21514d8981 20 * without specific prior written permission.
AnnaBridge 156:ff21514d8981 21 *
AnnaBridge 156:ff21514d8981 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 156:ff21514d8981 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 156:ff21514d8981 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 156:ff21514d8981 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 156:ff21514d8981 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 156:ff21514d8981 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 156:ff21514d8981 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 156:ff21514d8981 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 156:ff21514d8981 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 156:ff21514d8981 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 156:ff21514d8981 32 *
AnnaBridge 156:ff21514d8981 33 ******************************************************************************
AnnaBridge 156:ff21514d8981 34 */
AnnaBridge 156:ff21514d8981 35
AnnaBridge 156:ff21514d8981 36 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 156:ff21514d8981 37 #ifndef __STM32F4xx_HAL_DMA_H
AnnaBridge 156:ff21514d8981 38 #define __STM32F4xx_HAL_DMA_H
AnnaBridge 156:ff21514d8981 39
AnnaBridge 156:ff21514d8981 40 #ifdef __cplusplus
AnnaBridge 156:ff21514d8981 41 extern "C" {
AnnaBridge 156:ff21514d8981 42 #endif
AnnaBridge 156:ff21514d8981 43
AnnaBridge 156:ff21514d8981 44 /* Includes ------------------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 45 #include "stm32f4xx_hal_def.h"
AnnaBridge 156:ff21514d8981 46
AnnaBridge 156:ff21514d8981 47 /** @addtogroup STM32F4xx_HAL_Driver
AnnaBridge 156:ff21514d8981 48 * @{
AnnaBridge 156:ff21514d8981 49 */
AnnaBridge 156:ff21514d8981 50
AnnaBridge 156:ff21514d8981 51 /** @addtogroup DMA
AnnaBridge 156:ff21514d8981 52 * @{
AnnaBridge 156:ff21514d8981 53 */
AnnaBridge 156:ff21514d8981 54
AnnaBridge 156:ff21514d8981 55 /* Exported types ------------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 56
AnnaBridge 156:ff21514d8981 57 /** @defgroup DMA_Exported_Types DMA Exported Types
AnnaBridge 156:ff21514d8981 58 * @brief DMA Exported Types
AnnaBridge 156:ff21514d8981 59 * @{
AnnaBridge 156:ff21514d8981 60 */
AnnaBridge 156:ff21514d8981 61
AnnaBridge 156:ff21514d8981 62 /**
AnnaBridge 156:ff21514d8981 63 * @brief DMA Configuration Structure definition
AnnaBridge 156:ff21514d8981 64 */
AnnaBridge 156:ff21514d8981 65 typedef struct
AnnaBridge 156:ff21514d8981 66 {
AnnaBridge 156:ff21514d8981 67 uint32_t Channel; /*!< Specifies the channel used for the specified stream.
AnnaBridge 156:ff21514d8981 68 This parameter can be a value of @ref DMA_Channel_selection */
AnnaBridge 156:ff21514d8981 69
AnnaBridge 156:ff21514d8981 70 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
AnnaBridge 156:ff21514d8981 71 from memory to memory or from peripheral to memory.
AnnaBridge 156:ff21514d8981 72 This parameter can be a value of @ref DMA_Data_transfer_direction */
AnnaBridge 156:ff21514d8981 73
AnnaBridge 156:ff21514d8981 74 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
AnnaBridge 156:ff21514d8981 75 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
AnnaBridge 156:ff21514d8981 76
AnnaBridge 156:ff21514d8981 77 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
AnnaBridge 156:ff21514d8981 78 This parameter can be a value of @ref DMA_Memory_incremented_mode */
AnnaBridge 156:ff21514d8981 79
AnnaBridge 156:ff21514d8981 80 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
AnnaBridge 156:ff21514d8981 81 This parameter can be a value of @ref DMA_Peripheral_data_size */
AnnaBridge 156:ff21514d8981 82
AnnaBridge 156:ff21514d8981 83 uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
AnnaBridge 156:ff21514d8981 84 This parameter can be a value of @ref DMA_Memory_data_size */
AnnaBridge 156:ff21514d8981 85
AnnaBridge 156:ff21514d8981 86 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx.
AnnaBridge 156:ff21514d8981 87 This parameter can be a value of @ref DMA_mode
AnnaBridge 156:ff21514d8981 88 @note The circular buffer mode cannot be used if the memory-to-memory
AnnaBridge 156:ff21514d8981 89 data transfer is configured on the selected Stream */
AnnaBridge 156:ff21514d8981 90
AnnaBridge 156:ff21514d8981 91 uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx.
AnnaBridge 156:ff21514d8981 92 This parameter can be a value of @ref DMA_Priority_level */
AnnaBridge 156:ff21514d8981 93
AnnaBridge 156:ff21514d8981 94 uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
AnnaBridge 156:ff21514d8981 95 This parameter can be a value of @ref DMA_FIFO_direct_mode
AnnaBridge 156:ff21514d8981 96 @note The Direct mode (FIFO mode disabled) cannot be used if the
AnnaBridge 156:ff21514d8981 97 memory-to-memory data transfer is configured on the selected stream */
AnnaBridge 156:ff21514d8981 98
AnnaBridge 156:ff21514d8981 99 uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level.
AnnaBridge 156:ff21514d8981 100 This parameter can be a value of @ref DMA_FIFO_threshold_level */
AnnaBridge 156:ff21514d8981 101
AnnaBridge 156:ff21514d8981 102 uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
AnnaBridge 156:ff21514d8981 103 It specifies the amount of data to be transferred in a single non interruptible
AnnaBridge 156:ff21514d8981 104 transaction.
AnnaBridge 156:ff21514d8981 105 This parameter can be a value of @ref DMA_Memory_burst
AnnaBridge 156:ff21514d8981 106 @note The burst mode is possible only if the address Increment mode is enabled. */
AnnaBridge 156:ff21514d8981 107
AnnaBridge 156:ff21514d8981 108 uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
AnnaBridge 156:ff21514d8981 109 It specifies the amount of data to be transferred in a single non interruptible
AnnaBridge 156:ff21514d8981 110 transaction.
AnnaBridge 156:ff21514d8981 111 This parameter can be a value of @ref DMA_Peripheral_burst
AnnaBridge 156:ff21514d8981 112 @note The burst mode is possible only if the address Increment mode is enabled. */
AnnaBridge 156:ff21514d8981 113 }DMA_InitTypeDef;
AnnaBridge 156:ff21514d8981 114
AnnaBridge 156:ff21514d8981 115
AnnaBridge 156:ff21514d8981 116 /**
AnnaBridge 156:ff21514d8981 117 * @brief HAL DMA State structures definition
AnnaBridge 156:ff21514d8981 118 */
AnnaBridge 156:ff21514d8981 119 typedef enum
AnnaBridge 156:ff21514d8981 120 {
AnnaBridge 156:ff21514d8981 121 HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
AnnaBridge 156:ff21514d8981 122 HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */
AnnaBridge 156:ff21514d8981 123 HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
AnnaBridge 156:ff21514d8981 124 HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */
AnnaBridge 156:ff21514d8981 125 HAL_DMA_STATE_ERROR = 0x04U, /*!< DMA error state */
AnnaBridge 156:ff21514d8981 126 HAL_DMA_STATE_ABORT = 0x05U, /*!< DMA Abort state */
AnnaBridge 156:ff21514d8981 127 }HAL_DMA_StateTypeDef;
AnnaBridge 156:ff21514d8981 128
AnnaBridge 156:ff21514d8981 129 /**
AnnaBridge 156:ff21514d8981 130 * @brief HAL DMA Error Code structure definition
AnnaBridge 156:ff21514d8981 131 */
AnnaBridge 156:ff21514d8981 132 typedef enum
AnnaBridge 156:ff21514d8981 133 {
AnnaBridge 156:ff21514d8981 134 HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
AnnaBridge 156:ff21514d8981 135 HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */
AnnaBridge 156:ff21514d8981 136 }HAL_DMA_LevelCompleteTypeDef;
AnnaBridge 156:ff21514d8981 137
AnnaBridge 156:ff21514d8981 138 /**
AnnaBridge 156:ff21514d8981 139 * @brief HAL DMA Error Code structure definition
AnnaBridge 156:ff21514d8981 140 */
AnnaBridge 156:ff21514d8981 141 typedef enum
AnnaBridge 156:ff21514d8981 142 {
AnnaBridge 156:ff21514d8981 143 HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */
AnnaBridge 156:ff21514d8981 144 HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half Transfer */
AnnaBridge 156:ff21514d8981 145 HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U, /*!< M1 Full Transfer */
AnnaBridge 156:ff21514d8981 146 HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U, /*!< M1 Half Transfer */
AnnaBridge 156:ff21514d8981 147 HAL_DMA_XFER_ERROR_CB_ID = 0x04U, /*!< Error */
AnnaBridge 156:ff21514d8981 148 HAL_DMA_XFER_ABORT_CB_ID = 0x05U, /*!< Abort */
AnnaBridge 156:ff21514d8981 149 HAL_DMA_XFER_ALL_CB_ID = 0x06U /*!< All */
AnnaBridge 156:ff21514d8981 150 }HAL_DMA_CallbackIDTypeDef;
AnnaBridge 156:ff21514d8981 151
AnnaBridge 156:ff21514d8981 152 /**
AnnaBridge 156:ff21514d8981 153 * @brief DMA handle Structure definition
AnnaBridge 156:ff21514d8981 154 */
AnnaBridge 156:ff21514d8981 155 typedef struct __DMA_HandleTypeDef
AnnaBridge 156:ff21514d8981 156 {
AnnaBridge 156:ff21514d8981 157 DMA_Stream_TypeDef *Instance; /*!< Register base address */
AnnaBridge 156:ff21514d8981 158
AnnaBridge 156:ff21514d8981 159 DMA_InitTypeDef Init; /*!< DMA communication parameters */
AnnaBridge 156:ff21514d8981 160
AnnaBridge 156:ff21514d8981 161 HAL_LockTypeDef Lock; /*!< DMA locking object */
AnnaBridge 156:ff21514d8981 162
AnnaBridge 156:ff21514d8981 163 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
AnnaBridge 156:ff21514d8981 164
AnnaBridge 156:ff21514d8981 165 void *Parent; /*!< Parent object state */
AnnaBridge 156:ff21514d8981 166
AnnaBridge 156:ff21514d8981 167 void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
AnnaBridge 156:ff21514d8981 168
AnnaBridge 156:ff21514d8981 169 void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
AnnaBridge 156:ff21514d8981 170
AnnaBridge 156:ff21514d8981 171 void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */
AnnaBridge 156:ff21514d8981 172
AnnaBridge 156:ff21514d8981 173 void (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Half complete Memory1 callback */
AnnaBridge 156:ff21514d8981 174
AnnaBridge 156:ff21514d8981 175 void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
AnnaBridge 156:ff21514d8981 176
AnnaBridge 156:ff21514d8981 177 void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Abort callback */
AnnaBridge 156:ff21514d8981 178
AnnaBridge 156:ff21514d8981 179 __IO uint32_t ErrorCode; /*!< DMA Error code */
AnnaBridge 156:ff21514d8981 180
AnnaBridge 156:ff21514d8981 181 uint32_t StreamBaseAddress; /*!< DMA Stream Base Address */
AnnaBridge 156:ff21514d8981 182
AnnaBridge 156:ff21514d8981 183 uint32_t StreamIndex; /*!< DMA Stream Index */
AnnaBridge 156:ff21514d8981 184
AnnaBridge 156:ff21514d8981 185 }DMA_HandleTypeDef;
AnnaBridge 156:ff21514d8981 186
AnnaBridge 156:ff21514d8981 187 /**
AnnaBridge 156:ff21514d8981 188 * @}
AnnaBridge 156:ff21514d8981 189 */
AnnaBridge 156:ff21514d8981 190
AnnaBridge 156:ff21514d8981 191 /* Exported constants --------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 192
AnnaBridge 156:ff21514d8981 193 /** @defgroup DMA_Exported_Constants DMA Exported Constants
AnnaBridge 156:ff21514d8981 194 * @brief DMA Exported constants
AnnaBridge 156:ff21514d8981 195 * @{
AnnaBridge 156:ff21514d8981 196 */
AnnaBridge 156:ff21514d8981 197
AnnaBridge 156:ff21514d8981 198 /** @defgroup DMA_Error_Code DMA Error Code
AnnaBridge 156:ff21514d8981 199 * @brief DMA Error Code
AnnaBridge 156:ff21514d8981 200 * @{
AnnaBridge 156:ff21514d8981 201 */
AnnaBridge 156:ff21514d8981 202 #define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */
AnnaBridge 156:ff21514d8981 203 #define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */
AnnaBridge 156:ff21514d8981 204 #define HAL_DMA_ERROR_FE 0x00000002U /*!< FIFO error */
AnnaBridge 156:ff21514d8981 205 #define HAL_DMA_ERROR_DME 0x00000004U /*!< Direct Mode error */
AnnaBridge 156:ff21514d8981 206 #define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */
AnnaBridge 156:ff21514d8981 207 #define HAL_DMA_ERROR_PARAM 0x00000040U /*!< Parameter error */
AnnaBridge 156:ff21514d8981 208 #define HAL_DMA_ERROR_NO_XFER 0x00000080U /*!< Abort requested with no Xfer ongoing */
AnnaBridge 156:ff21514d8981 209 #define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */
AnnaBridge 156:ff21514d8981 210 /**
AnnaBridge 156:ff21514d8981 211 * @}
AnnaBridge 156:ff21514d8981 212 */
AnnaBridge 156:ff21514d8981 213
AnnaBridge 156:ff21514d8981 214 /** @defgroup DMA_Channel_selection DMA Channel selection
AnnaBridge 156:ff21514d8981 215 * @brief DMA channel selection
AnnaBridge 156:ff21514d8981 216 * @{
AnnaBridge 156:ff21514d8981 217 */
AnnaBridge 156:ff21514d8981 218 #define DMA_CHANNEL_0 0x00000000U /*!< DMA Channel 0 */
AnnaBridge 156:ff21514d8981 219 #define DMA_CHANNEL_1 0x02000000U /*!< DMA Channel 1 */
AnnaBridge 156:ff21514d8981 220 #define DMA_CHANNEL_2 0x04000000U /*!< DMA Channel 2 */
AnnaBridge 156:ff21514d8981 221 #define DMA_CHANNEL_3 0x06000000U /*!< DMA Channel 3 */
AnnaBridge 156:ff21514d8981 222 #define DMA_CHANNEL_4 0x08000000U /*!< DMA Channel 4 */
AnnaBridge 156:ff21514d8981 223 #define DMA_CHANNEL_5 0x0A000000U /*!< DMA Channel 5 */
AnnaBridge 156:ff21514d8981 224 #define DMA_CHANNEL_6 0x0C000000U /*!< DMA Channel 6 */
AnnaBridge 156:ff21514d8981 225 #define DMA_CHANNEL_7 0x0E000000U /*!< DMA Channel 7 */
AnnaBridge 156:ff21514d8981 226 #if defined (DMA_SxCR_CHSEL_3)
AnnaBridge 156:ff21514d8981 227 #define DMA_CHANNEL_8 0x10000000U /*!< DMA Channel 8 */
AnnaBridge 156:ff21514d8981 228 #define DMA_CHANNEL_9 0x12000000U /*!< DMA Channel 9 */
AnnaBridge 156:ff21514d8981 229 #define DMA_CHANNEL_10 0x14000000U /*!< DMA Channel 10 */
AnnaBridge 156:ff21514d8981 230 #define DMA_CHANNEL_11 0x16000000U /*!< DMA Channel 11 */
AnnaBridge 156:ff21514d8981 231 #define DMA_CHANNEL_12 0x18000000U /*!< DMA Channel 12 */
AnnaBridge 156:ff21514d8981 232 #define DMA_CHANNEL_13 0x1A000000U /*!< DMA Channel 13 */
AnnaBridge 156:ff21514d8981 233 #define DMA_CHANNEL_14 0x1C000000U /*!< DMA Channel 14 */
AnnaBridge 156:ff21514d8981 234 #define DMA_CHANNEL_15 0x1E000000U /*!< DMA Channel 15 */
AnnaBridge 156:ff21514d8981 235 #endif /* DMA_SxCR_CHSEL_3 */
AnnaBridge 156:ff21514d8981 236 /**
AnnaBridge 156:ff21514d8981 237 * @}
AnnaBridge 156:ff21514d8981 238 */
AnnaBridge 156:ff21514d8981 239
AnnaBridge 156:ff21514d8981 240 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
AnnaBridge 156:ff21514d8981 241 * @brief DMA data transfer direction
AnnaBridge 156:ff21514d8981 242 * @{
AnnaBridge 156:ff21514d8981 243 */
AnnaBridge 156:ff21514d8981 244 #define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
AnnaBridge 156:ff21514d8981 245 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */
AnnaBridge 156:ff21514d8981 246 #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */
AnnaBridge 156:ff21514d8981 247 /**
AnnaBridge 156:ff21514d8981 248 * @}
AnnaBridge 156:ff21514d8981 249 */
AnnaBridge 156:ff21514d8981 250
AnnaBridge 156:ff21514d8981 251 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
AnnaBridge 156:ff21514d8981 252 * @brief DMA peripheral incremented mode
AnnaBridge 156:ff21514d8981 253 * @{
AnnaBridge 156:ff21514d8981 254 */
AnnaBridge 156:ff21514d8981 255 #define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */
AnnaBridge 156:ff21514d8981 256 #define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode disable */
AnnaBridge 156:ff21514d8981 257 /**
AnnaBridge 156:ff21514d8981 258 * @}
AnnaBridge 156:ff21514d8981 259 */
AnnaBridge 156:ff21514d8981 260
AnnaBridge 156:ff21514d8981 261 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
AnnaBridge 156:ff21514d8981 262 * @brief DMA memory incremented mode
AnnaBridge 156:ff21514d8981 263 * @{
AnnaBridge 156:ff21514d8981 264 */
AnnaBridge 156:ff21514d8981 265 #define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */
AnnaBridge 156:ff21514d8981 266 #define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode disable */
AnnaBridge 156:ff21514d8981 267 /**
AnnaBridge 156:ff21514d8981 268 * @}
AnnaBridge 156:ff21514d8981 269 */
AnnaBridge 156:ff21514d8981 270
AnnaBridge 156:ff21514d8981 271 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
AnnaBridge 156:ff21514d8981 272 * @brief DMA peripheral data size
AnnaBridge 156:ff21514d8981 273 * @{
AnnaBridge 156:ff21514d8981 274 */
AnnaBridge 156:ff21514d8981 275 #define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment: Byte */
AnnaBridge 156:ff21514d8981 276 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */
AnnaBridge 156:ff21514d8981 277 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */
AnnaBridge 156:ff21514d8981 278 /**
AnnaBridge 156:ff21514d8981 279 * @}
AnnaBridge 156:ff21514d8981 280 */
AnnaBridge 156:ff21514d8981 281
AnnaBridge 156:ff21514d8981 282 /** @defgroup DMA_Memory_data_size DMA Memory data size
AnnaBridge 156:ff21514d8981 283 * @brief DMA memory data size
AnnaBridge 156:ff21514d8981 284 * @{
AnnaBridge 156:ff21514d8981 285 */
AnnaBridge 156:ff21514d8981 286 #define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment: Byte */
AnnaBridge 156:ff21514d8981 287 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */
AnnaBridge 156:ff21514d8981 288 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */
AnnaBridge 156:ff21514d8981 289 /**
AnnaBridge 156:ff21514d8981 290 * @}
AnnaBridge 156:ff21514d8981 291 */
AnnaBridge 156:ff21514d8981 292
AnnaBridge 156:ff21514d8981 293 /** @defgroup DMA_mode DMA mode
AnnaBridge 156:ff21514d8981 294 * @brief DMA mode
AnnaBridge 156:ff21514d8981 295 * @{
AnnaBridge 156:ff21514d8981 296 */
AnnaBridge 156:ff21514d8981 297 #define DMA_NORMAL 0x00000000U /*!< Normal mode */
AnnaBridge 156:ff21514d8981 298 #define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */
AnnaBridge 156:ff21514d8981 299 #define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */
AnnaBridge 156:ff21514d8981 300 /**
AnnaBridge 156:ff21514d8981 301 * @}
AnnaBridge 156:ff21514d8981 302 */
AnnaBridge 156:ff21514d8981 303
AnnaBridge 156:ff21514d8981 304 /** @defgroup DMA_Priority_level DMA Priority level
AnnaBridge 156:ff21514d8981 305 * @brief DMA priority levels
AnnaBridge 156:ff21514d8981 306 * @{
AnnaBridge 156:ff21514d8981 307 */
AnnaBridge 156:ff21514d8981 308 #define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level: Low */
AnnaBridge 156:ff21514d8981 309 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */
AnnaBridge 156:ff21514d8981 310 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */
AnnaBridge 156:ff21514d8981 311 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */
AnnaBridge 156:ff21514d8981 312 /**
AnnaBridge 156:ff21514d8981 313 * @}
AnnaBridge 156:ff21514d8981 314 */
AnnaBridge 156:ff21514d8981 315
AnnaBridge 156:ff21514d8981 316 /** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode
AnnaBridge 156:ff21514d8981 317 * @brief DMA FIFO direct mode
AnnaBridge 156:ff21514d8981 318 * @{
AnnaBridge 156:ff21514d8981 319 */
AnnaBridge 156:ff21514d8981 320 #define DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */
AnnaBridge 156:ff21514d8981 321 #define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */
AnnaBridge 156:ff21514d8981 322 /**
AnnaBridge 156:ff21514d8981 323 * @}
AnnaBridge 156:ff21514d8981 324 */
AnnaBridge 156:ff21514d8981 325
AnnaBridge 156:ff21514d8981 326 /** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level
AnnaBridge 156:ff21514d8981 327 * @brief DMA FIFO level
AnnaBridge 156:ff21514d8981 328 * @{
AnnaBridge 156:ff21514d8981 329 */
AnnaBridge 156:ff21514d8981 330 #define DMA_FIFO_THRESHOLD_1QUARTERFULL 0x00000000U /*!< FIFO threshold 1 quart full configuration */
AnnaBridge 156:ff21514d8981 331 #define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */
AnnaBridge 156:ff21514d8981 332 #define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */
AnnaBridge 156:ff21514d8981 333 #define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */
AnnaBridge 156:ff21514d8981 334 /**
AnnaBridge 156:ff21514d8981 335 * @}
AnnaBridge 156:ff21514d8981 336 */
AnnaBridge 156:ff21514d8981 337
AnnaBridge 156:ff21514d8981 338 /** @defgroup DMA_Memory_burst DMA Memory burst
AnnaBridge 156:ff21514d8981 339 * @brief DMA memory burst
AnnaBridge 156:ff21514d8981 340 * @{
AnnaBridge 156:ff21514d8981 341 */
AnnaBridge 156:ff21514d8981 342 #define DMA_MBURST_SINGLE 0x00000000U
AnnaBridge 156:ff21514d8981 343 #define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0)
AnnaBridge 156:ff21514d8981 344 #define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1)
AnnaBridge 156:ff21514d8981 345 #define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST)
AnnaBridge 156:ff21514d8981 346 /**
AnnaBridge 156:ff21514d8981 347 * @}
AnnaBridge 156:ff21514d8981 348 */
AnnaBridge 156:ff21514d8981 349
AnnaBridge 156:ff21514d8981 350 /** @defgroup DMA_Peripheral_burst DMA Peripheral burst
AnnaBridge 156:ff21514d8981 351 * @brief DMA peripheral burst
AnnaBridge 156:ff21514d8981 352 * @{
AnnaBridge 156:ff21514d8981 353 */
AnnaBridge 156:ff21514d8981 354 #define DMA_PBURST_SINGLE 0x00000000U
AnnaBridge 156:ff21514d8981 355 #define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0)
AnnaBridge 156:ff21514d8981 356 #define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1)
AnnaBridge 156:ff21514d8981 357 #define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST)
AnnaBridge 156:ff21514d8981 358 /**
AnnaBridge 156:ff21514d8981 359 * @}
AnnaBridge 156:ff21514d8981 360 */
AnnaBridge 156:ff21514d8981 361
AnnaBridge 156:ff21514d8981 362 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
AnnaBridge 156:ff21514d8981 363 * @brief DMA interrupts definition
AnnaBridge 156:ff21514d8981 364 * @{
AnnaBridge 156:ff21514d8981 365 */
AnnaBridge 156:ff21514d8981 366 #define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE)
AnnaBridge 156:ff21514d8981 367 #define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE)
AnnaBridge 156:ff21514d8981 368 #define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE)
AnnaBridge 156:ff21514d8981 369 #define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE)
AnnaBridge 156:ff21514d8981 370 #define DMA_IT_FE 0x00000080U
AnnaBridge 156:ff21514d8981 371 /**
AnnaBridge 156:ff21514d8981 372 * @}
AnnaBridge 156:ff21514d8981 373 */
AnnaBridge 156:ff21514d8981 374
AnnaBridge 156:ff21514d8981 375 /** @defgroup DMA_flag_definitions DMA flag definitions
AnnaBridge 156:ff21514d8981 376 * @brief DMA flag definitions
AnnaBridge 156:ff21514d8981 377 * @{
AnnaBridge 156:ff21514d8981 378 */
AnnaBridge 163:e59c8e839560 379 #define DMA_FLAG_FEIF0_4 0x00000001U
AnnaBridge 163:e59c8e839560 380 #define DMA_FLAG_DMEIF0_4 0x00000004U
AnnaBridge 156:ff21514d8981 381 #define DMA_FLAG_TEIF0_4 0x00000008U
AnnaBridge 156:ff21514d8981 382 #define DMA_FLAG_HTIF0_4 0x00000010U
AnnaBridge 156:ff21514d8981 383 #define DMA_FLAG_TCIF0_4 0x00000020U
AnnaBridge 156:ff21514d8981 384 #define DMA_FLAG_FEIF1_5 0x00000040U
AnnaBridge 156:ff21514d8981 385 #define DMA_FLAG_DMEIF1_5 0x00000100U
AnnaBridge 156:ff21514d8981 386 #define DMA_FLAG_TEIF1_5 0x00000200U
AnnaBridge 156:ff21514d8981 387 #define DMA_FLAG_HTIF1_5 0x00000400U
AnnaBridge 156:ff21514d8981 388 #define DMA_FLAG_TCIF1_5 0x00000800U
AnnaBridge 156:ff21514d8981 389 #define DMA_FLAG_FEIF2_6 0x00010000U
AnnaBridge 156:ff21514d8981 390 #define DMA_FLAG_DMEIF2_6 0x00040000U
AnnaBridge 156:ff21514d8981 391 #define DMA_FLAG_TEIF2_6 0x00080000U
AnnaBridge 156:ff21514d8981 392 #define DMA_FLAG_HTIF2_6 0x00100000U
AnnaBridge 156:ff21514d8981 393 #define DMA_FLAG_TCIF2_6 0x00200000U
AnnaBridge 156:ff21514d8981 394 #define DMA_FLAG_FEIF3_7 0x00400000U
AnnaBridge 156:ff21514d8981 395 #define DMA_FLAG_DMEIF3_7 0x01000000U
AnnaBridge 156:ff21514d8981 396 #define DMA_FLAG_TEIF3_7 0x02000000U
AnnaBridge 156:ff21514d8981 397 #define DMA_FLAG_HTIF3_7 0x04000000U
AnnaBridge 156:ff21514d8981 398 #define DMA_FLAG_TCIF3_7 0x08000000U
AnnaBridge 156:ff21514d8981 399 /**
AnnaBridge 156:ff21514d8981 400 * @}
AnnaBridge 156:ff21514d8981 401 */
AnnaBridge 156:ff21514d8981 402
AnnaBridge 156:ff21514d8981 403 /**
AnnaBridge 156:ff21514d8981 404 * @}
AnnaBridge 156:ff21514d8981 405 */
AnnaBridge 156:ff21514d8981 406
AnnaBridge 156:ff21514d8981 407 /* Exported macro ------------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 408
AnnaBridge 156:ff21514d8981 409 /** @brief Reset DMA handle state
AnnaBridge 163:e59c8e839560 410 * @param __HANDLE__ specifies the DMA handle.
AnnaBridge 156:ff21514d8981 411 * @retval None
AnnaBridge 156:ff21514d8981 412 */
AnnaBridge 156:ff21514d8981 413 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
AnnaBridge 156:ff21514d8981 414
AnnaBridge 156:ff21514d8981 415 /**
AnnaBridge 156:ff21514d8981 416 * @brief Return the current DMA Stream FIFO filled level.
AnnaBridge 163:e59c8e839560 417 * @param __HANDLE__ DMA handle
AnnaBridge 156:ff21514d8981 418 * @retval The FIFO filling state.
AnnaBridge 156:ff21514d8981 419 * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full
AnnaBridge 156:ff21514d8981 420 * and not empty.
AnnaBridge 156:ff21514d8981 421 * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
AnnaBridge 156:ff21514d8981 422 * - DMA_FIFOStatus_HalfFull: if more than 1 half-full.
AnnaBridge 156:ff21514d8981 423 * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
AnnaBridge 156:ff21514d8981 424 * - DMA_FIFOStatus_Empty: when FIFO is empty
AnnaBridge 156:ff21514d8981 425 * - DMA_FIFOStatus_Full: when FIFO is full
AnnaBridge 156:ff21514d8981 426 */
AnnaBridge 156:ff21514d8981 427 #define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))
AnnaBridge 156:ff21514d8981 428
AnnaBridge 156:ff21514d8981 429 /**
AnnaBridge 156:ff21514d8981 430 * @brief Enable the specified DMA Stream.
AnnaBridge 163:e59c8e839560 431 * @param __HANDLE__ DMA handle
AnnaBridge 156:ff21514d8981 432 * @retval None
AnnaBridge 156:ff21514d8981 433 */
AnnaBridge 156:ff21514d8981 434 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN)
AnnaBridge 156:ff21514d8981 435
AnnaBridge 156:ff21514d8981 436 /**
AnnaBridge 156:ff21514d8981 437 * @brief Disable the specified DMA Stream.
AnnaBridge 163:e59c8e839560 438 * @param __HANDLE__ DMA handle
AnnaBridge 156:ff21514d8981 439 * @retval None
AnnaBridge 156:ff21514d8981 440 */
AnnaBridge 156:ff21514d8981 441 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN)
AnnaBridge 156:ff21514d8981 442
AnnaBridge 156:ff21514d8981 443 /* Interrupt & Flag management */
AnnaBridge 156:ff21514d8981 444
AnnaBridge 156:ff21514d8981 445 /**
AnnaBridge 156:ff21514d8981 446 * @brief Return the current DMA Stream transfer complete flag.
AnnaBridge 163:e59c8e839560 447 * @param __HANDLE__ DMA handle
AnnaBridge 156:ff21514d8981 448 * @retval The specified transfer complete flag index.
AnnaBridge 156:ff21514d8981 449 */
AnnaBridge 156:ff21514d8981 450 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
AnnaBridge 156:ff21514d8981 451 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
AnnaBridge 156:ff21514d8981 452 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
AnnaBridge 156:ff21514d8981 453 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
AnnaBridge 156:ff21514d8981 454 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
AnnaBridge 156:ff21514d8981 455 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
AnnaBridge 156:ff21514d8981 456 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
AnnaBridge 156:ff21514d8981 457 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
AnnaBridge 156:ff21514d8981 458 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
AnnaBridge 156:ff21514d8981 459 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
AnnaBridge 156:ff21514d8981 460 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
AnnaBridge 156:ff21514d8981 461 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
AnnaBridge 156:ff21514d8981 462 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
AnnaBridge 156:ff21514d8981 463 DMA_FLAG_TCIF3_7)
AnnaBridge 156:ff21514d8981 464
AnnaBridge 156:ff21514d8981 465 /**
AnnaBridge 156:ff21514d8981 466 * @brief Return the current DMA Stream half transfer complete flag.
AnnaBridge 163:e59c8e839560 467 * @param __HANDLE__ DMA handle
AnnaBridge 156:ff21514d8981 468 * @retval The specified half transfer complete flag index.
AnnaBridge 156:ff21514d8981 469 */
AnnaBridge 156:ff21514d8981 470 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
AnnaBridge 156:ff21514d8981 471 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
AnnaBridge 156:ff21514d8981 472 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
AnnaBridge 156:ff21514d8981 473 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
AnnaBridge 156:ff21514d8981 474 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
AnnaBridge 156:ff21514d8981 475 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
AnnaBridge 156:ff21514d8981 476 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
AnnaBridge 156:ff21514d8981 477 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
AnnaBridge 156:ff21514d8981 478 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
AnnaBridge 156:ff21514d8981 479 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
AnnaBridge 156:ff21514d8981 480 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
AnnaBridge 156:ff21514d8981 481 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
AnnaBridge 156:ff21514d8981 482 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
AnnaBridge 156:ff21514d8981 483 DMA_FLAG_HTIF3_7)
AnnaBridge 156:ff21514d8981 484
AnnaBridge 156:ff21514d8981 485 /**
AnnaBridge 156:ff21514d8981 486 * @brief Return the current DMA Stream transfer error flag.
AnnaBridge 163:e59c8e839560 487 * @param __HANDLE__ DMA handle
AnnaBridge 156:ff21514d8981 488 * @retval The specified transfer error flag index.
AnnaBridge 156:ff21514d8981 489 */
AnnaBridge 156:ff21514d8981 490 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
AnnaBridge 156:ff21514d8981 491 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
AnnaBridge 156:ff21514d8981 492 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
AnnaBridge 156:ff21514d8981 493 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
AnnaBridge 156:ff21514d8981 494 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
AnnaBridge 156:ff21514d8981 495 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
AnnaBridge 156:ff21514d8981 496 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
AnnaBridge 156:ff21514d8981 497 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
AnnaBridge 156:ff21514d8981 498 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
AnnaBridge 156:ff21514d8981 499 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
AnnaBridge 156:ff21514d8981 500 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
AnnaBridge 156:ff21514d8981 501 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
AnnaBridge 156:ff21514d8981 502 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
AnnaBridge 156:ff21514d8981 503 DMA_FLAG_TEIF3_7)
AnnaBridge 156:ff21514d8981 504
AnnaBridge 156:ff21514d8981 505 /**
AnnaBridge 156:ff21514d8981 506 * @brief Return the current DMA Stream FIFO error flag.
AnnaBridge 163:e59c8e839560 507 * @param __HANDLE__ DMA handle
AnnaBridge 156:ff21514d8981 508 * @retval The specified FIFO error flag index.
AnnaBridge 156:ff21514d8981 509 */
AnnaBridge 156:ff21514d8981 510 #define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\
AnnaBridge 156:ff21514d8981 511 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\
AnnaBridge 156:ff21514d8981 512 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\
AnnaBridge 156:ff21514d8981 513 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\
AnnaBridge 156:ff21514d8981 514 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\
AnnaBridge 156:ff21514d8981 515 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\
AnnaBridge 156:ff21514d8981 516 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\
AnnaBridge 156:ff21514d8981 517 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
AnnaBridge 156:ff21514d8981 518 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\
AnnaBridge 156:ff21514d8981 519 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\
AnnaBridge 156:ff21514d8981 520 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\
AnnaBridge 156:ff21514d8981 521 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\
AnnaBridge 156:ff21514d8981 522 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\
AnnaBridge 156:ff21514d8981 523 DMA_FLAG_FEIF3_7)
AnnaBridge 156:ff21514d8981 524
AnnaBridge 156:ff21514d8981 525 /**
AnnaBridge 156:ff21514d8981 526 * @brief Return the current DMA Stream direct mode error flag.
AnnaBridge 163:e59c8e839560 527 * @param __HANDLE__ DMA handle
AnnaBridge 156:ff21514d8981 528 * @retval The specified direct mode error flag index.
AnnaBridge 156:ff21514d8981 529 */
AnnaBridge 156:ff21514d8981 530 #define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\
AnnaBridge 156:ff21514d8981 531 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\
AnnaBridge 156:ff21514d8981 532 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\
AnnaBridge 156:ff21514d8981 533 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\
AnnaBridge 156:ff21514d8981 534 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\
AnnaBridge 156:ff21514d8981 535 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\
AnnaBridge 156:ff21514d8981 536 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\
AnnaBridge 156:ff21514d8981 537 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
AnnaBridge 156:ff21514d8981 538 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\
AnnaBridge 156:ff21514d8981 539 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\
AnnaBridge 156:ff21514d8981 540 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\
AnnaBridge 156:ff21514d8981 541 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\
AnnaBridge 156:ff21514d8981 542 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\
AnnaBridge 156:ff21514d8981 543 DMA_FLAG_DMEIF3_7)
AnnaBridge 156:ff21514d8981 544
AnnaBridge 156:ff21514d8981 545 /**
AnnaBridge 156:ff21514d8981 546 * @brief Get the DMA Stream pending flags.
AnnaBridge 163:e59c8e839560 547 * @param __HANDLE__ DMA handle
AnnaBridge 163:e59c8e839560 548 * @param __FLAG__ Get the specified flag.
AnnaBridge 156:ff21514d8981 549 * This parameter can be any combination of the following values:
AnnaBridge 156:ff21514d8981 550 * @arg DMA_FLAG_TCIFx: Transfer complete flag.
AnnaBridge 156:ff21514d8981 551 * @arg DMA_FLAG_HTIFx: Half transfer complete flag.
AnnaBridge 156:ff21514d8981 552 * @arg DMA_FLAG_TEIFx: Transfer error flag.
AnnaBridge 156:ff21514d8981 553 * @arg DMA_FLAG_DMEIFx: Direct mode error flag.
AnnaBridge 156:ff21514d8981 554 * @arg DMA_FLAG_FEIFx: FIFO error flag.
AnnaBridge 156:ff21514d8981 555 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
AnnaBridge 156:ff21514d8981 556 * @retval The state of FLAG (SET or RESET).
AnnaBridge 156:ff21514d8981 557 */
AnnaBridge 156:ff21514d8981 558 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
AnnaBridge 156:ff21514d8981 559 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
AnnaBridge 156:ff21514d8981 560 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
AnnaBridge 156:ff21514d8981 561 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
AnnaBridge 156:ff21514d8981 562
AnnaBridge 156:ff21514d8981 563 /**
AnnaBridge 156:ff21514d8981 564 * @brief Clear the DMA Stream pending flags.
AnnaBridge 163:e59c8e839560 565 * @param __HANDLE__ DMA handle
AnnaBridge 163:e59c8e839560 566 * @param __FLAG__ specifies the flag to clear.
AnnaBridge 156:ff21514d8981 567 * This parameter can be any combination of the following values:
AnnaBridge 156:ff21514d8981 568 * @arg DMA_FLAG_TCIFx: Transfer complete flag.
AnnaBridge 156:ff21514d8981 569 * @arg DMA_FLAG_HTIFx: Half transfer complete flag.
AnnaBridge 156:ff21514d8981 570 * @arg DMA_FLAG_TEIFx: Transfer error flag.
AnnaBridge 156:ff21514d8981 571 * @arg DMA_FLAG_DMEIFx: Direct mode error flag.
AnnaBridge 156:ff21514d8981 572 * @arg DMA_FLAG_FEIFx: FIFO error flag.
AnnaBridge 156:ff21514d8981 573 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
AnnaBridge 156:ff21514d8981 574 * @retval None
AnnaBridge 156:ff21514d8981 575 */
AnnaBridge 156:ff21514d8981 576 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
AnnaBridge 156:ff21514d8981 577 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
AnnaBridge 156:ff21514d8981 578 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
AnnaBridge 156:ff21514d8981 579 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
AnnaBridge 156:ff21514d8981 580
AnnaBridge 156:ff21514d8981 581 /**
AnnaBridge 156:ff21514d8981 582 * @brief Enable the specified DMA Stream interrupts.
AnnaBridge 163:e59c8e839560 583 * @param __HANDLE__ DMA handle
AnnaBridge 163:e59c8e839560 584 * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
AnnaBridge 156:ff21514d8981 585 * This parameter can be any combination of the following values:
AnnaBridge 156:ff21514d8981 586 * @arg DMA_IT_TC: Transfer complete interrupt mask.
AnnaBridge 156:ff21514d8981 587 * @arg DMA_IT_HT: Half transfer complete interrupt mask.
AnnaBridge 156:ff21514d8981 588 * @arg DMA_IT_TE: Transfer error interrupt mask.
AnnaBridge 156:ff21514d8981 589 * @arg DMA_IT_FE: FIFO error interrupt mask.
AnnaBridge 156:ff21514d8981 590 * @arg DMA_IT_DME: Direct mode error interrupt.
AnnaBridge 156:ff21514d8981 591 * @retval None
AnnaBridge 156:ff21514d8981 592 */
AnnaBridge 156:ff21514d8981 593 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
AnnaBridge 156:ff21514d8981 594 ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__)))
AnnaBridge 156:ff21514d8981 595
AnnaBridge 156:ff21514d8981 596 /**
AnnaBridge 156:ff21514d8981 597 * @brief Disable the specified DMA Stream interrupts.
AnnaBridge 163:e59c8e839560 598 * @param __HANDLE__ DMA handle
AnnaBridge 163:e59c8e839560 599 * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
AnnaBridge 156:ff21514d8981 600 * This parameter can be any combination of the following values:
AnnaBridge 156:ff21514d8981 601 * @arg DMA_IT_TC: Transfer complete interrupt mask.
AnnaBridge 156:ff21514d8981 602 * @arg DMA_IT_HT: Half transfer complete interrupt mask.
AnnaBridge 156:ff21514d8981 603 * @arg DMA_IT_TE: Transfer error interrupt mask.
AnnaBridge 156:ff21514d8981 604 * @arg DMA_IT_FE: FIFO error interrupt mask.
AnnaBridge 156:ff21514d8981 605 * @arg DMA_IT_DME: Direct mode error interrupt.
AnnaBridge 156:ff21514d8981 606 * @retval None
AnnaBridge 156:ff21514d8981 607 */
AnnaBridge 156:ff21514d8981 608 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
AnnaBridge 156:ff21514d8981 609 ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__)))
AnnaBridge 156:ff21514d8981 610
AnnaBridge 156:ff21514d8981 611 /**
AnnaBridge 156:ff21514d8981 612 * @brief Check whether the specified DMA Stream interrupt is enabled or disabled.
AnnaBridge 163:e59c8e839560 613 * @param __HANDLE__ DMA handle
AnnaBridge 163:e59c8e839560 614 * @param __INTERRUPT__ specifies the DMA interrupt source to check.
AnnaBridge 156:ff21514d8981 615 * This parameter can be one of the following values:
AnnaBridge 156:ff21514d8981 616 * @arg DMA_IT_TC: Transfer complete interrupt mask.
AnnaBridge 156:ff21514d8981 617 * @arg DMA_IT_HT: Half transfer complete interrupt mask.
AnnaBridge 156:ff21514d8981 618 * @arg DMA_IT_TE: Transfer error interrupt mask.
AnnaBridge 156:ff21514d8981 619 * @arg DMA_IT_FE: FIFO error interrupt mask.
AnnaBridge 156:ff21514d8981 620 * @arg DMA_IT_DME: Direct mode error interrupt.
AnnaBridge 156:ff21514d8981 621 * @retval The state of DMA_IT.
AnnaBridge 156:ff21514d8981 622 */
AnnaBridge 156:ff21514d8981 623 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
AnnaBridge 156:ff21514d8981 624 ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \
AnnaBridge 156:ff21514d8981 625 ((__HANDLE__)->Instance->FCR & (__INTERRUPT__)))
AnnaBridge 156:ff21514d8981 626
AnnaBridge 156:ff21514d8981 627 /**
AnnaBridge 156:ff21514d8981 628 * @brief Writes the number of data units to be transferred on the DMA Stream.
AnnaBridge 163:e59c8e839560 629 * @param __HANDLE__ DMA handle
AnnaBridge 163:e59c8e839560 630 * @param __COUNTER__ Number of data units to be transferred (from 0 to 65535)
AnnaBridge 156:ff21514d8981 631 * Number of data items depends only on the Peripheral data format.
AnnaBridge 156:ff21514d8981 632 *
AnnaBridge 156:ff21514d8981 633 * @note If Peripheral data format is Bytes: number of data units is equal
AnnaBridge 156:ff21514d8981 634 * to total number of bytes to be transferred.
AnnaBridge 156:ff21514d8981 635 *
AnnaBridge 156:ff21514d8981 636 * @note If Peripheral data format is Half-Word: number of data units is
AnnaBridge 156:ff21514d8981 637 * equal to total number of bytes to be transferred / 2.
AnnaBridge 156:ff21514d8981 638 *
AnnaBridge 156:ff21514d8981 639 * @note If Peripheral data format is Word: number of data units is equal
AnnaBridge 156:ff21514d8981 640 * to total number of bytes to be transferred / 4.
AnnaBridge 156:ff21514d8981 641 *
AnnaBridge 156:ff21514d8981 642 * @retval The number of remaining data units in the current DMAy Streamx transfer.
AnnaBridge 156:ff21514d8981 643 */
AnnaBridge 156:ff21514d8981 644 #define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__))
AnnaBridge 156:ff21514d8981 645
AnnaBridge 156:ff21514d8981 646 /**
AnnaBridge 156:ff21514d8981 647 * @brief Returns the number of remaining data units in the current DMAy Streamx transfer.
AnnaBridge 163:e59c8e839560 648 * @param __HANDLE__ DMA handle
AnnaBridge 156:ff21514d8981 649 *
AnnaBridge 156:ff21514d8981 650 * @retval The number of remaining data units in the current DMA Stream transfer.
AnnaBridge 156:ff21514d8981 651 */
AnnaBridge 156:ff21514d8981 652 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR)
AnnaBridge 156:ff21514d8981 653
AnnaBridge 156:ff21514d8981 654
AnnaBridge 156:ff21514d8981 655 /* Include DMA HAL Extension module */
AnnaBridge 156:ff21514d8981 656 #include "stm32f4xx_hal_dma_ex.h"
AnnaBridge 156:ff21514d8981 657
AnnaBridge 156:ff21514d8981 658 /* Exported functions --------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 659
AnnaBridge 156:ff21514d8981 660 /** @defgroup DMA_Exported_Functions DMA Exported Functions
AnnaBridge 156:ff21514d8981 661 * @brief DMA Exported functions
AnnaBridge 156:ff21514d8981 662 * @{
AnnaBridge 156:ff21514d8981 663 */
AnnaBridge 156:ff21514d8981 664
AnnaBridge 156:ff21514d8981 665 /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
AnnaBridge 156:ff21514d8981 666 * @brief Initialization and de-initialization functions
AnnaBridge 156:ff21514d8981 667 * @{
AnnaBridge 156:ff21514d8981 668 */
AnnaBridge 156:ff21514d8981 669 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
AnnaBridge 156:ff21514d8981 670 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
AnnaBridge 156:ff21514d8981 671 /**
AnnaBridge 156:ff21514d8981 672 * @}
AnnaBridge 156:ff21514d8981 673 */
AnnaBridge 156:ff21514d8981 674
AnnaBridge 156:ff21514d8981 675 /** @defgroup DMA_Exported_Functions_Group2 I/O operation functions
AnnaBridge 156:ff21514d8981 676 * @brief I/O operation functions
AnnaBridge 156:ff21514d8981 677 * @{
AnnaBridge 156:ff21514d8981 678 */
AnnaBridge 156:ff21514d8981 679 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
AnnaBridge 156:ff21514d8981 680 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
AnnaBridge 156:ff21514d8981 681 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
AnnaBridge 156:ff21514d8981 682 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
AnnaBridge 156:ff21514d8981 683 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
AnnaBridge 156:ff21514d8981 684 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
AnnaBridge 156:ff21514d8981 685 HAL_StatusTypeDef HAL_DMA_CleanCallbacks(DMA_HandleTypeDef *hdma);
AnnaBridge 156:ff21514d8981 686 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
AnnaBridge 156:ff21514d8981 687 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
AnnaBridge 156:ff21514d8981 688
AnnaBridge 156:ff21514d8981 689 /**
AnnaBridge 156:ff21514d8981 690 * @}
AnnaBridge 156:ff21514d8981 691 */
AnnaBridge 156:ff21514d8981 692
AnnaBridge 156:ff21514d8981 693 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
AnnaBridge 156:ff21514d8981 694 * @brief Peripheral State functions
AnnaBridge 156:ff21514d8981 695 * @{
AnnaBridge 156:ff21514d8981 696 */
AnnaBridge 156:ff21514d8981 697 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
AnnaBridge 156:ff21514d8981 698 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
AnnaBridge 156:ff21514d8981 699 /**
AnnaBridge 156:ff21514d8981 700 * @}
AnnaBridge 156:ff21514d8981 701 */
AnnaBridge 156:ff21514d8981 702 /**
AnnaBridge 156:ff21514d8981 703 * @}
AnnaBridge 156:ff21514d8981 704 */
AnnaBridge 156:ff21514d8981 705 /* Private Constants -------------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 706 /** @defgroup DMA_Private_Constants DMA Private Constants
AnnaBridge 156:ff21514d8981 707 * @brief DMA private defines and constants
AnnaBridge 156:ff21514d8981 708 * @{
AnnaBridge 156:ff21514d8981 709 */
AnnaBridge 156:ff21514d8981 710 /**
AnnaBridge 156:ff21514d8981 711 * @}
AnnaBridge 156:ff21514d8981 712 */
AnnaBridge 156:ff21514d8981 713
AnnaBridge 156:ff21514d8981 714 /* Private macros ------------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 715 /** @defgroup DMA_Private_Macros DMA Private Macros
AnnaBridge 156:ff21514d8981 716 * @brief DMA private macros
AnnaBridge 156:ff21514d8981 717 * @{
AnnaBridge 156:ff21514d8981 718 */
AnnaBridge 156:ff21514d8981 719 #if defined (DMA_SxCR_CHSEL_3)
AnnaBridge 156:ff21514d8981 720 #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
AnnaBridge 156:ff21514d8981 721 ((CHANNEL) == DMA_CHANNEL_1) || \
AnnaBridge 156:ff21514d8981 722 ((CHANNEL) == DMA_CHANNEL_2) || \
AnnaBridge 156:ff21514d8981 723 ((CHANNEL) == DMA_CHANNEL_3) || \
AnnaBridge 156:ff21514d8981 724 ((CHANNEL) == DMA_CHANNEL_4) || \
AnnaBridge 156:ff21514d8981 725 ((CHANNEL) == DMA_CHANNEL_5) || \
AnnaBridge 156:ff21514d8981 726 ((CHANNEL) == DMA_CHANNEL_6) || \
AnnaBridge 156:ff21514d8981 727 ((CHANNEL) == DMA_CHANNEL_7) || \
AnnaBridge 156:ff21514d8981 728 ((CHANNEL) == DMA_CHANNEL_8) || \
AnnaBridge 156:ff21514d8981 729 ((CHANNEL) == DMA_CHANNEL_9) || \
AnnaBridge 156:ff21514d8981 730 ((CHANNEL) == DMA_CHANNEL_10)|| \
AnnaBridge 156:ff21514d8981 731 ((CHANNEL) == DMA_CHANNEL_11)|| \
AnnaBridge 156:ff21514d8981 732 ((CHANNEL) == DMA_CHANNEL_12)|| \
AnnaBridge 156:ff21514d8981 733 ((CHANNEL) == DMA_CHANNEL_13)|| \
AnnaBridge 156:ff21514d8981 734 ((CHANNEL) == DMA_CHANNEL_14)|| \
AnnaBridge 156:ff21514d8981 735 ((CHANNEL) == DMA_CHANNEL_15))
AnnaBridge 156:ff21514d8981 736 #else
AnnaBridge 156:ff21514d8981 737 #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
AnnaBridge 156:ff21514d8981 738 ((CHANNEL) == DMA_CHANNEL_1) || \
AnnaBridge 156:ff21514d8981 739 ((CHANNEL) == DMA_CHANNEL_2) || \
AnnaBridge 156:ff21514d8981 740 ((CHANNEL) == DMA_CHANNEL_3) || \
AnnaBridge 156:ff21514d8981 741 ((CHANNEL) == DMA_CHANNEL_4) || \
AnnaBridge 156:ff21514d8981 742 ((CHANNEL) == DMA_CHANNEL_5) || \
AnnaBridge 156:ff21514d8981 743 ((CHANNEL) == DMA_CHANNEL_6) || \
AnnaBridge 156:ff21514d8981 744 ((CHANNEL) == DMA_CHANNEL_7))
AnnaBridge 156:ff21514d8981 745 #endif /* DMA_SxCR_CHSEL_3 */
AnnaBridge 156:ff21514d8981 746
AnnaBridge 156:ff21514d8981 747 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
AnnaBridge 156:ff21514d8981 748 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
AnnaBridge 156:ff21514d8981 749 ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
AnnaBridge 156:ff21514d8981 750
AnnaBridge 156:ff21514d8981 751 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U))
AnnaBridge 156:ff21514d8981 752
AnnaBridge 156:ff21514d8981 753 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
AnnaBridge 156:ff21514d8981 754 ((STATE) == DMA_PINC_DISABLE))
AnnaBridge 156:ff21514d8981 755
AnnaBridge 156:ff21514d8981 756 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
AnnaBridge 156:ff21514d8981 757 ((STATE) == DMA_MINC_DISABLE))
AnnaBridge 156:ff21514d8981 758
AnnaBridge 156:ff21514d8981 759 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
AnnaBridge 156:ff21514d8981 760 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
AnnaBridge 156:ff21514d8981 761 ((SIZE) == DMA_PDATAALIGN_WORD))
AnnaBridge 156:ff21514d8981 762
AnnaBridge 156:ff21514d8981 763 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
AnnaBridge 156:ff21514d8981 764 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
AnnaBridge 156:ff21514d8981 765 ((SIZE) == DMA_MDATAALIGN_WORD ))
AnnaBridge 156:ff21514d8981 766
AnnaBridge 156:ff21514d8981 767 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
AnnaBridge 156:ff21514d8981 768 ((MODE) == DMA_CIRCULAR) || \
AnnaBridge 156:ff21514d8981 769 ((MODE) == DMA_PFCTRL))
AnnaBridge 156:ff21514d8981 770
AnnaBridge 156:ff21514d8981 771 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
AnnaBridge 156:ff21514d8981 772 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
AnnaBridge 156:ff21514d8981 773 ((PRIORITY) == DMA_PRIORITY_HIGH) || \
AnnaBridge 156:ff21514d8981 774 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
AnnaBridge 156:ff21514d8981 775
AnnaBridge 156:ff21514d8981 776 #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \
AnnaBridge 156:ff21514d8981 777 ((STATE) == DMA_FIFOMODE_ENABLE))
AnnaBridge 156:ff21514d8981 778
AnnaBridge 156:ff21514d8981 779 #define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \
AnnaBridge 156:ff21514d8981 780 ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \
AnnaBridge 156:ff21514d8981 781 ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \
AnnaBridge 156:ff21514d8981 782 ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))
AnnaBridge 156:ff21514d8981 783
AnnaBridge 156:ff21514d8981 784 #define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \
AnnaBridge 156:ff21514d8981 785 ((BURST) == DMA_MBURST_INC4) || \
AnnaBridge 156:ff21514d8981 786 ((BURST) == DMA_MBURST_INC8) || \
AnnaBridge 156:ff21514d8981 787 ((BURST) == DMA_MBURST_INC16))
AnnaBridge 156:ff21514d8981 788
AnnaBridge 156:ff21514d8981 789 #define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \
AnnaBridge 156:ff21514d8981 790 ((BURST) == DMA_PBURST_INC4) || \
AnnaBridge 156:ff21514d8981 791 ((BURST) == DMA_PBURST_INC8) || \
AnnaBridge 156:ff21514d8981 792 ((BURST) == DMA_PBURST_INC16))
AnnaBridge 156:ff21514d8981 793 /**
AnnaBridge 156:ff21514d8981 794 * @}
AnnaBridge 156:ff21514d8981 795 */
AnnaBridge 156:ff21514d8981 796
AnnaBridge 156:ff21514d8981 797 /* Private functions ---------------------------------------------------------*/
AnnaBridge 156:ff21514d8981 798 /** @defgroup DMA_Private_Functions DMA Private Functions
AnnaBridge 156:ff21514d8981 799 * @brief DMA private functions
AnnaBridge 156:ff21514d8981 800 * @{
AnnaBridge 156:ff21514d8981 801 */
AnnaBridge 156:ff21514d8981 802 /**
AnnaBridge 156:ff21514d8981 803 * @}
AnnaBridge 156:ff21514d8981 804 */
AnnaBridge 156:ff21514d8981 805
AnnaBridge 156:ff21514d8981 806 /**
AnnaBridge 156:ff21514d8981 807 * @}
AnnaBridge 156:ff21514d8981 808 */
AnnaBridge 156:ff21514d8981 809
AnnaBridge 156:ff21514d8981 810 /**
AnnaBridge 156:ff21514d8981 811 * @}
AnnaBridge 156:ff21514d8981 812 */
AnnaBridge 156:ff21514d8981 813
AnnaBridge 156:ff21514d8981 814 #ifdef __cplusplus
AnnaBridge 156:ff21514d8981 815 }
AnnaBridge 156:ff21514d8981 816 #endif
AnnaBridge 156:ff21514d8981 817
AnnaBridge 156:ff21514d8981 818 #endif /* __STM32F4xx_HAL_DMA_H */
AnnaBridge 156:ff21514d8981 819
AnnaBridge 156:ff21514d8981 820 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/