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TARGET_NCS36510/TARGET_ONSEMI/TARGET_NCS36510/spi_ipc7207_map.h@169:a7c7b631e539, 2018-06-22 (annotated)

Committer:
Anna Bridge
Date:
Fri Jun 22 15:38:59 2018 +0100
Revision:
169:a7c7b631e539
Parent:
156:ff21514d8981 
mbed library. Release version 162

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 156:ff21514d8981 1 /**
AnnaBridge 156:ff21514d8981 2 ******************************************************************************
AnnaBridge 156:ff21514d8981 3 * @file spi_ipc7207_map.h
AnnaBridge 156:ff21514d8981 4 * @brief SPI IPC 7207 HW register map
AnnaBridge 156:ff21514d8981 5 * @internal
AnnaBridge 156:ff21514d8981 6 * @author ON Semiconductor
AnnaBridge 156:ff21514d8981 7 * $Rev: 2110 $
AnnaBridge 156:ff21514d8981 8 * $Date: 2013-07-16 20:13:03 +0530 (Tue, 16 Jul 2013) $
AnnaBridge 156:ff21514d8981 9 ******************************************************************************
AnnaBridge 156:ff21514d8981 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
AnnaBridge 156:ff21514d8981 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
AnnaBridge 156:ff21514d8981 12 * under limited terms and conditions. The terms and conditions pertaining to the software
AnnaBridge 156:ff21514d8981 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
AnnaBridge 156:ff21514d8981 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
AnnaBridge 156:ff21514d8981 15 * if applicable the software license agreement. Do not use this software and/or
AnnaBridge 156:ff21514d8981 16 * documentation unless you have carefully read and you agree to the limited terms and
AnnaBridge 156:ff21514d8981 17 * conditions. By using this software and/or documentation, you agree to the limited
AnnaBridge 156:ff21514d8981 18 * terms and conditions.
AnnaBridge 156:ff21514d8981 19 *
AnnaBridge 156:ff21514d8981 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
AnnaBridge 156:ff21514d8981 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
AnnaBridge 156:ff21514d8981 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
AnnaBridge 156:ff21514d8981 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
AnnaBridge 156:ff21514d8981 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
AnnaBridge 156:ff21514d8981 25 * @endinternal
AnnaBridge 156:ff21514d8981 26 *
AnnaBridge 156:ff21514d8981 27 * @ingroup spi_ipc7207
AnnaBridge 156:ff21514d8981 28 *
AnnaBridge 156:ff21514d8981 29 * @details
AnnaBridge 156:ff21514d8981 30 * <p>
AnnaBridge 156:ff21514d8981 31 * SPI HW register map description
AnnaBridge 156:ff21514d8981 32 * </p>
AnnaBridge 156:ff21514d8981 33 *
AnnaBridge 156:ff21514d8981 34 * <h1> Reference document(s) </h1>
AnnaBridge 156:ff21514d8981 35 * <p>
AnnaBridge 156:ff21514d8981 36 * <a href="../pdf/IPC7207_SPI_APB_DS_v1P2.pdf" target="_blank">
AnnaBridge 156:ff21514d8981 37 * IPC7207 APB SPI Design Specification v1.2 </a>
AnnaBridge 156:ff21514d8981 38 * </p>
AnnaBridge 156:ff21514d8981 39 */
AnnaBridge 156:ff21514d8981 40
AnnaBridge 156:ff21514d8981 41 #ifndef SPI_IPC7207_MAP_H_
AnnaBridge 156:ff21514d8981 42 #define SPI_IPC7207_MAP_H_
AnnaBridge 156:ff21514d8981 43
AnnaBridge 156:ff21514d8981 44 #include "architecture.h"
AnnaBridge 156:ff21514d8981 45
AnnaBridge 156:ff21514d8981 46 /** SPI HW Structure Overlay */
AnnaBridge 156:ff21514d8981 47 typedef struct {
AnnaBridge 156:ff21514d8981 48 __O uint32_t TX_DATA;
AnnaBridge 156:ff21514d8981 49 __I uint32_t RX_DATA;
AnnaBridge 156:ff21514d8981 50 __IO uint32_t FDIV;
AnnaBridge 156:ff21514d8981 51 union {
AnnaBridge 156:ff21514d8981 52 struct {
AnnaBridge 156:ff21514d8981 53 __IO uint32_t ENABLE :1; /**< SPI port enable: 0 = disable , 1 = enable */
AnnaBridge 156:ff21514d8981 54 __IO uint32_t SAMPLING_EDGE :1; /**< SDI sampling edge: 0 = opposite to SDO edge / 1 = same as SDO edge */
AnnaBridge 156:ff21514d8981 55 __IO uint32_t ENDIAN :1; /**< Bits endianness: 0 = LSB first (little-endian) / 1 = MSB first (big-endian) */
AnnaBridge 156:ff21514d8981 56 __IO uint32_t CPHA :1; /**< Clock phase: 0 = SDO set before first SCLK edge / 1 = SDO set after first SCLK edge */
AnnaBridge 156:ff21514d8981 57 __IO uint32_t CPOL :1; /**< Clock polarity: 0 = active high / 1 = active low */
AnnaBridge 156:ff21514d8981 58 __IO uint32_t MODE :1; /**< Device mode: 0 = slave mode / 1 = master mode */
AnnaBridge 156:ff21514d8981 59 __IO uint32_t WORD_WIDTH :2; /**< Word width: 0 = 8b / 1 = 16b / 2 = 32b / 3 = reserved */
AnnaBridge 156:ff21514d8981 60 } BITS;
AnnaBridge 156:ff21514d8981 61 __IO uint32_t WORD;
AnnaBridge 156:ff21514d8981 62 } CONTROL;
AnnaBridge 156:ff21514d8981 63 union {
AnnaBridge 156:ff21514d8981 64 struct {
AnnaBridge 156:ff21514d8981 65 __I uint32_t XFER_IP :1; /**< Transfer in progress: 0 = No transfer in progress / 1 = transfer in progress */
AnnaBridge 156:ff21514d8981 66 __I uint32_t XFER_ERROR :1;/**< Transfer error: 0 = no error / 1 = SPI Overflow or Underflow */
AnnaBridge 156:ff21514d8981 67 __I uint32_t TX_EMPTY :1; /**< Transmit FIFO/buffer empty flag: 0 = not empty / 1 = empty */
AnnaBridge 156:ff21514d8981 68 __I uint32_t TX_HALF :1; /**< Transmit FIFO/buffer "half full" flag: 0 = (< half full) / 1 = (>= half full) */
AnnaBridge 156:ff21514d8981 69 __I uint32_t TX_FULL :1; /**< Transmit FIFO/buffer full flag: 0 = not full / 1 = full */
AnnaBridge 156:ff21514d8981 70 __I uint32_t RX_EMPTY :1; /**< Receive FIFO/buffer empty flag: 0 = not empty / 1 = empty */
AnnaBridge 156:ff21514d8981 71 __I uint32_t RX_HALF :1; /**< Receive FIFO/buffer "half full" flag: 0 = (< half full) / 1 = (>= half full) */
AnnaBridge 156:ff21514d8981 72 __I uint32_t RX_FULL :1; /**< Receive FIFO/buffer full flag: 0 = not full / 1 = full */
AnnaBridge 156:ff21514d8981 73 } BITS;
AnnaBridge 156:ff21514d8981 74 __I uint32_t WORD;
AnnaBridge 156:ff21514d8981 75 } STATUS;
AnnaBridge 156:ff21514d8981 76 union {
AnnaBridge 156:ff21514d8981 77 struct {
AnnaBridge 156:ff21514d8981 78 __IO uint32_t SS_ENABLE :4; /**< Slave Select (x4): 0 = disable / 1 = enable */
AnnaBridge 156:ff21514d8981 79 __IO uint32_t SS_BURST :1; /**< Slave Select burst mode (maintain SS active if TXFIFO not empty) */
AnnaBridge 156:ff21514d8981 80 } BITS;
AnnaBridge 156:ff21514d8981 81 __IO uint32_t WORD;
AnnaBridge 156:ff21514d8981 82 } SLAVE_SELECT;
AnnaBridge 156:ff21514d8981 83 __IO uint32_t SLAVE_SELECT_POLARITY; /**< Slave Select polarity for up to 4 slaves:0 = active low / 1 = active high */
AnnaBridge 156:ff21514d8981 84 __IO uint32_t IRQ_ENABLE; /**< IRQ (x8) enable: 0 = disable / 1 = enable */
AnnaBridge 156:ff21514d8981 85 __I uint32_t IRQ_STATUS; /**< IRQ (x8) status: 0 = no IRQ occurred / 1 = IRQ occurred */
AnnaBridge 156:ff21514d8981 86 __O uint32_t IRQ_CLEAR; /**< IRQ (x8) clearing: write 1 to clear IRQ */
AnnaBridge 156:ff21514d8981 87 __IO uint32_t TX_WATERMARK; /**< Transmit FIFO Watermark: Defines level of RX Half Full Flag */
AnnaBridge 156:ff21514d8981 88 __IO uint32_t RX_WATERMARK; /**< Receive FIFO Watermark: Defines level of TX Half Full Flag */
AnnaBridge 156:ff21514d8981 89 __I uint32_t TX_FIFO_LEVEL; /**< Transmit FIFO Level: Indicates actual fill level of TX FIFO. */
AnnaBridge 156:ff21514d8981 90 __I uint32_t RX_FIFO_LEVEL; /**< Transmit FIFO Level: Indicates actual fill level of RX FIFO. */
AnnaBridge 156:ff21514d8981 91 } SpiIpc7207Reg_t, *SpiIpc7207Reg_pt;
AnnaBridge 156:ff21514d8981 92
AnnaBridge 156:ff21514d8981 93 #endif /* SPI_IPC7207_MAP_H_ */