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TARGET_EFM32GG_STK3700/TARGET_Silicon_Labs/TARGET_EFM32/common/clocking.h@169:a7c7b631e539, 2018-06-22 (annotated)

Committer:
Anna Bridge
Date:
Fri Jun 22 15:38:59 2018 +0100
Revision:
169:a7c7b631e539
Parent:
161:aa5281ff4a02 
mbed library. Release version 162

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 128:9bcdf88f62b0 1 /***************************************************************************//**
<> 128:9bcdf88f62b0 2 * @file clocking.h
<> 128:9bcdf88f62b0 3 * @brief Clock selection calculations
<> 128:9bcdf88f62b0 4 *******************************************************************************
<> 128:9bcdf88f62b0 5 * @section License
<> 128:9bcdf88f62b0 6 * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
<> 128:9bcdf88f62b0 7 *******************************************************************************
<> 128:9bcdf88f62b0 8 *
<> 128:9bcdf88f62b0 9 * SPDX-License-Identifier: Apache-2.0
<> 128:9bcdf88f62b0 10 *
<> 128:9bcdf88f62b0 11 * Licensed under the Apache License, Version 2.0 (the "License"); you may
<> 128:9bcdf88f62b0 12 * not use this file except in compliance with the License.
<> 128:9bcdf88f62b0 13 * You may obtain a copy of the License at
<> 128:9bcdf88f62b0 14 *
<> 128:9bcdf88f62b0 15 * http://www.apache.org/licenses/LICENSE-2.0
<> 128:9bcdf88f62b0 16 *
<> 128:9bcdf88f62b0 17 * Unless required by applicable law or agreed to in writing, software
<> 128:9bcdf88f62b0 18 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
<> 128:9bcdf88f62b0 19 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 128:9bcdf88f62b0 20 * See the License for the specific language governing permissions and
<> 128:9bcdf88f62b0 21 * limitations under the License.
<> 128:9bcdf88f62b0 22 *
<> 128:9bcdf88f62b0 23 ******************************************************************************/
<> 128:9bcdf88f62b0 24 #ifndef MBED_CLOCKING_H
<> 128:9bcdf88f62b0 25 #define MBED_CLOCKING_H
<> 128:9bcdf88f62b0 26
AnnaBridge 161:aa5281ff4a02 27 #include "em_cmu.h"
AnnaBridge 161:aa5281ff4a02 28
<> 128:9bcdf88f62b0 29 /* Clock definitions */
<> 128:9bcdf88f62b0 30 #define LFXO 0
<> 128:9bcdf88f62b0 31 #define HFXO 1
<> 128:9bcdf88f62b0 32 #define LFRCO 2
<> 128:9bcdf88f62b0 33 #define HFRCO 3
<> 128:9bcdf88f62b0 34 #if !defined(_EFM32_GECKO_FAMILY)
<> 128:9bcdf88f62b0 35 #define ULFRCO 4
<> 128:9bcdf88f62b0 36 #endif
<> 128:9bcdf88f62b0 37
<> 128:9bcdf88f62b0 38 /* Low Energy peripheral clock source.
<> 128:9bcdf88f62b0 39 * Options:
<> 128:9bcdf88f62b0 40 * * LFXO: external crystal, please define frequency.
<> 128:9bcdf88f62b0 41 * * LFRCO: internal RC oscillator (32.768kHz)
<> 128:9bcdf88f62b0 42 * * ULFRCO: internal ultra-low power RC oscillator (available down to EM3) (1kHz)
<> 128:9bcdf88f62b0 43 */
<> 128:9bcdf88f62b0 44 #ifndef LOW_ENERGY_CLOCK_SOURCE
<> 128:9bcdf88f62b0 45 #define LOW_ENERGY_CLOCK_SOURCE LFXO
<> 128:9bcdf88f62b0 46 #endif
<> 128:9bcdf88f62b0 47
<> 128:9bcdf88f62b0 48 /** Core clock source.
<> 128:9bcdf88f62b0 49 * Options:
<> 128:9bcdf88f62b0 50 * * HFXO: external crystal, please define frequency.
<> 128:9bcdf88f62b0 51 * * HFRCO: High-frequency internal RC oscillator. Please select band as well.
<> 128:9bcdf88f62b0 52 */
<> 128:9bcdf88f62b0 53 #ifndef CORE_CLOCK_SOURCE
<> 128:9bcdf88f62b0 54 #define CORE_CLOCK_SOURCE HFRCO
<> 128:9bcdf88f62b0 55 #if defined(_CMU_HFRCOCTRL_BAND_MASK)
AnnaBridge 161:aa5281ff4a02 56 #define HFRCO_FREQUENCY_ENUM _CMU_HFRCOCTRL_BAND_21MHZ
AnnaBridge 161:aa5281ff4a02 57 #define HFRCO_FREQUENCY 21000000
<> 128:9bcdf88f62b0 58 #elif defined(_CMU_HFRCOCTRL_FREQRANGE_MASK)
<> 128:9bcdf88f62b0 59 #define HFRCO_FREQUENCY_ENUM cmuHFRCOFreq_32M0Hz
<> 128:9bcdf88f62b0 60 #define HFRCO_FREQUENCY 32000000
<> 128:9bcdf88f62b0 61 #endif
<> 128:9bcdf88f62b0 62 #endif // CORE_CLOCK_SOURCE
<> 128:9bcdf88f62b0 63
<> 128:9bcdf88f62b0 64 #if !defined(LFXO_FREQUENCY) && (LOW_ENERGY_CLOCK_SOURCE == LFXO)
<> 128:9bcdf88f62b0 65 #error "LFXO frequency is undefined!"
<> 128:9bcdf88f62b0 66 #endif
<> 128:9bcdf88f62b0 67
<> 128:9bcdf88f62b0 68 #if !defined(HFXO_FREQUENCY) && (CORE_CLOCK_SOURCE == HFXO)
<> 128:9bcdf88f62b0 69 #error "HFXO frequency is undefined!"
<> 128:9bcdf88f62b0 70 #endif
<> 128:9bcdf88f62b0 71
<> 128:9bcdf88f62b0 72 #if (LOW_ENERGY_CLOCK_SOURCE == LFXO)
<> 128:9bcdf88f62b0 73 #define LOW_ENERGY_CLOCK_FREQUENCY LFXO_FREQUENCY
<> 128:9bcdf88f62b0 74 #elif (LOW_ENERGY_CLOCK_SOURCE == LFRCO)
<> 128:9bcdf88f62b0 75 #define LOW_ENERGY_CLOCK_FREQUENCY 32768
<> 128:9bcdf88f62b0 76 #elif (LOW_ENERGY_CLOCK_SOURCE == ULFRCO)
<> 128:9bcdf88f62b0 77 #define LOW_ENERGY_CLOCK_FREQUENCY 1000
<> 128:9bcdf88f62b0 78 #else
<> 128:9bcdf88f62b0 79 #error "Unknown Low Energy Clock selection"
<> 128:9bcdf88f62b0 80 #endif
<> 128:9bcdf88f62b0 81
<> 128:9bcdf88f62b0 82 #if( CORE_CLOCK_SOURCE == HFXO)
<> 128:9bcdf88f62b0 83 # define REFERENCE_FREQUENCY HFXO_FREQUENCY
<> 128:9bcdf88f62b0 84 #elif( CORE_CLOCK_SOURCE == HFRCO)
<> 128:9bcdf88f62b0 85 #if !defined(HFRCO_FREQUENCY)
<> 128:9bcdf88f62b0 86 # error "HFRCO frequency is not defined!"
<> 128:9bcdf88f62b0 87 #else
<> 128:9bcdf88f62b0 88 # define REFERENCE_FREQUENCY HFRCO_FREQUENCY
<> 128:9bcdf88f62b0 89 #endif
<> 128:9bcdf88f62b0 90 #endif
<> 128:9bcdf88f62b0 91
<> 128:9bcdf88f62b0 92 #if ( LOW_ENERGY_CLOCK_SOURCE == LFXO )
<> 128:9bcdf88f62b0 93 # define LEUART_USING_LFXO
<> 128:9bcdf88f62b0 94 # if ( (defined(CMU_CTRL_HFLE) || defined(CMU_CTRL_WSHFLE) ) && (REFERENCE_FREQUENCY > 24000000) )
<> 128:9bcdf88f62b0 95 # define LEUART_HF_REF_FREQ (REFERENCE_FREQUENCY / 4)
<> 128:9bcdf88f62b0 96 # else
<> 128:9bcdf88f62b0 97 # define LEUART_HF_REF_FREQ (REFERENCE_FREQUENCY / 2)
<> 128:9bcdf88f62b0 98 # endif
<> 128:9bcdf88f62b0 99 # define LEUART_LF_REF_FREQ LFXO_FREQUENCY
<> 128:9bcdf88f62b0 100 #else
<> 128:9bcdf88f62b0 101 # if ( (defined(CMU_CTRL_HFLE) || defined(CMU_CTRL_WSHFLE) ) && (REFERENCE_FREQUENCY > 24000000) )
<> 128:9bcdf88f62b0 102 # define LEUART_REF_FREQ (REFERENCE_FREQUENCY / 4)
<> 128:9bcdf88f62b0 103 # else
<> 128:9bcdf88f62b0 104 # define LEUART_REF_FREQ (REFERENCE_FREQUENCY / 2)
<> 128:9bcdf88f62b0 105 # endif
<> 128:9bcdf88f62b0 106 #endif
<> 128:9bcdf88f62b0 107
AnnaBridge 161:aa5281ff4a02 108 /* Adjust this to change speed of RTC and LP ticker ticks */
Anna Bridge 169:a7c7b631e539 109 #define RTC_CLOCKDIV cmuClkDiv_1
AnnaBridge 161:aa5281ff4a02 110 /* Adjust this to match RTC_CLOCKDIV as integer value */
Anna Bridge 169:a7c7b631e539 111 #define RTC_CLOCKDIV_INT 1U
AnnaBridge 161:aa5281ff4a02 112 /* Adjust this to match RTC_CLOCKDIV as shift for 1 second worth of ticks.
AnnaBridge 161:aa5281ff4a02 113 * E.g. with 32768 Hz crystal and CLOCKDIV of 8, 1 second is 4096 ticks.
AnnaBridge 161:aa5281ff4a02 114 * 4096 equals 1 << 12, so RTC_FREQ_SHIFT needs to be 12. */
Anna Bridge 169:a7c7b631e539 115 #define RTC_FREQ_SHIFT 15U
AnnaBridge 161:aa5281ff4a02 116
<> 128:9bcdf88f62b0 117 #endif