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TARGET_MAX32600MBED/TARGET_Maxim/TARGET_MAX32600/device/spi_regs.h@128:9bcdf88f62b0, 2016-10-27 (annotated)

Committer:
<>
Date:
Thu Oct 27 16:45:56 2016 +0100
Revision:
128:9bcdf88f62b0
Release 128 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



2966: Add kw24 support https://github.com/ARMmbed/mbed-os/pull/2966

3068: MultiTech mDot - clean up PeripheralPins.c and add new pin names https://github.com/ARMmbed/mbed-os/pull/3068

3089: Kinetis HAL: Remove clock initialization code from serial and ticker  https://github.com/ARMmbed/mbed-os/pull/3089

2943: [NRF5] NVIC_SetVector functionality https://github.com/ARMmbed/mbed-os/pull/2943

2938: InterruptIn changes in NCS36510 HAL. https://github.com/ARMmbed/mbed-os/pull/2938

3108: Fix sleep function for NRF52. https://github.com/ARMmbed/mbed-os/pull/3108

3076: STM32F1: Correct timer master value reading https://github.com/ARMmbed/mbed-os/pull/3076

3085: Add LOWPOWERTIMER capability for NUCLEO_F303ZE https://github.com/ARMmbed/mbed-os/pull/3085

3046: [BEETLE] Update BLE stack on Beetle board https://github.com/ARMmbed/mbed-os/pull/3046

3122: [Silicon Labs] Update of Silicon Labs HAL https://github.com/ARMmbed/mbed-os/pull/3122

3022: OnSemi RAM usage fix https://github.com/ARMmbed/mbed-os/pull/3022

3121: STM32F3: Correct UART4 and UART5 defines when using DEVICE_SERIAL_ASYNCH https://github.com/ARMmbed/mbed-os/pull/3121

3142: Targets- NUMAKER_PFM_NUC47216 remove mbed 2 https://github.com/ARMmbed/mbed-os/pull/3142

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 128:9bcdf88f62b0 1 /*******************************************************************************
<> 128:9bcdf88f62b0 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
<> 128:9bcdf88f62b0 3 *
<> 128:9bcdf88f62b0 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 128:9bcdf88f62b0 5 * copy of this software and associated documentation files (the "Software"),
<> 128:9bcdf88f62b0 6 * to deal in the Software without restriction, including without limitation
<> 128:9bcdf88f62b0 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 128:9bcdf88f62b0 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 128:9bcdf88f62b0 9 * Software is furnished to do so, subject to the following conditions:
<> 128:9bcdf88f62b0 10 *
<> 128:9bcdf88f62b0 11 * The above copyright notice and this permission notice shall be included
<> 128:9bcdf88f62b0 12 * in all copies or substantial portions of the Software.
<> 128:9bcdf88f62b0 13 *
<> 128:9bcdf88f62b0 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 128:9bcdf88f62b0 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 128:9bcdf88f62b0 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 128:9bcdf88f62b0 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 128:9bcdf88f62b0 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 128:9bcdf88f62b0 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 128:9bcdf88f62b0 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 128:9bcdf88f62b0 21 *
<> 128:9bcdf88f62b0 22 * Except as contained in this notice, the name of Maxim Integrated
<> 128:9bcdf88f62b0 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 128:9bcdf88f62b0 24 * Products, Inc. Branding Policy.
<> 128:9bcdf88f62b0 25 *
<> 128:9bcdf88f62b0 26 * The mere transfer of this software does not imply any licenses
<> 128:9bcdf88f62b0 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 128:9bcdf88f62b0 28 * trademarks, maskwork rights, or any other form of intellectual
<> 128:9bcdf88f62b0 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 128:9bcdf88f62b0 30 * ownership rights.
<> 128:9bcdf88f62b0 31 *******************************************************************************
<> 128:9bcdf88f62b0 32 */
<> 128:9bcdf88f62b0 33
<> 128:9bcdf88f62b0 34 #ifndef _MXC_SPI_REGS_H
<> 128:9bcdf88f62b0 35 #define _MXC_SPI_REGS_H
<> 128:9bcdf88f62b0 36
<> 128:9bcdf88f62b0 37 #ifdef __cplusplus
<> 128:9bcdf88f62b0 38 extern "C" {
<> 128:9bcdf88f62b0 39 #endif
<> 128:9bcdf88f62b0 40
<> 128:9bcdf88f62b0 41 #include <stdint.h>
<> 128:9bcdf88f62b0 42
<> 128:9bcdf88f62b0 43 /**
<> 128:9bcdf88f62b0 44 * @file spi_regs.h
<> 128:9bcdf88f62b0 45 * @addtogroup spi SPI
<> 128:9bcdf88f62b0 46 * @{
<> 128:9bcdf88f62b0 47 */
<> 128:9bcdf88f62b0 48
<> 128:9bcdf88f62b0 49 /* Offset Register Description
<> 128:9bcdf88f62b0 50 ====== ============================================ */
<> 128:9bcdf88f62b0 51 typedef struct {
<> 128:9bcdf88f62b0 52 __IO uint32_t mstr_cfg; /* 0x0000 SPI Master Configuration Register */
<> 128:9bcdf88f62b0 53 __IO uint32_t ss_sr_polarity; /* 0x0004 Polarity Control for SS and SR Signals */
<> 128:9bcdf88f62b0 54 __IO uint32_t gen_ctrl; /* 0x0008 SPI Master General Control Register */
<> 128:9bcdf88f62b0 55 __IO uint32_t fifo_ctrl; /* 0x000C SPI Master FIFO Control Register */
<> 128:9bcdf88f62b0 56 __IO uint32_t spcl_ctrl; /* 0x0010 SPI Master Special Mode Controls */
<> 128:9bcdf88f62b0 57 __IO uint32_t intfl; /* 0x0014 SPI Master Interrupt Flags */
<> 128:9bcdf88f62b0 58 __IO uint32_t inten; /* 0x0018 SPI Master Interrupt Enable/Disable Settings */
<> 128:9bcdf88f62b0 59 __I uint32_t rsv001C; /* 0x001C Deprecated - was SPI_AHB_RETRY */
<> 128:9bcdf88f62b0 60 } mxc_spi_regs_t;
<> 128:9bcdf88f62b0 61
<> 128:9bcdf88f62b0 62 /**
<> 128:9bcdf88f62b0 63 * @brief TX FIFO register. Can do 8, 16, or 32 bit access.
<> 128:9bcdf88f62b0 64 */
<> 128:9bcdf88f62b0 65 typedef struct {
<> 128:9bcdf88f62b0 66 union {
<> 128:9bcdf88f62b0 67 __O uint8_t txfifo_8;
<> 128:9bcdf88f62b0 68 __O uint16_t txfifo_16;
<> 128:9bcdf88f62b0 69 __O uint32_t txfifo_32;
<> 128:9bcdf88f62b0 70 };
<> 128:9bcdf88f62b0 71 } mxc_spi_txfifo_regs_t;
<> 128:9bcdf88f62b0 72
<> 128:9bcdf88f62b0 73 /**
<> 128:9bcdf88f62b0 74 * @brief RX FIFO register. Can do 8, 16, or 32 bit access.
<> 128:9bcdf88f62b0 75 */
<> 128:9bcdf88f62b0 76 typedef struct {
<> 128:9bcdf88f62b0 77 union {
<> 128:9bcdf88f62b0 78 __I uint8_t rxfifo_8;
<> 128:9bcdf88f62b0 79 __I uint16_t rxfifo_16;
<> 128:9bcdf88f62b0 80 __I uint32_t rxfifo_32;
<> 128:9bcdf88f62b0 81 };
<> 128:9bcdf88f62b0 82 } mxc_spi_rxfifo_regs_t;
<> 128:9bcdf88f62b0 83
<> 128:9bcdf88f62b0 84 /*
<> 128:9bcdf88f62b0 85 Register offsets for module SPI.
<> 128:9bcdf88f62b0 86 */
<> 128:9bcdf88f62b0 87 #define MXC_R_SPI_OFFS_MSTR_CFG ((uint32_t)0x00000000UL)
<> 128:9bcdf88f62b0 88 #define MXC_R_SPI_OFFS_SS_SR_POLARITY ((uint32_t)0x00000004UL)
<> 128:9bcdf88f62b0 89 #define MXC_R_SPI_OFFS_GEN_CTRL ((uint32_t)0x00000008UL)
<> 128:9bcdf88f62b0 90 #define MXC_R_SPI_OFFS_FIFO_CTRL ((uint32_t)0x0000000CUL)
<> 128:9bcdf88f62b0 91 #define MXC_R_SPI_OFFS_SPCL_CTRL ((uint32_t)0x00000010UL)
<> 128:9bcdf88f62b0 92 #define MXC_R_SPI_OFFS_INTFL ((uint32_t)0x00000014UL)
<> 128:9bcdf88f62b0 93 #define MXC_R_SPI_OFFS_INTEN ((uint32_t)0x00000018UL)
<> 128:9bcdf88f62b0 94
<> 128:9bcdf88f62b0 95 #define MXC_R_SPI_FIFO_OFFS_TRANS ((uint32_t)0x00000000UL)
<> 128:9bcdf88f62b0 96 #define MXC_R_SPI_FIFO_OFFS_RSLTS ((uint32_t)0x00000800UL)
<> 128:9bcdf88f62b0 97
<> 128:9bcdf88f62b0 98 /*
<> 128:9bcdf88f62b0 99 Field positions and masks for module SPI.
<> 128:9bcdf88f62b0 100 */
<> 128:9bcdf88f62b0 101 #define MXC_F_SPI_MSTR_CFG_SLAVE_SEL_POS 0
<> 128:9bcdf88f62b0 102 #define MXC_F_SPI_MSTR_CFG_SLAVE_SEL ((uint32_t)(0x00000007UL << MXC_F_SPI_MSTR_CFG_SLAVE_SEL_POS))
<> 128:9bcdf88f62b0 103 #define MXC_F_SPI_MSTR_CFG_THREE_WIRE_MODE_POS 3
<> 128:9bcdf88f62b0 104 #define MXC_F_SPI_MSTR_CFG_THREE_WIRE_MODE ((uint32_t)(0x00000001UL << MXC_F_SPI_MSTR_CFG_THREE_WIRE_MODE_POS))
<> 128:9bcdf88f62b0 105 #define MXC_F_SPI_MSTR_CFG_SPI_MODE_POS 4
<> 128:9bcdf88f62b0 106 #define MXC_F_SPI_MSTR_CFG_SPI_MODE ((uint32_t)(0x00000003UL << MXC_F_SPI_MSTR_CFG_SPI_MODE_POS))
<> 128:9bcdf88f62b0 107 #define MXC_F_SPI_MSTR_CFG_PAGE_SIZE_POS 6
<> 128:9bcdf88f62b0 108 #define MXC_F_SPI_MSTR_CFG_PAGE_SIZE ((uint32_t)(0x00000003UL << MXC_F_SPI_MSTR_CFG_PAGE_SIZE_POS))
<> 128:9bcdf88f62b0 109 #define MXC_F_SPI_MSTR_CFG_SCK_HI_CLK_POS 8
<> 128:9bcdf88f62b0 110 #define MXC_F_SPI_MSTR_CFG_SCK_HI_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPI_MSTR_CFG_SCK_HI_CLK_POS))
<> 128:9bcdf88f62b0 111 #define MXC_F_SPI_MSTR_CFG_SCK_LO_CLK_POS 12
<> 128:9bcdf88f62b0 112 #define MXC_F_SPI_MSTR_CFG_SCK_LO_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPI_MSTR_CFG_SCK_LO_CLK_POS))
<> 128:9bcdf88f62b0 113 #define MXC_F_SPI_MSTR_CFG_ACT_DELAY_POS 16
<> 128:9bcdf88f62b0 114 #define MXC_F_SPI_MSTR_CFG_ACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPI_MSTR_CFG_ACT_DELAY_POS))
<> 128:9bcdf88f62b0 115 #define MXC_F_SPI_MSTR_CFG_INACT_DELAY_POS 18
<> 128:9bcdf88f62b0 116 #define MXC_F_SPI_MSTR_CFG_INACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPI_MSTR_CFG_INACT_DELAY_POS))
<> 128:9bcdf88f62b0 117 #define MXC_F_SPI_MSTR_CFG_ALT_SCK_HI_CLK_POS 20
<> 128:9bcdf88f62b0 118 #define MXC_F_SPI_MSTR_CFG_ALT_SCK_HI_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPI_MSTR_CFG_ALT_SCK_HI_CLK_POS))
<> 128:9bcdf88f62b0 119 #define MXC_F_SPI_MSTR_CFG_ALT_SCK_LO_CLK_POS 24
<> 128:9bcdf88f62b0 120 #define MXC_F_SPI_MSTR_CFG_ALT_SCK_LO_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPI_MSTR_CFG_ALT_SCK_LO_CLK_POS))
<> 128:9bcdf88f62b0 121
<> 128:9bcdf88f62b0 122 #define MXC_V_SPI_MSTR_CFG_PAGE_SIZE_4B ((uint32_t)0x00000000UL)
<> 128:9bcdf88f62b0 123 #define MXC_V_SPI_MSTR_CFG_PAGE_SIZE_8B ((uint32_t)0x00000001UL)
<> 128:9bcdf88f62b0 124 #define MXC_V_SPI_MSTR_CFG_PAGE_SIZE_16B ((uint32_t)0x00000002UL)
<> 128:9bcdf88f62b0 125 #define MXC_V_SPI_MSTR_CFG_PAGE_SIZE_32B ((uint32_t)0x00000003UL)
<> 128:9bcdf88f62b0 126
<> 128:9bcdf88f62b0 127 #define MXC_S_SPI_MSTR_CFG_PAGE_4B (MXC_V_SPI_MSTR_CFG_PAGE_SIZE_4B << MXC_F_SPI_MSTR_CFG_PAGE_SIZE_POS)
<> 128:9bcdf88f62b0 128 #define MXC_S_SPI_MSTR_CFG_PAGE_8B (MXC_V_SPI_MSTR_CFG_PAGE_SIZE_8B << MXC_F_SPI_MSTR_CFG_PAGE_SIZE_POS)
<> 128:9bcdf88f62b0 129 #define MXC_S_SPI_MSTR_CFG_PAGE_16B (MXC_V_SPI_MSTR_CFG_PAGE_SIZE_16B << MXC_F_SPI_MSTR_CFG_PAGE_SIZE_POS)
<> 128:9bcdf88f62b0 130 #define MXC_S_SPI_MSTR_CFG_PAGE_32B (MXC_V_SPI_MSTR_CFG_PAGE_SIZE_32B << MXC_F_SPI_MSTR_CFG_PAGE_SIZE_POS)
<> 128:9bcdf88f62b0 131
<> 128:9bcdf88f62b0 132 #define MXC_F_SPI_SS_SR_POLARITY_SS_POLARITY_POS 0
<> 128:9bcdf88f62b0 133 #define MXC_F_SPI_SS_SR_POLARITY_SS_POLARITY ((uint32_t)(0x000000FFUL << MXC_F_SPI_SS_SR_POLARITY_SS_POLARITY_POS))
<> 128:9bcdf88f62b0 134 #define MXC_F_SPI_SS_SR_POLARITY_FC_POLARITY_POS 8
<> 128:9bcdf88f62b0 135 #define MXC_F_SPI_SS_SR_POLARITY_FC_POLARITY ((uint32_t)(0x000000FFUL << MXC_F_SPI_SS_SR_POLARITY_FC_POLARITY_POS))
<> 128:9bcdf88f62b0 136
<> 128:9bcdf88f62b0 137 #define MXC_F_SPI_GEN_CTRL_SPI_MSTR_EN_POS 0
<> 128:9bcdf88f62b0 138 #define MXC_F_SPI_GEN_CTRL_SPI_MSTR_EN ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_SPI_MSTR_EN_POS))
<> 128:9bcdf88f62b0 139 #define MXC_F_SPI_GEN_CTRL_TX_FIFO_EN_POS 1
<> 128:9bcdf88f62b0 140 #define MXC_F_SPI_GEN_CTRL_TX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_TX_FIFO_EN_POS))
<> 128:9bcdf88f62b0 141 #define MXC_F_SPI_GEN_CTRL_RX_FIFO_EN_POS 2
<> 128:9bcdf88f62b0 142 #define MXC_F_SPI_GEN_CTRL_RX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_RX_FIFO_EN_POS))
<> 128:9bcdf88f62b0 143 #define MXC_F_SPI_GEN_CTRL_BIT_BANG_MODE_POS 3
<> 128:9bcdf88f62b0 144 #define MXC_F_SPI_GEN_CTRL_BIT_BANG_MODE ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_BIT_BANG_MODE_POS))
<> 128:9bcdf88f62b0 145 #define MXC_F_SPI_GEN_CTRL_BB_SS_IN_OUT_POS 4
<> 128:9bcdf88f62b0 146 #define MXC_F_SPI_GEN_CTRL_BB_SS_IN_OUT ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_BB_SS_IN_OUT_POS))
<> 128:9bcdf88f62b0 147 #define MXC_F_SPI_GEN_CTRL_BB_SR_IN_POS 5
<> 128:9bcdf88f62b0 148 #define MXC_F_SPI_GEN_CTRL_BB_SR_IN ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_BB_SR_IN_POS))
<> 128:9bcdf88f62b0 149 #define MXC_F_SPI_GEN_CTRL_BB_SCK_IN_OUT_POS 6
<> 128:9bcdf88f62b0 150 #define MXC_F_SPI_GEN_CTRL_BB_SCK_IN_OUT ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_BB_SCK_IN_OUT_POS))
<> 128:9bcdf88f62b0 151 #define MXC_F_SPI_GEN_CTRL_BB_SDIO_IN_POS 8
<> 128:9bcdf88f62b0 152 #define MXC_F_SPI_GEN_CTRL_BB_SDIO_IN ((uint32_t)(0x0000000FUL << MXC_F_SPI_GEN_CTRL_BB_SDIO_IN_POS))
<> 128:9bcdf88f62b0 153 #define MXC_F_SPI_GEN_CTRL_BB_SDIO_OUT_POS 12
<> 128:9bcdf88f62b0 154 #define MXC_F_SPI_GEN_CTRL_BB_SDIO_OUT ((uint32_t)(0x0000000FUL << MXC_F_SPI_GEN_CTRL_BB_SDIO_OUT_POS))
<> 128:9bcdf88f62b0 155 #define MXC_F_SPI_GEN_CTRL_BB_SDIO_DR_EN_POS 16
<> 128:9bcdf88f62b0 156 #define MXC_F_SPI_GEN_CTRL_BB_SDIO_DR_EN ((uint32_t)(0x0000000FUL << MXC_F_SPI_GEN_CTRL_BB_SDIO_DR_EN_POS))
<> 128:9bcdf88f62b0 157
<> 128:9bcdf88f62b0 158 #define MXC_F_SPI_FIFO_CTRL_TX_FIFO_AE_LVL_POS 0
<> 128:9bcdf88f62b0 159 #define MXC_F_SPI_FIFO_CTRL_TX_FIFO_AE_LVL ((uint32_t)(0x0000000FUL << MXC_F_SPI_FIFO_CTRL_TX_FIFO_AE_LVL_POS))
<> 128:9bcdf88f62b0 160 #define MXC_F_SPI_FIFO_CTRL_TX_FIFO_USED_POS 8
<> 128:9bcdf88f62b0 161 #define MXC_F_SPI_FIFO_CTRL_TX_FIFO_USED ((uint32_t)(0x0000001FUL << MXC_F_SPI_FIFO_CTRL_TX_FIFO_USED_POS))
<> 128:9bcdf88f62b0 162 #define MXC_F_SPI_FIFO_CTRL_RX_FIFO_AF_LVL_POS 16
<> 128:9bcdf88f62b0 163 #define MXC_F_SPI_FIFO_CTRL_RX_FIFO_AF_LVL ((uint32_t)(0x0000001FUL << MXC_F_SPI_FIFO_CTRL_RX_FIFO_AF_LVL_POS))
<> 128:9bcdf88f62b0 164 #define MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED_POS 24
<> 128:9bcdf88f62b0 165 #define MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED ((uint32_t)(0x0000003FUL << MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED_POS))
<> 128:9bcdf88f62b0 166
<> 128:9bcdf88f62b0 167 #define MXC_F_SPI_SPCL_CTRL_SS_SAMPLE_MODE_POS 0
<> 128:9bcdf88f62b0 168 #define MXC_F_SPI_SPCL_CTRL_SS_SAMPLE_MODE ((uint32_t)(0x00000001UL << MXC_F_SPI_SPCL_CTRL_SS_SAMPLE_MODE_POS))
<> 128:9bcdf88f62b0 169 #define MXC_F_SPI_SPCL_CTRL_MISO_FC_EN_POS 1
<> 128:9bcdf88f62b0 170 #define MXC_F_SPI_SPCL_CTRL_MISO_FC_EN ((uint32_t)(0x00000001UL << MXC_F_SPI_SPCL_CTRL_MISO_FC_EN_POS))
<> 128:9bcdf88f62b0 171 #define MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_OUT_POS 4
<> 128:9bcdf88f62b0 172 #define MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_OUT ((uint32_t)(0x0000000FUL << MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_OUT_POS))
<> 128:9bcdf88f62b0 173 #define MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_DR_EN_POS 8
<> 128:9bcdf88f62b0 174 #define MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_DR_EN ((uint32_t)(0x0000000FUL << MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_DR_EN_POS))
<> 128:9bcdf88f62b0 175
<> 128:9bcdf88f62b0 176 #define MXC_F_SPI_INTFL_TX_STALLED_POS 0
<> 128:9bcdf88f62b0 177 #define MXC_F_SPI_INTFL_TX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_TX_STALLED_POS))
<> 128:9bcdf88f62b0 178 #define MXC_F_SPI_INTFL_RX_STALLED_POS 1
<> 128:9bcdf88f62b0 179 #define MXC_F_SPI_INTFL_RX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_RX_STALLED_POS))
<> 128:9bcdf88f62b0 180 #define MXC_F_SPI_INTFL_TX_READY_POS 2
<> 128:9bcdf88f62b0 181 #define MXC_F_SPI_INTFL_TX_READY ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_TX_READY_POS))
<> 128:9bcdf88f62b0 182 #define MXC_F_SPI_INTFL_RX_DONE_POS 3
<> 128:9bcdf88f62b0 183 #define MXC_F_SPI_INTFL_RX_DONE ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_RX_DONE_POS))
<> 128:9bcdf88f62b0 184 #define MXC_F_SPI_INTFL_TX_FIFO_AE_POS 4
<> 128:9bcdf88f62b0 185 #define MXC_F_SPI_INTFL_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_TX_FIFO_AE_POS))
<> 128:9bcdf88f62b0 186 #define MXC_F_SPI_INTFL_RX_FIFO_AF_POS 5
<> 128:9bcdf88f62b0 187 #define MXC_F_SPI_INTFL_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_RX_FIFO_AF_POS))
<> 128:9bcdf88f62b0 188
<> 128:9bcdf88f62b0 189 #define MXC_F_SPI_INTEN_TX_STALLED_POS 0
<> 128:9bcdf88f62b0 190 #define MXC_F_SPI_INTEN_TX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_TX_STALLED_POS))
<> 128:9bcdf88f62b0 191 #define MXC_F_SPI_INTEN_RX_STALLED_POS 1
<> 128:9bcdf88f62b0 192 #define MXC_F_SPI_INTEN_RX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_RX_STALLED_POS))
<> 128:9bcdf88f62b0 193 #define MXC_F_SPI_INTEN_TX_READY_POS 2
<> 128:9bcdf88f62b0 194 #define MXC_F_SPI_INTEN_TX_READY ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_TX_READY_POS))
<> 128:9bcdf88f62b0 195 #define MXC_F_SPI_INTEN_RX_DONE_POS 3
<> 128:9bcdf88f62b0 196 #define MXC_F_SPI_INTEN_RX_DONE ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_RX_DONE_POS))
<> 128:9bcdf88f62b0 197 #define MXC_F_SPI_INTEN_TX_FIFO_AE_POS 4
<> 128:9bcdf88f62b0 198 #define MXC_F_SPI_INTEN_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_TX_FIFO_AE_POS))
<> 128:9bcdf88f62b0 199 #define MXC_F_SPI_INTEN_RX_FIFO_AF_POS 5
<> 128:9bcdf88f62b0 200 #define MXC_F_SPI_INTEN_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_RX_FIFO_AF_POS))
<> 128:9bcdf88f62b0 201
<> 128:9bcdf88f62b0 202 #define MXC_F_SPI_FIFO_DIR_POS 0
<> 128:9bcdf88f62b0 203 #define MXC_F_SPI_FIFO_DIR ((uint32_t)(0x00000003UL << MXC_F_SPI_FIFO_DIR_POS))
<> 128:9bcdf88f62b0 204 #define MXC_F_SPI_FIFO_UNIT_POS 2
<> 128:9bcdf88f62b0 205 #define MXC_F_SPI_FIFO_UNIT ((uint32_t)(0x00000003UL << MXC_F_SPI_FIFO_UNIT_POS))
<> 128:9bcdf88f62b0 206 #define MXC_F_SPI_FIFO_SIZE_POS 4
<> 128:9bcdf88f62b0 207 #define MXC_F_SPI_FIFO_SIZE ((uint32_t)(0x0000000FUL << MXC_F_SPI_FIFO_SIZE_POS))
<> 128:9bcdf88f62b0 208 #define MXC_F_SPI_FIFO_WIDTH_POS 9
<> 128:9bcdf88f62b0 209 #define MXC_F_SPI_FIFO_WIDTH ((uint32_t)(0x00000001UL << MXC_F_SPI_FIFO_WIDTH_POS))
<> 128:9bcdf88f62b0 210 #define MXC_F_SPI_FIFO_ALT_POS 11
<> 128:9bcdf88f62b0 211 #define MXC_F_SPI_FIFO_ALT ((uint32_t)(0x00000001UL << MXC_F_SPI_FIFO_ALT_POS))
<> 128:9bcdf88f62b0 212 #define MXC_F_SPI_FIFO_FLOW_POS 12
<> 128:9bcdf88f62b0 213 #define MXC_F_SPI_FIFO_FLOW ((uint32_t)(0x00000001UL << MXC_F_SPI_FIFO_FLOW_POS))
<> 128:9bcdf88f62b0 214 #define MXC_F_SPI_FIFO_DASS_POS 13
<> 128:9bcdf88f62b0 215 #define MXC_F_SPI_FIFO_DASS ((uint32_t)(0x00000001UL << MXC_F_SPI_FIFO_DASS_POS))
<> 128:9bcdf88f62b0 216
<> 128:9bcdf88f62b0 217 #ifdef __cplusplus
<> 128:9bcdf88f62b0 218 }
<> 128:9bcdf88f62b0 219 #endif
<> 128:9bcdf88f62b0 220
<> 128:9bcdf88f62b0 221 /**
<> 128:9bcdf88f62b0 222 * @}
<> 128:9bcdf88f62b0 223 */
<> 128:9bcdf88f62b0 224
<> 128:9bcdf88f62b0 225 #endif /* _MXC_SPI_REGS_H */