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Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

TARGET_DISCO_L053C8/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rcc.h@128:9bcdf88f62b0, 2016-10-27 (annotated)

Committer:
<>
Date:
Thu Oct 27 16:45:56 2016 +0100
Revision:
128:9bcdf88f62b0
Parent:
TARGET_NUCLEO_L053R8/stm32l0xx_hal_rcc.h@119:aae6fcc7d9bb
Child:
130:d75b3fe1f5cb
Release 128 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



2966: Add kw24 support https://github.com/ARMmbed/mbed-os/pull/2966

3068: MultiTech mDot - clean up PeripheralPins.c and add new pin names https://github.com/ARMmbed/mbed-os/pull/3068

3089: Kinetis HAL: Remove clock initialization code from serial and ticker  https://github.com/ARMmbed/mbed-os/pull/3089

2943: [NRF5] NVIC_SetVector functionality https://github.com/ARMmbed/mbed-os/pull/2943

2938: InterruptIn changes in NCS36510 HAL. https://github.com/ARMmbed/mbed-os/pull/2938

3108: Fix sleep function for NRF52. https://github.com/ARMmbed/mbed-os/pull/3108

3076: STM32F1: Correct timer master value reading https://github.com/ARMmbed/mbed-os/pull/3076

3085: Add LOWPOWERTIMER capability for NUCLEO_F303ZE https://github.com/ARMmbed/mbed-os/pull/3085

3046: [BEETLE] Update BLE stack on Beetle board https://github.com/ARMmbed/mbed-os/pull/3046

3122: [Silicon Labs] Update of Silicon Labs HAL https://github.com/ARMmbed/mbed-os/pull/3122

3022: OnSemi RAM usage fix https://github.com/ARMmbed/mbed-os/pull/3022

3121: STM32F3: Correct UART4 and UART5 defines when using DEVICE_SERIAL_ASYNCH https://github.com/ARMmbed/mbed-os/pull/3121

3142: Targets- NUMAKER_PFM_NUC47216 remove mbed 2 https://github.com/ARMmbed/mbed-os/pull/3142

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 84:0b3ab51c8877 1 /**
bogdanm 84:0b3ab51c8877 2 ******************************************************************************
bogdanm 84:0b3ab51c8877 3 * @file stm32l0xx_hal_rcc.h
bogdanm 84:0b3ab51c8877 4 * @author MCD Application Team
Kojto 119:aae6fcc7d9bb 5 * @version V1.5.0
Kojto 119:aae6fcc7d9bb 6 * @date 8-January-2016
bogdanm 84:0b3ab51c8877 7 * @brief Header file of RCC HAL module.
bogdanm 84:0b3ab51c8877 8 ******************************************************************************
bogdanm 84:0b3ab51c8877 9 * @attention
bogdanm 84:0b3ab51c8877 10 *
Kojto 119:aae6fcc7d9bb 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
bogdanm 84:0b3ab51c8877 12 *
bogdanm 84:0b3ab51c8877 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 84:0b3ab51c8877 14 * are permitted provided that the following conditions are met:
bogdanm 84:0b3ab51c8877 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 84:0b3ab51c8877 16 * this list of conditions and the following disclaimer.
bogdanm 84:0b3ab51c8877 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 84:0b3ab51c8877 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 84:0b3ab51c8877 19 * and/or other materials provided with the distribution.
bogdanm 84:0b3ab51c8877 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 84:0b3ab51c8877 21 * may be used to endorse or promote products derived from this software
bogdanm 84:0b3ab51c8877 22 * without specific prior written permission.
bogdanm 84:0b3ab51c8877 23 *
bogdanm 84:0b3ab51c8877 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 84:0b3ab51c8877 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 84:0b3ab51c8877 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 84:0b3ab51c8877 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 84:0b3ab51c8877 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 84:0b3ab51c8877 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 84:0b3ab51c8877 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 84:0b3ab51c8877 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 84:0b3ab51c8877 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 84:0b3ab51c8877 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 84:0b3ab51c8877 34 *
bogdanm 84:0b3ab51c8877 35 ******************************************************************************
bogdanm 84:0b3ab51c8877 36 */
bogdanm 84:0b3ab51c8877 37
bogdanm 84:0b3ab51c8877 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 84:0b3ab51c8877 39 #ifndef __STM32L0xx_HAL_RCC_H
bogdanm 84:0b3ab51c8877 40 #define __STM32L0xx_HAL_RCC_H
bogdanm 84:0b3ab51c8877 41
bogdanm 84:0b3ab51c8877 42 #ifdef __cplusplus
bogdanm 84:0b3ab51c8877 43 extern "C" {
bogdanm 84:0b3ab51c8877 44 #endif
bogdanm 84:0b3ab51c8877 45
bogdanm 84:0b3ab51c8877 46 /* Includes ------------------------------------------------------------------*/
bogdanm 84:0b3ab51c8877 47 #include "stm32l0xx_hal_def.h"
bogdanm 84:0b3ab51c8877 48
bogdanm 84:0b3ab51c8877 49 /** @addtogroup STM32L0xx_HAL_Driver
bogdanm 84:0b3ab51c8877 50 * @{
bogdanm 84:0b3ab51c8877 51 */
bogdanm 84:0b3ab51c8877 52
Kojto 96:487b796308b0 53 /** @defgroup RCC RCC
bogdanm 84:0b3ab51c8877 54 * @{
bogdanm 84:0b3ab51c8877 55 */
bogdanm 84:0b3ab51c8877 56
Kojto 119:aae6fcc7d9bb 57 /** @defgroup RCC_Exported_Types RCC Exported Types
Kojto 119:aae6fcc7d9bb 58 * @{
Kojto 119:aae6fcc7d9bb 59 */
bogdanm 84:0b3ab51c8877 60
bogdanm 84:0b3ab51c8877 61 /**
bogdanm 84:0b3ab51c8877 62 * @brief RCC PLL configuration structure definition
bogdanm 84:0b3ab51c8877 63 */
bogdanm 84:0b3ab51c8877 64 typedef struct
bogdanm 84:0b3ab51c8877 65 {
bogdanm 84:0b3ab51c8877 66 uint32_t PLLState; /*!< The new state of the PLL.
bogdanm 84:0b3ab51c8877 67 This parameter can be a value of @ref RCC_PLL_Config */
bogdanm 84:0b3ab51c8877 68
bogdanm 84:0b3ab51c8877 69 uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
bogdanm 84:0b3ab51c8877 70 This parameter must be a value of @ref RCC_PLL_Clock_Source */
bogdanm 84:0b3ab51c8877 71
bogdanm 84:0b3ab51c8877 72 uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO output clock
bogdanm 92:4fc01daae5a5 73 This parameter must of @ref RCC_PLLMultiplication_Factor */
bogdanm 84:0b3ab51c8877 74
bogdanm 84:0b3ab51c8877 75 uint32_t PLLDIV; /*!< PLLDIV: Division factor for main system clock (SYSCLK)
bogdanm 84:0b3ab51c8877 76 This parameter must be a value of @ref RCC_PLLDivider_Factor */
bogdanm 84:0b3ab51c8877 77
bogdanm 84:0b3ab51c8877 78 }RCC_PLLInitTypeDef;
bogdanm 84:0b3ab51c8877 79
bogdanm 84:0b3ab51c8877 80 /**
bogdanm 84:0b3ab51c8877 81 * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
bogdanm 84:0b3ab51c8877 82 */
bogdanm 84:0b3ab51c8877 83 typedef struct
bogdanm 84:0b3ab51c8877 84 {
bogdanm 84:0b3ab51c8877 85 uint32_t OscillatorType; /*!< The oscillators to be configured.
bogdanm 84:0b3ab51c8877 86 This parameter can be a value of @ref RCC_Oscillator_Type */
bogdanm 84:0b3ab51c8877 87
bogdanm 84:0b3ab51c8877 88 uint32_t HSEState; /*!< The new state of the HSE.
bogdanm 84:0b3ab51c8877 89 This parameter can be a value of @ref RCC_HSE_Config */
bogdanm 84:0b3ab51c8877 90
bogdanm 84:0b3ab51c8877 91 uint32_t LSEState; /*!< The new state of the LSE.
bogdanm 84:0b3ab51c8877 92 This parameter can be a value of @ref RCC_LSE_Config */
bogdanm 84:0b3ab51c8877 93
bogdanm 84:0b3ab51c8877 94 uint32_t HSIState; /*!< The new state of the HSI.
bogdanm 84:0b3ab51c8877 95 This parameter can be a value of @ref RCC_HSI_Config */
bogdanm 84:0b3ab51c8877 96
bogdanm 84:0b3ab51c8877 97 uint32_t HSICalibrationValue; /*!< The calibration trimming value.
bogdanm 84:0b3ab51c8877 98 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
bogdanm 84:0b3ab51c8877 99
bogdanm 84:0b3ab51c8877 100 uint32_t LSIState; /*!< The new state of the LSI.
bogdanm 84:0b3ab51c8877 101 This parameter can be a value of @ref RCC_LSI_Config */
bogdanm 84:0b3ab51c8877 102
Kojto 119:aae6fcc7d9bb 103 #if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) && \
Kojto 119:aae6fcc7d9bb 104 !defined (STM32L011xx) && !defined (STM32L021xx)
bogdanm 84:0b3ab51c8877 105 uint32_t HSI48State; /*!< The new state of the HSI48.
bogdanm 84:0b3ab51c8877 106 This parameter can be a value of @ref RCC_HSI48_Config */
Kojto 96:487b796308b0 107 #endif
bogdanm 84:0b3ab51c8877 108
bogdanm 84:0b3ab51c8877 109 uint32_t MSIState; /*!< The new state of the MSI.
bogdanm 84:0b3ab51c8877 110 This parameter can be a value of @ref RCC_MSI_Config */
bogdanm 84:0b3ab51c8877 111
bogdanm 84:0b3ab51c8877 112 uint32_t MSICalibrationValue; /*!< The calibration trimming value.
bogdanm 84:0b3ab51c8877 113 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
bogdanm 84:0b3ab51c8877 114
bogdanm 84:0b3ab51c8877 115 uint32_t MSIClockRange; /*!< The MSI frequency range.
bogdanm 84:0b3ab51c8877 116 This parameter can be a value of @ref RCC_MSI_Clock_Range */
bogdanm 84:0b3ab51c8877 117
bogdanm 84:0b3ab51c8877 118 RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
bogdanm 84:0b3ab51c8877 119
bogdanm 84:0b3ab51c8877 120 }RCC_OscInitTypeDef;
bogdanm 84:0b3ab51c8877 121
bogdanm 84:0b3ab51c8877 122 /**
bogdanm 84:0b3ab51c8877 123 * @brief RCC System, AHB and APB busses clock configuration structure definition
bogdanm 84:0b3ab51c8877 124 */
bogdanm 84:0b3ab51c8877 125 typedef struct
bogdanm 84:0b3ab51c8877 126 {
bogdanm 84:0b3ab51c8877 127 uint32_t ClockType; /*!< The clock to be configured.
bogdanm 84:0b3ab51c8877 128 This parameter can be a value of @ref RCC_System_Clock_Type */
bogdanm 84:0b3ab51c8877 129
bogdanm 84:0b3ab51c8877 130 uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
bogdanm 84:0b3ab51c8877 131 This parameter can be a value of @ref RCC_System_Clock_Source */
bogdanm 84:0b3ab51c8877 132
bogdanm 84:0b3ab51c8877 133 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
bogdanm 84:0b3ab51c8877 134 This parameter can be a value of @ref RCC_AHB_Clock_Source */
bogdanm 84:0b3ab51c8877 135
bogdanm 84:0b3ab51c8877 136 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
bogdanm 84:0b3ab51c8877 137 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
bogdanm 84:0b3ab51c8877 138
bogdanm 84:0b3ab51c8877 139 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
bogdanm 84:0b3ab51c8877 140 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
bogdanm 84:0b3ab51c8877 141
bogdanm 84:0b3ab51c8877 142 }RCC_ClkInitTypeDef;
bogdanm 84:0b3ab51c8877 143
Kojto 119:aae6fcc7d9bb 144 /**
Kojto 119:aae6fcc7d9bb 145 * @}
Kojto 119:aae6fcc7d9bb 146 */
Kojto 119:aae6fcc7d9bb 147
Kojto 119:aae6fcc7d9bb 148 /* Private constants --------------------------------------------------------*/
Kojto 119:aae6fcc7d9bb 149 /** @addtogroup RCC_Private
bogdanm 84:0b3ab51c8877 150 * @brief RCC registers bit address in the alias region
bogdanm 84:0b3ab51c8877 151 * @{
bogdanm 84:0b3ab51c8877 152 */
bogdanm 84:0b3ab51c8877 153 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
bogdanm 84:0b3ab51c8877 154 /* --- CR Register ---*/
bogdanm 84:0b3ab51c8877 155 /* Alias word address of HSION bit */
bogdanm 84:0b3ab51c8877 156 #define RCC_CR_OFFSET (RCC_OFFSET + 0x00)
bogdanm 84:0b3ab51c8877 157 /* --- CFGR Register ---*/
bogdanm 84:0b3ab51c8877 158 /* Alias word address of I2SSRC bit */
bogdanm 84:0b3ab51c8877 159 #define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08)
bogdanm 84:0b3ab51c8877 160 /* --- CSR Register ---*/
bogdanm 84:0b3ab51c8877 161 #define RCC_CSR_OFFSET (RCC_OFFSET + 0x74)
bogdanm 84:0b3ab51c8877 162
bogdanm 84:0b3ab51c8877 163 /* CR register byte 3 (Bits[23:16]) base address */
Kojto 96:487b796308b0 164 #define RCC_CR_BYTE2_ADDRESS ((uint32_t)0x40023802)
bogdanm 84:0b3ab51c8877 165
bogdanm 84:0b3ab51c8877 166 /* CIER register byte 0 (Bits[0:8]) base address */
bogdanm 84:0b3ab51c8877 167 #define CIER_BYTE0_ADDRESS ((uint32_t)(RCC_BASE + 0x10 + 0x00))
bogdanm 84:0b3ab51c8877 168
bogdanm 84:0b3ab51c8877 169 /**
bogdanm 84:0b3ab51c8877 170 * @}
bogdanm 84:0b3ab51c8877 171 */
Kojto 119:aae6fcc7d9bb 172
Kojto 119:aae6fcc7d9bb 173 /* Exported constants --------------------------------------------------------*/
Kojto 96:487b796308b0 174 /** @defgroup RCC_Exported_Constants RCC Exported Constants
Kojto 96:487b796308b0 175 * @{
Kojto 96:487b796308b0 176 */
Kojto 96:487b796308b0 177
Kojto 119:aae6fcc7d9bb 178 /** @defgroup RCC_Timeout_Value Timeout Values
bogdanm 84:0b3ab51c8877 179 * @{
bogdanm 84:0b3ab51c8877 180 */
Kojto 119:aae6fcc7d9bb 181 #define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
Kojto 119:aae6fcc7d9bb 182 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
Kojto 119:aae6fcc7d9bb 183 #define RCC_HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
Kojto 119:aae6fcc7d9bb 184 /**
Kojto 119:aae6fcc7d9bb 185 * @}
Kojto 119:aae6fcc7d9bb 186 */
Kojto 119:aae6fcc7d9bb 187
Kojto 119:aae6fcc7d9bb 188 /** @defgroup RCC_Oscillator_Type Oscillator Type
Kojto 119:aae6fcc7d9bb 189 * @{
Kojto 119:aae6fcc7d9bb 190 */
Kojto 119:aae6fcc7d9bb 191 #define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000) /*!< Oscillator configuration unchanged */
Kojto 119:aae6fcc7d9bb 192 #define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001) /*!< HSE to configure */
Kojto 119:aae6fcc7d9bb 193 #define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002) /*!< HSI to configure */
Kojto 119:aae6fcc7d9bb 194 #define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004) /*!< LSE to configure */
Kojto 119:aae6fcc7d9bb 195 #define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008) /*!< LSI to configure */
Kojto 119:aae6fcc7d9bb 196 #define RCC_OSCILLATORTYPE_MSI ((uint32_t)0x00000010) /*!< MSI to configure */
Kojto 96:487b796308b0 197 #if !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
bogdanm 84:0b3ab51c8877 198 #define RCC_OSCILLATORTYPE_HSI48 ((uint32_t)0x00000020)
Kojto 96:487b796308b0 199 #endif /* !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) */
bogdanm 92:4fc01daae5a5 200
bogdanm 84:0b3ab51c8877 201 /**
bogdanm 84:0b3ab51c8877 202 * @}
bogdanm 84:0b3ab51c8877 203 */
bogdanm 84:0b3ab51c8877 204
Kojto 96:487b796308b0 205 /** @defgroup RCC_HSE_Config RCC HSE Config
bogdanm 84:0b3ab51c8877 206 * @{
bogdanm 84:0b3ab51c8877 207 */
bogdanm 84:0b3ab51c8877 208 #define RCC_HSE_OFF ((uint32_t)0x00000000)
bogdanm 84:0b3ab51c8877 209 #define RCC_HSE_ON RCC_CR_HSEON
bogdanm 84:0b3ab51c8877 210 #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))
bogdanm 84:0b3ab51c8877 211
bogdanm 84:0b3ab51c8877 212 /**
bogdanm 84:0b3ab51c8877 213 * @}
bogdanm 84:0b3ab51c8877 214 */
bogdanm 84:0b3ab51c8877 215
Kojto 96:487b796308b0 216 /** @defgroup RCC_LSE_Config RCC LSE Config
bogdanm 84:0b3ab51c8877 217 * @{
bogdanm 84:0b3ab51c8877 218 */
bogdanm 84:0b3ab51c8877 219 #define RCC_LSE_OFF ((uint32_t)0x00000000)
bogdanm 84:0b3ab51c8877 220 #define RCC_LSE_ON RCC_CSR_LSEON
bogdanm 84:0b3ab51c8877 221 #define RCC_LSE_BYPASS ((uint32_t)(RCC_CSR_LSEBYP | RCC_CSR_LSEON))
bogdanm 84:0b3ab51c8877 222
bogdanm 84:0b3ab51c8877 223 /**
bogdanm 84:0b3ab51c8877 224 * @}
bogdanm 84:0b3ab51c8877 225 */
bogdanm 84:0b3ab51c8877 226
Kojto 96:487b796308b0 227
bogdanm 84:0b3ab51c8877 228
Kojto 96:487b796308b0 229 /** @defgroup RCC_LSI_Config RCC LSI Config
bogdanm 84:0b3ab51c8877 230 * @{
bogdanm 84:0b3ab51c8877 231 */
bogdanm 84:0b3ab51c8877 232 #define RCC_LSI_OFF ((uint8_t)0x00)
bogdanm 84:0b3ab51c8877 233 #define RCC_LSI_ON ((uint8_t)0x01)
bogdanm 84:0b3ab51c8877 234
Kojto 96:487b796308b0 235 #define RCC_MSICALIBRATION_DEFAULT ((uint32_t)0) /* Default MSI calibration trimming value */
Kojto 96:487b796308b0 236
bogdanm 84:0b3ab51c8877 237 /**
bogdanm 84:0b3ab51c8877 238 * @}
bogdanm 84:0b3ab51c8877 239 */
bogdanm 84:0b3ab51c8877 240
bogdanm 84:0b3ab51c8877 241
Kojto 96:487b796308b0 242 /** @defgroup RCC_MSI_Config RCC MSI Config
bogdanm 84:0b3ab51c8877 243 * @{
bogdanm 84:0b3ab51c8877 244 */
bogdanm 84:0b3ab51c8877 245 #define RCC_MSI_OFF ((uint8_t)0x00)
bogdanm 84:0b3ab51c8877 246 #define RCC_MSI_ON ((uint8_t)0x01)
bogdanm 84:0b3ab51c8877 247
Kojto 96:487b796308b0 248 #define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */
Kojto 96:487b796308b0 249
bogdanm 84:0b3ab51c8877 250 /**
bogdanm 84:0b3ab51c8877 251 * @}
bogdanm 84:0b3ab51c8877 252 */
bogdanm 84:0b3ab51c8877 253
Kojto 96:487b796308b0 254 #if !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
Kojto 119:aae6fcc7d9bb 255 /** @defgroup RCC_HSI48_Config RCC HSI48 Configuration
bogdanm 84:0b3ab51c8877 256 * @{
bogdanm 84:0b3ab51c8877 257 */
bogdanm 84:0b3ab51c8877 258 #define RCC_HSI48_OFF ((uint8_t)0x00)
bogdanm 84:0b3ab51c8877 259 #define RCC_HSI48_ON ((uint8_t)0x01)
bogdanm 84:0b3ab51c8877 260
bogdanm 84:0b3ab51c8877 261 /**
bogdanm 84:0b3ab51c8877 262 * @}
bogdanm 84:0b3ab51c8877 263 */
Kojto 96:487b796308b0 264 #endif /* !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) */
bogdanm 84:0b3ab51c8877 265
Kojto 96:487b796308b0 266 /** @defgroup RCC_PLL_Config RCC PLL Config
bogdanm 84:0b3ab51c8877 267 * @{
bogdanm 84:0b3ab51c8877 268 */
bogdanm 84:0b3ab51c8877 269 #define RCC_PLL_NONE ((uint8_t)0x00)
bogdanm 84:0b3ab51c8877 270 #define RCC_PLL_OFF ((uint8_t)0x01)
bogdanm 84:0b3ab51c8877 271 #define RCC_PLL_ON ((uint8_t)0x02)
bogdanm 84:0b3ab51c8877 272
bogdanm 84:0b3ab51c8877 273 /**
bogdanm 84:0b3ab51c8877 274 * @}
bogdanm 84:0b3ab51c8877 275 */
bogdanm 84:0b3ab51c8877 276
Kojto 119:aae6fcc7d9bb 277 /** @defgroup RCC_PLL_Clock_Source RCC PLL Clock Source
bogdanm 84:0b3ab51c8877 278 * @{
bogdanm 84:0b3ab51c8877 279 */
bogdanm 84:0b3ab51c8877 280 #define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI
bogdanm 84:0b3ab51c8877 281 #define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE
bogdanm 84:0b3ab51c8877 282
bogdanm 84:0b3ab51c8877 283
bogdanm 84:0b3ab51c8877 284 /**
bogdanm 84:0b3ab51c8877 285 * @}
bogdanm 84:0b3ab51c8877 286 */
bogdanm 84:0b3ab51c8877 287
Kojto 96:487b796308b0 288 /** @defgroup RCC_PLLMultiplication_Factor RCC PLL Multipliers
bogdanm 84:0b3ab51c8877 289 * @{
bogdanm 84:0b3ab51c8877 290 */
bogdanm 84:0b3ab51c8877 291
bogdanm 84:0b3ab51c8877 292 #define RCC_PLLMUL_3 RCC_CFGR_PLLMUL3
bogdanm 84:0b3ab51c8877 293 #define RCC_PLLMUL_4 RCC_CFGR_PLLMUL4
bogdanm 84:0b3ab51c8877 294 #define RCC_PLLMUL_6 RCC_CFGR_PLLMUL6
bogdanm 84:0b3ab51c8877 295 #define RCC_PLLMUL_8 RCC_CFGR_PLLMUL8
bogdanm 84:0b3ab51c8877 296 #define RCC_PLLMUL_12 RCC_CFGR_PLLMUL12
bogdanm 84:0b3ab51c8877 297 #define RCC_PLLMUL_16 RCC_CFGR_PLLMUL16
bogdanm 84:0b3ab51c8877 298 #define RCC_PLLMUL_24 RCC_CFGR_PLLMUL24
bogdanm 84:0b3ab51c8877 299 #define RCC_PLLMUL_32 RCC_CFGR_PLLMUL32
bogdanm 84:0b3ab51c8877 300 #define RCC_PLLMUL_48 RCC_CFGR_PLLMUL48
Kojto 119:aae6fcc7d9bb 301
bogdanm 84:0b3ab51c8877 302 /**
bogdanm 84:0b3ab51c8877 303 * @}
bogdanm 84:0b3ab51c8877 304 */
bogdanm 84:0b3ab51c8877 305
Kojto 96:487b796308b0 306 /** @defgroup RCC_PLLDivider_Factor RCC PLL Dividers
bogdanm 84:0b3ab51c8877 307 * @{
bogdanm 84:0b3ab51c8877 308 */
bogdanm 84:0b3ab51c8877 309
bogdanm 84:0b3ab51c8877 310 #define RCC_PLLDIV_2 RCC_CFGR_PLLDIV2
bogdanm 84:0b3ab51c8877 311 #define RCC_PLLDIV_3 RCC_CFGR_PLLDIV3
bogdanm 84:0b3ab51c8877 312 #define RCC_PLLDIV_4 RCC_CFGR_PLLDIV4
Kojto 119:aae6fcc7d9bb 313
Kojto 119:aae6fcc7d9bb 314 /**
Kojto 119:aae6fcc7d9bb 315 * @}
Kojto 119:aae6fcc7d9bb 316 */
Kojto 119:aae6fcc7d9bb 317
Kojto 119:aae6fcc7d9bb 318 /** @defgroup RCC_MSI_Clock_Range RCC MSI Clock Range
Kojto 119:aae6fcc7d9bb 319 * @{
Kojto 119:aae6fcc7d9bb 320 */
Kojto 119:aae6fcc7d9bb 321
Kojto 119:aae6fcc7d9bb 322 #define RCC_MSIRANGE_0 RCC_ICSCR_MSIRANGE_0 /*!< MSI = 65.536 KHz */
Kojto 119:aae6fcc7d9bb 323 #define RCC_MSIRANGE_1 RCC_ICSCR_MSIRANGE_1 /*!< MSI = 131.072 KHz */
Kojto 119:aae6fcc7d9bb 324 #define RCC_MSIRANGE_2 RCC_ICSCR_MSIRANGE_2 /*!< MSI = 262.144 KHz */
Kojto 119:aae6fcc7d9bb 325 #define RCC_MSIRANGE_3 RCC_ICSCR_MSIRANGE_3 /*!< MSI = 524.288 KHz */
Kojto 119:aae6fcc7d9bb 326 #define RCC_MSIRANGE_4 RCC_ICSCR_MSIRANGE_4 /*!< MSI = 1.048 MHz */
Kojto 119:aae6fcc7d9bb 327 #define RCC_MSIRANGE_5 RCC_ICSCR_MSIRANGE_5 /*!< MSI = 2.097 MHz */
Kojto 119:aae6fcc7d9bb 328 #define RCC_MSIRANGE_6 RCC_ICSCR_MSIRANGE_6 /*!< MSI = 4.194 MHz */
Kojto 119:aae6fcc7d9bb 329
Kojto 119:aae6fcc7d9bb 330
bogdanm 84:0b3ab51c8877 331 /**
bogdanm 84:0b3ab51c8877 332 * @}
bogdanm 84:0b3ab51c8877 333 */
bogdanm 84:0b3ab51c8877 334
Kojto 96:487b796308b0 335 /** @defgroup RCC_System_Clock_Type RCC System Clock Type
bogdanm 84:0b3ab51c8877 336 * @{
bogdanm 84:0b3ab51c8877 337 */
Kojto 119:aae6fcc7d9bb 338 #define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001) /*!< SYSCLK to configure */
Kojto 119:aae6fcc7d9bb 339 #define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002) /*!< HCLK to configure */
Kojto 119:aae6fcc7d9bb 340 #define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004) /*!< PCLK1 to configure */
Kojto 119:aae6fcc7d9bb 341 #define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008) /*!< PCLK2 to configure */
bogdanm 84:0b3ab51c8877 342 /**
bogdanm 84:0b3ab51c8877 343 * @}
bogdanm 84:0b3ab51c8877 344 */
Kojto 119:aae6fcc7d9bb 345
Kojto 96:487b796308b0 346 /** @defgroup RCC_System_Clock_Source RCC System Clock Source
bogdanm 84:0b3ab51c8877 347 * @{
bogdanm 84:0b3ab51c8877 348 */
Kojto 119:aae6fcc7d9bb 349 #define RCC_SYSCLKSOURCE_MSI RCC_CFGR_SW_MSI /*!< MSI selection as system clock */
Kojto 119:aae6fcc7d9bb 350 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */
Kojto 119:aae6fcc7d9bb 351 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */
Kojto 119:aae6fcc7d9bb 352 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selection as system clock */
Kojto 96:487b796308b0 353 /**
Kojto 96:487b796308b0 354 * @}
Kojto 96:487b796308b0 355 */
Kojto 96:487b796308b0 356
Kojto 119:aae6fcc7d9bb 357 /** @defgroup RCC_System_Clock_SOURCE_Status RCC System Clock Source Status
Kojto 119:aae6fcc7d9bb 358 * @{
Kojto 119:aae6fcc7d9bb 359 */
Kojto 119:aae6fcc7d9bb 360 #define RCC_SYSCLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI /*!< MSI used as system clock */
Kojto 119:aae6fcc7d9bb 361 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
Kojto 119:aae6fcc7d9bb 362 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
Kojto 119:aae6fcc7d9bb 363 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
Kojto 119:aae6fcc7d9bb 364 /**
Kojto 119:aae6fcc7d9bb 365 * @}
Kojto 119:aae6fcc7d9bb 366 */
Kojto 119:aae6fcc7d9bb 367
Kojto 119:aae6fcc7d9bb 368 /** @defgroup RCC_AHB_Clock_Source RCC AHB Clock Source
bogdanm 84:0b3ab51c8877 369 * @{
bogdanm 84:0b3ab51c8877 370 */
Kojto 119:aae6fcc7d9bb 371 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */
Kojto 119:aae6fcc7d9bb 372 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */
Kojto 119:aae6fcc7d9bb 373 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */
Kojto 119:aae6fcc7d9bb 374 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */
Kojto 119:aae6fcc7d9bb 375 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */
Kojto 119:aae6fcc7d9bb 376 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */
Kojto 119:aae6fcc7d9bb 377 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
Kojto 119:aae6fcc7d9bb 378 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
Kojto 119:aae6fcc7d9bb 379 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
bogdanm 84:0b3ab51c8877 380 /**
bogdanm 84:0b3ab51c8877 381 * @}
Kojto 119:aae6fcc7d9bb 382 */
Kojto 119:aae6fcc7d9bb 383
Kojto 119:aae6fcc7d9bb 384 /** @defgroup RCC_APB1_APB2_Clock_Source RCC APB1 APB2 Clock Source
bogdanm 84:0b3ab51c8877 385 * @{
bogdanm 84:0b3ab51c8877 386 */
Kojto 119:aae6fcc7d9bb 387 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */
Kojto 119:aae6fcc7d9bb 388 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */
Kojto 119:aae6fcc7d9bb 389 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */
Kojto 119:aae6fcc7d9bb 390 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */
Kojto 119:aae6fcc7d9bb 391 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
bogdanm 84:0b3ab51c8877 392 /**
bogdanm 84:0b3ab51c8877 393 * @}
Kojto 119:aae6fcc7d9bb 394 */
bogdanm 84:0b3ab51c8877 395
Kojto 96:487b796308b0 396 /** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source
bogdanm 84:0b3ab51c8877 397 * @{
bogdanm 84:0b3ab51c8877 398 */
Kojto 96:487b796308b0 399 #define RCC_RTCCLKSOURCE_NO_CLK ((uint32_t)0x00000000)
bogdanm 84:0b3ab51c8877 400 #define RCC_RTCCLKSOURCE_LSE RCC_CSR_RTCSEL_LSE
bogdanm 84:0b3ab51c8877 401 #define RCC_RTCCLKSOURCE_LSI RCC_CSR_RTCSEL_LSI
Kojto 119:aae6fcc7d9bb 402 #define RCC_RTCCLKSOURCE_HSE_DIVX RCC_CSR_RTCSEL_HSE
Kojto 119:aae6fcc7d9bb 403
bogdanm 84:0b3ab51c8877 404 #define RCC_RTCCLKSOURCE_HSE_DIV2 RCC_CSR_RTCSEL_HSE
bogdanm 84:0b3ab51c8877 405 #define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE_0)
bogdanm 84:0b3ab51c8877 406 #define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE_1)
bogdanm 84:0b3ab51c8877 407 #define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE)
Kojto 119:aae6fcc7d9bb 408
Kojto 119:aae6fcc7d9bb 409 #define RCC_RTC_HSE_DIV_2 (uint32_t)0x00000000U /*!< HSE is divided by 2 for RTC clock */
Kojto 119:aae6fcc7d9bb 410 #define RCC_RTC_HSE_DIV_4 RCC_CR_RTCPRE_0 /*!< HSE is divided by 4 for RTC clock */
Kojto 119:aae6fcc7d9bb 411 #define RCC_RTC_HSE_DIV_8 RCC_CR_RTCPRE_1 /*!< HSE is divided by 8 for RTC clock */
Kojto 119:aae6fcc7d9bb 412 #define RCC_RTC_HSE_DIV_16 RCC_CR_RTCPRE /*!< HSE is divided by 16 for RTC clock */
Kojto 119:aae6fcc7d9bb 413
bogdanm 84:0b3ab51c8877 414 /**
bogdanm 84:0b3ab51c8877 415 * @}
bogdanm 84:0b3ab51c8877 416 */
bogdanm 84:0b3ab51c8877 417
Kojto 119:aae6fcc7d9bb 418 /** @defgroup RCC_MCO1_Clock_Source RCC MCO1 Clock Source
bogdanm 84:0b3ab51c8877 419 * @{
bogdanm 84:0b3ab51c8877 420 */
Kojto 96:487b796308b0 421
Kojto 96:487b796308b0 422 #define RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCO_NOCLOCK
Kojto 96:487b796308b0 423 #define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK
Kojto 96:487b796308b0 424 #define RCC_MCO1SOURCE_HSI RCC_CFGR_MCO_HSI
Kojto 96:487b796308b0 425 #define RCC_MCO1SOURCE_MSI RCC_CFGR_MCO_MSI
Kojto 96:487b796308b0 426 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO_HSE
Kojto 96:487b796308b0 427 #define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO_PLL
Kojto 96:487b796308b0 428 #define RCC_MCO1SOURCE_LSI RCC_CFGR_MCO_LSI
Kojto 96:487b796308b0 429 #define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO_LSE
Kojto 119:aae6fcc7d9bb 430 #if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) \
Kojto 119:aae6fcc7d9bb 431 && !defined (STM32L011xx) && !defined (STM32L021xx)
Kojto 96:487b796308b0 432 #define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCO_HSI48
Kojto 96:487b796308b0 433 #endif
Kojto 119:aae6fcc7d9bb 434
Kojto 96:487b796308b0 435
bogdanm 84:0b3ab51c8877 436 /**
bogdanm 84:0b3ab51c8877 437 * @}
bogdanm 84:0b3ab51c8877 438 */
bogdanm 84:0b3ab51c8877 439
Kojto 96:487b796308b0 440 /** @defgroup RCC_MCOPrescaler RCC MCO Prescaler
bogdanm 84:0b3ab51c8877 441 * @{
bogdanm 84:0b3ab51c8877 442 */
bogdanm 84:0b3ab51c8877 443
bogdanm 84:0b3ab51c8877 444 #define RCC_MCODIV_1 RCC_CFGR_MCO_PRE_1
bogdanm 84:0b3ab51c8877 445 #define RCC_MCODIV_2 RCC_CFGR_MCO_PRE_2
bogdanm 84:0b3ab51c8877 446 #define RCC_MCODIV_4 RCC_CFGR_MCO_PRE_4
bogdanm 84:0b3ab51c8877 447 #define RCC_MCODIV_8 RCC_CFGR_MCO_PRE_8
bogdanm 84:0b3ab51c8877 448 #define RCC_MCODIV_16 RCC_CFGR_MCO_PRE_16
bogdanm 84:0b3ab51c8877 449
bogdanm 84:0b3ab51c8877 450 /**
bogdanm 84:0b3ab51c8877 451 * @}
bogdanm 84:0b3ab51c8877 452 */
bogdanm 84:0b3ab51c8877 453
Kojto 96:487b796308b0 454 /** @defgroup RCC_MCO_Index RCC MCO Index
bogdanm 84:0b3ab51c8877 455 * @{
bogdanm 84:0b3ab51c8877 456 */
bogdanm 84:0b3ab51c8877 457 #define RCC_MCO1 ((uint32_t)0x00000000)
bogdanm 84:0b3ab51c8877 458 #define RCC_MCO2 ((uint32_t)0x00000001)
Kojto 119:aae6fcc7d9bb 459 #if defined(STM32L031xx) || defined(STM32L041xx) || defined(STM32L073xx) || defined(STM32L083xx) || \
Kojto 119:aae6fcc7d9bb 460 defined(STM32L072xx) || defined(STM32L082xx) || defined(STM32L071xx) || defined(STM32L081xx)
Kojto 119:aae6fcc7d9bb 461 #define RCC_MCO3 ((uint32_t)0x00000002)
Kojto 119:aae6fcc7d9bb 462 #endif
bogdanm 84:0b3ab51c8877 463
bogdanm 84:0b3ab51c8877 464 /**
bogdanm 84:0b3ab51c8877 465 * @}
bogdanm 84:0b3ab51c8877 466 */
bogdanm 84:0b3ab51c8877 467
Kojto 96:487b796308b0 468 /** @defgroup RCC_Interrupt RCC Interruptions
bogdanm 84:0b3ab51c8877 469 * @{
bogdanm 84:0b3ab51c8877 470 */
bogdanm 84:0b3ab51c8877 471 #define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF
bogdanm 84:0b3ab51c8877 472 #define RCC_IT_LSERDY RCC_CIFR_LSERDYF
bogdanm 84:0b3ab51c8877 473 #define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF
bogdanm 84:0b3ab51c8877 474 #define RCC_IT_HSERDY RCC_CIFR_HSERDYF
bogdanm 84:0b3ab51c8877 475 #define RCC_IT_PLLRDY RCC_CIFR_PLLRDYF
bogdanm 84:0b3ab51c8877 476 #define RCC_IT_MSIRDY RCC_CIFR_MSIRDYF
Kojto 96:487b796308b0 477
Kojto 119:aae6fcc7d9bb 478 #define RCC_IT_CSSLSE RCC_CIFR_CSSLSEF
Kojto 119:aae6fcc7d9bb 479 #define RCC_IT_CSSHSE RCC_CIFR_CSSHSEF
bogdanm 84:0b3ab51c8877 480
Kojto 119:aae6fcc7d9bb 481 #if !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
Kojto 119:aae6fcc7d9bb 482 #define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF
Kojto 96:487b796308b0 483 #endif /* !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) */
bogdanm 84:0b3ab51c8877 484 /**
bogdanm 84:0b3ab51c8877 485 * @}
bogdanm 84:0b3ab51c8877 486 */
Kojto 96:487b796308b0 487
Kojto 119:aae6fcc7d9bb 488 /** @defgroup RCC_Flag RCC Flag
bogdanm 84:0b3ab51c8877 489 * Elements values convention: 0XXYYYYYb
bogdanm 84:0b3ab51c8877 490 * - YYYYY : Flag position in the register
bogdanm 84:0b3ab51c8877 491 * - 0XX : Register index
bogdanm 84:0b3ab51c8877 492 * - 01: CR register
bogdanm 84:0b3ab51c8877 493 * - 10: CSR register
bogdanm 84:0b3ab51c8877 494 * - 11: CRRCR register
bogdanm 84:0b3ab51c8877 495 * @{
bogdanm 84:0b3ab51c8877 496 */
bogdanm 84:0b3ab51c8877 497 /* Flags in the CR register */
bogdanm 84:0b3ab51c8877 498 #define RCC_FLAG_HSIRDY ((uint8_t)0x22)
bogdanm 84:0b3ab51c8877 499 #define RCC_FLAG_HSIDIV ((uint8_t)0x24)
bogdanm 84:0b3ab51c8877 500 #define RCC_FLAG_MSIRDY ((uint8_t)0x29)
bogdanm 84:0b3ab51c8877 501 #define RCC_FLAG_HSERDY ((uint8_t)0x31)
bogdanm 84:0b3ab51c8877 502 #define RCC_FLAG_PLLRDY ((uint8_t)0x39)
bogdanm 84:0b3ab51c8877 503
bogdanm 84:0b3ab51c8877 504 /* Flags in the CSR register */
bogdanm 84:0b3ab51c8877 505 #define RCC_FLAG_LSERDY ((uint8_t)0x49)
bogdanm 84:0b3ab51c8877 506 #define RCC_FLAG_LSECSS ((uint8_t)0x4E)
bogdanm 84:0b3ab51c8877 507 #define RCC_FLAG_LSIRDY ((uint8_t)0x41)
Kojto 96:487b796308b0 508 #define RCC_FLAG_FWRST ((uint8_t)0x58)
bogdanm 84:0b3ab51c8877 509 #define RCC_FLAG_OBLRST ((uint8_t)0x59)
bogdanm 84:0b3ab51c8877 510 #define RCC_FLAG_PINRST ((uint8_t)0x5A)
bogdanm 84:0b3ab51c8877 511 #define RCC_FLAG_PORRST ((uint8_t)0x5B)
bogdanm 84:0b3ab51c8877 512 #define RCC_FLAG_SFTRST ((uint8_t)0x5C)
bogdanm 84:0b3ab51c8877 513 #define RCC_FLAG_IWDGRST ((uint8_t)0x5D)
bogdanm 84:0b3ab51c8877 514 #define RCC_FLAG_WWDGRST ((uint8_t)0x5E)
bogdanm 84:0b3ab51c8877 515 #define RCC_FLAG_LPWRRST ((uint8_t)0x5F)
bogdanm 84:0b3ab51c8877 516
Kojto 96:487b796308b0 517 #if !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
bogdanm 84:0b3ab51c8877 518 /* Flags in the CRRCR register */
bogdanm 84:0b3ab51c8877 519 #define RCC_FLAG_HSI48RDY ((uint8_t)0x61)
Kojto 96:487b796308b0 520 #endif /* !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) */
bogdanm 84:0b3ab51c8877 521
Kojto 96:487b796308b0 522
bogdanm 84:0b3ab51c8877 523 /**
bogdanm 84:0b3ab51c8877 524 * @}
bogdanm 84:0b3ab51c8877 525 */
bogdanm 84:0b3ab51c8877 526
bogdanm 84:0b3ab51c8877 527 /**
bogdanm 84:0b3ab51c8877 528 * @}
bogdanm 84:0b3ab51c8877 529 */
bogdanm 84:0b3ab51c8877 530 /* Exported macro ------------------------------------------------------------*/
Kojto 96:487b796308b0 531 /** @defgroup RCC_Exported_Macros RCC Exported Macros
bogdanm 84:0b3ab51c8877 532 * @{
bogdanm 84:0b3ab51c8877 533 */
Kojto 119:aae6fcc7d9bb 534
Kojto 119:aae6fcc7d9bb 535 /** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable AHB Peripheral Clock Enable Disable
Kojto 119:aae6fcc7d9bb 536 * @brief Enable or disable the AHB peripheral clock.
bogdanm 84:0b3ab51c8877 537 * @note After reset, the peripheral clock (used for registers read/write access)
bogdanm 84:0b3ab51c8877 538 * is disabled and the application software has to enable this clock before
bogdanm 84:0b3ab51c8877 539 * using it.
Kojto 119:aae6fcc7d9bb 540 * @{
bogdanm 84:0b3ab51c8877 541 */
Kojto 96:487b796308b0 542 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \
Kojto 96:487b796308b0 543 __IO uint32_t tmpreg; \
Kojto 96:487b796308b0 544 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
Kojto 96:487b796308b0 545 /* Delay after an RCC peripheral clock enabling */ \
Kojto 96:487b796308b0 546 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
Kojto 96:487b796308b0 547 UNUSED(tmpreg); \
Kojto 96:487b796308b0 548 } while(0)
Kojto 96:487b796308b0 549
Kojto 96:487b796308b0 550 #define __HAL_RCC_MIF_CLK_ENABLE() do { \
Kojto 96:487b796308b0 551 __IO uint32_t tmpreg; \
Kojto 96:487b796308b0 552 SET_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN);\
Kojto 96:487b796308b0 553 /* Delay after an RCC peripheral clock enabling */ \
Kojto 96:487b796308b0 554 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN);\
Kojto 96:487b796308b0 555 UNUSED(tmpreg); \
Kojto 96:487b796308b0 556 } while(0)
Kojto 96:487b796308b0 557
Kojto 96:487b796308b0 558 #define __HAL_RCC_CRC_CLK_ENABLE() do { \
Kojto 96:487b796308b0 559 __IO uint32_t tmpreg; \
Kojto 96:487b796308b0 560 SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
Kojto 96:487b796308b0 561 /* Delay after an RCC peripheral clock enabling */ \
Kojto 96:487b796308b0 562 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
Kojto 96:487b796308b0 563 UNUSED(tmpreg); \
Kojto 96:487b796308b0 564 } while(0)
bogdanm 84:0b3ab51c8877 565
bogdanm 84:0b3ab51c8877 566
Kojto 119:aae6fcc7d9bb 567 #define __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN)
Kojto 119:aae6fcc7d9bb 568 #define __HAL_RCC_MIF_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN)
Kojto 119:aae6fcc7d9bb 569 #define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN)
bogdanm 84:0b3ab51c8877 570
Kojto 119:aae6fcc7d9bb 571 /**
Kojto 119:aae6fcc7d9bb 572 * @}
Kojto 119:aae6fcc7d9bb 573 */
bogdanm 84:0b3ab51c8877 574
Kojto 119:aae6fcc7d9bb 575 /** @defgroup RCC_IOPORT_Clock_Enable_Disable IOPORT Peripheral Clock Enable Disable
Kojto 119:aae6fcc7d9bb 576 * @brief Enable or disable the IOPORT peripheral clock.
bogdanm 84:0b3ab51c8877 577 * @note After reset, the peripheral clock (used for registers read/write access)
bogdanm 84:0b3ab51c8877 578 * is disabled and the application software has to enable this clock before
bogdanm 84:0b3ab51c8877 579 * using it.
Kojto 119:aae6fcc7d9bb 580 * @{
bogdanm 84:0b3ab51c8877 581 */
Kojto 96:487b796308b0 582 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
Kojto 96:487b796308b0 583 __IO uint32_t tmpreg; \
Kojto 96:487b796308b0 584 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN);\
Kojto 96:487b796308b0 585 /* Delay after an RCC peripheral clock enabling */ \
Kojto 96:487b796308b0 586 tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN);\
Kojto 96:487b796308b0 587 UNUSED(tmpreg); \
Kojto 96:487b796308b0 588 } while(0)
Kojto 96:487b796308b0 589
Kojto 96:487b796308b0 590 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
Kojto 96:487b796308b0 591 __IO uint32_t tmpreg; \
Kojto 96:487b796308b0 592 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN);\
Kojto 96:487b796308b0 593 /* Delay after an RCC peripheral clock enabling */ \
Kojto 96:487b796308b0 594 tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN);\
Kojto 96:487b796308b0 595 UNUSED(tmpreg); \
Kojto 96:487b796308b0 596 } while(0)
Kojto 96:487b796308b0 597
Kojto 96:487b796308b0 598 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
Kojto 96:487b796308b0 599 __IO uint32_t tmpreg; \
Kojto 96:487b796308b0 600 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN);\
Kojto 96:487b796308b0 601 /* Delay after an RCC peripheral clock enabling */ \
Kojto 96:487b796308b0 602 tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN);\
Kojto 96:487b796308b0 603 UNUSED(tmpreg); \
Kojto 96:487b796308b0 604 } while(0)
bogdanm 84:0b3ab51c8877 605
Kojto 96:487b796308b0 606 #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
Kojto 96:487b796308b0 607 __IO uint32_t tmpreg; \
Kojto 96:487b796308b0 608 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN);\
Kojto 96:487b796308b0 609 /* Delay after an RCC peripheral clock enabling */ \
Kojto 96:487b796308b0 610 tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN);\
Kojto 96:487b796308b0 611 UNUSED(tmpreg); \
Kojto 96:487b796308b0 612 } while(0)
Kojto 96:487b796308b0 613
Kojto 96:487b796308b0 614
Kojto 119:aae6fcc7d9bb 615 #define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN)
Kojto 119:aae6fcc7d9bb 616 #define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN)
Kojto 119:aae6fcc7d9bb 617 #define __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN)
Kojto 119:aae6fcc7d9bb 618 #define __HAL_RCC_GPIOH_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN)
bogdanm 84:0b3ab51c8877 619
Kojto 119:aae6fcc7d9bb 620 /**
Kojto 119:aae6fcc7d9bb 621 * @}
Kojto 119:aae6fcc7d9bb 622 */
bogdanm 84:0b3ab51c8877 623
Kojto 119:aae6fcc7d9bb 624 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
Kojto 119:aae6fcc7d9bb 625 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
bogdanm 84:0b3ab51c8877 626 * @note After reset, the peripheral clock (used for registers read/write access)
bogdanm 84:0b3ab51c8877 627 * is disabled and the application software has to enable this clock before
bogdanm 84:0b3ab51c8877 628 * using it.
Kojto 119:aae6fcc7d9bb 629 * @{
bogdanm 84:0b3ab51c8877 630 */
Kojto 119:aae6fcc7d9bb 631 #define __HAL_RCC_WWDG_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_WWDGEN))
Kojto 119:aae6fcc7d9bb 632 #define __HAL_RCC_PWR_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_PWREN))
bogdanm 84:0b3ab51c8877 633
Kojto 119:aae6fcc7d9bb 634 #define __HAL_RCC_WWDG_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_WWDGEN))
Kojto 119:aae6fcc7d9bb 635 #define __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_PWREN))
Kojto 119:aae6fcc7d9bb 636 /**
Kojto 119:aae6fcc7d9bb 637 * @}
Kojto 119:aae6fcc7d9bb 638 */
bogdanm 84:0b3ab51c8877 639
Kojto 119:aae6fcc7d9bb 640 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
Kojto 119:aae6fcc7d9bb 641 * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
bogdanm 84:0b3ab51c8877 642 * @note After reset, the peripheral clock (used for registers read/write access)
bogdanm 84:0b3ab51c8877 643 * is disabled and the application software has to enable this clock before
bogdanm 84:0b3ab51c8877 644 * using it.
Kojto 119:aae6fcc7d9bb 645 * @{
bogdanm 84:0b3ab51c8877 646 */
Kojto 119:aae6fcc7d9bb 647 #define __HAL_RCC_SYSCFG_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_SYSCFGEN))
Kojto 119:aae6fcc7d9bb 648 #define __HAL_RCC_DBGMCU_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_DBGMCUEN))
Kojto 119:aae6fcc7d9bb 649
Kojto 119:aae6fcc7d9bb 650 #define __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_SYSCFGEN))
Kojto 119:aae6fcc7d9bb 651 #define __HAL_RCC_DBGMCU_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_DBGMCUEN))
Kojto 119:aae6fcc7d9bb 652 /**
Kojto 119:aae6fcc7d9bb 653 * @}
Kojto 119:aae6fcc7d9bb 654 */
Kojto 119:aae6fcc7d9bb 655
Kojto 119:aae6fcc7d9bb 656 /** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enabled or Disabled Status
Kojto 119:aae6fcc7d9bb 657 * @brief Check whether the AHB peripheral clock is enabled or not.
Kojto 119:aae6fcc7d9bb 658 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 119:aae6fcc7d9bb 659 * is disabled and the application software has to enable this clock before
Kojto 119:aae6fcc7d9bb 660 * using it.
Kojto 119:aae6fcc7d9bb 661 * @{
Kojto 119:aae6fcc7d9bb 662 */
Kojto 119:aae6fcc7d9bb 663
Kojto 119:aae6fcc7d9bb 664 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN) != RESET)
Kojto 119:aae6fcc7d9bb 665 #define __HAL_RCC_MIF_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN) != RESET)
Kojto 119:aae6fcc7d9bb 666 #define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN) != RESET)
Kojto 119:aae6fcc7d9bb 667
Kojto 119:aae6fcc7d9bb 668 /**
Kojto 119:aae6fcc7d9bb 669 * @}
Kojto 119:aae6fcc7d9bb 670 */
Kojto 119:aae6fcc7d9bb 671
Kojto 119:aae6fcc7d9bb 672 /** @defgroup RCC_IOPORT_Peripheral_Clock_Enable_Disable_Status IOPORT Peripheral Clock Enabled or Disabled Status
Kojto 119:aae6fcc7d9bb 673 * @brief Check whether the IOPORT peripheral clock is enabled or not.
Kojto 119:aae6fcc7d9bb 674 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 119:aae6fcc7d9bb 675 * is disabled and the application software has to enable this clock before
Kojto 119:aae6fcc7d9bb 676 * using it.
Kojto 119:aae6fcc7d9bb 677 * @{
Kojto 119:aae6fcc7d9bb 678 */
bogdanm 84:0b3ab51c8877 679
Kojto 119:aae6fcc7d9bb 680 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN) != RESET)
Kojto 119:aae6fcc7d9bb 681 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN) != RESET)
Kojto 119:aae6fcc7d9bb 682 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN) != RESET)
Kojto 119:aae6fcc7d9bb 683 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN) != RESET)
Kojto 119:aae6fcc7d9bb 684
Kojto 119:aae6fcc7d9bb 685 /**
Kojto 119:aae6fcc7d9bb 686 * @}
Kojto 119:aae6fcc7d9bb 687 */
Kojto 119:aae6fcc7d9bb 688
Kojto 119:aae6fcc7d9bb 689 /** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status
Kojto 119:aae6fcc7d9bb 690 * @brief Check whether the APB1 peripheral clock is enabled or not.
Kojto 119:aae6fcc7d9bb 691 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 119:aae6fcc7d9bb 692 * is disabled and the application software has to enable this clock before
Kojto 119:aae6fcc7d9bb 693 * using it.
Kojto 119:aae6fcc7d9bb 694 * @{
Kojto 119:aae6fcc7d9bb 695 */
Kojto 119:aae6fcc7d9bb 696 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN) != RESET)
Kojto 119:aae6fcc7d9bb 697 #define __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN) != RESET)
bogdanm 84:0b3ab51c8877 698
Kojto 119:aae6fcc7d9bb 699 /**
Kojto 119:aae6fcc7d9bb 700 * @}
Kojto 119:aae6fcc7d9bb 701 */
Kojto 119:aae6fcc7d9bb 702
Kojto 119:aae6fcc7d9bb 703 /** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status
Kojto 119:aae6fcc7d9bb 704 * @brief Check whether the APB2 peripheral clock is enabled or not.
Kojto 119:aae6fcc7d9bb 705 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 119:aae6fcc7d9bb 706 * is disabled and the application software has to enable this clock before
Kojto 119:aae6fcc7d9bb 707 * using it.
Kojto 119:aae6fcc7d9bb 708 * @{
Kojto 119:aae6fcc7d9bb 709 */
Kojto 119:aae6fcc7d9bb 710 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) != RESET)
Kojto 119:aae6fcc7d9bb 711 #define __HAL_RCC_DBGMCU_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DBGMCUEN) != RESET)
Kojto 119:aae6fcc7d9bb 712
Kojto 119:aae6fcc7d9bb 713 /**
Kojto 119:aae6fcc7d9bb 714 * @}
Kojto 119:aae6fcc7d9bb 715 */
Kojto 119:aae6fcc7d9bb 716
Kojto 119:aae6fcc7d9bb 717 /** @defgroup RCC_AHB_Force_Release_Reset AHB Peripheral Force Release Reset
Kojto 119:aae6fcc7d9bb 718 * @brief Force or release AHB peripheral reset.
Kojto 119:aae6fcc7d9bb 719 * @{
bogdanm 84:0b3ab51c8877 720 */
Kojto 96:487b796308b0 721 #define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFF)
Kojto 119:aae6fcc7d9bb 722 #define __HAL_RCC_DMA1_FORCE_RESET() SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_DMA1RST))
Kojto 119:aae6fcc7d9bb 723 #define __HAL_RCC_MIF_FORCE_RESET() SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_MIFRST))
Kojto 119:aae6fcc7d9bb 724 #define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_CRCRST))
bogdanm 84:0b3ab51c8877 725
Kojto 96:487b796308b0 726 #define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00)
Kojto 119:aae6fcc7d9bb 727 #define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_CRCRST))
Kojto 119:aae6fcc7d9bb 728 #define __HAL_RCC_DMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_DMA1RST))
Kojto 119:aae6fcc7d9bb 729 #define __HAL_RCC_MIF_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_MIFRST))
Kojto 119:aae6fcc7d9bb 730 /**
Kojto 119:aae6fcc7d9bb 731 * @}
Kojto 119:aae6fcc7d9bb 732 */
Kojto 119:aae6fcc7d9bb 733
Kojto 119:aae6fcc7d9bb 734 /** @defgroup RCC_IOPORT_Force_Release_Reset IOPORT Peripheral Force Release Reset
Kojto 119:aae6fcc7d9bb 735 * @brief Force or release IOPORT peripheral reset.
Kojto 119:aae6fcc7d9bb 736 * @{
bogdanm 84:0b3ab51c8877 737 */
Kojto 96:487b796308b0 738 #define __HAL_RCC_IOP_FORCE_RESET() (RCC->IOPRSTR = 0xFFFFFFFF)
Kojto 119:aae6fcc7d9bb 739 #define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOARST))
Kojto 119:aae6fcc7d9bb 740 #define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOBRST))
Kojto 119:aae6fcc7d9bb 741 #define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOCRST))
Kojto 119:aae6fcc7d9bb 742 #define __HAL_RCC_GPIOH_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOHRST))
bogdanm 84:0b3ab51c8877 743
Kojto 96:487b796308b0 744 #define __HAL_RCC_IOP_RELEASE_RESET() (RCC->IOPRSTR = 0x00)
Kojto 119:aae6fcc7d9bb 745 #define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOARST))
Kojto 119:aae6fcc7d9bb 746 #define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOBRST))
Kojto 119:aae6fcc7d9bb 747 #define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOCRST))
Kojto 119:aae6fcc7d9bb 748 #define __HAL_RCC_GPIOH_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOHRST))
bogdanm 84:0b3ab51c8877 749
Kojto 119:aae6fcc7d9bb 750 /**
Kojto 119:aae6fcc7d9bb 751 * @}
Kojto 119:aae6fcc7d9bb 752 */
Kojto 119:aae6fcc7d9bb 753
Kojto 119:aae6fcc7d9bb 754 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset
Kojto 119:aae6fcc7d9bb 755 * @brief Force or release APB1 peripheral reset.
Kojto 119:aae6fcc7d9bb 756 * @{
bogdanm 84:0b3ab51c8877 757 */
Kojto 96:487b796308b0 758 #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
Kojto 119:aae6fcc7d9bb 759 #define __HAL_RCC_WWDG_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_WWDGRST))
Kojto 119:aae6fcc7d9bb 760 #define __HAL_RCC_PWR_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_PWRRST))
bogdanm 84:0b3ab51c8877 761
Kojto 96:487b796308b0 762 #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
Kojto 119:aae6fcc7d9bb 763 #define __HAL_RCC_WWDG_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_WWDGRST))
Kojto 119:aae6fcc7d9bb 764 #define __HAL_RCC_PWR_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_PWRRST))
bogdanm 84:0b3ab51c8877 765
Kojto 119:aae6fcc7d9bb 766 /**
Kojto 119:aae6fcc7d9bb 767 * @}
Kojto 119:aae6fcc7d9bb 768 */
Kojto 119:aae6fcc7d9bb 769
Kojto 119:aae6fcc7d9bb 770 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset
Kojto 119:aae6fcc7d9bb 771 * @brief Force or release APB2 peripheral reset.
Kojto 119:aae6fcc7d9bb 772 * @{
bogdanm 84:0b3ab51c8877 773 */
Kojto 96:487b796308b0 774 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
Kojto 119:aae6fcc7d9bb 775 #define __HAL_RCC_DBGMCU_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_DBGMCURST))
Kojto 119:aae6fcc7d9bb 776 #define __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SYSCFGRST))
bogdanm 84:0b3ab51c8877 777
Kojto 96:487b796308b0 778 #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
Kojto 119:aae6fcc7d9bb 779 #define __HAL_RCC_DBGMCU_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_DBGMCURST))
Kojto 119:aae6fcc7d9bb 780 #define __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SYSCFGRST))
Kojto 119:aae6fcc7d9bb 781 /**
Kojto 119:aae6fcc7d9bb 782 * @}
Kojto 119:aae6fcc7d9bb 783 */
Kojto 119:aae6fcc7d9bb 784
bogdanm 84:0b3ab51c8877 785
Kojto 119:aae6fcc7d9bb 786 /** @defgroup RCC_AHB_Clock_Sleep_Enable_Disable AHB Peripheral Clock Sleep Enable Disable
Kojto 119:aae6fcc7d9bb 787 * @brief Enable or disable the AHB peripheral clock during Low Power (Sleep) mode.
bogdanm 84:0b3ab51c8877 788 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm 84:0b3ab51c8877 789 * power consumption.
bogdanm 84:0b3ab51c8877 790 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 96:487b796308b0 791 * @note By default, all peripheral activated clocks remain enabled during SLEEP mode.
Kojto 119:aae6fcc7d9bb 792 * @{
bogdanm 84:0b3ab51c8877 793 */
Kojto 119:aae6fcc7d9bb 794 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_CRCSMEN))
Kojto 119:aae6fcc7d9bb 795 #define __HAL_RCC_MIF_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_MIFSMEN))
Kojto 119:aae6fcc7d9bb 796 #define __HAL_RCC_SRAM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_SRAMSMEN))
Kojto 119:aae6fcc7d9bb 797 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_DMA1SMEN))
Kojto 119:aae6fcc7d9bb 798
Kojto 119:aae6fcc7d9bb 799 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_CRCSMEN))
Kojto 119:aae6fcc7d9bb 800 #define __HAL_RCC_MIF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_MIFSMEN))
Kojto 119:aae6fcc7d9bb 801 #define __HAL_RCC_SRAM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_SRAMSMEN))
Kojto 119:aae6fcc7d9bb 802 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_DMA1SMEN))
Kojto 119:aae6fcc7d9bb 803 /**
Kojto 119:aae6fcc7d9bb 804 * @}
Kojto 119:aae6fcc7d9bb 805 */
Kojto 119:aae6fcc7d9bb 806
Kojto 119:aae6fcc7d9bb 807 /** @defgroup RCC_IOPORT_Clock_Sleep_Enable_Disable IOPORT Peripheral Clock Sleep Enable Disable
Kojto 119:aae6fcc7d9bb 808 * @brief Enable or disable the IOPORT peripheral clock during Low Power (Sleep) mode.
Kojto 119:aae6fcc7d9bb 809 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 119:aae6fcc7d9bb 810 * power consumption.
Kojto 119:aae6fcc7d9bb 811 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 119:aae6fcc7d9bb 812 * @note By default, all peripheral activated clocks remain enabled during SLEEP mode.
Kojto 119:aae6fcc7d9bb 813 * @{
Kojto 119:aae6fcc7d9bb 814 */
Kojto 119:aae6fcc7d9bb 815
Kojto 119:aae6fcc7d9bb 816 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOASMEN))
Kojto 119:aae6fcc7d9bb 817 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOBSMEN))
Kojto 119:aae6fcc7d9bb 818 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOCSMEN))
Kojto 119:aae6fcc7d9bb 819 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOHSMEN))
bogdanm 84:0b3ab51c8877 820
Kojto 119:aae6fcc7d9bb 821 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOASMEN))
Kojto 119:aae6fcc7d9bb 822 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOBSMEN))
Kojto 119:aae6fcc7d9bb 823 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOCSMEN))
Kojto 119:aae6fcc7d9bb 824 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOHSMEN))
Kojto 119:aae6fcc7d9bb 825 /**
Kojto 119:aae6fcc7d9bb 826 * @}
Kojto 119:aae6fcc7d9bb 827 */
Kojto 119:aae6fcc7d9bb 828
Kojto 119:aae6fcc7d9bb 829 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable
Kojto 119:aae6fcc7d9bb 830 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
Kojto 119:aae6fcc7d9bb 831 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 119:aae6fcc7d9bb 832 * power consumption.
Kojto 119:aae6fcc7d9bb 833 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 119:aae6fcc7d9bb 834 * @note By default, all peripheral activated clocks remain enabled during SLEEP mode.
Kojto 119:aae6fcc7d9bb 835 * @{
Kojto 119:aae6fcc7d9bb 836 */
Kojto 119:aae6fcc7d9bb 837 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_WWDGSMEN))
Kojto 119:aae6fcc7d9bb 838 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_PWRSMEN))
bogdanm 84:0b3ab51c8877 839
Kojto 119:aae6fcc7d9bb 840 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_WWDGSMEN))
Kojto 119:aae6fcc7d9bb 841 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_PWRSMEN))
Kojto 119:aae6fcc7d9bb 842
Kojto 119:aae6fcc7d9bb 843 /**
Kojto 119:aae6fcc7d9bb 844 * @}
Kojto 119:aae6fcc7d9bb 845 */
Kojto 119:aae6fcc7d9bb 846
Kojto 119:aae6fcc7d9bb 847 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable
Kojto 119:aae6fcc7d9bb 848 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
bogdanm 84:0b3ab51c8877 849 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm 84:0b3ab51c8877 850 * power consumption.
bogdanm 84:0b3ab51c8877 851 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 96:487b796308b0 852 * @note By default, all peripheral activated clocks remain enabled during SLEEP mode.
Kojto 119:aae6fcc7d9bb 853 * @{
Kojto 119:aae6fcc7d9bb 854 */
Kojto 119:aae6fcc7d9bb 855 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_SYSCFGSMEN))
Kojto 119:aae6fcc7d9bb 856 #define __HAL_RCC_DBGMCU_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_DBGMCUSMEN))
Kojto 119:aae6fcc7d9bb 857
Kojto 119:aae6fcc7d9bb 858 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_SYSCFGSMEN))
Kojto 119:aae6fcc7d9bb 859 #define __HAL_RCC_DBGMCU_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_DBGMCUSMEN))
Kojto 119:aae6fcc7d9bb 860
Kojto 119:aae6fcc7d9bb 861 /**
Kojto 119:aae6fcc7d9bb 862 * @}
Kojto 119:aae6fcc7d9bb 863 */
Kojto 119:aae6fcc7d9bb 864
Kojto 119:aae6fcc7d9bb 865 /** @defgroup RCC_AHB_Clock_Sleep_Enable_Disable_Status AHB Peripheral Clock Sleep Enabled or Disabled Status
Kojto 119:aae6fcc7d9bb 866 * @brief Check whether the AHB peripheral clock during Low Power (Sleep) mode is enabled or not.
Kojto 119:aae6fcc7d9bb 867 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 119:aae6fcc7d9bb 868 * power consumption.
Kojto 119:aae6fcc7d9bb 869 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 119:aae6fcc7d9bb 870 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 119:aae6fcc7d9bb 871 * @{
Kojto 119:aae6fcc7d9bb 872 */
Kojto 119:aae6fcc7d9bb 873 #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN) != RESET)
Kojto 119:aae6fcc7d9bb 874 #define __HAL_RCC_MIF_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_MIFSMEN) != RESET)
Kojto 119:aae6fcc7d9bb 875 #define __HAL_RCC_SRAM_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAMSMEN) != RESET)
Kojto 119:aae6fcc7d9bb 876 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN) != RESET)
Kojto 119:aae6fcc7d9bb 877
Kojto 119:aae6fcc7d9bb 878 /**
Kojto 119:aae6fcc7d9bb 879 * @}
Kojto 119:aae6fcc7d9bb 880 */
Kojto 119:aae6fcc7d9bb 881
Kojto 119:aae6fcc7d9bb 882 /** @defgroup RCC_IOPORT_Clock_Sleep_Enable_Disable_Status IOPORT Peripheral Clock Sleep Enabled or Disabled Status
Kojto 119:aae6fcc7d9bb 883 * @brief Check whether the IOPORT peripheral clock during Low Power (Sleep) mode is enabled or not.
Kojto 119:aae6fcc7d9bb 884 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 119:aae6fcc7d9bb 885 * power consumption.
Kojto 119:aae6fcc7d9bb 886 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 119:aae6fcc7d9bb 887 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 119:aae6fcc7d9bb 888 * @{
Kojto 119:aae6fcc7d9bb 889 */
Kojto 119:aae6fcc7d9bb 890 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOASMEN) != RESET)
Kojto 119:aae6fcc7d9bb 891 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOBSMEN) != RESET)
Kojto 119:aae6fcc7d9bb 892 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOCSMEN) != RESET)
Kojto 119:aae6fcc7d9bb 893 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOHSMEN) != RESET)
Kojto 119:aae6fcc7d9bb 894
Kojto 119:aae6fcc7d9bb 895 /**
Kojto 119:aae6fcc7d9bb 896 * @}
bogdanm 84:0b3ab51c8877 897 */
bogdanm 84:0b3ab51c8877 898
Kojto 119:aae6fcc7d9bb 899 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enabled or Disabled Status
Kojto 119:aae6fcc7d9bb 900 * @brief Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not.
Kojto 119:aae6fcc7d9bb 901 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 119:aae6fcc7d9bb 902 * power consumption.
Kojto 119:aae6fcc7d9bb 903 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 119:aae6fcc7d9bb 904 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 119:aae6fcc7d9bb 905 * @{
Kojto 119:aae6fcc7d9bb 906 */
Kojto 119:aae6fcc7d9bb 907 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_WWDGSMEN) != RESET)
Kojto 119:aae6fcc7d9bb 908 #define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_PWRSMEN) != RESET)
bogdanm 84:0b3ab51c8877 909
Kojto 119:aae6fcc7d9bb 910 /**
Kojto 119:aae6fcc7d9bb 911 * @}
Kojto 119:aae6fcc7d9bb 912 */
Kojto 119:aae6fcc7d9bb 913
Kojto 119:aae6fcc7d9bb 914 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enabled or Disabled Status
Kojto 119:aae6fcc7d9bb 915 * @brief Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not.
bogdanm 84:0b3ab51c8877 916 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm 84:0b3ab51c8877 917 * power consumption.
bogdanm 84:0b3ab51c8877 918 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 119:aae6fcc7d9bb 919 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 119:aae6fcc7d9bb 920 * @{
Kojto 119:aae6fcc7d9bb 921 */
Kojto 119:aae6fcc7d9bb 922 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) != RESET)
Kojto 119:aae6fcc7d9bb 923 #define __HAL_RCC_DBGMCU_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DBGMCUSMEN) != RESET)
Kojto 119:aae6fcc7d9bb 924
Kojto 119:aae6fcc7d9bb 925 /**
Kojto 119:aae6fcc7d9bb 926 * @}
bogdanm 84:0b3ab51c8877 927 */
Kojto 119:aae6fcc7d9bb 928
Kojto 119:aae6fcc7d9bb 929 /** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset
Kojto 119:aae6fcc7d9bb 930 * @{
Kojto 119:aae6fcc7d9bb 931 */
Kojto 119:aae6fcc7d9bb 932
Kojto 119:aae6fcc7d9bb 933 /** @brief Macros to force or release the Backup domain reset.
Kojto 119:aae6fcc7d9bb 934 * @note This function resets the RTC peripheral (including the backup registers)
Kojto 119:aae6fcc7d9bb 935 * and the RTC clock source selection in RCC_CSR register.
Kojto 119:aae6fcc7d9bb 936 * @note The BKPSRAM is not affected by this reset.
Kojto 119:aae6fcc7d9bb 937 */
Kojto 119:aae6fcc7d9bb 938 #define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->CSR, RCC_CSR_RTCRST)
Kojto 119:aae6fcc7d9bb 939 #define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->CSR, RCC_CSR_RTCRST)
bogdanm 84:0b3ab51c8877 940
Kojto 119:aae6fcc7d9bb 941 /**
Kojto 119:aae6fcc7d9bb 942 * @}
Kojto 119:aae6fcc7d9bb 943 */
bogdanm 84:0b3ab51c8877 944
Kojto 119:aae6fcc7d9bb 945 /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
Kojto 119:aae6fcc7d9bb 946 * @{
Kojto 119:aae6fcc7d9bb 947 */
Kojto 119:aae6fcc7d9bb 948
Kojto 119:aae6fcc7d9bb 949 /** @brief Macros to enable or disable the the RTC clock.
Kojto 119:aae6fcc7d9bb 950 * @note These macros must be used only after the RTC clock source was selected.
Kojto 119:aae6fcc7d9bb 951 */
Kojto 119:aae6fcc7d9bb 952 #define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_RTCEN)
Kojto 119:aae6fcc7d9bb 953 #define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_RTCEN)
Kojto 119:aae6fcc7d9bb 954
Kojto 119:aae6fcc7d9bb 955 /**
Kojto 119:aae6fcc7d9bb 956 * @}
bogdanm 84:0b3ab51c8877 957 */
Kojto 119:aae6fcc7d9bb 958
Kojto 119:aae6fcc7d9bb 959 /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
Kojto 119:aae6fcc7d9bb 960 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
Kojto 119:aae6fcc7d9bb 961 * It is used (enabled by hardware) as system clock source after startup
Kojto 119:aae6fcc7d9bb 962 * from Reset, wakeup from STOP and STANDBY mode, or in case of failure
Kojto 119:aae6fcc7d9bb 963 * of the HSE used directly or indirectly as system clock (if the Clock
Kojto 119:aae6fcc7d9bb 964 * Security System CSS is enabled).
Kojto 119:aae6fcc7d9bb 965 * @note HSI can not be stopped if it is used as system clock source. In this case,
Kojto 119:aae6fcc7d9bb 966 * you have to select another source of the system clock then stop the HSI.
Kojto 119:aae6fcc7d9bb 967 * @note After enabling the HSI, the application software should wait on HSIRDY
Kojto 119:aae6fcc7d9bb 968 * flag to be set indicating that HSI clock is stable and can be used as
Kojto 119:aae6fcc7d9bb 969 * system clock source.
Kojto 119:aae6fcc7d9bb 970 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
Kojto 119:aae6fcc7d9bb 971 * clock cycles.
Kojto 119:aae6fcc7d9bb 972 */
Kojto 119:aae6fcc7d9bb 973 #define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
Kojto 119:aae6fcc7d9bb 974 #define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
bogdanm 84:0b3ab51c8877 975
Kojto 119:aae6fcc7d9bb 976 /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
Kojto 119:aae6fcc7d9bb 977 * @note The calibration is used to compensate for the variations in voltage
Kojto 119:aae6fcc7d9bb 978 * and temperature that influence the frequency of the internal HSI RC.
Kojto 119:aae6fcc7d9bb 979 * @param __HSICalibrationValue__: specifies the calibration trimming value.
Kojto 119:aae6fcc7d9bb 980 * This parameter must be a number between 0 and 0x1F.
Kojto 119:aae6fcc7d9bb 981 */
Kojto 119:aae6fcc7d9bb 982 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->ICSCR,\
Kojto 119:aae6fcc7d9bb 983 RCC_ICSCR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << 8))
Kojto 119:aae6fcc7d9bb 984
bogdanm 84:0b3ab51c8877 985 /** @brief Macro to enable or disable the Internal High Speed oscillator (HSI).
bogdanm 84:0b3ab51c8877 986 * @note After enabling the HSI, the application software should wait on
bogdanm 84:0b3ab51c8877 987 * HSIRDY flag to be set indicating that HSI clock is stable and can
bogdanm 84:0b3ab51c8877 988 * be used to clock the PLL and/or system clock.
bogdanm 84:0b3ab51c8877 989 * @note HSI can not be stopped if it is used directly or through the PLL
bogdanm 84:0b3ab51c8877 990 * as system clock. In this case, you have to select another source
bogdanm 84:0b3ab51c8877 991 * of the system clock then stop the HSI.
bogdanm 84:0b3ab51c8877 992 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
bogdanm 84:0b3ab51c8877 993 * @param __STATE__: specifies the new state of the HSI.
bogdanm 84:0b3ab51c8877 994 * This parameter can be one of the following values:
bogdanm 84:0b3ab51c8877 995 * @arg RCC_HSI_OFF: turn OFF the HSI oscillator
bogdanm 84:0b3ab51c8877 996 * @arg RCC_HSI_ON: turn ON the HSI oscillator
bogdanm 84:0b3ab51c8877 997 * @arg RCC_HSI_DIV4: turn ON the HSI oscillator and divide it by 4
bogdanm 84:0b3ab51c8877 998 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
bogdanm 84:0b3ab51c8877 999 * clock cycles.
bogdanm 84:0b3ab51c8877 1000 */
bogdanm 84:0b3ab51c8877 1001 #define __HAL_RCC_HSI_CONFIG(__STATE__) \
Kojto 119:aae6fcc7d9bb 1002 MODIFY_REG(RCC->CR, RCC_CR_HSION | RCC_CR_HSIDIVEN , (uint32_t)(__STATE__))
Kojto 119:aae6fcc7d9bb 1003
bogdanm 84:0b3ab51c8877 1004 /**
bogdanm 84:0b3ab51c8877 1005 * @brief Macros to enable or disable the Internal Multi Speed oscillator (MSI).
bogdanm 84:0b3ab51c8877 1006 * @note The MSI is stopped by hardware when entering STOP and STANDBY modes.
bogdanm 84:0b3ab51c8877 1007 * It is used (enabled by hardware) as system clock source after
bogdanm 84:0b3ab51c8877 1008 * startup from Reset, wakeup from STOP and STANDBY mode, or in case
bogdanm 84:0b3ab51c8877 1009 * of failure of the HSE used directly or indirectly as system clock
bogdanm 84:0b3ab51c8877 1010 * (if the Clock Security System CSS is enabled).
bogdanm 84:0b3ab51c8877 1011 * @note MSI can not be stopped if it is used as system clock source.
bogdanm 84:0b3ab51c8877 1012 * In this case, you have to select another source of the system
bogdanm 84:0b3ab51c8877 1013 * clock then stop the MSI.
bogdanm 84:0b3ab51c8877 1014 * @note After enabling the MSI, the application software should wait on
bogdanm 84:0b3ab51c8877 1015 * MSIRDY flag to be set indicating that MSI clock is stable and can
bogdanm 84:0b3ab51c8877 1016 * be used as system clock source.
bogdanm 84:0b3ab51c8877 1017 * @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator
bogdanm 84:0b3ab51c8877 1018 * clock cycles.
bogdanm 84:0b3ab51c8877 1019 */
bogdanm 84:0b3ab51c8877 1020 #define __HAL_RCC_MSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_MSION)
bogdanm 84:0b3ab51c8877 1021 #define __HAL_RCC_MSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSION)
bogdanm 84:0b3ab51c8877 1022
bogdanm 84:0b3ab51c8877 1023
bogdanm 84:0b3ab51c8877 1024 /** @brief Macro Adjusts the Internal Multi Speed oscillator (MSI) calibration value.
bogdanm 84:0b3ab51c8877 1025 * @note The calibration is used to compensate for the variations in voltage
bogdanm 84:0b3ab51c8877 1026 * and temperature that influence the frequency of the internal MSI RC.
bogdanm 84:0b3ab51c8877 1027 * Refer to the Application Note AN3300 for more details on how to
bogdanm 84:0b3ab51c8877 1028 * calibrate the MSI.
bogdanm 84:0b3ab51c8877 1029 * @param __MSICalibrationValue__: specifies the calibration trimming value.
bogdanm 84:0b3ab51c8877 1030 * This parameter must be a number between 0 and 0xFF.
bogdanm 84:0b3ab51c8877 1031 */
bogdanm 84:0b3ab51c8877 1032 #define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICalibrationValue__) (MODIFY_REG(RCC->ICSCR,\
bogdanm 84:0b3ab51c8877 1033 RCC_ICSCR_MSITRIM, (uint32_t)(__MSICalibrationValue__) << 24))
bogdanm 84:0b3ab51c8877 1034
bogdanm 84:0b3ab51c8877 1035 /**
bogdanm 84:0b3ab51c8877 1036 * @brief Macro to configures the Internal Multi Speed oscillator (MSI) clock range.
bogdanm 84:0b3ab51c8877 1037 * @note After restart from Reset or wakeup from STANDBY, the MSI clock is
bogdanm 84:0b3ab51c8877 1038 * around 2.097 MHz. The MSI clock does not change after wake-up from
bogdanm 84:0b3ab51c8877 1039 * STOP mode.
bogdanm 84:0b3ab51c8877 1040 * @note The MSI clock range can be modified on the fly.
Kojto 119:aae6fcc7d9bb 1041 * @param __RCC_MSIRange__: specifies the MSI Clock range.
bogdanm 84:0b3ab51c8877 1042 * This parameter must be one of the following values:
bogdanm 84:0b3ab51c8877 1043 * @arg RCC_MSIRANGE_0: MSI clock is around 65.536 KHz
bogdanm 84:0b3ab51c8877 1044 * @arg RCC_MSIRANGE_1: MSI clock is around 131.072 KHz
bogdanm 84:0b3ab51c8877 1045 * @arg RCC_MSIRANGE_2: MSI clock is around 262.144 KHz
bogdanm 84:0b3ab51c8877 1046 * @arg RCC_MSIRANGE_3: MSI clock is around 524.288 KHz
bogdanm 84:0b3ab51c8877 1047 * @arg RCC_MSIRANGE_4: MSI clock is around 1.048 MHz
bogdanm 84:0b3ab51c8877 1048 * @arg RCC_MSIRANGE_5: MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY)
bogdanm 84:0b3ab51c8877 1049 * @arg RCC_MSIRANGE_6: MSI clock is around 4.194 MHz
bogdanm 84:0b3ab51c8877 1050 */
bogdanm 84:0b3ab51c8877 1051 #define __HAL_RCC_MSI_RANGE_CONFIG(__RCC_MSIRange__) (MODIFY_REG(RCC->ICSCR,\
bogdanm 84:0b3ab51c8877 1052 RCC_ICSCR_MSIRANGE, (uint32_t)(__RCC_MSIRange__) ))
Kojto 119:aae6fcc7d9bb 1053
Kojto 119:aae6fcc7d9bb 1054 /** @brief Macro to get the Internal Multi Speed oscillator (__MSI__) clock range in run mode
Kojto 119:aae6fcc7d9bb 1055 * @retval MSI clock range.
Kojto 119:aae6fcc7d9bb 1056 * This parameter must be one of the following values:
Kojto 119:aae6fcc7d9bb 1057 * @arg RCC_MSIRANGE_0: MSI clock is around 65.536 KHz
Kojto 119:aae6fcc7d9bb 1058 * @arg RCC_MSIRANGE_1: MSI clock is around 131.072 KHz
Kojto 119:aae6fcc7d9bb 1059 * @arg RCC_MSIRANGE_2: MSI clock is around 262.144 KHz
Kojto 119:aae6fcc7d9bb 1060 * @arg RCC_MSIRANGE_3: MSI clock is around 524.288 KHz
Kojto 119:aae6fcc7d9bb 1061 * @arg RCC_MSIRANGE_4: MSI clock is around 1.048 MHz
Kojto 119:aae6fcc7d9bb 1062 * @arg RCC_MSIRANGE_5: MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY)
Kojto 119:aae6fcc7d9bb 1063 * @arg RCC_MSIRANGE_6: MSI clock is around 4.194 MHz
Kojto 119:aae6fcc7d9bb 1064
Kojto 119:aae6fcc7d9bb 1065 */
Kojto 119:aae6fcc7d9bb 1066 #define __HAL_RCC_GET_MSI_RANGE() \
Kojto 119:aae6fcc7d9bb 1067 ((uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSIRANGE) >> 12))
bogdanm 84:0b3ab51c8877 1068
bogdanm 84:0b3ab51c8877 1069 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
bogdanm 84:0b3ab51c8877 1070 * @note After enabling the LSI, the application software should wait on
bogdanm 84:0b3ab51c8877 1071 * LSIRDY flag to be set indicating that LSI clock is stable and can
bogdanm 84:0b3ab51c8877 1072 * be used to clock the IWDG and/or the RTC.
bogdanm 84:0b3ab51c8877 1073 * @note LSI can not be disabled if the IWDG is running.
bogdanm 84:0b3ab51c8877 1074 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
bogdanm 84:0b3ab51c8877 1075 * clock cycles.
bogdanm 84:0b3ab51c8877 1076 */
Kojto 119:aae6fcc7d9bb 1077 #define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
bogdanm 84:0b3ab51c8877 1078 #define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
bogdanm 84:0b3ab51c8877 1079
bogdanm 84:0b3ab51c8877 1080 /**
bogdanm 84:0b3ab51c8877 1081 * @brief Macro to configure the External High Speed oscillator (HSE).
Kojto 119:aae6fcc7d9bb 1082 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
Kojto 119:aae6fcc7d9bb 1083 * supported by this macro. User should request a transition to HSE Off
Kojto 119:aae6fcc7d9bb 1084 * first and then HSE On or HSE Bypass.
bogdanm 84:0b3ab51c8877 1085 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
bogdanm 84:0b3ab51c8877 1086 * software should wait on HSERDY flag to be set indicating that HSE clock
bogdanm 84:0b3ab51c8877 1087 * is stable and can be used to clock the PLL and/or system clock.
bogdanm 84:0b3ab51c8877 1088 * @note HSE state can not be changed if it is used directly or through the
bogdanm 84:0b3ab51c8877 1089 * PLL as system clock. In this case, you have to select another source
bogdanm 84:0b3ab51c8877 1090 * of the system clock then change the HSE state (ex. disable it).
bogdanm 84:0b3ab51c8877 1091 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
bogdanm 84:0b3ab51c8877 1092 * @note This function reset the CSSON bit, so if the clock security system(CSS)
bogdanm 84:0b3ab51c8877 1093 * was previously enabled you have to enable it again after calling this
bogdanm 84:0b3ab51c8877 1094 * function.
bogdanm 84:0b3ab51c8877 1095 * @param __STATE__: specifies the new state of the HSE.
bogdanm 84:0b3ab51c8877 1096 * This parameter can be one of the following values:
bogdanm 84:0b3ab51c8877 1097 * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
bogdanm 84:0b3ab51c8877 1098 * 6 HSE oscillator clock cycles.
bogdanm 84:0b3ab51c8877 1099 * @arg RCC_HSE_ON: turn ON the HSE oscillator.
bogdanm 84:0b3ab51c8877 1100 * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
bogdanm 84:0b3ab51c8877 1101 */
bogdanm 84:0b3ab51c8877 1102 #define __HAL_RCC_HSE_CONFIG(__STATE__) \
Kojto 96:487b796308b0 1103 do { \
Kojto 119:aae6fcc7d9bb 1104 __IO uint32_t tmpreg; \
Kojto 96:487b796308b0 1105 if((__STATE__) == RCC_HSE_ON) \
Kojto 96:487b796308b0 1106 { \
Kojto 96:487b796308b0 1107 SET_BIT(RCC->CR, RCC_CR_HSEON); \
Kojto 96:487b796308b0 1108 } \
Kojto 96:487b796308b0 1109 else if((__STATE__) == RCC_HSE_BYPASS) \
Kojto 96:487b796308b0 1110 { \
Kojto 119:aae6fcc7d9bb 1111 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
Kojto 96:487b796308b0 1112 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
Kojto 96:487b796308b0 1113 SET_BIT(RCC->CR, RCC_CR_HSEON); \
Kojto 96:487b796308b0 1114 } \
Kojto 96:487b796308b0 1115 else \
Kojto 96:487b796308b0 1116 { \
Kojto 119:aae6fcc7d9bb 1117 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
Kojto 119:aae6fcc7d9bb 1118 /* Delay after an RCC peripheral clock */ \
Kojto 119:aae6fcc7d9bb 1119 tmpreg = READ_BIT(RCC->CR, RCC_CR_HSEON); \
Kojto 119:aae6fcc7d9bb 1120 UNUSED(tmpreg); \
Kojto 96:487b796308b0 1121 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
Kojto 96:487b796308b0 1122 } \
Kojto 96:487b796308b0 1123 } while(0)
Kojto 119:aae6fcc7d9bb 1124
bogdanm 84:0b3ab51c8877 1125 /**
bogdanm 84:0b3ab51c8877 1126 * @brief Macro to configure the External Low Speed oscillator (LSE).
Kojto 119:aae6fcc7d9bb 1127 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
Kojto 119:aae6fcc7d9bb 1128 * supported by this macro. User should request a transition to LSE Off
Kojto 119:aae6fcc7d9bb 1129 * first and then LSE On or LSE Bypass.
bogdanm 84:0b3ab51c8877 1130 * @note As the LSE is in the Backup domain and write access is denied to
Kojto 119:aae6fcc7d9bb 1131 * this domain after reset, you have to enable write access using
bogdanm 84:0b3ab51c8877 1132 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
Kojto 119:aae6fcc7d9bb 1133 * (to be done once after reset).
bogdanm 84:0b3ab51c8877 1134 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
bogdanm 84:0b3ab51c8877 1135 * software should wait on LSERDY flag to be set indicating that LSE clock
bogdanm 84:0b3ab51c8877 1136 * is stable and can be used to clock the RTC.
bogdanm 84:0b3ab51c8877 1137 * @param __STATE__: specifies the new state of the LSE.
bogdanm 84:0b3ab51c8877 1138 * This parameter can be one of the following values:
bogdanm 84:0b3ab51c8877 1139 * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
bogdanm 84:0b3ab51c8877 1140 * 6 LSE oscillator clock cycles.
bogdanm 84:0b3ab51c8877 1141 * @arg RCC_LSE_ON: turn ON the LSE oscillator.
bogdanm 84:0b3ab51c8877 1142 * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
bogdanm 84:0b3ab51c8877 1143 */
Kojto 119:aae6fcc7d9bb 1144 #define __HAL_RCC_LSE_CONFIG(__STATE__) \
Kojto 96:487b796308b0 1145 do { \
Kojto 96:487b796308b0 1146 if((__STATE__) == RCC_LSE_ON) \
Kojto 96:487b796308b0 1147 { \
Kojto 96:487b796308b0 1148 SET_BIT(RCC->CSR, RCC_CSR_LSEON); \
Kojto 96:487b796308b0 1149 } \
Kojto 96:487b796308b0 1150 else if((__STATE__) == RCC_LSE_OFF) \
Kojto 96:487b796308b0 1151 { \
Kojto 96:487b796308b0 1152 CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON); \
Kojto 119:aae6fcc7d9bb 1153 CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP); \
Kojto 96:487b796308b0 1154 } \
Kojto 96:487b796308b0 1155 else if((__STATE__) == RCC_LSE_BYPASS) \
Kojto 96:487b796308b0 1156 { \
Kojto 96:487b796308b0 1157 CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON); \
Kojto 96:487b796308b0 1158 SET_BIT(RCC->CSR, RCC_CSR_LSEBYP); \
Kojto 96:487b796308b0 1159 SET_BIT(RCC->CSR, RCC_CSR_LSEON); \
Kojto 96:487b796308b0 1160 } \
Kojto 96:487b796308b0 1161 else \
Kojto 96:487b796308b0 1162 { \
Kojto 96:487b796308b0 1163 CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON); \
Kojto 96:487b796308b0 1164 CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP); \
Kojto 96:487b796308b0 1165 } \
Kojto 96:487b796308b0 1166 } while(0)
bogdanm 84:0b3ab51c8877 1167
Kojto 119:aae6fcc7d9bb 1168
bogdanm 84:0b3ab51c8877 1169
bogdanm 84:0b3ab51c8877 1170 /**
bogdanm 84:0b3ab51c8877 1171 * @brief Configures or Get the RTC and LCD clock (RTCCLK / LCDCLK).
bogdanm 84:0b3ab51c8877 1172 * @note As the RTC clock configuration bits are in the RTC domain and write
bogdanm 84:0b3ab51c8877 1173 * access is denied to this domain after reset, you have to enable write
bogdanm 84:0b3ab51c8877 1174 * access using PWR_RTCAccessCmd(ENABLE) function before to configure
bogdanm 84:0b3ab51c8877 1175 * the RTC clock source (to be done once after reset).
Kojto 96:487b796308b0 1176 * @note Once the RTC clock is configured it cannot be changed unless the RTC
bogdanm 84:0b3ab51c8877 1177 * is reset using RCC_RTCResetCmd function, or by a Power On Reset (POR)
bogdanm 84:0b3ab51c8877 1178 * @note The RTC clock (RTCCLK) is used also to clock the LCD (LCDCLK).
bogdanm 84:0b3ab51c8877 1179 *
Kojto 119:aae6fcc7d9bb 1180 * @param __RTCCLKSOURCE__: specifies the RTC clock source.
bogdanm 84:0b3ab51c8877 1181 * This parameter can be one of the following values:
bogdanm 84:0b3ab51c8877 1182 * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
bogdanm 84:0b3ab51c8877 1183 * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
bogdanm 84:0b3ab51c8877 1184 * @arg RCC_RTCCLKSOURCE_HSE_DIV2: HSE divided by 2 selected as RTC clock
bogdanm 84:0b3ab51c8877 1185 * @arg RCC_RTCCLKSOURCE_HSE_DIV4: HSE divided by 4 selected as RTC clock
bogdanm 84:0b3ab51c8877 1186 * @arg RCC_RTCCLKSOURCE_HSE_DIV8: HSE divided by 8 selected as RTC clock
bogdanm 84:0b3ab51c8877 1187 * @arg RCC_RTCCLKSOURCE_HSE_DIV16: HSE divided by 16 selected as RTC clock
bogdanm 84:0b3ab51c8877 1188 *
bogdanm 84:0b3ab51c8877 1189 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
bogdanm 84:0b3ab51c8877 1190 * work in STOP and STANDBY modes, and can be used as wakeup source.
bogdanm 84:0b3ab51c8877 1191 * However, when the HSE clock is used as RTC clock source, the RTC
bogdanm 84:0b3ab51c8877 1192 * cannot be used in STOP and STANDBY modes.
bogdanm 84:0b3ab51c8877 1193 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
bogdanm 84:0b3ab51c8877 1194 * RTC clock source).
bogdanm 84:0b3ab51c8877 1195 */
Kojto 119:aae6fcc7d9bb 1196
Kojto 119:aae6fcc7d9bb 1197 #define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSOURCE__) (((__RTCCLKSOURCE__) & RCC_CSR_RTCSEL) == RCC_CSR_RTCSEL) ? \
Kojto 119:aae6fcc7d9bb 1198 MODIFY_REG(RCC->CR, RCC_CR_RTCPRE, (uint32_t)((__RTCCLKSOURCE__) & RCC_CR_RTCPRE)) : \
Kojto 119:aae6fcc7d9bb 1199 CLEAR_BIT(RCC->CR, RCC_CR_RTCPRE)
bogdanm 84:0b3ab51c8877 1200
Kojto 119:aae6fcc7d9bb 1201 #define __HAL_RCC_RTC_CONFIG(__RTCCLKSOURCE__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSOURCE__); \
Kojto 119:aae6fcc7d9bb 1202 MODIFY_REG( RCC->CSR, RCC_CSR_RTCSEL, (uint32_t)((__RTCCLKSOURCE__) & RCC_CSR_RTCSEL)); \
bogdanm 84:0b3ab51c8877 1203 } while (0)
bogdanm 84:0b3ab51c8877 1204
Kojto 119:aae6fcc7d9bb 1205
Kojto 119:aae6fcc7d9bb 1206 /**
Kojto 119:aae6fcc7d9bb 1207 * @brief Get the RTC and LCD clock (RTCCLK / LCDCLK).
Kojto 119:aae6fcc7d9bb 1208 *
Kojto 119:aae6fcc7d9bb 1209 * @retval The clock source can be one of the following values:
Kojto 119:aae6fcc7d9bb 1210 * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
Kojto 119:aae6fcc7d9bb 1211 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
Kojto 119:aae6fcc7d9bb 1212 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
Kojto 119:aae6fcc7d9bb 1213 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER()
Kojto 119:aae6fcc7d9bb 1214 *
Kojto 119:aae6fcc7d9bb 1215 */
bogdanm 92:4fc01daae5a5 1216 #define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_RTCSEL)))
Kojto 119:aae6fcc7d9bb 1217
Kojto 119:aae6fcc7d9bb 1218 /**
Kojto 119:aae6fcc7d9bb 1219 * @brief Get the RTC and LCD HSE clock divider (RTCCLK / LCDCLK).
Kojto 119:aae6fcc7d9bb 1220 *
Kojto 119:aae6fcc7d9bb 1221 * @retval Returned value can be one of the following values:
Kojto 119:aae6fcc7d9bb 1222 * @arg @ref RCC_RTC_HSE_DIV_2: HSE divided by 2 selected as RTC clock
Kojto 119:aae6fcc7d9bb 1223 * @arg @ref RCC_RTC_HSE_DIV_4: HSE divided by 4 selected as RTC clock
Kojto 119:aae6fcc7d9bb 1224 * @arg @ref RCC_RTC_HSE_DIV_8: HSE divided by 8 selected as RTC clock
Kojto 119:aae6fcc7d9bb 1225 * @arg @ref RCC_RTC_HSE_DIV_16: HSE divided by 16 selected as RTC clock
Kojto 119:aae6fcc7d9bb 1226 *
bogdanm 84:0b3ab51c8877 1227 */
Kojto 119:aae6fcc7d9bb 1228 #define __HAL_RCC_GET_RTC_HSE_PRESCALER() ((uint32_t)(READ_BIT(RCC->CR, RCC_CR_RTCPRE)))
bogdanm 84:0b3ab51c8877 1229
bogdanm 84:0b3ab51c8877 1230 /** @brief Macros to enable or disable the main PLL.
bogdanm 84:0b3ab51c8877 1231 * @note After enabling the main PLL, the application software should wait on
bogdanm 84:0b3ab51c8877 1232 * PLLRDY flag to be set indicating that PLL clock is stable and can
bogdanm 84:0b3ab51c8877 1233 * be used as system clock source.
bogdanm 84:0b3ab51c8877 1234 * @note The main PLL can not be disabled if it is used as system clock source
bogdanm 84:0b3ab51c8877 1235 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
bogdanm 84:0b3ab51c8877 1236 */
Kojto 119:aae6fcc7d9bb 1237 #define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
bogdanm 84:0b3ab51c8877 1238 #define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
bogdanm 84:0b3ab51c8877 1239
bogdanm 84:0b3ab51c8877 1240 /** @brief Macro to configure the main PLL clock source, multiplication and division factors.
bogdanm 84:0b3ab51c8877 1241 * @note This function must be used only when the main PLL is disabled.
Kojto 119:aae6fcc7d9bb 1242 * @param __RCC_PLLSOURCE__: specifies the PLL entry clock source.
bogdanm 84:0b3ab51c8877 1243 * This parameter can be one of the following values:
bogdanm 84:0b3ab51c8877 1244 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
bogdanm 84:0b3ab51c8877 1245 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
bogdanm 84:0b3ab51c8877 1246 * @param __PLLMUL__: specifies the multiplication factor to generate the PLL VCO clock
bogdanm 84:0b3ab51c8877 1247 * This parameter must be one of the following values:
bogdanm 84:0b3ab51c8877 1248 * @arg RCC_CFGR_PLLMUL3: PLLVCO = PLL clock entry x 3
bogdanm 84:0b3ab51c8877 1249 * @arg RCC_CFGR_PLLMUL4: PLLVCO = PLL clock entry x 4
bogdanm 84:0b3ab51c8877 1250 * @arg RCC_CFGR_PLLMUL6: PLLVCO = PLL clock entry x 6
bogdanm 84:0b3ab51c8877 1251 * @arg RCC_CFGR_PLLMUL8: PLLVCO = PLL clock entry x 8
bogdanm 84:0b3ab51c8877 1252 * @arg RCC_CFGR_PLLMUL12: PLLVCO = PLL clock entry x 12
bogdanm 84:0b3ab51c8877 1253 * @arg RCC_CFGR_PLLMUL16: PLLVCO = PLL clock entry x 16
bogdanm 84:0b3ab51c8877 1254 * @arg RCC_CFGR_PLLMUL24: PLLVCO = PLL clock entry x 24
bogdanm 84:0b3ab51c8877 1255 * @arg RCC_CFGR_PLLMUL32: PLLVCO = PLL clock entry x 32
bogdanm 84:0b3ab51c8877 1256 * @arg RCC_CFGR_PLLMUL48: PLLVCO = PLL clock entry x 48
bogdanm 84:0b3ab51c8877 1257 * @note The PLL VCO clock frequency must not exceed 96 MHz when the product is in
bogdanm 84:0b3ab51c8877 1258 * Range 1, 48 MHz when the product is in Range 2 and 24 MHz when the product is
bogdanm 84:0b3ab51c8877 1259 * in Range 3.
bogdanm 84:0b3ab51c8877 1260 * @param __PLLDIV__: specifies the PLL output clock division from PLL VCO clock
bogdanm 84:0b3ab51c8877 1261 * This parameter must be one of the following values:
bogdanm 84:0b3ab51c8877 1262 * @arg RCC_PLLDIV_2: PLL clock output = PLLVCO / 2
bogdanm 84:0b3ab51c8877 1263 * @arg RCC_PLLDIV_3: PLL clock output = PLLVCO / 3
bogdanm 84:0b3ab51c8877 1264 * @arg RCC_PLLDIV_4: PLL clock output = PLLVCO / 4
bogdanm 84:0b3ab51c8877 1265 */
bogdanm 84:0b3ab51c8877 1266
Kojto 119:aae6fcc7d9bb 1267 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__ , __PLLMUL__ ,__PLLDIV__ ) \
Kojto 119:aae6fcc7d9bb 1268 MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLDIV | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)| (__PLLDIV__)| (__RCC_PLLSOURCE__)))
bogdanm 84:0b3ab51c8877 1269
Kojto 119:aae6fcc7d9bb 1270 /** @brief Macro to get the oscillator used as PLL clock source.
bogdanm 84:0b3ab51c8877 1271 * @retval The oscillator used as PLL clock source. The returned value can be one
bogdanm 84:0b3ab51c8877 1272 * of the following:
bogdanm 84:0b3ab51c8877 1273 * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
bogdanm 84:0b3ab51c8877 1274 * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
bogdanm 84:0b3ab51c8877 1275 */
bogdanm 84:0b3ab51c8877 1276 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC))
bogdanm 84:0b3ab51c8877 1277
Kojto 119:aae6fcc7d9bb 1278 /**
Kojto 119:aae6fcc7d9bb 1279 * @brief Macro to configure the system clock source.
Kojto 119:aae6fcc7d9bb 1280 * @param __SYSCLKSOURCE__: specifies the system clock source.
Kojto 119:aae6fcc7d9bb 1281 * This parameter can be one of the following values:
Kojto 119:aae6fcc7d9bb 1282 * - RCC_SYSCLKSOURCE_MSI: MSI oscillator is used as system clock source.
Kojto 119:aae6fcc7d9bb 1283 * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
Kojto 119:aae6fcc7d9bb 1284 * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
Kojto 119:aae6fcc7d9bb 1285 * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
Kojto 119:aae6fcc7d9bb 1286 * @retval None
Kojto 119:aae6fcc7d9bb 1287 */
Kojto 119:aae6fcc7d9bb 1288 #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
Kojto 119:aae6fcc7d9bb 1289 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
Kojto 119:aae6fcc7d9bb 1290
Kojto 119:aae6fcc7d9bb 1291 /** @brief Macro to get the clock source used as system clock.
Kojto 119:aae6fcc7d9bb 1292 * @retval The clock source used as system clock. The returned value can be one
Kojto 119:aae6fcc7d9bb 1293 * of the following:
Kojto 119:aae6fcc7d9bb 1294 * - RCC_SYSCLKSOURCE_STATUS_MSI: MSI used as system clock.
Kojto 119:aae6fcc7d9bb 1295 * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
Kojto 119:aae6fcc7d9bb 1296 * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
Kojto 119:aae6fcc7d9bb 1297 * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
Kojto 119:aae6fcc7d9bb 1298 */
Kojto 119:aae6fcc7d9bb 1299 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
Kojto 119:aae6fcc7d9bb 1300
Kojto 119:aae6fcc7d9bb 1301
Kojto 119:aae6fcc7d9bb 1302 /** @brief Macro to configure the MCO clock.
Kojto 119:aae6fcc7d9bb 1303 * @param __MCOCLKSOURCE__ specifies the MCO clock source.
Kojto 119:aae6fcc7d9bb 1304 * This parameter can be one of the following values:
Kojto 119:aae6fcc7d9bb 1305 * @arg RCC_CFGR_MCO_HSI: HSI clock selected as MCO source
Kojto 119:aae6fcc7d9bb 1306 * @arg RCC_CFGR_MCO_MSI: MSI clock selected as MCO source
Kojto 119:aae6fcc7d9bb 1307 * @arg RCC_CFGR_MCO_HSE: HSE clock selected as MCO source
Kojto 119:aae6fcc7d9bb 1308 * @arg RCC_CFGR_MCO_PLL: PLL clock selected as MCO source
Kojto 119:aae6fcc7d9bb 1309 * @arg RCC_CFGR_MCO_LSI: LSI clock selected as MCO source
Kojto 119:aae6fcc7d9bb 1310 * @arg RCC_CFGR_MCO_LSE: LSE clock selected as MCO source
Kojto 119:aae6fcc7d9bb 1311 * @param __MCODIV__ specifies the MCO clock prescaler.
Kojto 119:aae6fcc7d9bb 1312 * This parameter can be one of the following values:
Kojto 119:aae6fcc7d9bb 1313 * @arg RCC_CFGR_MCO_PRE_1: no division applied to MCO clock
Kojto 119:aae6fcc7d9bb 1314 * @arg RCC_CFGR_MCO_PRE_2: division by 2 applied to MCO clock
Kojto 119:aae6fcc7d9bb 1315 * @arg RCC_CFGR_MCO_PRE_4: division by 4 applied to MCO clock
Kojto 119:aae6fcc7d9bb 1316 * @arg RCC_CFGR_MCO_PRE_8: division by 8 applied to MCO clock
Kojto 119:aae6fcc7d9bb 1317 * @arg RCC_CFGR_MCO_PRE_16: division by 16 applied to MCO clock
Kojto 119:aae6fcc7d9bb 1318 */
Kojto 119:aae6fcc7d9bb 1319
Kojto 119:aae6fcc7d9bb 1320 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
Kojto 119:aae6fcc7d9bb 1321 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCO_PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
Kojto 119:aae6fcc7d9bb 1322
Kojto 119:aae6fcc7d9bb 1323
Kojto 119:aae6fcc7d9bb 1324 /** @defgroup RCC_Flags_Interrupts_Management RCC Flags Interrupts Management
bogdanm 84:0b3ab51c8877 1325 * @brief macros to manage the specified RCC Flags and interrupts.
bogdanm 84:0b3ab51c8877 1326 * @{
bogdanm 84:0b3ab51c8877 1327 */
bogdanm 84:0b3ab51c8877 1328
bogdanm 84:0b3ab51c8877 1329 /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIER[0:7] bits to enable
bogdanm 84:0b3ab51c8877 1330 * the selected interrupts).
bogdanm 84:0b3ab51c8877 1331 * @note The CSS interrupt doesn't have an enable bit; once the CSS is enabled
bogdanm 84:0b3ab51c8877 1332 * and if the HSE clock fails, the CSS interrupt occurs and an NMI is
bogdanm 84:0b3ab51c8877 1333 * automatically generated. The NMI will be executed indefinitely, and
bogdanm 84:0b3ab51c8877 1334 * since NMI has higher priority than any other IRQ (and main program)
bogdanm 84:0b3ab51c8877 1335 * the application will be stacked in the NMI ISR unless the CSS interrupt
bogdanm 84:0b3ab51c8877 1336 * pending bit is cleared.
bogdanm 84:0b3ab51c8877 1337 * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
bogdanm 84:0b3ab51c8877 1338 * This parameter can be any combination of the following values:
bogdanm 84:0b3ab51c8877 1339 * @arg RCC_IT_LSIRDY: LSI ready interrupt
bogdanm 84:0b3ab51c8877 1340 * @arg RCC_IT_LSERDY: LSE ready interrupt
bogdanm 84:0b3ab51c8877 1341 * @arg RCC_IT_HSIRDY: HSI ready interrupt
bogdanm 84:0b3ab51c8877 1342 * @arg RCC_IT_HSERDY: HSE ready interrupt
bogdanm 84:0b3ab51c8877 1343 * @arg RCC_IT_PLLRDY: PLL ready interrupt
bogdanm 84:0b3ab51c8877 1344 * @arg RCC_IT_MSIRDY: MSI ready interrupt
Kojto 119:aae6fcc7d9bb 1345 * @arg RCC_IT_CSSLSE: LSE CSS interrupt
Kojto 96:487b796308b0 1346 * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt
bogdanm 84:0b3ab51c8877 1347 */
Kojto 119:aae6fcc7d9bb 1348 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
bogdanm 84:0b3ab51c8877 1349
bogdanm 84:0b3ab51c8877 1350 /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIER[0:7] bits to disable
bogdanm 84:0b3ab51c8877 1351 * the selected interrupts).
bogdanm 84:0b3ab51c8877 1352 * @note The CSS interrupt doesn't have an enable bit; once the CSS is enabled
bogdanm 84:0b3ab51c8877 1353 * and if the HSE clock fails, the CSS interrupt occurs and an NMI is
bogdanm 84:0b3ab51c8877 1354 * automatically generated. The NMI will be executed indefinitely, and
bogdanm 84:0b3ab51c8877 1355 * since NMI has higher priority than any other IRQ (and main program)
bogdanm 84:0b3ab51c8877 1356 * the application will be stacked in the NMI ISR unless the CSS interrupt
bogdanm 84:0b3ab51c8877 1357 * pending bit is cleared.
bogdanm 84:0b3ab51c8877 1358 * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
bogdanm 84:0b3ab51c8877 1359 * This parameter can be any combination of the following values:
bogdanm 84:0b3ab51c8877 1360 * @arg RCC_IT_LSIRDY: LSI ready interrupt
bogdanm 84:0b3ab51c8877 1361 * @arg RCC_IT_LSERDY: LSE ready interrupt
bogdanm 84:0b3ab51c8877 1362 * @arg RCC_IT_HSIRDY: HSI ready interrupt
bogdanm 84:0b3ab51c8877 1363 * @arg RCC_IT_HSERDY: HSE ready interrupt
bogdanm 84:0b3ab51c8877 1364 * @arg RCC_IT_PLLRDY: PLL ready interrupt
bogdanm 84:0b3ab51c8877 1365 * @arg RCC_IT_MSIRDY: MSI ready interrupt
Kojto 96:487b796308b0 1366 * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt
Kojto 119:aae6fcc7d9bb 1367 * @arg RCC_IT_CSSLSE: LSE CSS interrupt
Kojto 96:487b796308b0 1368
bogdanm 84:0b3ab51c8877 1369 */
Kojto 119:aae6fcc7d9bb 1370 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
bogdanm 84:0b3ab51c8877 1371
bogdanm 84:0b3ab51c8877 1372 /** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
bogdanm 84:0b3ab51c8877 1373 * bits to clear the selected interrupt pending bits.
bogdanm 84:0b3ab51c8877 1374 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
bogdanm 84:0b3ab51c8877 1375 * This parameter can be any combination of the following values:
bogdanm 84:0b3ab51c8877 1376 * @arg RCC_IT_LSIRDY: LSI ready interrupt
bogdanm 84:0b3ab51c8877 1377 * @arg RCC_IT_LSERDY: LSE ready interrupt
bogdanm 84:0b3ab51c8877 1378 * @arg RCC_IT_HSIRDY: HSI ready interrupt
bogdanm 84:0b3ab51c8877 1379 * @arg RCC_IT_HSERDY: HSE ready interrupt
bogdanm 84:0b3ab51c8877 1380 * @arg RCC_IT_PLLRDY: PLL ready interrupt
Kojto 96:487b796308b0 1381 * @arg RCC_IT_MSIRDY: MSI ready interrupt
Kojto 96:487b796308b0 1382 * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt
Kojto 119:aae6fcc7d9bb 1383 * @arg RCC_IT_CSSLSE: LSE CSS interrupt
Kojto 119:aae6fcc7d9bb 1384 * @arg RCC_IT_CSSHSE: Clock Security System interrupt
bogdanm 84:0b3ab51c8877 1385 */
bogdanm 92:4fc01daae5a5 1386 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))
bogdanm 84:0b3ab51c8877 1387
bogdanm 84:0b3ab51c8877 1388 /** @brief Check the RCC's interrupt has occurred or not.
bogdanm 84:0b3ab51c8877 1389 * @param __INTERRUPT__: specifies the RCC interrupt source to check.
bogdanm 84:0b3ab51c8877 1390 * This parameter can be one of the following values:
bogdanm 84:0b3ab51c8877 1391 * @arg RCC_IT_LSIRDY: LSI ready interrupt
bogdanm 84:0b3ab51c8877 1392 * @arg RCC_IT_LSERDY: LSE ready interrupt
bogdanm 84:0b3ab51c8877 1393 * @arg RCC_IT_HSIRDY: HSI ready interrupt
bogdanm 84:0b3ab51c8877 1394 * @arg RCC_IT_HSERDY: HSE ready interrupt
bogdanm 84:0b3ab51c8877 1395 * @arg RCC_IT_PLLRDY: PLL ready interrupt
bogdanm 84:0b3ab51c8877 1396 * @arg RCC_IT_MSIRDY: MSI ready interrupt
Kojto 119:aae6fcc7d9bb 1397 * @arg RCC_IT_CSSLSE: LSE CSS interrupt
Kojto 119:aae6fcc7d9bb 1398 * @arg RCC_IT_CSSHSE: Clock Security System interrupt
bogdanm 84:0b3ab51c8877 1399 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
bogdanm 84:0b3ab51c8877 1400 */
Kojto 119:aae6fcc7d9bb 1401 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
Kojto 119:aae6fcc7d9bb 1402
bogdanm 84:0b3ab51c8877 1403
bogdanm 84:0b3ab51c8877 1404 /** @brief Set RMVF bit to clear the reset flags.
bogdanm 84:0b3ab51c8877 1405 * The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST,
bogdanm 84:0b3ab51c8877 1406 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST.
bogdanm 84:0b3ab51c8877 1407 */
bogdanm 84:0b3ab51c8877 1408 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
bogdanm 84:0b3ab51c8877 1409
bogdanm 84:0b3ab51c8877 1410 /** @brief Check RCC flag is set or not.
bogdanm 84:0b3ab51c8877 1411 * @param __FLAG__: specifies the flag to check.
bogdanm 84:0b3ab51c8877 1412 * This parameter can be one of the following values:
bogdanm 84:0b3ab51c8877 1413 * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
Kojto 119:aae6fcc7d9bb 1414 * @arg RCC_FLAG_HSIDIV: HSI clock divider flag
bogdanm 84:0b3ab51c8877 1415 * @arg RCC_FLAG_MSIRDY: MSI oscillator clock ready
bogdanm 84:0b3ab51c8877 1416 * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
bogdanm 84:0b3ab51c8877 1417 * @arg RCC_FLAG_PLLRDY: PLL clock ready
bogdanm 84:0b3ab51c8877 1418 * @arg RCC_FLAG_LSECSS: LSE oscillator clock CSS detected
bogdanm 84:0b3ab51c8877 1419 * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
bogdanm 84:0b3ab51c8877 1420 * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
Kojto 96:487b796308b0 1421 * @arg RCC_FLAG_FWRST: Firewall reset
bogdanm 84:0b3ab51c8877 1422 * @arg RCC_FLAG_OBLRST: Option Byte Loader (OBL) reset
bogdanm 84:0b3ab51c8877 1423 * @arg RCC_FLAG_PINRST: Pin reset
bogdanm 84:0b3ab51c8877 1424 * @arg RCC_FLAG_PORRST: POR/PDR reset
bogdanm 84:0b3ab51c8877 1425 * @arg RCC_FLAG_SFTRST: Software reset
bogdanm 84:0b3ab51c8877 1426 * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
bogdanm 84:0b3ab51c8877 1427 * @arg RCC_FLAG_WWDGRST: Window Watchdog reset
bogdanm 84:0b3ab51c8877 1428 * @arg RCC_FLAG_LPWRRST: Low Power reset
bogdanm 84:0b3ab51c8877 1429 * @retval The new state of __FLAG__ (TRUE or FALSE).
bogdanm 84:0b3ab51c8877 1430 */
bogdanm 84:0b3ab51c8877 1431 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->CSR :((((__FLAG__) >> 5) == 3)? \
bogdanm 84:0b3ab51c8877 1432 RCC->CRRCR :RCC->CIFR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK))) != 0 ) ? 1 : 0 )
bogdanm 84:0b3ab51c8877 1433
bogdanm 84:0b3ab51c8877 1434 /**
bogdanm 84:0b3ab51c8877 1435 * @}
bogdanm 84:0b3ab51c8877 1436 */
bogdanm 84:0b3ab51c8877 1437
bogdanm 84:0b3ab51c8877 1438 /**
Kojto 96:487b796308b0 1439 * @}
Kojto 96:487b796308b0 1440 */
bogdanm 84:0b3ab51c8877 1441
Kojto 119:aae6fcc7d9bb 1442
Kojto 119:aae6fcc7d9bb 1443 /* Private constants ---------------------------------------------------------*/
Kojto 119:aae6fcc7d9bb 1444 /** @defgroup RCC_Private_Constants RCC Private Constants
Kojto 119:aae6fcc7d9bb 1445 * @{
Kojto 119:aae6fcc7d9bb 1446 */
Kojto 119:aae6fcc7d9bb 1447 /* Defines used for Flags */
Kojto 119:aae6fcc7d9bb 1448 #define RCC_FLAG_MASK ((uint8_t)0x1F)
Kojto 119:aae6fcc7d9bb 1449
Kojto 119:aae6fcc7d9bb 1450 /**
Kojto 119:aae6fcc7d9bb 1451 * @}
Kojto 119:aae6fcc7d9bb 1452 */
Kojto 119:aae6fcc7d9bb 1453
Kojto 119:aae6fcc7d9bb 1454 /* Private macros ------------------------------------------------------------*/
Kojto 119:aae6fcc7d9bb 1455 /** @addtogroup RCC_Private_Macros
Kojto 119:aae6fcc7d9bb 1456 * @{
Kojto 119:aae6fcc7d9bb 1457 */
Kojto 119:aae6fcc7d9bb 1458
Kojto 119:aae6fcc7d9bb 1459 #if !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
Kojto 119:aae6fcc7d9bb 1460 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) ((__OSCILLATOR__) <= 0x3F)
Kojto 119:aae6fcc7d9bb 1461 #else
Kojto 119:aae6fcc7d9bb 1462 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) ((__OSCILLATOR__) <= 0x1F)
Kojto 119:aae6fcc7d9bb 1463 #endif /* !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) */
Kojto 119:aae6fcc7d9bb 1464
Kojto 119:aae6fcc7d9bb 1465 #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
Kojto 119:aae6fcc7d9bb 1466 ((__HSE__) == RCC_HSE_BYPASS))
Kojto 119:aae6fcc7d9bb 1467 #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
Kojto 119:aae6fcc7d9bb 1468 ((__LSE__) == RCC_LSE_BYPASS))
Kojto 119:aae6fcc7d9bb 1469
Kojto 119:aae6fcc7d9bb 1470 #define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) || \
Kojto 119:aae6fcc7d9bb 1471 ((__RANGE__) == RCC_MSIRANGE_1) || \
Kojto 119:aae6fcc7d9bb 1472 ((__RANGE__) == RCC_MSIRANGE_2) || \
Kojto 119:aae6fcc7d9bb 1473 ((__RANGE__) == RCC_MSIRANGE_3) || \
Kojto 119:aae6fcc7d9bb 1474 ((__RANGE__) == RCC_MSIRANGE_4) || \
Kojto 119:aae6fcc7d9bb 1475 ((__RANGE__) == RCC_MSIRANGE_5) || \
Kojto 119:aae6fcc7d9bb 1476 ((__RANGE__) == RCC_MSIRANGE_6))
Kojto 119:aae6fcc7d9bb 1477
Kojto 119:aae6fcc7d9bb 1478 #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
Kojto 119:aae6fcc7d9bb 1479 #define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON))
Kojto 119:aae6fcc7d9bb 1480 #define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON))
Kojto 119:aae6fcc7d9bb 1481
Kojto 119:aae6fcc7d9bb 1482 #define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) ||((__PLL__) == RCC_PLL_OFF) || ((__PLL__) == RCC_PLL_ON))
Kojto 119:aae6fcc7d9bb 1483
Kojto 119:aae6fcc7d9bb 1484 #define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI) || \
Kojto 119:aae6fcc7d9bb 1485 ((__SOURCE__) == RCC_PLLSOURCE_HSE))
Kojto 119:aae6fcc7d9bb 1486
Kojto 119:aae6fcc7d9bb 1487 #define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLLMUL_3) || ((__MUL__) == RCC_PLLMUL_4) || \
Kojto 119:aae6fcc7d9bb 1488 ((__MUL__) == RCC_PLLMUL_6) || ((__MUL__) == RCC_PLLMUL_8) || \
Kojto 119:aae6fcc7d9bb 1489 ((__MUL__) == RCC_PLLMUL_12) || ((__MUL__) == RCC_PLLMUL_16) || \
Kojto 119:aae6fcc7d9bb 1490 ((__MUL__) == RCC_PLLMUL_24) || ((__MUL__) == RCC_PLLMUL_32) || \
Kojto 119:aae6fcc7d9bb 1491 ((__MUL__) == RCC_PLLMUL_48))
Kojto 119:aae6fcc7d9bb 1492
Kojto 119:aae6fcc7d9bb 1493 #define IS_RCC_PLL_DIV(__DIV__) (((__DIV__) == RCC_PLLDIV_2) || ((__DIV__) == RCC_PLLDIV_3) || \
Kojto 119:aae6fcc7d9bb 1494 ((__DIV__) == RCC_PLLDIV_4))
Kojto 119:aae6fcc7d9bb 1495
Kojto 119:aae6fcc7d9bb 1496 #define IS_RCC_CLOCKTYPE(__CLK__) ((1 <= (__CLK__)) && ((__CLK__) <= 15))
Kojto 119:aae6fcc7d9bb 1497
Kojto 119:aae6fcc7d9bb 1498 #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \
Kojto 119:aae6fcc7d9bb 1499 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
Kojto 119:aae6fcc7d9bb 1500 ((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) || \
Kojto 119:aae6fcc7d9bb 1501 ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
Kojto 119:aae6fcc7d9bb 1502
Kojto 119:aae6fcc7d9bb 1503 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \
Kojto 119:aae6fcc7d9bb 1504 ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \
Kojto 119:aae6fcc7d9bb 1505 ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \
Kojto 119:aae6fcc7d9bb 1506 ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
Kojto 119:aae6fcc7d9bb 1507 ((__HCLK__) == RCC_SYSCLK_DIV512))
Kojto 119:aae6fcc7d9bb 1508
Kojto 119:aae6fcc7d9bb 1509 #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
Kojto 119:aae6fcc7d9bb 1510 ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
Kojto 119:aae6fcc7d9bb 1511 ((__PCLK__) == RCC_HCLK_DIV16))
Kojto 119:aae6fcc7d9bb 1512
Kojto 119:aae6fcc7d9bb 1513 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
Kojto 119:aae6fcc7d9bb 1514 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
Kojto 119:aae6fcc7d9bb 1515 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) || \
Kojto 119:aae6fcc7d9bb 1516 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) || \
Kojto 119:aae6fcc7d9bb 1517 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) || \
Kojto 119:aae6fcc7d9bb 1518 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16))
Kojto 119:aae6fcc7d9bb 1519
Kojto 119:aae6fcc7d9bb 1520 #if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) \
Kojto 119:aae6fcc7d9bb 1521 && !defined (STM32L011xx) && !defined (STM32L021xx)
Kojto 119:aae6fcc7d9bb 1522 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \
Kojto 119:aae6fcc7d9bb 1523 ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \
Kojto 119:aae6fcc7d9bb 1524 ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \
Kojto 119:aae6fcc7d9bb 1525 ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \
Kojto 119:aae6fcc7d9bb 1526 ((__SOURCE__) == RCC_MCO1SOURCE_HSI48))
Kojto 119:aae6fcc7d9bb 1527 #else
Kojto 119:aae6fcc7d9bb 1528 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \
Kojto 119:aae6fcc7d9bb 1529 ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \
Kojto 119:aae6fcc7d9bb 1530 ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \
Kojto 119:aae6fcc7d9bb 1531 ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || ((__SOURCE__) == RCC_MCO1SOURCE_LSE))
Kojto 119:aae6fcc7d9bb 1532 #endif
Kojto 119:aae6fcc7d9bb 1533
Kojto 119:aae6fcc7d9bb 1534 #define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || \
Kojto 119:aae6fcc7d9bb 1535 ((__DIV__) == RCC_MCODIV_2) || \
Kojto 119:aae6fcc7d9bb 1536 ((__DIV__) == RCC_MCODIV_4) || \
Kojto 119:aae6fcc7d9bb 1537 ((__DIV__) == RCC_MCODIV_8) || \
Kojto 119:aae6fcc7d9bb 1538 ((__DIV__) == RCC_MCODIV_16))
Kojto 119:aae6fcc7d9bb 1539
Kojto 119:aae6fcc7d9bb 1540 #if defined(STM32L031xx) || defined(STM32L041xx) || defined(STM32L073xx) || defined(STM32L083xx) || \
Kojto 119:aae6fcc7d9bb 1541 defined(STM32L072xx) || defined(STM32L082xx) || defined(STM32L071xx) || defined(STM32L081xx)
Kojto 119:aae6fcc7d9bb 1542 #define IS_RCC_MCO(__MCOx__) (((__MCOx__) == RCC_MCO1) || ((__MCOx__) == RCC_MCO2) || ((__MCOx__) == RCC_MCO3))
Kojto 119:aae6fcc7d9bb 1543 #else
Kojto 119:aae6fcc7d9bb 1544 #define IS_RCC_MCO(__MCOx__) (((__MCOx__) == RCC_MCO1) || ((__MCOx__) == RCC_MCO2))
Kojto 119:aae6fcc7d9bb 1545
Kojto 119:aae6fcc7d9bb 1546 #endif
Kojto 119:aae6fcc7d9bb 1547
Kojto 119:aae6fcc7d9bb 1548 #define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1F)
Kojto 119:aae6fcc7d9bb 1549 #define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0xFF)
Kojto 119:aae6fcc7d9bb 1550
Kojto 119:aae6fcc7d9bb 1551 /**
Kojto 119:aae6fcc7d9bb 1552 * @}
Kojto 119:aae6fcc7d9bb 1553 */
Kojto 119:aae6fcc7d9bb 1554
bogdanm 84:0b3ab51c8877 1555 /* Include RCC HAL Extension module */
bogdanm 85:024bf7f99721 1556 #include "stm32l0xx_hal_rcc_ex.h"
bogdanm 84:0b3ab51c8877 1557
Kojto 96:487b796308b0 1558 /** @defgroup RCC_Exported_Functions RCC Exported Functions
Kojto 96:487b796308b0 1559 * @{
Kojto 96:487b796308b0 1560 */
Kojto 96:487b796308b0 1561
Kojto 96:487b796308b0 1562 /** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
Kojto 96:487b796308b0 1563 * @{
Kojto 96:487b796308b0 1564 */
bogdanm 84:0b3ab51c8877 1565 void HAL_RCC_DeInit(void);
bogdanm 84:0b3ab51c8877 1566 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
bogdanm 84:0b3ab51c8877 1567 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
Kojto 96:487b796308b0 1568 /**
Kojto 96:487b796308b0 1569 * @}
Kojto 96:487b796308b0 1570 */
bogdanm 84:0b3ab51c8877 1571
Kojto 96:487b796308b0 1572 /** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
Kojto 96:487b796308b0 1573 * @{
Kojto 96:487b796308b0 1574 */
bogdanm 84:0b3ab51c8877 1575 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
Kojto 119:aae6fcc7d9bb 1576 #if !defined (STM32L011xx) && !defined (STM32L021xx)
bogdanm 84:0b3ab51c8877 1577 void HAL_RCC_EnableCSS(void);
Kojto 119:aae6fcc7d9bb 1578 #endif
bogdanm 84:0b3ab51c8877 1579 uint32_t HAL_RCC_GetSysClockFreq(void);
bogdanm 84:0b3ab51c8877 1580 uint32_t HAL_RCC_GetHCLKFreq(void);
bogdanm 84:0b3ab51c8877 1581 uint32_t HAL_RCC_GetPCLK1Freq(void);
bogdanm 84:0b3ab51c8877 1582 uint32_t HAL_RCC_GetPCLK2Freq(void);
bogdanm 84:0b3ab51c8877 1583 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
bogdanm 84:0b3ab51c8877 1584 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
bogdanm 84:0b3ab51c8877 1585 /* CSS NMI IRQ handler */
bogdanm 84:0b3ab51c8877 1586 void HAL_RCC_NMI_IRQHandler(void);
bogdanm 84:0b3ab51c8877 1587
bogdanm 84:0b3ab51c8877 1588 /* User Callbacks in non blocking mode (IT mode) */
Kojto 96:487b796308b0 1589 void HAL_RCC_CSSCallback(void);
Kojto 96:487b796308b0 1590 /**
Kojto 96:487b796308b0 1591 * @}
Kojto 96:487b796308b0 1592 */
Kojto 96:487b796308b0 1593
Kojto 96:487b796308b0 1594 /**
Kojto 96:487b796308b0 1595 * @}
Kojto 96:487b796308b0 1596 */
Kojto 119:aae6fcc7d9bb 1597
Kojto 119:aae6fcc7d9bb 1598
bogdanm 84:0b3ab51c8877 1599 /**
bogdanm 84:0b3ab51c8877 1600 * @}
bogdanm 84:0b3ab51c8877 1601 */
bogdanm 84:0b3ab51c8877 1602
bogdanm 84:0b3ab51c8877 1603 /**
bogdanm 84:0b3ab51c8877 1604 * @}
bogdanm 84:0b3ab51c8877 1605 */
bogdanm 84:0b3ab51c8877 1606
bogdanm 84:0b3ab51c8877 1607 #ifdef __cplusplus
bogdanm 84:0b3ab51c8877 1608 }
bogdanm 84:0b3ab51c8877 1609 #endif
bogdanm 84:0b3ab51c8877 1610
Kojto 96:487b796308b0 1611 #endif /* __STM32l0xx_HAL_RCC_H */
bogdanm 84:0b3ab51c8877 1612
bogdanm 84:0b3ab51c8877 1613 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Kojto 96:487b796308b0 1614