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TARGET_MAX32620FTHR/cmsis_armclang.h@167:84c0a372a020, 2018-05-11 (annotated)

Committer:
AnnaBridge
Date:
Fri May 11 16:51:14 2018 +0100
Revision:
167:84c0a372a020
Child:
169:a7c7b631e539
mbed library. Release version 162

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 167:84c0a372a020 1 /**************************************************************************//**
AnnaBridge 167:84c0a372a020 2 * @file cmsis_armclang.h
AnnaBridge 167:84c0a372a020 3 * @brief CMSIS compiler ARMCLANG (ARM compiler V6) header file
AnnaBridge 167:84c0a372a020 4 * @version V5.0.3
AnnaBridge 167:84c0a372a020 5 * @date 27. March 2017
AnnaBridge 167:84c0a372a020 6 ******************************************************************************/
AnnaBridge 167:84c0a372a020 7 /*
AnnaBridge 167:84c0a372a020 8 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
AnnaBridge 167:84c0a372a020 9 *
AnnaBridge 167:84c0a372a020 10 * SPDX-License-Identifier: Apache-2.0
AnnaBridge 167:84c0a372a020 11 *
AnnaBridge 167:84c0a372a020 12 * Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge 167:84c0a372a020 13 * not use this file except in compliance with the License.
AnnaBridge 167:84c0a372a020 14 * You may obtain a copy of the License at
AnnaBridge 167:84c0a372a020 15 *
AnnaBridge 167:84c0a372a020 16 * www.apache.org/licenses/LICENSE-2.0
AnnaBridge 167:84c0a372a020 17 *
AnnaBridge 167:84c0a372a020 18 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 167:84c0a372a020 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge 167:84c0a372a020 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 167:84c0a372a020 21 * See the License for the specific language governing permissions and
AnnaBridge 167:84c0a372a020 22 * limitations under the License.
AnnaBridge 167:84c0a372a020 23 */
AnnaBridge 167:84c0a372a020 24
AnnaBridge 167:84c0a372a020 25 /*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
AnnaBridge 167:84c0a372a020 26
AnnaBridge 167:84c0a372a020 27 #ifndef __CMSIS_ARMCLANG_H
AnnaBridge 167:84c0a372a020 28 #define __CMSIS_ARMCLANG_H
AnnaBridge 167:84c0a372a020 29
AnnaBridge 167:84c0a372a020 30 #ifndef __ARM_COMPAT_H
AnnaBridge 167:84c0a372a020 31 #include <arm_compat.h> /* Compatibility header for ARM Compiler 5 intrinsics */
AnnaBridge 167:84c0a372a020 32 #endif
AnnaBridge 167:84c0a372a020 33
AnnaBridge 167:84c0a372a020 34 /* CMSIS compiler specific defines */
AnnaBridge 167:84c0a372a020 35 #ifndef __ASM
AnnaBridge 167:84c0a372a020 36 #define __ASM __asm
AnnaBridge 167:84c0a372a020 37 #endif
AnnaBridge 167:84c0a372a020 38 #ifndef __INLINE
AnnaBridge 167:84c0a372a020 39 #define __INLINE __inline
AnnaBridge 167:84c0a372a020 40 #endif
AnnaBridge 167:84c0a372a020 41 #ifndef __STATIC_INLINE
AnnaBridge 167:84c0a372a020 42 #define __STATIC_INLINE static __inline
AnnaBridge 167:84c0a372a020 43 #endif
AnnaBridge 167:84c0a372a020 44 #ifndef __NO_RETURN
AnnaBridge 167:84c0a372a020 45 #define __NO_RETURN __attribute__((noreturn))
AnnaBridge 167:84c0a372a020 46 #endif
AnnaBridge 167:84c0a372a020 47 #ifndef __USED
AnnaBridge 167:84c0a372a020 48 #define __USED __attribute__((used))
AnnaBridge 167:84c0a372a020 49 #endif
AnnaBridge 167:84c0a372a020 50 #ifndef __WEAK
AnnaBridge 167:84c0a372a020 51 #define __WEAK __attribute__((weak))
AnnaBridge 167:84c0a372a020 52 #endif
AnnaBridge 167:84c0a372a020 53 #ifndef __PACKED
AnnaBridge 167:84c0a372a020 54 #define __PACKED __attribute__((packed, aligned(1)))
AnnaBridge 167:84c0a372a020 55 #endif
AnnaBridge 167:84c0a372a020 56 #ifndef __PACKED_STRUCT
AnnaBridge 167:84c0a372a020 57 #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
AnnaBridge 167:84c0a372a020 58 #endif
AnnaBridge 167:84c0a372a020 59 #ifndef __PACKED_UNION
AnnaBridge 167:84c0a372a020 60 #define __PACKED_UNION union __attribute__((packed, aligned(1)))
AnnaBridge 167:84c0a372a020 61 #endif
AnnaBridge 167:84c0a372a020 62 #ifndef __UNALIGNED_UINT32 /* deprecated */
AnnaBridge 167:84c0a372a020 63 #pragma clang diagnostic push
AnnaBridge 167:84c0a372a020 64 #pragma clang diagnostic ignored "-Wpacked"
AnnaBridge 167:84c0a372a020 65 /*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
AnnaBridge 167:84c0a372a020 66 struct __attribute__((packed)) T_UINT32 { uint32_t v; };
AnnaBridge 167:84c0a372a020 67 #pragma clang diagnostic pop
AnnaBridge 167:84c0a372a020 68 #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
AnnaBridge 167:84c0a372a020 69 #endif
AnnaBridge 167:84c0a372a020 70 #ifndef __UNALIGNED_UINT16_WRITE
AnnaBridge 167:84c0a372a020 71 #pragma clang diagnostic push
AnnaBridge 167:84c0a372a020 72 #pragma clang diagnostic ignored "-Wpacked"
AnnaBridge 167:84c0a372a020 73 /*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
AnnaBridge 167:84c0a372a020 74 __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
AnnaBridge 167:84c0a372a020 75 #pragma clang diagnostic pop
AnnaBridge 167:84c0a372a020 76 #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
AnnaBridge 167:84c0a372a020 77 #endif
AnnaBridge 167:84c0a372a020 78 #ifndef __UNALIGNED_UINT16_READ
AnnaBridge 167:84c0a372a020 79 #pragma clang diagnostic push
AnnaBridge 167:84c0a372a020 80 #pragma clang diagnostic ignored "-Wpacked"
AnnaBridge 167:84c0a372a020 81 /*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
AnnaBridge 167:84c0a372a020 82 __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
AnnaBridge 167:84c0a372a020 83 #pragma clang diagnostic pop
AnnaBridge 167:84c0a372a020 84 #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
AnnaBridge 167:84c0a372a020 85 #endif
AnnaBridge 167:84c0a372a020 86 #ifndef __UNALIGNED_UINT32_WRITE
AnnaBridge 167:84c0a372a020 87 #pragma clang diagnostic push
AnnaBridge 167:84c0a372a020 88 #pragma clang diagnostic ignored "-Wpacked"
AnnaBridge 167:84c0a372a020 89 /*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
AnnaBridge 167:84c0a372a020 90 __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
AnnaBridge 167:84c0a372a020 91 #pragma clang diagnostic pop
AnnaBridge 167:84c0a372a020 92 #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
AnnaBridge 167:84c0a372a020 93 #endif
AnnaBridge 167:84c0a372a020 94 #ifndef __UNALIGNED_UINT32_READ
AnnaBridge 167:84c0a372a020 95 #pragma clang diagnostic push
AnnaBridge 167:84c0a372a020 96 #pragma clang diagnostic ignored "-Wpacked"
AnnaBridge 167:84c0a372a020 97 /*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
AnnaBridge 167:84c0a372a020 98 __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
AnnaBridge 167:84c0a372a020 99 #pragma clang diagnostic pop
AnnaBridge 167:84c0a372a020 100 #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
AnnaBridge 167:84c0a372a020 101 #endif
AnnaBridge 167:84c0a372a020 102 #ifndef __ALIGNED
AnnaBridge 167:84c0a372a020 103 #define __ALIGNED(x) __attribute__((aligned(x)))
AnnaBridge 167:84c0a372a020 104 #endif
AnnaBridge 167:84c0a372a020 105 #ifndef __RESTRICT
AnnaBridge 167:84c0a372a020 106 #define __RESTRICT __restrict
AnnaBridge 167:84c0a372a020 107 #endif
AnnaBridge 167:84c0a372a020 108
AnnaBridge 167:84c0a372a020 109
AnnaBridge 167:84c0a372a020 110 /* ########################### Core Function Access ########################### */
AnnaBridge 167:84c0a372a020 111 /** \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 167:84c0a372a020 112 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
AnnaBridge 167:84c0a372a020 113 @{
AnnaBridge 167:84c0a372a020 114 */
AnnaBridge 167:84c0a372a020 115
AnnaBridge 167:84c0a372a020 116 /**
AnnaBridge 167:84c0a372a020 117 \brief Enable IRQ Interrupts
AnnaBridge 167:84c0a372a020 118 \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
AnnaBridge 167:84c0a372a020 119 Can only be executed in Privileged modes.
AnnaBridge 167:84c0a372a020 120 */
AnnaBridge 167:84c0a372a020 121 /* intrinsic void __enable_irq(); see arm_compat.h */
AnnaBridge 167:84c0a372a020 122
AnnaBridge 167:84c0a372a020 123
AnnaBridge 167:84c0a372a020 124 /**
AnnaBridge 167:84c0a372a020 125 \brief Disable IRQ Interrupts
AnnaBridge 167:84c0a372a020 126 \details Disables IRQ interrupts by setting the I-bit in the CPSR.
AnnaBridge 167:84c0a372a020 127 Can only be executed in Privileged modes.
AnnaBridge 167:84c0a372a020 128 */
AnnaBridge 167:84c0a372a020 129 /* intrinsic void __disable_irq(); see arm_compat.h */
AnnaBridge 167:84c0a372a020 130
AnnaBridge 167:84c0a372a020 131
AnnaBridge 167:84c0a372a020 132 /**
AnnaBridge 167:84c0a372a020 133 \brief Get Control Register
AnnaBridge 167:84c0a372a020 134 \details Returns the content of the Control Register.
AnnaBridge 167:84c0a372a020 135 \return Control Register value
AnnaBridge 167:84c0a372a020 136 */
AnnaBridge 167:84c0a372a020 137 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)
AnnaBridge 167:84c0a372a020 138 {
AnnaBridge 167:84c0a372a020 139 uint32_t result;
AnnaBridge 167:84c0a372a020 140
AnnaBridge 167:84c0a372a020 141 __ASM volatile ("MRS %0, control" : "=r" (result) );
AnnaBridge 167:84c0a372a020 142 return(result);
AnnaBridge 167:84c0a372a020 143 }
AnnaBridge 167:84c0a372a020 144
AnnaBridge 167:84c0a372a020 145
AnnaBridge 167:84c0a372a020 146 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge 167:84c0a372a020 147 /**
AnnaBridge 167:84c0a372a020 148 \brief Get Control Register (non-secure)
AnnaBridge 167:84c0a372a020 149 \details Returns the content of the non-secure Control Register when in secure mode.
AnnaBridge 167:84c0a372a020 150 \return non-secure Control Register value
AnnaBridge 167:84c0a372a020 151 */
AnnaBridge 167:84c0a372a020 152 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void)
AnnaBridge 167:84c0a372a020 153 {
AnnaBridge 167:84c0a372a020 154 uint32_t result;
AnnaBridge 167:84c0a372a020 155
AnnaBridge 167:84c0a372a020 156 __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
AnnaBridge 167:84c0a372a020 157 return(result);
AnnaBridge 167:84c0a372a020 158 }
AnnaBridge 167:84c0a372a020 159 #endif
AnnaBridge 167:84c0a372a020 160
AnnaBridge 167:84c0a372a020 161
AnnaBridge 167:84c0a372a020 162 /**
AnnaBridge 167:84c0a372a020 163 \brief Set Control Register
AnnaBridge 167:84c0a372a020 164 \details Writes the given value to the Control Register.
AnnaBridge 167:84c0a372a020 165 \param [in] control Control Register value to set
AnnaBridge 167:84c0a372a020 166 */
AnnaBridge 167:84c0a372a020 167 __attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)
AnnaBridge 167:84c0a372a020 168 {
AnnaBridge 167:84c0a372a020 169 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
AnnaBridge 167:84c0a372a020 170 }
AnnaBridge 167:84c0a372a020 171
AnnaBridge 167:84c0a372a020 172
AnnaBridge 167:84c0a372a020 173 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge 167:84c0a372a020 174 /**
AnnaBridge 167:84c0a372a020 175 \brief Set Control Register (non-secure)
AnnaBridge 167:84c0a372a020 176 \details Writes the given value to the non-secure Control Register when in secure state.
AnnaBridge 167:84c0a372a020 177 \param [in] control Control Register value to set
AnnaBridge 167:84c0a372a020 178 */
AnnaBridge 167:84c0a372a020 179 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control)
AnnaBridge 167:84c0a372a020 180 {
AnnaBridge 167:84c0a372a020 181 __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
AnnaBridge 167:84c0a372a020 182 }
AnnaBridge 167:84c0a372a020 183 #endif
AnnaBridge 167:84c0a372a020 184
AnnaBridge 167:84c0a372a020 185
AnnaBridge 167:84c0a372a020 186 /**
AnnaBridge 167:84c0a372a020 187 \brief Get IPSR Register
AnnaBridge 167:84c0a372a020 188 \details Returns the content of the IPSR Register.
AnnaBridge 167:84c0a372a020 189 \return IPSR Register value
AnnaBridge 167:84c0a372a020 190 */
AnnaBridge 167:84c0a372a020 191 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)
AnnaBridge 167:84c0a372a020 192 {
AnnaBridge 167:84c0a372a020 193 uint32_t result;
AnnaBridge 167:84c0a372a020 194
AnnaBridge 167:84c0a372a020 195 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
AnnaBridge 167:84c0a372a020 196 return(result);
AnnaBridge 167:84c0a372a020 197 }
AnnaBridge 167:84c0a372a020 198
AnnaBridge 167:84c0a372a020 199
AnnaBridge 167:84c0a372a020 200 /**
AnnaBridge 167:84c0a372a020 201 \brief Get APSR Register
AnnaBridge 167:84c0a372a020 202 \details Returns the content of the APSR Register.
AnnaBridge 167:84c0a372a020 203 \return APSR Register value
AnnaBridge 167:84c0a372a020 204 */
AnnaBridge 167:84c0a372a020 205 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)
AnnaBridge 167:84c0a372a020 206 {
AnnaBridge 167:84c0a372a020 207 uint32_t result;
AnnaBridge 167:84c0a372a020 208
AnnaBridge 167:84c0a372a020 209 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
AnnaBridge 167:84c0a372a020 210 return(result);
AnnaBridge 167:84c0a372a020 211 }
AnnaBridge 167:84c0a372a020 212
AnnaBridge 167:84c0a372a020 213
AnnaBridge 167:84c0a372a020 214 /**
AnnaBridge 167:84c0a372a020 215 \brief Get xPSR Register
AnnaBridge 167:84c0a372a020 216 \details Returns the content of the xPSR Register.
AnnaBridge 167:84c0a372a020 217 \return xPSR Register value
AnnaBridge 167:84c0a372a020 218 */
AnnaBridge 167:84c0a372a020 219 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)
AnnaBridge 167:84c0a372a020 220 {
AnnaBridge 167:84c0a372a020 221 uint32_t result;
AnnaBridge 167:84c0a372a020 222
AnnaBridge 167:84c0a372a020 223 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
AnnaBridge 167:84c0a372a020 224 return(result);
AnnaBridge 167:84c0a372a020 225 }
AnnaBridge 167:84c0a372a020 226
AnnaBridge 167:84c0a372a020 227
AnnaBridge 167:84c0a372a020 228 /**
AnnaBridge 167:84c0a372a020 229 \brief Get Process Stack Pointer
AnnaBridge 167:84c0a372a020 230 \details Returns the current value of the Process Stack Pointer (PSP).
AnnaBridge 167:84c0a372a020 231 \return PSP Register value
AnnaBridge 167:84c0a372a020 232 */
AnnaBridge 167:84c0a372a020 233 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)
AnnaBridge 167:84c0a372a020 234 {
AnnaBridge 167:84c0a372a020 235 register uint32_t result;
AnnaBridge 167:84c0a372a020 236
AnnaBridge 167:84c0a372a020 237 __ASM volatile ("MRS %0, psp" : "=r" (result) );
AnnaBridge 167:84c0a372a020 238 return(result);
AnnaBridge 167:84c0a372a020 239 }
AnnaBridge 167:84c0a372a020 240
AnnaBridge 167:84c0a372a020 241
AnnaBridge 167:84c0a372a020 242 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge 167:84c0a372a020 243 /**
AnnaBridge 167:84c0a372a020 244 \brief Get Process Stack Pointer (non-secure)
AnnaBridge 167:84c0a372a020 245 \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
AnnaBridge 167:84c0a372a020 246 \return PSP Register value
AnnaBridge 167:84c0a372a020 247 */
AnnaBridge 167:84c0a372a020 248 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void)
AnnaBridge 167:84c0a372a020 249 {
AnnaBridge 167:84c0a372a020 250 register uint32_t result;
AnnaBridge 167:84c0a372a020 251
AnnaBridge 167:84c0a372a020 252 __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
AnnaBridge 167:84c0a372a020 253 return(result);
AnnaBridge 167:84c0a372a020 254 }
AnnaBridge 167:84c0a372a020 255 #endif
AnnaBridge 167:84c0a372a020 256
AnnaBridge 167:84c0a372a020 257
AnnaBridge 167:84c0a372a020 258 /**
AnnaBridge 167:84c0a372a020 259 \brief Set Process Stack Pointer
AnnaBridge 167:84c0a372a020 260 \details Assigns the given value to the Process Stack Pointer (PSP).
AnnaBridge 167:84c0a372a020 261 \param [in] topOfProcStack Process Stack Pointer value to set
AnnaBridge 167:84c0a372a020 262 */
AnnaBridge 167:84c0a372a020 263 __attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
AnnaBridge 167:84c0a372a020 264 {
AnnaBridge 167:84c0a372a020 265 __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
AnnaBridge 167:84c0a372a020 266 }
AnnaBridge 167:84c0a372a020 267
AnnaBridge 167:84c0a372a020 268
AnnaBridge 167:84c0a372a020 269 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge 167:84c0a372a020 270 /**
AnnaBridge 167:84c0a372a020 271 \brief Set Process Stack Pointer (non-secure)
AnnaBridge 167:84c0a372a020 272 \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
AnnaBridge 167:84c0a372a020 273 \param [in] topOfProcStack Process Stack Pointer value to set
AnnaBridge 167:84c0a372a020 274 */
AnnaBridge 167:84c0a372a020 275 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
AnnaBridge 167:84c0a372a020 276 {
AnnaBridge 167:84c0a372a020 277 __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
AnnaBridge 167:84c0a372a020 278 }
AnnaBridge 167:84c0a372a020 279 #endif
AnnaBridge 167:84c0a372a020 280
AnnaBridge 167:84c0a372a020 281
AnnaBridge 167:84c0a372a020 282 /**
AnnaBridge 167:84c0a372a020 283 \brief Get Main Stack Pointer
AnnaBridge 167:84c0a372a020 284 \details Returns the current value of the Main Stack Pointer (MSP).
AnnaBridge 167:84c0a372a020 285 \return MSP Register value
AnnaBridge 167:84c0a372a020 286 */
AnnaBridge 167:84c0a372a020 287 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)
AnnaBridge 167:84c0a372a020 288 {
AnnaBridge 167:84c0a372a020 289 register uint32_t result;
AnnaBridge 167:84c0a372a020 290
AnnaBridge 167:84c0a372a020 291 __ASM volatile ("MRS %0, msp" : "=r" (result) );
AnnaBridge 167:84c0a372a020 292 return(result);
AnnaBridge 167:84c0a372a020 293 }
AnnaBridge 167:84c0a372a020 294
AnnaBridge 167:84c0a372a020 295
AnnaBridge 167:84c0a372a020 296 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge 167:84c0a372a020 297 /**
AnnaBridge 167:84c0a372a020 298 \brief Get Main Stack Pointer (non-secure)
AnnaBridge 167:84c0a372a020 299 \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
AnnaBridge 167:84c0a372a020 300 \return MSP Register value
AnnaBridge 167:84c0a372a020 301 */
AnnaBridge 167:84c0a372a020 302 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void)
AnnaBridge 167:84c0a372a020 303 {
AnnaBridge 167:84c0a372a020 304 register uint32_t result;
AnnaBridge 167:84c0a372a020 305
AnnaBridge 167:84c0a372a020 306 __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
AnnaBridge 167:84c0a372a020 307 return(result);
AnnaBridge 167:84c0a372a020 308 }
AnnaBridge 167:84c0a372a020 309 #endif
AnnaBridge 167:84c0a372a020 310
AnnaBridge 167:84c0a372a020 311
AnnaBridge 167:84c0a372a020 312 /**
AnnaBridge 167:84c0a372a020 313 \brief Set Main Stack Pointer
AnnaBridge 167:84c0a372a020 314 \details Assigns the given value to the Main Stack Pointer (MSP).
AnnaBridge 167:84c0a372a020 315 \param [in] topOfMainStack Main Stack Pointer value to set
AnnaBridge 167:84c0a372a020 316 */
AnnaBridge 167:84c0a372a020 317 __attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
AnnaBridge 167:84c0a372a020 318 {
AnnaBridge 167:84c0a372a020 319 __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
AnnaBridge 167:84c0a372a020 320 }
AnnaBridge 167:84c0a372a020 321
AnnaBridge 167:84c0a372a020 322
AnnaBridge 167:84c0a372a020 323 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge 167:84c0a372a020 324 /**
AnnaBridge 167:84c0a372a020 325 \brief Set Main Stack Pointer (non-secure)
AnnaBridge 167:84c0a372a020 326 \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
AnnaBridge 167:84c0a372a020 327 \param [in] topOfMainStack Main Stack Pointer value to set
AnnaBridge 167:84c0a372a020 328 */
AnnaBridge 167:84c0a372a020 329 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
AnnaBridge 167:84c0a372a020 330 {
AnnaBridge 167:84c0a372a020 331 __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
AnnaBridge 167:84c0a372a020 332 }
AnnaBridge 167:84c0a372a020 333 #endif
AnnaBridge 167:84c0a372a020 334
AnnaBridge 167:84c0a372a020 335
AnnaBridge 167:84c0a372a020 336 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge 167:84c0a372a020 337 /**
AnnaBridge 167:84c0a372a020 338 \brief Get Stack Pointer (non-secure)
AnnaBridge 167:84c0a372a020 339 \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
AnnaBridge 167:84c0a372a020 340 \return SP Register value
AnnaBridge 167:84c0a372a020 341 */
AnnaBridge 167:84c0a372a020 342 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_SP_NS(void)
AnnaBridge 167:84c0a372a020 343 {
AnnaBridge 167:84c0a372a020 344 register uint32_t result;
AnnaBridge 167:84c0a372a020 345
AnnaBridge 167:84c0a372a020 346 __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
AnnaBridge 167:84c0a372a020 347 return(result);
AnnaBridge 167:84c0a372a020 348 }
AnnaBridge 167:84c0a372a020 349
AnnaBridge 167:84c0a372a020 350
AnnaBridge 167:84c0a372a020 351 /**
AnnaBridge 167:84c0a372a020 352 \brief Set Stack Pointer (non-secure)
AnnaBridge 167:84c0a372a020 353 \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
AnnaBridge 167:84c0a372a020 354 \param [in] topOfStack Stack Pointer value to set
AnnaBridge 167:84c0a372a020 355 */
AnnaBridge 167:84c0a372a020 356 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_SP_NS(uint32_t topOfStack)
AnnaBridge 167:84c0a372a020 357 {
AnnaBridge 167:84c0a372a020 358 __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
AnnaBridge 167:84c0a372a020 359 }
AnnaBridge 167:84c0a372a020 360 #endif
AnnaBridge 167:84c0a372a020 361
AnnaBridge 167:84c0a372a020 362
AnnaBridge 167:84c0a372a020 363 /**
AnnaBridge 167:84c0a372a020 364 \brief Get Priority Mask
AnnaBridge 167:84c0a372a020 365 \details Returns the current state of the priority mask bit from the Priority Mask Register.
AnnaBridge 167:84c0a372a020 366 \return Priority Mask value
AnnaBridge 167:84c0a372a020 367 */
AnnaBridge 167:84c0a372a020 368 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)
AnnaBridge 167:84c0a372a020 369 {
AnnaBridge 167:84c0a372a020 370 uint32_t result;
AnnaBridge 167:84c0a372a020 371
AnnaBridge 167:84c0a372a020 372 __ASM volatile ("MRS %0, primask" : "=r" (result) );
AnnaBridge 167:84c0a372a020 373 return(result);
AnnaBridge 167:84c0a372a020 374 }
AnnaBridge 167:84c0a372a020 375
AnnaBridge 167:84c0a372a020 376
AnnaBridge 167:84c0a372a020 377 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge 167:84c0a372a020 378 /**
AnnaBridge 167:84c0a372a020 379 \brief Get Priority Mask (non-secure)
AnnaBridge 167:84c0a372a020 380 \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
AnnaBridge 167:84c0a372a020 381 \return Priority Mask value
AnnaBridge 167:84c0a372a020 382 */
AnnaBridge 167:84c0a372a020 383 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void)
AnnaBridge 167:84c0a372a020 384 {
AnnaBridge 167:84c0a372a020 385 uint32_t result;
AnnaBridge 167:84c0a372a020 386
AnnaBridge 167:84c0a372a020 387 __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
AnnaBridge 167:84c0a372a020 388 return(result);
AnnaBridge 167:84c0a372a020 389 }
AnnaBridge 167:84c0a372a020 390 #endif
AnnaBridge 167:84c0a372a020 391
AnnaBridge 167:84c0a372a020 392
AnnaBridge 167:84c0a372a020 393 /**
AnnaBridge 167:84c0a372a020 394 \brief Set Priority Mask
AnnaBridge 167:84c0a372a020 395 \details Assigns the given value to the Priority Mask Register.
AnnaBridge 167:84c0a372a020 396 \param [in] priMask Priority Mask
AnnaBridge 167:84c0a372a020 397 */
AnnaBridge 167:84c0a372a020 398 __attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
AnnaBridge 167:84c0a372a020 399 {
AnnaBridge 167:84c0a372a020 400 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
AnnaBridge 167:84c0a372a020 401 }
AnnaBridge 167:84c0a372a020 402
AnnaBridge 167:84c0a372a020 403
AnnaBridge 167:84c0a372a020 404 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge 167:84c0a372a020 405 /**
AnnaBridge 167:84c0a372a020 406 \brief Set Priority Mask (non-secure)
AnnaBridge 167:84c0a372a020 407 \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
AnnaBridge 167:84c0a372a020 408 \param [in] priMask Priority Mask
AnnaBridge 167:84c0a372a020 409 */
AnnaBridge 167:84c0a372a020 410 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
AnnaBridge 167:84c0a372a020 411 {
AnnaBridge 167:84c0a372a020 412 __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
AnnaBridge 167:84c0a372a020 413 }
AnnaBridge 167:84c0a372a020 414 #endif
AnnaBridge 167:84c0a372a020 415
AnnaBridge 167:84c0a372a020 416
AnnaBridge 167:84c0a372a020 417 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
AnnaBridge 167:84c0a372a020 418 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
AnnaBridge 167:84c0a372a020 419 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge 167:84c0a372a020 420 /**
AnnaBridge 167:84c0a372a020 421 \brief Enable FIQ
AnnaBridge 167:84c0a372a020 422 \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
AnnaBridge 167:84c0a372a020 423 Can only be executed in Privileged modes.
AnnaBridge 167:84c0a372a020 424 */
AnnaBridge 167:84c0a372a020 425 #define __enable_fault_irq __enable_fiq /* see arm_compat.h */
AnnaBridge 167:84c0a372a020 426
AnnaBridge 167:84c0a372a020 427
AnnaBridge 167:84c0a372a020 428 /**
AnnaBridge 167:84c0a372a020 429 \brief Disable FIQ
AnnaBridge 167:84c0a372a020 430 \details Disables FIQ interrupts by setting the F-bit in the CPSR.
AnnaBridge 167:84c0a372a020 431 Can only be executed in Privileged modes.
AnnaBridge 167:84c0a372a020 432 */
AnnaBridge 167:84c0a372a020 433 #define __disable_fault_irq __disable_fiq /* see arm_compat.h */
AnnaBridge 167:84c0a372a020 434
AnnaBridge 167:84c0a372a020 435
AnnaBridge 167:84c0a372a020 436 /**
AnnaBridge 167:84c0a372a020 437 \brief Get Base Priority
AnnaBridge 167:84c0a372a020 438 \details Returns the current value of the Base Priority register.
AnnaBridge 167:84c0a372a020 439 \return Base Priority register value
AnnaBridge 167:84c0a372a020 440 */
AnnaBridge 167:84c0a372a020 441 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)
AnnaBridge 167:84c0a372a020 442 {
AnnaBridge 167:84c0a372a020 443 uint32_t result;
AnnaBridge 167:84c0a372a020 444
AnnaBridge 167:84c0a372a020 445 __ASM volatile ("MRS %0, basepri" : "=r" (result) );
AnnaBridge 167:84c0a372a020 446 return(result);
AnnaBridge 167:84c0a372a020 447 }
AnnaBridge 167:84c0a372a020 448
AnnaBridge 167:84c0a372a020 449
AnnaBridge 167:84c0a372a020 450 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge 167:84c0a372a020 451 /**
AnnaBridge 167:84c0a372a020 452 \brief Get Base Priority (non-secure)
AnnaBridge 167:84c0a372a020 453 \details Returns the current value of the non-secure Base Priority register when in secure state.
AnnaBridge 167:84c0a372a020 454 \return Base Priority register value
AnnaBridge 167:84c0a372a020 455 */
AnnaBridge 167:84c0a372a020 456 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void)
AnnaBridge 167:84c0a372a020 457 {
AnnaBridge 167:84c0a372a020 458 uint32_t result;
AnnaBridge 167:84c0a372a020 459
AnnaBridge 167:84c0a372a020 460 __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
AnnaBridge 167:84c0a372a020 461 return(result);
AnnaBridge 167:84c0a372a020 462 }
AnnaBridge 167:84c0a372a020 463 #endif
AnnaBridge 167:84c0a372a020 464
AnnaBridge 167:84c0a372a020 465
AnnaBridge 167:84c0a372a020 466 /**
AnnaBridge 167:84c0a372a020 467 \brief Set Base Priority
AnnaBridge 167:84c0a372a020 468 \details Assigns the given value to the Base Priority register.
AnnaBridge 167:84c0a372a020 469 \param [in] basePri Base Priority value to set
AnnaBridge 167:84c0a372a020 470 */
AnnaBridge 167:84c0a372a020 471 __attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
AnnaBridge 167:84c0a372a020 472 {
AnnaBridge 167:84c0a372a020 473 __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
AnnaBridge 167:84c0a372a020 474 }
AnnaBridge 167:84c0a372a020 475
AnnaBridge 167:84c0a372a020 476
AnnaBridge 167:84c0a372a020 477 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge 167:84c0a372a020 478 /**
AnnaBridge 167:84c0a372a020 479 \brief Set Base Priority (non-secure)
AnnaBridge 167:84c0a372a020 480 \details Assigns the given value to the non-secure Base Priority register when in secure state.
AnnaBridge 167:84c0a372a020 481 \param [in] basePri Base Priority value to set
AnnaBridge 167:84c0a372a020 482 */
AnnaBridge 167:84c0a372a020 483 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
AnnaBridge 167:84c0a372a020 484 {
AnnaBridge 167:84c0a372a020 485 __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
AnnaBridge 167:84c0a372a020 486 }
AnnaBridge 167:84c0a372a020 487 #endif
AnnaBridge 167:84c0a372a020 488
AnnaBridge 167:84c0a372a020 489
AnnaBridge 167:84c0a372a020 490 /**
AnnaBridge 167:84c0a372a020 491 \brief Set Base Priority with condition
AnnaBridge 167:84c0a372a020 492 \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
AnnaBridge 167:84c0a372a020 493 or the new value increases the BASEPRI priority level.
AnnaBridge 167:84c0a372a020 494 \param [in] basePri Base Priority value to set
AnnaBridge 167:84c0a372a020 495 */
AnnaBridge 167:84c0a372a020 496 __attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
AnnaBridge 167:84c0a372a020 497 {
AnnaBridge 167:84c0a372a020 498 __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
AnnaBridge 167:84c0a372a020 499 }
AnnaBridge 167:84c0a372a020 500
AnnaBridge 167:84c0a372a020 501
AnnaBridge 167:84c0a372a020 502 /**
AnnaBridge 167:84c0a372a020 503 \brief Get Fault Mask
AnnaBridge 167:84c0a372a020 504 \details Returns the current value of the Fault Mask register.
AnnaBridge 167:84c0a372a020 505 \return Fault Mask register value
AnnaBridge 167:84c0a372a020 506 */
AnnaBridge 167:84c0a372a020 507 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
AnnaBridge 167:84c0a372a020 508 {
AnnaBridge 167:84c0a372a020 509 uint32_t result;
AnnaBridge 167:84c0a372a020 510
AnnaBridge 167:84c0a372a020 511 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
AnnaBridge 167:84c0a372a020 512 return(result);
AnnaBridge 167:84c0a372a020 513 }
AnnaBridge 167:84c0a372a020 514
AnnaBridge 167:84c0a372a020 515
AnnaBridge 167:84c0a372a020 516 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge 167:84c0a372a020 517 /**
AnnaBridge 167:84c0a372a020 518 \brief Get Fault Mask (non-secure)
AnnaBridge 167:84c0a372a020 519 \details Returns the current value of the non-secure Fault Mask register when in secure state.
AnnaBridge 167:84c0a372a020 520 \return Fault Mask register value
AnnaBridge 167:84c0a372a020 521 */
AnnaBridge 167:84c0a372a020 522 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void)
AnnaBridge 167:84c0a372a020 523 {
AnnaBridge 167:84c0a372a020 524 uint32_t result;
AnnaBridge 167:84c0a372a020 525
AnnaBridge 167:84c0a372a020 526 __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
AnnaBridge 167:84c0a372a020 527 return(result);
AnnaBridge 167:84c0a372a020 528 }
AnnaBridge 167:84c0a372a020 529 #endif
AnnaBridge 167:84c0a372a020 530
AnnaBridge 167:84c0a372a020 531
AnnaBridge 167:84c0a372a020 532 /**
AnnaBridge 167:84c0a372a020 533 \brief Set Fault Mask
AnnaBridge 167:84c0a372a020 534 \details Assigns the given value to the Fault Mask register.
AnnaBridge 167:84c0a372a020 535 \param [in] faultMask Fault Mask value to set
AnnaBridge 167:84c0a372a020 536 */
AnnaBridge 167:84c0a372a020 537 __attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
AnnaBridge 167:84c0a372a020 538 {
AnnaBridge 167:84c0a372a020 539 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
AnnaBridge 167:84c0a372a020 540 }
AnnaBridge 167:84c0a372a020 541
AnnaBridge 167:84c0a372a020 542
AnnaBridge 167:84c0a372a020 543 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge 167:84c0a372a020 544 /**
AnnaBridge 167:84c0a372a020 545 \brief Set Fault Mask (non-secure)
AnnaBridge 167:84c0a372a020 546 \details Assigns the given value to the non-secure Fault Mask register when in secure state.
AnnaBridge 167:84c0a372a020 547 \param [in] faultMask Fault Mask value to set
AnnaBridge 167:84c0a372a020 548 */
AnnaBridge 167:84c0a372a020 549 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
AnnaBridge 167:84c0a372a020 550 {
AnnaBridge 167:84c0a372a020 551 __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
AnnaBridge 167:84c0a372a020 552 }
AnnaBridge 167:84c0a372a020 553 #endif
AnnaBridge 167:84c0a372a020 554
AnnaBridge 167:84c0a372a020 555 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
AnnaBridge 167:84c0a372a020 556 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
AnnaBridge 167:84c0a372a020 557 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
AnnaBridge 167:84c0a372a020 558
AnnaBridge 167:84c0a372a020 559
AnnaBridge 167:84c0a372a020 560 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
AnnaBridge 167:84c0a372a020 561 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
AnnaBridge 167:84c0a372a020 562
AnnaBridge 167:84c0a372a020 563 /**
AnnaBridge 167:84c0a372a020 564 \brief Get Process Stack Pointer Limit
AnnaBridge 167:84c0a372a020 565 \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
AnnaBridge 167:84c0a372a020 566 \return PSPLIM Register value
AnnaBridge 167:84c0a372a020 567 */
AnnaBridge 167:84c0a372a020 568 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void)
AnnaBridge 167:84c0a372a020 569 {
AnnaBridge 167:84c0a372a020 570 register uint32_t result;
AnnaBridge 167:84c0a372a020 571
AnnaBridge 167:84c0a372a020 572 __ASM volatile ("MRS %0, psplim" : "=r" (result) );
AnnaBridge 167:84c0a372a020 573 return(result);
AnnaBridge 167:84c0a372a020 574 }
AnnaBridge 167:84c0a372a020 575
AnnaBridge 167:84c0a372a020 576
AnnaBridge 167:84c0a372a020 577 #if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
AnnaBridge 167:84c0a372a020 578 (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge 167:84c0a372a020 579 /**
AnnaBridge 167:84c0a372a020 580 \brief Get Process Stack Pointer Limit (non-secure)
AnnaBridge 167:84c0a372a020 581 \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
AnnaBridge 167:84c0a372a020 582 \return PSPLIM Register value
AnnaBridge 167:84c0a372a020 583 */
AnnaBridge 167:84c0a372a020 584 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void)
AnnaBridge 167:84c0a372a020 585 {
AnnaBridge 167:84c0a372a020 586 register uint32_t result;
AnnaBridge 167:84c0a372a020 587
AnnaBridge 167:84c0a372a020 588 __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
AnnaBridge 167:84c0a372a020 589 return(result);
AnnaBridge 167:84c0a372a020 590 }
AnnaBridge 167:84c0a372a020 591 #endif
AnnaBridge 167:84c0a372a020 592
AnnaBridge 167:84c0a372a020 593
AnnaBridge 167:84c0a372a020 594 /**
AnnaBridge 167:84c0a372a020 595 \brief Set Process Stack Pointer Limit
AnnaBridge 167:84c0a372a020 596 \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
AnnaBridge 167:84c0a372a020 597 \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
AnnaBridge 167:84c0a372a020 598 */
AnnaBridge 167:84c0a372a020 599 __attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
AnnaBridge 167:84c0a372a020 600 {
AnnaBridge 167:84c0a372a020 601 __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
AnnaBridge 167:84c0a372a020 602 }
AnnaBridge 167:84c0a372a020 603
AnnaBridge 167:84c0a372a020 604
AnnaBridge 167:84c0a372a020 605 #if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
AnnaBridge 167:84c0a372a020 606 (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge 167:84c0a372a020 607 /**
AnnaBridge 167:84c0a372a020 608 \brief Set Process Stack Pointer (non-secure)
AnnaBridge 167:84c0a372a020 609 \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
AnnaBridge 167:84c0a372a020 610 \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
AnnaBridge 167:84c0a372a020 611 */
AnnaBridge 167:84c0a372a020 612 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
AnnaBridge 167:84c0a372a020 613 {
AnnaBridge 167:84c0a372a020 614 __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
AnnaBridge 167:84c0a372a020 615 }
AnnaBridge 167:84c0a372a020 616 #endif
AnnaBridge 167:84c0a372a020 617
AnnaBridge 167:84c0a372a020 618
AnnaBridge 167:84c0a372a020 619 /**
AnnaBridge 167:84c0a372a020 620 \brief Get Main Stack Pointer Limit
AnnaBridge 167:84c0a372a020 621 \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
AnnaBridge 167:84c0a372a020 622 \return MSPLIM Register value
AnnaBridge 167:84c0a372a020 623 */
AnnaBridge 167:84c0a372a020 624 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void)
AnnaBridge 167:84c0a372a020 625 {
AnnaBridge 167:84c0a372a020 626 register uint32_t result;
AnnaBridge 167:84c0a372a020 627
AnnaBridge 167:84c0a372a020 628 __ASM volatile ("MRS %0, msplim" : "=r" (result) );
AnnaBridge 167:84c0a372a020 629
AnnaBridge 167:84c0a372a020 630 return(result);
AnnaBridge 167:84c0a372a020 631 }
AnnaBridge 167:84c0a372a020 632
AnnaBridge 167:84c0a372a020 633
AnnaBridge 167:84c0a372a020 634 #if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
AnnaBridge 167:84c0a372a020 635 (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge 167:84c0a372a020 636 /**
AnnaBridge 167:84c0a372a020 637 \brief Get Main Stack Pointer Limit (non-secure)
AnnaBridge 167:84c0a372a020 638 \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
AnnaBridge 167:84c0a372a020 639 \return MSPLIM Register value
AnnaBridge 167:84c0a372a020 640 */
AnnaBridge 167:84c0a372a020 641 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void)
AnnaBridge 167:84c0a372a020 642 {
AnnaBridge 167:84c0a372a020 643 register uint32_t result;
AnnaBridge 167:84c0a372a020 644
AnnaBridge 167:84c0a372a020 645 __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
AnnaBridge 167:84c0a372a020 646 return(result);
AnnaBridge 167:84c0a372a020 647 }
AnnaBridge 167:84c0a372a020 648 #endif
AnnaBridge 167:84c0a372a020 649
AnnaBridge 167:84c0a372a020 650
AnnaBridge 167:84c0a372a020 651 /**
AnnaBridge 167:84c0a372a020 652 \brief Set Main Stack Pointer Limit
AnnaBridge 167:84c0a372a020 653 \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
AnnaBridge 167:84c0a372a020 654 \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
AnnaBridge 167:84c0a372a020 655 */
AnnaBridge 167:84c0a372a020 656 __attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
AnnaBridge 167:84c0a372a020 657 {
AnnaBridge 167:84c0a372a020 658 __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
AnnaBridge 167:84c0a372a020 659 }
AnnaBridge 167:84c0a372a020 660
AnnaBridge 167:84c0a372a020 661
AnnaBridge 167:84c0a372a020 662 #if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
AnnaBridge 167:84c0a372a020 663 (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge 167:84c0a372a020 664 /**
AnnaBridge 167:84c0a372a020 665 \brief Set Main Stack Pointer Limit (non-secure)
AnnaBridge 167:84c0a372a020 666 \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
AnnaBridge 167:84c0a372a020 667 \param [in] MainStackPtrLimit Main Stack Pointer value to set
AnnaBridge 167:84c0a372a020 668 */
AnnaBridge 167:84c0a372a020 669 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
AnnaBridge 167:84c0a372a020 670 {
AnnaBridge 167:84c0a372a020 671 __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
AnnaBridge 167:84c0a372a020 672 }
AnnaBridge 167:84c0a372a020 673 #endif
AnnaBridge 167:84c0a372a020 674
AnnaBridge 167:84c0a372a020 675 #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
AnnaBridge 167:84c0a372a020 676 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
AnnaBridge 167:84c0a372a020 677
AnnaBridge 167:84c0a372a020 678
AnnaBridge 167:84c0a372a020 679 #if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
AnnaBridge 167:84c0a372a020 680 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge 167:84c0a372a020 681
AnnaBridge 167:84c0a372a020 682 /**
AnnaBridge 167:84c0a372a020 683 \brief Get FPSCR
AnnaBridge 167:84c0a372a020 684 \details Returns the current value of the Floating Point Status/Control register.
AnnaBridge 167:84c0a372a020 685 \return Floating Point Status/Control register value
AnnaBridge 167:84c0a372a020 686 */
AnnaBridge 167:84c0a372a020 687 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
AnnaBridge 167:84c0a372a020 688 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
AnnaBridge 167:84c0a372a020 689 #define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr
AnnaBridge 167:84c0a372a020 690 #else
AnnaBridge 167:84c0a372a020 691 #define __get_FPSCR() ((uint32_t)0U)
AnnaBridge 167:84c0a372a020 692 #endif
AnnaBridge 167:84c0a372a020 693
AnnaBridge 167:84c0a372a020 694 /**
AnnaBridge 167:84c0a372a020 695 \brief Set FPSCR
AnnaBridge 167:84c0a372a020 696 \details Assigns the given value to the Floating Point Status/Control register.
AnnaBridge 167:84c0a372a020 697 \param [in] fpscr Floating Point Status/Control value to set
AnnaBridge 167:84c0a372a020 698 */
AnnaBridge 167:84c0a372a020 699 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
AnnaBridge 167:84c0a372a020 700 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
AnnaBridge 167:84c0a372a020 701 #define __set_FPSCR __builtin_arm_set_fpscr
AnnaBridge 167:84c0a372a020 702 #else
AnnaBridge 167:84c0a372a020 703 #define __set_FPSCR(x) ((void)(x))
AnnaBridge 167:84c0a372a020 704 #endif
AnnaBridge 167:84c0a372a020 705
AnnaBridge 167:84c0a372a020 706 #endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
AnnaBridge 167:84c0a372a020 707 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
AnnaBridge 167:84c0a372a020 708
AnnaBridge 167:84c0a372a020 709
AnnaBridge 167:84c0a372a020 710
AnnaBridge 167:84c0a372a020 711 /*@} end of CMSIS_Core_RegAccFunctions */
AnnaBridge 167:84c0a372a020 712
AnnaBridge 167:84c0a372a020 713
AnnaBridge 167:84c0a372a020 714 /* ########################## Core Instruction Access ######################### */
AnnaBridge 167:84c0a372a020 715 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
AnnaBridge 167:84c0a372a020 716 Access to dedicated instructions
AnnaBridge 167:84c0a372a020 717 @{
AnnaBridge 167:84c0a372a020 718 */
AnnaBridge 167:84c0a372a020 719
AnnaBridge 167:84c0a372a020 720 /* Define macros for porting to both thumb1 and thumb2.
AnnaBridge 167:84c0a372a020 721 * For thumb1, use low register (r0-r7), specified by constraint "l"
AnnaBridge 167:84c0a372a020 722 * Otherwise, use general registers, specified by constraint "r" */
AnnaBridge 167:84c0a372a020 723 #if defined (__thumb__) && !defined (__thumb2__)
AnnaBridge 167:84c0a372a020 724 #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
AnnaBridge 167:84c0a372a020 725 #define __CMSIS_GCC_USE_REG(r) "l" (r)
AnnaBridge 167:84c0a372a020 726 #else
AnnaBridge 167:84c0a372a020 727 #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
AnnaBridge 167:84c0a372a020 728 #define __CMSIS_GCC_USE_REG(r) "r" (r)
AnnaBridge 167:84c0a372a020 729 #endif
AnnaBridge 167:84c0a372a020 730
AnnaBridge 167:84c0a372a020 731 /**
AnnaBridge 167:84c0a372a020 732 \brief No Operation
AnnaBridge 167:84c0a372a020 733 \details No Operation does nothing. This instruction can be used for code alignment purposes.
AnnaBridge 167:84c0a372a020 734 */
AnnaBridge 167:84c0a372a020 735 #define __NOP __builtin_arm_nop
AnnaBridge 167:84c0a372a020 736
AnnaBridge 167:84c0a372a020 737 /**
AnnaBridge 167:84c0a372a020 738 \brief Wait For Interrupt
AnnaBridge 167:84c0a372a020 739 \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
AnnaBridge 167:84c0a372a020 740 */
AnnaBridge 167:84c0a372a020 741 #define __WFI __builtin_arm_wfi
AnnaBridge 167:84c0a372a020 742
AnnaBridge 167:84c0a372a020 743
AnnaBridge 167:84c0a372a020 744 /**
AnnaBridge 167:84c0a372a020 745 \brief Wait For Event
AnnaBridge 167:84c0a372a020 746 \details Wait For Event is a hint instruction that permits the processor to enter
AnnaBridge 167:84c0a372a020 747 a low-power state until one of a number of events occurs.
AnnaBridge 167:84c0a372a020 748 */
AnnaBridge 167:84c0a372a020 749 #define __WFE __builtin_arm_wfe
AnnaBridge 167:84c0a372a020 750
AnnaBridge 167:84c0a372a020 751
AnnaBridge 167:84c0a372a020 752 /**
AnnaBridge 167:84c0a372a020 753 \brief Send Event
AnnaBridge 167:84c0a372a020 754 \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
AnnaBridge 167:84c0a372a020 755 */
AnnaBridge 167:84c0a372a020 756 #define __SEV __builtin_arm_sev
AnnaBridge 167:84c0a372a020 757
AnnaBridge 167:84c0a372a020 758
AnnaBridge 167:84c0a372a020 759 /**
AnnaBridge 167:84c0a372a020 760 \brief Instruction Synchronization Barrier
AnnaBridge 167:84c0a372a020 761 \details Instruction Synchronization Barrier flushes the pipeline in the processor,
AnnaBridge 167:84c0a372a020 762 so that all instructions following the ISB are fetched from cache or memory,
AnnaBridge 167:84c0a372a020 763 after the instruction has been completed.
AnnaBridge 167:84c0a372a020 764 */
AnnaBridge 167:84c0a372a020 765 #define __ISB() __builtin_arm_isb(0xF);
AnnaBridge 167:84c0a372a020 766
AnnaBridge 167:84c0a372a020 767 /**
AnnaBridge 167:84c0a372a020 768 \brief Data Synchronization Barrier
AnnaBridge 167:84c0a372a020 769 \details Acts as a special kind of Data Memory Barrier.
AnnaBridge 167:84c0a372a020 770 It completes when all explicit memory accesses before this instruction complete.
AnnaBridge 167:84c0a372a020 771 */
AnnaBridge 167:84c0a372a020 772 #define __DSB() __builtin_arm_dsb(0xF);
AnnaBridge 167:84c0a372a020 773
AnnaBridge 167:84c0a372a020 774
AnnaBridge 167:84c0a372a020 775 /**
AnnaBridge 167:84c0a372a020 776 \brief Data Memory Barrier
AnnaBridge 167:84c0a372a020 777 \details Ensures the apparent order of the explicit memory operations before
AnnaBridge 167:84c0a372a020 778 and after the instruction, without ensuring their completion.
AnnaBridge 167:84c0a372a020 779 */
AnnaBridge 167:84c0a372a020 780 #define __DMB() __builtin_arm_dmb(0xF);
AnnaBridge 167:84c0a372a020 781
AnnaBridge 167:84c0a372a020 782
AnnaBridge 167:84c0a372a020 783 /**
AnnaBridge 167:84c0a372a020 784 \brief Reverse byte order (32 bit)
AnnaBridge 167:84c0a372a020 785 \details Reverses the byte order in integer value.
AnnaBridge 167:84c0a372a020 786 \param [in] value Value to reverse
AnnaBridge 167:84c0a372a020 787 \return Reversed value
AnnaBridge 167:84c0a372a020 788 */
AnnaBridge 167:84c0a372a020 789 #define __REV (uint32_t)__builtin_bswap32
AnnaBridge 167:84c0a372a020 790
AnnaBridge 167:84c0a372a020 791
AnnaBridge 167:84c0a372a020 792 /**
AnnaBridge 167:84c0a372a020 793 \brief Reverse byte order (16 bit)
AnnaBridge 167:84c0a372a020 794 \details Reverses the byte order in two unsigned short values.
AnnaBridge 167:84c0a372a020 795 \param [in] value Value to reverse
AnnaBridge 167:84c0a372a020 796 \return Reversed value
AnnaBridge 167:84c0a372a020 797 */
AnnaBridge 167:84c0a372a020 798 #define __REV16 (uint16_t)__builtin_bswap16
AnnaBridge 167:84c0a372a020 799
AnnaBridge 167:84c0a372a020 800
AnnaBridge 167:84c0a372a020 801 /**
AnnaBridge 167:84c0a372a020 802 \brief Reverse byte order in signed short value
AnnaBridge 167:84c0a372a020 803 \details Reverses the byte order in a signed short value with sign extension to integer.
AnnaBridge 167:84c0a372a020 804 \param [in] value Value to reverse
AnnaBridge 167:84c0a372a020 805 \return Reversed value
AnnaBridge 167:84c0a372a020 806 */
AnnaBridge 167:84c0a372a020 807 __attribute__((always_inline)) __STATIC_INLINE int16_t __REVSH(int16_t value)
AnnaBridge 167:84c0a372a020 808 {
AnnaBridge 167:84c0a372a020 809 int16_t result;
AnnaBridge 167:84c0a372a020 810
AnnaBridge 167:84c0a372a020 811 __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
AnnaBridge 167:84c0a372a020 812
AnnaBridge 167:84c0a372a020 813 return result;
AnnaBridge 167:84c0a372a020 814 }
AnnaBridge 167:84c0a372a020 815
AnnaBridge 167:84c0a372a020 816
AnnaBridge 167:84c0a372a020 817 /**
AnnaBridge 167:84c0a372a020 818 \brief Rotate Right in unsigned value (32 bit)
AnnaBridge 167:84c0a372a020 819 \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
AnnaBridge 167:84c0a372a020 820 \param [in] op1 Value to rotate
AnnaBridge 167:84c0a372a020 821 \param [in] op2 Number of Bits to rotate
AnnaBridge 167:84c0a372a020 822 \return Rotated value
AnnaBridge 167:84c0a372a020 823 */
AnnaBridge 167:84c0a372a020 824 __attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
AnnaBridge 167:84c0a372a020 825 {
AnnaBridge 167:84c0a372a020 826 return (op1 >> op2) | (op1 << (32U - op2));
AnnaBridge 167:84c0a372a020 827 }
AnnaBridge 167:84c0a372a020 828
AnnaBridge 167:84c0a372a020 829
AnnaBridge 167:84c0a372a020 830 /**
AnnaBridge 167:84c0a372a020 831 \brief Breakpoint
AnnaBridge 167:84c0a372a020 832 \details Causes the processor to enter Debug state.
AnnaBridge 167:84c0a372a020 833 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
AnnaBridge 167:84c0a372a020 834 \param [in] value is ignored by the processor.
AnnaBridge 167:84c0a372a020 835 If required, a debugger can use it to store additional information about the breakpoint.
AnnaBridge 167:84c0a372a020 836 */
AnnaBridge 167:84c0a372a020 837 #define __BKPT(value) __ASM volatile ("bkpt "#value)
AnnaBridge 167:84c0a372a020 838
AnnaBridge 167:84c0a372a020 839
AnnaBridge 167:84c0a372a020 840 /**
AnnaBridge 167:84c0a372a020 841 \brief Reverse bit order of value
AnnaBridge 167:84c0a372a020 842 \details Reverses the bit order of the given value.
AnnaBridge 167:84c0a372a020 843 \param [in] value Value to reverse
AnnaBridge 167:84c0a372a020 844 \return Reversed value
AnnaBridge 167:84c0a372a020 845 */
AnnaBridge 167:84c0a372a020 846 #define __RBIT (uint32_t)__builtin_arm_rbit
AnnaBridge 167:84c0a372a020 847
AnnaBridge 167:84c0a372a020 848 /**
AnnaBridge 167:84c0a372a020 849 \brief Count leading zeros
AnnaBridge 167:84c0a372a020 850 \details Counts the number of leading zeros of a data value.
AnnaBridge 167:84c0a372a020 851 \param [in] value Value to count the leading zeros
AnnaBridge 167:84c0a372a020 852 \return number of leading zeros in value
AnnaBridge 167:84c0a372a020 853 */
AnnaBridge 167:84c0a372a020 854 #define __CLZ __builtin_clz
AnnaBridge 167:84c0a372a020 855
AnnaBridge 167:84c0a372a020 856
AnnaBridge 167:84c0a372a020 857 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
AnnaBridge 167:84c0a372a020 858 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
AnnaBridge 167:84c0a372a020 859 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
AnnaBridge 167:84c0a372a020 860 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
AnnaBridge 167:84c0a372a020 861 /**
AnnaBridge 167:84c0a372a020 862 \brief LDR Exclusive (8 bit)
AnnaBridge 167:84c0a372a020 863 \details Executes a exclusive LDR instruction for 8 bit value.
AnnaBridge 167:84c0a372a020 864 \param [in] ptr Pointer to data
AnnaBridge 167:84c0a372a020 865 \return value of type uint8_t at (*ptr)
AnnaBridge 167:84c0a372a020 866 */
AnnaBridge 167:84c0a372a020 867 #define __LDREXB (uint8_t)__builtin_arm_ldrex
AnnaBridge 167:84c0a372a020 868
AnnaBridge 167:84c0a372a020 869
AnnaBridge 167:84c0a372a020 870 /**
AnnaBridge 167:84c0a372a020 871 \brief LDR Exclusive (16 bit)
AnnaBridge 167:84c0a372a020 872 \details Executes a exclusive LDR instruction for 16 bit values.
AnnaBridge 167:84c0a372a020 873 \param [in] ptr Pointer to data
AnnaBridge 167:84c0a372a020 874 \return value of type uint16_t at (*ptr)
AnnaBridge 167:84c0a372a020 875 */
AnnaBridge 167:84c0a372a020 876 #define __LDREXH (uint16_t)__builtin_arm_ldrex
AnnaBridge 167:84c0a372a020 877
AnnaBridge 167:84c0a372a020 878
AnnaBridge 167:84c0a372a020 879 /**
AnnaBridge 167:84c0a372a020 880 \brief LDR Exclusive (32 bit)
AnnaBridge 167:84c0a372a020 881 \details Executes a exclusive LDR instruction for 32 bit values.
AnnaBridge 167:84c0a372a020 882 \param [in] ptr Pointer to data
AnnaBridge 167:84c0a372a020 883 \return value of type uint32_t at (*ptr)
AnnaBridge 167:84c0a372a020 884 */
AnnaBridge 167:84c0a372a020 885 #define __LDREXW (uint32_t)__builtin_arm_ldrex
AnnaBridge 167:84c0a372a020 886
AnnaBridge 167:84c0a372a020 887
AnnaBridge 167:84c0a372a020 888 /**
AnnaBridge 167:84c0a372a020 889 \brief STR Exclusive (8 bit)
AnnaBridge 167:84c0a372a020 890 \details Executes a exclusive STR instruction for 8 bit values.
AnnaBridge 167:84c0a372a020 891 \param [in] value Value to store
AnnaBridge 167:84c0a372a020 892 \param [in] ptr Pointer to location
AnnaBridge 167:84c0a372a020 893 \return 0 Function succeeded
AnnaBridge 167:84c0a372a020 894 \return 1 Function failed
AnnaBridge 167:84c0a372a020 895 */
AnnaBridge 167:84c0a372a020 896 #define __STREXB (uint32_t)__builtin_arm_strex
AnnaBridge 167:84c0a372a020 897
AnnaBridge 167:84c0a372a020 898
AnnaBridge 167:84c0a372a020 899 /**
AnnaBridge 167:84c0a372a020 900 \brief STR Exclusive (16 bit)
AnnaBridge 167:84c0a372a020 901 \details Executes a exclusive STR instruction for 16 bit values.
AnnaBridge 167:84c0a372a020 902 \param [in] value Value to store
AnnaBridge 167:84c0a372a020 903 \param [in] ptr Pointer to location
AnnaBridge 167:84c0a372a020 904 \return 0 Function succeeded
AnnaBridge 167:84c0a372a020 905 \return 1 Function failed
AnnaBridge 167:84c0a372a020 906 */
AnnaBridge 167:84c0a372a020 907 #define __STREXH (uint32_t)__builtin_arm_strex
AnnaBridge 167:84c0a372a020 908
AnnaBridge 167:84c0a372a020 909
AnnaBridge 167:84c0a372a020 910 /**
AnnaBridge 167:84c0a372a020 911 \brief STR Exclusive (32 bit)
AnnaBridge 167:84c0a372a020 912 \details Executes a exclusive STR instruction for 32 bit values.
AnnaBridge 167:84c0a372a020 913 \param [in] value Value to store
AnnaBridge 167:84c0a372a020 914 \param [in] ptr Pointer to location
AnnaBridge 167:84c0a372a020 915 \return 0 Function succeeded
AnnaBridge 167:84c0a372a020 916 \return 1 Function failed
AnnaBridge 167:84c0a372a020 917 */
AnnaBridge 167:84c0a372a020 918 #define __STREXW (uint32_t)__builtin_arm_strex
AnnaBridge 167:84c0a372a020 919
AnnaBridge 167:84c0a372a020 920
AnnaBridge 167:84c0a372a020 921 /**
AnnaBridge 167:84c0a372a020 922 \brief Remove the exclusive lock
AnnaBridge 167:84c0a372a020 923 \details Removes the exclusive lock which is created by LDREX.
AnnaBridge 167:84c0a372a020 924 */
AnnaBridge 167:84c0a372a020 925 #define __CLREX __builtin_arm_clrex
AnnaBridge 167:84c0a372a020 926
AnnaBridge 167:84c0a372a020 927 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
AnnaBridge 167:84c0a372a020 928 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
AnnaBridge 167:84c0a372a020 929 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
AnnaBridge 167:84c0a372a020 930 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
AnnaBridge 167:84c0a372a020 931
AnnaBridge 167:84c0a372a020 932
AnnaBridge 167:84c0a372a020 933 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
AnnaBridge 167:84c0a372a020 934 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
AnnaBridge 167:84c0a372a020 935 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge 167:84c0a372a020 936
AnnaBridge 167:84c0a372a020 937 /**
AnnaBridge 167:84c0a372a020 938 \brief Signed Saturate
AnnaBridge 167:84c0a372a020 939 \details Saturates a signed value.
AnnaBridge 167:84c0a372a020 940 \param [in] value Value to be saturated
AnnaBridge 167:84c0a372a020 941 \param [in] sat Bit position to saturate to (1..32)
AnnaBridge 167:84c0a372a020 942 \return Saturated value
AnnaBridge 167:84c0a372a020 943 */
AnnaBridge 167:84c0a372a020 944 #define __SSAT __builtin_arm_ssat
AnnaBridge 167:84c0a372a020 945
AnnaBridge 167:84c0a372a020 946
AnnaBridge 167:84c0a372a020 947 /**
AnnaBridge 167:84c0a372a020 948 \brief Unsigned Saturate
AnnaBridge 167:84c0a372a020 949 \details Saturates an unsigned value.
AnnaBridge 167:84c0a372a020 950 \param [in] value Value to be saturated
AnnaBridge 167:84c0a372a020 951 \param [in] sat Bit position to saturate to (0..31)
AnnaBridge 167:84c0a372a020 952 \return Saturated value
AnnaBridge 167:84c0a372a020 953 */
AnnaBridge 167:84c0a372a020 954 #define __USAT __builtin_arm_usat
AnnaBridge 167:84c0a372a020 955
AnnaBridge 167:84c0a372a020 956
AnnaBridge 167:84c0a372a020 957 /**
AnnaBridge 167:84c0a372a020 958 \brief Rotate Right with Extend (32 bit)
AnnaBridge 167:84c0a372a020 959 \details Moves each bit of a bitstring right by one bit.
AnnaBridge 167:84c0a372a020 960 The carry input is shifted in at the left end of the bitstring.
AnnaBridge 167:84c0a372a020 961 \param [in] value Value to rotate
AnnaBridge 167:84c0a372a020 962 \return Rotated value
AnnaBridge 167:84c0a372a020 963 */
AnnaBridge 167:84c0a372a020 964 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
AnnaBridge 167:84c0a372a020 965 {
AnnaBridge 167:84c0a372a020 966 uint32_t result;
AnnaBridge 167:84c0a372a020 967
AnnaBridge 167:84c0a372a020 968 __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
AnnaBridge 167:84c0a372a020 969 return(result);
AnnaBridge 167:84c0a372a020 970 }
AnnaBridge 167:84c0a372a020 971
AnnaBridge 167:84c0a372a020 972
AnnaBridge 167:84c0a372a020 973 /**
AnnaBridge 167:84c0a372a020 974 \brief LDRT Unprivileged (8 bit)
AnnaBridge 167:84c0a372a020 975 \details Executes a Unprivileged LDRT instruction for 8 bit value.
AnnaBridge 167:84c0a372a020 976 \param [in] ptr Pointer to data
AnnaBridge 167:84c0a372a020 977 \return value of type uint8_t at (*ptr)
AnnaBridge 167:84c0a372a020 978 */
AnnaBridge 167:84c0a372a020 979 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr)
AnnaBridge 167:84c0a372a020 980 {
AnnaBridge 167:84c0a372a020 981 uint32_t result;
AnnaBridge 167:84c0a372a020 982
AnnaBridge 167:84c0a372a020 983 __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge 167:84c0a372a020 984 return ((uint8_t) result); /* Add explicit type cast here */
AnnaBridge 167:84c0a372a020 985 }
AnnaBridge 167:84c0a372a020 986
AnnaBridge 167:84c0a372a020 987
AnnaBridge 167:84c0a372a020 988 /**
AnnaBridge 167:84c0a372a020 989 \brief LDRT Unprivileged (16 bit)
AnnaBridge 167:84c0a372a020 990 \details Executes a Unprivileged LDRT instruction for 16 bit values.
AnnaBridge 167:84c0a372a020 991 \param [in] ptr Pointer to data
AnnaBridge 167:84c0a372a020 992 \return value of type uint16_t at (*ptr)
AnnaBridge 167:84c0a372a020 993 */
AnnaBridge 167:84c0a372a020 994 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr)
AnnaBridge 167:84c0a372a020 995 {
AnnaBridge 167:84c0a372a020 996 uint32_t result;
AnnaBridge 167:84c0a372a020 997
AnnaBridge 167:84c0a372a020 998 __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge 167:84c0a372a020 999 return ((uint16_t) result); /* Add explicit type cast here */
AnnaBridge 167:84c0a372a020 1000 }
AnnaBridge 167:84c0a372a020 1001
AnnaBridge 167:84c0a372a020 1002
AnnaBridge 167:84c0a372a020 1003 /**
AnnaBridge 167:84c0a372a020 1004 \brief LDRT Unprivileged (32 bit)
AnnaBridge 167:84c0a372a020 1005 \details Executes a Unprivileged LDRT instruction for 32 bit values.
AnnaBridge 167:84c0a372a020 1006 \param [in] ptr Pointer to data
AnnaBridge 167:84c0a372a020 1007 \return value of type uint32_t at (*ptr)
AnnaBridge 167:84c0a372a020 1008 */
AnnaBridge 167:84c0a372a020 1009 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr)
AnnaBridge 167:84c0a372a020 1010 {
AnnaBridge 167:84c0a372a020 1011 uint32_t result;
AnnaBridge 167:84c0a372a020 1012
AnnaBridge 167:84c0a372a020 1013 __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge 167:84c0a372a020 1014 return(result);
AnnaBridge 167:84c0a372a020 1015 }
AnnaBridge 167:84c0a372a020 1016
AnnaBridge 167:84c0a372a020 1017
AnnaBridge 167:84c0a372a020 1018 /**
AnnaBridge 167:84c0a372a020 1019 \brief STRT Unprivileged (8 bit)
AnnaBridge 167:84c0a372a020 1020 \details Executes a Unprivileged STRT instruction for 8 bit values.
AnnaBridge 167:84c0a372a020 1021 \param [in] value Value to store
AnnaBridge 167:84c0a372a020 1022 \param [in] ptr Pointer to location
AnnaBridge 167:84c0a372a020 1023 */
AnnaBridge 167:84c0a372a020 1024 __attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
AnnaBridge 167:84c0a372a020 1025 {
AnnaBridge 167:84c0a372a020 1026 __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge 167:84c0a372a020 1027 }
AnnaBridge 167:84c0a372a020 1028
AnnaBridge 167:84c0a372a020 1029
AnnaBridge 167:84c0a372a020 1030 /**
AnnaBridge 167:84c0a372a020 1031 \brief STRT Unprivileged (16 bit)
AnnaBridge 167:84c0a372a020 1032 \details Executes a Unprivileged STRT instruction for 16 bit values.
AnnaBridge 167:84c0a372a020 1033 \param [in] value Value to store
AnnaBridge 167:84c0a372a020 1034 \param [in] ptr Pointer to location
AnnaBridge 167:84c0a372a020 1035 */
AnnaBridge 167:84c0a372a020 1036 __attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
AnnaBridge 167:84c0a372a020 1037 {
AnnaBridge 167:84c0a372a020 1038 __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge 167:84c0a372a020 1039 }
AnnaBridge 167:84c0a372a020 1040
AnnaBridge 167:84c0a372a020 1041
AnnaBridge 167:84c0a372a020 1042 /**
AnnaBridge 167:84c0a372a020 1043 \brief STRT Unprivileged (32 bit)
AnnaBridge 167:84c0a372a020 1044 \details Executes a Unprivileged STRT instruction for 32 bit values.
AnnaBridge 167:84c0a372a020 1045 \param [in] value Value to store
AnnaBridge 167:84c0a372a020 1046 \param [in] ptr Pointer to location
AnnaBridge 167:84c0a372a020 1047 */
AnnaBridge 167:84c0a372a020 1048 __attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
AnnaBridge 167:84c0a372a020 1049 {
AnnaBridge 167:84c0a372a020 1050 __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
AnnaBridge 167:84c0a372a020 1051 }
AnnaBridge 167:84c0a372a020 1052
AnnaBridge 167:84c0a372a020 1053 #else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
AnnaBridge 167:84c0a372a020 1054 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
AnnaBridge 167:84c0a372a020 1055 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
AnnaBridge 167:84c0a372a020 1056
AnnaBridge 167:84c0a372a020 1057 /**
AnnaBridge 167:84c0a372a020 1058 \brief Signed Saturate
AnnaBridge 167:84c0a372a020 1059 \details Saturates a signed value.
AnnaBridge 167:84c0a372a020 1060 \param [in] value Value to be saturated
AnnaBridge 167:84c0a372a020 1061 \param [in] sat Bit position to saturate to (1..32)
AnnaBridge 167:84c0a372a020 1062 \return Saturated value
AnnaBridge 167:84c0a372a020 1063 */
AnnaBridge 167:84c0a372a020 1064 __attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
AnnaBridge 167:84c0a372a020 1065 {
AnnaBridge 167:84c0a372a020 1066 if ((sat >= 1U) && (sat <= 32U)) {
AnnaBridge 167:84c0a372a020 1067 const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
AnnaBridge 167:84c0a372a020 1068 const int32_t min = -1 - max ;
AnnaBridge 167:84c0a372a020 1069 if (val > max) {
AnnaBridge 167:84c0a372a020 1070 return max;
AnnaBridge 167:84c0a372a020 1071 } else if (val < min) {
AnnaBridge 167:84c0a372a020 1072 return min;
AnnaBridge 167:84c0a372a020 1073 }
AnnaBridge 167:84c0a372a020 1074 }
AnnaBridge 167:84c0a372a020 1075 return val;
AnnaBridge 167:84c0a372a020 1076 }
AnnaBridge 167:84c0a372a020 1077
AnnaBridge 167:84c0a372a020 1078 /**
AnnaBridge 167:84c0a372a020 1079 \brief Unsigned Saturate
AnnaBridge 167:84c0a372a020 1080 \details Saturates an unsigned value.
AnnaBridge 167:84c0a372a020 1081 \param [in] value Value to be saturated
AnnaBridge 167:84c0a372a020 1082 \param [in] sat Bit position to saturate to (0..31)
AnnaBridge 167:84c0a372a020 1083 \return Saturated value
AnnaBridge 167:84c0a372a020 1084 */
AnnaBridge 167:84c0a372a020 1085 __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
AnnaBridge 167:84c0a372a020 1086 {
AnnaBridge 167:84c0a372a020 1087 if (sat <= 31U) {
AnnaBridge 167:84c0a372a020 1088 const uint32_t max = ((1U << sat) - 1U);
AnnaBridge 167:84c0a372a020 1089 if (val > (int32_t)max) {
AnnaBridge 167:84c0a372a020 1090 return max;
AnnaBridge 167:84c0a372a020 1091 } else if (val < 0) {
AnnaBridge 167:84c0a372a020 1092 return 0U;
AnnaBridge 167:84c0a372a020 1093 }
AnnaBridge 167:84c0a372a020 1094 }
AnnaBridge 167:84c0a372a020 1095 return (uint32_t)val;
AnnaBridge 167:84c0a372a020 1096 }
AnnaBridge 167:84c0a372a020 1097
AnnaBridge 167:84c0a372a020 1098 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
AnnaBridge 167:84c0a372a020 1099 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
AnnaBridge 167:84c0a372a020 1100 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
AnnaBridge 167:84c0a372a020 1101
AnnaBridge 167:84c0a372a020 1102
AnnaBridge 167:84c0a372a020 1103 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
AnnaBridge 167:84c0a372a020 1104 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
AnnaBridge 167:84c0a372a020 1105 /**
AnnaBridge 167:84c0a372a020 1106 \brief Load-Acquire (8 bit)
AnnaBridge 167:84c0a372a020 1107 \details Executes a LDAB instruction for 8 bit value.
AnnaBridge 167:84c0a372a020 1108 \param [in] ptr Pointer to data
AnnaBridge 167:84c0a372a020 1109 \return value of type uint8_t at (*ptr)
AnnaBridge 167:84c0a372a020 1110 */
AnnaBridge 167:84c0a372a020 1111 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr)
AnnaBridge 167:84c0a372a020 1112 {
AnnaBridge 167:84c0a372a020 1113 uint32_t result;
AnnaBridge 167:84c0a372a020 1114
AnnaBridge 167:84c0a372a020 1115 __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge 167:84c0a372a020 1116 return ((uint8_t) result);
AnnaBridge 167:84c0a372a020 1117 }
AnnaBridge 167:84c0a372a020 1118
AnnaBridge 167:84c0a372a020 1119
AnnaBridge 167:84c0a372a020 1120 /**
AnnaBridge 167:84c0a372a020 1121 \brief Load-Acquire (16 bit)
AnnaBridge 167:84c0a372a020 1122 \details Executes a LDAH instruction for 16 bit values.
AnnaBridge 167:84c0a372a020 1123 \param [in] ptr Pointer to data
AnnaBridge 167:84c0a372a020 1124 \return value of type uint16_t at (*ptr)
AnnaBridge 167:84c0a372a020 1125 */
AnnaBridge 167:84c0a372a020 1126 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr)
AnnaBridge 167:84c0a372a020 1127 {
AnnaBridge 167:84c0a372a020 1128 uint32_t result;
AnnaBridge 167:84c0a372a020 1129
AnnaBridge 167:84c0a372a020 1130 __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge 167:84c0a372a020 1131 return ((uint16_t) result);
AnnaBridge 167:84c0a372a020 1132 }
AnnaBridge 167:84c0a372a020 1133
AnnaBridge 167:84c0a372a020 1134
AnnaBridge 167:84c0a372a020 1135 /**
AnnaBridge 167:84c0a372a020 1136 \brief Load-Acquire (32 bit)
AnnaBridge 167:84c0a372a020 1137 \details Executes a LDA instruction for 32 bit values.
AnnaBridge 167:84c0a372a020 1138 \param [in] ptr Pointer to data
AnnaBridge 167:84c0a372a020 1139 \return value of type uint32_t at (*ptr)
AnnaBridge 167:84c0a372a020 1140 */
AnnaBridge 167:84c0a372a020 1141 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr)
AnnaBridge 167:84c0a372a020 1142 {
AnnaBridge 167:84c0a372a020 1143 uint32_t result;
AnnaBridge 167:84c0a372a020 1144
AnnaBridge 167:84c0a372a020 1145 __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge 167:84c0a372a020 1146 return(result);
AnnaBridge 167:84c0a372a020 1147 }
AnnaBridge 167:84c0a372a020 1148
AnnaBridge 167:84c0a372a020 1149
AnnaBridge 167:84c0a372a020 1150 /**
AnnaBridge 167:84c0a372a020 1151 \brief Store-Release (8 bit)
AnnaBridge 167:84c0a372a020 1152 \details Executes a STLB instruction for 8 bit values.
AnnaBridge 167:84c0a372a020 1153 \param [in] value Value to store
AnnaBridge 167:84c0a372a020 1154 \param [in] ptr Pointer to location
AnnaBridge 167:84c0a372a020 1155 */
AnnaBridge 167:84c0a372a020 1156 __attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
AnnaBridge 167:84c0a372a020 1157 {
AnnaBridge 167:84c0a372a020 1158 __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge 167:84c0a372a020 1159 }
AnnaBridge 167:84c0a372a020 1160
AnnaBridge 167:84c0a372a020 1161
AnnaBridge 167:84c0a372a020 1162 /**
AnnaBridge 167:84c0a372a020 1163 \brief Store-Release (16 bit)
AnnaBridge 167:84c0a372a020 1164 \details Executes a STLH instruction for 16 bit values.
AnnaBridge 167:84c0a372a020 1165 \param [in] value Value to store
AnnaBridge 167:84c0a372a020 1166 \param [in] ptr Pointer to location
AnnaBridge 167:84c0a372a020 1167 */
AnnaBridge 167:84c0a372a020 1168 __attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
AnnaBridge 167:84c0a372a020 1169 {
AnnaBridge 167:84c0a372a020 1170 __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge 167:84c0a372a020 1171 }
AnnaBridge 167:84c0a372a020 1172
AnnaBridge 167:84c0a372a020 1173
AnnaBridge 167:84c0a372a020 1174 /**
AnnaBridge 167:84c0a372a020 1175 \brief Store-Release (32 bit)
AnnaBridge 167:84c0a372a020 1176 \details Executes a STL instruction for 32 bit values.
AnnaBridge 167:84c0a372a020 1177 \param [in] value Value to store
AnnaBridge 167:84c0a372a020 1178 \param [in] ptr Pointer to location
AnnaBridge 167:84c0a372a020 1179 */
AnnaBridge 167:84c0a372a020 1180 __attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr)
AnnaBridge 167:84c0a372a020 1181 {
AnnaBridge 167:84c0a372a020 1182 __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge 167:84c0a372a020 1183 }
AnnaBridge 167:84c0a372a020 1184
AnnaBridge 167:84c0a372a020 1185
AnnaBridge 167:84c0a372a020 1186 /**
AnnaBridge 167:84c0a372a020 1187 \brief Load-Acquire Exclusive (8 bit)
AnnaBridge 167:84c0a372a020 1188 \details Executes a LDAB exclusive instruction for 8 bit value.
AnnaBridge 167:84c0a372a020 1189 \param [in] ptr Pointer to data
AnnaBridge 167:84c0a372a020 1190 \return value of type uint8_t at (*ptr)
AnnaBridge 167:84c0a372a020 1191 */
AnnaBridge 167:84c0a372a020 1192 #define __LDAEXB (uint8_t)__builtin_arm_ldaex
AnnaBridge 167:84c0a372a020 1193
AnnaBridge 167:84c0a372a020 1194
AnnaBridge 167:84c0a372a020 1195 /**
AnnaBridge 167:84c0a372a020 1196 \brief Load-Acquire Exclusive (16 bit)
AnnaBridge 167:84c0a372a020 1197 \details Executes a LDAH exclusive instruction for 16 bit values.
AnnaBridge 167:84c0a372a020 1198 \param [in] ptr Pointer to data
AnnaBridge 167:84c0a372a020 1199 \return value of type uint16_t at (*ptr)
AnnaBridge 167:84c0a372a020 1200 */
AnnaBridge 167:84c0a372a020 1201 #define __LDAEXH (uint16_t)__builtin_arm_ldaex
AnnaBridge 167:84c0a372a020 1202
AnnaBridge 167:84c0a372a020 1203
AnnaBridge 167:84c0a372a020 1204 /**
AnnaBridge 167:84c0a372a020 1205 \brief Load-Acquire Exclusive (32 bit)
AnnaBridge 167:84c0a372a020 1206 \details Executes a LDA exclusive instruction for 32 bit values.
AnnaBridge 167:84c0a372a020 1207 \param [in] ptr Pointer to data
AnnaBridge 167:84c0a372a020 1208 \return value of type uint32_t at (*ptr)
AnnaBridge 167:84c0a372a020 1209 */
AnnaBridge 167:84c0a372a020 1210 #define __LDAEX (uint32_t)__builtin_arm_ldaex
AnnaBridge 167:84c0a372a020 1211
AnnaBridge 167:84c0a372a020 1212
AnnaBridge 167:84c0a372a020 1213 /**
AnnaBridge 167:84c0a372a020 1214 \brief Store-Release Exclusive (8 bit)
AnnaBridge 167:84c0a372a020 1215 \details Executes a STLB exclusive instruction for 8 bit values.
AnnaBridge 167:84c0a372a020 1216 \param [in] value Value to store
AnnaBridge 167:84c0a372a020 1217 \param [in] ptr Pointer to location
AnnaBridge 167:84c0a372a020 1218 \return 0 Function succeeded
AnnaBridge 167:84c0a372a020 1219 \return 1 Function failed
AnnaBridge 167:84c0a372a020 1220 */
AnnaBridge 167:84c0a372a020 1221 #define __STLEXB (uint32_t)__builtin_arm_stlex
AnnaBridge 167:84c0a372a020 1222
AnnaBridge 167:84c0a372a020 1223
AnnaBridge 167:84c0a372a020 1224 /**
AnnaBridge 167:84c0a372a020 1225 \brief Store-Release Exclusive (16 bit)
AnnaBridge 167:84c0a372a020 1226 \details Executes a STLH exclusive instruction for 16 bit values.
AnnaBridge 167:84c0a372a020 1227 \param [in] value Value to store
AnnaBridge 167:84c0a372a020 1228 \param [in] ptr Pointer to location
AnnaBridge 167:84c0a372a020 1229 \return 0 Function succeeded
AnnaBridge 167:84c0a372a020 1230 \return 1 Function failed
AnnaBridge 167:84c0a372a020 1231 */
AnnaBridge 167:84c0a372a020 1232 #define __STLEXH (uint32_t)__builtin_arm_stlex
AnnaBridge 167:84c0a372a020 1233
AnnaBridge 167:84c0a372a020 1234
AnnaBridge 167:84c0a372a020 1235 /**
AnnaBridge 167:84c0a372a020 1236 \brief Store-Release Exclusive (32 bit)
AnnaBridge 167:84c0a372a020 1237 \details Executes a STL exclusive instruction for 32 bit values.
AnnaBridge 167:84c0a372a020 1238 \param [in] value Value to store
AnnaBridge 167:84c0a372a020 1239 \param [in] ptr Pointer to location
AnnaBridge 167:84c0a372a020 1240 \return 0 Function succeeded
AnnaBridge 167:84c0a372a020 1241 \return 1 Function failed
AnnaBridge 167:84c0a372a020 1242 */
AnnaBridge 167:84c0a372a020 1243 #define __STLEX (uint32_t)__builtin_arm_stlex
AnnaBridge 167:84c0a372a020 1244
AnnaBridge 167:84c0a372a020 1245 #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
AnnaBridge 167:84c0a372a020 1246 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
AnnaBridge 167:84c0a372a020 1247
AnnaBridge 167:84c0a372a020 1248 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
AnnaBridge 167:84c0a372a020 1249
AnnaBridge 167:84c0a372a020 1250
AnnaBridge 167:84c0a372a020 1251 /* ################### Compiler specific Intrinsics ########################### */
AnnaBridge 167:84c0a372a020 1252 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
AnnaBridge 167:84c0a372a020 1253 Access to dedicated SIMD instructions
AnnaBridge 167:84c0a372a020 1254 @{
AnnaBridge 167:84c0a372a020 1255 */
AnnaBridge 167:84c0a372a020 1256
AnnaBridge 167:84c0a372a020 1257 #if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
AnnaBridge 167:84c0a372a020 1258
AnnaBridge 167:84c0a372a020 1259 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
AnnaBridge 167:84c0a372a020 1260 {
AnnaBridge 167:84c0a372a020 1261 uint32_t result;
AnnaBridge 167:84c0a372a020 1262
AnnaBridge 167:84c0a372a020 1263 __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 167:84c0a372a020 1264 return(result);
AnnaBridge 167:84c0a372a020 1265 }
AnnaBridge 167:84c0a372a020 1266
AnnaBridge 167:84c0a372a020 1267 __attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
AnnaBridge 167:84c0a372a020 1268 {
AnnaBridge 167:84c0a372a020 1269 uint32_t result;
AnnaBridge 167:84c0a372a020 1270
AnnaBridge 167:84c0a372a020 1271 __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 167:84c0a372a020 1272 return(result);
AnnaBridge 167:84c0a372a020 1273 }
AnnaBridge 167:84c0a372a020 1274
AnnaBridge 167:84c0a372a020 1275 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
AnnaBridge 167:84c0a372a020 1276 {
AnnaBridge 167:84c0a372a020 1277 uint32_t result;
AnnaBridge 167:84c0a372a020 1278
AnnaBridge 167:84c0a372a020 1279 __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 167:84c0a372a020 1280 return(result);
AnnaBridge 167:84c0a372a020 1281 }
AnnaBridge 167:84c0a372a020 1282
AnnaBridge 167:84c0a372a020 1283 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
AnnaBridge 167:84c0a372a020 1284 {
AnnaBridge 167:84c0a372a020 1285 uint32_t result;
AnnaBridge 167:84c0a372a020 1286
AnnaBridge 167:84c0a372a020 1287 __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 167:84c0a372a020 1288 return(result);
AnnaBridge 167:84c0a372a020 1289 }
AnnaBridge 167:84c0a372a020 1290
AnnaBridge 167:84c0a372a020 1291 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
AnnaBridge 167:84c0a372a020 1292 {
AnnaBridge 167:84c0a372a020 1293 uint32_t result;
AnnaBridge 167:84c0a372a020 1294
AnnaBridge 167:84c0a372a020 1295 __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 167:84c0a372a020 1296 return(result);
AnnaBridge 167:84c0a372a020 1297 }
AnnaBridge 167:84c0a372a020 1298
AnnaBridge 167:84c0a372a020 1299 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
AnnaBridge 167:84c0a372a020 1300 {
AnnaBridge 167:84c0a372a020 1301 uint32_t result;
AnnaBridge 167:84c0a372a020 1302
AnnaBridge 167:84c0a372a020 1303 __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 167:84c0a372a020 1304 return(result);
AnnaBridge 167:84c0a372a020 1305 }
AnnaBridge 167:84c0a372a020 1306
AnnaBridge 167:84c0a372a020 1307
AnnaBridge 167:84c0a372a020 1308 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
AnnaBridge 167:84c0a372a020 1309 {
AnnaBridge 167:84c0a372a020 1310 uint32_t result;
AnnaBridge 167:84c0a372a020 1311
AnnaBridge 167:84c0a372a020 1312 __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 167:84c0a372a020 1313 return(result);
AnnaBridge 167:84c0a372a020 1314 }
AnnaBridge 167:84c0a372a020 1315
AnnaBridge 167:84c0a372a020 1316 __attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
AnnaBridge 167:84c0a372a020 1317 {
AnnaBridge 167:84c0a372a020 1318 uint32_t result;
AnnaBridge 167:84c0a372a020 1319
AnnaBridge 167:84c0a372a020 1320 __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 167:84c0a372a020 1321 return(result);
AnnaBridge 167:84c0a372a020 1322 }
AnnaBridge 167:84c0a372a020 1323
AnnaBridge 167:84c0a372a020 1324 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
AnnaBridge 167:84c0a372a020 1325 {
AnnaBridge 167:84c0a372a020 1326 uint32_t result;
AnnaBridge 167:84c0a372a020 1327
AnnaBridge 167:84c0a372a020 1328 __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 167:84c0a372a020 1329 return(result);
AnnaBridge 167:84c0a372a020 1330 }
AnnaBridge 167:84c0a372a020 1331
AnnaBridge 167:84c0a372a020 1332 __attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
AnnaBridge 167:84c0a372a020 1333 {
AnnaBridge 167:84c0a372a020 1334 uint32_t result;
AnnaBridge 167:84c0a372a020 1335
AnnaBridge 167:84c0a372a020 1336 __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 167:84c0a372a020 1337 return(result);
AnnaBridge 167:84c0a372a020 1338 }
AnnaBridge 167:84c0a372a020 1339
AnnaBridge 167:84c0a372a020 1340 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
AnnaBridge 167:84c0a372a020 1341 {
AnnaBridge 167:84c0a372a020 1342 uint32_t result;
AnnaBridge 167:84c0a372a020 1343
AnnaBridge 167:84c0a372a020 1344 __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 167:84c0a372a020 1345 return(result);
AnnaBridge 167:84c0a372a020 1346 }
AnnaBridge 167:84c0a372a020 1347
AnnaBridge 167:84c0a372a020 1348 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
AnnaBridge 167:84c0a372a020 1349 {
AnnaBridge 167:84c0a372a020 1350 uint32_t result;
AnnaBridge 167:84c0a372a020 1351
AnnaBridge 167:84c0a372a020 1352 __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 167:84c0a372a020 1353 return(result);
AnnaBridge 167:84c0a372a020 1354 }
AnnaBridge 167:84c0a372a020 1355
AnnaBridge 167:84c0a372a020 1356
AnnaBridge 167:84c0a372a020 1357 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
AnnaBridge 167:84c0a372a020 1358 {
AnnaBridge 167:84c0a372a020 1359 uint32_t result;
AnnaBridge 167:84c0a372a020 1360
AnnaBridge 167:84c0a372a020 1361 __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 167:84c0a372a020 1362 return(result);
AnnaBridge 167:84c0a372a020 1363 }
AnnaBridge 167:84c0a372a020 1364
AnnaBridge 167:84c0a372a020 1365 __attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
AnnaBridge 167:84c0a372a020 1366 {
AnnaBridge 167:84c0a372a020 1367 uint32_t result;
AnnaBridge 167:84c0a372a020 1368
AnnaBridge 167:84c0a372a020 1369 __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 167:84c0a372a020 1370 return(result);
AnnaBridge 167:84c0a372a020 1371 }
AnnaBridge 167:84c0a372a020 1372
AnnaBridge 167:84c0a372a020 1373 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
AnnaBridge 167:84c0a372a020 1374 {
AnnaBridge 167:84c0a372a020 1375 uint32_t result;
AnnaBridge 167:84c0a372a020 1376
AnnaBridge 167:84c0a372a020 1377 __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 167:84c0a372a020 1378 return(result);
AnnaBridge 167:84c0a372a020 1379 }
AnnaBridge 167:84c0a372a020 1380
AnnaBridge 167:84c0a372a020 1381 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
AnnaBridge 167:84c0a372a020 1382 {
AnnaBridge 167:84c0a372a020 1383 uint32_t result;
AnnaBridge 167:84c0a372a020 1384
AnnaBridge 167:84c0a372a020 1385 __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 167:84c0a372a020 1386 return(result);
AnnaBridge 167:84c0a372a020 1387 }
AnnaBridge 167:84c0a372a020 1388
AnnaBridge 167:84c0a372a020 1389 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
AnnaBridge 167:84c0a372a020 1390 {
AnnaBridge 167:84c0a372a020 1391 uint32_t result;
AnnaBridge 167:84c0a372a020 1392
AnnaBridge 167:84c0a372a020 1393 __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 167:84c0a372a020 1394 return(result);
AnnaBridge 167:84c0a372a020 1395 }
AnnaBridge 167:84c0a372a020 1396
AnnaBridge 167:84c0a372a020 1397 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
AnnaBridge 167:84c0a372a020 1398 {
AnnaBridge 167:84c0a372a020 1399 uint32_t result;
AnnaBridge 167:84c0a372a020 1400
AnnaBridge 167:84c0a372a020 1401 __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 167:84c0a372a020 1402 return(result);
AnnaBridge 167:84c0a372a020 1403 }
AnnaBridge 167:84c0a372a020 1404
AnnaBridge 167:84c0a372a020 1405 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
AnnaBridge 167:84c0a372a020 1406 {
AnnaBridge 167:84c0a372a020 1407 uint32_t result;
AnnaBridge 167:84c0a372a020 1408
AnnaBridge 167:84c0a372a020 1409 __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 167:84c0a372a020 1410 return(result);
AnnaBridge 167:84c0a372a020 1411 }
AnnaBridge 167:84c0a372a020 1412
AnnaBridge 167:84c0a372a020 1413 __attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
AnnaBridge 167:84c0a372a020 1414 {
AnnaBridge 167:84c0a372a020 1415 uint32_t result;
AnnaBridge 167:84c0a372a020 1416
AnnaBridge 167:84c0a372a020 1417 __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 167:84c0a372a020 1418 return(result);
AnnaBridge 167:84c0a372a020 1419 }
AnnaBridge 167:84c0a372a020 1420
AnnaBridge 167:84c0a372a020 1421 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
AnnaBridge 167:84c0a372a020 1422 {
AnnaBridge 167:84c0a372a020 1423 uint32_t result;
AnnaBridge 167:84c0a372a020 1424
AnnaBridge 167:84c0a372a020 1425 __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 167:84c0a372a020 1426 return(result);
AnnaBridge 167:84c0a372a020 1427 }
AnnaBridge 167:84c0a372a020 1428
AnnaBridge 167:84c0a372a020 1429 __attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
AnnaBridge 167:84c0a372a020 1430 {
AnnaBridge 167:84c0a372a020 1431 uint32_t result;
AnnaBridge 167:84c0a372a020 1432
AnnaBridge 167:84c0a372a020 1433 __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 167:84c0a372a020 1434 return(result);
AnnaBridge 167:84c0a372a020 1435 }
AnnaBridge 167:84c0a372a020 1436
AnnaBridge 167:84c0a372a020 1437 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
AnnaBridge 167:84c0a372a020 1438 {
AnnaBridge 167:84c0a372a020 1439 uint32_t result;
AnnaBridge 167:84c0a372a020 1440
AnnaBridge 167:84c0a372a020 1441 __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 167:84c0a372a020 1442 return(result);
AnnaBridge 167:84c0a372a020 1443 }
AnnaBridge 167:84c0a372a020 1444
AnnaBridge 167:84c0a372a020 1445 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
AnnaBridge 167:84c0a372a020 1446 {
AnnaBridge 167:84c0a372a020 1447 uint32_t result;
AnnaBridge 167:84c0a372a020 1448
AnnaBridge 167:84c0a372a020 1449 __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 167:84c0a372a020 1450 return(result);
AnnaBridge 167:84c0a372a020 1451 }
AnnaBridge 167:84c0a372a020 1452
AnnaBridge 167:84c0a372a020 1453 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
AnnaBridge 167:84c0a372a020 1454 {
AnnaBridge 167:84c0a372a020 1455 uint32_t result;
AnnaBridge 167:84c0a372a020 1456
AnnaBridge 167:84c0a372a020 1457 __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 167:84c0a372a020 1458 return(result);
AnnaBridge 167:84c0a372a020 1459 }
AnnaBridge 167:84c0a372a020 1460
AnnaBridge 167:84c0a372a020 1461 __attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
AnnaBridge 167:84c0a372a020 1462 {
AnnaBridge 167:84c0a372a020 1463 uint32_t result;
AnnaBridge 167:84c0a372a020 1464
AnnaBridge 167:84c0a372a020 1465 __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 167:84c0a372a020 1466 return(result);
AnnaBridge 167:84c0a372a020 1467 }
AnnaBridge 167:84c0a372a020 1468
AnnaBridge 167:84c0a372a020 1469 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
AnnaBridge 167:84c0a372a020 1470 {
AnnaBridge 167:84c0a372a020 1471 uint32_t result;
AnnaBridge 167:84c0a372a020 1472
AnnaBridge 167:84c0a372a020 1473 __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 167:84c0a372a020 1474 return(result);
AnnaBridge 167:84c0a372a020 1475 }
AnnaBridge 167:84c0a372a020 1476
AnnaBridge 167:84c0a372a020 1477 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
AnnaBridge 167:84c0a372a020 1478 {
AnnaBridge 167:84c0a372a020 1479 uint32_t result;
AnnaBridge 167:84c0a372a020 1480
AnnaBridge 167:84c0a372a020 1481 __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 167:84c0a372a020 1482 return(result);
AnnaBridge 167:84c0a372a020 1483 }
AnnaBridge 167:84c0a372a020 1484
AnnaBridge 167:84c0a372a020 1485 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
AnnaBridge 167:84c0a372a020 1486 {
AnnaBridge 167:84c0a372a020 1487 uint32_t result;
AnnaBridge 167:84c0a372a020 1488
AnnaBridge 167:84c0a372a020 1489 __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 167:84c0a372a020 1490 return(result);
AnnaBridge 167:84c0a372a020 1491 }
AnnaBridge 167:84c0a372a020 1492
AnnaBridge 167:84c0a372a020 1493 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
AnnaBridge 167:84c0a372a020 1494 {
AnnaBridge 167:84c0a372a020 1495 uint32_t result;
AnnaBridge 167:84c0a372a020 1496
AnnaBridge 167:84c0a372a020 1497 __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 167:84c0a372a020 1498 return(result);
AnnaBridge 167:84c0a372a020 1499 }
AnnaBridge 167:84c0a372a020 1500
AnnaBridge 167:84c0a372a020 1501 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
AnnaBridge 167:84c0a372a020 1502 {
AnnaBridge 167:84c0a372a020 1503 uint32_t result;
AnnaBridge 167:84c0a372a020 1504
AnnaBridge 167:84c0a372a020 1505 __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 167:84c0a372a020 1506 return(result);
AnnaBridge 167:84c0a372a020 1507 }
AnnaBridge 167:84c0a372a020 1508
AnnaBridge 167:84c0a372a020 1509 __attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
AnnaBridge 167:84c0a372a020 1510 {
AnnaBridge 167:84c0a372a020 1511 uint32_t result;
AnnaBridge 167:84c0a372a020 1512
AnnaBridge 167:84c0a372a020 1513 __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 167:84c0a372a020 1514 return(result);
AnnaBridge 167:84c0a372a020 1515 }
AnnaBridge 167:84c0a372a020 1516
AnnaBridge 167:84c0a372a020 1517 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
AnnaBridge 167:84c0a372a020 1518 {
AnnaBridge 167:84c0a372a020 1519 uint32_t result;
AnnaBridge 167:84c0a372a020 1520
AnnaBridge 167:84c0a372a020 1521 __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 167:84c0a372a020 1522 return(result);
AnnaBridge 167:84c0a372a020 1523 }
AnnaBridge 167:84c0a372a020 1524
AnnaBridge 167:84c0a372a020 1525 __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
AnnaBridge 167:84c0a372a020 1526 {
AnnaBridge 167:84c0a372a020 1527 uint32_t result;
AnnaBridge 167:84c0a372a020 1528
AnnaBridge 167:84c0a372a020 1529 __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 167:84c0a372a020 1530 return(result);
AnnaBridge 167:84c0a372a020 1531 }
AnnaBridge 167:84c0a372a020 1532
AnnaBridge 167:84c0a372a020 1533 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
AnnaBridge 167:84c0a372a020 1534 {
AnnaBridge 167:84c0a372a020 1535 uint32_t result;
AnnaBridge 167:84c0a372a020 1536
AnnaBridge 167:84c0a372a020 1537 __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 167:84c0a372a020 1538 return(result);
AnnaBridge 167:84c0a372a020 1539 }
AnnaBridge 167:84c0a372a020 1540
AnnaBridge 167:84c0a372a020 1541 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
AnnaBridge 167:84c0a372a020 1542 {
AnnaBridge 167:84c0a372a020 1543 uint32_t result;
AnnaBridge 167:84c0a372a020 1544
AnnaBridge 167:84c0a372a020 1545 __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 167:84c0a372a020 1546 return(result);
AnnaBridge 167:84c0a372a020 1547 }
AnnaBridge 167:84c0a372a020 1548
AnnaBridge 167:84c0a372a020 1549 __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
AnnaBridge 167:84c0a372a020 1550 {
AnnaBridge 167:84c0a372a020 1551 uint32_t result;
AnnaBridge 167:84c0a372a020 1552
AnnaBridge 167:84c0a372a020 1553 __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 167:84c0a372a020 1554 return(result);
AnnaBridge 167:84c0a372a020 1555 }
AnnaBridge 167:84c0a372a020 1556
AnnaBridge 167:84c0a372a020 1557 __attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
AnnaBridge 167:84c0a372a020 1558 {
AnnaBridge 167:84c0a372a020 1559 uint32_t result;
AnnaBridge 167:84c0a372a020 1560
AnnaBridge 167:84c0a372a020 1561 __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
AnnaBridge 167:84c0a372a020 1562 return(result);
AnnaBridge 167:84c0a372a020 1563 }
AnnaBridge 167:84c0a372a020 1564
AnnaBridge 167:84c0a372a020 1565 #define __SSAT16(ARG1,ARG2) \
AnnaBridge 167:84c0a372a020 1566 ({ \
AnnaBridge 167:84c0a372a020 1567 int32_t __RES, __ARG1 = (ARG1); \
AnnaBridge 167:84c0a372a020 1568 __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
AnnaBridge 167:84c0a372a020 1569 __RES; \
AnnaBridge 167:84c0a372a020 1570 })
AnnaBridge 167:84c0a372a020 1571
AnnaBridge 167:84c0a372a020 1572 #define __USAT16(ARG1,ARG2) \
AnnaBridge 167:84c0a372a020 1573 ({ \
AnnaBridge 167:84c0a372a020 1574 uint32_t __RES, __ARG1 = (ARG1); \
AnnaBridge 167:84c0a372a020 1575 __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
AnnaBridge 167:84c0a372a020 1576 __RES; \
AnnaBridge 167:84c0a372a020 1577 })
AnnaBridge 167:84c0a372a020 1578
AnnaBridge 167:84c0a372a020 1579 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
AnnaBridge 167:84c0a372a020 1580 {
AnnaBridge 167:84c0a372a020 1581 uint32_t result;
AnnaBridge 167:84c0a372a020 1582
AnnaBridge 167:84c0a372a020 1583 __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
AnnaBridge 167:84c0a372a020 1584 return(result);
AnnaBridge 167:84c0a372a020 1585 }
AnnaBridge 167:84c0a372a020 1586
AnnaBridge 167:84c0a372a020 1587 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
AnnaBridge 167:84c0a372a020 1588 {
AnnaBridge 167:84c0a372a020 1589 uint32_t result;
AnnaBridge 167:84c0a372a020 1590
AnnaBridge 167:84c0a372a020 1591 __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 167:84c0a372a020 1592 return(result);
AnnaBridge 167:84c0a372a020 1593 }
AnnaBridge 167:84c0a372a020 1594
AnnaBridge 167:84c0a372a020 1595 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
AnnaBridge 167:84c0a372a020 1596 {
AnnaBridge 167:84c0a372a020 1597 uint32_t result;
AnnaBridge 167:84c0a372a020 1598
AnnaBridge 167:84c0a372a020 1599 __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
AnnaBridge 167:84c0a372a020 1600 return(result);
AnnaBridge 167:84c0a372a020 1601 }
AnnaBridge 167:84c0a372a020 1602
AnnaBridge 167:84c0a372a020 1603 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
AnnaBridge 167:84c0a372a020 1604 {
AnnaBridge 167:84c0a372a020 1605 uint32_t result;
AnnaBridge 167:84c0a372a020 1606
AnnaBridge 167:84c0a372a020 1607 __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 167:84c0a372a020 1608 return(result);
AnnaBridge 167:84c0a372a020 1609 }
AnnaBridge 167:84c0a372a020 1610
AnnaBridge 167:84c0a372a020 1611 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
AnnaBridge 167:84c0a372a020 1612 {
AnnaBridge 167:84c0a372a020 1613 uint32_t result;
AnnaBridge 167:84c0a372a020 1614
AnnaBridge 167:84c0a372a020 1615 __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 167:84c0a372a020 1616 return(result);
AnnaBridge 167:84c0a372a020 1617 }
AnnaBridge 167:84c0a372a020 1618
AnnaBridge 167:84c0a372a020 1619 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
AnnaBridge 167:84c0a372a020 1620 {
AnnaBridge 167:84c0a372a020 1621 uint32_t result;
AnnaBridge 167:84c0a372a020 1622
AnnaBridge 167:84c0a372a020 1623 __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 167:84c0a372a020 1624 return(result);
AnnaBridge 167:84c0a372a020 1625 }
AnnaBridge 167:84c0a372a020 1626
AnnaBridge 167:84c0a372a020 1627 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
AnnaBridge 167:84c0a372a020 1628 {
AnnaBridge 167:84c0a372a020 1629 uint32_t result;
AnnaBridge 167:84c0a372a020 1630
AnnaBridge 167:84c0a372a020 1631 __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
AnnaBridge 167:84c0a372a020 1632 return(result);
AnnaBridge 167:84c0a372a020 1633 }
AnnaBridge 167:84c0a372a020 1634
AnnaBridge 167:84c0a372a020 1635 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
AnnaBridge 167:84c0a372a020 1636 {
AnnaBridge 167:84c0a372a020 1637 uint32_t result;
AnnaBridge 167:84c0a372a020 1638
AnnaBridge 167:84c0a372a020 1639 __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
AnnaBridge 167:84c0a372a020 1640 return(result);
AnnaBridge 167:84c0a372a020 1641 }
AnnaBridge 167:84c0a372a020 1642
AnnaBridge 167:84c0a372a020 1643 __attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
AnnaBridge 167:84c0a372a020 1644 {
AnnaBridge 167:84c0a372a020 1645 union llreg_u{
AnnaBridge 167:84c0a372a020 1646 uint32_t w32[2];
AnnaBridge 167:84c0a372a020 1647 uint64_t w64;
AnnaBridge 167:84c0a372a020 1648 } llr;
AnnaBridge 167:84c0a372a020 1649 llr.w64 = acc;
AnnaBridge 167:84c0a372a020 1650
AnnaBridge 167:84c0a372a020 1651 #ifndef __ARMEB__ /* Little endian */
AnnaBridge 167:84c0a372a020 1652 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
AnnaBridge 167:84c0a372a020 1653 #else /* Big endian */
AnnaBridge 167:84c0a372a020 1654 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
AnnaBridge 167:84c0a372a020 1655 #endif
AnnaBridge 167:84c0a372a020 1656
AnnaBridge 167:84c0a372a020 1657 return(llr.w64);
AnnaBridge 167:84c0a372a020 1658 }
AnnaBridge 167:84c0a372a020 1659
AnnaBridge 167:84c0a372a020 1660 __attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
AnnaBridge 167:84c0a372a020 1661 {
AnnaBridge 167:84c0a372a020 1662 union llreg_u{
AnnaBridge 167:84c0a372a020 1663 uint32_t w32[2];
AnnaBridge 167:84c0a372a020 1664 uint64_t w64;
AnnaBridge 167:84c0a372a020 1665 } llr;
AnnaBridge 167:84c0a372a020 1666 llr.w64 = acc;
AnnaBridge 167:84c0a372a020 1667
AnnaBridge 167:84c0a372a020 1668 #ifndef __ARMEB__ /* Little endian */
AnnaBridge 167:84c0a372a020 1669 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
AnnaBridge 167:84c0a372a020 1670 #else /* Big endian */
AnnaBridge 167:84c0a372a020 1671 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
AnnaBridge 167:84c0a372a020 1672 #endif
AnnaBridge 167:84c0a372a020 1673
AnnaBridge 167:84c0a372a020 1674 return(llr.w64);
AnnaBridge 167:84c0a372a020 1675 }
AnnaBridge 167:84c0a372a020 1676
AnnaBridge 167:84c0a372a020 1677 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
AnnaBridge 167:84c0a372a020 1678 {
AnnaBridge 167:84c0a372a020 1679 uint32_t result;
AnnaBridge 167:84c0a372a020 1680
AnnaBridge 167:84c0a372a020 1681 __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 167:84c0a372a020 1682 return(result);
AnnaBridge 167:84c0a372a020 1683 }
AnnaBridge 167:84c0a372a020 1684
AnnaBridge 167:84c0a372a020 1685 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
AnnaBridge 167:84c0a372a020 1686 {
AnnaBridge 167:84c0a372a020 1687 uint32_t result;
AnnaBridge 167:84c0a372a020 1688
AnnaBridge 167:84c0a372a020 1689 __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 167:84c0a372a020 1690 return(result);
AnnaBridge 167:84c0a372a020 1691 }
AnnaBridge 167:84c0a372a020 1692
AnnaBridge 167:84c0a372a020 1693 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
AnnaBridge 167:84c0a372a020 1694 {
AnnaBridge 167:84c0a372a020 1695 uint32_t result;
AnnaBridge 167:84c0a372a020 1696
AnnaBridge 167:84c0a372a020 1697 __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
AnnaBridge 167:84c0a372a020 1698 return(result);
AnnaBridge 167:84c0a372a020 1699 }
AnnaBridge 167:84c0a372a020 1700
AnnaBridge 167:84c0a372a020 1701 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
AnnaBridge 167:84c0a372a020 1702 {
AnnaBridge 167:84c0a372a020 1703 uint32_t result;
AnnaBridge 167:84c0a372a020 1704
AnnaBridge 167:84c0a372a020 1705 __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
AnnaBridge 167:84c0a372a020 1706 return(result);
AnnaBridge 167:84c0a372a020 1707 }
AnnaBridge 167:84c0a372a020 1708
AnnaBridge 167:84c0a372a020 1709 __attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
AnnaBridge 167:84c0a372a020 1710 {
AnnaBridge 167:84c0a372a020 1711 union llreg_u{
AnnaBridge 167:84c0a372a020 1712 uint32_t w32[2];
AnnaBridge 167:84c0a372a020 1713 uint64_t w64;
AnnaBridge 167:84c0a372a020 1714 } llr;
AnnaBridge 167:84c0a372a020 1715 llr.w64 = acc;
AnnaBridge 167:84c0a372a020 1716
AnnaBridge 167:84c0a372a020 1717 #ifndef __ARMEB__ /* Little endian */
AnnaBridge 167:84c0a372a020 1718 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
AnnaBridge 167:84c0a372a020 1719 #else /* Big endian */
AnnaBridge 167:84c0a372a020 1720 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
AnnaBridge 167:84c0a372a020 1721 #endif
AnnaBridge 167:84c0a372a020 1722
AnnaBridge 167:84c0a372a020 1723 return(llr.w64);
AnnaBridge 167:84c0a372a020 1724 }
AnnaBridge 167:84c0a372a020 1725
AnnaBridge 167:84c0a372a020 1726 __attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
AnnaBridge 167:84c0a372a020 1727 {
AnnaBridge 167:84c0a372a020 1728 union llreg_u{
AnnaBridge 167:84c0a372a020 1729 uint32_t w32[2];
AnnaBridge 167:84c0a372a020 1730 uint64_t w64;
AnnaBridge 167:84c0a372a020 1731 } llr;
AnnaBridge 167:84c0a372a020 1732 llr.w64 = acc;
AnnaBridge 167:84c0a372a020 1733
AnnaBridge 167:84c0a372a020 1734 #ifndef __ARMEB__ /* Little endian */
AnnaBridge 167:84c0a372a020 1735 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
AnnaBridge 167:84c0a372a020 1736 #else /* Big endian */
AnnaBridge 167:84c0a372a020 1737 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
AnnaBridge 167:84c0a372a020 1738 #endif
AnnaBridge 167:84c0a372a020 1739
AnnaBridge 167:84c0a372a020 1740 return(llr.w64);
AnnaBridge 167:84c0a372a020 1741 }
AnnaBridge 167:84c0a372a020 1742
AnnaBridge 167:84c0a372a020 1743 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
AnnaBridge 167:84c0a372a020 1744 {
AnnaBridge 167:84c0a372a020 1745 uint32_t result;
AnnaBridge 167:84c0a372a020 1746
AnnaBridge 167:84c0a372a020 1747 __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 167:84c0a372a020 1748 return(result);
AnnaBridge 167:84c0a372a020 1749 }
AnnaBridge 167:84c0a372a020 1750
AnnaBridge 167:84c0a372a020 1751 __attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2)
AnnaBridge 167:84c0a372a020 1752 {
AnnaBridge 167:84c0a372a020 1753 int32_t result;
AnnaBridge 167:84c0a372a020 1754
AnnaBridge 167:84c0a372a020 1755 __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 167:84c0a372a020 1756 return(result);
AnnaBridge 167:84c0a372a020 1757 }
AnnaBridge 167:84c0a372a020 1758
AnnaBridge 167:84c0a372a020 1759 __attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2)
AnnaBridge 167:84c0a372a020 1760 {
AnnaBridge 167:84c0a372a020 1761 int32_t result;
AnnaBridge 167:84c0a372a020 1762
AnnaBridge 167:84c0a372a020 1763 __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 167:84c0a372a020 1764 return(result);
AnnaBridge 167:84c0a372a020 1765 }
AnnaBridge 167:84c0a372a020 1766
AnnaBridge 167:84c0a372a020 1767 #if 0
AnnaBridge 167:84c0a372a020 1768 #define __PKHBT(ARG1,ARG2,ARG3) \
AnnaBridge 167:84c0a372a020 1769 ({ \
AnnaBridge 167:84c0a372a020 1770 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
AnnaBridge 167:84c0a372a020 1771 __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
AnnaBridge 167:84c0a372a020 1772 __RES; \
AnnaBridge 167:84c0a372a020 1773 })
AnnaBridge 167:84c0a372a020 1774
AnnaBridge 167:84c0a372a020 1775 #define __PKHTB(ARG1,ARG2,ARG3) \
AnnaBridge 167:84c0a372a020 1776 ({ \
AnnaBridge 167:84c0a372a020 1777 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
AnnaBridge 167:84c0a372a020 1778 if (ARG3 == 0) \
AnnaBridge 167:84c0a372a020 1779 __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
AnnaBridge 167:84c0a372a020 1780 else \
AnnaBridge 167:84c0a372a020 1781 __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
AnnaBridge 167:84c0a372a020 1782 __RES; \
AnnaBridge 167:84c0a372a020 1783 })
AnnaBridge 167:84c0a372a020 1784 #endif
AnnaBridge 167:84c0a372a020 1785
AnnaBridge 167:84c0a372a020 1786 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
AnnaBridge 167:84c0a372a020 1787 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
AnnaBridge 167:84c0a372a020 1788
AnnaBridge 167:84c0a372a020 1789 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
AnnaBridge 167:84c0a372a020 1790 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
AnnaBridge 167:84c0a372a020 1791
AnnaBridge 167:84c0a372a020 1792 __attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
AnnaBridge 167:84c0a372a020 1793 {
AnnaBridge 167:84c0a372a020 1794 int32_t result;
AnnaBridge 167:84c0a372a020 1795
AnnaBridge 167:84c0a372a020 1796 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
AnnaBridge 167:84c0a372a020 1797 return(result);
AnnaBridge 167:84c0a372a020 1798 }
AnnaBridge 167:84c0a372a020 1799
AnnaBridge 167:84c0a372a020 1800 #endif /* (__ARM_FEATURE_DSP == 1) */
AnnaBridge 167:84c0a372a020 1801 /*@} end of group CMSIS_SIMD_intrinsics */
AnnaBridge 167:84c0a372a020 1802
AnnaBridge 167:84c0a372a020 1803
AnnaBridge 167:84c0a372a020 1804 #endif /* __CMSIS_ARMCLANG_H */