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TARGET_WIZwiki_W7500/W7500x_pwm.h@101:7cff1c4259d7, 2015-06-09 (annotated)

Committer:
Kojto
Date:
Tue Jun 09 14:29:26 2015 +0100
Revision:
101:7cff1c4259d7
Release 101 of the mbed library



Changes:

- new platform: APPNEARME_MICRONFCBOARD, MTS_DRAGONFLY_F411RE, MAX32600MBED, WIZwiki_W7500

- Silabs memory optimization in gpio, pwm fixes

- SPI  - ssel documentation fixes and its use

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 101:7cff1c4259d7 1 /**
Kojto 101:7cff1c4259d7 2 ******************************************************************************
Kojto 101:7cff1c4259d7 3 * @file
Kojto 101:7cff1c4259d7 4 * @author
Kojto 101:7cff1c4259d7 5 * @version
Kojto 101:7cff1c4259d7 6 * @date
Kojto 101:7cff1c4259d7 7 * @brief This file contains all the functions prototypes for the UART
Kojto 101:7cff1c4259d7 8 * firmware library.
Kojto 101:7cff1c4259d7 9 ******************************************************************************
Kojto 101:7cff1c4259d7 10 *
Kojto 101:7cff1c4259d7 11 ******************************************************************************
Kojto 101:7cff1c4259d7 12 */
Kojto 101:7cff1c4259d7 13
Kojto 101:7cff1c4259d7 14 /* Define to prevent recursive inclusion -------------------------------------*/
Kojto 101:7cff1c4259d7 15 #ifndef __W7500X_PWM_H
Kojto 101:7cff1c4259d7 16 #define __W7500X_PWM_H
Kojto 101:7cff1c4259d7 17
Kojto 101:7cff1c4259d7 18 #ifdef __cplusplus
Kojto 101:7cff1c4259d7 19 extern "C" {
Kojto 101:7cff1c4259d7 20 #endif
Kojto 101:7cff1c4259d7 21
Kojto 101:7cff1c4259d7 22 /* Includes ------------------------------------------------------------------*/
Kojto 101:7cff1c4259d7 23 #include "W7500x.h"
Kojto 101:7cff1c4259d7 24
Kojto 101:7cff1c4259d7 25 /**********************************************************************************************/
Kojto 101:7cff1c4259d7 26 /**********************************************************************************************/
Kojto 101:7cff1c4259d7 27 // This structure and define must be in W7500x.h
Kojto 101:7cff1c4259d7 28 /**********************************************************************************************/
Kojto 101:7cff1c4259d7 29 /**********************************************************************************************/
Kojto 101:7cff1c4259d7 30
Kojto 101:7cff1c4259d7 31 typedef struct
Kojto 101:7cff1c4259d7 32 {
Kojto 101:7cff1c4259d7 33 uint32_t PWM_CHn_PEEER;
Kojto 101:7cff1c4259d7 34 }PWM_CtrlPWMOutputTypeDef;
Kojto 101:7cff1c4259d7 35
Kojto 101:7cff1c4259d7 36 typedef struct
Kojto 101:7cff1c4259d7 37 {
Kojto 101:7cff1c4259d7 38 uint32_t PWM_CHn_PR;
Kojto 101:7cff1c4259d7 39 uint32_t PWM_CHn_MR;
Kojto 101:7cff1c4259d7 40 uint32_t PWM_CHn_LR;
Kojto 101:7cff1c4259d7 41 uint32_t PWM_CHn_UDMR;
Kojto 101:7cff1c4259d7 42 uint32_t PWM_CHn_PDMR;
Kojto 101:7cff1c4259d7 43 uint32_t PWM_CHn_DZCR;
Kojto 101:7cff1c4259d7 44 }PWM_DeadzoneModeInitTypDef;
Kojto 101:7cff1c4259d7 45
Kojto 101:7cff1c4259d7 46 #define IS_PWM_ALL_CH(CHn) ((CHn == PWM_CH0) || \
Kojto 101:7cff1c4259d7 47 (CHn == PWM_CH1) || \
Kojto 101:7cff1c4259d7 48 (CHn == PWM_CH2) || \
Kojto 101:7cff1c4259d7 49 (CHn == PWM_CH3) || \
Kojto 101:7cff1c4259d7 50 (CHn == PWM_CH4) || \
Kojto 101:7cff1c4259d7 51 (CHn == PWM_CH5) || \
Kojto 101:7cff1c4259d7 52 (CHn == PWM_CH6) || \
Kojto 101:7cff1c4259d7 53 (CHn == PWM_CH7))
Kojto 101:7cff1c4259d7 54
Kojto 101:7cff1c4259d7 55 #define PWM_IER_IE0_Enable (0x1ul << 0)
Kojto 101:7cff1c4259d7 56 #define PWM_IER_IE1_Enable (0x1ul << 1)
Kojto 101:7cff1c4259d7 57 #define PWM_IER_IE2_Enable (0x1ul << 2)
Kojto 101:7cff1c4259d7 58 #define PWM_IER_IE3_Enable (0x1ul << 3)
Kojto 101:7cff1c4259d7 59 #define PWM_IER_IE4_Enable (0x1ul << 4)
Kojto 101:7cff1c4259d7 60 #define PWM_IER_IE5_Enable (0x1ul << 5)
Kojto 101:7cff1c4259d7 61 #define PWM_IER_IE6_Enable (0x1ul << 6)
Kojto 101:7cff1c4259d7 62 #define PWM_IER_IE7_Enable (0x1ul << 7)
Kojto 101:7cff1c4259d7 63
Kojto 101:7cff1c4259d7 64 #define PWM_IER_IE0_Disable ~PWM_IER_IE0_Enable
Kojto 101:7cff1c4259d7 65 #define PWM_IER_IE1_Disable ~PWM_IER_IE1_Enable
Kojto 101:7cff1c4259d7 66 #define PWM_IER_IE2_Disable ~PWM_IER_IE2_Enable
Kojto 101:7cff1c4259d7 67 #define PWM_IER_IE3_Disable ~PWM_IER_IE3_Enable
Kojto 101:7cff1c4259d7 68 #define PWM_IER_IE4_Disable ~PWM_IER_IE4_Enable
Kojto 101:7cff1c4259d7 69 #define PWM_IER_IE5_Disable ~PWM_IER_IE5_Enable
Kojto 101:7cff1c4259d7 70 #define PWM_IER_IE6_Disable ~PWM_IER_IE6_Enable
Kojto 101:7cff1c4259d7 71 #define PWM_IER_IE7_Disable ~PWM_IER_IE7_Enable
Kojto 101:7cff1c4259d7 72
Kojto 101:7cff1c4259d7 73 #define PWM_SSR_SS0_Start (0x1ul << 0)
Kojto 101:7cff1c4259d7 74 #define PWM_SSR_SS1_Start (0x1ul << 1)
Kojto 101:7cff1c4259d7 75 #define PWM_SSR_SS2_Start (0x1ul << 2)
Kojto 101:7cff1c4259d7 76 #define PWM_SSR_SS3_Start (0x1ul << 3)
Kojto 101:7cff1c4259d7 77 #define PWM_SSR_SS4_Start (0x1ul << 4)
Kojto 101:7cff1c4259d7 78 #define PWM_SSR_SS5_Start (0x1ul << 5)
Kojto 101:7cff1c4259d7 79 #define PWM_SSR_SS6_Start (0x1ul << 6)
Kojto 101:7cff1c4259d7 80 #define PWM_SSR_SS7_Start (0x1ul << 7)
Kojto 101:7cff1c4259d7 81
Kojto 101:7cff1c4259d7 82 #define PWM_SSR_SS0_Stop ~PWM_SSR_SS0_Start
Kojto 101:7cff1c4259d7 83 #define PWM_SSR_SS1_Stop ~PWM_SSR_SS1_Start
Kojto 101:7cff1c4259d7 84 #define PWM_SSR_SS2_Stop ~PWM_SSR_SS2_Start
Kojto 101:7cff1c4259d7 85 #define PWM_SSR_SS3_Stop ~PWM_SSR_SS3_Start
Kojto 101:7cff1c4259d7 86 #define PWM_SSR_SS4_Stop ~PWM_SSR_SS4_Start
Kojto 101:7cff1c4259d7 87 #define PWM_SSR_SS5_Stop ~PWM_SSR_SS5_Start
Kojto 101:7cff1c4259d7 88 #define PWM_SSR_SS6_Stop ~PWM_SSR_SS6_Start
Kojto 101:7cff1c4259d7 89 #define PWM_SSR_SS7_Stop ~PWM_SSR_SS7_Start
Kojto 101:7cff1c4259d7 90
Kojto 101:7cff1c4259d7 91 #define IS_SSR_BIT_FLAG(FLAG) (FLAG <= 0xFF)
Kojto 101:7cff1c4259d7 92
Kojto 101:7cff1c4259d7 93 #define PWM_PSR_PS0_Pause (0x1ul << 0)
Kojto 101:7cff1c4259d7 94 #define PWM_PSR_PS1_Pause (0x1ul << 1)
Kojto 101:7cff1c4259d7 95 #define PWM_PSR_PS2_Pause (0x1ul << 2)
Kojto 101:7cff1c4259d7 96 #define PWM_PSR_PS3_Pause (0x1ul << 3)
Kojto 101:7cff1c4259d7 97 #define PWM_PSR_PS4_Pause (0x1ul << 4)
Kojto 101:7cff1c4259d7 98 #define PWM_PSR_PS5_Pause (0x1ul << 5)
Kojto 101:7cff1c4259d7 99 #define PWM_PSR_PS6_Pause (0x1ul << 6)
Kojto 101:7cff1c4259d7 100 #define PWM_PSR_PS7_Pause (0x1ul << 7)
Kojto 101:7cff1c4259d7 101
Kojto 101:7cff1c4259d7 102 #define PWM_PSR_PS0_Restart ~PWM_PSR_PS0_Pause
Kojto 101:7cff1c4259d7 103 #define PWM_PSR_PS1_Restart ~PWM_PSR_PS1_Pause
Kojto 101:7cff1c4259d7 104 #define PWM_PSR_PS2_Restart ~PWM_PSR_PS2_Pause
Kojto 101:7cff1c4259d7 105 #define PWM_PSR_PS3_Restart ~PWM_PSR_PS3_Pause
Kojto 101:7cff1c4259d7 106 #define PWM_PSR_PS4_Restart ~PWM_PSR_PS4_Pause
Kojto 101:7cff1c4259d7 107 #define PWM_PSR_PS5_Restart ~PWM_PSR_PS5_Pause
Kojto 101:7cff1c4259d7 108 #define PWM_PSR_PS6_Restart ~PWM_PSR_PS6_Pause
Kojto 101:7cff1c4259d7 109 #define PWM_PSR_PS7_Restart ~PWM_PSR_PS7_Pause
Kojto 101:7cff1c4259d7 110
Kojto 101:7cff1c4259d7 111 #define IS_PWM_PSR_BIT_FLAG(FLAG) (FLAG <= 0xFF)
Kojto 101:7cff1c4259d7 112
Kojto 101:7cff1c4259d7 113 #define PWM_CHn_IER_MIE (0x1ul << 0) ///< Match Interrupt Enable
Kojto 101:7cff1c4259d7 114 #define PWM_CHn_IER_OIE (0x1ul << 1) ///< Overflow Interrupt Enable
Kojto 101:7cff1c4259d7 115 #define PWM_CHn_IER_CIE (0x1ul << 2) ///< Capture Interrupt Enable
Kojto 101:7cff1c4259d7 116 #define IS_PWM_CHn_IER(FLAG) (FLAG <= 0x7)
Kojto 101:7cff1c4259d7 117
Kojto 101:7cff1c4259d7 118 #define PWM_CHn_IER_MI_Msk (0x1ul << 0) ///< Match Interrupt Enable Mask
Kojto 101:7cff1c4259d7 119 #define PWM_CHn_IER_OI_Msk (0x1ul << 1) ///< Overflow Interrupt Enable Mask
Kojto 101:7cff1c4259d7 120 #define PWM_CHn_IER_CI_Msk (0x1ul << 2) ///< Capture Interrupt Enable Mask
Kojto 101:7cff1c4259d7 121
Kojto 101:7cff1c4259d7 122 #define PWM_CHn_ICR_MatchInterruptClear (0x1ul << 0)
Kojto 101:7cff1c4259d7 123 #define PWM_CHn_ICR_OverflowInterruptClear (0x1ul << 1)
Kojto 101:7cff1c4259d7 124 #define PWM_CHn_ICR_CaptureInterruptClear (0x1ul << 2)
Kojto 101:7cff1c4259d7 125 #define IS_PWM_CHn_IntClearFlag(FLAG) FLAG <= 0x7
Kojto 101:7cff1c4259d7 126
Kojto 101:7cff1c4259d7 127 /*
Kojto 101:7cff1c4259d7 128 #define IS_PWM_STOP(CHn) (((CHn == PWM_CH0) && (PWM->SSR & PWM_SSR_SS0)) || \
Kojto 101:7cff1c4259d7 129 ((CHn == PWM_CH1) && (PWM->SSR & PWM_SSR_SS1)) || \
Kojto 101:7cff1c4259d7 130 ((CHn == PWM_CH2) && (PWM->SSR & PWM_SSR_SS2)) || \
Kojto 101:7cff1c4259d7 131 ((CHn == PWM_CH3) && (PWM->SSR & PWM_SSR_SS3)) || \
Kojto 101:7cff1c4259d7 132 ((CHn == PWM_CH4) && (PWM->SSR & PWM_SSR_SS4)) || \
Kojto 101:7cff1c4259d7 133 ((CHn == PWM_CH5) && (PWM->SSR & PWM_SSR_SS5)) || \
Kojto 101:7cff1c4259d7 134 ((CHn == PWM_CH6) && (PWM->SSR & PWM_SSR_SS6)) || \
Kojto 101:7cff1c4259d7 135 ((CHn == PWM_CH7) && (PWM->SSR & PWM_SSR_SS7)))
Kojto 101:7cff1c4259d7 136 */
Kojto 101:7cff1c4259d7 137
Kojto 101:7cff1c4259d7 138
Kojto 101:7cff1c4259d7 139 #define IS_PWM_PR_FILTER(MAXVAL) (MAXVAL <= 0x1F)
Kojto 101:7cff1c4259d7 140
Kojto 101:7cff1c4259d7 141
Kojto 101:7cff1c4259d7 142 #define PWM_CHn_UDMR_UpCount (0x0ul)
Kojto 101:7cff1c4259d7 143 #define PWM_CHn_UDMR_DownCount (0x1ul)
Kojto 101:7cff1c4259d7 144 #define IS_PWM_CHn_UDMR(MODE) ((MODE == PWM_CHn_UDMR_UpCount) || \
Kojto 101:7cff1c4259d7 145 (MODE == PWM_CHn_UDMR_DownCount))
Kojto 101:7cff1c4259d7 146
Kojto 101:7cff1c4259d7 147 #define PWM_CHn_TCMR_TimerMode (0x0ul)
Kojto 101:7cff1c4259d7 148 #define PWM_CHn_TCMR_RisingCounterMode (0x1ul)
Kojto 101:7cff1c4259d7 149 #define PWM_CHn_TCMR_FallingCounterMode (0x2ul)
Kojto 101:7cff1c4259d7 150 #define PWM_CHn_TCMR_BothCounterMode (0x3ul)
Kojto 101:7cff1c4259d7 151 #define IS_PWM_CHn_TCMR(MODE) ((MODE == PWM_CHn_TCMR_RisingCounterMode) || \
Kojto 101:7cff1c4259d7 152 (MODE == PWM_CHn_TCMR_FallingCounterMode) || \
Kojto 101:7cff1c4259d7 153 (MODE == PWM_CHn_TCMR_BothCounterMode))
Kojto 101:7cff1c4259d7 154
Kojto 101:7cff1c4259d7 155 #define PWM_CHn_PEEER_Disable (0x0ul)
Kojto 101:7cff1c4259d7 156 #define PWM_CHn_PEEER_ExtEnable (0x1ul)
Kojto 101:7cff1c4259d7 157 #define PWM_CHn_PEEER_PWMEnable (0x2ul)
Kojto 101:7cff1c4259d7 158 #define IS_PWM_CHn_PEEER(ENABLE) ((ENABLE == PWM_CHn_PEEER_Disable) || \
Kojto 101:7cff1c4259d7 159 (ENABLE == PWM_CHn_PEEER_ExtEnable) || \
Kojto 101:7cff1c4259d7 160 (ENABLE == PWM_CHn_PEEER_PWMEnable))
Kojto 101:7cff1c4259d7 161
Kojto 101:7cff1c4259d7 162 #define IS_PWM_Output(ENABLE) ((ENABLE == PWM_CHn_PEEER_Disable) || \
Kojto 101:7cff1c4259d7 163 (ENABLE == PWM_CHn_PEEER_PWMEnable))
Kojto 101:7cff1c4259d7 164
Kojto 101:7cff1c4259d7 165 #define PWM_CHn_CMR_RisingEdge 0x0ul
Kojto 101:7cff1c4259d7 166 #define PWM_CHn_CMR_FallingEdge 0x1ul
Kojto 101:7cff1c4259d7 167 #define IS_PWM_CHn_CMR(MODE) ((MODE == PWM_CHn_CMR_RisingEdge) || \
Kojto 101:7cff1c4259d7 168 (MODE == PWM_CHn_CMR_FallingEdge))
Kojto 101:7cff1c4259d7 169
Kojto 101:7cff1c4259d7 170 #define PWM_CHn_PDMR_Oneshot (0x0ul)
Kojto 101:7cff1c4259d7 171 #define PWM_CHn_PDMR_Periodic (0x1ul)
Kojto 101:7cff1c4259d7 172 #define IS_PWM_CHn_PDMR(MODE) ((MODE == PWM_CHn_PDMR_Periodic) || \
Kojto 101:7cff1c4259d7 173 (MODE == PWM_CHn_PDMR_Oneshot))
Kojto 101:7cff1c4259d7 174
Kojto 101:7cff1c4259d7 175 #define PWM_CHn_DZER_Enable (0x1ul)
Kojto 101:7cff1c4259d7 176 #define PWM_CHn_DZER_Disable (0x0ul)
Kojto 101:7cff1c4259d7 177 #define PWM_CHn_DZER(ENABLE) ((ENABLE == PWM_CHn_DZER_Enable) || \
Kojto 101:7cff1c4259d7 178 (ENABLE == PWM_CHn_DZER_Disable))
Kojto 101:7cff1c4259d7 179
Kojto 101:7cff1c4259d7 180 #define IS_PWM_Deadznoe(CHn) (((CHn == PWM_CH0) && (PWM_CH1->DZER == PWM_CHn_DZER_Disable)) || \
Kojto 101:7cff1c4259d7 181 ((CHn == PWM_CH1) && (PWM_CH0->DZER == PWM_CHn_DZER_Disable)) || \
Kojto 101:7cff1c4259d7 182 ((CHn == PWM_CH2) && (PWM_CH3->DZER == PWM_CHn_DZER_Disable)) || \
Kojto 101:7cff1c4259d7 183 ((CHn == PWM_CH3) && (PWM_CH2->DZER == PWM_CHn_DZER_Disable)) || \
Kojto 101:7cff1c4259d7 184 ((CHn == PWM_CH4) && (PWM_CH5->DZER == PWM_CHn_DZER_Disable)) || \
Kojto 101:7cff1c4259d7 185 ((CHn == PWM_CH5) && (PWM_CH4->DZER == PWM_CHn_DZER_Disable)) || \
Kojto 101:7cff1c4259d7 186 ((CHn == PWM_CH6) && (PWM_CH7->DZER == PWM_CHn_DZER_Disable)) || \
Kojto 101:7cff1c4259d7 187 ((CHn == PWM_CH7) && (PWM_CH6->DZER == PWM_CHn_DZER_Disable)))
Kojto 101:7cff1c4259d7 188
Kojto 101:7cff1c4259d7 189 #define IS_PWM_CHn_DZCR_FILTER(MAXVAL) (MAXVAL <= 0x3FF)
Kojto 101:7cff1c4259d7 190
Kojto 101:7cff1c4259d7 191
Kojto 101:7cff1c4259d7 192
Kojto 101:7cff1c4259d7 193
Kojto 101:7cff1c4259d7 194
Kojto 101:7cff1c4259d7 195
Kojto 101:7cff1c4259d7 196 void PWM_DeInit(PWM_CHn_TypeDef* PWM_CHn);
Kojto 101:7cff1c4259d7 197 void PWM_TimerModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_TimerModeInitTypeDef* PWM_TimerModeInitStruct);
Kojto 101:7cff1c4259d7 198 void PWM_CaptureModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_CaptureModeInitTypeDef* PWM_CaptureModeInitStruct);
Kojto 101:7cff1c4259d7 199 void PWM_CounterModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_CounterModeInitTypeDef* PWM_CounterModeInitStruct);
Kojto 101:7cff1c4259d7 200 void PWM_DeadzoneModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_DeadzoneModeInitTypDef* PWM_DeadzoneModeInitStruct);
Kojto 101:7cff1c4259d7 201 void PWM_CtrlPWMOutput(PWM_CHn_TypeDef* PWM_CHn, uint32_t outputEnDisable );
Kojto 101:7cff1c4259d7 202 void PWM_CtrlPWMOutputEnable(PWM_CHn_TypeDef* PWM_CHn) ;
Kojto 101:7cff1c4259d7 203 void PWM_CtrlPWMOutputDisable(PWM_CHn_TypeDef* PWM_CHn) ;
Kojto 101:7cff1c4259d7 204 void PWM_IntConfig(PWM_CHn_TypeDef* PWM_CHn, FunctionalState state);
Kojto 101:7cff1c4259d7 205 FlagStatus PWM_GetIntEnableStatus(PWM_CHn_TypeDef* PWM_CHn);
Kojto 101:7cff1c4259d7 206 void PWM_CHn_IntConfig(PWM_CHn_TypeDef* PWM_CHn, uint32_t PWM_CHn_IER, FunctionalState state);
Kojto 101:7cff1c4259d7 207 void PWM_CHn_Start(PWM_CHn_TypeDef* PWM_CHn);
Kojto 101:7cff1c4259d7 208 void PWM_Multi_Start(uint32_t ssr_bit_flag);
Kojto 101:7cff1c4259d7 209 void PWM_CHn_Stop(PWM_CHn_TypeDef* PWM_CHn);
Kojto 101:7cff1c4259d7 210 void PWM_Multi_Stop(uint32_t ssr_bit_flag);
Kojto 101:7cff1c4259d7 211 void PWM_CHn_Pause(PWM_CHn_TypeDef* PWM_CHn);
Kojto 101:7cff1c4259d7 212 void PWM_Multi_Pause(uint32_t psr_bit_flag);
Kojto 101:7cff1c4259d7 213 void PWM_CHn_Restart(PWM_CHn_TypeDef* PWM_CHn);
Kojto 101:7cff1c4259d7 214 void PWM_Multi_Restart(uint32_t psr_bit_flag);
Kojto 101:7cff1c4259d7 215 uint32_t PWM_CHn_GetIntEnableStatus(PWM_CHn_TypeDef* PWM_CHn);
Kojto 101:7cff1c4259d7 216 uint32_t PWM_CHn_GetIntFlagStatus(PWM_CHn_TypeDef* PWM_CHn);
Kojto 101:7cff1c4259d7 217 void PWM_CHn_ClearInt(PWM_CHn_TypeDef* PWM_CHn, uint32_t PWM_CHn_ICR);
Kojto 101:7cff1c4259d7 218 uint32_t PWM_CHn_GetTCR(PWM_CHn_TypeDef* PWM_CHn);
Kojto 101:7cff1c4259d7 219 uint32_t PWM_CHn_GetPCR(PWM_CHn_TypeDef* PWM_CHn);
Kojto 101:7cff1c4259d7 220 uint32_t PWM_CHn_GetPR(PWM_CHn_TypeDef* PWM_CHn);
Kojto 101:7cff1c4259d7 221 void PWM_CHn_SetPR(PWM_CHn_TypeDef* PWM_CHn, uint32_t PR);
Kojto 101:7cff1c4259d7 222 uint32_t PWM_CHn_GetMR(PWM_CHn_TypeDef* PWM_CHn);
Kojto 101:7cff1c4259d7 223 void PWM_CHn_SetMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t MR);
Kojto 101:7cff1c4259d7 224 uint32_t PWM_CHn_GetLR(PWM_CHn_TypeDef* PWM_CHn);
Kojto 101:7cff1c4259d7 225 void PWM_CHn_SetLR(PWM_CHn_TypeDef* PWM_CHn, uint32_t LR);
Kojto 101:7cff1c4259d7 226 uint32_t PWM_CHn_GetUDMR(PWM_CHn_TypeDef* PWM_CHn);
Kojto 101:7cff1c4259d7 227 void PWM_CHn_SetUDMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t UDMR);
Kojto 101:7cff1c4259d7 228 uint32_t PWM_CHn_GetTCMR(PWM_CHn_TypeDef* PWM_CHn);
Kojto 101:7cff1c4259d7 229 void PWM_CHn_SetTCMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t TCMR);
Kojto 101:7cff1c4259d7 230 uint32_t PWM_CHn_GetPEEER(PWM_CHn_TypeDef* PWM_CHn);
Kojto 101:7cff1c4259d7 231 void PWM_CHn_SetPEEER(PWM_CHn_TypeDef* PWM_CHn, uint32_t PEEER);
Kojto 101:7cff1c4259d7 232 uint32_t PWM_CHn_GetCMR(PWM_CHn_TypeDef* PWM_CHn);
Kojto 101:7cff1c4259d7 233 void PWM_CHn_SetCMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t CMR);
Kojto 101:7cff1c4259d7 234 uint32_t PWM_CHn_GetCR(PWM_CHn_TypeDef* PWM_CHn);
Kojto 101:7cff1c4259d7 235 uint32_t PWM_CHn_GetPDMR(PWM_CHn_TypeDef* PWM_CHn);
Kojto 101:7cff1c4259d7 236 void PWM_CHn_SetPDMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t PDMR);
Kojto 101:7cff1c4259d7 237 void PWM_CHn_SetDZER(PWM_CHn_TypeDef* PWM_CHn, uint32_t DZER);
Kojto 101:7cff1c4259d7 238 uint32_t PWM_CHn_GetDZCR(PWM_CHn_TypeDef* PWM_CHn);
Kojto 101:7cff1c4259d7 239 void PWM_CHn_SetDZCR(PWM_CHn_TypeDef* PWM_CHn, uint32_t DZCR);
Kojto 101:7cff1c4259d7 240 void PWM_CH0_ClearMatchInt(void);
Kojto 101:7cff1c4259d7 241 void PWM_CH0_ClearOverflowInt(void);
Kojto 101:7cff1c4259d7 242 void PWM_CH0_ClearCaptureInt(void);
Kojto 101:7cff1c4259d7 243 void PWM_CH1_ClearMatchInt(void);
Kojto 101:7cff1c4259d7 244 void PWM_CH1_ClearOverflowInt(void);
Kojto 101:7cff1c4259d7 245 void PWM_CH1_ClearCaptureInt(void);
Kojto 101:7cff1c4259d7 246 void PWM_CH2_ClearMatchInt(void);
Kojto 101:7cff1c4259d7 247 void PWM_CH2_ClearOverflowInt(void);
Kojto 101:7cff1c4259d7 248 void PWM_CH2_ClearCaptureInt(void);
Kojto 101:7cff1c4259d7 249 void PWM_CH3_ClearMatchInt(void);
Kojto 101:7cff1c4259d7 250 void PWM_CH3_ClearOverflowInt(void);
Kojto 101:7cff1c4259d7 251 void PWM_CH3_ClearCaptureInt(void);
Kojto 101:7cff1c4259d7 252 void PWM_CH4_ClearMatchInt(void);
Kojto 101:7cff1c4259d7 253 void PWM_CH4_ClearOverflowInt(void);
Kojto 101:7cff1c4259d7 254 void PWM_CH4_ClearCaptureInt(void);
Kojto 101:7cff1c4259d7 255 void PWM_CH5_ClearMatchInt(void);
Kojto 101:7cff1c4259d7 256 void PWM_CH5_ClearOverflowInt(void);
Kojto 101:7cff1c4259d7 257 void PWM_CH5_ClearCaptureInt(void);
Kojto 101:7cff1c4259d7 258 void PWM_CH6_ClearMatchInt(void);
Kojto 101:7cff1c4259d7 259 void PWM_CH6_ClearOverflowInt(void);
Kojto 101:7cff1c4259d7 260 void PWM_CH6_ClearCaptureInt(void);
Kojto 101:7cff1c4259d7 261 void PWM_CH7_ClearMatchInt(void);
Kojto 101:7cff1c4259d7 262 void PWM_CH7_ClearOverflowInt(void);
Kojto 101:7cff1c4259d7 263 void PWM_CH7_ClearCaptureInt(void);
Kojto 101:7cff1c4259d7 264
Kojto 101:7cff1c4259d7 265
Kojto 101:7cff1c4259d7 266 void PWM0_Handler(void);
Kojto 101:7cff1c4259d7 267 void PWM1_Handler(void);
Kojto 101:7cff1c4259d7 268 void PWM2_Handler(void);
Kojto 101:7cff1c4259d7 269 void PWM3_Handler(void);
Kojto 101:7cff1c4259d7 270 void PWM4_Handler(void);
Kojto 101:7cff1c4259d7 271 void PWM5_Handler(void);
Kojto 101:7cff1c4259d7 272 void PWM6_Handler(void);
Kojto 101:7cff1c4259d7 273 void PWM7_Handler(void);
Kojto 101:7cff1c4259d7 274
Kojto 101:7cff1c4259d7 275
Kojto 101:7cff1c4259d7 276
Kojto 101:7cff1c4259d7 277
Kojto 101:7cff1c4259d7 278 //Temporary macro=======
Kojto 101:7cff1c4259d7 279 #define PWM_CH(N) ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + (N * 0x100UL)))
Kojto 101:7cff1c4259d7 280 //======================
Kojto 101:7cff1c4259d7 281
Kojto 101:7cff1c4259d7 282
Kojto 101:7cff1c4259d7 283 #ifdef __cplusplus
Kojto 101:7cff1c4259d7 284 }
Kojto 101:7cff1c4259d7 285 #endif
Kojto 101:7cff1c4259d7 286
Kojto 101:7cff1c4259d7 287
Kojto 101:7cff1c4259d7 288 #endif //__W7500X_PWM_H
Kojto 101:7cff1c4259d7 289