mbed official / mbed

Important changes to repositories hosted on mbed.com

Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.

To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.

It is also possible to export all your personal repositories from the account settings page.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

TARGET_RAPIDIOT_KW41Z/TOOLCHAIN_ARM_STD/fsl_clock.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 172:65be27845400 1 /*
AnnaBridge 172:65be27845400 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
AnnaBridge 172:65be27845400 3 * All rights reserved.
AnnaBridge 172:65be27845400 4 *
AnnaBridge 172:65be27845400 5 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 172:65be27845400 6 * are permitted provided that the following conditions are met:
AnnaBridge 172:65be27845400 7 *
AnnaBridge 172:65be27845400 8 * o Redistributions of source code must retain the above copyright notice, this list
AnnaBridge 172:65be27845400 9 * of conditions and the following disclaimer.
AnnaBridge 172:65be27845400 10 *
AnnaBridge 172:65be27845400 11 * o Redistributions in binary form must reproduce the above copyright notice, this
AnnaBridge 172:65be27845400 12 * list of conditions and the following disclaimer in the documentation and/or
AnnaBridge 172:65be27845400 13 * other materials provided with the distribution.
AnnaBridge 172:65be27845400 14 *
AnnaBridge 172:65be27845400 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
AnnaBridge 172:65be27845400 16 * contributors may be used to endorse or promote products derived from this
AnnaBridge 172:65be27845400 17 * software without specific prior written permission.
AnnaBridge 172:65be27845400 18 *
AnnaBridge 172:65be27845400 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
AnnaBridge 172:65be27845400 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
AnnaBridge 172:65be27845400 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 172:65be27845400 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
AnnaBridge 172:65be27845400 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
AnnaBridge 172:65be27845400 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
AnnaBridge 172:65be27845400 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
AnnaBridge 172:65be27845400 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
AnnaBridge 172:65be27845400 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
AnnaBridge 172:65be27845400 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 172:65be27845400 29 */
AnnaBridge 172:65be27845400 30
AnnaBridge 172:65be27845400 31 #ifndef _FSL_CLOCK_H_
AnnaBridge 172:65be27845400 32 #define _FSL_CLOCK_H_
AnnaBridge 172:65be27845400 33
AnnaBridge 172:65be27845400 34 #include "fsl_common.h"
AnnaBridge 172:65be27845400 35
AnnaBridge 172:65be27845400 36 /*! @addtogroup clock */
AnnaBridge 172:65be27845400 37 /*! @{ */
AnnaBridge 172:65be27845400 38
AnnaBridge 172:65be27845400 39 /*! @file */
AnnaBridge 172:65be27845400 40
AnnaBridge 172:65be27845400 41 /*******************************************************************************
AnnaBridge 172:65be27845400 42 * Definitions
AnnaBridge 172:65be27845400 43 ******************************************************************************/
AnnaBridge 172:65be27845400 44
AnnaBridge 172:65be27845400 45 /*! @name Driver version */
AnnaBridge 172:65be27845400 46 /*@{*/
AnnaBridge 172:65be27845400 47 /*! @brief CLOCK driver version 2.2.0. */
AnnaBridge 172:65be27845400 48 #define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 2, 0))
AnnaBridge 172:65be27845400 49 /*@}*/
AnnaBridge 172:65be27845400 50
AnnaBridge 172:65be27845400 51 /*! @brief External XTAL0 (OSC0) clock frequency.
AnnaBridge 172:65be27845400 52 *
AnnaBridge 172:65be27845400 53 * The XTAL0/EXTAL0 (OSC0) clock frequency in Hz. When the clock is set up, use the
AnnaBridge 172:65be27845400 54 * function CLOCK_SetXtal0Freq to set the value in the clock driver. For example,
AnnaBridge 172:65be27845400 55 * if XTAL0 is 8 MHz:
AnnaBridge 172:65be27845400 56 * @code
AnnaBridge 172:65be27845400 57 * CLOCK_InitOsc0(...); // Set up the OSC0
AnnaBridge 172:65be27845400 58 * CLOCK_SetXtal0Freq(80000000); // Set the XTAL0 value to the clock driver.
AnnaBridge 172:65be27845400 59 * @endcode
AnnaBridge 172:65be27845400 60 *
AnnaBridge 172:65be27845400 61 * This is important for the multicore platforms where only one core needs to set up the
AnnaBridge 172:65be27845400 62 * OSC0 using the CLOCK_InitOsc0. All other cores need to call the CLOCK_SetXtal0Freq
AnnaBridge 172:65be27845400 63 * to get a valid clock frequency.
AnnaBridge 172:65be27845400 64 */
AnnaBridge 172:65be27845400 65 extern uint32_t g_xtal0Freq;
AnnaBridge 172:65be27845400 66
AnnaBridge 172:65be27845400 67 /*! @brief External XTAL32/EXTAL32/RTC_CLKIN clock frequency.
AnnaBridge 172:65be27845400 68 *
AnnaBridge 172:65be27845400 69 * The XTAL32/EXTAL32/RTC_CLKIN clock frequency in Hz. When the clock is set up, use the
AnnaBridge 172:65be27845400 70 * function CLOCK_SetXtal32Freq to set the value in the clock driver.
AnnaBridge 172:65be27845400 71 *
AnnaBridge 172:65be27845400 72 * This is important for the multicore platforms where only one core needs to set up
AnnaBridge 172:65be27845400 73 * the clock. All other cores need to call the CLOCK_SetXtal32Freq
AnnaBridge 172:65be27845400 74 * to get a valid clock frequency.
AnnaBridge 172:65be27845400 75 */
AnnaBridge 172:65be27845400 76 extern uint32_t g_xtal32Freq;
AnnaBridge 172:65be27845400 77
AnnaBridge 172:65be27845400 78 #if (defined(OSC) && !(defined(OSC0)))
AnnaBridge 172:65be27845400 79 #define OSC0 OSC
AnnaBridge 172:65be27845400 80 #endif
AnnaBridge 172:65be27845400 81
AnnaBridge 172:65be27845400 82 /*! @brief Clock ip name array for DMAMUX. */
AnnaBridge 172:65be27845400 83 #define DMAMUX_CLOCKS \
AnnaBridge 172:65be27845400 84 { \
AnnaBridge 172:65be27845400 85 kCLOCK_Dmamux0 \
AnnaBridge 172:65be27845400 86 }
AnnaBridge 172:65be27845400 87
AnnaBridge 172:65be27845400 88 /*! @brief Clock ip name array for RTC. */
AnnaBridge 172:65be27845400 89 #define RTC_CLOCKS \
AnnaBridge 172:65be27845400 90 { \
AnnaBridge 172:65be27845400 91 kCLOCK_Rtc0 \
AnnaBridge 172:65be27845400 92 }
AnnaBridge 172:65be27845400 93
AnnaBridge 172:65be27845400 94 /*! @brief Clock ip name array for PIT. */
AnnaBridge 172:65be27845400 95 #define PIT_CLOCKS \
AnnaBridge 172:65be27845400 96 { \
AnnaBridge 172:65be27845400 97 kCLOCK_Pit0 \
AnnaBridge 172:65be27845400 98 }
AnnaBridge 172:65be27845400 99
AnnaBridge 172:65be27845400 100 /*! @brief Clock ip name array for PORT. */
AnnaBridge 172:65be27845400 101 #define PORT_CLOCKS \
AnnaBridge 172:65be27845400 102 { \
AnnaBridge 172:65be27845400 103 kCLOCK_PortA, kCLOCK_PortB, kCLOCK_PortC \
AnnaBridge 172:65be27845400 104 }
AnnaBridge 172:65be27845400 105
AnnaBridge 172:65be27845400 106 /*! @brief Clock ip name array for TSI. */
AnnaBridge 172:65be27845400 107 #define TSI_CLOCKS \
AnnaBridge 172:65be27845400 108 { \
AnnaBridge 172:65be27845400 109 kCLOCK_Tsi0 \
AnnaBridge 172:65be27845400 110 }
AnnaBridge 172:65be27845400 111
AnnaBridge 172:65be27845400 112 /*! @brief Clock ip name array for DSPI. */
AnnaBridge 172:65be27845400 113 #define DSPI_CLOCKS \
AnnaBridge 172:65be27845400 114 { \
AnnaBridge 172:65be27845400 115 kCLOCK_Spi0, kCLOCK_Spi1 \
AnnaBridge 172:65be27845400 116 }
AnnaBridge 172:65be27845400 117
AnnaBridge 172:65be27845400 118 /*! @brief Clock ip name array for LPUART. */
AnnaBridge 172:65be27845400 119 #define LPUART_CLOCKS \
AnnaBridge 172:65be27845400 120 { \
AnnaBridge 172:65be27845400 121 kCLOCK_Lpuart0 \
AnnaBridge 172:65be27845400 122 }
AnnaBridge 172:65be27845400 123
AnnaBridge 172:65be27845400 124 /*! @brief Clock ip name array for DAC. */
AnnaBridge 172:65be27845400 125 #define DAC_CLOCKS \
AnnaBridge 172:65be27845400 126 { \
AnnaBridge 172:65be27845400 127 kCLOCK_Dac0 \
AnnaBridge 172:65be27845400 128 }
AnnaBridge 172:65be27845400 129
AnnaBridge 172:65be27845400 130 /*! @brief Clock ip name array for LPTMR. */
AnnaBridge 172:65be27845400 131 #define LPTMR_CLOCKS \
AnnaBridge 172:65be27845400 132 { \
AnnaBridge 172:65be27845400 133 kCLOCK_Lptmr0 \
AnnaBridge 172:65be27845400 134 }
AnnaBridge 172:65be27845400 135
AnnaBridge 172:65be27845400 136 /*! @brief Clock ip name array for ADC16. */
AnnaBridge 172:65be27845400 137 #define ADC16_CLOCKS \
AnnaBridge 172:65be27845400 138 { \
AnnaBridge 172:65be27845400 139 kCLOCK_Adc0 \
AnnaBridge 172:65be27845400 140 }
AnnaBridge 172:65be27845400 141
AnnaBridge 172:65be27845400 142 /*! @brief Clock ip name array for TRNG. */
AnnaBridge 172:65be27845400 143 #define TRNG_CLOCKS \
AnnaBridge 172:65be27845400 144 { \
AnnaBridge 172:65be27845400 145 kCLOCK_Trng0 \
AnnaBridge 172:65be27845400 146 }
AnnaBridge 172:65be27845400 147
AnnaBridge 172:65be27845400 148 /*! @brief Clock ip name array for DMA. */
AnnaBridge 172:65be27845400 149 #define EDMA_CLOCKS \
AnnaBridge 172:65be27845400 150 { \
AnnaBridge 172:65be27845400 151 kCLOCK_Dma0 \
AnnaBridge 172:65be27845400 152 }
AnnaBridge 172:65be27845400 153
AnnaBridge 172:65be27845400 154 /*! @brief Clock ip name array for CMT. */
AnnaBridge 172:65be27845400 155 #define CMT_CLOCKS \
AnnaBridge 172:65be27845400 156 { \
AnnaBridge 172:65be27845400 157 kCLOCK_Cmt0 \
AnnaBridge 172:65be27845400 158 }
AnnaBridge 172:65be27845400 159
AnnaBridge 172:65be27845400 160 /*! @brief Clock ip name array for TPM. */
AnnaBridge 172:65be27845400 161 #define TPM_CLOCKS \
AnnaBridge 172:65be27845400 162 { \
AnnaBridge 172:65be27845400 163 kCLOCK_Tpm0, kCLOCK_Tpm1, kCLOCK_Tpm2 \
AnnaBridge 172:65be27845400 164 }
AnnaBridge 172:65be27845400 165
AnnaBridge 172:65be27845400 166 /*! @brief Clock ip name array for LTC. */
AnnaBridge 172:65be27845400 167 #define LTC_CLOCKS \
AnnaBridge 172:65be27845400 168 { \
AnnaBridge 172:65be27845400 169 kCLOCK_Ltc0 \
AnnaBridge 172:65be27845400 170 }
AnnaBridge 172:65be27845400 171
AnnaBridge 172:65be27845400 172 /*! @brief Clock ip name array for I2C. */
AnnaBridge 172:65be27845400 173 #define I2C_CLOCKS \
AnnaBridge 172:65be27845400 174 { \
AnnaBridge 172:65be27845400 175 kCLOCK_I2c0, kCLOCK_I2c1 \
AnnaBridge 172:65be27845400 176 }
AnnaBridge 172:65be27845400 177
AnnaBridge 172:65be27845400 178 /*! @brief Clock ip name array for CMP. */
AnnaBridge 172:65be27845400 179 #define CMP_CLOCKS \
AnnaBridge 172:65be27845400 180 { \
AnnaBridge 172:65be27845400 181 kCLOCK_Cmp0 \
AnnaBridge 172:65be27845400 182 }
AnnaBridge 172:65be27845400 183
AnnaBridge 172:65be27845400 184 /*! @brief Clock ip name array for VREF. */
AnnaBridge 172:65be27845400 185 #define VREF_CLOCKS \
AnnaBridge 172:65be27845400 186 { \
AnnaBridge 172:65be27845400 187 kCLOCK_Vref0 \
AnnaBridge 172:65be27845400 188 }
AnnaBridge 172:65be27845400 189
AnnaBridge 172:65be27845400 190 /*! @brief Clock ip name array for DCDC. */
AnnaBridge 172:65be27845400 191 #define DCDC_CLOCKS \
AnnaBridge 172:65be27845400 192 { \
AnnaBridge 172:65be27845400 193 kCLOCK_Dcdc0 \
AnnaBridge 172:65be27845400 194 }
AnnaBridge 172:65be27845400 195
AnnaBridge 172:65be27845400 196 /*!
AnnaBridge 172:65be27845400 197 * @brief LPO clock frequency.
AnnaBridge 172:65be27845400 198 */
AnnaBridge 172:65be27845400 199 #define LPO_CLK_FREQ 1000U
AnnaBridge 172:65be27845400 200
AnnaBridge 172:65be27845400 201 /*! @brief Prepherials clock source definition. */
AnnaBridge 172:65be27845400 202 #define SYS_CLK kCLOCK_CoreSysClk
AnnaBridge 172:65be27845400 203 #define BUS_CLK kCLOCK_BusClk
AnnaBridge 172:65be27845400 204
AnnaBridge 172:65be27845400 205 #define I2C0_CLK_SRC BUS_CLK
AnnaBridge 172:65be27845400 206 #define I2C1_CLK_SRC SYS_CLK
AnnaBridge 172:65be27845400 207 #define DSPI0_CLK_SRC BUS_CLK
AnnaBridge 172:65be27845400 208 #define DSPI1_CLK_SRC BUS_CLK
AnnaBridge 172:65be27845400 209
AnnaBridge 172:65be27845400 210 /*! @brief Clock name used to get clock frequency. */
AnnaBridge 172:65be27845400 211 typedef enum _clock_name
AnnaBridge 172:65be27845400 212 {
AnnaBridge 172:65be27845400 213 /* ----------------------------- System layer clock -------------------------------*/
AnnaBridge 172:65be27845400 214 kCLOCK_CoreSysClk, /*!< Core/system clock */
AnnaBridge 172:65be27845400 215 kCLOCK_PlatClk, /*!< Platform clock */
AnnaBridge 172:65be27845400 216 kCLOCK_BusClk, /*!< Bus clock */
AnnaBridge 172:65be27845400 217 kCLOCK_FlashClk, /*!< Flash clock */
AnnaBridge 172:65be27845400 218
AnnaBridge 172:65be27845400 219 /* ---------------------------------- OSC clock -----------------------------------*/
AnnaBridge 172:65be27845400 220 kCLOCK_Er32kClk, /*!< External reference 32K clock (ERCLK32K) */
AnnaBridge 172:65be27845400 221 kCLOCK_Osc0ErClk, /*!< OSC0 external reference clock (OSC0ERCLK) */
AnnaBridge 172:65be27845400 222
AnnaBridge 172:65be27845400 223 /* ----------------------------- MCG and MCG-Lite clock ---------------------------*/
AnnaBridge 172:65be27845400 224 kCLOCK_McgFixedFreqClk, /*!< MCG fixed frequency clock (MCGFFCLK) */
AnnaBridge 172:65be27845400 225 kCLOCK_McgInternalRefClk, /*!< MCG internal reference clock (MCGIRCLK) */
AnnaBridge 172:65be27845400 226 kCLOCK_McgFllClk, /*!< MCGFLLCLK */
AnnaBridge 172:65be27845400 227 kCLOCK_McgPeriphClk, /*!< MCG peripheral clock (MCGPCLK) */
AnnaBridge 172:65be27845400 228
AnnaBridge 172:65be27845400 229 /* --------------------------------- Other clock ----------------------------------*/
AnnaBridge 172:65be27845400 230 kCLOCK_LpoClk, /*!< LPO clock */
AnnaBridge 172:65be27845400 231
AnnaBridge 172:65be27845400 232 } clock_name_t;
AnnaBridge 172:65be27845400 233
AnnaBridge 172:65be27845400 234 /*------------------------------------------------------------------------------
AnnaBridge 172:65be27845400 235
AnnaBridge 172:65be27845400 236 clock_gate_t definition:
AnnaBridge 172:65be27845400 237
AnnaBridge 172:65be27845400 238 31 16 0
AnnaBridge 172:65be27845400 239 -----------------------------------------------------------------
AnnaBridge 172:65be27845400 240 | SIM_SCGC register offset | control bit offset in SCGC |
AnnaBridge 172:65be27845400 241 -----------------------------------------------------------------
AnnaBridge 172:65be27845400 242
AnnaBridge 172:65be27845400 243 For example, the SDHC clock gate is controlled by SIM_SCGC3[17], the
AnnaBridge 172:65be27845400 244 SIM_SCGC3 offset in SIM is 0x1030, then kClockGateSdhc0 is defined as
AnnaBridge 172:65be27845400 245
AnnaBridge 172:65be27845400 246 kClockGateSdhc0 = (0x1030 << 16) | 17;
AnnaBridge 172:65be27845400 247
AnnaBridge 172:65be27845400 248 ------------------------------------------------------------------------------*/
AnnaBridge 172:65be27845400 249
AnnaBridge 172:65be27845400 250 #define CLK_GATE_REG_OFFSET_SHIFT 16U
AnnaBridge 172:65be27845400 251 #define CLK_GATE_REG_OFFSET_MASK 0xFFFF0000U
AnnaBridge 172:65be27845400 252 #define CLK_GATE_BIT_SHIFT_SHIFT 0U
AnnaBridge 172:65be27845400 253 #define CLK_GATE_BIT_SHIFT_MASK 0x0000FFFFU
AnnaBridge 172:65be27845400 254
AnnaBridge 172:65be27845400 255 #define CLK_GATE_DEFINE(reg_offset, bit_shift) \
AnnaBridge 172:65be27845400 256 ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \
AnnaBridge 172:65be27845400 257 (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK))
AnnaBridge 172:65be27845400 258
AnnaBridge 172:65be27845400 259 #define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT)
AnnaBridge 172:65be27845400 260 #define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)
AnnaBridge 172:65be27845400 261
AnnaBridge 172:65be27845400 262 /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
AnnaBridge 172:65be27845400 263 typedef enum _clock_ip_name
AnnaBridge 172:65be27845400 264 {
AnnaBridge 172:65be27845400 265 kCLOCK_IpInvalid = 0U,
AnnaBridge 172:65be27845400 266
AnnaBridge 172:65be27845400 267 kCLOCK_Cmt0 = CLK_GATE_DEFINE(0x1034U, 2U),
AnnaBridge 172:65be27845400 268 kCLOCK_I2c0 = CLK_GATE_DEFINE(0x1034U, 6U),
AnnaBridge 172:65be27845400 269 kCLOCK_I2c1 = CLK_GATE_DEFINE(0x1034U, 7U),
AnnaBridge 172:65be27845400 270 kCLOCK_Cmp0 = CLK_GATE_DEFINE(0x1034U, 19U),
AnnaBridge 172:65be27845400 271 kCLOCK_Vref0 = CLK_GATE_DEFINE(0x1034U, 20U),
AnnaBridge 172:65be27845400 272
AnnaBridge 172:65be27845400 273 kCLOCK_Lptmr0 = CLK_GATE_DEFINE(0x1038U, 0U),
AnnaBridge 172:65be27845400 274 kCLOCK_Tsi0 = CLK_GATE_DEFINE(0x1038U, 5U),
AnnaBridge 172:65be27845400 275 kCLOCK_PortA = CLK_GATE_DEFINE(0x1038U, 9U),
AnnaBridge 172:65be27845400 276 kCLOCK_PortB = CLK_GATE_DEFINE(0x1038U, 10U),
AnnaBridge 172:65be27845400 277 kCLOCK_PortC = CLK_GATE_DEFINE(0x1038U, 11U),
AnnaBridge 172:65be27845400 278 kCLOCK_Lpuart0 = CLK_GATE_DEFINE(0x1038U, 20U),
AnnaBridge 172:65be27845400 279 kCLOCK_Aesa = CLK_GATE_DEFINE(0x1038U, 24U),
AnnaBridge 172:65be27845400 280 kCLOCK_Ltc0 = CLK_GATE_DEFINE(0x1038U, 24U),
AnnaBridge 172:65be27845400 281 kCLOCK_Rsim = CLK_GATE_DEFINE(0x1038U, 25U),
AnnaBridge 172:65be27845400 282 kCLOCK_Dcdc0 = CLK_GATE_DEFINE(0x1038U, 26U),
AnnaBridge 172:65be27845400 283 kCLOCK_Btll = CLK_GATE_DEFINE(0x1038U, 27U),
AnnaBridge 172:65be27845400 284 kCLOCK_PhyDig = CLK_GATE_DEFINE(0x1038U, 28U),
AnnaBridge 172:65be27845400 285 kCLOCK_ZigBee = CLK_GATE_DEFINE(0x1038U, 29U),
AnnaBridge 172:65be27845400 286 kCLOCK_GenFsk = CLK_GATE_DEFINE(0x1038U, 31U),
AnnaBridge 172:65be27845400 287
AnnaBridge 172:65be27845400 288 kCLOCK_Ftf0 = CLK_GATE_DEFINE(0x103CU, 0U),
AnnaBridge 172:65be27845400 289 kCLOCK_Dmamux0 = CLK_GATE_DEFINE(0x103CU, 1U),
AnnaBridge 172:65be27845400 290 kCLOCK_Trng0 = CLK_GATE_DEFINE(0x103CU, 9U),
AnnaBridge 172:65be27845400 291 kCLOCK_Spi0 = CLK_GATE_DEFINE(0x103CU, 12U),
AnnaBridge 172:65be27845400 292 kCLOCK_Spi1 = CLK_GATE_DEFINE(0x103CU, 13U),
AnnaBridge 172:65be27845400 293 kCLOCK_Pit0 = CLK_GATE_DEFINE(0x103CU, 23U),
AnnaBridge 172:65be27845400 294 kCLOCK_Tpm0 = CLK_GATE_DEFINE(0x103CU, 24U),
AnnaBridge 172:65be27845400 295 kCLOCK_Tpm1 = CLK_GATE_DEFINE(0x103CU, 25U),
AnnaBridge 172:65be27845400 296 kCLOCK_Tpm2 = CLK_GATE_DEFINE(0x103CU, 26U),
AnnaBridge 172:65be27845400 297 kCLOCK_Adc0 = CLK_GATE_DEFINE(0x103CU, 27U),
AnnaBridge 172:65be27845400 298 kCLOCK_Rtc0 = CLK_GATE_DEFINE(0x103CU, 29U),
AnnaBridge 172:65be27845400 299 kCLOCK_Dac0 = CLK_GATE_DEFINE(0x103CU, 31U),
AnnaBridge 172:65be27845400 300
AnnaBridge 172:65be27845400 301 kCLOCK_Dma0 = CLK_GATE_DEFINE(0x1040U, 8U),
AnnaBridge 172:65be27845400 302 } clock_ip_name_t;
AnnaBridge 172:65be27845400 303
AnnaBridge 172:65be27845400 304 /*!@brief SIM configuration structure for clock setting. */
AnnaBridge 172:65be27845400 305 typedef struct _sim_clock_config
AnnaBridge 172:65be27845400 306 {
AnnaBridge 172:65be27845400 307 uint8_t pllFllSel; /*!< PLL/FLL/IRC48M selection. */
AnnaBridge 172:65be27845400 308 uint8_t pllFllDiv; /*!< PLLFLLSEL clock divider divisor. */
AnnaBridge 172:65be27845400 309 uint8_t pllFllFrac; /*!< PLLFLLSEL clock divider fraction. */
AnnaBridge 172:65be27845400 310 uint8_t er32kSrc; /*!< ERCLK32K source selection. */
AnnaBridge 172:65be27845400 311 uint32_t clkdiv1; /*!< SIM_CLKDIV1. */
AnnaBridge 172:65be27845400 312 } sim_clock_config_t;
AnnaBridge 172:65be27845400 313
AnnaBridge 172:65be27845400 314 /*! @brief OSC work mode. */
AnnaBridge 172:65be27845400 315 typedef enum _osc_mode
AnnaBridge 172:65be27845400 316 {
AnnaBridge 172:65be27845400 317 kOSC_ModeExt = 0U, /*!< Use an external clock. */
AnnaBridge 172:65be27845400 318 #if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK)))
AnnaBridge 172:65be27845400 319 kOSC_ModeOscLowPower = MCG_C2_EREFS_MASK, /*!< Oscillator low power. */
AnnaBridge 172:65be27845400 320 #else
AnnaBridge 172:65be27845400 321 kOSC_ModeOscLowPower = MCG_C2_EREFS0_MASK, /*!< Oscillator low power. */
AnnaBridge 172:65be27845400 322 #endif
AnnaBridge 172:65be27845400 323 kOSC_ModeOscHighGain = 0U
AnnaBridge 172:65be27845400 324 #if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK)))
AnnaBridge 172:65be27845400 325 |
AnnaBridge 172:65be27845400 326 MCG_C2_EREFS_MASK
AnnaBridge 172:65be27845400 327 #else
AnnaBridge 172:65be27845400 328 |
AnnaBridge 172:65be27845400 329 MCG_C2_EREFS0_MASK
AnnaBridge 172:65be27845400 330 #endif
AnnaBridge 172:65be27845400 331 #if (defined(MCG_C2_HGO_MASK) && !(defined(MCG_C2_HGO0_MASK)))
AnnaBridge 172:65be27845400 332 |
AnnaBridge 172:65be27845400 333 MCG_C2_HGO_MASK, /*!< Oscillator high gain. */
AnnaBridge 172:65be27845400 334 #else
AnnaBridge 172:65be27845400 335 |
AnnaBridge 172:65be27845400 336 MCG_C2_HGO0_MASK, /*!< Oscillator high gain. */
AnnaBridge 172:65be27845400 337 #endif
AnnaBridge 172:65be27845400 338 } osc_mode_t;
AnnaBridge 172:65be27845400 339
AnnaBridge 172:65be27845400 340 /*!
AnnaBridge 172:65be27845400 341 * @brief OSC Initialization Configuration Structure
AnnaBridge 172:65be27845400 342 *
AnnaBridge 172:65be27845400 343 * Defines the configuration data structure to initialize the OSC.
AnnaBridge 172:65be27845400 344 * When porting to a new board, set the following members
AnnaBridge 172:65be27845400 345 * according to the board setting:
AnnaBridge 172:65be27845400 346 * 1. freq: The external frequency.
AnnaBridge 172:65be27845400 347 * 2. workMode: The OSC module mode.
AnnaBridge 172:65be27845400 348 */
AnnaBridge 172:65be27845400 349 typedef struct _osc_config
AnnaBridge 172:65be27845400 350 {
AnnaBridge 172:65be27845400 351 uint32_t freq; /*!< External clock frequency. */
AnnaBridge 172:65be27845400 352 osc_mode_t workMode; /*!< OSC work mode setting. */
AnnaBridge 172:65be27845400 353 } osc_config_t;
AnnaBridge 172:65be27845400 354
AnnaBridge 172:65be27845400 355 /*! @brief MCG FLL reference clock source select. */
AnnaBridge 172:65be27845400 356 typedef enum _mcg_fll_src
AnnaBridge 172:65be27845400 357 {
AnnaBridge 172:65be27845400 358 kMCG_FllSrcExternal, /*!< External reference clock is selected */
AnnaBridge 172:65be27845400 359 kMCG_FllSrcInternal /*!< The slow internal reference clock is selected */
AnnaBridge 172:65be27845400 360 } mcg_fll_src_t;
AnnaBridge 172:65be27845400 361
AnnaBridge 172:65be27845400 362 /*! @brief MCG internal reference clock select */
AnnaBridge 172:65be27845400 363 typedef enum _mcg_irc_mode
AnnaBridge 172:65be27845400 364 {
AnnaBridge 172:65be27845400 365 kMCG_IrcSlow, /*!< Slow internal reference clock selected */
AnnaBridge 172:65be27845400 366 kMCG_IrcFast /*!< Fast internal reference clock selected */
AnnaBridge 172:65be27845400 367 } mcg_irc_mode_t;
AnnaBridge 172:65be27845400 368
AnnaBridge 172:65be27845400 369 /*! @brief MCG DCO Maximum Frequency with 32.768 kHz Reference */
AnnaBridge 172:65be27845400 370 typedef enum _mcg_dmx32
AnnaBridge 172:65be27845400 371 {
AnnaBridge 172:65be27845400 372 kMCG_Dmx32Default, /*!< DCO has a default range of 25% */
AnnaBridge 172:65be27845400 373 kMCG_Dmx32Fine /*!< DCO is fine-tuned for maximum frequency with 32.768 kHz reference */
AnnaBridge 172:65be27845400 374 } mcg_dmx32_t;
AnnaBridge 172:65be27845400 375
AnnaBridge 172:65be27845400 376 /*! @brief MCG DCO range select */
AnnaBridge 172:65be27845400 377 typedef enum _mcg_drs
AnnaBridge 172:65be27845400 378 {
AnnaBridge 172:65be27845400 379 kMCG_DrsLow, /*!< Low frequency range */
AnnaBridge 172:65be27845400 380 kMCG_DrsMid, /*!< Mid frequency range */
AnnaBridge 172:65be27845400 381 kMCG_DrsMidHigh, /*!< Mid-High frequency range */
AnnaBridge 172:65be27845400 382 kMCG_DrsHigh /*!< High frequency range */
AnnaBridge 172:65be27845400 383 } mcg_drs_t;
AnnaBridge 172:65be27845400 384
AnnaBridge 172:65be27845400 385 /*! @brief MCG PLL reference clock select */
AnnaBridge 172:65be27845400 386 typedef enum _mcg_pll_ref_src
AnnaBridge 172:65be27845400 387 {
AnnaBridge 172:65be27845400 388 kMCG_PllRefOsc0, /*!< Selects OSC0 as PLL reference clock */
AnnaBridge 172:65be27845400 389 kMCG_PllRefOsc1 /*!< Selects OSC1 as PLL reference clock */
AnnaBridge 172:65be27845400 390 } mcg_pll_ref_src_t;
AnnaBridge 172:65be27845400 391
AnnaBridge 172:65be27845400 392 /*! @brief MCGOUT clock source. */
AnnaBridge 172:65be27845400 393 typedef enum _mcg_clkout_src
AnnaBridge 172:65be27845400 394 {
AnnaBridge 172:65be27845400 395 kMCG_ClkOutSrcOut, /*!< Output of the FLL is selected (reset default) */
AnnaBridge 172:65be27845400 396 kMCG_ClkOutSrcInternal, /*!< Internal reference clock is selected */
AnnaBridge 172:65be27845400 397 kMCG_ClkOutSrcExternal, /*!< External reference clock is selected */
AnnaBridge 172:65be27845400 398 } mcg_clkout_src_t;
AnnaBridge 172:65be27845400 399
AnnaBridge 172:65be27845400 400 /*! @brief MCG Automatic Trim Machine Select */
AnnaBridge 172:65be27845400 401 typedef enum _mcg_atm_select
AnnaBridge 172:65be27845400 402 {
AnnaBridge 172:65be27845400 403 kMCG_AtmSel32k, /*!< 32 kHz Internal Reference Clock selected */
AnnaBridge 172:65be27845400 404 kMCG_AtmSel4m /*!< 4 MHz Internal Reference Clock selected */
AnnaBridge 172:65be27845400 405 } mcg_atm_select_t;
AnnaBridge 172:65be27845400 406
AnnaBridge 172:65be27845400 407 /*! @brief MCG OSC Clock Select */
AnnaBridge 172:65be27845400 408 typedef enum _mcg_oscsel
AnnaBridge 172:65be27845400 409 {
AnnaBridge 172:65be27845400 410 kMCG_OscselOsc, /*!< Selects System Oscillator (OSCCLK) */
AnnaBridge 172:65be27845400 411 kMCG_OscselRtc, /*!< Selects 32 kHz RTC Oscillator */
AnnaBridge 172:65be27845400 412 } mcg_oscsel_t;
AnnaBridge 172:65be27845400 413
AnnaBridge 172:65be27845400 414 /*! @brief MCG PLLCS select */
AnnaBridge 172:65be27845400 415 typedef enum _mcg_pll_clk_select
AnnaBridge 172:65be27845400 416 {
AnnaBridge 172:65be27845400 417 kMCG_PllClkSelPll0, /*!< PLL0 output clock is selected */
AnnaBridge 172:65be27845400 418 kMCG_PllClkSelPll1 /* PLL1 output clock is selected */
AnnaBridge 172:65be27845400 419 } mcg_pll_clk_select_t;
AnnaBridge 172:65be27845400 420
AnnaBridge 172:65be27845400 421 /*! @brief MCG clock monitor mode. */
AnnaBridge 172:65be27845400 422 typedef enum _mcg_monitor_mode
AnnaBridge 172:65be27845400 423 {
AnnaBridge 172:65be27845400 424 kMCG_MonitorNone, /*!< Clock monitor is disabled. */
AnnaBridge 172:65be27845400 425 kMCG_MonitorInt, /*!< Trigger interrupt when clock lost. */
AnnaBridge 172:65be27845400 426 kMCG_MonitorReset /*!< System reset when clock lost. */
AnnaBridge 172:65be27845400 427 } mcg_monitor_mode_t;
AnnaBridge 172:65be27845400 428
AnnaBridge 172:65be27845400 429 /*! @brief MCG status. */
AnnaBridge 172:65be27845400 430 enum _mcg_status
AnnaBridge 172:65be27845400 431 {
AnnaBridge 172:65be27845400 432 kStatus_MCG_ModeUnreachable = MAKE_STATUS(kStatusGroup_MCG, 0), /*!< Can't switch to target mode. */
AnnaBridge 172:65be27845400 433 kStatus_MCG_ModeInvalid = MAKE_STATUS(kStatusGroup_MCG, 1), /*!< Current mode invalid for the specific
AnnaBridge 172:65be27845400 434 function. */
AnnaBridge 172:65be27845400 435 kStatus_MCG_AtmBusClockInvalid = MAKE_STATUS(kStatusGroup_MCG, 2), /*!< Invalid bus clock for ATM. */
AnnaBridge 172:65be27845400 436 kStatus_MCG_AtmDesiredFreqInvalid = MAKE_STATUS(kStatusGroup_MCG, 3), /*!< Invalid desired frequency for ATM. */
AnnaBridge 172:65be27845400 437 kStatus_MCG_AtmIrcUsed = MAKE_STATUS(kStatusGroup_MCG, 4), /*!< IRC is used when using ATM. */
AnnaBridge 172:65be27845400 438 kStatus_MCG_AtmHardwareFail = MAKE_STATUS(kStatusGroup_MCG, 5), /*!< Hardware fail occurs during ATM. */
AnnaBridge 172:65be27845400 439 kStatus_MCG_SourceUsed = MAKE_STATUS(kStatusGroup_MCG, 6) /*!< Can't change the clock source because
AnnaBridge 172:65be27845400 440 it is in use. */
AnnaBridge 172:65be27845400 441 };
AnnaBridge 172:65be27845400 442
AnnaBridge 172:65be27845400 443 /*! @brief MCG status flags. */
AnnaBridge 172:65be27845400 444 enum _mcg_status_flags_t
AnnaBridge 172:65be27845400 445 {
AnnaBridge 172:65be27845400 446 kMCG_RtcOscLostFlag = (1U << 4U), /*!< RTC OSC lost. */
AnnaBridge 172:65be27845400 447 };
AnnaBridge 172:65be27845400 448
AnnaBridge 172:65be27845400 449 /*! @brief MCG internal reference clock (MCGIRCLK) enable mode definition. */
AnnaBridge 172:65be27845400 450 enum _mcg_irclk_enable_mode
AnnaBridge 172:65be27845400 451 {
AnnaBridge 172:65be27845400 452 kMCG_IrclkEnable = MCG_C1_IRCLKEN_MASK, /*!< MCGIRCLK enable. */
AnnaBridge 172:65be27845400 453 kMCG_IrclkEnableInStop = MCG_C1_IREFSTEN_MASK /*!< MCGIRCLK enable in stop mode. */
AnnaBridge 172:65be27845400 454 };
AnnaBridge 172:65be27845400 455
AnnaBridge 172:65be27845400 456 /*! @brief MCG mode definitions */
AnnaBridge 172:65be27845400 457 typedef enum _mcg_mode
AnnaBridge 172:65be27845400 458 {
AnnaBridge 172:65be27845400 459 kMCG_ModeFEI = 0U, /*!< FEI - FLL Engaged Internal */
AnnaBridge 172:65be27845400 460 kMCG_ModeFBI, /*!< FBI - FLL Bypassed Internal */
AnnaBridge 172:65be27845400 461 kMCG_ModeBLPI, /*!< BLPI - Bypassed Low Power Internal */
AnnaBridge 172:65be27845400 462 kMCG_ModeFEE, /*!< FEE - FLL Engaged External */
AnnaBridge 172:65be27845400 463 kMCG_ModeFBE, /*!< FBE - FLL Bypassed External */
AnnaBridge 172:65be27845400 464 kMCG_ModeBLPE, /*!< BLPE - Bypassed Low Power External */
AnnaBridge 172:65be27845400 465 kMCG_ModeError /*!< Unknown mode */
AnnaBridge 172:65be27845400 466 } mcg_mode_t;
AnnaBridge 172:65be27845400 467
AnnaBridge 172:65be27845400 468 /*! @brief MCG mode change configuration structure
AnnaBridge 172:65be27845400 469 *
AnnaBridge 172:65be27845400 470 * When porting to a new board, set the following members
AnnaBridge 172:65be27845400 471 * according to the board setting:
AnnaBridge 172:65be27845400 472 * 1. frdiv: If the FLL uses the external reference clock, set this
AnnaBridge 172:65be27845400 473 * value to ensure that the external reference clock divided by frdiv is
AnnaBridge 172:65be27845400 474 * in the 31.25 kHz to 39.0625 kHz range.
AnnaBridge 172:65be27845400 475 * 2. The PLL reference clock divider PRDIV: PLL reference clock frequency after
AnnaBridge 172:65be27845400 476 * PRDIV should be in the FSL_FEATURE_MCG_PLL_REF_MIN to
AnnaBridge 172:65be27845400 477 * FSL_FEATURE_MCG_PLL_REF_MAX range.
AnnaBridge 172:65be27845400 478 */
AnnaBridge 172:65be27845400 479 typedef struct _mcg_config
AnnaBridge 172:65be27845400 480 {
AnnaBridge 172:65be27845400 481 mcg_mode_t mcgMode; /*!< MCG mode. */
AnnaBridge 172:65be27845400 482
AnnaBridge 172:65be27845400 483 /* ----------------------- MCGIRCCLK settings ------------------------ */
AnnaBridge 172:65be27845400 484 uint8_t irclkEnableMode; /*!< MCGIRCLK enable mode. */
AnnaBridge 172:65be27845400 485 mcg_irc_mode_t ircs; /*!< Source, MCG_C2[IRCS]. */
AnnaBridge 172:65be27845400 486 uint8_t fcrdiv; /*!< Divider, MCG_SC[FCRDIV]. */
AnnaBridge 172:65be27845400 487
AnnaBridge 172:65be27845400 488 /* ------------------------ MCG FLL settings ------------------------- */
AnnaBridge 172:65be27845400 489 uint8_t frdiv; /*!< Divider MCG_C1[FRDIV]. */
AnnaBridge 172:65be27845400 490 mcg_drs_t drs; /*!< DCO range MCG_C4[DRST_DRS]. */
AnnaBridge 172:65be27845400 491 mcg_dmx32_t dmx32; /*!< MCG_C4[DMX32]. */
AnnaBridge 172:65be27845400 492 mcg_oscsel_t oscsel; /*!< OSC select MCG_C7[OSCSEL]. */
AnnaBridge 172:65be27845400 493
AnnaBridge 172:65be27845400 494 /* ------------------------ MCG PLL settings ------------------------- */
AnnaBridge 172:65be27845400 495 } mcg_config_t;
AnnaBridge 172:65be27845400 496
AnnaBridge 172:65be27845400 497 /*******************************************************************************
AnnaBridge 172:65be27845400 498 * API
AnnaBridge 172:65be27845400 499 ******************************************************************************/
AnnaBridge 172:65be27845400 500
AnnaBridge 172:65be27845400 501 #if defined(__cplusplus)
AnnaBridge 172:65be27845400 502 extern "C" {
AnnaBridge 172:65be27845400 503 #endif /* __cplusplus */
AnnaBridge 172:65be27845400 504
AnnaBridge 172:65be27845400 505 /*!
AnnaBridge 172:65be27845400 506 * @brief Enable the clock for specific IP.
AnnaBridge 172:65be27845400 507 *
AnnaBridge 172:65be27845400 508 * @param name Which clock to enable, see \ref clock_ip_name_t.
AnnaBridge 172:65be27845400 509 */
AnnaBridge 172:65be27845400 510 static inline void CLOCK_EnableClock(clock_ip_name_t name)
AnnaBridge 172:65be27845400 511 {
AnnaBridge 172:65be27845400 512 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name);
AnnaBridge 172:65be27845400 513 (*(volatile uint32_t *)regAddr) |= (1U << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name));
AnnaBridge 172:65be27845400 514 }
AnnaBridge 172:65be27845400 515
AnnaBridge 172:65be27845400 516 /*!
AnnaBridge 172:65be27845400 517 * @brief Disable the clock for specific IP.
AnnaBridge 172:65be27845400 518 *
AnnaBridge 172:65be27845400 519 * @param name Which clock to disable, see \ref clock_ip_name_t.
AnnaBridge 172:65be27845400 520 */
AnnaBridge 172:65be27845400 521 static inline void CLOCK_DisableClock(clock_ip_name_t name)
AnnaBridge 172:65be27845400 522 {
AnnaBridge 172:65be27845400 523 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name);
AnnaBridge 172:65be27845400 524 (*(volatile uint32_t *)regAddr) &= ~(1U << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name));
AnnaBridge 172:65be27845400 525 }
AnnaBridge 172:65be27845400 526
AnnaBridge 172:65be27845400 527 /*!
AnnaBridge 172:65be27845400 528 * @brief Set ERCLK32K source.
AnnaBridge 172:65be27845400 529 *
AnnaBridge 172:65be27845400 530 * @param src The value to set ERCLK32K clock source.
AnnaBridge 172:65be27845400 531 */
AnnaBridge 172:65be27845400 532 static inline void CLOCK_SetEr32kClock(uint32_t src)
AnnaBridge 172:65be27845400 533 {
AnnaBridge 172:65be27845400 534 SIM->SOPT1 = ((SIM->SOPT1 & ~SIM_SOPT1_OSC32KSEL_MASK) | SIM_SOPT1_OSC32KSEL(src));
AnnaBridge 172:65be27845400 535 }
AnnaBridge 172:65be27845400 536
AnnaBridge 172:65be27845400 537 /*!
AnnaBridge 172:65be27845400 538 * @brief Set LPUART clock source.
AnnaBridge 172:65be27845400 539 *
AnnaBridge 172:65be27845400 540 * @param src The value to set LPUART clock source.
AnnaBridge 172:65be27845400 541 */
AnnaBridge 172:65be27845400 542 static inline void CLOCK_SetLpuartClock(uint32_t src)
AnnaBridge 172:65be27845400 543 {
AnnaBridge 172:65be27845400 544 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_LPUART0SRC_MASK) | SIM_SOPT2_LPUART0SRC(src));
AnnaBridge 172:65be27845400 545 }
AnnaBridge 172:65be27845400 546
AnnaBridge 172:65be27845400 547 /*!
AnnaBridge 172:65be27845400 548 * @brief Set TPM clock source.
AnnaBridge 172:65be27845400 549 *
AnnaBridge 172:65be27845400 550 * @param src The value to set TPM clock source.
AnnaBridge 172:65be27845400 551 */
AnnaBridge 172:65be27845400 552 static inline void CLOCK_SetTpmClock(uint32_t src)
AnnaBridge 172:65be27845400 553 {
AnnaBridge 172:65be27845400 554 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_TPMSRC_MASK) | SIM_SOPT2_TPMSRC(src));
AnnaBridge 172:65be27845400 555 }
AnnaBridge 172:65be27845400 556
AnnaBridge 172:65be27845400 557 /*!
AnnaBridge 172:65be27845400 558 * @brief Set CLKOUT source.
AnnaBridge 172:65be27845400 559 *
AnnaBridge 172:65be27845400 560 * @param src The value to set CLKOUT source.
AnnaBridge 172:65be27845400 561 */
AnnaBridge 172:65be27845400 562 static inline void CLOCK_SetClkOutClock(uint32_t src)
AnnaBridge 172:65be27845400 563 {
AnnaBridge 172:65be27845400 564 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_CLKOUTSEL_MASK) | SIM_SOPT2_CLKOUTSEL(src));
AnnaBridge 172:65be27845400 565 }
AnnaBridge 172:65be27845400 566
AnnaBridge 172:65be27845400 567 /*!
AnnaBridge 172:65be27845400 568 * @brief System clock divider
AnnaBridge 172:65be27845400 569 *
AnnaBridge 172:65be27845400 570 * Set the SIM_CLKDIV1[OUTDIV1], SIM_CLKDIV1[OUTDIV4].
AnnaBridge 172:65be27845400 571 *
AnnaBridge 172:65be27845400 572 * @param outdiv1 Clock 1 output divider value.
AnnaBridge 172:65be27845400 573 *
AnnaBridge 172:65be27845400 574 * @param outdiv4 Clock 4 output divider value.
AnnaBridge 172:65be27845400 575 */
AnnaBridge 172:65be27845400 576 static inline void CLOCK_SetOutDiv(uint32_t outdiv1, uint32_t outdiv4)
AnnaBridge 172:65be27845400 577 {
AnnaBridge 172:65be27845400 578 SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(outdiv1) | SIM_CLKDIV1_OUTDIV4(outdiv4);
AnnaBridge 172:65be27845400 579 }
AnnaBridge 172:65be27845400 580
AnnaBridge 172:65be27845400 581 /*!
AnnaBridge 172:65be27845400 582 * @brief Gets the clock frequency for a specific clock name.
AnnaBridge 172:65be27845400 583 *
AnnaBridge 172:65be27845400 584 * This function checks the current clock configurations and then calculates
AnnaBridge 172:65be27845400 585 * the clock frequency for a specific clock name defined in clock_name_t.
AnnaBridge 172:65be27845400 586 * The MCG must be properly configured before using this function.
AnnaBridge 172:65be27845400 587 *
AnnaBridge 172:65be27845400 588 * @param clockName Clock names defined in clock_name_t
AnnaBridge 172:65be27845400 589 * @return Clock frequency value in Hertz
AnnaBridge 172:65be27845400 590 */
AnnaBridge 172:65be27845400 591 uint32_t CLOCK_GetFreq(clock_name_t clockName);
AnnaBridge 172:65be27845400 592
AnnaBridge 172:65be27845400 593 /*!
AnnaBridge 172:65be27845400 594 * @brief Get the core clock or system clock frequency.
AnnaBridge 172:65be27845400 595 *
AnnaBridge 172:65be27845400 596 * @return Clock frequency in Hz.
AnnaBridge 172:65be27845400 597 */
AnnaBridge 172:65be27845400 598 uint32_t CLOCK_GetCoreSysClkFreq(void);
AnnaBridge 172:65be27845400 599
AnnaBridge 172:65be27845400 600 /*!
AnnaBridge 172:65be27845400 601 * @brief Get the platform clock frequency.
AnnaBridge 172:65be27845400 602 *
AnnaBridge 172:65be27845400 603 * @return Clock frequency in Hz.
AnnaBridge 172:65be27845400 604 */
AnnaBridge 172:65be27845400 605 uint32_t CLOCK_GetPlatClkFreq(void);
AnnaBridge 172:65be27845400 606
AnnaBridge 172:65be27845400 607 /*!
AnnaBridge 172:65be27845400 608 * @brief Get the bus clock frequency.
AnnaBridge 172:65be27845400 609 *
AnnaBridge 172:65be27845400 610 * @return Clock frequency in Hz.
AnnaBridge 172:65be27845400 611 */
AnnaBridge 172:65be27845400 612 uint32_t CLOCK_GetBusClkFreq(void);
AnnaBridge 172:65be27845400 613
AnnaBridge 172:65be27845400 614 /*!
AnnaBridge 172:65be27845400 615 * @brief Get the flash clock frequency.
AnnaBridge 172:65be27845400 616 *
AnnaBridge 172:65be27845400 617 * @return Clock frequency in Hz.
AnnaBridge 172:65be27845400 618 */
AnnaBridge 172:65be27845400 619 uint32_t CLOCK_GetFlashClkFreq(void);
AnnaBridge 172:65be27845400 620
AnnaBridge 172:65be27845400 621 /*!
AnnaBridge 172:65be27845400 622 * @brief Get the external reference 32K clock frequency (ERCLK32K).
AnnaBridge 172:65be27845400 623 *
AnnaBridge 172:65be27845400 624 * @return Clock frequency in Hz.
AnnaBridge 172:65be27845400 625 */
AnnaBridge 172:65be27845400 626 uint32_t CLOCK_GetEr32kClkFreq(void);
AnnaBridge 172:65be27845400 627
AnnaBridge 172:65be27845400 628 /*!
AnnaBridge 172:65be27845400 629 * @brief Get the OSC0 external reference clock frequency (OSC0ERCLK).
AnnaBridge 172:65be27845400 630 *
AnnaBridge 172:65be27845400 631 * @return Clock frequency in Hz.
AnnaBridge 172:65be27845400 632 */
AnnaBridge 172:65be27845400 633 uint32_t CLOCK_GetOsc0ErClkFreq(void);
AnnaBridge 172:65be27845400 634
AnnaBridge 172:65be27845400 635 /*!
AnnaBridge 172:65be27845400 636 * @brief Set the clock configure in SIM module.
AnnaBridge 172:65be27845400 637 *
AnnaBridge 172:65be27845400 638 * This function sets system layer clock settings in SIM module.
AnnaBridge 172:65be27845400 639 *
AnnaBridge 172:65be27845400 640 * @param config Pointer to the configure structure.
AnnaBridge 172:65be27845400 641 */
AnnaBridge 172:65be27845400 642 void CLOCK_SetSimConfig(sim_clock_config_t const *config);
AnnaBridge 172:65be27845400 643
AnnaBridge 172:65be27845400 644 /*!
AnnaBridge 172:65be27845400 645 * @brief Set the system clock dividers in SIM to safe value.
AnnaBridge 172:65be27845400 646 *
AnnaBridge 172:65be27845400 647 * The system level clocks (core clock, bus clock, flexbus clock and flash clock)
AnnaBridge 172:65be27845400 648 * must be in allowed ranges. During MCG clock mode switch, the MCG output clock
AnnaBridge 172:65be27845400 649 * changes then the system level clocks may be out of range. This function could
AnnaBridge 172:65be27845400 650 * be used before MCG mode change, to make sure system level clocks are in allowed
AnnaBridge 172:65be27845400 651 * range.
AnnaBridge 172:65be27845400 652 *
AnnaBridge 172:65be27845400 653 * @param config Pointer to the configure structure.
AnnaBridge 172:65be27845400 654 */
AnnaBridge 172:65be27845400 655 static inline void CLOCK_SetSimSafeDivs(void)
AnnaBridge 172:65be27845400 656 {
AnnaBridge 172:65be27845400 657 SIM->CLKDIV1 = 0x00040000U;
AnnaBridge 172:65be27845400 658 }
AnnaBridge 172:65be27845400 659
AnnaBridge 172:65be27845400 660 /*! @name MCG frequency functions. */
AnnaBridge 172:65be27845400 661 /*@{*/
AnnaBridge 172:65be27845400 662
AnnaBridge 172:65be27845400 663 /*!
AnnaBridge 172:65be27845400 664 * @brief Gets the MCG output clock (MCGOUTCLK) frequency.
AnnaBridge 172:65be27845400 665 *
AnnaBridge 172:65be27845400 666 * This function gets the MCG output clock frequency in Hz based on the current MCG
AnnaBridge 172:65be27845400 667 * register value.
AnnaBridge 172:65be27845400 668 *
AnnaBridge 172:65be27845400 669 * @return The frequency of MCGOUTCLK.
AnnaBridge 172:65be27845400 670 */
AnnaBridge 172:65be27845400 671 uint32_t CLOCK_GetOutClkFreq(void);
AnnaBridge 172:65be27845400 672
AnnaBridge 172:65be27845400 673 /*!
AnnaBridge 172:65be27845400 674 * @brief Gets the MCG FLL clock (MCGFLLCLK) frequency.
AnnaBridge 172:65be27845400 675 *
AnnaBridge 172:65be27845400 676 * This function gets the MCG FLL clock frequency in Hz based on the current MCG
AnnaBridge 172:65be27845400 677 * register value. The FLL is enabled in FEI/FBI/FEE/FBE mode and
AnnaBridge 172:65be27845400 678 * disabled in low power state in other modes.
AnnaBridge 172:65be27845400 679 *
AnnaBridge 172:65be27845400 680 * @return The frequency of MCGFLLCLK.
AnnaBridge 172:65be27845400 681 */
AnnaBridge 172:65be27845400 682 uint32_t CLOCK_GetFllFreq(void);
AnnaBridge 172:65be27845400 683
AnnaBridge 172:65be27845400 684 /*!
AnnaBridge 172:65be27845400 685 * @brief Gets the MCG internal reference clock (MCGIRCLK) frequency.
AnnaBridge 172:65be27845400 686 *
AnnaBridge 172:65be27845400 687 * This function gets the MCG internal reference clock frequency in Hz based
AnnaBridge 172:65be27845400 688 * on the current MCG register value.
AnnaBridge 172:65be27845400 689 *
AnnaBridge 172:65be27845400 690 * @return The frequency of MCGIRCLK.
AnnaBridge 172:65be27845400 691 */
AnnaBridge 172:65be27845400 692 uint32_t CLOCK_GetInternalRefClkFreq(void);
AnnaBridge 172:65be27845400 693
AnnaBridge 172:65be27845400 694 /*!
AnnaBridge 172:65be27845400 695 * @brief Gets the MCG fixed frequency clock (MCGFFCLK) frequency.
AnnaBridge 172:65be27845400 696 *
AnnaBridge 172:65be27845400 697 * This function gets the MCG fixed frequency clock frequency in Hz based
AnnaBridge 172:65be27845400 698 * on the current MCG register value.
AnnaBridge 172:65be27845400 699 *
AnnaBridge 172:65be27845400 700 * @return The frequency of MCGFFCLK.
AnnaBridge 172:65be27845400 701 */
AnnaBridge 172:65be27845400 702 uint32_t CLOCK_GetFixedFreqClkFreq(void);
AnnaBridge 172:65be27845400 703
AnnaBridge 172:65be27845400 704 /*@}*/
AnnaBridge 172:65be27845400 705
AnnaBridge 172:65be27845400 706 /*! @name MCG clock configuration. */
AnnaBridge 172:65be27845400 707 /*@{*/
AnnaBridge 172:65be27845400 708
AnnaBridge 172:65be27845400 709 /*!
AnnaBridge 172:65be27845400 710 * @brief Enables or disables the MCG low power.
AnnaBridge 172:65be27845400 711 *
AnnaBridge 172:65be27845400 712 * Enabling the MCG low power disables the PLL and FLL in bypass modes. In other words,
AnnaBridge 172:65be27845400 713 * in FBE and PBE modes, enabling low power sets the MCG to BLPE mode. In FBI and
AnnaBridge 172:65be27845400 714 * PBI modes, enabling low power sets the MCG to BLPI mode.
AnnaBridge 172:65be27845400 715 * When disabling the MCG low power, the PLL or FLL are enabled based on MCG settings.
AnnaBridge 172:65be27845400 716 *
AnnaBridge 172:65be27845400 717 * @param enable True to enable MCG low power, false to disable MCG low power.
AnnaBridge 172:65be27845400 718 */
AnnaBridge 172:65be27845400 719 static inline void CLOCK_SetLowPowerEnable(bool enable)
AnnaBridge 172:65be27845400 720 {
AnnaBridge 172:65be27845400 721 if (enable)
AnnaBridge 172:65be27845400 722 {
AnnaBridge 172:65be27845400 723 MCG->C2 |= MCG_C2_LP_MASK;
AnnaBridge 172:65be27845400 724 }
AnnaBridge 172:65be27845400 725 else
AnnaBridge 172:65be27845400 726 {
AnnaBridge 172:65be27845400 727 MCG->C2 &= ~MCG_C2_LP_MASK;
AnnaBridge 172:65be27845400 728 }
AnnaBridge 172:65be27845400 729 }
AnnaBridge 172:65be27845400 730
AnnaBridge 172:65be27845400 731 /*!
AnnaBridge 172:65be27845400 732 * @brief Configures the Internal Reference clock (MCGIRCLK).
AnnaBridge 172:65be27845400 733 *
AnnaBridge 172:65be27845400 734 * This function sets the \c MCGIRCLK base on parameters. It also selects the IRC
AnnaBridge 172:65be27845400 735 * source. If the fast IRC is used, this function sets the fast IRC divider.
AnnaBridge 172:65be27845400 736 * This function also sets whether the \c MCGIRCLK is enabled in stop mode.
AnnaBridge 172:65be27845400 737 * Calling this function in FBI/PBI/BLPI modes may change the system clock. As a result,
AnnaBridge 172:65be27845400 738 * using the function in these modes it is not allowed.
AnnaBridge 172:65be27845400 739 *
AnnaBridge 172:65be27845400 740 * @param enableMode MCGIRCLK enable mode, OR'ed value of @ref _mcg_irclk_enable_mode.
AnnaBridge 172:65be27845400 741 * @param ircs MCGIRCLK clock source, choose fast or slow.
AnnaBridge 172:65be27845400 742 * @param fcrdiv Fast IRC divider setting (\c FCRDIV).
AnnaBridge 172:65be27845400 743 * @retval kStatus_MCG_SourceUsed Because the internall reference clock is used as a clock source,
AnnaBridge 172:65be27845400 744 * the confuration should not be changed. Otherwise, a glitch occurs.
AnnaBridge 172:65be27845400 745 * @retval kStatus_Success MCGIRCLK configuration finished successfully.
AnnaBridge 172:65be27845400 746 */
AnnaBridge 172:65be27845400 747 status_t CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv);
AnnaBridge 172:65be27845400 748
AnnaBridge 172:65be27845400 749 /*!
AnnaBridge 172:65be27845400 750 * @brief Selects the MCG external reference clock.
AnnaBridge 172:65be27845400 751 *
AnnaBridge 172:65be27845400 752 * Selects the MCG external reference clock source, changes the MCG_C7[OSCSEL],
AnnaBridge 172:65be27845400 753 * and waits for the clock source to be stable. Because the external reference
AnnaBridge 172:65be27845400 754 * clock should not be changed in FEE/FBE/BLPE/PBE/PEE modes, do not call this function in these modes.
AnnaBridge 172:65be27845400 755 *
AnnaBridge 172:65be27845400 756 * @param oscsel MCG external reference clock source, MCG_C7[OSCSEL].
AnnaBridge 172:65be27845400 757 * @retval kStatus_MCG_SourceUsed Because the external reference clock is used as a clock source,
AnnaBridge 172:65be27845400 758 * the confuration should not be changed. Otherwise, a glitch occurs.
AnnaBridge 172:65be27845400 759 * @retval kStatus_Success External reference clock set successfully.
AnnaBridge 172:65be27845400 760 */
AnnaBridge 172:65be27845400 761 status_t CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel);
AnnaBridge 172:65be27845400 762
AnnaBridge 172:65be27845400 763 /*!
AnnaBridge 172:65be27845400 764 * @brief Set the FLL external reference clock divider value.
AnnaBridge 172:65be27845400 765 *
AnnaBridge 172:65be27845400 766 * Sets the FLL external reference clock divider value, the register MCG_C1[FRDIV].
AnnaBridge 172:65be27845400 767 *
AnnaBridge 172:65be27845400 768 * @param frdiv The FLL external reference clock divider value, MCG_C1[FRDIV].
AnnaBridge 172:65be27845400 769 */
AnnaBridge 172:65be27845400 770 static inline void CLOCK_SetFllExtRefDiv(uint8_t frdiv)
AnnaBridge 172:65be27845400 771 {
AnnaBridge 172:65be27845400 772 MCG->C1 = (MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv);
AnnaBridge 172:65be27845400 773 }
AnnaBridge 172:65be27845400 774
AnnaBridge 172:65be27845400 775 /*@}*/
AnnaBridge 172:65be27845400 776
AnnaBridge 172:65be27845400 777 /*! @name MCG clock lock monitor functions. */
AnnaBridge 172:65be27845400 778 /*@{*/
AnnaBridge 172:65be27845400 779
AnnaBridge 172:65be27845400 780 /*!
AnnaBridge 172:65be27845400 781 * @brief Sets the RTC OSC clock monitor mode.
AnnaBridge 172:65be27845400 782 *
AnnaBridge 172:65be27845400 783 * This function sets the RTC OSC clock monitor mode. See @ref mcg_monitor_mode_t for details.
AnnaBridge 172:65be27845400 784 *
AnnaBridge 172:65be27845400 785 * @param mode Monitor mode to set.
AnnaBridge 172:65be27845400 786 */
AnnaBridge 172:65be27845400 787 void CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode);
AnnaBridge 172:65be27845400 788
AnnaBridge 172:65be27845400 789 /*!
AnnaBridge 172:65be27845400 790 * @brief Gets the MCG status flags.
AnnaBridge 172:65be27845400 791 *
AnnaBridge 172:65be27845400 792 * This function gets the MCG clock status flags. All status flags are
AnnaBridge 172:65be27845400 793 * returned as a logical OR of the enumeration @ref _mcg_status_flags_t. To
AnnaBridge 172:65be27845400 794 * check a specific flag, compare the return value with the flag.
AnnaBridge 172:65be27845400 795 *
AnnaBridge 172:65be27845400 796 * Example:
AnnaBridge 172:65be27845400 797 * @code
AnnaBridge 172:65be27845400 798 // To check the clock lost lock status of OSC0 and PLL0.
AnnaBridge 172:65be27845400 799 uint32_t mcgFlags;
AnnaBridge 172:65be27845400 800
AnnaBridge 172:65be27845400 801 mcgFlags = CLOCK_GetStatusFlags();
AnnaBridge 172:65be27845400 802
AnnaBridge 172:65be27845400 803 if (mcgFlags & kMCG_Osc0LostFlag)
AnnaBridge 172:65be27845400 804 {
AnnaBridge 172:65be27845400 805 // OSC0 clock lock lost. Do something.
AnnaBridge 172:65be27845400 806 }
AnnaBridge 172:65be27845400 807 if (mcgFlags & kMCG_Pll0LostFlag)
AnnaBridge 172:65be27845400 808 {
AnnaBridge 172:65be27845400 809 // PLL0 clock lock lost. Do something.
AnnaBridge 172:65be27845400 810 }
AnnaBridge 172:65be27845400 811 @endcode
AnnaBridge 172:65be27845400 812 *
AnnaBridge 172:65be27845400 813 * @return Logical OR value of the @ref _mcg_status_flags_t.
AnnaBridge 172:65be27845400 814 */
AnnaBridge 172:65be27845400 815 uint32_t CLOCK_GetStatusFlags(void);
AnnaBridge 172:65be27845400 816
AnnaBridge 172:65be27845400 817 /*!
AnnaBridge 172:65be27845400 818 * @brief Clears the MCG status flags.
AnnaBridge 172:65be27845400 819 *
AnnaBridge 172:65be27845400 820 * This function clears the MCG clock lock lost status. The parameter is a logical
AnnaBridge 172:65be27845400 821 * OR value of the flags to clear. See @ref _mcg_status_flags_t.
AnnaBridge 172:65be27845400 822 *
AnnaBridge 172:65be27845400 823 * Example:
AnnaBridge 172:65be27845400 824 * @code
AnnaBridge 172:65be27845400 825 // To clear the clock lost lock status flags of OSC0 and PLL0.
AnnaBridge 172:65be27845400 826
AnnaBridge 172:65be27845400 827 CLOCK_ClearStatusFlags(kMCG_Osc0LostFlag | kMCG_Pll0LostFlag);
AnnaBridge 172:65be27845400 828 @endcode
AnnaBridge 172:65be27845400 829 *
AnnaBridge 172:65be27845400 830 * @param mask The status flags to clear. This is a logical OR of members of the
AnnaBridge 172:65be27845400 831 * enumeration @ref _mcg_status_flags_t.
AnnaBridge 172:65be27845400 832 */
AnnaBridge 172:65be27845400 833 void CLOCK_ClearStatusFlags(uint32_t mask);
AnnaBridge 172:65be27845400 834
AnnaBridge 172:65be27845400 835 /*@}*/
AnnaBridge 172:65be27845400 836
AnnaBridge 172:65be27845400 837 /*!
AnnaBridge 172:65be27845400 838 * @name OSC configuration
AnnaBridge 172:65be27845400 839 * @{
AnnaBridge 172:65be27845400 840 */
AnnaBridge 172:65be27845400 841
AnnaBridge 172:65be27845400 842 /*!
AnnaBridge 172:65be27845400 843 * @brief Initializes the OSC0.
AnnaBridge 172:65be27845400 844 *
AnnaBridge 172:65be27845400 845 * This function initializes the OSC0 according to the board configuration.
AnnaBridge 172:65be27845400 846 *
AnnaBridge 172:65be27845400 847 * @param config Pointer to the OSC0 configuration structure.
AnnaBridge 172:65be27845400 848 */
AnnaBridge 172:65be27845400 849 void CLOCK_InitOsc0(osc_config_t const *config);
AnnaBridge 172:65be27845400 850
AnnaBridge 172:65be27845400 851 /*!
AnnaBridge 172:65be27845400 852 * @brief Deinitializes the OSC0.
AnnaBridge 172:65be27845400 853 *
AnnaBridge 172:65be27845400 854 * This function deinitializes the OSC0.
AnnaBridge 172:65be27845400 855 */
AnnaBridge 172:65be27845400 856 void CLOCK_DeinitOsc0(void);
AnnaBridge 172:65be27845400 857
AnnaBridge 172:65be27845400 858 /* @} */
AnnaBridge 172:65be27845400 859
AnnaBridge 172:65be27845400 860 /*!
AnnaBridge 172:65be27845400 861 * @name External clock frequency
AnnaBridge 172:65be27845400 862 * @{
AnnaBridge 172:65be27845400 863 */
AnnaBridge 172:65be27845400 864
AnnaBridge 172:65be27845400 865 /*!
AnnaBridge 172:65be27845400 866 * @brief Sets the XTAL0 frequency based on board settings.
AnnaBridge 172:65be27845400 867 *
AnnaBridge 172:65be27845400 868 * @param freq The XTAL0/EXTAL0 input clock frequency in Hz.
AnnaBridge 172:65be27845400 869 */
AnnaBridge 172:65be27845400 870 static inline void CLOCK_SetXtal0Freq(uint32_t freq)
AnnaBridge 172:65be27845400 871 {
AnnaBridge 172:65be27845400 872 g_xtal0Freq = freq;
AnnaBridge 172:65be27845400 873 }
AnnaBridge 172:65be27845400 874
AnnaBridge 172:65be27845400 875 /*!
AnnaBridge 172:65be27845400 876 * @brief Sets the XTAL32/RTC_CLKIN frequency based on board settings.
AnnaBridge 172:65be27845400 877 *
AnnaBridge 172:65be27845400 878 * @param freq The XTAL32/EXTAL32/RTC_CLKIN input clock frequency in Hz.
AnnaBridge 172:65be27845400 879 */
AnnaBridge 172:65be27845400 880 static inline void CLOCK_SetXtal32Freq(uint32_t freq)
AnnaBridge 172:65be27845400 881 {
AnnaBridge 172:65be27845400 882 g_xtal32Freq = freq;
AnnaBridge 172:65be27845400 883 }
AnnaBridge 172:65be27845400 884 /* @} */
AnnaBridge 172:65be27845400 885
AnnaBridge 172:65be27845400 886 /*!
AnnaBridge 172:65be27845400 887 * @name MCG auto-trim machine.
AnnaBridge 172:65be27845400 888 * @{
AnnaBridge 172:65be27845400 889 */
AnnaBridge 172:65be27845400 890
AnnaBridge 172:65be27845400 891 /*!
AnnaBridge 172:65be27845400 892 * @brief Auto trims the internal reference clock.
AnnaBridge 172:65be27845400 893 *
AnnaBridge 172:65be27845400 894 * This function trims the internal reference clock by using the external clock. If
AnnaBridge 172:65be27845400 895 * successful, it returns the kStatus_Success and the frequency after
AnnaBridge 172:65be27845400 896 * trimming is received in the parameter @p actualFreq. If an error occurs,
AnnaBridge 172:65be27845400 897 * the error code is returned.
AnnaBridge 172:65be27845400 898 *
AnnaBridge 172:65be27845400 899 * @param extFreq External clock frequency, which should be a bus clock.
AnnaBridge 172:65be27845400 900 * @param desireFreq Frequency to trim to.
AnnaBridge 172:65be27845400 901 * @param actualFreq Actual frequency after trimming.
AnnaBridge 172:65be27845400 902 * @param atms Trim fast or slow internal reference clock.
AnnaBridge 172:65be27845400 903 * @retval kStatus_Success ATM success.
AnnaBridge 172:65be27845400 904 * @retval kStatus_MCG_AtmBusClockInvalid The bus clock is not in allowed range for the ATM.
AnnaBridge 172:65be27845400 905 * @retval kStatus_MCG_AtmDesiredFreqInvalid MCGIRCLK could not be trimmed to the desired frequency.
AnnaBridge 172:65be27845400 906 * @retval kStatus_MCG_AtmIrcUsed Could not trim because MCGIRCLK is used as a bus clock source.
AnnaBridge 172:65be27845400 907 * @retval kStatus_MCG_AtmHardwareFail Hardware fails while trimming.
AnnaBridge 172:65be27845400 908 */
AnnaBridge 172:65be27845400 909 status_t CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms);
AnnaBridge 172:65be27845400 910 /* @} */
AnnaBridge 172:65be27845400 911
AnnaBridge 172:65be27845400 912 /*! @name MCG mode functions. */
AnnaBridge 172:65be27845400 913 /*@{*/
AnnaBridge 172:65be27845400 914
AnnaBridge 172:65be27845400 915 /*!
AnnaBridge 172:65be27845400 916 * @brief Gets the current MCG mode.
AnnaBridge 172:65be27845400 917 *
AnnaBridge 172:65be27845400 918 * This function checks the MCG registers and determines the current MCG mode.
AnnaBridge 172:65be27845400 919 *
AnnaBridge 172:65be27845400 920 * @return Current MCG mode or error code; See @ref mcg_mode_t.
AnnaBridge 172:65be27845400 921 */
AnnaBridge 172:65be27845400 922 mcg_mode_t CLOCK_GetMode(void);
AnnaBridge 172:65be27845400 923
AnnaBridge 172:65be27845400 924 /*!
AnnaBridge 172:65be27845400 925 * @brief Sets the MCG to FEI mode.
AnnaBridge 172:65be27845400 926 *
AnnaBridge 172:65be27845400 927 * This function sets the MCG to FEI mode. If setting to FEI mode fails
AnnaBridge 172:65be27845400 928 * from the current mode, this function returns an error.
AnnaBridge 172:65be27845400 929 *
AnnaBridge 172:65be27845400 930 * @param dmx32 DMX32 in FEI mode.
AnnaBridge 172:65be27845400 931 * @param drs The DCO range selection.
AnnaBridge 172:65be27845400 932 * @param fllStableDelay Delay function to ensure that the FLL is stable. Passing
AnnaBridge 172:65be27845400 933 * NULL does not cause a delay.
AnnaBridge 172:65be27845400 934 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
AnnaBridge 172:65be27845400 935 * @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge 172:65be27845400 936 * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
AnnaBridge 172:65be27845400 937 * to a frequency above 32768 Hz.
AnnaBridge 172:65be27845400 938 */
AnnaBridge 172:65be27845400 939 status_t CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
AnnaBridge 172:65be27845400 940
AnnaBridge 172:65be27845400 941 /*!
AnnaBridge 172:65be27845400 942 * @brief Sets the MCG to FEE mode.
AnnaBridge 172:65be27845400 943 *
AnnaBridge 172:65be27845400 944 * This function sets the MCG to FEE mode. If setting to FEE mode fails
AnnaBridge 172:65be27845400 945 * from the current mode, this function returns an error.
AnnaBridge 172:65be27845400 946 *
AnnaBridge 172:65be27845400 947 * @param frdiv FLL reference clock divider setting, FRDIV.
AnnaBridge 172:65be27845400 948 * @param dmx32 DMX32 in FEE mode.
AnnaBridge 172:65be27845400 949 * @param drs The DCO range selection.
AnnaBridge 172:65be27845400 950 * @param fllStableDelay Delay function to make sure FLL is stable. Passing
AnnaBridge 172:65be27845400 951 * NULL does not cause a delay.
AnnaBridge 172:65be27845400 952 *
AnnaBridge 172:65be27845400 953 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
AnnaBridge 172:65be27845400 954 * @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge 172:65be27845400 955 */
AnnaBridge 172:65be27845400 956 status_t CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
AnnaBridge 172:65be27845400 957
AnnaBridge 172:65be27845400 958 /*!
AnnaBridge 172:65be27845400 959 * @brief Sets the MCG to FBI mode.
AnnaBridge 172:65be27845400 960 *
AnnaBridge 172:65be27845400 961 * This function sets the MCG to FBI mode. If setting to FBI mode fails
AnnaBridge 172:65be27845400 962 * from the current mode, this function returns an error.
AnnaBridge 172:65be27845400 963 *
AnnaBridge 172:65be27845400 964 * @param dmx32 DMX32 in FBI mode.
AnnaBridge 172:65be27845400 965 * @param drs The DCO range selection.
AnnaBridge 172:65be27845400 966 * @param fllStableDelay Delay function to make sure FLL is stable. If the FLL
AnnaBridge 172:65be27845400 967 * is not used in FBI mode, this parameter can be NULL. Passing
AnnaBridge 172:65be27845400 968 * NULL does not cause a delay.
AnnaBridge 172:65be27845400 969 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
AnnaBridge 172:65be27845400 970 * @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge 172:65be27845400 971 * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
AnnaBridge 172:65be27845400 972 * to frequency above 32768 Hz.
AnnaBridge 172:65be27845400 973 */
AnnaBridge 172:65be27845400 974 status_t CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
AnnaBridge 172:65be27845400 975
AnnaBridge 172:65be27845400 976 /*!
AnnaBridge 172:65be27845400 977 * @brief Sets the MCG to FBE mode.
AnnaBridge 172:65be27845400 978 *
AnnaBridge 172:65be27845400 979 * This function sets the MCG to FBE mode. If setting to FBE mode fails
AnnaBridge 172:65be27845400 980 * from the current mode, this function returns an error.
AnnaBridge 172:65be27845400 981 *
AnnaBridge 172:65be27845400 982 * @param frdiv FLL reference clock divider setting, FRDIV.
AnnaBridge 172:65be27845400 983 * @param dmx32 DMX32 in FBE mode.
AnnaBridge 172:65be27845400 984 * @param drs The DCO range selection.
AnnaBridge 172:65be27845400 985 * @param fllStableDelay Delay function to make sure FLL is stable. If the FLL
AnnaBridge 172:65be27845400 986 * is not used in FBE mode, this parameter can be NULL. Passing NULL
AnnaBridge 172:65be27845400 987 * does not cause a delay.
AnnaBridge 172:65be27845400 988 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
AnnaBridge 172:65be27845400 989 * @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge 172:65be27845400 990 */
AnnaBridge 172:65be27845400 991 status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
AnnaBridge 172:65be27845400 992
AnnaBridge 172:65be27845400 993 /*!
AnnaBridge 172:65be27845400 994 * @brief Sets the MCG to BLPI mode.
AnnaBridge 172:65be27845400 995 *
AnnaBridge 172:65be27845400 996 * This function sets the MCG to BLPI mode. If setting to BLPI mode fails
AnnaBridge 172:65be27845400 997 * from the current mode, this function returns an error.
AnnaBridge 172:65be27845400 998 *
AnnaBridge 172:65be27845400 999 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
AnnaBridge 172:65be27845400 1000 * @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge 172:65be27845400 1001 */
AnnaBridge 172:65be27845400 1002 status_t CLOCK_SetBlpiMode(void);
AnnaBridge 172:65be27845400 1003
AnnaBridge 172:65be27845400 1004 /*!
AnnaBridge 172:65be27845400 1005 * @brief Sets the MCG to BLPE mode.
AnnaBridge 172:65be27845400 1006 *
AnnaBridge 172:65be27845400 1007 * This function sets the MCG to BLPE mode. If setting to BLPE mode fails
AnnaBridge 172:65be27845400 1008 * from the current mode, this function returns an error.
AnnaBridge 172:65be27845400 1009 *
AnnaBridge 172:65be27845400 1010 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
AnnaBridge 172:65be27845400 1011 * @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge 172:65be27845400 1012 */
AnnaBridge 172:65be27845400 1013 status_t CLOCK_SetBlpeMode(void);
AnnaBridge 172:65be27845400 1014
AnnaBridge 172:65be27845400 1015 /*!
AnnaBridge 172:65be27845400 1016 * @brief Switches the MCG to FBE mode from the external mode.
AnnaBridge 172:65be27845400 1017 *
AnnaBridge 172:65be27845400 1018 * This function switches the MCG from external modes (PEE/PBE/BLPE/FEE) to the FBE mode quickly.
AnnaBridge 172:65be27845400 1019 * The external clock is used as the system clock souce and PLL is disabled. However,
AnnaBridge 172:65be27845400 1020 * the FLL settings are not configured. This is a lite function with a small code size, which is useful
AnnaBridge 172:65be27845400 1021 * during the mode switch. For example, to switch from PEE mode to FEI mode:
AnnaBridge 172:65be27845400 1022 *
AnnaBridge 172:65be27845400 1023 * @code
AnnaBridge 172:65be27845400 1024 * CLOCK_ExternalModeToFbeModeQuick();
AnnaBridge 172:65be27845400 1025 * CLOCK_SetFeiMode(...);
AnnaBridge 172:65be27845400 1026 * @endcode
AnnaBridge 172:65be27845400 1027 *
AnnaBridge 172:65be27845400 1028 * @retval kStatus_Success Switched successfully.
AnnaBridge 172:65be27845400 1029 * @retval kStatus_MCG_ModeInvalid If the current mode is not an external mode, do not call this function.
AnnaBridge 172:65be27845400 1030 */
AnnaBridge 172:65be27845400 1031 status_t CLOCK_ExternalModeToFbeModeQuick(void);
AnnaBridge 172:65be27845400 1032
AnnaBridge 172:65be27845400 1033 /*!
AnnaBridge 172:65be27845400 1034 * @brief Switches the MCG to FBI mode from internal modes.
AnnaBridge 172:65be27845400 1035 *
AnnaBridge 172:65be27845400 1036 * This function switches the MCG from internal modes (PEI/PBI/BLPI/FEI) to the FBI mode quickly.
AnnaBridge 172:65be27845400 1037 * The MCGIRCLK is used as the system clock souce and PLL is disabled. However,
AnnaBridge 172:65be27845400 1038 * FLL settings are not configured. This is a lite function with a small code size, which is useful
AnnaBridge 172:65be27845400 1039 * during the mode switch. For example, to switch from PEI mode to FEE mode:
AnnaBridge 172:65be27845400 1040 *
AnnaBridge 172:65be27845400 1041 * @code
AnnaBridge 172:65be27845400 1042 * CLOCK_InternalModeToFbiModeQuick();
AnnaBridge 172:65be27845400 1043 * CLOCK_SetFeeMode(...);
AnnaBridge 172:65be27845400 1044 * @endcode
AnnaBridge 172:65be27845400 1045 *
AnnaBridge 172:65be27845400 1046 * @retval kStatus_Success Switched successfully.
AnnaBridge 172:65be27845400 1047 * @retval kStatus_MCG_ModeInvalid If the current mode is not an internal mode, do not call this function.
AnnaBridge 172:65be27845400 1048 */
AnnaBridge 172:65be27845400 1049 status_t CLOCK_InternalModeToFbiModeQuick(void);
AnnaBridge 172:65be27845400 1050
AnnaBridge 172:65be27845400 1051 /*!
AnnaBridge 172:65be27845400 1052 * @brief Sets the MCG to FEI mode during system boot up.
AnnaBridge 172:65be27845400 1053 *
AnnaBridge 172:65be27845400 1054 * This function sets the MCG to FEI mode from the reset mode. It can also be used to
AnnaBridge 172:65be27845400 1055 * set up MCG during system boot up.
AnnaBridge 172:65be27845400 1056 *
AnnaBridge 172:65be27845400 1057 * @param dmx32 DMX32 in FEI mode.
AnnaBridge 172:65be27845400 1058 * @param drs The DCO range selection.
AnnaBridge 172:65be27845400 1059 * @param fllStableDelay Delay function to ensure that the FLL is stable.
AnnaBridge 172:65be27845400 1060 *
AnnaBridge 172:65be27845400 1061 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
AnnaBridge 172:65be27845400 1062 * @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge 172:65be27845400 1063 * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
AnnaBridge 172:65be27845400 1064 * to frequency above 32768 Hz.
AnnaBridge 172:65be27845400 1065 */
AnnaBridge 172:65be27845400 1066 status_t CLOCK_BootToFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
AnnaBridge 172:65be27845400 1067
AnnaBridge 172:65be27845400 1068 /*!
AnnaBridge 172:65be27845400 1069 * @brief Sets the MCG to FEE mode during system bootup.
AnnaBridge 172:65be27845400 1070 *
AnnaBridge 172:65be27845400 1071 * This function sets MCG to FEE mode from the reset mode. It can also be used to
AnnaBridge 172:65be27845400 1072 * set up the MCG during system boot up.
AnnaBridge 172:65be27845400 1073 *
AnnaBridge 172:65be27845400 1074 * @param oscsel OSC clock select, OSCSEL.
AnnaBridge 172:65be27845400 1075 * @param frdiv FLL reference clock divider setting, FRDIV.
AnnaBridge 172:65be27845400 1076 * @param dmx32 DMX32 in FEE mode.
AnnaBridge 172:65be27845400 1077 * @param drs The DCO range selection.
AnnaBridge 172:65be27845400 1078 * @param fllStableDelay Delay function to ensure that the FLL is stable.
AnnaBridge 172:65be27845400 1079 *
AnnaBridge 172:65be27845400 1080 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
AnnaBridge 172:65be27845400 1081 * @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge 172:65be27845400 1082 */
AnnaBridge 172:65be27845400 1083 status_t CLOCK_BootToFeeMode(
AnnaBridge 172:65be27845400 1084 mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
AnnaBridge 172:65be27845400 1085
AnnaBridge 172:65be27845400 1086 /*!
AnnaBridge 172:65be27845400 1087 * @brief Sets the MCG to BLPI mode during system boot up.
AnnaBridge 172:65be27845400 1088 *
AnnaBridge 172:65be27845400 1089 * This function sets the MCG to BLPI mode from the reset mode. It can also be used to
AnnaBridge 172:65be27845400 1090 * set up the MCG during sytem boot up.
AnnaBridge 172:65be27845400 1091 *
AnnaBridge 172:65be27845400 1092 * @param fcrdiv Fast IRC divider, FCRDIV.
AnnaBridge 172:65be27845400 1093 * @param ircs The internal reference clock to select, IRCS.
AnnaBridge 172:65be27845400 1094 * @param ircEnableMode The MCGIRCLK enable mode, OR'ed value of @ref _mcg_irclk_enable_mode.
AnnaBridge 172:65be27845400 1095 *
AnnaBridge 172:65be27845400 1096 * @retval kStatus_MCG_SourceUsed Could not change MCGIRCLK setting.
AnnaBridge 172:65be27845400 1097 * @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge 172:65be27845400 1098 */
AnnaBridge 172:65be27845400 1099 status_t CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode);
AnnaBridge 172:65be27845400 1100
AnnaBridge 172:65be27845400 1101 /*!
AnnaBridge 172:65be27845400 1102 * @brief Sets the MCG to BLPE mode during sytem boot up.
AnnaBridge 172:65be27845400 1103 *
AnnaBridge 172:65be27845400 1104 * This function sets the MCG to BLPE mode from the reset mode. It can also be used to
AnnaBridge 172:65be27845400 1105 * set up the MCG during sytem boot up.
AnnaBridge 172:65be27845400 1106 *
AnnaBridge 172:65be27845400 1107 * @param oscsel OSC clock select, MCG_C7[OSCSEL].
AnnaBridge 172:65be27845400 1108 *
AnnaBridge 172:65be27845400 1109 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
AnnaBridge 172:65be27845400 1110 * @retval kStatus_Success Switched to the target mode successfully.
AnnaBridge 172:65be27845400 1111 */
AnnaBridge 172:65be27845400 1112 status_t CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel);
AnnaBridge 172:65be27845400 1113
AnnaBridge 172:65be27845400 1114 /*!
AnnaBridge 172:65be27845400 1115 * @brief Sets the MCG to a target mode.
AnnaBridge 172:65be27845400 1116 *
AnnaBridge 172:65be27845400 1117 * This function sets MCG to a target mode defined by the configuration
AnnaBridge 172:65be27845400 1118 * structure. If switching to the target mode fails, this function
AnnaBridge 172:65be27845400 1119 * chooses the correct path.
AnnaBridge 172:65be27845400 1120 *
AnnaBridge 172:65be27845400 1121 * @param config Pointer to the target MCG mode configuration structure.
AnnaBridge 172:65be27845400 1122 * @return Return kStatus_Success if switched successfully; Otherwise, it returns an error code #_mcg_status.
AnnaBridge 172:65be27845400 1123 *
AnnaBridge 172:65be27845400 1124 * @note If the external clock is used in the target mode, ensure that it is
AnnaBridge 172:65be27845400 1125 * enabled. For example, if the OSC0 is used, set up OSC0 correctly before calling this
AnnaBridge 172:65be27845400 1126 * function.
AnnaBridge 172:65be27845400 1127 */
AnnaBridge 172:65be27845400 1128 status_t CLOCK_SetMcgConfig(mcg_config_t const *config);
AnnaBridge 172:65be27845400 1129
AnnaBridge 172:65be27845400 1130 /*@}*/
AnnaBridge 172:65be27845400 1131
AnnaBridge 172:65be27845400 1132 #if defined(__cplusplus)
AnnaBridge 172:65be27845400 1133 }
AnnaBridge 172:65be27845400 1134 #endif /* __cplusplus */
AnnaBridge 172:65be27845400 1135
AnnaBridge 172:65be27845400 1136 /*! @} */
AnnaBridge 172:65be27845400 1137
AnnaBridge 172:65be27845400 1138 #endif /* _FSL_CLOCK_H_ */